PCA9561

General description

The PCA9561 is a 20-pin CMOS device consisting of four 6-bit non-volatile EEPROM registers, 6 hardware pin inputs and a 6-bit multiplexed output. It is used for DIP switch-free or jumper-less system configuration and supports Mobile and Desktop VID Configuration, where 5 preset values (4 sets of internal non-volatile registers and 1 set of external hardware pins) set processor voltage for operation in various performance or battery conservation sleep modes. The PCA9561 is also useful in server and telecom/networking applications when used to replace DIP switches or jumpers, since the settings can be easily changed via I²C/SMBus without having to power down the equipment to open the cabinet. The non-volatile memory retains the most current setting selected before the power is turned off.

The PCA9561 typically resides between the CPU and Voltage Regulator Module (VRM) when used for CPU VID (Voltage IDentification code) configuration. It is used to bypass the CPU-defined VID values and provide a different set of VID values to the VRM, if an increase in the CPU voltage is desired. An increase in CPU voltage combined with an increase in CPU frequency leads to a performance boost of up to 7.5 pct. Lower CPU voltage reduces power consumption. The main advantage of the PCA9561 over older devices, such as the PCA9559 or PCA9560, is that it contains four internal non-volatile EEPROM registers instead of just one or two, allowing five independent settings which allows a more accurate CPU voltage tuning depending on specific applications.

The PCA9561 has 2 address pins, allowing up to 4 devices to be placed on the same I²C-bus or SMBus.

Features

• Selection of non-volatile register_n as source to MUX_OUT pins via I²C-bus
• I²C-bus can override MUX_SELECT pin in selecting output source
• 6-bit 5-to-1 multiplexer DIP switch
• 4 internal non-volatile registers
• Internal non-volatile registers programmable and readable via I²C-bus
• 6 open drain multiplexed outputs
• 400 kHz maximum clock frequency
• Operating supply voltage 3.0 V to 3.6 V
• 5 V and 2.5 V tolerant inputs/outputs
• Useful for Speed Step® configuration of laptop
• 2 address pins, allowing up to 4 devices on the I²C-bus
• MUX_IN values readable via I²C-bus
• ESD protection exceeds 200 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101
• Latch-up testing is done to JESDEC Standard JESD78 which exceeds 100 mA.

Products/packages

Quality/reliability/chemical content

Quality and reliability disclaimer

Pricing/ordering/availability

Applications

Related applications
Intelligent washing machine

Block diagrams/pinning

Design support

Application Notes

AN10146; I2C 2002-1A Evaluation Board (2003-02-26)

AN10216; I2C manual (2003-03-27)

AN10441; Level shifting techniques in I2C-bus design (2007-06-20)

AN250; PCA8550 4-bit multiplexed/1-bit latched 5-bit I2C EEPROM (1998-10-01)

Support Documents

design_con_2003_tecforum_i2c_bus_overview; DesignCon 2003 TecForum I 2 C Bus Overview (2003-01-27)

UM10206; I2C Demonstration Board 2005-1 Quick Start Guide (2006-06-13)

39340011; I2C-bus specification (version 2.1) (2000-01-01)

UM10204; I2C-bus specification and user manual (2007-06-26)

web; IBIS and HSPICE Model ()

75016531; NXP I2C 2002-1A evaluation board kits OM6285 and OM6278 (2008-07-01)

Parametrics/similar products

Similar products
PCA9561 links to the similar products page containing an overview of products that are similar in function or related to the type number(s) as listed on this page. The similar products page includes products from the same catalog tree(s), relevant selection guides and products from the same functional category.

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Disclaimers

• General product disclaimer
• Quality and reliability disclaimer