PCA9600

General description

The PCA9600 is designed to isolate I²C-bus capacitance, allowing long buses to be driven in point-to-point or multipoint applications of up to 4000 pF. The PCA9600 is a higher-speed version of the P82B96. It creates a non-latching, bidirectional, logic interface between a normal I²C-bus and a range of other higher capacitance or different voltage bus configurations. It can operate at speeds up to at least 1 MHz, and the high drive side is compatible with the Fast-mode Plus (Fm+) specifications.

The PCA9600 features temperature-stabilized logic voltage levels at its SX/SY interface making it suitable for interfacing with buses that have non I²C-bus-compliant logic levels such as SMBus, PMBus, or with microprocessors that use those same TTL logic levels.

The separation of the bidirectional I²C-bus signals into unidirectional TX and RX signals enables the SDA and SCL signals to be transmitted via balanced transmission lines (twisted pairs), or with galvanic isolation using opto or magnetic coupling. The TX and RX signals may be connected together to provide a normal bidirectional signal.

Features

• Bidirectional data transfer of I²C-bus signals
• Isolates capacitance allowing 400 pF on SX/SY side and 4000 pF on TX/TY side
• TX/TY outputs have 60 mA sink capability for driving low-impedance or high-capacitive buses
• 1 MHz operation on up to 20 meters of wire (see AN10658)
• Supply voltage range of 2.5 V to 15 V with I²C-bus logic levels on SX/SY side independent of supply voltage
• Splits I²C-bus signal into pairs of forward/reverse TX/RX, TY/RY signals for interface with opto-electrical isolators and similar devices that need unidirectional input and output signal paths
• Low power supply current
• ESD protection exceeds 4500 V HBM per JESD22-A114, 450 V MM per JESD22-A115, and 1400 V CDM per JESD22-C101
• Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
• Packages offered: SO8 and TSSOP8 (MSOP8)

Products/packages

Pricing/ordering/availability

Applications

• Interface between I²C-buses operating at different logic levels (for example, 5 V and 3 V or 15 V)
• Interface between I²C-bus and SMBus (350 uA) standard or Fm+ standard
• Simple conversion of I²C-bus SDA or SCL signals to multi-drop differential bus hardware, for example, via compatible PCA82C250
• Interfaces with opto-couplers to provide opto-isolation between I²C-bus nodes up to 1 MHz
• Long distance point-to-point or multipoint architectures

Block diagrams/pinning

Design support

Application Notes

AN10710_1; Features and applications of the P82B715 I2C-bus extender (2008-05-28)

AN255_2; I2C / SMBus Repeaters, Hubs and Expanders (2002-12-19)

AN255_2; I2C / SMBus Repeaters, Hubs and Expanders (2002-12-19)

AN10441_1; Level shifting techniques in I2C-bus design (2007-06-20)

AN10658_1; Sending I2C-bus signals via long communications cables (2008-02-28)

Support Documents

UM10206_1; I2C Demonstration Board 2005-1 Quick Start Guide (2006-06-13)

UM10204_3; I2C-bus specification and user manual (2007-06-26)

web; IBIS and HSPICE Model ()

75016532; NXP 2-channel I (2008-07-01)

75016527; NXP I (2008-05-01)

UM10323_1; PCA9600 demonstration board OM6293 (2008-12-15)

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