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General description

Zero delay buffer to distribute an SSTL differential clock input pair to 10 SSTL_2 differential output pairs. Outputs are slope controlled. External feedback pin for synchronization of the outputs to the input. A CMOS style Enable/Disable pin is provided for low power disable.

Features

    • Optimized for clock distribution in DDR (Double Data Rate) SDRAM applications
    • 1-to-10 differential clock distribution
    • Very low skew (< 100 ps) and jitter (< 100 ps)
    • 3 V AVCC and 2.5 V VCC
    • SSTL_2 interface clock inputs and outputs
    • CMOS control signal input
    • Test mode enables buffers while disabling PLL
    • Low current power-down mode
  • Tolerant of Spread Spectrum input clock
  • Full DDR solution provided when used with SSTL16857 and CBT3857

Products/packages

Type numberNorth American Type numberOrdering code (12NC)Product statusPackagePackingMarkingChemical contentLeadfree conversion date
PCK857DGGPCK857DG9352 629 00112Volume productionSOT362-1
(TSSOP48)
TubeStandard MarkingPCK857DGG
PCK857DGGPCK857DG-T9352 629 00118Volume productionSOT362-1
(TSSOP48)
Reel Pack, SMD, 13"Standard MarkingPCK857DGG
PCK857DGGPCK857DG9352 629 00512Volume productionSOT362-1
(TSSOP48)
Tube Dry PackStandard MarkingPCK857DGG
week 12, 2005
PCK857DGGPCK857DG-T9352 629 00518Volume productionSOT362-1
(TSSOP48)
Reel Dry Pack, SMD, 13"Standard MarkingPCK857DGG
week 12, 2005

Pricing/ordering/availability

Type numberOrdering code(12NC)Indicative price/unit($)RegionDistributorIn stockInventory dateBuy onlineSamples
PCK857DGG9352 629  00112       not available
PCK857DGG9352 629  00118        Order samples
PCK857DGG9352 629  00512  2.0800     not available
PCK857DGG9352 629  00518  2.0800     not available

Block diagrams/pinning

Technical documents

Support Documents

75014354; Memory interface selection guide Support logic for memory modules and other memory subsystems (2005-06-01)

Parametrics/similar products

Type numberPackageSupply
voltage(V)
ApplicationOther
features
Operating
temp.(Cel)
InputsOutputsOutput frequency range(MHz)Jitter (pk-pk)(ps)Output skew(ps)Phase offset(ps)
PCK857DGGSOT362-1
(TSSOP48)
2.5
3.3
DDR zero-delay clock distribution, DIMMs output enable 0~+85 1 x SSTL-2 11 x SSTL-2 66~167 100 100 150

Similar products

PCK857 links to the similar products page containing an overview of products that are similar in function or related to the type number(s) as listed on this page. The similar products page includes products from the same catalog tree(s), relevant selection guides and products from the same functional category.

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