PCK946

General description

The PCK946 is a low voltage CMOS 1 : 10 clock buffer. The 10 outputs can be configured into a standard fan-out buffer or into 1x and 1/2x combinations. The ten outputs were designed and optimized to drive 50 Ohm series or parallel terminated transmission lines. With output-to-output skews of 350 ps, the PCK946 is ideal as a clock distribution chip for synchronous systems which need a tight level of skew from a large number of outputs.

With an output impedance of approximately 7 Ohm, in both the HIGH and LOW logic states, the output buffers of the PCK946 are ideal for driving series terminated transmission lines. More specifically, each of the 10 PCK946 outputs can drive two series terminated transmission lines. With this capability, the PCK946 has an effective fan-out of 1 : 20 in applications using point-to-point distribution schemes.

The PCK946 has the capability of generating 1x and 1/2x signals from a 1x source. The design is fully static; the signals are generated and re-timed inside the chip to ensure minimal skew between the 1x and 1/2x signals. The device features selectability to allow the user to select the ratio of 1x outputs to 1/2x outputs.

Two independent LVCMOS/LVTTL compatible clock inputs are available. Designers can take advantage of this feature to provide redundant clock sources or the addition of a test clock into the system design. With the TCLK_SEL input pulled HIGH, the TCLK1 input is selected.

All of the control inputs are LVCMOS/LVTTL compatible. The DSELn pins choose between 1x and 1/2x outputs. A LOW on the DSELn pins will select the 1x output. The MR/OE input will reset the internal flip-flops and 3-state the outputs when it is forced HIGH.

The PCK946 is fully 3.3 V compatible. The 32-lead LQFP package was chosen to optimize performance, board space, and cost of the device. The 32-lead LQFP package has a 7 mm x 7 mm body size with a conservative 0.8 mm pin spacing.

Features

• 2 selectable LVCMOS/LVTTL clock inputs
• 350 ps output-to-output skew
• Drives up to 20 series terminated independent clock lines
• Maximum input/output frequency of 150 MHz
• 3-stateable outputs
• 32-lead LQFP packaging
• 3.3 V V_CC supply voltage

Block diagrams/pinning

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