PCKV857

General description

The PCKV857 is a high-performance, low-skew, low-jitter zero delay buffer designed for 2.5 V V_DD and 2.5 V AV_DD operation and differential data input and output levels.

The PCKV857 is a zero delay buffer that distributes a differential clock input pair (CLK, CLK) to ten differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair feedback clock outputs (FB_OUT, FB_OUT) . The clock outputs are controlled by the clock inputs (CLK, CLK), the feedback clocks (FB_IN, FB_IN), and the analog power input (AV_DD). When PWRDWN is high, the outputs switch in phase and frequency with CLK. When PWRDWN is low, all outputs are disabled to high impedance state (3-State), and the PLL is shut down (low power mode). The device also enters the low power mode when the input frequency falls below 20 MHz. An input frequency detection circuit will detect the low frequency condition and after applying a > 20 MHz input signal, the detection circuit turns on the PLL again and enables the outputs.

When AV_DD is grounded, the PLL is turned off and bypassed for test purposes. The PCKV857 is also able to track spread spectrum clocking for reduced EMI.

The PCKV857 is characterized for operation from 0 to +70 Cel.

Features

• ESD classification testing is done to JEDEC Standard JESD22. Protection exceeds 2000 V to HBM per method A114.
• Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
• Optimized for clock distribution in DDR (Double Data Rate) SDRAM applications as per JEDEC specifications
• 1-to-10 differential clock distribution
• Very low skew (< 100 ps) and jitter (< 100 ps)
• Operation from 2.2 V to 2.7 V AV DD and 2.3 V to 2.7 V V_DD
• SSTL_2 interface clock inputs and outputs
• CMOS control signal input
• Test mode enables buffers while disabling PLL
• Low current power-down mode
• Tolerant of Spread Spectrum input clock
• Full DDR solution provided when used with SSTL16877 or SSTV16857
• Designed for DDR 200 and 266 DIMM applications
• Available in TSSOP-48, TVSOP-48, and VFBGA56 (8 no connects) packages

Block diagrams/pinning

Technical documents

Support Documents

75010693; DDR (2002-12-20)

75014354; Memory interface selection guide Support logic for memory modules and other memory subsystems (2005-06-01)

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