PLS100/PLS101

General description

The PLS100 (3-State) and PLS101 (Open Collector) are bipolar, fuse Programmable Logic Arrays (PLAs). Each device utilizes the standard AND/OR/Invert architecture to directly implement custom sum of product equations.

Each device consists of 16 dedicated inputs and 8 dedicated outputs. Each output is capable of being actively controlled by any or all of the 48 product terms. The True, Complement, or Don?t Care condition of each of the 16 inputs and be ANDed together to comprise one P-term. All 48 P-terms can be selectively ORed to each output. The PLS100 and PLS101 are fully TTL compatible, and chip enable control for expansion of input variables and output inhibit. They feature either Open Collector or 3-State outputs for ease of expansion of product terms and application in bus-organized systems.

Order codes are listed in the Ordering Information Table.

Features

• Field-programmable (Ni-Cr link)
• Input variables: 16
• Output functions: 8
• Product terms: 48
• I/O propagation delay: 50ns (max.)
• Power dissipation: 600mW (typ.)
• Input loading: -100µA (max.)
• Chip Enable input
• Output option:
  - PLS100: 3-State
  - PLS101: Open-Collector
• Output disable function:
  - 3-State: Hi-Z
  - Open-Collector: High

Applications

• CRT display systems
• Code conversion
• Peripheral controllers
• Function generators
• Look-up and decision tables
• Microprogramming
• Address mapping
• Character generators
• Data security encoders
• Fault detectors
• Frequency synthesizers
• 16-bit to 8-bit bus interface
• Random logic replacement

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Disclaimers

• General product disclaimer
• Quality and reliability disclaimer