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SAA7104H; SAA7105H

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Datasheet

SAA7104H; SAA7105H
(Product Specification)
04-Mar-04, 71 pages, 355 kB

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SAA7104H; SAA7105H - Digital video encoder

General description
Features
Products/packages
Quality/reliability/chemical content
Pricing/ordering/availability
Samples
Discontinued information
Applications
Block diagrams/pinning
Design support
Parametrics/similar products
Print/email
Disclaimers
All information hereunder is subject to the subsequent disclaimers

General description

The SAA7104H; SAA7105H is an advanced next-generation video encoder which converts PC graphics data at maximum 1280 X 1024 resolution (optionally 1920 X 1080 interlaced) to PAL (50 Hz) or NTSC (60 Hz) video signals. A programmable scaler and anti-flicker filter (maximum 5 lines) ensures properly sized and flicker-free TV display as CVBS or S-video output.

Alternatively, the three Digital-to-Analog Converters (DACs) can output RGB signals together with a TTL composite sync to feed SCART connectors.

When the scaler/interlacer is bypassed, a second VGA monitor can be connected to the RGB outputs and separate H and V-syncs as well, thereby serving as an auxiliary monitor at maximum 1280 X 1024 resolution/60 Hz (PIXCLK < 85 MHz). Alternatively this port can provide Y, PB and PR signals for HDTV monitors.

The device includes a sync/clock generator and on-chip DACs.

All inputs intended to interface to the host graphics controller are designed for low-voltage signals between down to 1.1 V and up to 3.6 V.

Features

  • Digital PAL/NTSC encoder with integrated high quality scaler and anti-flicker filter for TV output from a PC
  • Supports Intel® Digital Video Out (DVO) low voltage interfacing to graphics controller
  • 27 MHz crystal-stable subcarrier generation
  • Maximum graphics pixel clock 85 MHz at double edged clocking, synthesized on-chip or from external source
  • Programmable assignment of clock edge to bytes (in double edged mode)
  • Synthesizable pixel clock (PIXCLK) with minimized output jitter, can be used as reference clock for the VGC, as well)
  • PIXCLK output and bi-phase PIXCLK input (VGC clock loop-through possible)
  • Hot-plug detection through dedicated interrupt pin
  • Supported VGA resolutions for PAL or NTSC legacy video output up to 1280 X 1024 graphics data at 60 or 50 Hz frame rate
  • Supported VGA resolutions for HDTV output up to 1920 X 1080 interlaced graphics data at 60 or 50 Hz frame rate
  • Three Digital-to-Analog Converters (DACs) for CVBS (BLUE, CB), VBS (GREEN, CVBS) and C (RED, CR) at 27 MHz sample rate (signals in parenthesis are optionally), all at 10-bit resolution
  • Non-interlaced CB-Y-CR or RGB input at maximum 4 : 4 : 4 sampling
  • Downscaling and upscaling from 50 to 400 pct.
  • Optional interlaced CB-Y-CR input of Digital Versatile Disk (DVD) signals
  • Optional non-interlaced RGB output to drive second VGA monitor (bypass mode, maximum 85 MHz)
  • 3 X 256 bytes RGB Look-Up Table (LUT)
  • Support for hardware cursor
  • HDTV up to 1920 X 1080 interlaced and 1280 X 720 progressive, including 3-level sync pulses
  • Programmable border colour of underscan area
  • Programmable 5 line anti-flicker filter
  • On-chip 27 MHz crystal oscillator (3rd-harmonic or fundamental 27 MHz crystal)
  • Fast I2C-bus control port (400 kHz)
  • Encoder can be master or slave
  • Adjustable output levels for the DACs
  • Programmable horizontal and vertical input synchronization phase
  • Programmable horizontal sync output phase
  • Internal Colour Bar Generator (CBG)
  • Optional support of various Vertical Blanking Interval (VBI) data insertion
  • Macrovision™(1) Pay-per-View copy protection system rev. 7.01, rev. 6.1 and rev. 1.03 (525p) as option; this applies to the SAA7104H only. The device is protected by USA patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. Use of the Macrovision anti-copy process in the device is licensed for non-commercial home use only. Reverse engineering or disassembly is prohibited. Please contact your nearest Philips Semiconductors sales office for more information.
  • Optional cross-colour reduction for PAL and NTSC CVBS outputs
  • Power-save modes
  • Joint Test Action Group (JTAG) boundary scan test
  • Monolithic CMOS 3.3 V device, 5 V tolerant I/Os
  • QFP64 package.

(1) Macrovision™ is a trademark of the Macrovision Corporation.

Products/packages

Type numberOrderable part numberOrdering code (12NC)Product statusPackagePackingMarkingECCN
SAA7105H/V1SAA7105H/V1,5189352 705 44518Volume productionSOT393Reel Dry Pack, SMD, 13"Standard Marking
SAA7105H/V1SAA7105H/V1,5579352 705 44557Volume productionSOT393Tray Dry Pack, Bakeable, MultipleStandard Marking

Quality/reliability/chemical content

Type numberOrderable part numberChemical contentRoHSLeadfree Conversion dateRHFIRF (FIT)MTBF (hours)MSL
SAA7105H/V1SAA7105H/V1,518SAA7105H_V1
week 21, 2004
SAA7105H/V1SAA7105H/V1,557SAA7105H_V1
week 21, 2004

Quality and reliability disclaimer

Pricing/ordering/availability

Type numberOrdering code(12NC)Orderable part numberIndicative price/unit($)RegionDistributorIn stockOrder quantityInventory dateBuy onlineSamples
SAA7105H/V19352 705 44518  SAA7105H/V1,518  NAMOUSER ELECTRONICS598 11/20/2009Buy onlinenot available
    NAMOUSER ELECTRONICS598 11/20/2009Buy online 
    ASIASACL - Hong Kong/Chinayes60011/20/2009Buy online 
SAA7105H/V19352 705 44557  SAA7105H/V1,557  NADIGI-KEY CORPORATION491 11/20/2009Buy onlinenot available
    NAAVNET ELECTRONICS MARKETING324 11/19/2009Buy online 
    NAARROW ELECTRONICS220 11/19/2009Buy online 
    ASIASACL - Hong Kong/Chinayes42011/20/2009Buy online 

Design support

Support Documents