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SAA7144HL

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Datasheet

SAA7144HL
(Product Specification)
21-Apr-05, 64 pages, 312 kB

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SAA7144HL - Quadruple video input processor

General description
Features
Products/packages
Quality/reliability/chemical content
Pricing/ordering/availability
Samples
Discontinued information
Applications
Block diagrams/pinning
Design support
Parametrics/similar products
Print/email
Disclaimers
All information hereunder is subject to the subsequent disclaimers

General description

The SAA7144HL is a combination of four stand alone multistandard video decoders.

The SAA7144HL is a pure 3.3 V (5 V tolerant inputs and I/Os) CMOS circuit and a highly integrated circuit for video surveillance applications. All four video decoders are based on the principle of line-locked clock decoding and are able to decode the color of PAL, SECAM and NTSC signals into "CCIR 601" compatible color component values.

The SAA7144HL accepts as analog inputs in total eight CVBS sources from TV or VTR (two selectable CVBS sources for each of the four decoders).

Each of the four video decoders (A, B, C, D) contains an analog preprocessing circuit including source selection for two CVBS sources, anti-aliasing filter and Analog-to-Digital Converter (ADC), an automatic clamp and gain control, a Clock Generation Circuit (CGC), a digital multistandard decoder (PAL, NTSC and SECAM), a Brightness Contrast Saturation (BCS) control circuit, a multistandard text slicer see Figure 1 and a 27 MHz VBI data bypass.

The integrated high performance multistandard data slicer supports several VBI data standards:

  • Teletext [WST (World Standard Teletext), CCST (Chinese teletext)] (625 lines)
  • Teletext [US-WST, NABTS (North American Broadcast Text System) and MOJI (Japanese teletext)] (525 lines)
  • Closed caption [Europe, US (line 21)]
  • Wide Screen Signalling (WSS)
  • Video Programming Signal (VPS)
  • Time codes (VITC EBU/SMPTE)
  • HIGH-speed VBI data bypass for Intercast application.

The circuit is I2C-bus controlled via two I2C-bus interfaces where two video decoders share one I2C-bus interface on different I2C-bus slave addresses. Each of the four video decoders of the SAA7144HL uses a register mapping which is compatible to the SAA7113H register mapping.

Features

General

  • Four stand alone video decoder instances (A, B, C, D) with two selectable CVBS video inputs each and digital video outputs
  • Programming register mapping identical to SAA7113H
  • Small package (LQFP128)
  • Requires only one crystal (24.576 MHz) for all standards shared by all video decoder instances
  • CMOS 3.3 V device with 5 V tolerant digital inputs and I/O ports
  • All four decoder instances are I2C-bus controlled. Two decoder instances share one I2C-bus interface (full read-back ability by an external controller, bit rate up to 400 kbit/s).

Features of each of the four video decoder instances A, B, C and D

  • Two analog CVBS inputs with internal analog source selectors
  • One analog preprocessing channel in differential CMOS style with built-in analog anti-aliasing filter
  • Fully programmable static gain or automatic gain control for the selected CVBS channel
  • Switchable white peak control
  • Line-locked system clock frequencies
  • Digital PLL for horizontal sync processing and clock generation, horizontal and vertical sync detection
  • Automatic detection of 50 Hz and 60 Hz field frequency and automatic switching between PAL and NTSC standards
  • Luminance and chrominance signal processing for PAL BGHI, PAL N, combination PAL N, PAL M, NTSC M, NTSC N, NTSC 4.43, NTSC Japan and SECAM
  • User programmable luminance peaking or aperture correction
  • Cross-color reduction for NTSC by chrominance comb filtering
  • PAL delay line for correcting PAL phase errors
  • Brightness Contrast Saturation (BCS) and hue control on-chip
  • Multistandard VBI data slicer decoding World Standard Teletext (WST), North American Broadcast Text System (NABTS), closed caption, Wide Screen Signalling (WSS), Video Programming System (VPS), Vertical Interval Time Code (VITC) variants (EBU/SMPTE), etc.
  • Standard ITU-R BT 656 Y-CB -CR 4 : 2 : 2 format (8-bit) on VPO output bus
  • Enhanced ITU-R BT 656 output format on VPO output bus containing:
    • Active video
    • Decoded VBI data
  • Boundary scan test circuit complies with the "IEEE Std. 1149.b1 - 1994".

Products/packages

Type numberOrderable part numberOrdering code (12NC)Product statusPackagePackingMarkingECCN
SAA7144HL/V1SAA7144HL/V1,5579352 766 79557Volume productionSOT425-1
(LQFP128)
Tray Dry Pack, Bakeable, MultipleStandard Marking

Quality/reliability/chemical content

Type numberOrderable part numberChemical contentRoHSLeadfree Conversion dateRHFIRF (FIT)MTBF (hours)MSL
SAA7144HL/V1SAA7144HL/V1,557SAA7144HL_V1
Always Pb-free

Quality and reliability disclaimer

Pricing/ordering/availability

Type numberOrdering code(12NC)Orderable part numberIndicative price/unit($)RegionDistributorIn stockOrder quantityInventory dateBuy onlineSamples
SAA7144HL/V19352 766 79557  SAA7144HL/V1,557  ASIASACL - Hong Kong/Chinayes36011/20/2009Buy onlineOrder samples

Applications

  • Surveillance application.

Design support

Support Documents