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SSTL16857
Datasheet
General description
The SSTL16857 is a 14-bit SSTL_2 registered driver with differential clock inputs. Both VCC and VDDQ support 2.5V and 3.3V operation however. VDDQ must not exceed VCC. Inputs are SSTL_2 type with VREF normally at 0.5*VDDQ. The outputs support class I which can be used for standard stub-series applications or capacitive loads. Master reset (RESET) asynchronously resets all registers to zero.
The SSTL16857 is intended to be incorporated into standard DIMM (Dual In-Line Memory Module) designs defined by JEDEC, such as DDR (Double Data Rate) SDRAM or SDRAM II Memory Modules. Different from traditional SDRAM, DDR SDRAM transfers data on both clock edges (rising and falling), thus doubling the peak bus bandwidth. A DDR DRAM rated at 100 MHz will have a burst rate of 200 MHz. The modules require between 23 and 27 registered control and address lines, so two 14-bit wide devices will be used on each module. The SSTL16857 is intended to be used for SSTL_2 input and output signals.
The device data inputs consist of differential receivers. One differential input is tied to the input pin while the other is tied to a reference input pad, which is shared by all inputs.
The clock input is fully differential to be compatible with DRAM devices that are installed on the DIMM. However, since the control inputs to the SDRAM change at only half the data rate, the device must only change state on the positive transition of the CLK signal. In order to be able to provide defined outputs from the device even before a stable clock has been supplied, the device must support an asynchronous input pin (reset), which when held to the LOW state will assume that all registers are reset to the LOW state and all outputs drive a LOW signal as well.
Features
- Stub-series terminated logic for 2.5V VDDQ (SSTL_2)
- Optimized for DDR (Double Data Rate) SDRAM applications
- Supports SSTL_2 signal inputs and outputs
- Flow-through architecture optimizes PCB layout
- Meets SSTL_2 class I and class II specifications
- Latch-up protection exceeds 500mA per JEDEC Std 17
- ESD protection exceeds 2000 V per MIL STD 833 Method 3015 and 200 V per Machine Model
- Full DDR solution provided when used with PCK857 and CBT3857
Products/packages
| Type number | North American Type number | Ordering code (12NC) | Product status | Package | Packing | Marking | Chemical content | Leadfree conversion date |
|---|---|---|---|---|---|---|---|---|
| SSTL16857DGG | 9352 630 37512 | Samples available | SOT362-1
(TSSOP48) | Tube Dry Pack | Standard Marking | SSTL16857DGG
| week 13, 2005 | |
| SSTL16857DGG | 9352 630 37518 | Samples available | SOT362-1
(TSSOP48) | Reel Dry Pack, SMD, 13" | Standard Marking | SSTL16857DGG
| week 13, 2005 |
Pricing/ordering/availability
| Type number | Ordering code(12NC) | Indicative price/unit($) | Region | Distributor | In stock | Inventory date | Buy online | Samples |
|---|---|---|---|---|---|---|---|---|
| SSTL16857DGG | 9352 630 37512 | not available | ||||||
| SSTL16857DGG | 9352 630 37518 | not available |
Technical documents
Support Documents
Parametrics/similar products
| Type number | Package | Supply voltage(V) | Application | Other features | Operating temp.(Cel) | Propagation Delay(ns) | Operating Frequency(MHz) | Inputs | Outputs | Set-up time (DATA-CLK)(ns) | Hold time (CLK-DATA)(ns) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| SSTL16857DGG | SOT362-1
(TSSOP48) |
2.5 3.3 | DDR SDRAM register | master reset | 0~+70 | 1.8 | 200 | 14 x SSTL-2 | 14 x SSTL-2 | 0.8 | 0.5 |
Similar products
SSTL16857 links to the similar products page containing an overview of products that are similar in function or related to the type number(s) as listed on this page. The similar products page includes products from the same catalog tree(s), relevant selection guides and products from the same functional category.
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