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SSTU32866

Selection guide

Datasheet

SSTU32866
(Product Specification)
11-Nov-04, 29 pages, 158 kB

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SSTU32866 - 1.8 V 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity for DDR2 RDIMM applications

General description
Features
Products/packages
Quality/reliability/chemical content
Pricing/ordering/availability
Samples
Discontinued information
Applications
Block diagrams/pinning
Design support
Parametrics/similar products
Print/email
Disclaimers
All information hereunder is subject to the subsequent disclaimers

General description

The SSTU32866 is a 1.8 V configurable register specifically designed for use on DDR2 memory modules requiring a parity checking function. It is defined in accordance with the JEDEC JESD82-7 standard for the SSTU32864 registered buffer, while adding the parity checking function in a compatible pinout. The JEDEC standard for SSTU32866 is pending publication. The register is configurable (using configuration pins C0 and C1) to two topologies: 25-bit 1:1 or 14-bit 1:2, and in the latter configuration can be designated as Register A or Register B on the DIMM.

The SSTU32866 accepts a parity bit from the memory controller on its parity bit (PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs and indicates whether a parity error has occurred on its open-drain QERR pin (active-LOW). The convention is even parity, that is, valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity input bit.

The SSTU32866 is packaged in a 96-ball, 6 x 16 grid, 0.8 mm ball pitch LFBGA package (13.5 mm by 5.5 mm).

Features

  • Configurable register supporting DDR2 Registered DIMM applications
  • Configurable to 25-bit 1:1 mode or 14-bit 1:2 mode
  • Controlled output impedance drivers enable optimal signal integrity and speed
  • Exceeds JESD82-7 speed performance (1.8 ns max. single-bit switching propagation delay; 2.0 ns max. mass-switching)
  • Supports up to 450 MHz clock frequency of operation
  • Optimized pinout for high-density DDR2 module design
  • Chip-selects minimize power consumption by gating data outputs from changing state
  • Supports SSTL_18 data inputs
  • Checks parity on the DIMM-independent data inputs
  • Partial parity output and input allows cascading of two SSTU32866s for correct parity error processing
  • Differential clock (CK and CK) inputs
  • Supports LVCMOS switching levels on the control and RESET inputs
  • Single 1.8 V supply operation
  • Available in 96-ball, 13.5 x 5.5 mm, 0.8 mm ball pitch LFBGA package

Products/packages

Type numberOrderable part numberOrdering code (12NC)Product statusPackagePackingMarkingECCN
SSTU32866ECSSTU32866EC,5189352 750 71518Volume productionSOT536-1
(LFBGA96)
Tape reel smdStandard Marking
SSTU32866ECSSTU32866EC,5519352 750 71551Volume productionSOT536-1
(LFBGA96)
Tray Dry Pack, Bakeable, SingleStandard Marking
SSTU32866ECSSTU32866EC,5579352 750 71557Volume productionSOT536-1
(LFBGA96)
Tray Dry Pack, Bakeable, MultipleStandard Marking
SSTU32866EC/GSSTU32866EC/G,5189352 754 73518Volume productionSOT536-1
(LFBGA96)
Tape reel smdStandard Marking
SSTU32866EC/GSSTU32866EC/G,5519352 754 73551Volume productionSOT536-1
(LFBGA96)
Tray Dry Pack, Bakeable, SingleStandard Marking
SSTU32866EC/GSSTU32866EC/G,5579352 754 73557Volume productionSOT536-1
(LFBGA96)
Tray Dry Pack, Bakeable, MultipleStandard Marking

Quality/reliability/chemical content

Type numberOrderable part numberChemical contentRoHSLeadfree Conversion dateRHFIRF (FIT)MTBF (hours)MSL
SSTU32866ECSSTU32866EC,518SSTU32866EC
SSTU32866ECSSTU32866EC,551SSTU32866EC
SSTU32866ECSSTU32866EC,557SSTU32866EC
SSTU32866EC/GSSTU32866EC/G,518SSTU32866EC_G
Always Pb-free
SSTU32866EC/GSSTU32866EC/G,551SSTU32866EC_G
Always Pb-free
SSTU32866EC/GSSTU32866EC/G,557SSTU32866EC_G
Always Pb-free

Quality and reliability disclaimer

Pricing/ordering/availability

Type numberOrdering code(12NC)Orderable part numberIndicative price/unit($)RegionDistributorIn stockOrder quantityInventory dateBuy onlineSamples
SSTU32866EC9352 750 71518  SSTU32866EC,518  6.8700      not available
SSTU32866EC9352 750 71551  SSTU32866EC,551  6.8700      not available
SSTU32866EC9352 750 71557  SSTU32866EC,557  6.8700      not available
SSTU32866EC/G9352 754 73518  SSTU32866EC/G,518        not available
SSTU32866EC/G9352 754 73551  SSTU32866EC/G,551  NADIGI-KEY CORPORATION260 11/20/2009Buy onlinenot available
SSTU32866EC/G9352 754 73557  SSTU32866EC/G,557        not available

Applications

  • DDR2 registered DIMMs desiring parity checking functionality

Block diagrams/pinning

Parametrics/similar products

Type numberPackageSupply
voltage(V)
ApplicationFEATURESOperating
temp.(Cel)
Propagation Delay(ns)Operating Frequency(MHz)InputsOutputsSet-up time (DATA-CLK)(ns)Hold time (CLK-DATA)(ns)
SSTU32866ECSOT536-1
(LFBGA96)
1.7~1.9DDR2 400-533 Registered DIMMsParity checking0~+701.4~1.80~27014 (1:2) or 25 (1:1) x SSTL_1825 (1:1) or 28 (1:2) x SSTL_180.20.75
SSTU32866EC/GSOT536-1
(LFBGA96)
1.7~1.9DDR2 400-533 Registered DIMMsParity checking0~+701.4~1.80~27014 (1:2) or 25 (1:1) x SSTL_1825 (1:1) or 28 (1:2) x SSTL_180.20.75


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