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Datasheet

SSTU32866
(Product Specification)
11-Nov-04, 29 pages, 158 kB

General description

The SSTU32866 is a 1.8 V configurable register specifically designed for use on DDR2 memory modules requiring a parity checking function. It is defined in accordance with the JEDEC JESD82-7 standard for the SSTU32864 registered buffer, while adding the parity checking function in a compatible pinout. The JEDEC standard for SSTU32866 is pending publication. The register is configurable (using configuration pins C0 and C1) to two topologies: 25-bit 1:1 or 14-bit 1:2, and in the latter configuration can be designated as Register A or Register B on the DIMM.

The SSTU32866 accepts a parity bit from the memory controller on its parity bit (PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs and indicates whether a parity error has occurred on its open-drain QERR pin (active-LOW). The convention is even parity, that is, valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity input bit.

The SSTU32866 is packaged in a 96-ball, 6 x 16 grid, 0.8 mm ball pitch LFBGA package (13.5 mm by 5.5 mm).

Features

  • Configurable register supporting DDR2 Registered DIMM applications
  • Configurable to 25-bit 1:1 mode or 14-bit 1:2 mode
  • Controlled output impedance drivers enable optimal signal integrity and speed
  • Exceeds JESD82-7 speed performance (1.8 ns max. single-bit switching propagation delay; 2.0 ns max. mass-switching)
  • Supports up to 450 MHz clock frequency of operation
  • Optimized pinout for high-density DDR2 module design
  • Chip-selects minimize power consumption by gating data outputs from changing state
  • Supports SSTL_18 data inputs
  • Checks parity on the DIMM-independent data inputs
  • Partial parity output and input allows cascading of two SSTU32866s for correct parity error processing
  • Differential clock (CK and CK) inputs
  • Supports LVCMOS switching levels on the control and RESET inputs
  • Single 1.8 V supply operation
  • Available in 96-ball, 13.5 x 5.5 mm, 0.8 mm ball pitch LFBGA package

Products/packages

Type numberNorth American Type numberOrdering code (12NC)Product statusPackagePackingMarkingChemical contentLeadfree conversion date
SSTU32866ECSSTU32866EC-T9352 750 71518Volume productionSOT536-1
(LFBGA96)
Tape reel smdStandard MarkingSSTU32866EC
SSTU32866ECSSTU32866EC-S9352 750 71551Volume productionSOT536-1
(LFBGA96)
Tray Dry Pack, Bakeable, SingleStandard MarkingSSTU32866EC
SSTU32866ECSSTU32866EC9352 750 71557Volume productionSOT536-1
(LFBGA96)
Tray Dry Pack, Bakeable, MultipleStandard MarkingSSTU32866EC
SSTU32866EC/GSSTU32866EC/G-T9352 754 73518Volume productionSOT536-1
(LFBGA96)
Tape reel smdStandard MarkingSSTU32866EC/G
Always Pb-free
SSTU32866EC/GSSTU32866EC/G-S9352 754 73551Volume productionSOT536-1
(LFBGA96)
Tray Dry Pack, Bakeable, SingleStandard MarkingSSTU32866EC/G
Always Pb-free
SSTU32866EC/GSSTU32866EC/G9352 754 73557Volume productionSOT536-1
(LFBGA96)
Tray Dry Pack, Bakeable, MultipleStandard MarkingSSTU32866EC/G
Always Pb-free

Pricing/ordering/availability

Type numberOrdering code(12NC)Indicative price/unit($)RegionDistributorIn stockInventory dateBuy onlineSamples
SSTU32866EC9352 750  71518  6.8700     not available
SSTU32866EC9352 750  71551  6.8700      Order samples
SSTU32866EC9352 750  71557  6.8700     not available
SSTU32866EC/G9352 754  73518       not available
SSTU32866EC/G9352 754  73551  NADIGI-KEY CORPORATION1857/18/2008 Buy online not available
SSTU32866EC/G9352 754  73557       not available

Applications

  • DDR2 registered DIMMs desiring parity checking functionality

Block diagrams/pinning

Technical documents

Support Documents

75014354; Memory interface selection guide Support logic for memory modules and other memory subsystems (2005-06-01)
75014345; SSTU32864/5/6 and PCKU877/8 Complete register and PLL solutions for DDR2 (2005-06-01)

Parametrics/similar products

Type numberPackageSupply
voltage(V)
ApplicationFEATURESOperating
temp.(Cel)
Propagation Delay(ns)Operating Frequency(MHz)InputsOutputsSet-up time (DATA-CLK)(ns)Hold time (CLK-DATA)(ns)
SSTU32866ECSOT536-1
(LFBGA96)
1.7~1.9 DDR2 400-533 Registered DIMMs Parity checking 0~+70 1.4~1.8 0~270 14 (1:2) or 25 (1:1) x SSTL_18 25 (1:1) or 28 (1:2) x SSTL_18 0.2 0.75
SSTU32866EC/GSOT536-1
(LFBGA96)
1.7~1.9 DDR2 400-533 Registered DIMMs Parity checking 0~+70 1.4~1.8 0~270 14 (1:2) or 25 (1:1) x SSTL_18 25 (1:1) or 28 (1:2) x SSTL_18 0.2 0.75

Similar products

SSTU32866 links to the similar products page containing an overview of products that are similar in function or related to the type number(s) as listed on this page. The similar products page includes products from the same catalog tree(s), relevant selection guides and products from the same functional category.

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