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SSTUA32S865
Datasheet
(Product Specification)
16-Mar-07, 29 pages, 152 kB
General description
The SSTUA32S865 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank by four (2R x 4) and similar high-density Double Data Rate 2 (DDR2) memory modules. It is similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the functionality of the normally required two registers in a single package, thereby freeing up board real-estate and facilitating routing to accommodate high-density Dual In-line Memory Module (DIMM) designs.
The SSTUA32S865 also integrates a parity function, which accepts a parity bit from the memory controller, compares it with the data received on the D-inputs and indicates whether a parity error has occurred on its open-drain PTYERR pin (active LOW).
The SSTUA32S865 is packaged in a 160-ball, 12 x 18 grid, 0.65 mm ball pitch, thin profile fine-pitch ball grid array (TFBGA) package, which (while requiring a minimum 9 mm x 13 mm of board space) allows for adequate signal routing and escape using conventional card technology.
Features
- 28-bit data register supporting DDR2
- Fully compliant to JEDEC standard for SSTUA32S865
- Supports 2 rank by 4 DIMM density by integrating equivalent functionality of two JEDEC-standard DDR2 registers (that is, 2 x SSTUA32864 or 2 x SSTUA32866)
- Parity checking function across 22 input data bits
- Parity out signal
- Controlled output impedance drivers enable optimal signal integrity and speed
- Exceeds JESD82-9 speed performance (1.8 ns max. single-bit switching propagation delay, 2.0 ns max. mass-switching)
- Supports up to 450 MHz clock frequency of operation
- Optimized pinout for high-density DDR2 module design
- Chip-selects minimize power consumption by gating data outputs from changing state
- Supports Stub Series Terminated Logic SSTL_18 data inputs
- Differential clock (CK and CK) inputs
- Supports Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS) switching levels on the control and RESET inputs
- Single 1.8 V supply operation (1.7 V to 2.0 V)
- Available in 160-ball 9 mm x 13 mm, 0.65 mm ball pitch TFBGA package
Products/packages
| Type number | Orderable part number | Ordering code (12NC) | Product status | Package | Packing | Marking | ECCN |
|---|---|---|---|---|---|---|---|
| SSTUA32S865ET/G | SSTUA32S865ET/G,51 | 9352 794 45518 | Volume production | SOT802-2
(TFBGA160) | Reel Dry Pack, SMD, 13" | Standard Marking |
Quality/reliability/chemical content
| Type number | Orderable part number | Chemical content | RoHS | Leadfree Conversion date | RHF | IRF (FIT) | MTBF (hours) | MSL |
|---|---|---|---|---|---|---|---|---|
| SSTUA32S865ET/G | SSTUA32S865ET/G,51 | SSTUA32S865ET_G |
| Always Pb-free |
Pricing/ordering/availability
| Type number | Ordering code(12NC) | Orderable part number | Indicative price/unit($) | Region | Distributor | In stock | Order quantity | Inventory date | Buy online | Samples |
|---|---|---|---|---|---|---|---|---|---|---|
| SSTUA32S865ET/G | 9352 794 45518 | SSTUA32S865ET/G,51 | not available |
Applications
Parametrics/similar products
| Type number | Package | Supply voltage(V) | Application | FEATURES | Other features | Operating temp.(Cel) | Propagation Delay(ns) | Operating Frequency(MHz) | Inputs | Outputs |
|---|---|---|---|---|---|---|---|---|---|---|
| SSTUA32S865ET/G | SOT802-2
(TFBGA160) | 1.7~2.0 | DDR2 400-667 Registered DIMMs | Parity checking | drive strength programmable; 4 chip select inputs | 0~+70 | 1.2~1.8 | 0~450 | 28 x SSTL_18 | 56 x SSTL_18 |
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