SSTUG32865

General description

The SSTUG32865 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank by four (2R x 4) and similar high-density Double Data Rate 2 (DDR2) memory modules. It is similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the functionality of the normally required two registers in a single package, thereby freeing up board real-estate and facilitating routing to accommodate high-density Dual In-line Memory Module (DIMM) designs.

The SSTUG32865 also integrates a parity function, which accepts a parity bit from the memory controller, compares it with the data received on the D-inputs and indicates whether a parity error has occurred on its open-drain PTYERR pin (active LOW).

It further offers added features over the JEDEC standard register in that it can be configured for normal or high output drive strength, simply by tying input pin SELDR either HIGH of LOW as needed. This allows use in different module designs varying from low to high density designs by picking the appropriate drive strength to match net loading conditions. Furthermore, the SSTUG32865 features two additional chip select inputs, which allow more versatile enabling and disabling in densely populated memory modules. Both added features (drive strength and chip selects) are fully backward compatible to the JEDEC standard register.

The SSTUG32865 is packaged in a 160-ball, 12 x 18 grid, 0.65 mm ball pitch, thin profile fine-pitch ball grid array (TFBGA) package, which, while requiring a minimum 9 mm x 13 mm of board space, allows for adequate signal routing and escape using conventional card technology.

Features

• 28-bit data register supporting DDR2
• Fully compliant to JEDEC standard for SSTUB32865
• Supports 2 rank by 4 DIMM density by integrating equivalent functionality of two JEDEC-standard DDR2 registers (that is, 2 x SSTUB32864 or 2 x SSTUB32866)
• Parity checking function across 22 input data bits
• Parity out signal
• Controlled multi-impedance output impedance drivers enable optimal signal integrity and speed
• Exceeds SSTUB32865 JEDEC standard speed performance
• Supports up to 550 MHz clock frequency of operation
• Programmable for normal or high output drive
• Optimized pinout for high-density DDR2 module design
• Chip-selects minimize power consumption by gating data outputs from changing state
• Two additional chip select inputs allow optional flexible enabling and disabling
• Supports Stub Series Terminated Logic SSTL_18 data inputs
• Differential clock (CK and CK) inputs
• Supports LVCMOS switching levels on the control and RESET inputs
• Single 1.8 V supply operation (1.7 V to 2.0 V)
• Available in 160-ball 9 mm x 13 mm, 0.65 mm ball pitch TFBGA package

Products/packages

Quality/reliability/chemical content

Quality and reliability disclaimer

Pricing/ordering/availability

Applications

• 400 MT/s to 800 MT/s high-density (for example, 2 rank by 4) DDR2 registered DIMMs
• DDR2 Registered DIMMs (RDIMM) desiring parity checking functionality

Block diagrams/pinning

Parametrics/similar products

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SSTUG32865 links to the similar products page containing an overview of products that are similar in function or related to the type number(s) as listed on this page. The similar products page includes products from the same catalog tree(s), relevant selection guides and products from the same functional category.

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Disclaimers

• General product disclaimer
• Quality and reliability disclaimer