SSTUH32866

General description

The SSTUH32866 is a 1.8 V configurable register specifically designed for use on DDR2 memory modules requiring a parity checking function. It is defined in accordance with the JEDEC JESD82-7 standard for the SSTU32864 registered buffer, while adding the parity checking function in a compatible pinout. The JEDEC standard for SSTUH32866 is pending publication. The register is configurable (using configuration pins C0 and C1) to two topologies: 25-bit 1 : 1 or 14-bit 1 : 2, and in the latter configuration can be designated as Register A or Register B on the DIMM.

The SSTUH32866 accepts a parity bit from the memory controller on its parity bit (PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs and indicates whether a parity error has occurred on its open-drain QERR pin (active LOW). The convention is even parity, that is, valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity input bit.

The SSTUH32866 is packaged in a 96-ball, 6 x 16 grid, 0.8 mm ball pitch LFBGA package (13.5 mm x 5.5 mm).

The SSTUH32866 is identical to SSTU32866 in function and performance, with higher-drive outputs optimized to drive heavy load nets (for example, stacked DRAMs) while maintaining speed and signal integrity.

Features

• Configurable register supporting DDR2 Registered DIMM applications
• Higher output drive strength version of SSTU32866 optimized for high-capacitive load nets
• Configurable to 25-bit 1 : 1 mode or 14-bit 1 : 2 mode
• Controlled output impedance drivers enable optimal signal integrity and speed
• Exceeds JESD82-7 speed performance (1.8 ns max. single-bit switching propagation delay; 2.0 ns max. mass-switching)
• Supports up to 450 MHz clock frequency of operation
• Optimized pinout for high-density DDR2 module design
• Chip-selects minimize power consumption by gating data outputs from changing state
• Supports SSTL_18 data inputs
• Checks parity on the DIMM-independent data inputs
• Partial parity output and input allows cascading of two SSTUH32866s for correct parity error processing
• Differential clock (CK and CK) inputs
• Supports LVCMOS switching levels on the control and RESET inputs
• Single 1.8 V supply operation
• Available in 96-ball, 13.5 mm x 5.5 mm, 0.8 mm ball pitch LFBGA package

Products/packages

The variants in the table below are discontinued. See the table Discontinued information for more information.

Quality/reliability/chemical content

The variants in the table below are discontinued. See the table Discontinued information for more information.

Quality and reliability disclaimer

Pricing/ordering/availability

Discontinued information

Applications

• DDR2 registered DIMMs desiring parity checking functionality
• Stacked or planar high-DRAM count registered DIMMs

Block diagrams/pinning

Parametrics/similar products

Similar products
SSTUH32866 links to the similar products page containing an overview of products that are similar in function or related to the type number(s) as listed on this page. The similar products page includes products from the same catalog tree(s), relevant selection guides and products from the same functional category.

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Disclaimers

• General product disclaimer
• Quality and reliability disclaimer