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SSTUM32866

Selection guide

Datasheet

SSTUM32866
(Product Specification)
29-Jun-07, 28 pages, 151 kB

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SSTUM32866 - 1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-1G RDIMM applications

General description
Features
Products/packages
Quality/reliability/chemical content
Pricing/ordering/availability
Samples
Discontinued information
Applications
Block diagrams/pinning
Design support
Parametrics/similar products
Print/email
Disclaimers
All information hereunder is subject to the subsequent disclaimers

General description

The SSTUM32866 is a 1.8 V configurable register specifically designed for use on DDR2 memory modules requiring a parity checking function. It is defined in accordance with the JEDEC standard for the SSTUM32866 registered buffer. The register is configurable (using configuration pins C0 and C1) to two topologies: 25-bit 1 : 1 or 14-bit 1 : 2, and in the latter configuration can be designated as Register A or Register B on the DIMM.

The SSTUM32866 accepts a parity bit from the memory controller on its parity bit (PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs and indicates whether a parity error has occurred on its open-drain QERR pin (active LOW). The convention is even parity, that is, valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity input bit.

The SSTUM32866 is the high-output drive version of SSTUG32866.

The SSTUM32866 is packaged in a 96-ball, 6 x 16 grid, 0.8 mm ball pitch LFBGA package (13.5 mm x 5.5 mm).

Features

  • Configurable register supporting DDR2 up to 800 MT/s Registered DIMM applications
  • Configurable to 25-bit 1 : 1 mode or 14-bit 1 : 2 mode
  • Controlled output impedance drivers enable optimal signal integrity and speed
  • Meets or exceeds SSTUM32866 JEDEC standard speed performance
  • High output drive
  • Supports up to 550 MHz clock frequency of operation
  • Optimized pinout for high-density DDR2 module design
  • Chip-selects minimize power consumption by gating data outputs from changing state
  • Supports SSTL_18 data inputs
  • Checks parity on the DIMM-independent data inputs
  • Partial parity output and input allows cascading of two SSTUM32866s for correct parity error processing
  • Differential clock (CK and CK) inputs
  • Supports LVCMOS switching levels on the control and RESET inputs
  • Single 1.8 V supply operation (1.7 V to 2.0 V)
  • Available in 96-ball, 13.5 mm x 5.5 mm, 0.8 mm ball pitch LFBGA package

Products/packages

Type numberOrderable part numberOrdering code (12NC)Product statusPackagePackingMarkingECCN
SSTUM32866EC/GSSTUM32866EC/G,5189352 845 77518Volume productionSOT536-1
(LFBGA96)
Tape reel smdStandard Marking
SSTUM32866EC/SSSTUM32866EC/S,5189352 845 78518Volume productionSOT536-1
(LFBGA96)
Tape reel smdStandard Marking

Quality/reliability/chemical content

Type numberOrderable part numberChemical contentRoHSLeadfree Conversion dateRHFIRF (FIT)MTBF (hours)MSL
SSTUM32866EC/GSSTUM32866EC/G,518SSTUM32866EC_G
Always Pb-free
SSTUM32866EC/SSSTUM32866EC/S,518SSTUM32866EC_S
Always Pb-free

Quality and reliability disclaimer

Pricing/ordering/availability

Type numberOrdering code(12NC)Orderable part numberIndicative price/unit($)RegionDistributorIn stockOrder quantityInventory dateBuy onlineSamples
SSTUM32866EC/G9352 845 77518  SSTUM32866EC/G,518        Order samples
SSTUM32866EC/S9352 845 78518  SSTUM32866EC/S,518        not available

Applications

  • 400 MT/s to 800 MT/s and higher DDR2 registered DIMMs desiring parity checking functionality

Parametrics/similar products

Type numberPackageSupply
voltage(V)
ApplicationFEATURESOther
features
Operating
temp.(Cel)
Propagation Delay(ns)Operating Frequency(MHz)InputsOutputs
SSTUM32866EC/GSOT536-1
(LFBGA96)
1.7~2.0DDR2 800-1G Registered DIMMsParity checkinghigh drive strength0~+701.0~1.40~55014 (1:2) or 25 (1:1) x SSTL_1825 (1:1) or 28 (1:2) x SSTL_18
SSTUM32866EC/SSOT536-1
(LFBGA96)
1.7~2.0DDR2 800-1G Registered DIMMsParity checkinghigh drive strength0~+851.0~1.40~55014 (1:2) or 25 (1:1) x SSTL_1825 (1:1) or 28 (1:2) x SSTL_18


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