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SSTUP32866
Datasheet
(Product Specification)
14-Sep-06, 31 pages, 538 kB
General description
The SSTUP32866 is a 1.8 V configurable register specifically designed for use on DDR2 memory modules requiring a parity checking function. It is defined in accordance with the JEDEC standard for the SSTUA32866 and SSTUB32866 registered buffers. The register is configurable (using configuration pins C0 and C1) to two topologies: 25-bit 1 : 1 or 14-bit 1 : 2, and in the latter configuration can be designated as Register A or Register B on the DIMM. It offers added features over the JEDEC standard register in that it can be configured for high or normal output drive strength, as well as for operation to 667 MT/s or 800 MT/s, simply by tying two input pins HIGH or LOW as needed.
The SSTUP32866 accepts a parity bit from the memory controller on its parity bit (PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs and indicates whether a parity error has occurred on its open-drain QERR pin (active LOW). The convention is even parity, that is, valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity input bit.
The SSTUP32866 is packaged in a 96-ball, 6 x 16 grid, 0.8 mm ball pitch LFBGA package (13.5 mm x 5.5 mm).
Features
- Configurable register supporting DDR2 up to 667 MT/s or 800 MT/s Registered DIMM applications
- Configurable to 25-bit 1 : 1 mode or 14-bit 1 : 2 mode
- Programmable for normal or high output drive
- Controlled multi-impedance output drivers enable optimal signal integrity and speed
- Programmable for 667 MT/s or 800 MT/s speed
- Excellent propagation delay performance
- Supports up to 450 MHz clock frequency of operation
- Optimized pinout for high-density DDR2 module design
- Chip-selects minimize power consumption by gating data outputs from changing state
- Supports SSTL_18 data inputs
- Checks parity on the DIMM-independent data inputs
- Partial parity output and input allows cascading of two SSTUP32866s for correct parity error processing
- Differential clock (CK and CK) inputs
- Supports LVCMOS switching levels on the control and RESET inputs
- Single 1.8 V supply operation (1.7 V to 2.0 V)
- Available in 96-ball, 13.5 mm x 5.5 mm, 0.8 mm ball pitch LFBGA package
Products/packages
| Type number | Orderable part number | Ordering code (12NC) | Product status | Package | Packing | Marking | ECCN |
|---|---|---|---|---|---|---|---|
| SSTUP32866EC/G | SSTUP32866EC/G,518 | 9352 813 92518 | Volume production | SOT536-1
(LFBGA96) | Tape reel smd | Standard Marking | |
| SSTUP32866EC/S | SSTUP32866EC/S,518 | 9352 831 47518 | Volume production | SOT536-1
(LFBGA96) | Tape reel smd | Standard Marking |
Quality/reliability/chemical content
| Type number | Orderable part number | Chemical content | RoHS | Leadfree Conversion date | RHF | IRF (FIT) | MTBF (hours) | MSL |
|---|---|---|---|---|---|---|---|---|
| SSTUP32866EC/G | SSTUP32866EC/G,518 | SSTUP32866EC_G |
| Always Pb-free | ||||
| SSTUP32866EC/S | SSTUP32866EC/S,518 | SSTUP32866EC_S |
| Always Pb-free |
Pricing/ordering/availability
| Type number | Ordering code(12NC) | Orderable part number | Indicative price/unit($) | Region | Distributor | In stock | Order quantity | Inventory date | Buy online | Samples |
|---|---|---|---|---|---|---|---|---|---|---|
| SSTUP32866EC/G | 9352 813 92518 | SSTUP32866EC/G,518 | Order samples | |||||||
| SSTUP32866EC/S | 9352 831 47518 | SSTUP32866EC/S,518 | not available |
Applications
- 667 MT/s to 800 MT/s DDR2 registered DIMMs desiring parity checking functionality
Design support
Support Documents
Parametrics/similar products
| Type number | Package | Supply voltage(V) | Application | FEATURES | Other features | Operating temp.(Cel) | Propagation Delay(ns) | Operating Frequency(MHz) | Inputs | Outputs |
|---|---|---|---|---|---|---|---|---|---|---|
| SSTUP32866EC/G | SOT536-1
(LFBGA96) | 1.7~1.9 | DDR2 400-800 Registered DIMMs | Parity checking | drive strength programmable | 0~+70 | 1.2~1.8 | 0~450 | 14 (1:2) or 25 (1:1) x SSTL_18 | 25 (1:1) or 28 (1:2) x SSTL_18 |
| SSTUP32866EC/S | SOT536-1
(LFBGA96) | 1.7~1.9 | DDR2 400-800 Registered DIMMs | Parity checking | drive strength programmable | 0~+85 | 1.2~1.8 | 0~450 | 14 (1:2) or 25 (1:1) x SSTL_18 | 25 (1:1) or 28 (1:2) x SSTL_18 |
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