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Datasheet

SSTV16857
(Product Specification)
27-Sep-02, 12 pages, 110 kB

General description

The SSTV16857 is a 14-bit SSTL_2 registered driver with differential clock inputs, designed to operate between 2.3 V and 2.7 V. VDDQ must not exceed VCC. Inputs are SSTL_2 type with VREF normally at 0.5*VDDQ. The outputs support class I which can be used for standard stub-series applications or capacitive loads. Master reset (RESET) asynchronously resets all registers to zero.

The SSTV16857 is intended to be incorporated into standard DIMM (Dual In-Line Memory Module) designs defined by JEDEC, such as DDR (Double Data Rate) SDRAM or SDRAM II Memory Modules. Different from traditional SDRAM, DDR SDRAM transfers data on both clock edges (rising and falling), thus doubling the peak bus bandwidth. A DDR DRAM rated at 133 MHz will have a burst rate of 266 MHz. The modules require between 23 and 27 registered control and address lines, so two 14-bit wide devices will be used on each module. The SSTV16857 is intended to be used for SSTL_2 input and output signals.

The device data inputs consist of differential receivers. One differential input is tied to the input pin while the other is tied to a reference input pad, which is shared by all inputs.

The clock input is fully differential to be compatible with DRAM devices that are installed on the DIMM. However, since the control inputs to the SDRAM change at only half the data rate, the device must only change state on the positive transition of the CLK signal. In order to be able to provide defined outputs from the device even before a stable clock has been supplied, the device must support an asynchronous input pin (reset), which when held to the LOW state will assume that all registers are reset to the LOW state and all outputs drive a LOW signal as well.

Features

  • Stub-series terminated logic for 2.5 V VDDQ (SSTL_2)
  • Optimized for DDR (Double Data Rate) SDRAM applications
  • Inputs compatible with JESD8?9 SSTL_2 specifications.
  • Flow-through architecture optimizes PCB layout
  • ESD classification testing is done to JEDEC Standard JESD22. Protection exceeds 2000 V to HBM per method A114.
  • Latch-up testing is done to JEDEC Standard JESD78, which exceeds 100 mA.
  • Same form, fit, and function as SSTL16877
  • Full DDR 200/266 solution @ 2.5 V when used with PCKV857
  • See SSTV16856 for driver/buffer version with mode select.
  • Available in TSSOP-48, TVSOP-48 and 56 ball VFBGA packages

Products/packages

Type numberNorth American Type numberOrdering code (12NC)Product statusPackagePackingMarkingChemical contentLeadfree conversion date
SSTV16857DGGSSTV16857DGG9352 686 61112Volume productionSOT362-1
(TSSOP48)
TubeStandard MarkingSSTV16857DGG
SSTV16857DGGSSTV16857DGG-T9352 686 61118Volume productionSOT362-1
(TSSOP48)
Reel Pack, SMD, 13"Standard MarkingSSTV16857DGG
SSTV16857DGG9352 686 61512Volume productionSOT362-1
(TSSOP48)
Tube Dry PackStandard MarkingSSTV16857DGG
week 14, 2005
SSTV16857DGGSSTV16857DGG-T9352 686 61518Volume productionSOT362-1
(TSSOP48)
Reel Dry Pack, SMD, 13"Standard MarkingSSTV16857DGG
week 14, 2005
SSTV16857DGVSSTV16857DGV9352 706 68112Volume productionSOT480-1
(TSSOP48)
TubeStandard MarkingSSTV16857DGV
week 14, 2005
SSTV16857DGVSSTV16857DGV-T9352 706 68118Volume productionSOT480-1
(TSSOP48)
Reel Pack, SMD, 13"Standard MarkingSSTV16857DGV
week 14, 2005
SSTV16857EVSSTV16857EV-T9352 725 35118Volume productionSOT702-1
(VFBGA56)
Reel Pack, SMD, 13"Standard MarkingSSTV16857EV
SSTV16857EVSSTV16857EV-S9352 725 35151Volume productionSOT702-1
(VFBGA56)
Tray Pack, Bakeable, SingleStandard MarkingSSTV16857EV
SSTV16857EVSSTV16857EV9352 725 35157Volume productionSOT702-1
(VFBGA56)
Tray Pack, Bakeable, MultipleStandard MarkingSSTV16857EV

Pricing/ordering/availability

Type numberOrdering code(12NC)Indicative price/unit($)RegionDistributorIn stockInventory dateBuy onlineSamples
SSTV16857DGG9352 686  61112  1.2500     not available
SSTV16857DGG9352 686  61118       not available
SSTV16857DGG9352 686  61512       not available
SSTV16857DGG9352 686  61518  1.1900      Order samples
SSTV16857DGV9352 706  68112  1.2500     not available
SSTV16857DGV9352 706  68118  1.2500      Order samples
SSTV16857EV9352 725  35118  1.4100     not available
SSTV16857EV9352 725  35151  1.4100     not available
SSTV16857EV9352 725  35157  1.4100      Order samples

Block diagrams/pinning

Technical documents

Support Documents

75010693; DDR (2002-12-20)
75014354; Memory interface selection guide Support logic for memory modules and other memory subsystems (2005-06-01)

Parametrics/similar products

Type numberPackageSupply
voltage(V)
ApplicationOther
features
Operating
temp.(Cel)
Propagation Delay(ns)Operating Frequency(MHz)InputsOutputsSet-up time (DATA-CLK)(ns)Hold time (CLK-DATA)(ns)
SSTV16857DGGSOT362-1
(TSSOP48)
2.5 DDR SDRAM register master reset 0~+70 2.4 200 14 x SSTL-2 14 x SSTL-2 0.2 0.75
SSTV16857DGVSOT480-1
(TSSOP48)
2.5 DDR SDRAM register master reset 0~+70 2.4 200 14 x SSTL-2 14 x SSTL-2 0.2 0.75
SSTV16857EVSOT702-1
(VFBGA56)
2.5 DDR SDRAM register master reset 0~+70 2.4 200 14 x SSTL-2 14 x SSTL-2 0.2 0.75

Similar products

SSTV16857 links to the similar products page containing an overview of products that are similar in function or related to the type number(s) as listed on this page. The similar products page includes products from the same catalog tree(s), relevant selection guides and products from the same functional category.

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