Datasheet
UDA1352HL
(Preliminary Specification)
25-Mar-03, 64 pages, 263 kB
UDA1352HL - 48 kHz IEC 60958 audio DAC
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General description
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Features
- Products/packages
- Quality/reliability/chemical content
- Pricing/ordering/availability
- Samples
- Discontinued information
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Applications
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Block diagrams/pinning
- Design support
- Parametrics/similar products
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Print/email
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Disclaimers
This product has been withdrawn. Please contact your local
Sales or Distributor office
for more details.All information hereunder is subject to the subsequent disclaimers
General description
The UDA1352HL is a single-chip IEC 60958 audio
decoder with an integrated stereo DAC employing
bitstream conversion techniques.
A lock status signal is available on pin LOCK, to indicate
when the IEC 60958 decoder is locked. A PCM detection
status signal is available on pin PCMDET to indicate when
PCM data is present at the input.
By default, the DAC output and the data output interface
are muted when the decoder is out-of-lock. However, this
setting can be overridden in the L3-bus or I2C-bus modes.
The UDA1352HL in package LQFP48 is the full featured
version. Also available is the UDA1352TS in package
SSOP28 which has the IEC 60958 input only to the DAC.
Features
1.1 General
- 2.7 to 3.6 V power supply
- Integrated digital filter and Digital-to-Analog
Converter (DAC)
- 256fs system clock output
- 20-bit data path in interpolator
- High performance
- No analog post filtering required for DAC
- Supported sampling frequencies of 28 up to 55 kHz.
1.2 Control
- Controlled by either static pins, I2C-bus or L3-bus
microcontroller interfaces.
1.3 IEC 60958 input
- On-chip amplifier converts IEC 60958 input to CMOS
levels
- Lock status indication at pin LOCK
- Pulse Code Modulation (PCM) input signal status
indication at pin PCMDET
- Right and left channels each have 40 key
channel-status bits available via L3-bus or I2C-bus
interfaces.
1.4 Digital sound processing and DAC
- Automatic de-emphasis when using IEC 60958 input
with audio sample frequencies (fs ) of 32.0, 44.1 and
48.0 kHz
- Soft mute using a cosine roll-off circuit selectable via
pin MUTE, L3-bus or I2C-bus interfaces
- Left and right independent dB linear volume control
having 0.25 dB steps from 0 to -50 dB, 1 dB steps to
-60, -66 and -∞ dB
- Bass boost and treble control in L3-bus or I2C-bus
modes
- Interpolating filter (fs to 64fs or 128fs ) using cascaded
recursive and FIR filters
- Fifth-order noise shaper (operating either at 64fs
or 128fs ) generates the bitstream for the DAC
- Filter Stream DAC (FSDAC).
Block diagrams/pinning
