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Datasheet

XA-C3
(Preliminary Specification)
25-Jan-00, 68 pages, 368 kB

XA 16-bit microcontroller family 32K/1024 OTP/ROM CAN transport layer controller 1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID Filters, transport layer co-processor

General description
Features
Products/packages
Chemical content
Pricing/ordering/availability
Samples
Applications
Block diagrams/pinning
Technical documents
Parametrics/similar products
Print/email

General description

The XA-C3 is a member of the Philips XA (eXtended Architecture) family of high-performance 16-bit single-chip microcontrollers. The XA-C3 combines an array of standard peripherals together with a PeliCAN CAN 2.0B engine and unique "Message Management" hardware to provide integrated support for most CAN Transport Layer (CTL) protocols such as DeviceNet, CANopen and OSEK. For additional details.

The XA architecture supports:

  • Easy 16-bit migration from the 80C51 architecture.
  • 16-bit fully static CPU with 24-bit addressed PROGRAM and DATA spaces.
  • Twenty-one 16-bit CPU core registers capable of all arithmetic and logic operations while serving as memory pointers.
  • An enhanced orthogonal instruction set tailored for high-level support of the C language.
  • Multi-tasking and direct real-time executive support.
  • Low-power operation intrinsic to the XA architecture includes Power-Down and Idle modes.


Features

FEATURES IN COMMON WITH XA-G3

  • Pin-compatibility (CAN RxD and CAN TxD use the XA-G3 NC pins).
  • 32K bytes of on-chip EPROM PROGRAM memory .
  • 44-pin PLCC and 44-pin LQFP packages.
  • Commercial (0 to 70 °C) and Industrial (-40 to 85 °C) ranges.
  • Supports off-chip addressing of PROGRAM and DATA memory up to 1 megabyte each (20 address lines).
  • Three standard counter/timers (T0, T1, and T2) with enhancements such as Auto Reload for PWM outputs.
  • UART-0 with enhancements such as separate Rx and Tx interrupts, Break Detection, and Automatic Address Recognition.
  • Watchdog with a secure WFEED1 / WFEED2 sequence.
  • Four 8-bit I/O ports with 4 programmable output configurations per pin.


XA-C3 SPECIFIC FEATURES

  • 32 MHz operating frequency at 4.5 to 5.5V operation.
  • One Serial Port Interface (SPI)
  • 1024 bytes of on-chip DATA RAM.
  • 42 vectored interrupts. These include 13 maskable Events, 7 Software interrupts, 6 Exceptions, 16 software Traps, segmented DATA memory, multiple User stacks, and banked registers to support rapid context switching.
  • External interfacing via a 16?bit DATA bus width.


XA-C3 CAN AND CTL FEATURES

  • A PeliCAN CAN 2.0B engine from the SJA1000 Stand-alone CAN controller which supports 11- and 29-bit IDentifiers and the maximum CAN data rate (1 Mbps) and CAN Diagnostics.
  • Hardware "Message Management" support for all major CTL protocols: DeviceNet, CANopen, OSEK.
  • Automatic (hardware) assembly of Fragmented Messages via a Transport Layer Co-Processor. Concurrent assembly of up to 32 separate interleaved Fragmented Messages
  • 32 CAN Transport Layer (CTL) Message Objects are modelled as a FullCAN Object Superset.
  • 32 separate filters/screeners (one per Message Object), each allowing a 30-bit ID Match and full 29-bit Mask (i.e., each filter/screener represents a unique Group address).
  • Each Message Object can be configured as Receive or Transmit.
  • A separate message buffer is associated with each CTL Message Object. 32 message buffers are located in XRAM and managed by 32 DMA channels. Message buffer size for each Message Object is independently configurable in length (from 2 to 256 bytes).
  • For single-chip systems there is a 512-byte (on-chip) XRAM message buffer, independent of the 1K on-chip DATA RAM, which is extendable (off-chip) to 8K bytes (i.e., 32 Message Objects that can be up to 256 bytes each).


CAN Higher Layer Protocols

Products/packages

Type numberNorth American Type numberOrdering code (12NC)Product statusPackagePackingMarkingChemical contentLeadfree conversion date
PXAC37KFA/00PXAC37KFA9352 665 16512Volume productionSOT187-2
(PLCC44)
Tube Dry PackStandard MarkingPXAC37KFA/00
week 45, 2004
PXAC37KFBD/009352 665 18157Volume productionSOT389-1
(LQFP44)
Tray Pack, Bakeable, MultipleStandard MarkingPXAC37KFBD/00
week 33, 2004

Pricing/ordering/availability

Type numberOrdering code(12NC)Indicative price/unit($)RegionDistributorIn stockInventory dateBuy onlineSamples
PXAC37KFA/009352 665  16512  17.5400NADIGI-KEY CORPORATION1,2606/29/2008 Buy online Order samples
   NAARROW ELECTRONICS1,1187/4/2008 Buy online  
PXAC37KFBD/009352 665  18157        Order samples

Block diagrams/pinning

Technical documents

Support Documents

philips_i2c_logic_overview; Interface Products Business Line Specialty Logic Product Line I2C Logic Family Overview (2004-01-01)
75013474; Philips -- The Innovation Leader in Microcontrollers (2004-06-30)
75012668; Philips Microcontroller Line Card (2004-02-24)
XA_USER_GUIDE_1; XA Architecture Reference User Guide (24-Mar-97)

Parametrics/similar products

Type numberPackagePower
supply
RAM(bytes)System
Freq(MHz)
FUNCTIONADCsWatchdog
timer
I/O
pins
Operating
temp.(Cel)
TimersPWMsMemory TypeSerial InterfacesExternal InterruptProgram SecuritySeriesNo. of PinsClock TypeMemory Size(kBits)Operating Frequency(MHz)Reset Active Low or High
PXAC37KFA/00SOT187-2
(PLCC44)
4.5~5.5 1024 0~32 16-bit XA uController - yes 32 -40~85 3 x 16-bit - OTP UART
CAN
SPI
3 yes XA (eXtended Architecture) 44 n/a 32K 0~32 Low
PXAC37KFBD/00SOT389-1
(LQFP44)
4.5~5.5 1024 0~32 16-bit XA uController - yes 32 -40~85 3 x 16-bit - OTP UART
CAN
SPI
3 yes XA (eXtended Architecture) 44 n/a 32K 0~32 Low

Similar products

XA-C3 links to the similar products page containing an overview of products that are similar in function or related to the type number(s) as listed on this page. The similar products page includes products from the same catalog tree(s), relevant selection guides and products from the same functional category.

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