The UJA1167 is a mini high-speed CAN System Basis Chip (SBC) containing an ISO 11898-2/5 compliant HS-CAN transceiver and an integrated 5 V/100 mA supply for a microcontroller. It also features a watchdog and a Serial Peripheral Interface (SPI). The UJA1167 can be operated in very low-current Standby and Sleep modes with bus and local wake-up capability and supports ISO 11898-6 compliant autonomous CAN biasing. The microcontroller supply is switched off in Sleep mode. The UJA1167TK version contains a battery-related high-voltage output (INH) for controlling an external voltage regulator, while the UJA1167TK/VX is equipped with a 5 V sensor supply (VEXT).
The UJA1167 implements the standard CAN physical layer as defined in the current ISO11898 standard (-2 and -5). Pending the release of the updated version of ISO11898 including CAN FD, additional timing parameters defining loop delay symmetry are included. This implementation enables reliable communication in the CAN FD fast phase at data rates up to 2 Mbit/s.
A number of configuration settings are stored in non-volatile memory, allowing the SBC to be adapted for use in a specific application. This makes it possible to configure the power-on behavior of the UJA1167 to meet the requirements of different applications.