ADC1213D105HN

Dual 12-bit ADC; 105 Msps


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The ADC1213D is a dual channel 12-bit Analog-to-Digital Converter (ADC) optimized for high dynamic performances and low power at sample rates up to 105 Msps. Pipelined architecture and output error correction ensure the ADC1213D is accurate enough to guarantee zero missing codes over the entire operating range. Supplied from a 3.3 V source for analog and a 1.8 V source for the output driver, it can output data in serial mode, because of the two lanes of differential outputs, which are compliant with the JESD204A standard.

Features and benefits

  • 2 configurable serial outputs
  • Compliant with JESD204A serial transmission standard
  • Dual channel 12-bit pipelined ADC core
  • High IF capability
  • Input bandwidth, 600 MHz
  • Power-down and Sleep modes
  • Sample rate up to 105 Msps
  • SPI interface

Applications

  • Imaging systems
  • Portable instrumentation
  • Spectral analysis
  • Ultrasound equipment
  • Wireless and wired broadband communications
All information on this product information page is subject to the subsequent disclaimers:
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Demo boards

ADC1213D105W1ADC1213D105W1

ADC1213D105W1 Demo board With FPGA

ADC1213D105WOADC1213D105WO

ADC1213D105WO demoboard; compliant with Lattice, Altera, Xilinx FPGA boards through specific connectors


Parametrics of this product

SymbolParameterConditionsMinTyp/NomMaxUnit
Static characteristics
VDDAanalog supply voltage2.8533.4V
VDDDdigital supply voltage1.651.83.6V
IDDAanalog supply currentfclk = 125 Msps; fi = 70 MHz; VDDA = 3 V310mA
IDDDdigital supply currentVDDD = 1.8 V; fclk = 125 Msps; fi = 70 MHz145mA
Ptottotal power dissipationanalog supply only; fclk = 105 Msps; VDDA = 3 V; VDDD = 1.8 V1150mW
fssampling rate105Msps
Nchnumber of channels2
Nfuncnumber of functions2
Nresresolution12bit
Dynamic characteristics
SFDRspurious-free dynamic rangefi = 3 MHz85dBc
SNRsignal-to-noise ratiofi = 3 MHz69.8dBFS

Similar products

Products / Packages

Type numberOrderable part numberOrdering code (12NC)Product statusPackagePackingMarking
ADC1213D105HN/C1ADC1213D105HN/C1,59352 890 99518Volume productionSOT684-7
(HVQFN56) 		Reel Dry Pack, SMD, 13"Standard Marking
ADC1213D105HN/C1ADC1213D105HN/C1/59352 890 99551Volume productionSOT684-7
(HVQFN56) 		Tray Dry Pack, Bakeable, SingleStandard Marking

Quality, reliability & chemical content

Type numberOrderable part numberChemical contentRoHSLeadfree conversion dateRHFIFR (FIT)MTBF (hours)MSLMSL LF
ADC1213D105HN/C1ADC1213D105HN/C1,5ADC1213D105HN/C1Always Pb-free33
ADC1213D105HN/C1ADC1213D105HN/C1/5ADC1213D105HN/C1Always Pb-free33
Quality and reliability disclaimer

Quality and reliability disclaimer

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NXP Semiconductors is providing this data for your convenience only. Please note however that NO WARRANTY, REPRESENTATION, GUARANTEE OR LEGALLY BINDING PRODUCT DESCRIPTION is provided by publishing this informational data, nor does NXP Semiconductors acknowledge or accept any liability related thereto. The documentation and data on NXP Semiconductors products can be found in the data sheets as officially published by NXP Semiconductors. For all purchase of products from NXP Semiconductors the NXP Semiconductors' General Terms and Conditions of Commercial Sale will apply.

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Documentation for this product

If you have any questions related to this product please contact our support team via e-mail: dataconverter-support@nxp.com. Thank you for your cooperation.

TypeFormatTitleDate
Data sheetpdfDual 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; serial JESD204A interface (v.7.0)2011-06-09
Application notepdfInterconnection between JESD204A compliant devices (v.2.0)2010-09-24
Application notepdfR_10002 Technical analysis of the JEDEC JESD204A data converter interface (v.1.0)2010-08-23
Application notepdfR_10002 Technical analysis of the JEDEC JESD204A data converter interface Japanese (v.1.1)2010-08-30
Application notepdfR_10002 Technical analysis of the JEDEC JESD204A data converter interface Chinese (v.1.1)2010-08-30
BrochurepdfYour partner in Mobile Communication Infrastructure design; High Performance RF for wireless infrastructure (v.1.0)2011-05-23
Design toolshtmlXilinx JESD204B v1.1 LogiCORE IP core (v.1.0)2011-12-07
LeafletpdfDual-channel ADCs with JESD204A-compliant outputs for wireless and industrial; NXP dual 11, 12, 14, 16 bits ADC: ADC1113D series, ADC1213D series, ADC1413D series, ADC1613D series (v.2.0)2010-06-01
LeafletpdfSingle-channel ADC with input buffer (v.1.0)2010-09-13
Other typepdfThe JESD204A interface - The key to broadband wireless system miniaturizationminiaturization - NXP and Xilinx (v.1.0)2010-12-15
ReportpdfTechnical analysis of the JEDEC JESD204A data converter interface (v.2.1)2011-10-14
ReportpdfPower consumption benefits of JESD204 serial interface (v.1.0)2010-12-23
Selection guidepdfDemoboards for high-speed converters (v.1.0)2010-05-01
Selection guidepdfNXP high-speed ADC/DAC selection guide (v.1.0)2011-12-14

Ordering & availability

Type numberOrdering code(12NC)Orderable part numberRegionDistributorIn stockOrder quantityInventory dateBuy onlineSamples
ADC1213D105HN/C19352 890 99518ADC1213D105HN/C1,5       
ADC1213D105HN/C19352 890 99551ADC1213D105HN/C1/5NADIGI-KEY CORPORATION2605/24/2012Buy onlinenot available

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If you do not have a direct account with NXP our network of global and regional distributors is available and equipped to support you with NXP samples. As a NXP customer you also have the option to order samples via our sales organisation.

Demo boards

ADC1213D105W1
ADC1213D105W1

ADC1213D105W1 Demo board With FPGA

ADC1213D105WO
ADC1213D105WO

ADC1213D105WO demoboard; compliant with Lattice, Altera, Xilinx FPGA boards through specific connectors

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