Ultra-low power small footprint logic solutions

The advanced ultra-low power (AUP) logic family provides ultra-low power, small footprint logic solutions for use in 1.8 V and mixed 1.8 V / 3.3 V applications

The AUP family is the industry standard family for portable applications. It is manufactured in a CMOS process resulting in lower static and dynamic power dissipation. It’s 3.6 V tolerance, low-threshold inputs (option) and IOFF features make it suitable for use in mixed 1.8 V / 3.3 V and partial power-down applications. The family is fully specified from 1.1 V to 3.6 V and over for industrial and automotive operating temperatures.

The product portfolio includes low pin count single, dual and triple gate functions as well as configurable logic. AUP is available in leaded and leadless PicoGate packages.

Table 1. AUP logic family characteristics

Supply voltage

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

Input characteristics

Schmitt trigger

Schmitt action*

Low threshold




Output characteristics**

standard output

* Standard inputs have Schmitt action (small hysteresis) to improve noise immunity.

** For open-drain outputs refer only to the IOL curves.


  • Very low dynamic power dissipation (CPD)
  • Wide VCC from 0.8 V to 3.6 V
  • Schmitt trigger action provide high noise immunity
  • Superior ESD protection
  • Wide operating temperature of -40 °C to +125 °C
  • tPD of 3.2 ns and IOL of 2.2 mA at 1.8 V VCC
  • Leaded and Leadless PicoGate packaging

Target Applications

  • Mobile phones
  • PDAs
  • Digital cameras
  • Media players
  • Portable medical devices
  • Other hand-held, power-sensitive applications