How the I²C-Bus works
![[MBC-645]](images/mbc645.jpg)
Any I²C device can be attached to an I²C-bus and every device can talk with any master, passing information back and forth. There needs to be at least one master (e.g., microcontroller or DSP) on the bus but there can be more than one, with all masters having equal priority. Devices can be easily added to and removed from the I²C-bus.
![[MBC-631]](images/mbc631.jpg)
Total bus capacitance needs to be less than 400 pF (e.g., about 20-30 devices or 10 m of trace) to respect rise and fall time requirements. Each device must be able to drive up to 3 mA for a logic low level of 0.4 mA on an open drain bus with pull-ups in the range of 2 K to 10 K ohms. Bi-directional I²C bus buffers are available that isolate the capacitance on different legs of the bus, allowing larger (e.g., 2000 pF) and longer (e.g., 2000 m) buses.
Each device has a unique 7-bit I²C address so that the master knows specifically whom they are communicating with. Typically the four most significant bits are fixed and assigned to specific categories of devices (e.g. 1010 is assigned to serial EEPROMs). The three less significant bits (e.g., A2, A1 and A0) are programmable through hardware address pins allowing up to eight different I²C address combinations and therefore allowing up to eight of that type of device to operate on the same I²C-bus. These pins are held high to VCC (1) or held low to GND (0). 7-bit addressing allows up to 128 devices on the same bus but some of these addresses are reserved for special commands so the practical limit is around 120.
I²C-Bus Terminology
Transmitter - the device that sends data to the bus. A transmitter can either be a device that puts data on the bus on its own accord
(a 'master-transmitter'), or in response to a request from the master (a 'slave-transmitter').
Receiver - the device that receives data from the bus. A receiver can either be a device that receives data on its own request
(a 'master-receiver), or in response to a request from the master (a 'slave-receiver).
Master - the component that initializes a transfer (Start command), generates the clock (SCL) signal and terminates the transfer
(Stop command). A master can be either a transmitter or a receiver.
Slave - the device addressed by the master. A slave can be either receiver or transmitter.
Multi-master - the ability for more than one master to co-exist on the bus at the same time without collision or data loss. Typically
"bit-banged" software implemented masters are not multi-master capable. Parallel to I²C bus controllers provide an easy way to add
a multi-master hardware I²C port to DSPs and ASICs.
Arbitration - the prearranged procedure that authorizes only one master at a time to take control of the bus.
Synchronization - the prearranged procedure that synchronizes the clock signals provided by two or more masters.
SDA - data signal line (Serial DAta)
SCL - clock signal line (Serial CLock)
I²C address of the targeted device is sent in the 1st byte and the lest significant bit of this initial byte indicates if the master is going to send (write) or receive (read) data from the receiver, called the slave device. Each transmission sequence must begin with the Start condition and end with the Stop or ReStart condition. If there are two masters on the same I²C-bus, there is an arbitration procedure if both try to take control of the bus at the same time by generating the Start command at the same time. Once a master (e.g., microcontroller) has control of the bus, no other master can take control until the first master sends a Stop condition and places the bus in an idle state.
Terminology for Bus Transfer
F (FREE) - the bus is free or idle; the data line SDA and the SCL clock are both in the high state.
S (START) or R (RESTART) - data transfer begins with a Start condition. The level of the SDA data line changes from high to low, while the
SCL clock line remains high. When this occurs, the bus becomes 'busy'.
C (CHANGE) - while the SCL clock line is low, the data bit to be transferred can be applied to the SDA data line by a transmitter. During
this time, SDA may change its state, as long as the SCL line remains low.
D (DATA) - a high or low bit of information on the SDA data line is valid during the high level of the SCL clock line. This level must be
kept stable during the entire time that the clock remains high to avoid misinterpretation as a Start or Stop condition.
P (STOP) - data transfer is terminated by a Stop condition. This occurs when the level on the SDA data line passes from the low state to
the high state, while the SCL clock line remains high. When the data transfer has been terminated, the bus is free once again.
Level-shifting I²C
As new I²C devices are operating at various voltage levels, Philips Semiconductors developed a fully bi-directional data transfer circuit for I²C-devices operating from different supply voltages for almost no additional design-in effort or cost. The simple addition of two low-cost transistors, placed between the different voltage level sections of the I²C-bus, separates and transfers the logic voltage levels of the bus lines on either side of the level-shifter. This set-up also allows the level-shifter to be used to isolate a section of powered-down devices from the bus, allowing powered I²C devices to operate normally. These level-shifting functions can also be done with low cost level shifting bus buffer or GTL translator devices. The I²C-bus specification has been extended for devices operating below 2.7 V to ensure the I²C-bus will remain the serial bus of choice for future systems into the next century.
High-speed mode I²C-bus
Developments in high-speed serial RAMs and mixed technology telecom systems have created a demand for buses capable of operating at high speeds and with a variety of supply voltages. The I²C-bus High-speed mode (3.4 MHz) meets these needs without sacrificing its compatibility with existing Standard and Fast-mode devices or its low-cost simplicity - no special logic levels, timing or drive capability are needed. A purpose-designed bridge in a High-speed mode master allows for bi-directional communications between Fast- and Standard-mode devices within a single I²C-bus system and, if required, this master can also perform bi-directional level shifting, supporting a variety of different voltage devices. The high-speed mode is normally found only on LCD display, high bit count ADC or high capacity EEPROM devices due to the need to transfer large amount of data. Most maintenance and control applications, the typical reason to use the I²C-bus, continue to operate at 100 kHz.
10-bit I²C addressing
10-bit addressing allows the use of up to 1024 additional addresses to prevent problems with the allocation of slave addresses as the number of I²C devices rapidly expands. It does not change the format for addresses defined in the I²C-bus specification, using addresses reserved in the existing specification. 10-bit addressing does not affect the existing 7-bit addressing; allowing devices with 7-bit or 10-bit addresses to be connected to the same I²C-bus, and both types of devices can be used in Standard-, Fast- or High-speed mode systems. Most all I²C devices continue to use 7-bit addressing however as designers work around addressing concerns by using multiple I²C bus ports or multiplexers/switches to allow smaller device populations on the active bus.
I²C vs SMBus
Developed by Intel in the mid-1990s, the System Management Bus, also known as SMBus, is a popular derivative of the I²C-bus that is, in most cases, compatible with I²C. Both buses use a two-wire communication scheme and have addressable slaves. The SMBus is limited to a maximum data transfer rate of only 100 kbps, requiring special handling in systems that also use the higher transfer rates available with I²C. Other differences include timeout and minimum clock speed, voltage levels, pull-up resistor values, and current levels. New I²C devices are starting to incorporate SMBus features such as timeout that can be turned on and off depending on the application requirements.
Additional Information resources
I²C Information resources
SMBus Information resources
