Level Translating I2C-Bus Repeater

  • Not Recommended for New Designs
  • This page contains information on a product that is not recommended for new designs.

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Block Diagram

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PCA9517 Block Diagram

PCA9517 Block Diagram

PCA9517D, PCA9517DP Block Diagram

Features

Key Features

  • 2 channel, bidirectional buffer isolates capacitance and allows 400 pF on either side of the device
  • Voltage level translation from 0.9 V to 5.5 V and from 2.7 V to 5.5 V
  • Footprint and functional replacement for PCA9515/15A
  • I2C-bus and SMBus compatible
  • Active HIGH repeater enable input
  • Open-drain input/outputs
  • Lock-up free operation
  • Supports arbitration and clock stretching across the repeater
  • Accommodates Standard mode and Fast mode I2C-bus devices and multiple controllers
  • Powered-off high-impedance I2C-bus pins
  • A-side operating supply voltage range of 0.9 V to 5.5 V
  • B-side operating supply voltage range of 2.7 V to 5.5 V
  • 5 V tolerant I2C-bus and enable pins
  • 0 Hz to 400 kHz clock frequency (the maximum system operating frequency may be less than 400 kHz because of the delays added by the repeater).
  • ESD protection exceeds 2000 V HBM per JESD22-A114, 150 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101
  • Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
  • Packages offered: SO8 and TSSOP8

Part numbers include: PCA9517D, PCA9517DP.

Documentation

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Design Resources

Design Files

2 design files

Hardware

1 hardware offering

Engineering Services

2 engineering services

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