20-bit buffer/line driver, non-inverting,with 30Ohm termination resistors (3-State)
The 74ALVT162827 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. It is designed for VCC operation at 2.5 V or 3.3 V with I/O compatibility to 5 V.
The 74ALVT162827 20-bit buffers provide high performance bus interface buffering for wide data/address paths or buses carrying parity. They have NOR Output Enables (nOE1, nOE2) for maximum control flexibility.
The 74ALVT162827 is designed with 30 Ω series resistance in both the pull-up and pull-down output structures. This design reduces line noise in applications such as memory address drivers, clock drivers and bus receivers/transmitters.
|Type number||Package||Nr of pins||Package name||Product status||tpd(ns)||VCC(V)||Family||Nr of bits||Power dissipation considerations||Logic switching levels||Output drive capability(mA)||fmax(MHz)||Description||Tamb(Cel)|
|56||TSSOP56||Production||2.2||2.3 - 3.6||ALVT||20||medium||LVTTL||+/- 12||75||20-bit buffer/line driver with bus hold and 30 Ohm termination resistors (3-state)||-40~85|
|Package Version||Package Name||Package Description||Reference Codes||Issue Date|
|SOT364-1||TSSOP56||plastic thin shrink small outline package; 56 leads; body width 6.1 mm||MO-153 (JEDEC);||2003-02-19|
|Type number||Orderable part number||Chemical content||RoHS||Leadfree conversion date||RHF||IFR (FIT)||MTBF (hours)||MSL||MSL LF|
|74ALVT162827DGG||74ALVT162827DGG,11||74ALVT162827DGG||week 2, 2006||1.33||7.518796992481203E8||1||1|
|74ALVT162827DGG||74ALVT162827DGG:11||74ALVT162827DGG||week 2, 2006||1.33||7.518796992481203E8||1||1|
Sample orders normally take 2-4 days for delivery.
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