Digital decoders and demultiplexers enable interface bus width reduction.
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Digital demultiplexers for GPIO expansion and decoding
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CBTL06DP213EE
Third generation high-performance DisplayPort multiplexer
Key features and benefits
- Simple control interface
- I/O expansion
- Multiple input enable for easy expansion or independent controls
- Integrated input latch to store the address of decoder lines
- Ideal for memory chip select decoding
- Asynchronous and synchronous load options
- Overvoltage tolerant input options
- Inverting and non-inverting output options
- 3-stage outputs
- High frequency
- Can be cascaded
- AEC Q100 grade 1
Key applications
- Selection of memory banks and peripherals in display clusters
- I/O expansion for Infotainment CODECs
- Implementation of lane departure warning systems
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Descriptive summary
NXP's demultiplexers are available in multiple logic families with 1, 2, 3 and 4 input lines and 2, 4, 8 and 16 output lines reducing the bit width of interface busses. They can be used as decoders by activating one of several mutually-exclusive output lines, based on the digital code present at the binary-weighted inputs. A typical use of decoders is in memory addressing in automotive applications such as display clusters, global positioning systems and keyless entry systems; allowing several memory devices to share a common data bus by ensuring that only one memoiry device is enabled at a time
Digital decoders / demultiplexers are available in standard SO, TSSOP and leadless DQFN packages for PCB space saving. NXP's automotive digital decoders / demultiplexers are fully specified from -40°C to 125°C, and are qualified per AEC Q100 grade 1.







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