74AHC377PW

Octal D-type flip-flop with data enable; positive-edge trigger


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The 74AHC377; 74AHCT377 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.

The 74AHC377; 74AHCT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. A common clock input (CP) loads all flip-flops simultaneously when the data enable input (E) is LOW. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop. The E input is only required to be stable one set-up time prior to the LOW-to-HIGH transition for predictable operation.

For versions associated with the 74AHC377; 74AHCT377, refer to the following:

  • For the master reset version, see 74AHC273; 74AHCT273
  • For the transparent latch version, see 74AHC373; 74AHCT373
  • For the 3-state version, see 74AHC374; 74AHCT374

Features and benefits

  • Balanced propagation delays
  • All inputs have Schmitt-trigger actions
  • Inputs accept voltages higher than VCC
  • Ideal for addressable register applications
  • Data enable for address and data synchronization
  • Eight positive-edge triggered D-type flip-flops
  • Input levels:
    • For 74AHC377: CMOS level
    • For 74AHCT377: TTL level
  • ESD protection:
    • HBM EIA/JESD22-A114E exceeds 2000 V
    • MM EIA/JESD22-A115-A exceeds 200 V
    • CDM EIA/JESD22-C101C exceeds 1000 V
  • Multiple package options
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C
All information on this product information page is subject to the subsequent disclaimers:
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Show functional diagram

Block diagram: 74AHC377D, 74AHC377PW, 74AHCT377D, 74AHCT377PW
Block diagram: 74AHC377D, 74AHC377PW, 74AHCT377D, 74AHCT377PW

Parametrics of this product

Type numberPackageNr of pinsPackage nameProduct statustpd(ns)VCC(V)FamilyPower dissipation considerationsLogic switching levelsOutput drive capability(mA)fmax(MHz)DescriptionTamb(Cel)
74AHC377PWSOT360-1
(TSSOP20)		20TSSOP20Production3.92.0 - 5.5AHC(T)lowCMOS+/- 8175octal D-type flip-flop with data enable; positive-edge trigger-40~125

Package

Type numberOrderable part numberOrdering code (12NC)Product statusPackagePackingMarking
74AHC377PW74AHC377PW,1129352 679 95112Volume productionSOT360-1
(TSSOP20) 		TubeAHC377
74AHC377PW74AHC377PW,1189352 679 95118Volume productionSOT360-1
(TSSOP20) 		Reel Pack, SMD, 13"AHC377

Outline drawing

Package VersionPackage NamePackage DescriptionReference CodesIssue Date
SOT360-1TSSOP20plastic thin shrink small outline package; 20 leads; body width 4.4 mmMO-153 (JEDEC); 2003-02-19

Related documents

Wave soldering

Quality, reliability & chemical content

Type numberOrderable part numberChemical contentRoHSLeadfree conversion dateRHFIFR (FIT)MTBF (hours)MSLMSL LF
74AHC377PW74AHC377PW,11274AHC377PWweek 7, 20056.621.5105740181268883E811
74AHC377PW74AHC377PW,11874AHC377PWweek 7, 20056.621.5105740181268883E811
Quality and reliability disclaimer

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Documentation for this product

File nameTitleTypeFormatDate
74AHC_AHCT377Octal D-type flip-flop with data enable; positive-edge triggerData sheetpdf2008-06-12
AN11106Pin FMEA for AHC/AHCT familyApplication notepdf2011-11-04
AN223Ground and VCC Bounce of High-Speed Integrated CircuitsApplication notepdf2013-03-13
AN252Live Insertion Aspects of Philips Logic FamiliesApplication notepdf2013-03-13
AN212Package lead inductance considerations in high-speed applicationsApplication notepdf2013-03-13
AN10156Sorting through the low voltage logic mazeApplication notepdf2013-03-13
ahc377ahc377 IBIS modelIBIS modelibs2013-04-07

Ordering & availability

Type numberOrdering code (12NC)Orderable part numberRegionDistributorIn stockOrder quantityInventory dateBuy onlineSamples
74AHC377PW9352 679 9511274AHC377PW,112NADIGI-KEY CORPORATION1115/18/2013Buy onlinenot available
74AHC377PW9352 679 9511874AHC377PW,118NAMOUSER ELECTRONICS6905/18/2013Buy online 
   JAPANCHIP ONE STOP10005/20/2013Buy online 

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