Low-power D-type flip-flop with set and reset; positive-edge trigger
The 74AUP1G74 provides a low-power, low-voltage single positive-edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and complementary Q and Q outputs. The SD and RD are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
|Type number||Package||Nr of pins||Package name||Product status||tpd(ns)||VCC(V)||Family||Power dissipation considerations||Logic switching levels||Output drive capability(mA)||fmax(MHz)||Description||Tamb(Cel)|
|8||VSSOP8||Production||9.2||1.1 - 3.6||AUP||ultra low||CMOS||+/- 1.9||400||single D-type flip-flop with set and reset; positive-edge trigger||-40~125|
|Package Version||Package Name||Package Description||Reference Codes||Issue Date|
|SOT765-1||VSSOP8||plastic very thin shrink small outline package; 8 leads; body width 2.3 mm||MO-187 (JEDEC);||2002-06-07|
|Type number||Ordering code (12NC)||Orderable part number||Region||Distributor||In stock||Order quantity||Inventory date||Buy online||Samples|
|74AUP1G74DC||9352 807 17125||74AUP1G74DC,125||NA||DIGI-KEY CORPORATION||7,618||5/23/2013|
|EU||FUTURE ELECTRONICS UK||2,995||5/22/2013|
|ASIA||FUTURE ELECTRONICS- ASIA||2,995||5/22/2013|
|NA||AVNET EXPRESS AMERICAS||2,305||5/23/2013|
|JAPAN||CHIP ONE STOP||100||05/23/2013|
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