74AUP1G74DC

Low-power D-type flip-flop with set and reset; positive-edge trigger


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The 74AUP1G74 provides a low-power, low-voltage single positive-edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and complementary Q and Q outputs. The SD and RD are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

Features and benefits

  • Wide supply voltage range from 0.8 V to 3.6 V
  • High noise immunity
  • Complies with JEDEC standards:
    • JESD8-12 (0.8 V to 1.3 V)
    • JESD8-11 (0.9 V to 1.65 V)
    • JESD8-7 (1.2 V to 1.95 V)
    • JESD8-5 (1.8 V to 2.7 V)
    • JESD8-B (2.7 V to 3.6 V)
  • ESD protection:
    • HBM JESD22-A114F Class 3A exceeds 5000 V
    • MM JESD22-A115-A exceeds 200 V
    • CDM JESD22-C101E exceeds 1000 V
  • Low static power consumption; ICC = 0.9 μA (maximum)
  • Latch-up performance exceeds 100 mA per JESD 78 Class II
  • Inputs accept voltages up to 3.6 V
  • Low noise overshoot and undershoot < 10 % of VCC
  • IOFF circuitry provides partial power-down mode operation
  • Multiple package options
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C
All information on this product information page is subject to the subsequent disclaimers:
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Show functional diagram

Block diagram: 74AUP1G74DC, 74AUP1G74GD, 74AUP1G74GM, 74AUP1G74GT
Block diagram: 74AUP1G74DC, 74AUP1G74GD, 74AUP1G74GM, 74AUP1G74GT

Parametrics of this product

Type numberPackageNr of pinsPackage nameProduct statustpd(ns)VCC(V)FamilyPower dissipation considerationsLogic switching levelsOutput drive capability(mA)fmax(MHz)DescriptionTamb(Cel)
74AUP1G74DCSOT765-1
(VSSOP8)		8VSSOP8Production9.21.1 - 3.6AUPultra lowCMOS+/- 1.9400single D-type flip-flop with set and reset; positive-edge trigger-40~125

Package

Type numberOrderable part numberOrdering code (12NC)Product statusPackagePackingMarking
74AUP1G74DC74AUP1G74DC,1259352 807 17125Volume productionSOT765-1
(VSSOP8) 		Reel Pack, Reverse, Reversep74

Outline drawing

Package VersionPackage NamePackage DescriptionReference CodesIssue Date
SOT765-1VSSOP8plastic very thin shrink small outline package; 8 leads; body width 2.3 mmMO-187 (JEDEC); 2002-06-07

Related documents

Reflow soldering

Quality, reliability & chemical content

Type numberOrderable part numberChemical contentRoHSLeadfree conversion dateRHFIFR (FIT)MTBF (hours)MSLMSL LF
74AUP1G74DC74AUP1G74DC,12574AUP1G74DCAlways Pb-free3.293.03951367781155E811
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Documentation for this product

File nameTitleTypeFormatDate
74AUP1G74Low-power D-type flip-flop with set and reset; positive-edge triggerData sheetpdf2013-01-23
AN10161PicoGate Logic footprintsApplication notepdf2002-10-30
AN11052Pin FMEA for AUP familyApplication notepdf2011-05-06
AN10156Sorting through the low voltage logic mazeApplication notepdf2013-03-13
aup1g74aup1g74 IBIS modelIBIS modelibs2013-04-07

Ordering & availability

Type numberOrdering code (12NC)Orderable part numberRegionDistributorIn stockOrder quantityInventory dateBuy onlineSamples
74AUP1G74DC9352 807 1712574AUP1G74DC,125NADIGI-KEY CORPORATION7,6185/23/2013Buy online 
   NAFUTURE ELECTRONICS2,9955/22/2013Buy online 
   EUFUTURE ELECTRONICS UK2,9955/22/2013Buy online 
   ASIAFUTURE ELECTRONICS- ASIA2,9955/22/2013Buy online 
   NAAVNET EXPRESS AMERICAS2,3055/23/2013Buy online 
   JAPANCHIP ONE STOP10005/23/2013Buy online 

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