Low-power D-type flip-flop; positive-edge trigger
The 74AUP1G79 provides the single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one setup time prior to the LOW-to-HIGH clock transition for predictable operation.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
|Type number||Package||Nr of pins||Package name||Product status||tpd(ns)||VCC(V)||Family||Power dissipation considerations||Logic switching levels||Output drive capability(mA)||fmax(MHz)||Description||Tamb(Cel)|
|5||X2SON5||Production||9.1||1.1 - 3.6||AUP||ultra low||CMOS||+/- 1.9||400||single D-type flip-flop; positive-edge trigger||-40~125|
|Type number||Orderable part number||Ordering code (12NC)||Product status||Package||Packing||Marking|
|74AUP1G79GX||74AUP1G79GX,125||9352 983 65125||Volume production||SOT1226|
|Reel Pack, Reverse, Reverse||pP|
|Package Version||Package Name||Package Description||Reference Codes||Issue Date|
|SOT1226||X2SON5||plastic thermal enhanced extremely thin small outline package; no leads; 5 terminals||2012-04-18|
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