74LVC1G175GS

Single D-type flip-flop with reset; positive edge trigger


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The 74LVC1G175 is a low-power, low-voltage single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output.

The master reset (MR) is an asynchronous active LOW input and operates independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.

The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times.

Features and benefits

  • Wide supply voltage range from 1.65 V to 5.5 V
  • 5 V tolerant inputs for interfacing with 5 V logic
  • High noise immunity
  • Complies with JEDEC standard:
    • JESD8-7 (1.65 V to 1.95 V)
    • JESD8-5 (2.3 V to 2.7 V)
    • JESD8B/JESD36 (2.7 V to 3.6 V)
  • ESD protection:
    • HBM JESD22-A114F exceeds 2000 V
    • MM JESD22-A115-A exceeds 200 V
  • ±24 mA output drive (VCC = 3.0 V)
  • CMOS low power consumption
  • Latch-up performance exceeds 250 mA
  • Direct interface with TTL levels
  • Inputs accept voltages up to 5 V
  • Multiple package options
  • Specified from –40 ℃ to +85 ℃ and –40 ℃ to +125 ℃
All information on this product information page is subject to the subsequent disclaimers:
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Parametrics of this product

Type numberPackageNr of pinsPackage nameProduct statustpd(ns)VCC(V)FamilyPower dissipation considerationsLogic switching levelsOutput drive capability(mA)fmax(MHz)DescriptionTamb(Cel)
74LVC1G175GSSOT1202
(XSON6)		6XSON6Production3.11.65 - 5.5LVClowCMOS/LVTTL+/- 32300single D flip-flop with reset; positive-edge trigger-40~125

Package

Type numberOrderable part numberOrdering code (12NC)Product statusPackagePackingMarking
74LVC1G175GS74LVC1G175GS,1329352 929 05132Volume productionSOT1202
(XSON6) 		YT

Outline drawing

Package VersionPackage NamePackage DescriptionReference CodesIssue Date
SOT1202XSON6extremely thin small outline package; no leads; 6 terminals2010-04-06

Related documents

Other type

Quality, reliability & chemical content

Type numberOrderable part numberChemical contentRoHSLeadfree conversion dateRHFIFR (FIT)MTBF (hours)MSLMSL LF
74LVC1G175GS74LVC1G175GS,13274LVC1G175GSAlways Pb-free3.872.5839793281653747E811
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Documentation for this product

File nameTitleTypeFormatDate
74LVC1G175Single D-type flip-flop with reset; positive edge triggerData sheetpdf2011-12-19
AN10343MicroPak soldering informationApplication notepdf2010-12-30
AN11009Pin FMEA for LVC familyApplication notepdf2011-02-04
AN212Package lead inductance considerations in high-speed applicationsApplication notepdf2013-03-13
AN10156Sorting through the low voltage logic mazeApplication notepdf2013-03-13
lvc1g17lvc1g17 IBIS modelIBIS modelibs2013-04-07
lvc1g175lvc1g175 IBIS modelIBIS modelibs2013-04-07

Ordering & availability

Type numberOrdering code (12NC)Orderable part numberRegionDistributorIn stockOrder quantityInventory dateBuy onlineSamples
74LVC1G175GS9352 929 0513274LVC1G175GS,132ASIAElement 140123/05/2013Buy onlinenot available

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