Single D-type flip-flop with reset; positive edge trigger
The 74LVC1G175 is a low-power, low-voltage single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output.
The master reset (MR) is an asynchronous active LOW input and operates independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.
The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times.
|Type number||Package||Nr of pins||Package name||Product status||tpd(ns)||VCC(V)||Family||Power dissipation considerations||Logic switching levels||Output drive capability(mA)||fmax(MHz)||Description||Tamb(Cel)|
|6||XSON6||Production||3.1||1.65 - 5.5||LVC||low||CMOS/LVTTL||+/- 32||300||single D flip-flop with reset; positive-edge trigger||-40~125|
|Type number||Orderable part number||Ordering code (12NC)||Product status||Package||Packing||Marking|
|74LVC1G175GS||74LVC1G175GS,132||9352 929 05132||Volume production||SOT1202|
|Package Version||Package Name||Package Description||Reference Codes||Issue Date|
|SOT1202||XSON6||extremely thin small outline package; no leads; 6 terminals||2010-04-06|
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