
74LVC74APW
Dual D-type flip-flop with set and reset; positive-edge trigger
The 74LVC74A is a dual edge triggered D-type flip-flop with individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs.
The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse. The nD inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation.
Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times.
Dual D-type flip-flop with set and reset; positive-edge trigger
Low-Voltage CMOS (LVC)
| Type number | Package | Nr of pins | Package name | Product status | tpd(ns) | VCC(V) | Family | Power dissipation considerations | Logic switching levels | Output drive capability(mA) | fmax(MHz) | Description | Tamb(Cel) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74LVC74APW | SOT402-1 (TSSOP14) | 14 | TSSOP14 | Production | 2.5 | 1.2 - 3.6 | LVC | low | CMOS/LVTTL | +/- 24 | 250 | dual D-type flip-flop with set and reset; positive-edge trigger | -40~125 |
| Type number | Orderable part number | Ordering code (12NC) | Product status | Package | Packing | Marking |
|---|---|---|---|---|---|---|
| 74LVC74APW | 74LVC74APW,112 | 9352 607 36112 | Volume production | SOT402-1 (TSSOP14) | Tube | LVC74A |
| 74LVC74APW | 74LVC74APW,118 | 9352 607 36118 | Volume production | SOT402-1 (TSSOP14) | Reel Pack, SMD, 13" | LVC74A |
| Package Version | Package Name | Package Description | Reference Codes | Issue Date |
|---|---|---|---|---|
| SOT402-1 | TSSOP14 | plastic thin shrink small outline package; 14 leads; body width 4.4 mm | MO-153 (JEDEC); | 2003-02-18 |
| Type number | Orderable part number | Chemical content | RoHS | Leadfree conversion date | RHF | IFR (FIT) | MTBF (hours) | MSL | MSL LF |
|---|---|---|---|---|---|---|---|---|---|
| 74LVC74APW | 74LVC74APW,112 | 74LVC74APW | week 10, 2005 | 3.87 | 2.5839793281653747E8 | 1 | 1 | ||
| 74LVC74APW | 74LVC74APW,118 | 74LVC74APW | week 10, 2005 | 3.87 | 2.5839793281653747E8 | 1 | 1 |
| File name | Title | Type | Format | Date |
|---|---|---|---|---|
| 74LVC74A | Dual D-type flip-flop with set and reset; positive-edge trigger | Data sheet | 2012-11-20 | |
| AN240 | Interfacing 3 Volt and 5 Volt Applications | Application note | 1995-09-15 | |
| AN263 | Power considerations when using CMOS and BiCMOS logic devices | Application note | 2002-02-05 | |
| AN11009 | Pin FMEA for LVC family | Application note | 2011-02-04 | |
| AN212 | Package lead inductance considerations in high-speed applications | Application note | 2013-03-13 | |
| AN10156 | Sorting through the low voltage logic maze | Application note | 2013-03-13 | |
| lvc74a | lvc74a IBIS model | IBIS model | ibs | 2013-04-07 |
| lvc | lvc Spice model | SPICE model | zip | 2013-05-07 |
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