74AHC(T)74

Dual D-type flip-flop with set and reset; positive-edge trigger


The 74AHC74; 74AHCT74 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.

The 74AHC74; 74AHCT74 is a dual positive-edge triggered, D-type flip-flop with individual data inputs (D), clock inputs (CP), set inputs (SD) and reset inputs (RD). It also has complementary outputs (Q and Q).

The set and reset are asynchronous active LOW inputs that operate independent of the clock input. Information on the data input is transferred to the Q output on the LOW to HIGH transition of the clock pulse. The data inputs must be stable one set-up time prior to the LOW to HIGH clock transition for predictable operation.

Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

Features and benefits

  • Balanced propagation delays
  • All inputs have Schmitt-trigger actions
  • Inputs accept voltages higher than VCC
  • Input levels:
    • For 74AHC74: CMOS level
    • For 74AHCT74: TTL level
  • ESD protection:
    • HBM EIA/JESD22-A114E exceeds 2000 V
    • MM EIA/JESD22-A115-A exceeds 200 V
    • CDM EIA/JESD22-C101C exceeds 1000 V
  • Multiple package options
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C

Show functional diagram

Block diagram: 74AHC74BQ, 74AHC74D, 74AHC74PW, 74AHCT74BQ, 74AHCT74D, 74AHCT74PW, 74LVC2G74DC, 74LVC2G74DP, 74LVC2G74GD, 74LVC2G74GM, 74LVC2G74GT
Block diagram: 74AHC74BQ, 74AHC74D, 74AHC74PW, 74AHCT74BQ, 74AHCT74D, 74AHCT74PW, 74LVC2G74DC, 74LVC2G74DP, 74LVC2G74GD, 74LVC2G74GM, 74LVC2G74GT

Documentation for this product

File nameTitleTypeFormatDate
74AHC_AHCT74Dual D-type flip-flop with set and reset; positive-edge triggerData sheetpdf2008-06-09
AN223Ground and VCC Bounce of High-Speed Integrated CircuitsApplication notepdf2013-03-13
AN212Package lead inductance considerations in high-speed applicationsApplication notepdf2013-03-13
75017511Voltage translation: How to manage mixed-voltage designs with NXP level translatorsBrochurepdf2014-05-20
ahc74ahc74 IBIS modelIBIS modelibs2013-04-07
ahct74ahct74 IBIS modelIBIS modelibs2013-04-07

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Models

TitleTypeDate
ahc74 IBIS modelIBIS model2013-04-07
ahct74 IBIS modelIBIS model2013-04-07

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{"subtitle":"Dual D-type flip-flop with set and reset; positive-edge trigger","category":["Logic","Flip-flops","D-type flip-flops",""],"basictype":["74AHC(T)74"]}

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