74LVC2G38GM

Dual 2-input NAND gate; open drain


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The 74LVC2G38 provides a 2-input NAND function.

The outputs of the 74LVC2G38 devices are open-drain and can be connected to other open-drain outputs to implement active-LOW, wired-OR or active-HIGH wired-AND functions.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

Features and benefits

  • Wide supply voltage range from 1.65 V to 5.5 V
  • 5 V tolerant outputs for interfacing with 5 V logic
  • High noise immunity
  • Complies with JEDEC standard:
    • JESD8-7 (1.65 V to 1.95 V)
    • JESD8-5 (2.3 V to 2.7 V)
    • JESD8B/JESD36 (2.7 V to 3.6 V)
  • ESD protection:
    • HBM EIA/JESD22-A114F exceeds 2000 V
    • MM EIA/JESD22-A115-A exceeds 200 V
  • ±24 mA output drive (VCC = 3.0 V)
  • CMOS low power consumption
  • Open-drain outputs
  • Latch-up performance exceeds 250 mA
  • Direct interface with TTL levels
  • Inputs accept voltages up to 5 V
  • Multiple package options
  • Specified from -40 ℃ to +85 ℃ and -40 ℃ to +125 ℃
All information on this product information page is subject to the subsequent disclaimers:
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Show functional diagram

Block diagram: 74AUP2G38DC, 74AUP2G38GM, 74AUP2G38GT, 74LVC2G38DC, 74LVC2G38DP, 74LVC2G38GD, 74LVC2G38GM, 74LVC2G38GT
Block diagram: 74AUP2G38DC, 74AUP2G38GM, 74AUP2G38GT, 74LVC2G38DC, 74LVC2G38DP, 74LVC2G38GD, 74LVC2G38GM, 74LVC2G38GT
Block diagram: 74LVC2G38DC, 74LVC2G38DP, 74LVC2G38GD, 74LVC2G38GM, 74LVC2G38GT
Block diagram: 74LVC2G38DC, 74LVC2G38DP, 74LVC2G38GD, 74LVC2G38GM, 74LVC2G38GT

Parametrics of this product

Type numberPackageNr of pinsPackage nameProduct statustpd(ns)VCC(V)FamilyNr of bitsPower dissipation considerationsLogic switching levelsOutput drive capability(mA)fmax(MHz)DescriptionTamb(Cel)
74LVC2G38GMSOT902-1
(XQFN8U)		8XQFN8UProduction2.11.65 - 5.5LVC2lowCMOS/LVTTL32175dual 2-input NAND gate; open-drain-40~125

Package

Type numberOrderable part numberOrdering code (12NC)Product statusPackagePackingMarking
74LVC2G38GM74LVC2G38GM,1259352 772 41125Volume productionSOT902-1
(XQFN8U) 		Reel Pack, Reverse, ReverseY38

Outline drawing

Package VersionPackage NamePackage DescriptionReference CodesIssue Date
SOT902-1XQFN8Uplastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mmMO-255 (JEDEC); 2007-11-14

Related documents

Reflow soldering

Quality, reliability & chemical content

Type numberOrderable part numberChemical contentRoHSLeadfree conversion dateRHFIFR (FIT)MTBF (hours)MSLMSL LF
74LVC2G38GM74LVC2G38GM,12574LVC2G38GMAlways Pb-free3.872.5839793281653747E811
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Documentation for this product

File nameTitleTypeFormatDate
74LVC2G38Dual 2-input NAND gate; open drainData sheetpdf2013-04-08
AN10161PicoGate Logic footprintsApplication notepdf2002-10-30
AN11009Pin FMEA for LVC familyApplication notepdf2011-02-04
AN212Package lead inductance considerations in high-speed applicationsApplication notepdf2013-03-13
AN10156Sorting through the low voltage logic mazeApplication notepdf2013-03-13
lvc2g38lvc2g38 IBIS modelIBIS modelibs2013-04-07

Ordering & availability

Type numberOrdering code (12NC)Orderable part numberRegionDistributorIn stockOrder quantityInventory dateBuy onlineSamples
74LVC2G38GM9352 772 4112574LVC2G38GM,125ASIAElement 14100116/05/2013Buy online 
   JAPANCHIP ONE STOP10005/16/2013Buy online 

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