74AUP1T34GW

Low-power dual supply translating buffer


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The 74AUP1T34 provides a single buffer with two separate supply voltages. Input A is designed to track VCC(A). Output Y is designed to track VCC(Y). Both, VCC(A) and VCC(Y) accepts any supply voltage from 1.1 V to 3.6 V. This feature allows universal low voltage interfacing between any of the 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V voltage nodes.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 1.1 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 1.1 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

Features and benefits

  • Wide supply voltage range from 1.1 V to 3.6 V
  • High noise immunity
  • Complies with JEDEC standards:
    • JESD8-7 (1.2 V to 1.95 V)
    • JESD8-5 (1.8 V to 2.7 V)
    • JESD8-B (2.7 V to 3.6 V)
  • ESD protection:
    • HBM JESD22-A114F Class 3A exceeds 5000 V
    • MM JESD22-A115-A exceeds 200 V
    • CDM JESD22-C101E exceeds 1000 V
  • Wide supply voltage range:
    • VCC(A) : 1.1 V to 3.6 V
    • VCC(Y) : 1.1 V to 3.6 V
  • Low static power consumption; ICC = 0.9 µA (maximum)
  • Each port operates over the full 1.1 V to 3.6 V power supply range
  • Latch-up performance exceeds 100 mA per JESD 78 Class II
  • Inputs accept voltages up to 3.6 V
  • Low noise overshoot and undershoot < 10 % of VCC
  • IOFF circuitry provides partial Power-down mode operation
  • Multiple package options
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C
All information on this product information page is subject to the subsequent disclaimers:
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Show functional diagram

Block diagram: 74AUP1T34GF, 74AUP1T34GM, 74AUP1T34GW
Block diagram: 74AUP1T34GF, 74AUP1T34GM, 74AUP1T34GW

Parametrics of this product

Type numberPackageNr of pinsPackage nameProduct statustpd(ns)FamilyNr of bitsVCC(A)(V)VCC(B)(V)Power dissipation considerationsLogic switching levelsOutput drive capability(mA)DescriptionTamb(Cel)
74AUP1T34GWSOT353-1
(TSSOP5)		5TSSOP5Production15.2AUP11.1 - 3.61.1 - 3.6ultra lowCMOS+/- 1.9single dual supply translating buffer-40~125

Package

Type numberOrderable part numberOrdering code (12NC)Product statusPackagePackingMarking
74AUP1T34GW74AUP1T34GW,1259352 805 16125Volume productionSOT353-1
(TSSOP5) 		Reel Pack, Reverse, ReversepQ

Outline drawing

Package VersionPackage NamePackage DescriptionReference CodesIssue Date
SOT353-1TSSOP5plastic thin shrink small outline package; 5 leads; body width 1.25 mmSC-88A (EIAJ); MO-203 (JEDEC); 2003-02-19

Related documents

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Quality, reliability & chemical content

Type numberOrderable part numberChemical contentRoHSLeadfree conversion dateRHFIFR (FIT)MTBF (hours)MSLMSL LF
74AUP1T34GW74AUP1T34GW,12574AUP1T34GWAlways Pb-free11
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Documentation for this product

File nameTitleTypeFormatDate
74AUP1T34Low-power dual supply translating bufferData sheetpdf2012-03-16
AN10161PicoGate Logic footprintsApplication notepdf2002-10-30
AN10156Sorting through the low voltage logic mazeApplication notepdf2013-03-13
aup1t34aup1t34 IBIS modelIBIS modelibs2013-04-07
75017085Application guide: Flat-panel TV setsLine cardpdf2012-03-13
75017090Application guide; Portable devices and mobile handsetsSelection guidepdf2012-03-13

Ordering & availability

Type numberOrdering code (12NC)Orderable part numberRegionDistributorIn stockOrder quantityInventory dateBuy onlineSamples
74AUP1T34GW9352 805 1612574AUP1T34GW,125NADIGI-KEY CORPORATION8,8265/23/2013Buy online 
   NAARROW ELECTRONICS3,0005/23/2013Buy online 
   EUARROW EUROPE3,0005/23/2013Buy online 
   NANEWARK/ELEMENT142,8785/23/2013Buy online 
   EUFarnell Europe2,878105/23/2013Buy online 
   NAAVNET EXPRESS AMERICAS2,3105/23/2013Buy online 
   ASIAElement 14100123/05/2013Buy online 
   JAPANCHIP ONE STOP9505/23/2013Buy online 

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