74AUP1T1326GT

Low-power dual supply buffer/line driver; 3-state


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The 74AUP1T1326 is a high-performance, low-power, low-voltage, single-bit, dual supply buffer/line driver with output enable circuitry. The 74AUP1T1326 is designed for logic-level translation applications and combines the functions of the 74AUP1G32 and 74AUP1G126. The buffer/line driver is controlled by two output enable Schmitt trigger inputs (1OE and 2OE) through an OR-gate. The output enable inputs accept standard input signals and are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. The output of the OR-gate is also available at output 1Y.

Features and benefits

  • Complies with JEDEC standard: JESD8-5 (1.8 V to 2.7 V)
  • Complies with JEDEC standard: JESD8-7 (1.2 V to 1.95 V)
  • Complies with JEDEC standard: JESD8-B (2.7 V to 3.6 V)
  • ESD protection: CDM JESD22-C101C exceeds 1000 V
  • ESD protection: HBM JESD22-A114E Class 2A exceeds 2000 V
  • ESD protection: MM JESD22-A115-A exceeds 200 V
  • High noise immunity
  • IOFF circuitry provides partial Power-down mode operation
  • Inputs accept voltages up to 3.6 V
  • Latch-up performance exceeds 100 mA per JESD 78 Class II
  • Low noise overshoot and undershoot < 10 % of VCC
  • Low static power consumption; ICC = 0.9 μA (maximu)
  • Multiple package options
  • Specified from 40 °C to +85 °C
  • Wide supply voltage range: VCC(A): 1.1 V to 3.6 V
  • Wide supply voltage range: VCC(B): 1.1 V to 3.6 V
All information on this product information page is subject to the subsequent disclaimers:
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Parametric search

Parametrics of this product

SymbolParameterConditionsMinTyp/NomMaxUnit
VCCsupply voltage1.13.6V
VIinput voltage03.6V
Tambambient temperature-4025125°C
Δt/ΔVinput transition rise and fall rateVCC is the supply voltage associated with an input pin; 1.1 V < VCC < 3.6 V; input A200ns/V
Δt/ΔVinput transition rise and fall rateinput nOE; VCC is the supply voltage associated with an input pin; 1.1 V < VCC < 3.6 V0.03s/V
CIinput capacitance0.9pF
CPDpower dissipation capacitance3pF
tPDpropagation delayTamb = 25 °C; VCC = 1.8 V2.43.54.9ns

Similar products

Products / Packages

Type numberOrderable part numberOrdering code (12NC)Product statusPackagePackingMarking
74AUP1T1326GT74AUP1T1326GT,1159352 860 82115Volume productionSOT833-1
(XSON8) 		Reel Pack, SMD, 7"Standard Marking

Pinning information

PinSymbolDescriptionSimplified outlineGraphic symbol
1VCC(B)supply voltage BPin configuration SOT833-1 (XSON8)R_pd = Internal pull-down resistor
2Adata input
3VCC(A)supply voltage A
4GNDground (0 V)
51OEoutput enable input (Schmitt trigger input)
62OEoutput enable input (Schmitt trigger input)
71Ydata output
82Ydata output

Quality, reliability & chemical content

Type numberOrderable part numberChemical contentRoHSLeadfree conversion dateRHFIFR (FIT)MTBF (hours)MSLMSL LF
74AUP1T1326GT74AUP1T1326GT,11574AUP1T1326GTAlways Pb-free11
Quality and reliability disclaimer

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Documentation for this product

TypeFormatTitleDate
Data sheetpdfLow-power dual supply buffer/line driver; 3-state (v.1.0)2009-01-20
Application notepdfPicoGate Logic footprints (v.2.0)2002-10-30

Ordering & availability

Type numberOrdering code(12NC)Orderable part numberRegionDistributorIn stockOrder quantityInventory dateBuy onlineSamples
74AUP1T1326GT9352 860 8211574AUP1T1326GT,115NADIGI-KEY CORPORATION5,0005/23/2012Buy online 
   JAPANCHIP ONE STOPno05/14/2012Buy online 

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