8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
The 74HC595; 74HCT595 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A.
The 74HC595; 74HCT595 are 8-stage serial shift registers with a storage register and 3-state outputs. The registers have separate clocks.
Data is shifted on the positive-going transitions of the shift register clock input (SHCP). The data in each register is transferred to the storage register on a positive-going transition of the storage register clock input (STCP). If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register.
The shift register has a serial input (DS) and a serial standard output (Q7S) for cascading. It is also provided with asynchronous reset (active LOW) for all 8 shift register stages. The storage register has 8 parallel 3-state bus driver outputs. Data in the storage register appears at the output whenever the output enable input (OE) is LOW.
|Type number||Product status||VCC (V)||Logic switching levels||Output drive capability (mA)||tpd (ns)||fmax (MHz)||Nr of bits||Power dissipation considerations||Tamb (Cel)||Package name|
|74HC595N||Production||2.0 - 6.0||CMOS||+/- 7.8||16||108||8||low||-40~125||DIP16|
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