The PowerQUICC II™ integrated communications processor family delivers excellent integration of processing power for networking and communications peripherals, providing customers with an innovative, total system solution for building high-end communications systems. NXP Semiconductors's PowerQUICC II processor family is the next generation of the leading PowerQUICC™ line of integrated communications processors, providing higher performance in all areas of device operation, including greater flexibility, extended capabilities, and higher integration.
Our leading PowerQUICC architecture integrates two processing blocks. One block is a high-performance embedded G2 core and the second block is the Communications Processor Module (CPM). The CPM of the MPC8255 processor can support up to two fast serial communications controllers (FCCs), one multichannel controller (MCC), four serial communications controllers (SCCs), two serial management controllers (SMCs), one serial peripheral interface (SPI) and one I2C interface. The combination of the G2 core and the CPM, along with the versatility and performance of the PowerQUICC II processor family, provides customers with enormous potential in developing networking and communications products while significantly reducing time-to-market development stages.
|Ethernet (10T)||Up to 4||Up to 4||Up to 4||Up to 4||Up to 4||Up to 4|
|Ethernet (10/100)||Up to 3||Up to 2||Up to 3||Up to 3||Up to 3||Up to 3|
|UTOPIA II Ports||0||2||2||2||2||2|
|Multi-Channel HDLC||Up to 128||Up to 128||Up to 256||Up to 256||Up to 256||Up to 256|
|Fast Communication Controllers (FCCs)||3||2||3||3||3||3|
|Serial Communications Controllers (SCCs)||4||4||4||4||4||4|
1. The IMMR[16-31] indicates the mask number.
2. The Rev_Num located at offset 0x8AF0 in DPRAM indicates the CPM microcode revision number.
3 . Encryption Enabled.
4 . Encryption Disabled.
Masks and versions table last updated on 14OCT2004.