NXP’s next-generation PowerQUICC® III integrated communications processors are designed to provide solutions for symmetrical and asymmetrical multi-core systems. Based on the scalable e500 processor and system-on-chip (SoC) platform, they deliver dual-core gigahertz plus processing performance with advanced content processing and security features.
The MPC8572E family of processors offers clock speeds from 1.2 GHz up to 1.5 GHz, combining two powerful e500 processor cores built on Power Architecture® technology, enhanced peripherals and high-speed interconnect technology to balance processor performance with I/O system throughput. These processors also contain application acceleration blocks such as a table lookup unit (TLU) that offloads complex table searches and header inspections, a pattern-matching engine to handle regular expression matching with a deflate engine to manage file decompression and a security engine that accelerates crypto operations in IPsec and SSL/TLS for VPNs.
Based on NXP®.s 90 nm silicon-on-insulator (SOI) copper interconnect process technology, the MPC8572E is designed to deliver higher performance with lower power dissipation. The MPC8572E processors provide a significant performance increase and represent continuous innovation from the popular PowerQUICC family. With uncompromising integration, the MPC8572E platform builds on the embedded core performance of Power Architecture technology and adds new features to enhance traffic management and security acceleration.
Support for high-speed interfaces on the MPC8572E enables scalable connectivity to network processors and/or ASICs in the data plane while the MPC8572E platform handles complex, computationally demanding control plane processing tasks. These processors include dual memory controllers supporting DDR2 and DDR3 for future proofing and error correction codes for high reliability, enhanced Gigabit Ethernet (GbE) support and double precision floating point.
Use a dual core device for higher performance with symmetric multiprocessor (SMP); to collapse two non-SMP operation systems (either homogenous or heterogeneous) onto one device; for split control and data plane applications; for adding services/applications on Linux next to an existing OS; for later in-field upgrade to higher performance by turning on the second core; for in-field “hot swap” OS upgrade by loading new OS to second core before putting first core with old OS into sleep mode.