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QorIQ® Data Path Acceleration Architecture

The Data Path Acceleration Architecture (DPAA) is a set of hardware components on specific QorIQ® P and T series multicore processors. This architecture provides the infrastructure to support simplified sharing of networking interfaces and accelerators by multiple CPU cores, and the accelerators themselves.

QorIQ DPAA components include:

  • Multicore infrastructure components such as the Queue Manager and Buffer Manager
  • Frame Manager for network I/O
  • RapidIO® Message Manager for high-speed serial interconnect
  • Hardware accelerators for cryptography (SEC), regular expression scanning (PME) and compression (DCE)

Together these components address multicore requirements including:

  • Load spreading and prioritization
  • Packet order preservation and restoration
  • Device virtualization
  • Inter-core communication

Design Resources


  • Determines and separates ingress flows then manages the temporary, permanent or semi-permanent flow-to-core affinity.
  • Provides a work priority scheme, which ensures ingress critical flows are addressed properly and frees software from the need to implement a queuing mechanism on egress.
  • Performance is boosted by direct cache warming/stashing as well as by providing biasing for core-to-flow affinity, which ensures that flow-specific data structures can remain in the core’s cache.