The dual-core P5020 and single-core P5010 processors deliver 64-bit processing, based on the e5500 core built on Power Architecture® technology. With frequencies scalable to 2.0 GHz, large caches and high per-cycle efficiency, these products target control plane and compute applications that require high single-threaded performance.
The P5 platform leverages architectural features pioneered in the P4 platform, including the three-level cache hierarchy for low latencies, hardware hypervisor for robust virtualization support, data path acceleration architecture (DPAA) for offloading packet handling tasks from the core and the CoreNet® switch fabric that eliminates internal bottlenecks. This enables architectural compatibility from the P5 platform to the P4 platform as well as to the P3 platform.
|Core Frequency||1.6 to 2.0 GHz||1.6 to 2.0 GHz|
|L2 Cache||512 KB||512 KB|
|L3/Platform Cache||2 MB||1 MB|
|DDR3||2x 64-bit||1x 64-bit|
|GbE||5x 1 GbE 1x 10 GbE||5x 1 GbE 1x 10 GbE|
|SERDES||18 Lanes||18 Lanes|