Q: Can you recommend a good book on ARM architecture?
A: ARM - System on Chip Architecture by Steve Furber (Addison Wesley ISBN 0-202-67519-6) There are also helpful ARM documents on the www.arm.com site.
Q: Does the ARM LPC products have memory-mapped chip-select?
A: LPC212x have up to 4 programmable memory chip-select.
Q: Does NXP have a partnership with MathWorks so MathLab can support the ARM LPC?
A: NXP currently does not have a partnership with MathWorks. However, ARM made the following announcement. Once their collaboration is completed, MathWorks under the ARM Developer Suite will support NXP ARM LPC.
CAMBRIDGE, UK and AACHEN, GERMANY - Sept. 13, 2001
- ARM [(LSE:ARM); (Nasdaq:ARMHY)], the industry's leading provider of 16/32-bit embedded RISC microprocessor solutions, and
The MathWorks GmbH, the German subsidiary of the leading supplier of technical computing software for engineers and scientists,
today announced a collaborative project aimed at combining the ARM Developer Suite™ (ADS) code development toolchain, the
ARMulator™ instruction set simulator, and the MATLAB/Simulink system simulation and code generation toolchain.
Q: If you remove the clock from our LPC210x, does the PLL keep running? What happens at the output pins?
A: Removing the clock will cause the PLL to stop working because it's an Analog PLL with a phase detector. Some Digital PLLs will indeed continue to work at the last clock if the clock is removed but their principle of operation is completely different. What happens at the pins is difficult to predict (depends on what anomalous mode the PLL goes into).
Q: How many hardware breakpoints can be used, without using the RAM?
A: The ARM Embedded ICE unit only allows 2 hardware breakpoints.
Q: What is the ETM trace depth?
A: The ETM version we use has a 10 byte FIFO (Address trace only).
Q: Does LPC210x have good multiply or multiply-and-accumulate (MAC) functions?
A: The ARM7TDMI-S Core we use has excellent Multiply and Multiply-Accumulate capability and can be run at 60 MHz offering good DSP capability. See spreadsheet (bottom of this document) describes the Multiply and Multiply-Accumulate instructions and how long they take to execute.
Q: Are LPC210x I/O's true I/Os?
A: All LPC210x port 0 are true bi-directional I/Os (the only exception being the 2 I²C pins that have open drain structure; with external pull-ups they can also be used as regular GP I/Os). There is no push-pull or open-collector as those found on the 80C51. (When GPIO functionality is on the pin, and it is in output mode, the pin is acting as full-drive (there is no internal pull-up for high-output as in the 80C51)
Q: What does "Deterministic" mean in your press release?
A: In some ARM implementation, there is cache on board. In ours, there is none and it's not needed in a single chip (with on-chip Flash and on-chip SRAM) MCU. The cache implementation is a way to improve external memory/data access. In those systems, depends on where the data/instructions are located the performance can vary (i.e. in cache vs. in ext. RAM/Flash). Our implementation keeps everything on-chip with zero-wait access for data/instruction; therefore, this is already the optimum implementation. In addition, cache (SRAM) and cache controller (big logic block) will increase the power consumption.
Q: What is the finest resolution on the LPC210x PWM?
A: The finest resolution is = 1/processor clock max (60MHz). In this case = 16 ns.
Q: What is the maximum UART speed on the LPC210x devices?
A: The baud-rate is calculated as:
pclk/(16* divisor);
The divisor is 16 bits long; the maximum for this formula is pclk/16 - in case you do not divide cclk in order to get pclk,
result is cclk/16. The pclk = cclk/4 value is selected to save power, not because the UART clock has to be limited.
The max UART speed is 60MHz /16 = 3.75 Mbit/sec.
Q: What is the maximum SPI speed on the LPC210x devices?
The peripheral bus (VPB) is capable of running with the same max. speed as the ARM7 system bus (AHB), which is 60MHz (using VPBDIV=1). The "Maximum SPI data bit rate is one eighth of the input clock rate" (User manual chapter 10, ISP features).
The SPI rate may be calculated as: PCLK rate / SPCCR value. The value of the SPI Clock Counter Register (SPCCR) must always be greater than or equal to 8. The pclk rate is CCLK / VPB divider rate as determined by the VPBDIV registers contents.
PCLK = 60MHz / 1 = 60MHz
The max. SPI rate is 7.5MHz = PCLK / VPBDIV = 60MHz / 8
Q: Having the Thumb core allows more compact code and better performance, are there any trade offs?
A: Thumb is a 16-bit compressed instruction set that is decoded by the Thumb core into full 32-bit instructions that are then fed into an ARM core for execution. It increases code density drastically. The trade-off includes that the Thumb instruction set loses the conditional instruction execution and can only address the first eight registers of the processor.
Q: Can multiple ports be read at one time?
A: 32 I/Os can be read at a time.
Q: What is the Flash endurance?
A: Program Flash has typical 100K write cycles. It is guaranteed to 10K write-cycles with greater than 10-year retention.
Q: I need a LDO (low drop out regulator) with the LPC210x. Can you recommend one?
A: NXP makes a family of LDOs that doesn't require output capacitors. The SA57017 is one such device.
- CapFREE: No output capacitor needed, stable for all capacitive loads, regardless of ESR.
- 5 leaded (SO5) SOT23-5 and Wafer level Chip-Scale (WL-CSP5) packages
- Low 25 uVrms noise without noise bypass capacitor.
- Preset output voltages to 1.25, 1.8, 2.4 2.6, 2.8, 3.0, and 3.3V
- 1% output voltage accuracy.
- 150 mA Maximum Output Current with current limitation.
Q: What is the typical current consumption for the LPC210x?
A: Typical current consumption for the LPC210x:
- 30 mA - active
- 20 mA - Idle
- 10 uA - sleep
For detailed supply current, please refer to the latest datasheet.
Q: What kind of programming and erase time does the LPC210x have?
A: Program time: 1ms up to 512 bytes.
Erase time: 400 ms 8KB or chip erase.
Q: Can the LPC210x run Windows CE?
A: No, to run Windows CE properly, MMU is required. The LPC210x does not have an MMU.
Q: Oscillator start up time and PLL-lock-in-time (for a crystal and Operating frequency of your choice)
A: Oscillator start up time - for a crystal range from 10-25 MHz you could expect start up times between 0.4 - 1.95 ms. This range also includes the time whether you are using caps or not.
The PLL lock-in-time not specified at present (7/18/03). At room temp at it was around 50 microseconds with a 10 MHz crystal. The PLL was getting set to 60 MHz.
Q: What about RTOS support for LPC210x
- MicroCOS2 (by Micrium ltd.)
- CMX (CMX Systems)
- ThreadX and Integrity- (By Green Hills Software)
- Nucleus (Accelerated Technology)
Debuggers like Nohau's Seehau and IAR's C-SPY debuggers have plug- ins for the MicroC-OS2
Q: Can I run the peripherals at full speed
A: Yes, the system clock (cclk) could be directly fed to all the peripherals (pclk) by setting the VPBDIV register to 1. All the peripherals can run at full speed as per specification.
Q: How do we set the PLL as the clock source
A: The steps are as follows:
- Calculate the multiplier and divider values and feed it to the PLLCFG register
- Enter the feed sequence
- Enable the PLL (PLLCON=0x1)
- Enter the feed sequence
- Wait for a successful lock (you should poll the PLOCK bit in the PLLSTAT register)
- Connect the PLL as clock source (PLLCON=0x3)
- Enter the feed sequence
You can optionally run other functions and configure the PLL lock as an interrupt source and connect the PLL when the interrupt occurs
Q: Why does the code run slowly from flash when NXP claims that the chip runs with nearly zero wait states from flash?
A: On reset, the Memory Accelerator Module (MAM) is disabled but the MAM Timing register has a reset value of 0x7, which means that 6 wait states are inserted for every flash access. You need to set it depending upon the frequency at which you are running. If you are running your application below or at 20 MHz you can set this register to 0x1, which implies no wait states.
Q: When I enter debug mode port pins 22-31 are not useable by the application even though I am using JTAG for debugging, which uses only 5 pins
A: Yes, that is true and this is because in primary debug mode the port pins 22-31 are configured for trace even if you are only using JTAG. If you wish to use only JTAG while debugging and your application needs additional port pins then you need to use the secondary JTAG interface. In this interface, port pins 27-31 is used for debugging purposes and all other pins can be used by the application. An application note will be provided with detailed instructions as to how to use this interface.
Q: Are there any flash programming tools offered by NXP itself
A: NXP provides an ISP (In-System Programming) utility, which is available at no cost at the NXP website. Click on the link to download the utility
Q: Does the PWM block use the same timer counters as the General purpose timers
A: No, the PWM has its own set of timer counter registers
Q: I am using the SPI in just the master mode. Hence I am only mapped MOSI, SCLK to respective port pins but I don't see any output.
A: When you are using the SPI in master mode you also need to map SSEL pin to P0.7 and drive it high. You need not map MISO pin.
Q: What is the Flash programming time?
A: To program the complete 128KB of flash on the LPC210x is around 10seconds.We are working on an option that will reduce the programming time to 2seconds. As soon as this is available the information will be posted online.