ADC1413D065HN

Dual 14 bits ADC; 65 Msps; serial JESD204A


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The ADC1413D065HN is a dual channel 14-bit Analog-to-Digital Converter (ADC) optimized for high dynamic performances and low power at sample rates of 65 Msps. Pipelined architecture and output error correction ensure the ADC1413D065HN is accurate enough to guarantee zero missing codes over the entire operating range. Supplied from a 3.3 V source for analog and a 1.8 V source for the output driver, it has two serial outputs, because of the two lanes of differential outputs, which are compliant with the JESD204A standard. An integrated SPI (Serial Peripheral Interface) allows the user to easily configure the ADC. A set of IC configurations is also available via the binary level control pins taken, which are used at power-up.

Features and benefits

  • 2 configurable serial outputs
  • 3.3 V, 1.8 V single supplies
  • Compliant with JESD204A serial transmission standard
  • Dual channel 14-bit pipelined ADC core
  • Duty cycle stabilizer
  • Flexible input voltage range: 1 V (p-p) to 2 V (p-p) with 6 dB programmable fine gain
  • High IF capability
  • Input bandwidth, 600 MHz
  • Offset binary, 2"s complement, gray code
  • Power dissipation, 995 mW at 80 Msps
  • Power-down and Sleep modes
  • Sample rate up to 65 Msps
  • SFDR, 90 dBc
  • SNR, 73 dB
  • SPI interface

Applications

  • Imaging systems
  • Portable instrumentation
  • Spectral analysis
  • Ultrasound equipment
  • Wireless and wired broadband communications
All information on this product information page is subject to the subsequent disclaimers:
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Demo boards

ADC1413D065W1ADC1413D065W1

SSL4101DB01 150 W SSL reference design

ADC1413D065WOADC1413D065WO

ADC1413D065W0 demoboard; compliant with Lattice, Altera, Xilinx FPGA boards through specific connectors


Parametrics of this product

SymbolParameterConditionsMinTyp/NomMaxUnit
VDDAanalog supply voltage2.8533.4V
VDDDdigital supply voltage1.651.81.95V
Tambambient temperature-4085°C
fssampling rate65Msps
Nchnumber of channels2
Nfuncnumber of functions2
Nresresolution14bit
Tstgstorage temperature-55125°C
Static characteristics, Supplies
Ptottotal power dissipationVDDD = 1.8 V; normal operation; fclk = 65 MHz885mW
Dynamic characteristics, Analog signal processing
Bbandwidth600MHz
fssampling frequency65Msps
SFDRspurious-free dynamic rangefi = 3 MHz86dBc
SNRsignal-to-noise ratiofi = 3 MHz72.1dBFS

Similar products

Products / Packages

Type numberOrderable part numberOrdering code (12NC)Product statusPackagePackingMarking
ADC1413D065HN/C1ADC1413D065HN/C1:59352 890 78518Volume productionSOT684-7
(HVQFN56) 		Reel Dry Pack, SMD, 13"Standard Marking
ADC1413D065HN/C1ADC1413D065HN/C1,59352 890 78551Volume productionSOT684-7
(HVQFN56) 		Tray Dry Pack, Bakeable, SingleStandard Marking

Quality, reliability & chemical content

Type numberOrderable part numberChemical contentRoHSLeadfree conversion dateRHFIFR (FIT)MTBF (hours)MSLMSL LF
ADC1413D065HN/C1ADC1413D065HN/C1:5ADC1413D065HN/C1Always Pb-free33
ADC1413D065HN/C1ADC1413D065HN/C1,5ADC1413D065HN/C1Always Pb-free33
Quality and reliability disclaimer

Quality and reliability disclaimer

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Documentation for this product

If you have any questions related to this product please contact our support team via e-mail: dataconverter-support@nxp.com. Thank you for your cooperation.

TypeFormatTitleDate
Data sheetpdfDual 14-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; serial JESD204A interface (v.6.0)2011-06-08
Application notepdfJESD204A: High speed serialization for data converters (v.2.0)2010-09-23
Application notepdfInterconnection between JESD204A compliant devices (v.2.0)2010-09-24
Application notepdfR_10002 Technical analysis of the JEDEC JESD204A data converter interface (v.1.0)2010-08-23
Application notepdfR_10002 Technical analysis of the JEDEC JESD204A data converter interface Japanese (v.1.1)2010-08-30
Application notepdfR_10002 Technical analysis of the JEDEC JESD204A data converter interface Chinese (v.1.1)2010-08-30
BrochurepdfYour partner in Mobile Communication Infrastructure design; High Performance RF for wireless infrastructure (v.1.0)2011-05-23
Design toolshtmlXilinx JESD204B v1.1 LogiCORE IP core (v.1.0)2011-12-07
LeafletpdfDual-channel ADCs with JESD204A-compliant outputs for wireless and industrial; NXP dual 11, 12, 14, 16 bits ADC: ADC1113D series, ADC1213D series, ADC1413D series, ADC1613D series (v.2.0)2010-06-01
LeafletpdfSingle-channel ADC with input buffer (v.1.0)2010-09-13
Other typepdfThe JESD204A interface - The key to broadband wireless system miniaturizationminiaturization - NXP and Xilinx (v.1.0)2010-12-15
ReportpdfTechnical analysis of the JEDEC JESD204A data converter interface (v.2.1)2011-10-14
ReportpdfPower consumption benefits of JESD204 serial interface (v.1.0)2010-12-23
Selection guidepdfDemoboards for high-speed converters (v.1.0)2010-05-01
Selection guidepdfNXP high-speed ADC/DAC selection guide (v.1.0)2011-12-14

Ordering & availability

Type numberOrdering code(12NC)Orderable part numberRegionDistributorIn stockOrder quantityInventory dateBuy onlineSamples
ADC1413D065HN/C19352 890 78518ADC1413D065HN/C1:5       
ADC1413D065HN/C19352 890 78551ADC1413D065HN/C1,5NADIGI-KEY CORPORATION2605/24/2012Buy onlinenot available
   NAAVNET EXPRESS2605/24/2012Buy online 

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Demo boards

ADC1413D065W1
ADC1413D065W1

SSL4101DB01 150 W SSL reference design

ADC1413D065WO
ADC1413D065WO

ADC1413D065W0 demoboard; compliant with Lattice, Altera, Xilinx FPGA boards through specific connectors

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