ADC1613D125HN

ADC1613D125 - Dual 16 bits ADC; 125 Msps; serial JESD204A


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The ADC1613D is a dual channel 16-bit Analog-to-Digital Converter (ADC) optimized for high dynamic performances and low power at sample rates up to 125 Msps. Pipelined architecture and output error correction ensure the ADC1613D is accurate enough to guarantee zero missing codes over the entire operating range. Supplied from a 3 V source for analog and a 1.8 V source for the output driver, it has two serial outputs, which are compliant with the JESD204A standard. An integrated SPI (Serial Peripheral Interface) allows the user to easily configure the ADC.

Features and benefits

  • 2 configurable serial outputs
  • 3 V, 1.8 V single supplies
  • Compliant with JESD204A serial transmission standard
  • Dual channel 16-bit pipelined ADC core
  • Duty cycle stabilizer
  • Flexible input voltage range: 1 V (p-p) to 2 V (p-p)
  • High IF capability
  • Input bandwidth, 600 MHz
  • Offset binary, 2"s complement, gray code
  • Power-down and Sleep modes
  • Sample rate up to 125 Msps
  • SFDR, 90 dBc
  • SNR, 73 dB
  • SPI interface

Applications

  • Imaging systems
  • Portable instrumentation
  • Spectral analysis
  • Ultrasound equipment
  • Wireless and wired broadband communications
All information on this product information page is subject to the subsequent disclaimers:
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Demo boards

ADC1613D125W1ADC1613D125W1

ADC1613D125W1 demo board

ADC1613D125WOADC1613D125WO

ADC1613D125WO demoboard; compliant with Lattice, Altera, Xilinx FPGA boards through specific connectors


Parametrics of this product

SymbolParameterConditionsMinTyp/NomMaxUnit
Static characteristics
VDDAanalog supply voltage2.8533.4V
VDDDdigital supply voltage1.651.81.95V
Ptottotal power dissipation1270mW
Tambambient temperature-4085°C
Tjjunction temperature125°C
Tstgstorage temperature-55125°C
Dynamic characteristics
Bbandwidth600MHz
fssampling frequency125Msps
SFDRspurious-free dynamic rangefi = 3 MHz89dBc
SNRsignal-to-noise ratiofi = 3 MHz71.6dBFS

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Products / Packages

Type numberOrderable part numberOrdering code (12NC)Product statusPackagePackingMarking
ADC1613D125HN/C1ADC1613D125HN/C1,59352 907 52518Volume productionSOT684-7
(HVQFN56) 		Reel Dry Pack, SMD, 13"Standard Marking
ADC1613D125HN/C1ADC1613D125HN/C1:59352 907 52551Volume productionSOT684-7
(HVQFN56) 		Tray Dry Pack, Bakeable, SingleStandard Marking

Quality, reliability & chemical content

Type numberOrderable part numberChemical contentRoHSLeadfree conversion dateRHFIFR (FIT)MTBF (hours)MSLMSL LF
ADC1613D125HN/C1ADC1613D125HN/C1,5ADC1613D125HN/C1Always Pb-free33
ADC1613D125HN/C1ADC1613D125HN/C1:5ADC1613D125HN/C1Always Pb-free33
Quality and reliability disclaimer

Quality and reliability disclaimer

Important Legal Notice on the product/generic quality information, No Warranty

NXP Semiconductors is providing this data for your convenience only. Please note however that NO WARRANTY, REPRESENTATION, GUARANTEE OR LEGALLY BINDING PRODUCT DESCRIPTION is provided by publishing this informational data, nor does NXP Semiconductors acknowledge or accept any liability related thereto. The documentation and data on NXP Semiconductors products can be found in the data sheets as officially published by NXP Semiconductors. For all purchase of products from NXP Semiconductors the NXP Semiconductors' General Terms and Conditions of Commercial Sale will apply.

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Documentation for this product

If you have any questions related to this product please contact our support team via e-mail: dataconverter-support@nxp.com. Thank you for your cooperation.

TypeFormatTitleDate
Data sheetpdfDual 16-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; serial JESD204A interface (v.3.0)2011-02-09
Application notepdfR_10002 Technical analysis of the JEDEC JESD204A data converter interface (v.1.0)2010-08-23
Application notepdfR_10002 Technical analysis of the JEDEC JESD204A data converter interface Japanese (v.1.1)2010-08-30
Application notepdfR_10002 Technical analysis of the JEDEC JESD204A data converter interface Chinese (v.1.1)2010-08-30
BrochurepdfYour partner in Mobile Communication Infrastructure design; High Performance RF for wireless infrastructure (v.1.0)2011-05-23
Design toolshtmlXilinx JESD204B v1.1 LogiCORE IP core (v.1.0)2011-12-07
LeafletpdfDual-channel ADCs with JESD204A-compliant outputs for wireless and industrial; NXP dual 11, 12, 14, 16 bits ADC: ADC1113D series, ADC1213D series, ADC1413D series, ADC1613D series (v.2.0)2010-06-01
LeafletpdfSingle-channel ADC with input buffer (v.1.0)2010-09-13
Other typepdfThe JESD204A interface - The key to broadband wireless system miniaturizationminiaturization - NXP and Xilinx (v.1.0)2010-12-15
Other typepdfAvateq, NXP and Xilinx Join to Meet Digital Broadcast Repeater Design Challenges (v.2.0)2012-04-11
ReportpdfTechnical analysis of the JEDEC JESD204A data converter interface (v.2.1)2011-10-14
ReportpdfPower consumption benefits of JESD204 serial interface (v.1.0)2010-12-23
Selection guidepdfDemoboards for high-speed converters (v.1.0)2010-05-01
Selection guidepdfNXP high-speed ADC/DAC selection guide (v.1.0)2011-12-14

Ordering & availability

Type numberOrdering code(12NC)Orderable part numberRegionDistributorIn stockOrder quantityInventory dateBuy onlineSamples
ADC1613D125HN/C19352 907 52518ADC1613D125HN/C1,5NADIGI-KEY CORPORATION205/24/2012Buy onlinenot available
ADC1613D125HN/C19352 907 52551ADC1613D125HN/C1:5NAFUTURE ELECTRONICS55/23/2012Buy online 
   EUFUTURE ELECTRONICS UK55/23/2012Buy online 
   ASIAFUTURE ELECTRONICS- ASIA55/23/2012Buy online 

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Demo boards

ADC1613D125W1
ADC1613D125W1

ADC1613D125W1 demo board

ADC1613D125WO
ADC1613D125WO

ADC1613D125WO demoboard; compliant with Lattice, Altera, Xilinx FPGA boards through specific connectors

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