
ADC1415S105HN
Single 14-bit ADC 105 Msps with Input Buffer CMOS or LVDS DDR digital outputs
The ADC1415S is a single channel 14-bit Analog-to-Digital Converter (ADC) optimized for high dynamic performances and low power consumption at sample rates up to 125 Msps. Pipelined architecture and output error correction ensure the ADC1415S is accurate enough to guarantee zero missing codes over the entire operating range. Supplied from a single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode, thanks to a separate digital output supply. The ADC1415S supports the LVDS (Low Voltage Differential Signalling) DDR (Double Data Rate) output standard. An integrated SPI (Serial Peripheral Interface) allows the user to easily configure the ADC.


ADC1415S105ADC1415S105 demo board; both CMOS and LVDS outputs
ADC1415S105F1ADC1415S105F1 demo board; CMOS outputs
| Symbol | Parameter | Conditions | Min | Typ/Nom | Max | Unit |
|---|---|---|---|---|---|---|
| VDDA | analog supply voltage | 3 V supply | 2.85 | 3 | 3.4 | V |
| VDDA | analog supply voltage | 5 V supply | 4.75 | 5 | 5.25 | V |
| VDDO | output supply voltage | CMOS mode | 1.65 | 1.8 | 3.6 | V |
| VDDO | output supply voltage | LVDS DDR mode | 2.85 | 3 | 3.6 | V |
| Tamb | ambient temperature | -40 | 85 | °C | ||
| Tstg | storage temperature | -55 | 125 | °C | ||
| Static characteristics | ||||||
| Ptot | total power dissipation | fclk = 105 MHz; VDDA = 3 V; VDDO = 1.8 V | 688 | mW | ||
| Dynamic characteristics | ||||||
| B | bandwidth | 600 | MHz | |||
| fs | sampling frequency | 105 | Msps | |||
| SFDR | spurious-free dynamic range | fi = 3 MHz | 85 | dBc | ||
| SNR | signal-to-noise ratio | fi = 3 MHz | 71.8 | dBFS | ||
| THD | total harmonic distortion | fi = 30 MHz | 87 | dB | ||
| THD | total harmonic distortion | fi = 170 MHz | 82 | dB | ||
| THD | total harmonic distortion | fi = 70 MHz | 85 | dB | ||
| THD | total harmonic distortion | fi = 3 MHz | 87 | dB | ||
| Type number | Orderable part number | Ordering code (12NC) | Product status | Package | Packing | Marking |
|---|---|---|---|---|---|---|
| ADC1415S105HN/C1 | ADC1415S105HN/C1:5 | 9352 890 31518 | Volume production | SOT618-6 (HVQFN40) | Reel Dry Pack, SMD, 13" | Standard Marking |
| ADC1415S105HN/C1 | ADC1415S105HN/C1,5 | 9352 890 31551 | Volume production | SOT618-6 (HVQFN40) | Tray Dry Pack, Bakeable, Single | Standard Marking |
| Type number | Orderable part number | Chemical content | RoHS | Leadfree conversion date | RHF | IFR (FIT) | MTBF (hours) | MSL | MSL LF |
|---|---|---|---|---|---|---|---|---|---|
| ADC1415S105HN/C1 | ADC1415S105HN/C1:5 | ADC1415S105HN/C1 | Always Pb-free | 3 | 3 | ||||
| ADC1415S105HN/C1 | ADC1415S105HN/C1,5 | ADC1415S105HN/C1 | Always Pb-free | 3 | 3 |
If you have any questions related to this product please contact our support team via e-mail: dataconverter-support@nxp.com. Thank you for your cooperation.
| Type | Format | Title | Date |
|---|---|---|---|
| Data sheet | Single 14-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps with input buffer; CMOS or LVDS DDR digital outputs (v.4.0) | 2010-12-17 | |
| Brochure | Your partner in Mobile Communication Infrastructure design; High Performance RF for wireless infrastructure (v.1.0) | 2011-05-23 | |
| Leaflet | Single-channel ADC with input buffer (v.1.0) | 2010-09-13 | |
| Report | Technical analysis of the JEDEC JESD204A data converter interface (v.2.1) | 2011-10-14 | |
| Report | Power consumption benefits of JESD204 serial interface (v.1.0) | 2010-12-23 | |
| Selection guide | NXP high-speed ADC/DAC selection guide (v.1.0) | 2011-12-14 |
Sample orders normally take 2-4 days for delivery.
If you do not have a direct account with NXP our network of global and regional distributors is available and equipped to support you with NXP samples. As a NXP customer you also have the option to order samples via our sales organisation.
ADC1415S105 demo board; both CMOS and LVDS outputs
ADC1415S105F1 demo board; CMOS outputs
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