NFC Controlled Machine Access

Block Diagram

Industrial Machine Access Contol

NFC Controlled Machine Access BD

Supported Devices



NFC Readers

Processors and Microcontrollers

K6x Ethernet



  • Arm® Cortex®-M4 core + DSP. 120 MHz, single-cycle MAC, single instruction multiple data (SIMD) extensions, single precision floating point unit
  • Up to 16-channel DMA for peripheral and memory servicing with reduced CPU loading and faster system throughput
  • Crossbar switch enables concurrent multi-leader bus accesses, increasing bus bandwidth
  • Independent flash banks allow concurrent code execution and firmware updating with no performance degradation or complex coding routines


  • Flexible low-power modes with power and clock gating for optimal peripheral activity and recovery times. Stop currents of < 340 nA, run currents of < 250 µA/MHz, 4.5 µs wake-up from Stop mode
  • Full memory and analog operation down to 1.71 volts for extended battery life
  • Low-leakage wake-up unit with up to seven internal modules and 16 pins as wake-up sources in low-leakage stop (LLS)/very low-leakage stop (VLLS) modes
  • Low-power timer for continuous system operation in reduced power state

NFC features

  • High power (2 W), feature-filled transmitter: DPC 2.0 (dynamic power control without processing load on host MCU)
  • Single 3.3 V supply with max TX transmitter power possible
  • Connection of 1 differential or 2 single-ended antennas
  • Robust receiver: Automatic configuration, advanced insensitivity against TFT display noise for higher RF performance
  • Full NFC Frontend with active load modulation in Card Mode for large operating distance
  • All relevant RF protocols implemented
  • NXP proprietary high data rates up to 212 Kbit for NTAG5 communication
  • Ultra-low-power card detect for low average current consumption


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