KIT33905BD3EVBE: Evaluation Kit - 33905D3, SBC Gen2 with CAN and LIN

Overview

Target Applications

NXP<sup>®</sup> KIT33905DxEKEVBE Evaluation Kit Product Image

Specifications

Supported Devices

Power Management

CAN/LIN SBCs
  • MC33904 : System Basis Chip Gen2 with High Speed CAN

Interfaces

  • MC33905 : SBC Gen2 with High-Speed CAN and LIN

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Technical and Functional Specifications

Connectivity
  • Multiple CAN Bus termination options supported via socket
  • Two high/low side I/Os (SPI configurable) accessible through test points
  • 100 mil 2 x 8 pin standard header connector for SPI communication
  • 100 mil 16-pin standard header connector for custom MCU board connections
Power Management
  • Nominal operating supply voltage range of 5.5 V to 27 V
  • Individually routed power supply inputs for VSUP1 and VSUP2
  • 5.0/3.3 V regulator for MCU with an external PNP ballast transistor to increase current capability
  • MUX output voltage accessible through a test point and external resistor selectable through jumper
  • 3.3 V or 5.0 V output voltage test point VAUX (SPI configurable)
Debug Debug mode/watchdog configuration via jumper settings
General Specifications
  • Status of I/O-0 and I/O-1 indicated by an LED (dependent on jumper configuration)
  • I/O-0, I/O-1, VAUX, 5 V_CAN, SAFE, and VDD status indicated by LED
Test Points
  • I_WAKE_I test point to enable a FET and load VDD with current to wake up the SBC
  • LIN1_T and LIN2_T test points to monitor I/O voltages (SPI configurable)

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  • KIT33905BD3EVBE   Active

  • Evaluation Kit - MC33905D3, System Basis Chip Gen2 with High Speed CAN and LIN Interface
    • KIT33814AEEVBE Hardware
    • Quick Reference Guide
    • KIT33905BD3EVBE
    • 1 @ US
    • $85.00
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    • Distributor

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Evaluation and Development Boards

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Design Resources

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Documents   ( 3 )

Design Resources   ( 1 )

Software   ( 1 )

Documents

Data Sheet  ( 1 )

User Guide  ( 1 )

Errata  ( 1 )

  • MC33903, MC33904, and MC33905, Mask M87W, Rev. 3.2 Errata

    In some instances, the SPI write command is not properly interpreted by the device. This results in either a “non received SPI command” or a “corrupted SPI command”, caused by the synchronization between internal and external (oscillator and Chip Select) signals.

    • PDF
    • Rev 1.0
    • Sep 12, 2011
    • 280.5 KB
    • MC33903_4_5ER
    • English

Design Resources

Design Tools & Files  ( 1 )

Printed Circuit Boards and Schematics  ( 1 )

Software

Development Software  ( 1 )

Components and Modules  ( 1 )