Handling Exceptions in Multicore Arm^®v8 Processors

About This Training

Understanding the Arm^® v8 exception level processing (EL0 through EL3) and the generic interrupt controller v3 (GICv3) logic on the latest LS series processors might represent a challenge. The purpose of this training is to explain how to handle private peripheral (PPI) and software generated interrupts (SGI) using the GIC-500. It will be useful for embedded developers writing exception handlers and for anyone interested in learning more about Arm v8.

Training Outline

Handling Exceptions in Arm v8 Processors
Security Model and Exception Levels in Armv8
Interrupt Types
GICV3 (Generic Interrupt Controller)
How to Configure the Core to Receive and Handle Exceptions
Configuring the PPI (Private Peripheral) and SGI (Software Generated) Interrupts
Enabling the Generic Timer Interrupt
Example Code with CodeWarrior

What You Will Learn

• How to implement IRQ and FIQs in Arm v8 processors
• Types of interrupts and interrupt handlers in Armv8 processors
• Example code in CodeWarrior^®