For best experience this site requires Javascript to be enabled. To enable on your browser, follow our accessibility instructions.

Training
Handling Exceptions in Multicore Arm^®v8 Processors

Handling Exceptions in Multicore Arm^®v8 Processors

About This Training

Understanding the Arm^® v8 exception level processing (EL0 through EL3) and the generic interrupt controller v3 (GICv3) logic on the latest LS series processors might represent a challenge. The purpose of this training is to explain how to handle private peripheral (PPI) and software generated interrupts (SGI) using the GIC-500. It will be useful for embedded developers writing exception handlers and for anyone interested in learning more about Arm v8.

Training Outline

Handling Exceptions in Arm v8 Processors

Security Model and Exception Levels in Armv8

Interrupt Types

GICV3 (Generic Interrupt Controller)

How to Configure the Core to Receive and Handle Exceptions

Configuring the PPI (Private Peripheral) and SGI (Software Generated) Interrupts

Enabling the Generic Timer Interrupt

Example Code with CodeWarrior

Presented by

Chuck Corley

Senior Principal Engineer

MoreLess

DURATION

30 min

LANGUAGE

English

0Views0Likes

We are looking for ways to improve.

Take the survey.

Stay In the Loop

Subscribe to our newsletter to stay updated with our latest developments and if you need further assistance, we are here to help.

Subscribe Contact Support