Handling Exceptions in Multicore Arm®v8 QorIQ Processors - Part 5| Configuring the Core

About This Course

Understanding the Arm® v8 exception level processing (EL0 through EL3) and the Generic Interrupt Controller v3 (GICv3) logic on the latest LS series processors can be challenging outside of the pre-packaged Linux SDK environment. This presentation will look at configuring the Distributor (GICD), the Re-Distributor (GICR), the CPU interface (ICC_*_EL*), and Arm® core to handle Private Peripheral (PPI) and Software Generated Interrupts (SGI). It will be useful for embedded developers writing exception handlers and for anyone confused by all the acronyms. CodeWarrior will be used to show example exception handling projects.

What you will Learn

Understanding the Arm® v8 exception level processing

Course Outline