/*
** ###################################################################
**     Processors:          LPC55S36JBD100
**                          LPC55S36JHI48
**
**     Compilers:           GNU C Compiler
**                          IAR ANSI C/C++ Compiler for ARM
**                          Keil ARM C/C++ Compiler
**                          MCUXpresso Compiler
**
**     Reference manual:    LPC55S3x Reference Manual Rev. DraftG, 07/2021
**     Version:             rev. 1.1, 2021-08-04
**     Build:               b211210
**
**     Abstract:
**         CMSIS Peripheral Access Layer for LPC55S36
**
**     Copyright 1997-2016 Freescale Semiconductor, Inc.
**     Copyright 2016-2021 NXP
**     All rights reserved.
**
**     SPDX-License-Identifier: BSD-3-Clause
**
**     http:                 www.nxp.com
**     mail:                 support@nxp.com
**
**     Revisions:
**     - rev. 1.0 (2021-04-12)
**         Initial version based on RM DraftF
**     - rev. 1.1 (2021-08-04)
**         Initial version based on RM DraftG
**
** ###################################################################
*/

/*!
 * @file LPC55S36.h
 * @version 1.1
 * @date 2021-08-04
 * @brief CMSIS Peripheral Access Layer for LPC55S36
 *
 * CMSIS Peripheral Access Layer for LPC55S36
 */

#ifndef _LPC55S36_H_
#define _LPC55S36_H_                             /**< Symbol preventing repeated inclusion */

/** Memory map major version (memory maps with equal major version number are
 * compatible) */
#define MCU_MEM_MAP_VERSION 0x0100U
/** Memory map minor version */
#define MCU_MEM_MAP_VERSION_MINOR 0x0001U


/* ----------------------------------------------------------------------------
   -- Interrupt vector numbers
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
 * @{
 */

/** Interrupt Number Definitions */
#define NUMBER_OF_INT_VECTORS 136                /**< Number of interrupts in the Vector table */

typedef enum IRQn {
  /* Auxiliary constants */
  NotAvail_IRQn                = -128,             /**< Not available device specific interrupt */

  /* Core interrupts */
  NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
  HardFault_IRQn               = -13,              /**< Cortex-M33 SV Hard Fault Interrupt */
  MemoryManagement_IRQn        = -12,              /**< Cortex-M33 Memory Management Interrupt */
  BusFault_IRQn                = -11,              /**< Cortex-M33 Bus Fault Interrupt */
  UsageFault_IRQn              = -10,              /**< Cortex-M33 Usage Fault Interrupt */
  SecureFault_IRQn             = -9,               /**< Cortex-M33 Secure Fault Interrupt */
  SVCall_IRQn                  = -5,               /**< Cortex-M33 SV Call Interrupt */
  DebugMonitor_IRQn            = -4,               /**< Cortex-M33 Debug Monitor Interrupt */
  PendSV_IRQn                  = -2,               /**< Cortex-M33 Pend SV Interrupt */
  SysTick_IRQn                 = -1,               /**< Cortex-M33 System Tick Interrupt */

  /* Device specific interrupts */
  WDT_BOD_IRQn                 = 0,                /**< Windowed watchdog timer, Brownout detect, Flash interrupt */
  DMA0_IRQn                    = 1,                /**< DMA0 controller */
  GINT0_IRQn                   = 2,                /**< GPIO group 0 */
  GINT1_IRQn                   = 3,                /**< GPIO group 1 */
  PIN_INT0_IRQn                = 4,                /**< Pin interrupt 0 or pattern match engine slice 0 */
  PIN_INT1_IRQn                = 5,                /**< Pin interrupt 1or pattern match engine slice 1 */
  PIN_INT2_IRQn                = 6,                /**< Pin interrupt 2 or pattern match engine slice 2 */
  PIN_INT3_IRQn                = 7,                /**< Pin interrupt 3 or pattern match engine slice 3 */
  UTICK0_IRQn                  = 8,                /**< Micro-tick Timer */
  MRT0_IRQn                    = 9,                /**< Multi-rate timer */
  CTIMER0_IRQn                 = 10,               /**< Standard counter/timer CTIMER0 */
  CTIMER1_IRQn                 = 11,               /**< Standard counter/timer CTIMER1 */
  SCT0_IRQn                    = 12,               /**< SCTimer/PWM */
  CTIMER3_IRQn                 = 13,               /**< Standard counter/timer CTIMER3 */
  FLEXCOMM0_IRQn               = 14,               /**< Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */
  FLEXCOMM1_IRQn               = 15,               /**< Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */
  FLEXCOMM2_IRQn               = 16,               /**< Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */
  FLEXCOMM3_IRQn               = 17,               /**< Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */
  FLEXCOMM4_IRQn               = 18,               /**< Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */
  FLEXCOMM5_IRQn               = 19,               /**< Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */
  FLEXCOMM6_IRQn               = 20,               /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */
  FLEXCOMM7_IRQn               = 21,               /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */
  ADC0_IRQn                    = 22,               /**< ADC0  */
  ADC1_IRQn                    = 23,               /**< ADC1 */
  ACMP_IRQn                    = 24,               /**< ACMP interrupts */
  DMIC_IRQn                    = 25,               /**< Digital microphone and DMIC subsystem */
  HWVAD0_IRQn                  = 26,               /**< Hardware Voice Activity Detector */
  USB0_NEEDCLK_IRQn            = 27,               /**< USB Activity Wake-up Interrupt */
  USB0_IRQn                    = 28,               /**< USB device */
  RTC_IRQn                     = 29,               /**< RTC alarm and wake-up interrupts */
  EZH_ARCH_B0_IRQn             = 30,               /**< EZH interrupt */
  WAKEUP_IRQn                  = 31,               /**< Wakeup interrupt */
  PIN_INT4_IRQn                = 32,               /**< Pin interrupt 4 or pattern match engine slice 4 int */
  PIN_INT5_IRQn                = 33,               /**< Pin interrupt 5 or pattern match engine slice 5 int */
  PIN_INT6_IRQn                = 34,               /**< Pin interrupt 6 or pattern match engine slice 6 int */
  PIN_INT7_IRQn                = 35,               /**< Pin interrupt 7 or pattern match engine slice 7 int */
  CTIMER2_IRQn                 = 36,               /**< Standard counter/timer CTIMER2 */
  CTIMER4_IRQn                 = 37,               /**< Standard counter/timer CTIMER4 */
  OS_EVENT_IRQn                = 38,               /**< OS_EVENT_TIMER and OS_EVENT_WAKEUP interrupts */
  FlexSPI0_IRQn                = 39,               /**< FlexSPI interrupt */
  Reserved56_IRQn              = 40,               /**< Reserved interrupt */
  Reserved57_IRQn              = 41,               /**< Reserved interrupt */
  Reserved58_IRQn              = 42,               /**< Reserved interrupt */
  CAN0_IRQ0_IRQn               = 43,               /**< CAN0 interrupt0 */
  CAN0_IRQ1_IRQn               = 44,               /**< CAN0 interrupt1 */
  SPI_FILTER_IRQn              = 45,               /**< SPI Filter interrupt */
  Reserved62_IRQn              = 46,               /**< Reserved interrupt */
  Reserved63_IRQn              = 47,               /**< Reserved interrupt */
  Reserved64_IRQn              = 48,               /**< Reserved interrupt */
  SEC_HYPERVISOR_CALL_IRQn     = 49,               /**< SEC_HYPERVISOR_CALL interrupt */
  SEC_GPIO_INT0_IRQ0_IRQn      = 50,               /**< SEC_GPIO_INT00 interrupt */
  SEC_GPIO_INT0_IRQ1_IRQn      = 51,               /**< SEC_GPIO_INT01 interrupt */
  Freqme_IRQn                  = 52,               /**< frequency measure interrupt */
  SEC_VIO_IRQn                 = 53,               /**< SEC_VIO interrupt */
  CSS_IRQn                     = 54,               /**< SHA interrupt */
  PKC_IRQn                     = 55,               /**< CASPER interrupt */
  PUF_IRQn                     = 56,               /**< PUF interrupt */
  POWERQUAD_IRQn               = 57,               /**< PowerQuad interrupt */
  DMA1_IRQn                    = 58,               /**< DMA1 interrupt */
  FLEXCOMM8_IRQn               = 59,               /**< LSPI_HS interrupt */
  CDOG_IRQn                    = 60,               /**< CodeWDG interrupt */
  Reserved77_IRQn              = 61,               /**< Reserved interrupt */
  I3C0_IRQn                    = 62,               /**< I3C interrupt */
  Reserved79_IRQn              = 63,               /**< Reserved interrupt */
  Reserved80_IRQn              = 64,               /**< Reserved interrupt */
  CSS_IRQ1_IRQn                = 65,               /**< CSS_IRQ1 */
  Tamper_IRQn                  = 66,               /**< Tamper */
  Reserved83_IRQn              = 67,               /**< Reserved interrupt */
  Reserved84_IRQn              = 68,               /**< Reserved interrupt */
  Reserved85_IRQn              = 69,               /**< Reserved interrupt */
  Reserved86_IRQn              = 70,               /**< Reserved interrupt */
  Reserved87_IRQn              = 71,               /**< Reserved interrupt */
  Reserved88_IRQn              = 72,               /**< Reserved interrupt */
  Reserved89_IRQn              = 73,               /**< Reserved interrupt */
  DAC0_IRQn                    = 74,               /**< dac0 interrupt */
  DAC1_IRQn                    = 75,               /**< dac1 interrupt */
  DAC2_IRQn                    = 76,               /**< dac2 interrupt */
  HSCMP0_IRQn                  = 77,               /**< hscmp0 interrupt */
  HSCMP1_IRQn                  = 78,               /**< hscmp1 interrupt */
  HSCMP2_IRQn                  = 79,               /**< hscmp2 interrupt */
  FLEXPWM0_CAPTURE_IRQn        = 80,               /**< flexpwm0_capture interrupt */
  FLEXPWM0_FAULT_IRQn          = 81,               /**< flexpwm0_fault interrupt */
  FLEXPWM0_RELOAD_ERROR_IRQn   = 82,               /**< flexpwm0_reload_error interrupt */
  FLEXPWM0_COMPARE0_IRQn       = 83,               /**< flexpwm0_compare0 interrupt */
  FLEXPWM0_RELOAD0_IRQn        = 84,               /**< flexpwm0_reload0 interrupt */
  FLEXPWM0_COMPARE1_IRQn       = 85,               /**< flexpwm0_compare1 interrupt */
  FLEXPWM0_RELOAD1_IRQn        = 86,               /**< flexpwm0_reload1 interrupt */
  FLEXPWM0_COMPARE2_IRQn       = 87,               /**< flexpwm0_compare2 interrupt */
  FLEXPWM0_RELOAD2_IRQn        = 88,               /**< flexpwm0_reload2 interrupt */
  FLEXPWM0_COMPARE3_IRQn       = 89,               /**< flexpwm0_compare3 interrupt */
  FLEXPWM0_RELOAD3_IRQn        = 90,               /**< flexpwm0_reload3 interrupt */
  FLEXPWM1_CAPTURE_IRQn        = 91,               /**< flexpwm1_capture interrupt */
  FLEXPWM1_FAULT_IRQn          = 92,               /**< flexpwm1_fault interrupt */
  FLEXPWM1_RELOAD_ERROR_IRQn   = 93,               /**< flexpwm1_reload_error interrupt */
  FLEXPWM1_COMPARE0_IRQn       = 94,               /**< flexpwm1_compare0 interrupt */
  FLEXPWM1_RELOAD0_IRQn        = 95,               /**< flexpwm1_reload0 interrupt */
  FLEXPWM1_COMPARE1_IRQn       = 96,               /**< flexpwm1_compare1 interrupt */
  FLEXPWM1_RELOAD1_IRQn        = 97,               /**< flexpwm1_reload1 interrupt */
  FLEXPWM1_COMPARE2_IRQn       = 98,               /**< flexpwm1_compare2 interrupt */
  FLEXPWM1_RELOAD2_IRQn        = 99,               /**< flexpwm1_reload2 interrupt */
  FLEXPWM1_COMPARE3_IRQn       = 100,              /**< flexpwm1_compare3 interrupt */
  FLEXPWM1_RELOAD3_IRQn        = 101,              /**< flexpwm1_reload3 interrupt */
  ENC0_COMPARE_IRQn            = 102,              /**< enc0_compare interrupt */
  ENC0_HOME_IRQn               = 103,              /**< enc0_home interrupt */
  ENC0_WDG_IRQn                = 104,              /**< enc0_wdg interrupt */
  ENC0_IDX_IRQn                = 105,              /**< enc0_idx interrupt */
  ENC1_COMPARE_IRQn            = 106,              /**< enc1_compare interrupt */
  ENC1_HOME_IRQn               = 107,              /**< enc1_home interrupt */
  ENC1_WDG_IRQn                = 108,              /**< enc1_wdg interrupt */
  ENC1_IDX_IRQn                = 109,              /**< enc1_idx interrupt */
  ITRC0_IRQn                   = 110,              /**< itrc0 interrupt */
  Reserved127_IRQn             = 111,              /**< Reserved interrupt */
  CSSV2_ERR_IRQn               = 112,              /**< cssv2_err interrupt */
  PKC_ERR_IRQn                 = 113,              /**< pkc_err interrupt */
  Reserved130_IRQn             = 114,              /**< Reserved interrupt */
  Reserved131_IRQn             = 115,              /**< Reserved interrupt */
  Reserved132_IRQn             = 116,              /**< Reserved interrupt */
  Reserved133_IRQn             = 117,              /**< Reserved interrupt */
  FLASH_IRQn                   = 118,              /**< flash interrupt */
  RAM_PARITY_ECC_ERR_IRQn      = 119               /**< ram_parity_ecc_err interrupt */
} IRQn_Type;

/*!
 * @}
 */ /* end of group Interrupt_vector_numbers */


/* ----------------------------------------------------------------------------
   -- Cortex M33 Core Configuration
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration
 * @{
 */

#define __MPU_PRESENT                  1         /**< Defines if an MPU is present or not */
#define __NVIC_PRIO_BITS               3         /**< Number of priority bits implemented in the NVIC */
#define __Vendor_SysTickConfig         0         /**< Vendor specific implementation of SysTickConfig is defined */
#define __FPU_PRESENT                  1         /**< Defines if an FPU is present or not */
#define __DSP_PRESENT                  1         /**< Defines if Armv8-M Mainline core supports DSP instructions */
#define __SAUREGION_PRESENT            1         /**< Defines if an SAU is present or not */

#include "core_cm33.h"                 /* Core Peripheral Access Layer */
#include "system_LPC55S36.h"           /* Device specific configuration file */

/*!
 * @}
 */ /* end of group Cortex_Core_Configuration */


/* ----------------------------------------------------------------------------
   -- Mapping Information
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup Mapping_Information Mapping Information
 * @{
 */

/** Mapping Information */
/*!
 * @addtogroup dma_request
 * @{
 */

/*******************************************************************************
 * Definitions
 ******************************************************************************/

/*!
 * @brief Structure for the DMA hardware request
 *
 * Defines the structure for the DMA hardware request collections. The user can configure the
 * hardware request to trigger the DMA transfer accordingly. The index
 * of the hardware request varies according  to the to SoC.
 */
typedef enum _dma_request_source
{
    kDma0RequestFLEXSPIRX           = 0U,          /**< FlexSPI RX */
    kDma1RequestUnusedDMARequest0   = 0U,          /**< Unused DMA request 0 */
    kDma0RequestFLEXSPITX           = 1U,          /**< FlexSPI TX */
    kDma1RequestUnusedDMARequest1   = 1U,          /**< Unused DMA request 1 */
    kDma0RequestHSSPIRX             = 2U,          /**< HS_SPI RX(Flexcomm Interface 8 RX) */
    kDma1RequestHSLSPIRX            = 2U,          /**< High Speed SPI RX( */
    kDma0RequestHSSPITX             = 3U,          /**< HS_SPI TX(Flexcomm Interface 8 TX) */
    kDma1RequestHSLSPITX            = 3U,          /**< High Speed SPI TX( */
    kDma0RequestFlexcomm0Rx         = 4U,          /**< Flexcomm Interface 0 RX/I2C Slave */
    kDma1RequestFlexcomm0Rx         = 4U,          /**< Flexcomm Interface 0 RX */
    kDma0RequestFlexcomm0Tx         = 5U,          /**< Flexcomm Interface 0 TX/I2C Master */
    kDma1RequestFlexcomm0Tx         = 5U,          /**< Flexcomm Interface 0 TX */
    kDma0RequestFlexcomm1Rx         = 6U,          /**< Flexcomm Interface 1 RX/I2C Slave */
    kDma1RequestFlexcomm1Rx         = 6U,          /**< Flexcomm Interface 1 RX */
    kDma0RequestFlexcomm1Tx         = 7U,          /**< Flexcomm Interface 1 TX/I2C Master */
    kDma1RequestFlexcomm1Tx         = 7U,          /**< Flexcomm Interface 1 TX */
    kDma0RequestFlexcomm3Rx         = 8U,          /**< Flexcomm Interface 3 RX/I2C Slave */
    kDma1RequestFlexcomm3Rx         = 8U,          /**< Flexcomm Interface 3 RX */
    kDma0RequestFlexcomm3Tx         = 9U,          /**< Flexcomm Interface 3 TX/I2C Master */
    kDma1RequestFlexcomm3Tx         = 9U,          /**< Flexcomm Interface 3 TX */
    kDma0RequestFlexcomm2Rx         = 10U,         /**< Flexcomm Interface 2 RX/I2C Slave */
    kDma1RequestDmic0Ch0            = 10U,         /**< DMIC0 CH0 */
    kDma0RequestFlexcomm2Tx         = 11U,         /**< Flexcomm Interface 2 TX/I2C Master */
    kDma1RequestDmic0Ch1            = 11U,         /**< DMIC0 CH1 */
    kDma0RequestFlexcomm4Rx         = 12U,         /**< Flexcomm Interface 4 RX/I2C Slave */
    kDma1RequestI3c0Rx              = 12U,         /**< I3C0 RX */
    kDma0RequestFlexcomm4Tx         = 13U,         /**< Flexcomm Interface 4 TX/I2C Master */
    kDma1RequestI3c0Tx              = 13U,         /**< I3C0 TX */
    kDma0RequestFlexcomm5Rx         = 14U,         /**< Flexcomm Interface 5 RX/I2C Slave */
    kDma1RequestFLEXSPIRX           = 14U,         /**< FlexSpi RX */
    kDma0RequestFlexcomm5Tx         = 15U,         /**< Flexcomm Interface 5 TX/I2C Master */
    kDma1RequestFLEXSPITX           = 15U,         /**< FlexSpi TX */
    kDma0RequestFlexcomm6Rx         = 16U,         /**< Flexcomm Interface 6 RX/I2C Slave */
    kDma0RequestFlexcomm6Tx         = 17U,         /**< Flexcomm Interface 6 TX/I2C Master */
    kDma0RequestFlexcomm7Rx         = 18U,         /**< Flexcomm Interface 7 RX/I2C Slave */
    kDma0RequestFlexcomm7Tx         = 19U,         /**< Flexcomm Interface 7 TX/I2C Master */
    kDma0RequestDAC0                = 20U,         /**< DAC0 */
    kDma0RequestADC0FIFO0           = 21U,         /**< ADC0 FIFO 0 */
    kDma0RequestADC0FIFO1           = 22U,         /**< ADC0 FIFO 1 */
    kDma0RequestDMIC0CH0            = 23U,         /**< DMIC0 channel0 */
    kDma0RequestDMIC0CH1            = 24U,         /**< DMIC0 channel1 */
    kDma0RequestI3C0RX              = 25U,         /**< I3C0 RX */
    kDma0RequestI3C0TX              = 26U,         /**< I3C0 TX */
    kDma0RequestADC1FIFO0           = 27U,         /**< ADC1 FIFO 0 */
    kDma0RequestADC1FIFO1           = 28U,         /**< ADC1 FIFO 1 */
    kDma0RequestDAC1                = 29U,         /**< DAC1 */
    kDma0RequestDAC2                = 30U,         /**< DAC2 */
    kDma0RequestUnusedDMARequest31  = 31U,         /**< Unused DMA request 31 */
    kDma0RequestUnusedDMARequest32  = 32U,         /**< Unused DMA request 32 */
    kDma0RequestUnusedDMARequest33  = 33U,         /**< Unused DMA request 33 */
    kDma0RequestUnusedDMARequest34  = 34U,         /**< Unused DMA request 34 */
    kDma0RequestUnusedDMARequest35  = 35U,         /**< Unused DMA request 35 */
    kDma0RequestUnassignedDMARequest36 = 36U,      /**< Unassigned DMA request 36(but required for FlexPWM0_req_capt0) */
    kDma0RequestUnassignedDMARequest37 = 37U,      /**< Unassigned DMA request 37(but required for FlexPWM0_req_capt1) */
    kDma0RequestUnassignedDMARequest38 = 38U,      /**< Unassigned DMA request 38(but required for FlexPWM0_req_capt2) */
    kDma0RequestUnassignedDMARequest39 = 39U,      /**< Unassigned DMA request 39(but required for FlexPWM0_req_capt3) */
    kDma0RequestUnassignedDMARequest40 = 40U,      /**< Unassigned DMA request 40(but required for FlexPWM0_req_val0) */
    kDma0RequestUnassignedDMARequest41 = 41U,      /**< Unassigned DMA request 41(but required for FlexPWM0_req_val1) */
    kDma0RequestUnassignedDMARequest42 = 42U,      /**< Unassigned DMA request 42(but required for FlexPWM0_req_val2) */
    kDma0RequestUnassignedDMARequest43 = 43U,      /**< Unassigned DMA request 43(but required for FlexPWM0_req_val3) */
    kDma0RequestUnassignedDMARequest44 = 44U,      /**< Unassigned DMA request 44(but required for FlexPWM1_req_capt0) */
    kDma0RequestUnassignedDMARequest45 = 45U,      /**< Unassigned DMA request 45(but required for FlexPWM1_req_capt1) */
    kDma0RequestUnassignedDMARequest46 = 46U,      /**< Unassigned DMA request 46(but required for FlexPWM1_req_capt2) */
    kDma0RequestUnassignedDMARequest47 = 47U,      /**< Unassigned DMA request 47(but required for FlexPWM1_req_capt3) */
    kDma0RequestUnassignedDMARequest48 = 48U,      /**< Unassigned DMA request 48(but required for FlexPWM1_req_val0) */
    kDma0RequestUnassignedDMARequest49 = 49U,      /**< Unassigned DMA request 49(but required for FlexPWM1_req_val1) */
    kDma0RequestUnassignedDMARequest50 = 50U,      /**< Unassigned DMA request 50(but required for FlexPWM1_req_val2) */
    kDma0RequestUnassignedDMARequest51 = 51U,      /**< Unassigned DMA request 51(but required for FlexPWM1_req_val3) */
} dma_request_source_t;

/* @} */


/*!
 * @}
 */ /* end of group Mapping_Information */


/* ----------------------------------------------------------------------------
   -- Device Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
 * @{
 */


/*
** Start of section using anonymous unions
*/

#if defined(__ARMCC_VERSION)
  #if (__ARMCC_VERSION >= 6010050)
    #pragma clang diagnostic push
  #else
    #pragma push
    #pragma anon_unions
  #endif
#elif defined(__GNUC__)
  /* anonymous unions are enabled by default */
#elif defined(__IAR_SYSTEMS_ICC__)
  #pragma language=extended
#else
  #error Not supported compiler type
#endif

/* ----------------------------------------------------------------------------
   -- ADC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
 * @{
 */

/** ADC - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
       uint8_t RESERVED_0[8];
  __IO uint32_t CTRL;                              /**< ADC Control Register, offset: 0x10 */
  __IO uint32_t STAT;                              /**< ADC Status Register, offset: 0x14 */
  __IO uint32_t IE;                                /**< Interrupt Enable Register, offset: 0x18 */
  __IO uint32_t DE;                                /**< DMA Enable Register, offset: 0x1C */
  __IO uint32_t CFG;                               /**< ADC Configuration Register, offset: 0x20 */
  __IO uint32_t PAUSE;                             /**< ADC Pause Register, offset: 0x24 */
       uint8_t RESERVED_1[12];
  __O  uint32_t SWTRIG;                            /**< Software Trigger Register, offset: 0x34 */
  __IO uint32_t TSTAT;                             /**< Trigger Status Register, offset: 0x38 */
       uint8_t RESERVED_2[4];
  __IO uint32_t OFSTRIM;                           /**< ADC Offset Trim Register, offset: 0x40 */
       uint8_t RESERVED_3[92];
  __IO uint32_t TCTRL[4];                          /**< Trigger Control Register, array offset: 0xA0, array step: 0x4 */
       uint8_t RESERVED_4[48];
  __IO uint32_t FCTRL[2];                          /**< FIFO Control Register, array offset: 0xE0, array step: 0x4 */
       uint8_t RESERVED_5[8];
  __I  uint32_t GCC[2];                            /**< Gain Calibration Control, array offset: 0xF0, array step: 0x4 */
  __IO uint32_t GCR[2];                            /**< Gain Calculation Result, array offset: 0xF8, array step: 0x4 */
  struct {                                         /* offset: 0x100, array step: 0x8 */
    __IO uint32_t CMDL;                              /**< ADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */
    __IO uint32_t CMDH;                              /**< ADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */
  } CMD[15];
       uint8_t RESERVED_6[136];
  __IO uint32_t CV[15];                            /**< Compare Value Register, array offset: 0x200, array step: 0x4 */
       uint8_t RESERVED_7[196];
  __I  uint32_t RESFIFO[2];                        /**< ADC Data Result FIFO Register, array offset: 0x300, array step: 0x4 */
       uint8_t RESERVED_8[248];
  __IO uint32_t CAL_GAR[33];                       /**< Calibration General A-Side Registers, array offset: 0x400, array step: 0x4 */
       uint8_t RESERVED_9[124];
  __IO uint32_t CAL_GBR[33];                       /**< Calibration General B-Side Registers, array offset: 0x500, array step: 0x4 */
} ADC_Type;

/* ----------------------------------------------------------------------------
   -- ADC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup ADC_Register_Masks ADC Register Masks
 * @{
 */

/*! @name VERID - Version ID Register */
/*! @{ */

#define ADC_VERID_RES_MASK                       (0x1U)
#define ADC_VERID_RES_SHIFT                      (0U)
/*! RES - Resolution
 *  0b0..Up to 13-bit differential/12-bit single ended resolution supported.
 *  0b1..Up to 16-bit differential/16-bit single ended resolution supported.
 */
#define ADC_VERID_RES(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK)

#define ADC_VERID_DIFFEN_MASK                    (0x2U)
#define ADC_VERID_DIFFEN_SHIFT                   (1U)
/*! DIFFEN - Differential Supported
 *  0b0..Differential operation not supported.
 *  0b1..Differential operation supported. CMDLa[CTYPE] controls fields implemented.
 */
#define ADC_VERID_DIFFEN(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK)

#define ADC_VERID_MVI_MASK                       (0x8U)
#define ADC_VERID_MVI_SHIFT                      (3U)
/*! MVI - Multi Vref Implemented
 *  0b0..Single voltage reference high (VREFH) input supported.
 *  0b1..Multiple voltage reference high (VREFH) inputs supported.
 */
#define ADC_VERID_MVI(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK)

#define ADC_VERID_CSW_MASK                       (0x70U)
#define ADC_VERID_CSW_SHIFT                      (4U)
/*! CSW - Channel Scale Width
 *  0b000..Channel scaling not supported.
 *  0b001..Channel scaling supported. 1-bit CSCALE control field.
 *  0b110..Channel scaling supported. 6-bit CSCALE control field.
 */
#define ADC_VERID_CSW(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK)

#define ADC_VERID_VR1RNGI_MASK                   (0x100U)
#define ADC_VERID_VR1RNGI_SHIFT                  (8U)
/*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented
 *  0b0..Range control not required. CFG[VREF1RNG] is not implemented.
 *  0b1..Range control required. CFG[VREF1RNG] is implemented.
 */
#define ADC_VERID_VR1RNGI(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK)

#define ADC_VERID_IADCKI_MASK                    (0x200U)
#define ADC_VERID_IADCKI_SHIFT                   (9U)
/*! IADCKI - Internal ADC Clock implemented
 *  0b0..Internal clock source not implemented.
 *  0b1..Internal clock source (and CFG[ADCKEN]) implemented.
 */
#define ADC_VERID_IADCKI(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK)

#define ADC_VERID_CALOFSI_MASK                   (0x400U)
#define ADC_VERID_CALOFSI_SHIFT                  (10U)
/*! CALOFSI - Calibration Function Implemented
 *  0b0..Calibration Not Implemented.
 *  0b1..Calibration Implemented.
 */
#define ADC_VERID_CALOFSI(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK)

#define ADC_VERID_NUM_SEC_MASK                   (0x800U)
#define ADC_VERID_NUM_SEC_SHIFT                  (11U)
/*! NUM_SEC - Number of Single Ended Outputs Supported
 *  0b0..This design supports one single ended conversion at a time.
 *  0b1..This design supports two simultanious single ended conversions.
 */
#define ADC_VERID_NUM_SEC(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_SEC_SHIFT)) & ADC_VERID_NUM_SEC_MASK)

#define ADC_VERID_NUM_FIFO_MASK                  (0x7000U)
#define ADC_VERID_NUM_FIFO_SHIFT                 (12U)
/*! NUM_FIFO - Number of FIFOs
 *  0b000..N/A
 *  0b001..This design supports one result FIFO.
 *  0b010..This design supports two result FIFOs.
 *  0b011..This design supports three result FIFOs.
 *  0b100..This design supports four result FIFOs.
 */
#define ADC_VERID_NUM_FIFO(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_FIFO_SHIFT)) & ADC_VERID_NUM_FIFO_MASK)

#define ADC_VERID_MINOR_MASK                     (0xFF0000U)
#define ADC_VERID_MINOR_SHIFT                    (16U)
/*! MINOR - Minor Version Number
 */
#define ADC_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK)

#define ADC_VERID_MAJOR_MASK                     (0xFF000000U)
#define ADC_VERID_MAJOR_SHIFT                    (24U)
/*! MAJOR - Major Version Number
 */
#define ADC_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK)
/*! @} */

/*! @name PARAM - Parameter Register */
/*! @{ */

#define ADC_PARAM_TRIG_NUM_MASK                  (0xFFU)
#define ADC_PARAM_TRIG_NUM_SHIFT                 (0U)
/*! TRIG_NUM - Trigger Number
 */
#define ADC_PARAM_TRIG_NUM(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK)

#define ADC_PARAM_FIFOSIZE_MASK                  (0xFF00U)
#define ADC_PARAM_FIFOSIZE_SHIFT                 (8U)
/*! FIFOSIZE - Result FIFO Depth
 *  0b00000001..Result FIFO depth = 1 dataword.
 *  0b00000100..Result FIFO depth = 4 datawords.
 *  0b00001000..Result FIFO depth = 8 datawords.
 *  0b00010000..Result FIFO depth = 16 datawords.
 *  0b00100000..Result FIFO depth = 32 datawords.
 *  0b01000000..Result FIFO depth = 64 datawords.
 */
#define ADC_PARAM_FIFOSIZE(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK)

#define ADC_PARAM_CV_NUM_MASK                    (0xFF0000U)
#define ADC_PARAM_CV_NUM_SHIFT                   (16U)
/*! CV_NUM - Compare Value Number
 */
#define ADC_PARAM_CV_NUM(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK)

#define ADC_PARAM_CMD_NUM_MASK                   (0xFF000000U)
#define ADC_PARAM_CMD_NUM_SHIFT                  (24U)
/*! CMD_NUM - Command Buffer Number
 */
#define ADC_PARAM_CMD_NUM(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK)
/*! @} */

/*! @name CTRL - ADC Control Register */
/*! @{ */

#define ADC_CTRL_ADCEN_MASK                      (0x1U)
#define ADC_CTRL_ADCEN_SHIFT                     (0U)
/*! ADCEN - ADC Enable
 *  0b0..ADC is disabled.
 *  0b1..ADC is enabled.
 */
#define ADC_CTRL_ADCEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK)

#define ADC_CTRL_RST_MASK                        (0x2U)
#define ADC_CTRL_RST_SHIFT                       (1U)
/*! RST - Software Reset
 *  0b0..ADC logic is not reset.
 *  0b1..ADC logic is reset.
 */
#define ADC_CTRL_RST(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK)

#define ADC_CTRL_DOZEN_MASK                      (0x4U)
#define ADC_CTRL_DOZEN_SHIFT                     (2U)
/*! DOZEN - Doze Enable
 *  0b0..ADC is enabled in low power mode.
 *  0b1..ADC is disabled in low power mode.
 */
#define ADC_CTRL_DOZEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK)

#define ADC_CTRL_CAL_REQ_MASK                    (0x8U)
#define ADC_CTRL_CAL_REQ_SHIFT                   (3U)
/*! CAL_REQ - Auto-Calibration Request
 *  0b0..No request for auto-calibration has been made.
 *  0b1..A request for auto-calibration has been made
 */
#define ADC_CTRL_CAL_REQ(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_REQ_SHIFT)) & ADC_CTRL_CAL_REQ_MASK)

#define ADC_CTRL_CALOFS_MASK                     (0x10U)
#define ADC_CTRL_CALOFS_SHIFT                    (4U)
/*! CALOFS - Configure for offset calibration function
 *  0b0..Calibration function disabled
 *  0b1..Request for offset calibration function
 */
#define ADC_CTRL_CALOFS(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALOFS_SHIFT)) & ADC_CTRL_CALOFS_MASK)

#define ADC_CTRL_RSTFIFO0_MASK                   (0x100U)
#define ADC_CTRL_RSTFIFO0_SHIFT                  (8U)
/*! RSTFIFO0 - Reset FIFO 0
 *  0b0..No effect.
 *  0b1..FIFO 0 is reset.
 */
#define ADC_CTRL_RSTFIFO0(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO0_SHIFT)) & ADC_CTRL_RSTFIFO0_MASK)

#define ADC_CTRL_RSTFIFO1_MASK                   (0x200U)
#define ADC_CTRL_RSTFIFO1_SHIFT                  (9U)
/*! RSTFIFO1 - Reset FIFO 1
 *  0b0..No effect.
 *  0b1..FIFO 1 is reset.
 */
#define ADC_CTRL_RSTFIFO1(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO1_SHIFT)) & ADC_CTRL_RSTFIFO1_MASK)

#define ADC_CTRL_CAL_AVGS_MASK                   (0x70000U)
#define ADC_CTRL_CAL_AVGS_SHIFT                  (16U)
/*! CAL_AVGS - Auto-Calibration Averages
 *  0b000..Single conversion.
 *  0b001..2 conversions averaged.
 *  0b010..4 conversions averaged.
 *  0b011..8 conversions averaged.
 *  0b100..16 conversions averaged.
 *  0b101..32 conversions averaged.
 *  0b110..64 conversions averaged.
 *  0b111..128 conversions averaged.
 */
#define ADC_CTRL_CAL_AVGS(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_AVGS_SHIFT)) & ADC_CTRL_CAL_AVGS_MASK)
/*! @} */

/*! @name STAT - ADC Status Register */
/*! @{ */

#define ADC_STAT_RDY0_MASK                       (0x1U)
#define ADC_STAT_RDY0_SHIFT                      (0U)
/*! RDY0 - Result FIFO 0 Ready Flag
 *  0b0..Result FIFO 0 data level not above watermark level.
 *  0b1..Result FIFO 0 holding data above watermark level.
 */
#define ADC_STAT_RDY0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY0_SHIFT)) & ADC_STAT_RDY0_MASK)

#define ADC_STAT_FOF0_MASK                       (0x2U)
#define ADC_STAT_FOF0_SHIFT                      (1U)
/*! FOF0 - Result FIFO 0 Overflow Flag
 *  0b0..No result FIFO 0 overflow has occurred since the last time the flag was cleared.
 *  0b1..At least one result FIFO 0 overflow has occurred since the last time the flag was cleared.
 */
#define ADC_STAT_FOF0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF0_SHIFT)) & ADC_STAT_FOF0_MASK)

#define ADC_STAT_RDY1_MASK                       (0x4U)
#define ADC_STAT_RDY1_SHIFT                      (2U)
/*! RDY1 - Result FIFO1 Ready Flag
 *  0b0..Result FIFO1 data level not above watermark level.
 *  0b1..Result FIFO1 holding data above watermark level.
 */
#define ADC_STAT_RDY1(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY1_SHIFT)) & ADC_STAT_RDY1_MASK)

#define ADC_STAT_FOF1_MASK                       (0x8U)
#define ADC_STAT_FOF1_SHIFT                      (3U)
/*! FOF1 - Result FIFO1 Overflow Flag
 *  0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared.
 *  0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared.
 */
#define ADC_STAT_FOF1(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF1_SHIFT)) & ADC_STAT_FOF1_MASK)

#define ADC_STAT_TEXC_INT_MASK                   (0x100U)
#define ADC_STAT_TEXC_INT_SHIFT                  (8U)
/*! TEXC_INT - Interrupt Flag For High Priority Trigger Exception
 *  0b0..No trigger exceptions have occurred.
 *  0b1..A trigger exception has occurred and is pending acknowledgement.
 */
#define ADC_STAT_TEXC_INT(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TEXC_INT_SHIFT)) & ADC_STAT_TEXC_INT_MASK)

#define ADC_STAT_TCOMP_INT_MASK                  (0x200U)
#define ADC_STAT_TCOMP_INT_SHIFT                 (9U)
/*! TCOMP_INT - Interrupt Flag For Trigger Completion
 *  0b0..Either IE[TCOMP_IE] is set to 0, or no trigger sequences have run to completion.
 *  0b1..Trigger sequence has been completed and all data is stored in the associated FIFO.
 */
#define ADC_STAT_TCOMP_INT(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TCOMP_INT_SHIFT)) & ADC_STAT_TCOMP_INT_MASK)

#define ADC_STAT_CAL_RDY_MASK                    (0x400U)
#define ADC_STAT_CAL_RDY_SHIFT                   (10U)
/*! CAL_RDY - Calibration Ready
 *  0b0..Calibration is incomplete or hasn't been ran.
 *  0b1..The ADC is calibrated.
 */
#define ADC_STAT_CAL_RDY(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CAL_RDY_SHIFT)) & ADC_STAT_CAL_RDY_MASK)

#define ADC_STAT_ADC_ACTIVE_MASK                 (0x800U)
#define ADC_STAT_ADC_ACTIVE_SHIFT                (11U)
/*! ADC_ACTIVE - ADC Active
 *  0b0..The ADC is IDLE. There are no pending triggers to service and no active commands are being processed.
 *  0b1..The ADC is processing a conversion, running through the power up delay, or servicing a trigger.
 */
#define ADC_STAT_ADC_ACTIVE(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK)

#define ADC_STAT_TRGACT_MASK                     (0x30000U)
#define ADC_STAT_TRGACT_SHIFT                    (16U)
/*! TRGACT - Trigger Active
 *  0b00..Command (sequence) associated with Trigger 0 currently being executed.
 *  0b01..Command (sequence) associated with Trigger 1 currently being executed.
 *  0b10..Command (sequence) associated with Trigger 2 currently being executed.
 *  0b11..Command (sequence) associated with Trigger 3 currently being executed.
 */
#define ADC_STAT_TRGACT(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK)

#define ADC_STAT_CMDACT_MASK                     (0xF000000U)
#define ADC_STAT_CMDACT_SHIFT                    (24U)
/*! CMDACT - Command Active
 *  0b0000..No command is currently in progress.
 *  0b0001..Command 1 currently being executed.
 *  0b0010..Command 2 currently being executed.
 *  0b0011-0b1111..Associated command number is currently being executed.
 */
#define ADC_STAT_CMDACT(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK)
/*! @} */

/*! @name IE - Interrupt Enable Register */
/*! @{ */

#define ADC_IE_FWMIE0_MASK                       (0x1U)
#define ADC_IE_FWMIE0_SHIFT                      (0U)
/*! FWMIE0 - FIFO 0 Watermark Interrupt Enable
 *  0b0..FIFO 0 watermark interrupts are not enabled.
 *  0b1..FIFO 0 watermark interrupts are enabled.
 */
#define ADC_IE_FWMIE0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE0_SHIFT)) & ADC_IE_FWMIE0_MASK)

#define ADC_IE_FOFIE0_MASK                       (0x2U)
#define ADC_IE_FOFIE0_SHIFT                      (1U)
/*! FOFIE0 - Result FIFO 0 Overflow Interrupt Enable
 *  0b0..FIFO 0 overflow interrupts are not enabled.
 *  0b1..FIFO 0 overflow interrupts are enabled.
 */
#define ADC_IE_FOFIE0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE0_SHIFT)) & ADC_IE_FOFIE0_MASK)

#define ADC_IE_FWMIE1_MASK                       (0x4U)
#define ADC_IE_FWMIE1_SHIFT                      (2U)
/*! FWMIE1 - FIFO1 Watermark Interrupt Enable
 *  0b0..FIFO1 watermark interrupts are not enabled.
 *  0b1..FIFO1 watermark interrupts are enabled.
 */
#define ADC_IE_FWMIE1(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE1_SHIFT)) & ADC_IE_FWMIE1_MASK)

#define ADC_IE_FOFIE1_MASK                       (0x8U)
#define ADC_IE_FOFIE1_SHIFT                      (3U)
/*! FOFIE1 - Result FIFO1 Overflow Interrupt Enable
 *  0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared.
 *  0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared.
 */
#define ADC_IE_FOFIE1(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE1_SHIFT)) & ADC_IE_FOFIE1_MASK)

#define ADC_IE_TEXC_IE_MASK                      (0x100U)
#define ADC_IE_TEXC_IE_SHIFT                     (8U)
/*! TEXC_IE - Trigger Exception Interrupt Enable
 *  0b0..Trigger exception interrupts are disabled.
 *  0b1..Trigger exception interrupts are enabled.
 */
#define ADC_IE_TEXC_IE(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_IE_TEXC_IE_SHIFT)) & ADC_IE_TEXC_IE_MASK)

#define ADC_IE_TCOMP_IE_MASK                     (0xF0000U)
#define ADC_IE_TCOMP_IE_SHIFT                    (16U)
/*! TCOMP_IE - Trigger Completion Interrupt Enable
 *  0b0000..Trigger completion interrupts are disabled.
 *  0b0001..Trigger completion interrupts are enabled for trigger source 0 only.
 *  0b0010..Trigger completion interrupts are enabled for trigger source 1 only.
 *  0b0011-0b1110..Associated trigger completion interrupts are enabled.
 *  0b1111..Trigger completion interrupts are enabled for every trigger source.
 */
#define ADC_IE_TCOMP_IE(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_IE_TCOMP_IE_SHIFT)) & ADC_IE_TCOMP_IE_MASK)
/*! @} */

/*! @name DE - DMA Enable Register */
/*! @{ */

#define ADC_DE_FWMDE0_MASK                       (0x1U)
#define ADC_DE_FWMDE0_SHIFT                      (0U)
/*! FWMDE0 - FIFO 0 Watermark DMA Enable
 *  0b0..DMA request disabled.
 *  0b1..DMA request enabled.
 */
#define ADC_DE_FWMDE0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE0_SHIFT)) & ADC_DE_FWMDE0_MASK)

#define ADC_DE_FWMDE1_MASK                       (0x2U)
#define ADC_DE_FWMDE1_SHIFT                      (1U)
/*! FWMDE1 - FIFO1 Watermark DMA Enable
 *  0b0..DMA request disabled.
 *  0b1..DMA request enabled.
 */
#define ADC_DE_FWMDE1(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE1_SHIFT)) & ADC_DE_FWMDE1_MASK)
/*! @} */

/*! @name CFG - ADC Configuration Register */
/*! @{ */

#define ADC_CFG_TPRICTRL_MASK                    (0x3U)
#define ADC_CFG_TPRICTRL_SHIFT                   (0U)
/*! TPRICTRL - ADC trigger priority control
 *  0b00..If a higher priority trigger is detected during command processing, the current conversion is aborted
 *        and the new command specified by the trigger is started.
 *  0b01..If a higher priority trigger is received during command processing, the current command is stopped after
 *        completing the current conversion. If averaging is enabled, the averaging loop will be completed.
 *        However, CMDHa[LOOP] will be ignored and the higher priority trigger will be serviced.
 *  0b10..If a higher priority trigger is received during command processing, the current command will be
 *        completed (averaging, looping, compare) before servicing the higher priority trigger.
 *  0b11..RESERVED
 */
#define ADC_CFG_TPRICTRL(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK)

#define ADC_CFG_PWRSEL_MASK                      (0x30U)
#define ADC_CFG_PWRSEL_SHIFT                     (4U)
/*! PWRSEL - Power Configuration Select
 *  0b0x..Low power setting.
 *  0b1x..High power setting.
 */
#define ADC_CFG_PWRSEL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK)

#define ADC_CFG_REFSEL_MASK                      (0xC0U)
#define ADC_CFG_REFSEL_SHIFT                     (6U)
/*! REFSEL - Voltage Reference Selection
 *  0b00..(Default) Option 1 setting.
 *  0b01..Option 2 setting.
 *  0b10..Option 3 setting.
 *  0b11..Reserved
 */
#define ADC_CFG_REFSEL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)

#define ADC_CFG_TRES_MASK                        (0x100U)
#define ADC_CFG_TRES_SHIFT                       (8U)
/*! TRES - Trigger Resume Enable
 *  0b0..Trigger sequences interrupted by a high priority trigger exception are not automatically resumed or restarted.
 *  0b1..Trigger sequences interrupted by a high priority trigger exception are automatically resumed or restarted.
 */
#define ADC_CFG_TRES(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TRES_SHIFT)) & ADC_CFG_TRES_MASK)

#define ADC_CFG_TCMDRES_MASK                     (0x200U)
#define ADC_CFG_TCMDRES_SHIFT                    (9U)
/*! TCMDRES - Trigger Command Resume
 *  0b0..Trigger sequences interrupted by a high priority trigger exception is automatically restarted.
 *  0b1..Trigger sequences interrupted by a high priority trigger exception is resumed from the command executing before the exception.
 */
#define ADC_CFG_TCMDRES(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TCMDRES_SHIFT)) & ADC_CFG_TCMDRES_MASK)

#define ADC_CFG_HPT_EXDI_MASK                    (0x400U)
#define ADC_CFG_HPT_EXDI_SHIFT                   (10U)
/*! HPT_EXDI - High Priority Trigger Exception Disable
 *  0b0..High priority trigger exceptions are enabled.
 *  0b1..High priority trigger exceptions are disabled.
 */
#define ADC_CFG_HPT_EXDI(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CFG_HPT_EXDI_SHIFT)) & ADC_CFG_HPT_EXDI_MASK)

#define ADC_CFG_PUDLY_MASK                       (0xFF0000U)
#define ADC_CFG_PUDLY_SHIFT                      (16U)
/*! PUDLY - Power Up Delay
 */
#define ADC_CFG_PUDLY(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK)

#define ADC_CFG_PWREN_MASK                       (0x10000000U)
#define ADC_CFG_PWREN_SHIFT                      (28U)
/*! PWREN - ADC Analog Pre-Enable
 *  0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays.
 *  0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost
 *       of higher DC current consumption). A single power up delay (CFG[PUDLY]) is executed immediately once PWREN
 *       is set, and any detected trigger does not begin ADC operation until the power up delay time has passed.
 *       After this initial delay expires the analog will remain pre-enabled, and no additional delays will be
 *       executed.
 */
#define ADC_CFG_PWREN(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK)
/*! @} */

/*! @name PAUSE - ADC Pause Register */
/*! @{ */

#define ADC_PAUSE_PAUSEDLY_MASK                  (0x1FFU)
#define ADC_PAUSE_PAUSEDLY_SHIFT                 (0U)
/*! PAUSEDLY - Pause Delay
 */
#define ADC_PAUSE_PAUSEDLY(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK)

#define ADC_PAUSE_PAUSEEN_MASK                   (0x80000000U)
#define ADC_PAUSE_PAUSEEN_SHIFT                  (31U)
/*! PAUSEEN - PAUSE Option Enable
 *  0b0..Pause operation disabled
 *  0b1..Pause operation enabled
 */
#define ADC_PAUSE_PAUSEEN(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK)
/*! @} */

/*! @name SWTRIG - Software Trigger Register */
/*! @{ */

#define ADC_SWTRIG_SWT0_MASK                     (0x1U)
#define ADC_SWTRIG_SWT0_SHIFT                    (0U)
/*! SWT0 - Software trigger 0 event
 *  0b0..No trigger 0 event generated.
 *  0b1..Trigger 0 event generated.
 */
#define ADC_SWTRIG_SWT0(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK)

#define ADC_SWTRIG_SWT1_MASK                     (0x2U)
#define ADC_SWTRIG_SWT1_SHIFT                    (1U)
/*! SWT1 - Software trigger 1 event
 *  0b0..No trigger 1 event generated.
 *  0b1..Trigger 1 event generated.
 */
#define ADC_SWTRIG_SWT1(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK)

#define ADC_SWTRIG_SWT2_MASK                     (0x4U)
#define ADC_SWTRIG_SWT2_SHIFT                    (2U)
/*! SWT2 - Software trigger 2 event
 *  0b0..No trigger 2 event generated.
 *  0b1..Trigger 2 event generated.
 */
#define ADC_SWTRIG_SWT2(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK)

#define ADC_SWTRIG_SWT3_MASK                     (0x8U)
#define ADC_SWTRIG_SWT3_SHIFT                    (3U)
/*! SWT3 - Software trigger 3 event
 *  0b0..No trigger 3 event generated.
 *  0b1..Trigger 3 event generated.
 */
#define ADC_SWTRIG_SWT3(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK)
/*! @} */

/*! @name TSTAT - Trigger Status Register */
/*! @{ */

#define ADC_TSTAT_TEXC_NUM_MASK                  (0xFU)
#define ADC_TSTAT_TEXC_NUM_SHIFT                 (0U)
/*! TEXC_NUM - Trigger Exception Number
 *  0b0000..No triggers have been interrupted by a high priority exception. Or CFG[TRES] = 1.
 *  0b0001..Trigger 0 has been interrupted by a high priority exception.
 *  0b0010..Trigger 1 has been interrupted by a high priority exception.
 *  0b0011-0b1110..Associated trigger sequence has interrupted by a high priority exception.
 *  0b1111..Every trigger sequence has been interrupted by a high priority exception.
 */
#define ADC_TSTAT_TEXC_NUM(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TEXC_NUM_SHIFT)) & ADC_TSTAT_TEXC_NUM_MASK)

#define ADC_TSTAT_TCOMP_FLAG_MASK                (0xF0000U)
#define ADC_TSTAT_TCOMP_FLAG_SHIFT               (16U)
/*! TCOMP_FLAG - Trigger Completion Flag
 *  0b0000..No triggers have been completed. Trigger completion interrupts are disabled.
 *  0b0001..Trigger 0 has been completed and triger 0 has enabled completion interrupts.
 *  0b0010..Trigger 1 has been completed and triger 1 has enabled completion interrupts.
 *  0b0011-0b1110..Associated trigger sequence has completed and has enabled completion interrupts.
 *  0b1111..Every trigger sequence has been completed and every trigger has enabled completion interrupts.
 */
#define ADC_TSTAT_TCOMP_FLAG(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TCOMP_FLAG_SHIFT)) & ADC_TSTAT_TCOMP_FLAG_MASK)
/*! @} */

/*! @name OFSTRIM - ADC Offset Trim Register */
/*! @{ */

#define ADC_OFSTRIM_OFSTRIM_A_MASK               (0x1FU)
#define ADC_OFSTRIM_OFSTRIM_A_SHIFT              (0U)
/*! OFSTRIM_A - Trim for offset
 */
#define ADC_OFSTRIM_OFSTRIM_A(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_A_SHIFT)) & ADC_OFSTRIM_OFSTRIM_A_MASK)

#define ADC_OFSTRIM_OFSTRIM_B_MASK               (0x1F0000U)
#define ADC_OFSTRIM_OFSTRIM_B_SHIFT              (16U)
/*! OFSTRIM_B - Trim for offset
 */
#define ADC_OFSTRIM_OFSTRIM_B(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_B_SHIFT)) & ADC_OFSTRIM_OFSTRIM_B_MASK)
/*! @} */

/*! @name TCTRL - Trigger Control Register */
/*! @{ */

#define ADC_TCTRL_HTEN_MASK                      (0x1U)
#define ADC_TCTRL_HTEN_SHIFT                     (0U)
/*! HTEN - Trigger enable
 *  0b0..Hardware trigger source disabled
 *  0b1..Hardware trigger source enabled
 */
#define ADC_TCTRL_HTEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK)

#define ADC_TCTRL_FIFO_SEL_A_MASK                (0x2U)
#define ADC_TCTRL_FIFO_SEL_A_SHIFT               (1U)
/*! FIFO_SEL_A - SAR Result Destination For Channel A
 *  0b0..Result written to FIFO 0
 *  0b1..Result written to FIFO 1
 */
#define ADC_TCTRL_FIFO_SEL_A(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_A_SHIFT)) & ADC_TCTRL_FIFO_SEL_A_MASK)

#define ADC_TCTRL_FIFO_SEL_B_MASK                (0x4U)
#define ADC_TCTRL_FIFO_SEL_B_SHIFT               (2U)
/*! FIFO_SEL_B - SAR Result Destination For Channel B
 *  0b0..Result written to FIFO 0
 *  0b1..Result written to FIFO 1
 */
#define ADC_TCTRL_FIFO_SEL_B(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_B_SHIFT)) & ADC_TCTRL_FIFO_SEL_B_MASK)

#define ADC_TCTRL_TPRI_MASK                      (0x300U)
#define ADC_TCTRL_TPRI_SHIFT                     (8U)
/*! TPRI - Trigger priority setting
 *  0b00..Set to highest priority, Level 1
 *  0b01-0b10..Set to corresponding priority level
 *  0b11..Set to lowest priority, Level 4
 */
#define ADC_TCTRL_TPRI(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK)

#define ADC_TCTRL_RSYNC_MASK                     (0x8000U)
#define ADC_TCTRL_RSYNC_SHIFT                    (15U)
/*! RSYNC - Trigger Resync
 */
#define ADC_TCTRL_RSYNC(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_RSYNC_SHIFT)) & ADC_TCTRL_RSYNC_MASK)

#define ADC_TCTRL_TDLY_MASK                      (0xF0000U)
#define ADC_TCTRL_TDLY_SHIFT                     (16U)
/*! TDLY - Trigger delay select
 */
#define ADC_TCTRL_TDLY(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK)

#define ADC_TCTRL_TCMD_MASK                      (0xF000000U)
#define ADC_TCTRL_TCMD_SHIFT                     (24U)
/*! TCMD - Trigger command select
 *  0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
 *  0b0001..CMD1 is executed
 *  0b0010-0b1110..Corresponding CMD is executed
 *  0b1111..CMD15 is executed
 */
#define ADC_TCTRL_TCMD(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK)
/*! @} */

/* The count of ADC_TCTRL */
#define ADC_TCTRL_COUNT                          (4U)

/*! @name FCTRL - FIFO Control Register */
/*! @{ */

#define ADC_FCTRL_FCOUNT_MASK                    (0x1FU)
#define ADC_FCTRL_FCOUNT_SHIFT                   (0U)
/*! FCOUNT - Result FIFO counter
 */
#define ADC_FCTRL_FCOUNT(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK)

#define ADC_FCTRL_FWMARK_MASK                    (0xF0000U)
#define ADC_FCTRL_FWMARK_SHIFT                   (16U)
/*! FWMARK - Watermark level selection
 */
#define ADC_FCTRL_FWMARK(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK)
/*! @} */

/* The count of ADC_FCTRL */
#define ADC_FCTRL_COUNT                          (2U)

/*! @name GCC - Gain Calibration Control */
/*! @{ */

#define ADC_GCC_GAIN_CAL_MASK                    (0xFFFFU)
#define ADC_GCC_GAIN_CAL_SHIFT                   (0U)
/*! GAIN_CAL - Gain Calibration Value
 */
#define ADC_GCC_GAIN_CAL(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_GCC_GAIN_CAL_SHIFT)) & ADC_GCC_GAIN_CAL_MASK)

#define ADC_GCC_RDY_MASK                         (0x1000000U)
#define ADC_GCC_RDY_SHIFT                        (24U)
/*! RDY - Gain Calibration Value Valid
 *  0b0..The gain calibration value is invalid. Run the auto-calibration routine for this value to be written.
 *  0b1..The gain calibration value is valid. It should be used to update the GCRa[GCALR] register field.
 */
#define ADC_GCC_RDY(x)                           (((uint32_t)(((uint32_t)(x)) << ADC_GCC_RDY_SHIFT)) & ADC_GCC_RDY_MASK)
/*! @} */

/* The count of ADC_GCC */
#define ADC_GCC_COUNT                            (2U)

/*! @name GCR - Gain Calculation Result */
/*! @{ */

#define ADC_GCR_GCALR_MASK                       (0xFFFFU)
#define ADC_GCR_GCALR_SHIFT                      (0U)
/*! GCALR - Gain Calculation Result
 */
#define ADC_GCR_GCALR(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_GCR_GCALR_SHIFT)) & ADC_GCR_GCALR_MASK)

#define ADC_GCR_RDY_MASK                         (0x1000000U)
#define ADC_GCR_RDY_SHIFT                        (24U)
/*! RDY - Gain Calculation Ready
 *  0b0..The gain offset calculation value is invalid.
 *  0b1..The gain calibration value is valid.
 */
#define ADC_GCR_RDY(x)                           (((uint32_t)(((uint32_t)(x)) << ADC_GCR_RDY_SHIFT)) & ADC_GCR_RDY_MASK)
/*! @} */

/* The count of ADC_GCR */
#define ADC_GCR_COUNT                            (2U)

/*! @name CMDL - ADC Command Low Buffer Register */
/*! @{ */

#define ADC_CMDL_ADCH_MASK                       (0x1FU)
#define ADC_CMDL_ADCH_SHIFT                      (0U)
/*! ADCH - Input channel select
 *  0b00000..Select CH0A or CH0B or CH0A/CH0B pair.
 *  0b00001..Select CH1A or CH1B or CH1A/CH1B pair.
 *  0b00010..Select CH2A or CH2B or CH2A/CH2B pair.
 *  0b00011..Select CH3A or CH3B or CH3A/CH3B pair.
 *  0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
 *  0b11110..Select CH30A or CH30B or CH30A/CH30B pair.
 *  0b11111..Select CH31A or CH31B or CH31A/CH31B pair.
 */
#define ADC_CMDL_ADCH(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK)

#define ADC_CMDL_CTYPE_MASK                      (0x60U)
#define ADC_CMDL_CTYPE_SHIFT                     (5U)
/*! CTYPE - Conversion Type
 *  0b00..Single-Ended Mode. Only A side channel is converted.
 *  0b01..Single-Ended Mode. Only B side channel is converted.
 *  0b10..Differential Mode. A-B.
 *  0b11..Dual-Single-Ended Mode. Both A side and B side channels are converted independently.
 */
#define ADC_CMDL_CTYPE(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CTYPE_SHIFT)) & ADC_CMDL_CTYPE_MASK)

#define ADC_CMDL_MODE_MASK                       (0x80U)
#define ADC_CMDL_MODE_SHIFT                      (7U)
/*! MODE - Select resolution of conversions
 *  0b0..Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output.
 *  0b1..High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output.
 */
#define ADC_CMDL_MODE(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_MODE_SHIFT)) & ADC_CMDL_MODE_MASK)

#define ADC_CMDL_ALTB_ADCH_MASK                  (0x1F0000U)
#define ADC_CMDL_ALTB_ADCH_SHIFT                 (16U)
/*! ALTB_ADCH - Alternate Channel B Input channel select
 *  0b00000..Select CH0B
 *  0b00001..Select CH1B
 *  0b00010..Select CH2B
 *  0b00011..Select CH3B
 *  0b00100-0b11101..Select corresponding channel CHnB
 *  0b11110..Select CH30B
 *  0b11111..Select CH31B
 */
#define ADC_CMDL_ALTB_ADCH(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ALTB_ADCH_SHIFT)) & ADC_CMDL_ALTB_ADCH_MASK)

#define ADC_CMDL_ALTBEN_MASK                     (0x200000U)
#define ADC_CMDL_ALTBEN_SHIFT                    (21U)
/*! ALTBEN - Alternate Channel B Select Enable
 *  0b0..ALTBEN_ADCH disabled. Channel A and Channel B inputs are selected based on ADCH settings.
 *  0b1..ALTBEN_ADCH enabled. Channel A inputs selected by ADCH setting and Channel B inputs selected by ALTB_ADCH setting.
 */
#define ADC_CMDL_ALTBEN(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ALTBEN_SHIFT)) & ADC_CMDL_ALTBEN_MASK)
/*! @} */

/* The count of ADC_CMDL */
#define ADC_CMDL_COUNT                           (15U)

/*! @name CMDH - ADC Command High Buffer Register */
/*! @{ */

#define ADC_CMDH_CMPEN_MASK                      (0x3U)
#define ADC_CMDH_CMPEN_SHIFT                     (0U)
/*! CMPEN - Compare Function Enable
 *  0b00..Compare disabled.
 *  0b01..Reserved
 *  0b10..Compare enabled. Store on true.
 *  0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.
 */
#define ADC_CMDH_CMPEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK)

#define ADC_CMDH_WAIT_TRIG_MASK                  (0x4U)
#define ADC_CMDH_WAIT_TRIG_SHIFT                 (2U)
/*! WAIT_TRIG - Wait for trigger assertion before execution.
 *  0b0..This command will be automatically executed.
 *  0b1..The active trigger must be asserted again before executing this command.
 */
#define ADC_CMDH_WAIT_TRIG(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_WAIT_TRIG_SHIFT)) & ADC_CMDH_WAIT_TRIG_MASK)

#define ADC_CMDH_LWI_MASK                        (0x80U)
#define ADC_CMDH_LWI_SHIFT                       (7U)
/*! LWI - Loop with Increment
 *  0b0..Auto channel increment disabled
 *  0b1..Auto channel increment enabled
 */
#define ADC_CMDH_LWI(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK)

#define ADC_CMDH_STS_MASK                        (0x700U)
#define ADC_CMDH_STS_SHIFT                       (8U)
/*! STS - Sample Time Select
 *  0b000..Minimum sample time of 3.5 ADCK cycles.
 *  0b001..3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time.
 *  0b010..3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time.
 *  0b011..3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time.
 *  0b100..3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time.
 *  0b101..3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time.
 *  0b110..3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time.
 *  0b111..3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time.
 */
#define ADC_CMDH_STS(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK)

#define ADC_CMDH_AVGS_MASK                       (0x7000U)
#define ADC_CMDH_AVGS_SHIFT                      (12U)
/*! AVGS - Hardware Average Select
 *  0b000..Single conversion.
 *  0b001..2 conversions averaged.
 *  0b010..4 conversions averaged.
 *  0b011..8 conversions averaged.
 *  0b100..16 conversions averaged.
 *  0b101..32 conversions averaged.
 *  0b110..64 conversions averaged.
 *  0b111..128 conversions averaged.
 */
#define ADC_CMDH_AVGS(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK)

#define ADC_CMDH_LOOP_MASK                       (0xF0000U)
#define ADC_CMDH_LOOP_SHIFT                      (16U)
/*! LOOP - Loop Count Select
 *  0b0000..Looping not enabled. Command executes 1 time.
 *  0b0001..Loop 1 time. Command executes 2 times.
 *  0b0010..Loop 2 times. Command executes 3 times.
 *  0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times.
 *  0b1111..Loop 15 times. Command executes 16 times.
 */
#define ADC_CMDH_LOOP(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK)

#define ADC_CMDH_NEXT_MASK                       (0xF000000U)
#define ADC_CMDH_NEXT_SHIFT                      (24U)
/*! NEXT - Next Command Select
 *  0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority
 *          trigger pending, begin command associated with lower priority trigger.
 *  0b0001..Select CMD1 command buffer register as next command.
 *  0b0010-0b1110..Select corresponding CMD command buffer register as next command
 *  0b1111..Select CMD15 command buffer register as next command.
 */
#define ADC_CMDH_NEXT(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK)
/*! @} */

/* The count of ADC_CMDH */
#define ADC_CMDH_COUNT                           (15U)

/*! @name CV - Compare Value Register */
/*! @{ */

#define ADC_CV_CVL_MASK                          (0xFFFFU)
#define ADC_CV_CVL_SHIFT                         (0U)
/*! CVL - Compare Value Low.
 */
#define ADC_CV_CVL(x)                            (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK)

#define ADC_CV_CVH_MASK                          (0xFFFF0000U)
#define ADC_CV_CVH_SHIFT                         (16U)
/*! CVH - Compare Value High.
 */
#define ADC_CV_CVH(x)                            (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK)
/*! @} */

/* The count of ADC_CV */
#define ADC_CV_COUNT                             (15U)

/*! @name RESFIFO - ADC Data Result FIFO Register */
/*! @{ */

#define ADC_RESFIFO_D_MASK                       (0xFFFFU)
#define ADC_RESFIFO_D_SHIFT                      (0U)
/*! D - Data result
 */
#define ADC_RESFIFO_D(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK)

#define ADC_RESFIFO_TSRC_MASK                    (0x30000U)
#define ADC_RESFIFO_TSRC_SHIFT                   (16U)
/*! TSRC - Trigger Source
 *  0b00..Trigger source 0 initiated this conversion.
 *  0b01..Trigger source 1 initiated this conversion.
 *  0b10-0b10..Corresponding trigger source initiated this conversion.
 *  0b11..Trigger source 3 initiated this conversion.
 */
#define ADC_RESFIFO_TSRC(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK)

#define ADC_RESFIFO_LOOPCNT_MASK                 (0xF00000U)
#define ADC_RESFIFO_LOOPCNT_SHIFT                (20U)
/*! LOOPCNT - Loop count value
 *  0b0000..Result is from initial conversion in command.
 *  0b0001..Result is from second conversion in command.
 *  0b0010-0b1110..Result is from LOOPCNT+1 conversion in command.
 *  0b1111..Result is from 16th conversion in command.
 */
#define ADC_RESFIFO_LOOPCNT(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK)

#define ADC_RESFIFO_CMDSRC_MASK                  (0xF000000U)
#define ADC_RESFIFO_CMDSRC_SHIFT                 (24U)
/*! CMDSRC - Command Buffer Source
 *  0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state
 *          prior to an ADC conversion result dataword being stored to a RESFIFO buffer.
 *  0b0001..CMD1 buffer used as control settings for this conversion.
 *  0b0010-0b1110..Corresponding command buffer used as control settings for this conversion.
 *  0b1111..CMD15 buffer used as control settings for this conversion.
 */
#define ADC_RESFIFO_CMDSRC(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK)

#define ADC_RESFIFO_VALID_MASK                   (0x80000000U)
#define ADC_RESFIFO_VALID_SHIFT                  (31U)
/*! VALID - FIFO entry is valid
 *  0b0..FIFO is empty. Discard any read from RESFIFO.
 *  0b1..FIFO record read from RESFIFO is valid.
 */
#define ADC_RESFIFO_VALID(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK)
/*! @} */

/* The count of ADC_RESFIFO */
#define ADC_RESFIFO_COUNT                        (2U)

/*! @name CAL_GAR - Calibration General A-Side Registers */
/*! @{ */

#define ADC_CAL_GAR_CAL_GAR_VAL_MASK             (0xFFFFU)
#define ADC_CAL_GAR_CAL_GAR_VAL_SHIFT            (0U)
/*! CAL_GAR_VAL - Calibration General A Side Register Element
 */
#define ADC_CAL_GAR_CAL_GAR_VAL(x)               (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR_CAL_GAR_VAL_MASK)
/*! @} */

/* The count of ADC_CAL_GAR */
#define ADC_CAL_GAR_COUNT                        (33U)

/*! @name CAL_GBR - Calibration General B-Side Registers */
/*! @{ */

#define ADC_CAL_GBR_CAL_GBR_VAL_MASK             (0xFFFFU)
#define ADC_CAL_GBR_CAL_GBR_VAL_SHIFT            (0U)
/*! CAL_GBR_VAL - Calibration General B Side Register Element
 */
#define ADC_CAL_GBR_CAL_GBR_VAL(x)               (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR_CAL_GBR_VAL_MASK)
/*! @} */

/* The count of ADC_CAL_GBR */
#define ADC_CAL_GBR_COUNT                        (33U)


/*!
 * @}
 */ /* end of group ADC_Register_Masks */


/* ADC - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral ADC0 base address */
  #define ADC0_BASE                                (0x500A0000u)
  /** Peripheral ADC0 base address */
  #define ADC0_BASE_NS                             (0x400A0000u)
  /** Peripheral ADC0 base pointer */
  #define ADC0                                     ((ADC_Type *)ADC0_BASE)
  /** Peripheral ADC0 base pointer */
  #define ADC0_NS                                  ((ADC_Type *)ADC0_BASE_NS)
  /** Peripheral ADC1 base address */
  #define ADC1_BASE                                (0x500B1000u)
  /** Peripheral ADC1 base address */
  #define ADC1_BASE_NS                             (0x400B1000u)
  /** Peripheral ADC1 base pointer */
  #define ADC1                                     ((ADC_Type *)ADC1_BASE)
  /** Peripheral ADC1 base pointer */
  #define ADC1_NS                                  ((ADC_Type *)ADC1_BASE_NS)
  /** Array initializer of ADC peripheral base addresses */
  #define ADC_BASE_ADDRS                           { ADC0_BASE, ADC1_BASE }
  /** Array initializer of ADC peripheral base pointers */
  #define ADC_BASE_PTRS                            { ADC0, ADC1 }
  /** Array initializer of ADC peripheral base addresses */
  #define ADC_BASE_ADDRS_NS                        { ADC0_BASE_NS, ADC1_BASE_NS }
  /** Array initializer of ADC peripheral base pointers */
  #define ADC_BASE_PTRS_NS                         { ADC0_NS, ADC1_NS }
#else
  /** Peripheral ADC0 base address */
  #define ADC0_BASE                                (0x400A0000u)
  /** Peripheral ADC0 base pointer */
  #define ADC0                                     ((ADC_Type *)ADC0_BASE)
  /** Peripheral ADC1 base address */
  #define ADC1_BASE                                (0x400B1000u)
  /** Peripheral ADC1 base pointer */
  #define ADC1                                     ((ADC_Type *)ADC1_BASE)
  /** Array initializer of ADC peripheral base addresses */
  #define ADC_BASE_ADDRS                           { ADC0_BASE, ADC1_BASE }
  /** Array initializer of ADC peripheral base pointers */
  #define ADC_BASE_PTRS                            { ADC0, ADC1 }
#endif
/** Interrupt vectors for the ADC peripheral type */
#define ADC_IRQS                                 { ADC0_IRQn, ADC1_IRQn }

/*!
 * @}
 */ /* end of group ADC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- ANACTRL Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup ANACTRL_Peripheral_Access_Layer ANACTRL Peripheral Access Layer
 * @{
 */

/** ANACTRL - Register Layout Typedef */
typedef struct {
  __IO uint32_t ANALOG_CTRL_CFG;                   /**< Various Analog blocks configuration (like FRO 192MHz trimmings source ...), offset: 0x0 */
  __I  uint32_t ANALOG_CTRL_STATUS;                /**< Analog Control and Status, offset: 0x4 */
       uint8_t RESERVED_0[8];
  __IO uint32_t FRO192M_CTRL;                      /**< 192MHz Free Running Oscillator (FRO) Control, offset: 0x10 */
  __I  uint32_t FRO192M_STATUS;                    /**< 192MHz Free Running Oscillator (FRO) Status, offset: 0x14 */
  __IO uint32_t ADC_CTRL;                          /**< General Purpose ADC VBAT Divider branch control, offset: 0x18 */
       uint8_t RESERVED_1[4];
  __IO uint32_t XO32M_CTRL;                        /**< High speed Crystal Oscillator Control register, offset: 0x20 */
  __I  uint32_t XO32M_STATUS;                      /**< High speed Crystal Oscillator Status, offset: 0x24 */
       uint8_t RESERVED_2[8];
  __IO uint32_t BOD_DCDC_INT_CTRL;                 /**< Brown Out Detectors & DCDC interrupt control, offset: 0x30 */
  __I  uint32_t BOD_DCDC_INT_STATUS;               /**< BoDs & DCDC interrupt status, offset: 0x34 */
       uint8_t RESERVED_3[120];
  __IO uint32_t LDO_XO32M;                         /**< High Speed Crystal Oscillator (12 MHz - 32 MHz) Voltage Source Supply Control register, offset: 0xB0 */
  __IO uint32_t AUX_BIAS;                          /**< AUX_BIAS, offset: 0xB4 */
       uint8_t RESERVED_4[56];
  __IO uint32_t OSC_TESTBUS;                       /**< Oscillators Analog Macrobloc ACBUS and DCBUS control, offset: 0xF0 */
       uint8_t RESERVED_5[4];
  __IO uint32_t DUMMY_CTRL;                        /**< Dummy Control bus to analog modules, offset: 0xF8 */
} ANACTRL_Type;

/* ----------------------------------------------------------------------------
   -- ANACTRL Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup ANACTRL_Register_Masks ANACTRL Register Masks
 * @{
 */

/*! @name ANALOG_CTRL_CFG - Various Analog blocks configuration (like FRO 192MHz trimmings source ...) */
/*! @{ */

#define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_MASK (0x1U)
#define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_SHIFT (0U)
/*! FRO192M_TRIM_SRC - FRO192M trimming and 'Enable' source.
 *  0b0..FRO192M trimming and 'Enable' comes from eFUSE.
 *  0b1..FRO192M trimming and 'Enable' comes from FRO192M_CTRL registers.
 */
#define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_SHIFT)) & ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_MASK)
/*! @} */

/*! @name ANALOG_CTRL_STATUS - Analog Control and Status */
/*! @{ */

#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK (0x1000U)
#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT (12U)
/*! FLASH_PWRDWN - Flash Power Down status
 *  0b0..Not in power down mode.
 *  0b1..In power down mode.
 */
#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK)

#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK (0x2000U)
#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT (13U)
/*! FLASH_INIT_ERROR - Flash initialization error status
 *  0b0..No error
 *  0b1..At least one error occurred
 */
#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK)

#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_ECC_ERROR_FLAG_MASK (0x10000U)
#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_ECC_ERROR_FLAG_SHIFT (16U)
/*! FLASH_ECC_ERROR_FLAG - Flash ECC Error Flag
 */
#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_ECC_ERROR_FLAG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_ECC_ERROR_FLAG_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_ECC_ERROR_FLAG_MASK)
/*! @} */

/*! @name FRO192M_CTRL - 192MHz Free Running Oscillator (FRO) Control */
/*! @{ */

#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK   (0x4000U)
#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT  (14U)
/*! ENA_12MHZCLK - 12 MHz clock control.
 *  0b0..Disable the 12 MHz clock.
 *  0b1..Enable the 12 MHz clock.
 */
#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK(x)     (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK)

#define ANACTRL_FRO192M_CTRL_FREQ_TRIM_MASK      (0xFF0000U)
#define ANACTRL_FRO192M_CTRL_FREQ_TRIM_SHIFT     (16U)
/*! FREQ_TRIM - Frequency trim.
 */
#define ANACTRL_FRO192M_CTRL_FREQ_TRIM(x)        (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_FREQ_TRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_FREQ_TRIM_MASK)

#define ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK      (0x1000000U)
#define ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT     (24U)
/*! USBCLKADJ - If USBCLKADJ bit is set and the USB peripheral is enabled for full speed device
 *    mode, the USB block will provide FRO clock adjustments to synchronize the frequency to the host
 *    clock using the SOF packets.
 */
#define ANACTRL_FRO192M_CTRL_USBCLKADJ(x)        (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT)) & ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK)

#define ANACTRL_FRO192M_CTRL_USBMODCHG_MASK      (0x2000000U)
#define ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT     (25U)
/*! USBMODCHG - USBCLKADJ mode trim change
 */
#define ANACTRL_FRO192M_CTRL_USBMODCHG(x)        (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT)) & ANACTRL_FRO192M_CTRL_USBMODCHG_MASK)

#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK   (0x40000000U)
#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT  (30U)
/*! ENA_96MHZCLK - 96 MHz clock control
 *  0b0..Disable the 96 MHz clock.
 *  0b1..Enable the 96 MHz clock.
 */
#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK(x)     (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK)

#define ANACTRL_FRO192M_CTRL_WRTRIM_MASK         (0x80000000U)
#define ANACTRL_FRO192M_CTRL_WRTRIM_SHIFT        (31U)
/*! WRTRIM - This must be written to 1 to modify the BIAS_TRIM and TEMP_TRIM fields.
 */
#define ANACTRL_FRO192M_CTRL_WRTRIM(x)           (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_WRTRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_WRTRIM_MASK)
/*! @} */

/*! @name FRO192M_STATUS - 192MHz Free Running Oscillator (FRO) Status */
/*! @{ */

#define ANACTRL_FRO192M_STATUS_CLK_VALID_MASK    (0x1U)
#define ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT   (0U)
/*! CLK_VALID - Output clock valid.
 *  0b0..No output clock available
 *  0b1..Output clock is available
 */
#define ANACTRL_FRO192M_STATUS_CLK_VALID(x)      (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT)) & ANACTRL_FRO192M_STATUS_CLK_VALID_MASK)

#define ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK    (0x2U)
#define ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT   (1U)
/*! ATB_VCTRL - CCO threshold voltage detector output (signal vcco_ok).
 */
#define ANACTRL_FRO192M_STATUS_ATB_VCTRL(x)      (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT)) & ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK)
/*! @} */

/*! @name ADC_CTRL - General Purpose ADC VBAT Divider branch control */
/*! @{ */

#define ANACTRL_ADC_CTRL_VBATDIVENABLE_MASK      (0x1U)
#define ANACTRL_ADC_CTRL_VBATDIVENABLE_SHIFT     (0U)
/*! VBATDIVENABLE - Switch On/Off VBAT divider branch.
 *  0b0..VBAT divider branch is disabled.
 *  0b1..VBAT divider branch is enabled.
 */
#define ANACTRL_ADC_CTRL_VBATDIVENABLE(x)        (((uint32_t)(((uint32_t)(x)) << ANACTRL_ADC_CTRL_VBATDIVENABLE_SHIFT)) & ANACTRL_ADC_CTRL_VBATDIVENABLE_MASK)
/*! @} */

/*! @name XO32M_CTRL - High speed Crystal Oscillator Control register */
/*! @{ */

#define ANACTRL_XO32M_CTRL_SLAVE_MASK            (0x10U)
#define ANACTRL_XO32M_CTRL_SLAVE_SHIFT           (4U)
/*! SLAVE - XO in slave mode.
 */
#define ANACTRL_XO32M_CTRL_SLAVE(x)              (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_SLAVE_SHIFT)) & ANACTRL_XO32M_CTRL_SLAVE_MASK)

#define ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK       (0x7F00U)
#define ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT      (8U)
/*! OSC_CAP_IN - Tune capa banks of High speed Crystal Oscillator input pin
 */
#define ANACTRL_XO32M_CTRL_OSC_CAP_IN(x)         (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT)) & ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK)

#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK      (0x3F8000U)
#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT     (15U)
/*! OSC_CAP_OUT - Tune capa banks of High speed Crystal Oscillator output pin
 */
#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT(x)        (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK)

#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK (0x400000U)
#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT (22U)
/*! ACBUF_PASS_ENABLE - Allows XO32M to be configured in bypass mode.
 *  0b0..XO bypass is disabled.
 *  0b1..XO bypass is enabled.
 */
#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE(x)  (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT)) & ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK)

#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK (0x1000000U)
#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT (24U)
/*! ENABLE_SYSTEM_CLK_OUT - Enable High speed Crystal oscillator output to CPU system.
 *  0b0..Disable the oscillator.
 *  0b1..Enable the oscillator.
 */
#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK)
/*! @} */

/*! @name XO32M_STATUS - High speed Crystal Oscillator Status */
/*! @{ */

#define ANACTRL_XO32M_STATUS_XO_READY_MASK       (0x1U)
#define ANACTRL_XO32M_STATUS_XO_READY_SHIFT      (0U)
/*! XO_READY - Crystal Oscillator Ready
 *  0b0..Frequency is not yet stable.
 *  0b1..Frequency is stable.
 */
#define ANACTRL_XO32M_STATUS_XO_READY(x)         (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_STATUS_XO_READY_SHIFT)) & ANACTRL_XO32M_STATUS_XO_READY_MASK)
/*! @} */

/*! @name BOD_DCDC_INT_CTRL - Brown Out Detectors & DCDC interrupt control */
/*! @{ */

#define ANACTRL_BOD_DCDC_INT_CTRL_BODVDDMAIN_INT_ENABLE_MASK (0x1U)
#define ANACTRL_BOD_DCDC_INT_CTRL_BODVDDMAIN_INT_ENABLE_SHIFT (0U)
/*! BODVDDMAIN_INT_ENABLE - BOD VDDMAIN interrupt control.
 *  0b0..Disable the interrupt.
 *  0b1..Enable the interrupt.
 */
#define ANACTRL_BOD_DCDC_INT_CTRL_BODVDDMAIN_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVDDMAIN_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVDDMAIN_INT_ENABLE_MASK)

#define ANACTRL_BOD_DCDC_INT_CTRL_BODVDDMAIN_INT_CLEAR_MASK (0x2U)
#define ANACTRL_BOD_DCDC_INT_CTRL_BODVDDMAIN_INT_CLEAR_SHIFT (1U)
/*! BODVDDMAIN_INT_CLEAR - BOD VDDMAIN interrupt clear.1: Clear the interrupt. Self-cleared bit.
 */
#define ANACTRL_BOD_DCDC_INT_CTRL_BODVDDMAIN_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVDDMAIN_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVDDMAIN_INT_CLEAR_MASK)

#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK (0x4U)
#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT (2U)
/*! BODCORE_INT_ENABLE - BOD CORE interrupt control.
 *  0b0..Disable the interrupt.
 *  0b1..Enable the interrupt.
 */
#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK)

#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK (0x8U)
#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT (3U)
/*! BODCORE_INT_CLEAR - BOD CORE interrupt clear.1: Clear the interrupt. Self-cleared bit.
 */
#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK)

#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK (0x10U)
#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT (4U)
/*! DCDC_INT_ENABLE - DCDC interrupt control.
 *  0b0..Disable the interrupt.
 *  0b1..Enable the interrupt.
 */
#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK)

#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK (0x20U)
#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT (5U)
/*! DCDC_INT_CLEAR - DCDC interrupt clear.1: Clear the interrupt. Self-cleared bit.
 */
#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK)
/*! @} */

/*! @name BOD_DCDC_INT_STATUS - BoDs & DCDC interrupt status */
/*! @{ */

#define ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_STATUS_MASK (0x1U)
#define ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_STATUS_SHIFT (0U)
/*! BODVDDMAIN_STATUS - BOD VDDMAIN Interrupt status before Interrupt Enable.
 *  0b0..No interrupt pending.
 *  0b1..Interrupt pending.
 */
#define ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_STATUS_MASK)

#define ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_INT_STATUS_MASK (0x2U)
#define ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_INT_STATUS_SHIFT (1U)
/*! BODVDDMAIN_INT_STATUS - BOD VDDMAIN Interrupt status after Interrupt Enable.
 *  0b0..No interrupt pending.
 *  0b1..Interrupt pending.
 */
#define ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_INT_STATUS_MASK)

#define ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_VAL_MASK (0x4U)
#define ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_VAL_SHIFT (2U)
/*! BODVDDMAIN_VAL - BOD VDDMAIN power status
 *  0b0..Below the threshold.
 *  0b1..Above the threshold.
 */
#define ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_VAL_MASK)

#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK (0x8U)
#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT (3U)
/*! BODCORE_STATUS - BOD CORE Interrupt status before Interrupt Enable.
 *  0b0..No interrupt pending.
 *  0b1..Interrupt pending.
 */
#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK)

#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK (0x10U)
#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT (4U)
/*! BODCORE_INT_STATUS - BOD CORE Interrupt status after Interrupt Enable.
 *  0b0..No interrupt pending.
 *  0b1..Interrupt pending.
 */
#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK)

#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK (0x20U)
#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT (5U)
/*! BODCORE_VAL - BOD CORE power status
 *  0b0..Below the threshold.
 *  0b1..Above the threshold.
 */
#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK)

#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK (0x40U)
#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT (6U)
/*! DCDC_STATUS - DCDC Interrupt status before Interrupt Enable.
 *  0b0..No interrupt pending.
 *  0b1..Interrupt pending.
 */
#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK)

#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK (0x80U)
#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT (7U)
/*! DCDC_INT_STATUS - DCDC Interrupt status after Interrupt Enable.
 *  0b0..No interrupt pending.
 *  0b1..Interrupt pending.
 */
#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK)

#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK (0x100U)
#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT (8U)
/*! DCDC_VAL - DCDC power status
 *  0b0..Below the target.
 *  0b1..Above the target.
 */
#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL(x)  (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK)
/*! @} */

/*! @name LDO_XO32M - High Speed Crystal Oscillator (12 MHz - 32 MHz) Voltage Source Supply Control register */
/*! @{ */

#define ANACTRL_LDO_XO32M_BYPASS_MASK            (0x2U)
#define ANACTRL_LDO_XO32M_BYPASS_SHIFT           (1U)
/*! BYPASS - Activate LDO bypass.
 *  0b0..Disable bypass mode (for normal operations).
 *  0b1..Activate LDO bypass.
 */
#define ANACTRL_LDO_XO32M_BYPASS(x)              (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_BYPASS_SHIFT)) & ANACTRL_LDO_XO32M_BYPASS_MASK)

#define ANACTRL_LDO_XO32M_HIGHZ_MASK             (0x4U)
#define ANACTRL_LDO_XO32M_HIGHZ_SHIFT            (2U)
/*! HIGHZ - .
 *  0b0..Output in High normal state.
 *  0b1..Output in High Impedance state.
 */
#define ANACTRL_LDO_XO32M_HIGHZ(x)               (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_HIGHZ_SHIFT)) & ANACTRL_LDO_XO32M_HIGHZ_MASK)

#define ANACTRL_LDO_XO32M_VOUT_MASK              (0x38U)
#define ANACTRL_LDO_XO32M_VOUT_SHIFT             (3U)
/*! VOUT - Sets the LDO output level.
 *  0b000..0.750 V.
 *  0b001..0.775 V.
 *  0b010..0.800 V.
 *  0b011..0.825 V.
 *  0b100..0.850 V.
 *  0b101..0.875 V.
 *  0b110..0.900 V.
 *  0b111..0.925 V.
 */
#define ANACTRL_LDO_XO32M_VOUT(x)                (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_VOUT_SHIFT)) & ANACTRL_LDO_XO32M_VOUT_MASK)

#define ANACTRL_LDO_XO32M_IBIAS_MASK             (0xC0U)
#define ANACTRL_LDO_XO32M_IBIAS_SHIFT            (6U)
/*! IBIAS - Adjust the biasing current.
 */
#define ANACTRL_LDO_XO32M_IBIAS(x)               (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_IBIAS_SHIFT)) & ANACTRL_LDO_XO32M_IBIAS_MASK)

#define ANACTRL_LDO_XO32M_STABMODE_MASK          (0x300U)
#define ANACTRL_LDO_XO32M_STABMODE_SHIFT         (8U)
/*! STABMODE - Stability configuration.
 */
#define ANACTRL_LDO_XO32M_STABMODE(x)            (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_STABMODE_SHIFT)) & ANACTRL_LDO_XO32M_STABMODE_MASK)
/*! @} */

/*! @name AUX_BIAS - AUX_BIAS */
/*! @{ */

#define ANACTRL_AUX_BIAS_VREF1VENABLE_MASK       (0x2U)
#define ANACTRL_AUX_BIAS_VREF1VENABLE_SHIFT      (1U)
/*! VREF1VENABLE - Control output of 1V reference voltage.
 *  0b0..Output of 1V reference voltage buffer is bypassed.
 *  0b1..Output of 1V reference voltage is enabled.
 */
#define ANACTRL_AUX_BIAS_VREF1VENABLE(x)         (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_VREF1VENABLE_SHIFT)) & ANACTRL_AUX_BIAS_VREF1VENABLE_MASK)

#define ANACTRL_AUX_BIAS_ITRIM_MASK              (0x7CU)
#define ANACTRL_AUX_BIAS_ITRIM_SHIFT             (2U)
/*! ITRIM - current trimming control word.
 */
#define ANACTRL_AUX_BIAS_ITRIM(x)                (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_ITRIM_SHIFT)) & ANACTRL_AUX_BIAS_ITRIM_MASK)

#define ANACTRL_AUX_BIAS_PTATITRIM_MASK          (0xF80U)
#define ANACTRL_AUX_BIAS_PTATITRIM_SHIFT         (7U)
/*! PTATITRIM - current trimming control word for ptat current.
 */
#define ANACTRL_AUX_BIAS_PTATITRIM(x)            (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_PTATITRIM_SHIFT)) & ANACTRL_AUX_BIAS_PTATITRIM_MASK)

#define ANACTRL_AUX_BIAS_VREF1VTRIM_MASK         (0x1F000U)
#define ANACTRL_AUX_BIAS_VREF1VTRIM_SHIFT        (12U)
/*! VREF1VTRIM - voltage trimming control word.
 */
#define ANACTRL_AUX_BIAS_VREF1VTRIM(x)           (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_VREF1VTRIM_SHIFT)) & ANACTRL_AUX_BIAS_VREF1VTRIM_MASK)

#define ANACTRL_AUX_BIAS_VREF1VCURVETRIM_MASK    (0xE0000U)
#define ANACTRL_AUX_BIAS_VREF1VCURVETRIM_SHIFT   (17U)
/*! VREF1VCURVETRIM - Control bit to configure trimming state of mirror.
 */
#define ANACTRL_AUX_BIAS_VREF1VCURVETRIM(x)      (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_VREF1VCURVETRIM_SHIFT)) & ANACTRL_AUX_BIAS_VREF1VCURVETRIM_MASK)

#define ANACTRL_AUX_BIAS_ITRIMCTRL0_MASK         (0x100000U)
#define ANACTRL_AUX_BIAS_ITRIMCTRL0_SHIFT        (20U)
/*! ITRIMCTRL0 - Control bit to configure trimming state of mirror.
 */
#define ANACTRL_AUX_BIAS_ITRIMCTRL0(x)           (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_ITRIMCTRL0_SHIFT)) & ANACTRL_AUX_BIAS_ITRIMCTRL0_MASK)

#define ANACTRL_AUX_BIAS_ITRIMCTRL1_MASK         (0x200000U)
#define ANACTRL_AUX_BIAS_ITRIMCTRL1_SHIFT        (21U)
/*! ITRIMCTRL1 - Control bit to configure trimming state of mirror.
 */
#define ANACTRL_AUX_BIAS_ITRIMCTRL1(x)           (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_ITRIMCTRL1_SHIFT)) & ANACTRL_AUX_BIAS_ITRIMCTRL1_MASK)
/*! @} */

/*! @name OSC_TESTBUS - Oscillators Analog Macrobloc ACBUS and DCBUS control */
/*! @{ */

#define ANACTRL_OSC_TESTBUS_ACBUS_MASK           (0x3FU)
#define ANACTRL_OSC_TESTBUS_ACBUS_SHIFT          (0U)
/*! ACBUS - Alternate current BUS
 */
#define ANACTRL_OSC_TESTBUS_ACBUS(x)             (((uint32_t)(((uint32_t)(x)) << ANACTRL_OSC_TESTBUS_ACBUS_SHIFT)) & ANACTRL_OSC_TESTBUS_ACBUS_MASK)

#define ANACTRL_OSC_TESTBUS_DCBUS_MASK           (0x3F0000U)
#define ANACTRL_OSC_TESTBUS_DCBUS_SHIFT          (16U)
/*! DCBUS - Direct current BUS
 */
#define ANACTRL_OSC_TESTBUS_DCBUS(x)             (((uint32_t)(((uint32_t)(x)) << ANACTRL_OSC_TESTBUS_DCBUS_SHIFT)) & ANACTRL_OSC_TESTBUS_DCBUS_MASK)
/*! @} */

/*! @name DUMMY_CTRL - Dummy Control bus to analog modules */
/*! @{ */

#define ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_MASK (0xC00U)
#define ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_SHIFT (10U)
/*! XO32M_ADC_CLK_MODE - Control High speed Crystal oscillator mode of the ADC clock.
 *  0b00..High speed Crystal oscillator output to ADC is disabled.
 *  0b01..High speed Crystal oscillator output to ADC is enable.
 */
#define ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_SHIFT)) & ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group ANACTRL_Register_Masks */


/* ANACTRL - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral ANACTRL base address */
  #define ANACTRL_BASE                             (0x50013000u)
  /** Peripheral ANACTRL base address */
  #define ANACTRL_BASE_NS                          (0x40013000u)
  /** Peripheral ANACTRL base pointer */
  #define ANACTRL                                  ((ANACTRL_Type *)ANACTRL_BASE)
  /** Peripheral ANACTRL base pointer */
  #define ANACTRL_NS                               ((ANACTRL_Type *)ANACTRL_BASE_NS)
  /** Array initializer of ANACTRL peripheral base addresses */
  #define ANACTRL_BASE_ADDRS                       { ANACTRL_BASE }
  /** Array initializer of ANACTRL peripheral base pointers */
  #define ANACTRL_BASE_PTRS                        { ANACTRL }
  /** Array initializer of ANACTRL peripheral base addresses */
  #define ANACTRL_BASE_ADDRS_NS                    { ANACTRL_BASE_NS }
  /** Array initializer of ANACTRL peripheral base pointers */
  #define ANACTRL_BASE_PTRS_NS                     { ANACTRL_NS }
#else
  /** Peripheral ANACTRL base address */
  #define ANACTRL_BASE                             (0x40013000u)
  /** Peripheral ANACTRL base pointer */
  #define ANACTRL                                  ((ANACTRL_Type *)ANACTRL_BASE)
  /** Array initializer of ANACTRL peripheral base addresses */
  #define ANACTRL_BASE_ADDRS                       { ANACTRL_BASE }
  /** Array initializer of ANACTRL peripheral base pointers */
  #define ANACTRL_BASE_PTRS                        { ANACTRL }
#endif

/*!
 * @}
 */ /* end of group ANACTRL_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- AOI Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AOI_Peripheral_Access_Layer AOI Peripheral Access Layer
 * @{
 */

/** AOI - Register Layout Typedef */
typedef struct {
  struct {                                         /* offset: 0x0, array step: 0x4 */
    __IO uint16_t BFCRT01;                           /**< Boolean Function Term 0 and 1 Configuration Register for EVENTn, array offset: 0x0, array step: 0x4 */
    __IO uint16_t BFCRT23;                           /**< Boolean Function Term 2 and 3 Configuration Register for EVENTn, array offset: 0x2, array step: 0x4 */
  } BFCRT[4];
} AOI_Type;

/* ----------------------------------------------------------------------------
   -- AOI Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AOI_Register_Masks AOI Register Masks
 * @{
 */

/*! @name BFCRT01 - Boolean Function Term 0 and 1 Configuration Register for EVENTn */
/*! @{ */

#define AOI_BFCRT01_PT1_DC_MASK                  (0x3U)
#define AOI_BFCRT01_PT1_DC_SHIFT                 (0U)
/*! PT1_DC - Product term 1, D input configuration
 *  0b00..Force the D input in this product term to a logical zero
 *  0b01..Pass the D input in this product term
 *  0b10..Complement the D input in this product term
 *  0b11..Force the D input in this product term to a logical one
 */
#define AOI_BFCRT01_PT1_DC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_DC_SHIFT)) & AOI_BFCRT01_PT1_DC_MASK)

#define AOI_BFCRT01_PT1_CC_MASK                  (0xCU)
#define AOI_BFCRT01_PT1_CC_SHIFT                 (2U)
/*! PT1_CC - Product term 1, C input configuration
 *  0b00..Force the C input in this product term to a logical zero
 *  0b01..Pass the C input in this product term
 *  0b10..Complement the C input in this product term
 *  0b11..Force the C input in this product term to a logical one
 */
#define AOI_BFCRT01_PT1_CC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_CC_SHIFT)) & AOI_BFCRT01_PT1_CC_MASK)

#define AOI_BFCRT01_PT1_BC_MASK                  (0x30U)
#define AOI_BFCRT01_PT1_BC_SHIFT                 (4U)
/*! PT1_BC - Product term 1, B input configuration
 *  0b00..Force the B input in this product term to a logical zero
 *  0b01..Pass the B input in this product term
 *  0b10..Complement the B input in this product term
 *  0b11..Force the B input in this product term to a logical one
 */
#define AOI_BFCRT01_PT1_BC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_BC_SHIFT)) & AOI_BFCRT01_PT1_BC_MASK)

#define AOI_BFCRT01_PT1_AC_MASK                  (0xC0U)
#define AOI_BFCRT01_PT1_AC_SHIFT                 (6U)
/*! PT1_AC - Product term 1, A input configuration
 *  0b00..Force the A input in this product term to a logical zero
 *  0b01..Pass the A input in this product term
 *  0b10..Complement the A input in this product term
 *  0b11..Force the A input in this product term to a logical one
 */
#define AOI_BFCRT01_PT1_AC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_AC_SHIFT)) & AOI_BFCRT01_PT1_AC_MASK)

#define AOI_BFCRT01_PT0_DC_MASK                  (0x300U)
#define AOI_BFCRT01_PT0_DC_SHIFT                 (8U)
/*! PT0_DC - Product term 0, D input configuration
 *  0b00..Force the D input in this product term to a logical zero
 *  0b01..Pass the D input in this product term
 *  0b10..Complement the D input in this product term
 *  0b11..Force the D input in this product term to a logical one
 */
#define AOI_BFCRT01_PT0_DC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_DC_SHIFT)) & AOI_BFCRT01_PT0_DC_MASK)

#define AOI_BFCRT01_PT0_CC_MASK                  (0xC00U)
#define AOI_BFCRT01_PT0_CC_SHIFT                 (10U)
/*! PT0_CC - Product term 0, C input configuration
 *  0b00..Force the C input in this product term to a logical zero
 *  0b01..Pass the C input in this product term
 *  0b10..Complement the C input in this product term
 *  0b11..Force the C input in this product term to a logical one
 */
#define AOI_BFCRT01_PT0_CC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_CC_SHIFT)) & AOI_BFCRT01_PT0_CC_MASK)

#define AOI_BFCRT01_PT0_BC_MASK                  (0x3000U)
#define AOI_BFCRT01_PT0_BC_SHIFT                 (12U)
/*! PT0_BC - Product term 0, B input configuration
 *  0b00..Force the B input in this product term to a logical zero
 *  0b01..Pass the B input in this product term
 *  0b10..Complement the B input in this product term
 *  0b11..Force the B input in this product term to a logical one
 */
#define AOI_BFCRT01_PT0_BC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_BC_SHIFT)) & AOI_BFCRT01_PT0_BC_MASK)

#define AOI_BFCRT01_PT0_AC_MASK                  (0xC000U)
#define AOI_BFCRT01_PT0_AC_SHIFT                 (14U)
/*! PT0_AC - Product term 0, A input configuration
 *  0b00..Force the A input in this product term to a logical zero
 *  0b01..Pass the A input in this product term
 *  0b10..Complement the A input in this product term
 *  0b11..Force the A input in this product term to a logical one
 */
#define AOI_BFCRT01_PT0_AC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_AC_SHIFT)) & AOI_BFCRT01_PT0_AC_MASK)
/*! @} */

/* The count of AOI_BFCRT01 */
#define AOI_BFCRT01_COUNT                        (4U)

/*! @name BFCRT23 - Boolean Function Term 2 and 3 Configuration Register for EVENTn */
/*! @{ */

#define AOI_BFCRT23_PT3_DC_MASK                  (0x3U)
#define AOI_BFCRT23_PT3_DC_SHIFT                 (0U)
/*! PT3_DC - Product term 3, D input configuration
 *  0b00..Force the D input in this product term to a logical zero
 *  0b01..Pass the D input in this product term
 *  0b10..Complement the D input in this product term
 *  0b11..Force the D input in this product term to a logical one
 */
#define AOI_BFCRT23_PT3_DC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_DC_SHIFT)) & AOI_BFCRT23_PT3_DC_MASK)

#define AOI_BFCRT23_PT3_CC_MASK                  (0xCU)
#define AOI_BFCRT23_PT3_CC_SHIFT                 (2U)
/*! PT3_CC - Product term 3, C input configuration
 *  0b00..Force the C input in this product term to a logical zero
 *  0b01..Pass the C input in this product term
 *  0b10..Complement the C input in this product term
 *  0b11..Force the C input in this product term to a logical one
 */
#define AOI_BFCRT23_PT3_CC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_CC_SHIFT)) & AOI_BFCRT23_PT3_CC_MASK)

#define AOI_BFCRT23_PT3_BC_MASK                  (0x30U)
#define AOI_BFCRT23_PT3_BC_SHIFT                 (4U)
/*! PT3_BC - Product term 3, B input configuration
 *  0b00..Force the B input in this product term to a logical zero
 *  0b01..Pass the B input in this product term
 *  0b10..Complement the B input in this product term
 *  0b11..Force the B input in this product term to a logical one
 */
#define AOI_BFCRT23_PT3_BC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_BC_SHIFT)) & AOI_BFCRT23_PT3_BC_MASK)

#define AOI_BFCRT23_PT3_AC_MASK                  (0xC0U)
#define AOI_BFCRT23_PT3_AC_SHIFT                 (6U)
/*! PT3_AC - Product term 3, A input configuration
 *  0b00..Force the A input in this product term to a logical zero
 *  0b01..Pass the A input in this product term
 *  0b10..Complement the A input in this product term
 *  0b11..Force the A input in this product term to a logical one
 */
#define AOI_BFCRT23_PT3_AC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_AC_SHIFT)) & AOI_BFCRT23_PT3_AC_MASK)

#define AOI_BFCRT23_PT2_DC_MASK                  (0x300U)
#define AOI_BFCRT23_PT2_DC_SHIFT                 (8U)
/*! PT2_DC - Product term 2, D input configuration
 *  0b00..Force the D input in this product term to a logical zero
 *  0b01..Pass the D input in this product term
 *  0b10..Complement the D input in this product term
 *  0b11..Force the D input in this product term to a logical one
 */
#define AOI_BFCRT23_PT2_DC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_DC_SHIFT)) & AOI_BFCRT23_PT2_DC_MASK)

#define AOI_BFCRT23_PT2_CC_MASK                  (0xC00U)
#define AOI_BFCRT23_PT2_CC_SHIFT                 (10U)
/*! PT2_CC - Product term 2, C input configuration
 *  0b00..Force the C input in this product term to a logical zero
 *  0b01..Pass the C input in this product term
 *  0b10..Complement the C input in this product term
 *  0b11..Force the C input in this product term to a logical one
 */
#define AOI_BFCRT23_PT2_CC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_CC_SHIFT)) & AOI_BFCRT23_PT2_CC_MASK)

#define AOI_BFCRT23_PT2_BC_MASK                  (0x3000U)
#define AOI_BFCRT23_PT2_BC_SHIFT                 (12U)
/*! PT2_BC - Product term 2, B input configuration
 *  0b00..Force the B input in this product term to a logical zero
 *  0b01..Pass the B input in this product term
 *  0b10..Complement the B input in this product term
 *  0b11..Force the B input in this product term to a logical one
 */
#define AOI_BFCRT23_PT2_BC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_BC_SHIFT)) & AOI_BFCRT23_PT2_BC_MASK)

#define AOI_BFCRT23_PT2_AC_MASK                  (0xC000U)
#define AOI_BFCRT23_PT2_AC_SHIFT                 (14U)
/*! PT2_AC - Product term 2, A input configuration
 *  0b00..Force the A input in this product term to a logical zero
 *  0b01..Pass the A input in this product term
 *  0b10..Complement the A input in this product term
 *  0b11..Force the A input in this product term to a logical one
 */
#define AOI_BFCRT23_PT2_AC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_AC_SHIFT)) & AOI_BFCRT23_PT2_AC_MASK)
/*! @} */

/* The count of AOI_BFCRT23 */
#define AOI_BFCRT23_COUNT                        (4U)


/*!
 * @}
 */ /* end of group AOI_Register_Masks */


/* AOI - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral AOI0 base address */
  #define AOI0_BASE                                (0x500C7000u)
  /** Peripheral AOI0 base address */
  #define AOI0_BASE_NS                             (0x400C7000u)
  /** Peripheral AOI0 base pointer */
  #define AOI0                                     ((AOI_Type *)AOI0_BASE)
  /** Peripheral AOI0 base pointer */
  #define AOI0_NS                                  ((AOI_Type *)AOI0_BASE_NS)
  /** Peripheral AOI1 base address */
  #define AOI1_BASE                                (0x500C8000u)
  /** Peripheral AOI1 base address */
  #define AOI1_BASE_NS                             (0x400C8000u)
  /** Peripheral AOI1 base pointer */
  #define AOI1                                     ((AOI_Type *)AOI1_BASE)
  /** Peripheral AOI1 base pointer */
  #define AOI1_NS                                  ((AOI_Type *)AOI1_BASE_NS)
  /** Array initializer of AOI peripheral base addresses */
  #define AOI_BASE_ADDRS                           { AOI0_BASE, AOI1_BASE }
  /** Array initializer of AOI peripheral base pointers */
  #define AOI_BASE_PTRS                            { AOI0, AOI1 }
  /** Array initializer of AOI peripheral base addresses */
  #define AOI_BASE_ADDRS_NS                        { AOI0_BASE_NS, AOI1_BASE_NS }
  /** Array initializer of AOI peripheral base pointers */
  #define AOI_BASE_PTRS_NS                         { AOI0_NS, AOI1_NS }
#else
  /** Peripheral AOI0 base address */
  #define AOI0_BASE                                (0x400C7000u)
  /** Peripheral AOI0 base pointer */
  #define AOI0                                     ((AOI_Type *)AOI0_BASE)
  /** Peripheral AOI1 base address */
  #define AOI1_BASE                                (0x400C8000u)
  /** Peripheral AOI1 base pointer */
  #define AOI1                                     ((AOI_Type *)AOI1_BASE)
  /** Array initializer of AOI peripheral base addresses */
  #define AOI_BASE_ADDRS                           { AOI0_BASE, AOI1_BASE }
  /** Array initializer of AOI peripheral base pointers */
  #define AOI_BASE_PTRS                            { AOI0, AOI1 }
#endif

/*!
 * @}
 */ /* end of group AOI_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CACHE64_CTRL Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CACHE64_CTRL_Peripheral_Access_Layer CACHE64_CTRL Peripheral Access Layer
 * @{
 */

/** CACHE64_CTRL - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[2048];
  __IO uint32_t CCR;                               /**< Cache control register, offset: 0x800 */
  __IO uint32_t CLCR;                              /**< Cache line control register, offset: 0x804 */
  __IO uint32_t CSAR;                              /**< Cache search address register, offset: 0x808 */
  __IO uint32_t CCVR;                              /**< Cache read/write value register, offset: 0x80C */
} CACHE64_CTRL_Type;

/* ----------------------------------------------------------------------------
   -- CACHE64_CTRL Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CACHE64_CTRL_Register_Masks CACHE64_CTRL Register Masks
 * @{
 */

/*! @name CCR - Cache control register */
/*! @{ */

#define CACHE64_CTRL_CCR_ENCACHE_MASK            (0x1U)
#define CACHE64_CTRL_CCR_ENCACHE_SHIFT           (0U)
/*! ENCACHE - Cache enable
 *  0b0..Cache disabled
 *  0b1..Cache enabled
 */
#define CACHE64_CTRL_CCR_ENCACHE(x)              (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_ENCACHE_SHIFT)) & CACHE64_CTRL_CCR_ENCACHE_MASK)

#define CACHE64_CTRL_CCR_ENWRBUF_MASK            (0x2U)
#define CACHE64_CTRL_CCR_ENWRBUF_SHIFT           (1U)
/*! ENWRBUF - Enable Write Buffer
 *  0b0..Write buffer disabled
 *  0b1..Write buffer enabled
 */
#define CACHE64_CTRL_CCR_ENWRBUF(x)              (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_ENWRBUF_SHIFT)) & CACHE64_CTRL_CCR_ENWRBUF_MASK)

#define CACHE64_CTRL_CCR_INVW0_MASK              (0x1000000U)
#define CACHE64_CTRL_CCR_INVW0_SHIFT             (24U)
/*! INVW0 - Invalidate Way 0
 *  0b0..No operation
 *  0b1..When setting the GO bit, invalidate all lines in way 0.
 */
#define CACHE64_CTRL_CCR_INVW0(x)                (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_INVW0_SHIFT)) & CACHE64_CTRL_CCR_INVW0_MASK)

#define CACHE64_CTRL_CCR_PUSHW0_MASK             (0x2000000U)
#define CACHE64_CTRL_CCR_PUSHW0_SHIFT            (25U)
/*! PUSHW0 - Push Way 0
 *  0b0..No operation
 *  0b1..When setting the GO bit, push all modified lines in way 0
 */
#define CACHE64_CTRL_CCR_PUSHW0(x)               (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_PUSHW0_SHIFT)) & CACHE64_CTRL_CCR_PUSHW0_MASK)

#define CACHE64_CTRL_CCR_INVW1_MASK              (0x4000000U)
#define CACHE64_CTRL_CCR_INVW1_SHIFT             (26U)
/*! INVW1 - Invalidate Way 1
 *  0b0..No operation
 *  0b1..When setting the GO bit, invalidate all lines in way 1
 */
#define CACHE64_CTRL_CCR_INVW1(x)                (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_INVW1_SHIFT)) & CACHE64_CTRL_CCR_INVW1_MASK)

#define CACHE64_CTRL_CCR_PUSHW1_MASK             (0x8000000U)
#define CACHE64_CTRL_CCR_PUSHW1_SHIFT            (27U)
/*! PUSHW1 - Push Way 1
 *  0b0..No operation
 *  0b1..When setting the GO bit, push all modified lines in way 1
 */
#define CACHE64_CTRL_CCR_PUSHW1(x)               (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_PUSHW1_SHIFT)) & CACHE64_CTRL_CCR_PUSHW1_MASK)

#define CACHE64_CTRL_CCR_GO_MASK                 (0x80000000U)
#define CACHE64_CTRL_CCR_GO_SHIFT                (31U)
/*! GO - Initiate Cache Command
 *  0b0..Write: no effect. Read: no cache command active.
 *  0b1..Write: initiate command indicated by bits 27-24. Read: cache command active.
 */
#define CACHE64_CTRL_CCR_GO(x)                   (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_GO_SHIFT)) & CACHE64_CTRL_CCR_GO_MASK)
/*! @} */

/*! @name CLCR - Cache line control register */
/*! @{ */

#define CACHE64_CTRL_CLCR_LGO_MASK               (0x1U)
#define CACHE64_CTRL_CLCR_LGO_SHIFT              (0U)
/*! LGO - Initiate Cache Line Command
 *  0b0..Write: no effect. Read: no line command active.
 *  0b1..Write: initiate line command indicated by bits 27-24. Read: line command active.
 */
#define CACHE64_CTRL_CLCR_LGO(x)                 (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LGO_SHIFT)) & CACHE64_CTRL_CLCR_LGO_MASK)

#define CACHE64_CTRL_CLCR_CACHEADDR_MASK         (0x3FFCU)
#define CACHE64_CTRL_CLCR_CACHEADDR_SHIFT        (2U)
/*! CACHEADDR - Cache address
 */
#define CACHE64_CTRL_CLCR_CACHEADDR(x)           (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_CACHEADDR_SHIFT)) & CACHE64_CTRL_CLCR_CACHEADDR_MASK)

#define CACHE64_CTRL_CLCR_WSEL_MASK              (0x4000U)
#define CACHE64_CTRL_CLCR_WSEL_SHIFT             (14U)
/*! WSEL - Way select
 *  0b0..Way 0
 *  0b1..Way 1
 */
#define CACHE64_CTRL_CLCR_WSEL(x)                (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_WSEL_SHIFT)) & CACHE64_CTRL_CLCR_WSEL_MASK)

#define CACHE64_CTRL_CLCR_TDSEL_MASK             (0x10000U)
#define CACHE64_CTRL_CLCR_TDSEL_SHIFT            (16U)
/*! TDSEL - Tag/Data Select
 *  0b0..Data
 *  0b1..Tag
 */
#define CACHE64_CTRL_CLCR_TDSEL(x)               (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_TDSEL_SHIFT)) & CACHE64_CTRL_CLCR_TDSEL_MASK)

#define CACHE64_CTRL_CLCR_LCIVB_MASK             (0x100000U)
#define CACHE64_CTRL_CLCR_LCIVB_SHIFT            (20U)
/*! LCIVB - Line Command Initial Valid Bit
 */
#define CACHE64_CTRL_CLCR_LCIVB(x)               (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LCIVB_SHIFT)) & CACHE64_CTRL_CLCR_LCIVB_MASK)

#define CACHE64_CTRL_CLCR_LCIMB_MASK             (0x200000U)
#define CACHE64_CTRL_CLCR_LCIMB_SHIFT            (21U)
/*! LCIMB - Line Command Initial Modified Bit
 */
#define CACHE64_CTRL_CLCR_LCIMB(x)               (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LCIMB_SHIFT)) & CACHE64_CTRL_CLCR_LCIMB_MASK)

#define CACHE64_CTRL_CLCR_LCWAY_MASK             (0x400000U)
#define CACHE64_CTRL_CLCR_LCWAY_SHIFT            (22U)
/*! LCWAY - Line Command Way
 */
#define CACHE64_CTRL_CLCR_LCWAY(x)               (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LCWAY_SHIFT)) & CACHE64_CTRL_CLCR_LCWAY_MASK)

#define CACHE64_CTRL_CLCR_LCMD_MASK              (0x3000000U)
#define CACHE64_CTRL_CLCR_LCMD_SHIFT             (24U)
/*! LCMD - Line Command
 *  0b00..Search and read or write
 *  0b01..Invalidate
 *  0b10..Push
 *  0b11..Clear
 */
#define CACHE64_CTRL_CLCR_LCMD(x)                (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LCMD_SHIFT)) & CACHE64_CTRL_CLCR_LCMD_MASK)

#define CACHE64_CTRL_CLCR_LADSEL_MASK            (0x4000000U)
#define CACHE64_CTRL_CLCR_LADSEL_SHIFT           (26U)
/*! LADSEL - Line Address Select
 *  0b0..Cache address
 *  0b1..Physical address
 */
#define CACHE64_CTRL_CLCR_LADSEL(x)              (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LADSEL_SHIFT)) & CACHE64_CTRL_CLCR_LADSEL_MASK)

#define CACHE64_CTRL_CLCR_LACC_MASK              (0x8000000U)
#define CACHE64_CTRL_CLCR_LACC_SHIFT             (27U)
/*! LACC - Line access type
 *  0b0..Read
 *  0b1..Write
 */
#define CACHE64_CTRL_CLCR_LACC(x)                (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LACC_SHIFT)) & CACHE64_CTRL_CLCR_LACC_MASK)
/*! @} */

/*! @name CSAR - Cache search address register */
/*! @{ */

#define CACHE64_CTRL_CSAR_LGO_MASK               (0x1U)
#define CACHE64_CTRL_CSAR_LGO_SHIFT              (0U)
/*! LGO - Initiate Cache Line Command
 *  0b0..Write: no effect. Read: no line command active.
 *  0b1..Write: initiate line command indicated by bits CLCR[27:24]. Read: line command active.
 */
#define CACHE64_CTRL_CSAR_LGO(x)                 (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CSAR_LGO_SHIFT)) & CACHE64_CTRL_CSAR_LGO_MASK)

#define CACHE64_CTRL_CSAR_PHYADDR_MASK           (0xFFFFFFFEU)
#define CACHE64_CTRL_CSAR_PHYADDR_SHIFT          (1U)
/*! PHYADDR - Physical Address
 */
#define CACHE64_CTRL_CSAR_PHYADDR(x)             (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CSAR_PHYADDR_SHIFT)) & CACHE64_CTRL_CSAR_PHYADDR_MASK)
/*! @} */

/*! @name CCVR - Cache read/write value register */
/*! @{ */

#define CACHE64_CTRL_CCVR_DATA_MASK              (0xFFFFFFFFU)
#define CACHE64_CTRL_CCVR_DATA_SHIFT             (0U)
/*! DATA - Cache read/write Data
 */
#define CACHE64_CTRL_CCVR_DATA(x)                (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCVR_DATA_SHIFT)) & CACHE64_CTRL_CCVR_DATA_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group CACHE64_CTRL_Register_Masks */


/* CACHE64_CTRL - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral CACHE64_CTRL0 base address */
  #define CACHE64_CTRL0_BASE                       (0x5002E000u)
  /** Peripheral CACHE64_CTRL0 base address */
  #define CACHE64_CTRL0_BASE_NS                    (0x4002E000u)
  /** Peripheral CACHE64_CTRL0 base pointer */
  #define CACHE64_CTRL0                            ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE)
  /** Peripheral CACHE64_CTRL0 base pointer */
  #define CACHE64_CTRL0_NS                         ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE_NS)
  /** Array initializer of CACHE64_CTRL peripheral base addresses */
  #define CACHE64_CTRL_BASE_ADDRS                  { CACHE64_CTRL0_BASE }
  /** Array initializer of CACHE64_CTRL peripheral base pointers */
  #define CACHE64_CTRL_BASE_PTRS                   { CACHE64_CTRL0 }
  /** Array initializer of CACHE64_CTRL peripheral base addresses */
  #define CACHE64_CTRL_BASE_ADDRS_NS               { CACHE64_CTRL0_BASE_NS }
  /** Array initializer of CACHE64_CTRL peripheral base pointers */
  #define CACHE64_CTRL_BASE_PTRS_NS                { CACHE64_CTRL0_NS }
#else
  /** Peripheral CACHE64_CTRL0 base address */
  #define CACHE64_CTRL0_BASE                       (0x4002E000u)
  /** Peripheral CACHE64_CTRL0 base pointer */
  #define CACHE64_CTRL0                            ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE)
  /** Array initializer of CACHE64_CTRL peripheral base addresses */
  #define CACHE64_CTRL_BASE_ADDRS                  { CACHE64_CTRL0_BASE }
  /** Array initializer of CACHE64_CTRL peripheral base pointers */
  #define CACHE64_CTRL_BASE_PTRS                   { CACHE64_CTRL0 }
#endif
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
/** CACHE64_CTRL physical memory base address */
 #define CACHE64_CTRL_PHYMEM_BASES                { 0x18000000u, 0x38000000u }
/** CACHE64_CTRL physical memory size */
 #define CACHE64_CTRL_PHYMEM_SIZES                { 0x08000000u, 0x08000000u }
/** CACHE64_CTRL physical memory base address */
 #define CACHE64_CTRL_PHYMEM_BASES_NS             { 0x08000000u, 0x28000000u }
/** CACHE64_CTRL physical memory size */
 #define CACHE64_CTRL_PHYMEM_SIZES_NS             { 0x08000000u, 0x08000000u }
#else
/** CACHE64_CTRL physical memory base address */
 #define CACHE64_CTRL_PHYMEM_BASES                { 0x08000000u, 0x28000000u }
/** CACHE64_CTRL physical memory size */
 #define CACHE64_CTRL_PHYMEM_SIZES                { 0x08000000u, 0x08000000u }
#endif
/* Backward compatibility */


/*!
 * @}
 */ /* end of group CACHE64_CTRL_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CACHE64_POLSEL Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CACHE64_POLSEL_Peripheral_Access_Layer CACHE64_POLSEL Peripheral Access Layer
 * @{
 */

/** CACHE64_POLSEL - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[20];
  __IO uint32_t REG0_TOP;                          /**< Region 0 Top Boundary, offset: 0x14 */
  __IO uint32_t REG1_TOP;                          /**< Region 1 Top Boundary, offset: 0x18 */
  __IO uint32_t POLSEL;                            /**< Policy Select, offset: 0x1C */
} CACHE64_POLSEL_Type;

/* ----------------------------------------------------------------------------
   -- CACHE64_POLSEL Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CACHE64_POLSEL_Register_Masks CACHE64_POLSEL Register Masks
 * @{
 */

/*! @name REG0_TOP - Region 0 Top Boundary */
/*! @{ */

#define CACHE64_POLSEL_REG0_TOP_REG0_TOP_MASK    (0x7FFFC00U)
#define CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT   (10U)
/*! REG0_TOP - Upper limit of Region 0
 */
#define CACHE64_POLSEL_REG0_TOP_REG0_TOP(x)      (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT)) & CACHE64_POLSEL_REG0_TOP_REG0_TOP_MASK)
/*! @} */

/*! @name REG1_TOP - Region 1 Top Boundary */
/*! @{ */

#define CACHE64_POLSEL_REG1_TOP_REG1_TOP_MASK    (0x7FFFC00U)
#define CACHE64_POLSEL_REG1_TOP_REG1_TOP_SHIFT   (10U)
/*! REG1_TOP - Upper limit of Region 1
 */
#define CACHE64_POLSEL_REG1_TOP_REG1_TOP(x)      (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_REG1_TOP_REG1_TOP_SHIFT)) & CACHE64_POLSEL_REG1_TOP_REG1_TOP_MASK)
/*! @} */

/*! @name POLSEL - Policy Select */
/*! @{ */

#define CACHE64_POLSEL_POLSEL_REG0_POLICY_MASK   (0x3U)
#define CACHE64_POLSEL_POLSEL_REG0_POLICY_SHIFT  (0U)
/*! REG0_POLICY - Policy Select for Region 0
 *  0b00..Non-cache
 *  0b01..Write-thru
 *  0b10..Write-back
 *  0b11..Invalid
 */
#define CACHE64_POLSEL_POLSEL_REG0_POLICY(x)     (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_POLSEL_REG0_POLICY_SHIFT)) & CACHE64_POLSEL_POLSEL_REG0_POLICY_MASK)

#define CACHE64_POLSEL_POLSEL_REG1_POLICY_MASK   (0xCU)
#define CACHE64_POLSEL_POLSEL_REG1_POLICY_SHIFT  (2U)
/*! REG1_POLICY - Policy Select for Region 0
 *  0b00..Non-cache
 *  0b01..Write-thru
 *  0b10..Write-back
 *  0b11..Invalid
 */
#define CACHE64_POLSEL_POLSEL_REG1_POLICY(x)     (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_POLSEL_REG1_POLICY_SHIFT)) & CACHE64_POLSEL_POLSEL_REG1_POLICY_MASK)

#define CACHE64_POLSEL_POLSEL_REG02_POLICY_MASK  (0x30U)
#define CACHE64_POLSEL_POLSEL_REG02_POLICY_SHIFT (4U)
/*! REG02_POLICY - Policy Select for Region 0
 *  0b00..Non-cache
 *  0b01..Write-thru
 *  0b10..Write-back
 *  0b11..Invalid
 */
#define CACHE64_POLSEL_POLSEL_REG02_POLICY(x)    (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_POLSEL_REG02_POLICY_SHIFT)) & CACHE64_POLSEL_POLSEL_REG02_POLICY_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group CACHE64_POLSEL_Register_Masks */


/* CACHE64_POLSEL - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral CACHE64_POLSEL0 base address */
  #define CACHE64_POLSEL0_BASE                     (0x5002E000u)
  /** Peripheral CACHE64_POLSEL0 base address */
  #define CACHE64_POLSEL0_BASE_NS                  (0x4002E000u)
  /** Peripheral CACHE64_POLSEL0 base pointer */
  #define CACHE64_POLSEL0                          ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE)
  /** Peripheral CACHE64_POLSEL0 base pointer */
  #define CACHE64_POLSEL0_NS                       ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE_NS)
  /** Array initializer of CACHE64_POLSEL peripheral base addresses */
  #define CACHE64_POLSEL_BASE_ADDRS                { CACHE64_POLSEL0_BASE }
  /** Array initializer of CACHE64_POLSEL peripheral base pointers */
  #define CACHE64_POLSEL_BASE_PTRS                 { CACHE64_POLSEL0 }
  /** Array initializer of CACHE64_POLSEL peripheral base addresses */
  #define CACHE64_POLSEL_BASE_ADDRS_NS             { CACHE64_POLSEL0_BASE_NS }
  /** Array initializer of CACHE64_POLSEL peripheral base pointers */
  #define CACHE64_POLSEL_BASE_PTRS_NS              { CACHE64_POLSEL0_NS }
#else
  /** Peripheral CACHE64_POLSEL0 base address */
  #define CACHE64_POLSEL0_BASE                     (0x4002E000u)
  /** Peripheral CACHE64_POLSEL0 base pointer */
  #define CACHE64_POLSEL0                          ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE)
  /** Array initializer of CACHE64_POLSEL peripheral base addresses */
  #define CACHE64_POLSEL_BASE_ADDRS                { CACHE64_POLSEL0_BASE }
  /** Array initializer of CACHE64_POLSEL peripheral base pointers */
  #define CACHE64_POLSEL_BASE_PTRS                 { CACHE64_POLSEL0 }
#endif

/*!
 * @}
 */ /* end of group CACHE64_POLSEL_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CAN Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
 * @{
 */

/** CAN - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[12];
  __IO uint32_t DBTP;                              /**< Data Bit Timing and Prescaler, offset: 0xC */
  __IO uint32_t TEST;                              /**< Test, offset: 0x10 */
       uint8_t RESERVED_1[4];
  __IO uint32_t CCCR;                              /**< CC Control, offset: 0x18 */
  __IO uint32_t NBTP;                              /**< Nominal Bit Timing and Prescaler, offset: 0x1C */
  __IO uint32_t TSCC;                              /**< Timestamp Counter Configuration, offset: 0x20 */
  __I  uint32_t TSCV;                              /**< Timestamp Counter Value, offset: 0x24 */
  __IO uint32_t TOCC;                              /**< Timeout Counter Configuration, offset: 0x28 */
  __I  uint32_t TOCV;                              /**< Timeout Counter Value, offset: 0x2C */
       uint8_t RESERVED_2[16];
  __I  uint32_t ECR;                               /**< Error Counter, offset: 0x40 */
  __I  uint32_t PSR;                               /**< Protocol Status, offset: 0x44 */
  __IO uint32_t TDCR;                              /**< Transmitter Delay Compensator, offset: 0x48 */
       uint8_t RESERVED_3[4];
  __IO uint32_t IR;                                /**< Interrupt, offset: 0x50 */
  __IO uint32_t IE;                                /**< Interrupt Enable, offset: 0x54 */
  __IO uint32_t ILS;                               /**< Interrupt Line Select, offset: 0x58 */
  __IO uint32_t ILE;                               /**< Interrupt Line Enable, offset: 0x5C */
       uint8_t RESERVED_4[32];
  __IO uint32_t GFC;                               /**< Global Filter Configuration, offset: 0x80 */
  __IO uint32_t SIDFC;                             /**< Standard ID Filter Configuration, offset: 0x84 */
  __IO uint32_t XIDFC;                             /**< Extended ID Filter Configuration, offset: 0x88 */
       uint8_t RESERVED_5[4];
  __IO uint32_t XIDAM;                             /**< Extended ID AND Mask, offset: 0x90 */
  __I  uint32_t HPMS;                              /**< High Priority Message Status, offset: 0x94 */
  __IO uint32_t NDAT1;                             /**< New Data 1, offset: 0x98 */
  __IO uint32_t NDAT2;                             /**< New Data 2, offset: 0x9C */
  __IO uint32_t RXF0C;                             /**< Rx FIFO 0 Configuration, offset: 0xA0 */
  __I  uint32_t RXF0S;                             /**< Rx FIFO 0 Status, offset: 0xA4 */
  __IO uint32_t RXF0A;                             /**< Rx FIFO 0 Acknowledge, offset: 0xA8 */
  __IO uint32_t RXBC;                              /**< Rx Buffer Configuration, offset: 0xAC */
  __IO uint32_t RXF1C;                             /**< Rx FIFO 1 Configuration, offset: 0xB0 */
  __I  uint32_t RXF1S;                             /**< Rx FIFO 1 Status, offset: 0xB4 */
  __IO uint32_t RXF1A;                             /**< Rx FIFO 1 Acknowledge, offset: 0xB8 */
  __IO uint32_t RXESC;                             /**< Rx Buffer and FIFO Element Size Configuration, offset: 0xBC */
  __IO uint32_t TXBC;                              /**< Tx Buffer Configuration, offset: 0xC0 */
  __IO uint32_t TXFQS;                             /**< Tx FIFO/Queue Status, offset: 0xC4 */
  __IO uint32_t TXESC;                             /**< Tx Buffer Element Size Configuration, offset: 0xC8 */
  __I  uint32_t TXBRP;                             /**< Tx Buffer Request Pending, offset: 0xCC */
  __IO uint32_t TXBAR;                             /**< Tx Buffer Add Request, offset: 0xD0 */
  __IO uint32_t TXBCR;                             /**< Tx Buffer Cancellation Request, offset: 0xD4 */
  __I  uint32_t TXBTO;                             /**< Tx Buffer Transmission Occurred, offset: 0xD8 */
  __I  uint32_t TXBCF;                             /**< Tx Buffer Cancellation Finished, offset: 0xDC */
  __IO uint32_t TXBTIE;                            /**< Tx Buffer Transmission Interrupt Enable, offset: 0xE0 */
  __IO uint32_t TXBCIE;                            /**< Tx Buffer Cancellation Finished Interrupt Enable, offset: 0xE4 */
       uint8_t RESERVED_6[8];
  __IO uint32_t TXEFC;                             /**< Tx Event FIFO Configuration, offset: 0xF0 */
  __I  uint32_t TXEFS;                             /**< Tx Event FIFO Status, offset: 0xF4 */
  __IO uint32_t TXEFA;                             /**< Tx Event FIFO Acknowledge, offset: 0xF8 */
       uint8_t RESERVED_7[260];
  __IO uint32_t MRBA;                              /**< Message RAM Base Address, offset: 0x200 */
       uint8_t RESERVED_8[508];
  __IO uint32_t ETSCC;                             /**< External Timestamp Counter Configuration, offset: 0x400 */
       uint8_t RESERVED_9[508];
  __IO uint32_t ETSCV;                             /**< External Timestamp Counter Value, offset: 0x600 */
} CAN_Type;

/* ----------------------------------------------------------------------------
   -- CAN Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CAN_Register_Masks CAN Register Masks
 * @{
 */

/*! @name DBTP - Data Bit Timing and Prescaler */
/*! @{ */

#define CAN_DBTP_DSJW_MASK                       (0xFU)
#define CAN_DBTP_DSJW_SHIFT                      (0U)
/*! DSJW - Data (Re)Synchronization Jump Width
 */
#define CAN_DBTP_DSJW(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DSJW_SHIFT)) & CAN_DBTP_DSJW_MASK)

#define CAN_DBTP_DTSEG2_MASK                     (0xF0U)
#define CAN_DBTP_DTSEG2_SHIFT                    (4U)
/*! DTSEG2 - Data Time Segment After Sample Point
 */
#define CAN_DBTP_DTSEG2(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG2_SHIFT)) & CAN_DBTP_DTSEG2_MASK)

#define CAN_DBTP_DTSEG1_MASK                     (0x1F00U)
#define CAN_DBTP_DTSEG1_SHIFT                    (8U)
/*! DTSEG1 - Data Time Segment Before Sample Point
 */
#define CAN_DBTP_DTSEG1(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG1_SHIFT)) & CAN_DBTP_DTSEG1_MASK)

#define CAN_DBTP_DBRP_MASK                       (0x1F0000U)
#define CAN_DBTP_DBRP_SHIFT                      (16U)
/*! DBRP - Data Bit Rate Prescaler
 */
#define CAN_DBTP_DBRP(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DBRP_SHIFT)) & CAN_DBTP_DBRP_MASK)

#define CAN_DBTP_TDC_MASK                        (0x800000U)
#define CAN_DBTP_TDC_SHIFT                       (23U)
/*! TDC - Transmitter Delay Compensation
 *  0b0..Transmitter delay compensation disabled
 *  0b1..Transmitter delay compensation enabled
 */
#define CAN_DBTP_TDC(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_TDC_SHIFT)) & CAN_DBTP_TDC_MASK)
/*! @} */

/*! @name TEST - Test */
/*! @{ */

#define CAN_TEST_LBCK_MASK                       (0x10U)
#define CAN_TEST_LBCK_SHIFT                      (4U)
/*! LBCK - Loop Back Mode
 *  0b0..Loop back mode is disabled.
 *  0b1..Loop back mode is enabled.
 */
#define CAN_TEST_LBCK(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TEST_LBCK_SHIFT)) & CAN_TEST_LBCK_MASK)

#define CAN_TEST_TX_MASK                         (0x60U)
#define CAN_TEST_TX_SHIFT                        (5U)
/*! TX - Control of Transmit Pin
 *  0b00..Loop back mode is disabled.
 *  0b01..The sample point can be monitored at the CAN_TXD.
 *  0b10..CAN_TXD pin is driven LOW/dominant.
 *  0b11..CAN_TXD is driven HIGH/recessive.
 */
#define CAN_TEST_TX(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_TEST_TX_SHIFT)) & CAN_TEST_TX_MASK)

#define CAN_TEST_RX_MASK                         (0x80U)
#define CAN_TEST_RX_SHIFT                        (7U)
/*! RX - Monitors the Actual Value of the CAN_RXD
 *  0b0..The CAN bus is dominant (CAN_RXD = 0).
 *  0b1..The CAN bus is recessive (CAN_RXD = 1).
 */
#define CAN_TEST_RX(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_TEST_RX_SHIFT)) & CAN_TEST_RX_MASK)
/*! @} */

/*! @name CCCR - CC Control */
/*! @{ */

#define CAN_CCCR_INIT_MASK                       (0x1U)
#define CAN_CCCR_INIT_SHIFT                      (0U)
/*! INIT - Initialization
 *  0b0..Normal operation
 *  0b1..Initialization is started
 */
#define CAN_CCCR_INIT(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_INIT_SHIFT)) & CAN_CCCR_INIT_MASK)

#define CAN_CCCR_CCE_MASK                        (0x2U)
#define CAN_CCCR_CCE_SHIFT                       (1U)
/*! CCE - Configuration Change Enable
 *  0b0..No write access. The CPU has no write access to the protected configuration registers.
 *  0b1..Write access. The CPU has write access to the protected configuration registers.
 */
#define CAN_CCCR_CCE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CCE_SHIFT)) & CAN_CCCR_CCE_MASK)

#define CAN_CCCR_ASM_MASK                        (0x4U)
#define CAN_CCCR_ASM_SHIFT                       (2U)
/*! ASM - Restricted Operational Mode
 *  0b0..Normal CAN operation
 *  0b1..Restricted operation mode active
 */
#define CAN_CCCR_ASM(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_ASM_SHIFT)) & CAN_CCCR_ASM_MASK)

#define CAN_CCCR_CSA_MASK                        (0x8U)
#define CAN_CCCR_CSA_SHIFT                       (3U)
/*! CSA - Clock Stop Acknowledge
 *  0b0..No clock stop acknowledged.
 *  0b1..MCAN may be set in Power Down mode by stopping the internal MCAN clocks.
 */
#define CAN_CCCR_CSA(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSA_SHIFT)) & CAN_CCCR_CSA_MASK)

#define CAN_CCCR_CSR_MASK                        (0x10U)
#define CAN_CCCR_CSR_SHIFT                       (4U)
/*! CSR - Clock Stop Request
 *  0b0..No clock stop is requested.
 *  0b1..Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pending
 *       transfer requests have been completed and the CAN bus reaches idle.
 */
#define CAN_CCCR_CSR(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSR_SHIFT)) & CAN_CCCR_CSR_MASK)

#define CAN_CCCR_MON_MASK                        (0x20U)
#define CAN_CCCR_MON_SHIFT                       (5U)
/*! MON - Bus Monitoring Mode
 *  0b0..Bus Monitoring mode is disabled.
 *  0b1..Bus Monitoring mode is enabled.
 */
#define CAN_CCCR_MON(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_MON_SHIFT)) & CAN_CCCR_MON_MASK)

#define CAN_CCCR_DAR_MASK                        (0x40U)
#define CAN_CCCR_DAR_SHIFT                       (6U)
/*! DAR - Disable Automatic Retransmission
 *  0b0..Automatic retransmission of messages not transmitted successfully enabled.
 *  0b1..Automatic retransmission disabled.
 */
#define CAN_CCCR_DAR(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_DAR_SHIFT)) & CAN_CCCR_DAR_MASK)

#define CAN_CCCR_TEST_MASK                       (0x80U)
#define CAN_CCCR_TEST_SHIFT                      (7U)
/*! TEST - Test Mode Enable
 *  0b0..Normal operation
 *  0b1..Test mode enabled
 */
#define CAN_CCCR_TEST(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TEST_SHIFT)) & CAN_CCCR_TEST_MASK)

#define CAN_CCCR_FDOE_MASK                       (0x100U)
#define CAN_CCCR_FDOE_SHIFT                      (8U)
/*! FDOE - CAN FD Operation Enable
 *  0b0..CAN FD operation is disabled.
 *  0b1..CAN FD operation is enabled.
 */
#define CAN_CCCR_FDOE(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_FDOE_SHIFT)) & CAN_CCCR_FDOE_MASK)

#define CAN_CCCR_BRSE_MASK                       (0x200U)
#define CAN_CCCR_BRSE_SHIFT                      (9U)
/*! BRSE - Bit Rate Switching Enable
 *  0b0..Bit rate switching for transmissions is disabled.
 *  0b1..Bit rate switching for transmission is enabled.
 */
#define CAN_CCCR_BRSE(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_BRSE_SHIFT)) & CAN_CCCR_BRSE_MASK)

#define CAN_CCCR_PXHD_MASK                       (0x1000U)
#define CAN_CCCR_PXHD_SHIFT                      (12U)
/*! PXHD - Protocol Exception Handling Disable
 *  0b0..Protocol exception handling is enabled.
 *  0b1..Protocol exception handling is disabled.
 */
#define CAN_CCCR_PXHD(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_PXHD_SHIFT)) & CAN_CCCR_PXHD_MASK)

#define CAN_CCCR_EFBI_MASK                       (0x2000U)
#define CAN_CCCR_EFBI_SHIFT                      (13U)
/*! EFBI - Edge Filtering During Bus Integration
 *  0b0..Edge filtering is disabled.
 *  0b1..Two consecutive dominant quanta required to detect an edge for hard synchronization.
 */
#define CAN_CCCR_EFBI(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_EFBI_SHIFT)) & CAN_CCCR_EFBI_MASK)

#define CAN_CCCR_TXP_MASK                        (0x4000U)
#define CAN_CCCR_TXP_SHIFT                       (14U)
/*! TXP - Transmit Pause
 *  0b0..Transmit pause is disabled.
 *  0b1..Transmit pause is enabled.
 */
#define CAN_CCCR_TXP(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TXP_SHIFT)) & CAN_CCCR_TXP_MASK)

#define CAN_CCCR_NISO_MASK                       (0x8000U)
#define CAN_CCCR_NISO_SHIFT                      (15U)
/*! NISO - Non ISO Operation
 *  0b0..CAN FD frame format will follow according to ISO11898-1.
 *  0b1..CAN FD frame format will follow according to Bosch CAN FD Specification V1.0.
 */
#define CAN_CCCR_NISO(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_NISO_SHIFT)) & CAN_CCCR_NISO_MASK)
/*! @} */

/*! @name NBTP - Nominal Bit Timing and Prescaler */
/*! @{ */

#define CAN_NBTP_NTSEG2_MASK                     (0x7FU)
#define CAN_NBTP_NTSEG2_SHIFT                    (0U)
/*! NTSEG2 - Nominal Time Segment After Sample Point
 */
#define CAN_NBTP_NTSEG2(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG2_SHIFT)) & CAN_NBTP_NTSEG2_MASK)

#define CAN_NBTP_NTSEG1_MASK                     (0xFF00U)
#define CAN_NBTP_NTSEG1_SHIFT                    (8U)
/*! NTSEG1 - Nominal Time Segment Before Sample Point
 */
#define CAN_NBTP_NTSEG1(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG1_SHIFT)) & CAN_NBTP_NTSEG1_MASK)

#define CAN_NBTP_NBRP_MASK                       (0x1FF0000U)
#define CAN_NBTP_NBRP_SHIFT                      (16U)
/*! NBRP - Nominal Bit Rate Prescaler
 */
#define CAN_NBTP_NBRP(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NBRP_SHIFT)) & CAN_NBTP_NBRP_MASK)

#define CAN_NBTP_NSJW_MASK                       (0xFE000000U)
#define CAN_NBTP_NSJW_SHIFT                      (25U)
/*! NSJW - Nominal (Re)Synchronization Jump Width
 */
#define CAN_NBTP_NSJW(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NSJW_SHIFT)) & CAN_NBTP_NSJW_MASK)
/*! @} */

/*! @name TSCC - Timestamp Counter Configuration */
/*! @{ */

#define CAN_TSCC_TSS_MASK                        (0x3U)
#define CAN_TSCC_TSS_SHIFT                       (0U)
/*! TSS - Timestamp Select
 *  0b00, 0b11..Timestamp counter value static at 0x0000
 *  0b01..Timestamp counter value incremented according to TCP bits
 *  0b10..External timestamp counter value used
 */
#define CAN_TSCC_TSS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TSS_SHIFT)) & CAN_TSCC_TSS_MASK)

#define CAN_TSCC_TCP_MASK                        (0xF0000U)
#define CAN_TSCC_TCP_SHIFT                       (16U)
/*! TCP - Timestamp Counter Prescaler
 */
#define CAN_TSCC_TCP(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TCP_SHIFT)) & CAN_TSCC_TCP_MASK)
/*! @} */

/*! @name TSCV - Timestamp Counter Value */
/*! @{ */

#define CAN_TSCV_TSC_MASK                        (0xFFFFU)
#define CAN_TSCV_TSC_SHIFT                       (0U)
/*! TSC - Timestamp Counter
 */
#define CAN_TSCV_TSC(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TSCV_TSC_SHIFT)) & CAN_TSCV_TSC_MASK)
/*! @} */

/*! @name TOCC - Timeout Counter Configuration */
/*! @{ */

#define CAN_TOCC_ETOC_MASK                       (0x1U)
#define CAN_TOCC_ETOC_SHIFT                      (0U)
/*! ETOC - Enable Timeout Counter
 *  0b0..Timeout counter is disabled.
 *  0b1..Timeout counter is enabled.
 */
#define CAN_TOCC_ETOC(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_ETOC_SHIFT)) & CAN_TOCC_ETOC_MASK)

#define CAN_TOCC_TOS_MASK                        (0x6U)
#define CAN_TOCC_TOS_SHIFT                       (1U)
/*! TOS - Timeout Select
 *  0b00..Continuous operation
 *  0b01..Timeout is controlled by Tx event FIFO.
 *  0b10..Timeout is controlled by Rx FIFO 0.
 *  0b11..Timeout is controlled by Rx FIFO 1.
 */
#define CAN_TOCC_TOS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOS_SHIFT)) & CAN_TOCC_TOS_MASK)

#define CAN_TOCC_TOP_MASK                        (0xFFFF0000U)
#define CAN_TOCC_TOP_SHIFT                       (16U)
/*! TOP - Timeout Period
 */
#define CAN_TOCC_TOP(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOP_SHIFT)) & CAN_TOCC_TOP_MASK)
/*! @} */

/*! @name TOCV - Timeout Counter Value */
/*! @{ */

#define CAN_TOCV_TOC_MASK                        (0xFFFFU)
#define CAN_TOCV_TOC_SHIFT                       (0U)
/*! TOC - Timeout Counter
 */
#define CAN_TOCV_TOC(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TOCV_TOC_SHIFT)) & CAN_TOCV_TOC_MASK)
/*! @} */

/*! @name ECR - Error Counter */
/*! @{ */

#define CAN_ECR_TEC_MASK                         (0xFFU)
#define CAN_ECR_TEC_SHIFT                        (0U)
/*! TEC - Transmit Error Counter
 */
#define CAN_ECR_TEC(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TEC_SHIFT)) & CAN_ECR_TEC_MASK)

#define CAN_ECR_REC_MASK                         (0x7F00U)
#define CAN_ECR_REC_SHIFT                        (8U)
/*! REC - Receive Error Counter
 */
#define CAN_ECR_REC(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ECR_REC_SHIFT)) & CAN_ECR_REC_MASK)

#define CAN_ECR_RP_MASK                          (0x8000U)
#define CAN_ECR_RP_SHIFT                         (15U)
/*! RP - Receive Error Passive
 *  0b0..Below error level. The receive counter is below the error passive level of 128.
 *  0b1..At error level. The receive counter has reached the error passive level of 128.
 */
#define CAN_ECR_RP(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RP_SHIFT)) & CAN_ECR_RP_MASK)

#define CAN_ECR_CEL_MASK                         (0xFF0000U)
#define CAN_ECR_CEL_SHIFT                        (16U)
/*! CEL - CAN Error Logging
 */
#define CAN_ECR_CEL(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ECR_CEL_SHIFT)) & CAN_ECR_CEL_MASK)
/*! @} */

/*! @name PSR - Protocol Status */
/*! @{ */

#define CAN_PSR_LEC_MASK                         (0x7U)
#define CAN_PSR_LEC_SHIFT                        (0U)
/*! LEC - Last Error Code
 *  0b000..No error: No error has occurred since the LEC bits has been reset by successful reception or transmission.
 *  0b001..Stuff error: More than 5 equal bits in a sequence have occurred in a part of a received message where not allowed.
 *  0b010..Form error: A fixed format part of a received frame has the wrong format.
 *  0b011..AckError: The message transmitted by the MCAN was not acknowledged by another node.
 *  0b100..Bit1Error: During the transmission of a message (with the exception of the arbitration field), the
 *         device wanted to send a recessive level (bit of logical value 1), but the monitored bus value was dominant.
 *  0b101..Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload
 *         flag), the device wanted to send a dominant level (data or identifier bit logical value 0), but the
 *         monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11
 *         recessive bits has been monitored. This enables the CPU to monitor the processing of the Bus_Off recovery
 *         sequence (indicating the bus is not stuck at dominant or continuously disturbed).
 *  0b110..CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does
 *         not match with the CRC calculated from the received data.
 *  0b111..NoChange: Any read access to the protocol status register re-initializes the LEC bits to 0x7. When the
 *         LEC equals the value 0x7, no CAN bus event was detected since the last CPU read access to the protocol
 *         status register.
 */
#define CAN_PSR_LEC(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_PSR_LEC_SHIFT)) & CAN_PSR_LEC_MASK)

#define CAN_PSR_ACT_MASK                         (0x18U)
#define CAN_PSR_ACT_SHIFT                        (3U)
/*! ACT - Activity
 *  0b00..Synchronizing - node is synchronizing on CAN communication.
 *  0b01..Idle - node is neither receiver nor transmitter.
 *  0b10..Receiver - node is operating as receiver.
 *  0b11..Transmitter - node is operating as transmitter.
 */
#define CAN_PSR_ACT(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_PSR_ACT_SHIFT)) & CAN_PSR_ACT_MASK)

#define CAN_PSR_EP_MASK                          (0x20U)
#define CAN_PSR_EP_SHIFT                         (5U)
/*! EP - Error Passive
 *  0b0..The MCAN is in Error_Active state. It normally takes part in bus communication and sends an active error
 *       flag when an error has been detected.
 *  0b1..The MCAN is in the Error_Passive state.
 */
#define CAN_PSR_EP(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EP_SHIFT)) & CAN_PSR_EP_MASK)

#define CAN_PSR_EW_MASK                          (0x40U)
#define CAN_PSR_EW_SHIFT                         (6U)
/*! EW - Warning Status
 *  0b0..Both error counters are below the Error_Warning limit of 96.
 *  0b1..At least one of error counter has reached the Error_Warning limit of 96.
 */
#define CAN_PSR_EW(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EW_SHIFT)) & CAN_PSR_EW_MASK)

#define CAN_PSR_BO_MASK                          (0x80U)
#define CAN_PSR_BO_SHIFT                         (7U)
/*! BO - Bus Off Status
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CAN_PSR_BO(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_PSR_BO_SHIFT)) & CAN_PSR_BO_MASK)

#define CAN_PSR_DLEC_MASK                        (0x700U)
#define CAN_PSR_DLEC_SHIFT                       (8U)
/*! DLEC - Data Phase Last Error Code
 */
#define CAN_PSR_DLEC(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_PSR_DLEC_SHIFT)) & CAN_PSR_DLEC_MASK)

#define CAN_PSR_RESI_MASK                        (0x800U)
#define CAN_PSR_RESI_SHIFT                       (11U)
/*! RESI - ESI Flag of the Last Received CAN FD Message
 *  0b0..Last received CAN FD message did not have its ESI flag set.
 *  0b1..Last received CAN FD message had its ESI flag set.
 */
#define CAN_PSR_RESI(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RESI_SHIFT)) & CAN_PSR_RESI_MASK)

#define CAN_PSR_RBRS_MASK                        (0x1000U)
#define CAN_PSR_RBRS_SHIFT                       (12U)
/*! RBRS - BRS Flag of Last Received CAN FD Message
 *  0b0..Last received CAN FD message did not have its BRS flag set.
 *  0b1..Last received CAN FD message had its BRS flag set.
 */
#define CAN_PSR_RBRS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RBRS_SHIFT)) & CAN_PSR_RBRS_MASK)

#define CAN_PSR_RFDF_MASK                        (0x2000U)
#define CAN_PSR_RFDF_SHIFT                       (13U)
/*! RFDF - Received a CAN FD Message
 *  0b0..No CAN FD message received since the last CPU reset.
 *  0b1..Message in CAN FD format with FDF flag set has been received.
 */
#define CAN_PSR_RFDF(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RFDF_SHIFT)) & CAN_PSR_RFDF_MASK)

#define CAN_PSR_PXE_MASK                         (0x4000U)
#define CAN_PSR_PXE_SHIFT                        (14U)
/*! PXE - Protocol Exception Event
 *  0b0..No protocol exception event occurred since last read access.
 *  0b1..Protocol exception event occurred.
 */
#define CAN_PSR_PXE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_PSR_PXE_SHIFT)) & CAN_PSR_PXE_MASK)

#define CAN_PSR_TDCV_MASK                        (0x7F0000U)
#define CAN_PSR_TDCV_SHIFT                       (16U)
/*! TDCV - Transmitter Delay Compensation Value
 */
#define CAN_PSR_TDCV(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_PSR_TDCV_SHIFT)) & CAN_PSR_TDCV_MASK)
/*! @} */

/*! @name TDCR - Transmitter Delay Compensator */
/*! @{ */

#define CAN_TDCR_TDCF_MASK                       (0x7FU)
#define CAN_TDCR_TDCF_SHIFT                      (0U)
/*! TDCF - Transmitter Delay Compensation Filter Window Length
 */
#define CAN_TDCR_TDCF(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCF_SHIFT)) & CAN_TDCR_TDCF_MASK)

#define CAN_TDCR_TDCO_MASK                       (0x7F00U)
#define CAN_TDCR_TDCO_SHIFT                      (8U)
/*! TDCO - Transmitter Delay Compensation Offset
 */
#define CAN_TDCR_TDCO(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCO_SHIFT)) & CAN_TDCR_TDCO_MASK)
/*! @} */

/*! @name IR - Interrupt */
/*! @{ */

#define CAN_IR_RF0N_MASK                         (0x1U)
#define CAN_IR_RF0N_SHIFT                        (0U)
/*! RF0N - Rx FIFO 0 New Message
 *  0b0..No new message written to Rx FIFO 0.
 *  0b1..New message written to Rx FIFO 0.
 */
#define CAN_IR_RF0N(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0N_SHIFT)) & CAN_IR_RF0N_MASK)

#define CAN_IR_RF0W_MASK                         (0x2U)
#define CAN_IR_RF0W_SHIFT                        (1U)
/*! RF0W - Rx FIFO 0 Watermark Reached
 *  0b0..Rx FIFO 0 fill level below watermark.
 *  0b1..Rx FIFO 0 fill level reached watermark.
 */
#define CAN_IR_RF0W(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0W_SHIFT)) & CAN_IR_RF0W_MASK)

#define CAN_IR_RF0F_MASK                         (0x4U)
#define CAN_IR_RF0F_SHIFT                        (2U)
/*! RF0F - Rx FIFO 0 Full
 *  0b0..Rx FIFO 0 not full.
 *  0b1..Rx FIFO 0 full.
 */
#define CAN_IR_RF0F(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0F_SHIFT)) & CAN_IR_RF0F_MASK)

#define CAN_IR_RF0L_MASK                         (0x8U)
#define CAN_IR_RF0L_SHIFT                        (3U)
/*! RF0L - Rx FIFO 0 Message Lost
 *  0b0..No Rx FIFO 0 message lost.
 *  0b1..Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero.
 */
#define CAN_IR_RF0L(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0L_SHIFT)) & CAN_IR_RF0L_MASK)

#define CAN_IR_RF1N_MASK                         (0x10U)
#define CAN_IR_RF1N_SHIFT                        (4U)
/*! RF1N - Rx FIFO 1 New Message
 *  0b0..No new message written to Rx FIFO 1.
 *  0b1..New message written to Rx FIFO 1.
 */
#define CAN_IR_RF1N(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1N_SHIFT)) & CAN_IR_RF1N_MASK)

#define CAN_IR_RF1W_MASK                         (0x20U)
#define CAN_IR_RF1W_SHIFT                        (5U)
/*! RF1W - Rx FIFO 1 Watermark Reached
 *  0b0..Rx FIFO 1 fill level below watermark.
 *  0b1..Rx FIFO 1 fill level reached watermark.
 */
#define CAN_IR_RF1W(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1W_SHIFT)) & CAN_IR_RF1W_MASK)

#define CAN_IR_RF1F_MASK                         (0x40U)
#define CAN_IR_RF1F_SHIFT                        (6U)
/*! RF1F - Rx FIFO 1 Full
 *  0b0..Rx FIFO 1 not full.
 *  0b1..Rx FIFO 1 full.
 */
#define CAN_IR_RF1F(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1F_SHIFT)) & CAN_IR_RF1F_MASK)

#define CAN_IR_RF1L_MASK                         (0x80U)
#define CAN_IR_RF1L_SHIFT                        (7U)
/*! RF1L - Rx FIFO 1 Message Lost
 *  0b0..No Rx FIFO 1 message lost.
 *  0b1..Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero.
 */
#define CAN_IR_RF1L(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1L_SHIFT)) & CAN_IR_RF1L_MASK)

#define CAN_IR_HPM_MASK                          (0x100U)
#define CAN_IR_HPM_SHIFT                         (8U)
/*! HPM - High Priority Message
 *  0b0..No high priority message received.
 *  0b1..High priority message received.
 */
#define CAN_IR_HPM(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_HPM_SHIFT)) & CAN_IR_HPM_MASK)

#define CAN_IR_TC_MASK                           (0x200U)
#define CAN_IR_TC_SHIFT                          (9U)
/*! TC - Transmission Completed
 *  0b0..No transmission completed.
 *  0b1..Transmission completed.
 */
#define CAN_IR_TC(x)                             (((uint32_t)(((uint32_t)(x)) << CAN_IR_TC_SHIFT)) & CAN_IR_TC_MASK)

#define CAN_IR_TCF_MASK                          (0x400U)
#define CAN_IR_TCF_SHIFT                         (10U)
/*! TCF - Transmission Cancellation Finished
 *  0b0..No transmission cancellation finished.
 *  0b1..Transmission cancellation finished.
 */
#define CAN_IR_TCF(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_TCF_SHIFT)) & CAN_IR_TCF_MASK)

#define CAN_IR_TFE_MASK                          (0x800U)
#define CAN_IR_TFE_SHIFT                         (11U)
/*! TFE - Tx FIFO Empty
 *  0b0..Tx FIFO non-empty.
 *  0b1..Tx FIFO empty.
 */
#define CAN_IR_TFE(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_TFE_SHIFT)) & CAN_IR_TFE_MASK)

#define CAN_IR_TEFN_MASK                         (0x1000U)
#define CAN_IR_TEFN_SHIFT                        (12U)
/*! TEFN - Tx Event FIFO New Entry
 *  0b0..Tx event FIFO unchanged.
 *  0b1..Tx Handler wrote Tx event FIFO element.
 */
#define CAN_IR_TEFN(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFN_SHIFT)) & CAN_IR_TEFN_MASK)

#define CAN_IR_TEFW_MASK                         (0x2000U)
#define CAN_IR_TEFW_SHIFT                        (13U)
/*! TEFW - Tx Event FIFO Watermark Reached
 *  0b0..Tx event FIFO fill level below watermark.
 *  0b1..Tx event FIFO fill level reached watermark.
 */
#define CAN_IR_TEFW(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFW_SHIFT)) & CAN_IR_TEFW_MASK)

#define CAN_IR_TEFF_MASK                         (0x4000U)
#define CAN_IR_TEFF_SHIFT                        (14U)
/*! TEFF - Tx Event FIFO Full
 *  0b0..Tx event FIFO not full.
 *  0b1..Tx event FIFO full.
 */
#define CAN_IR_TEFF(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFF_SHIFT)) & CAN_IR_TEFF_MASK)

#define CAN_IR_TEFL_MASK                         (0x8000U)
#define CAN_IR_TEFL_SHIFT                        (15U)
/*! TEFL - Tx Event FIFO Element Lost
 *  0b0..No Tx event FIFO element lost.
 *  0b1..Tx event FIFO element lost, also set after write attempt to Tx event FIFO of size zero.
 */
#define CAN_IR_TEFL(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFL_SHIFT)) & CAN_IR_TEFL_MASK)

#define CAN_IR_TSW_MASK                          (0x10000U)
#define CAN_IR_TSW_SHIFT                         (16U)
/*! TSW - Timestamp Wraparound
 *  0b0..No timestamp counter wraparound.
 *  0b1..Timestamp counter wrapped around.
 */
#define CAN_IR_TSW(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_TSW_SHIFT)) & CAN_IR_TSW_MASK)

#define CAN_IR_MRAF_MASK                         (0x20000U)
#define CAN_IR_MRAF_SHIFT                        (17U)
/*! MRAF - Message RAM Access Failure
 *  0b0..No message RAM access failure occurred.
 *  0b1..Message RAM access failure occurred.
 */
#define CAN_IR_MRAF(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IR_MRAF_SHIFT)) & CAN_IR_MRAF_MASK)

#define CAN_IR_TOO_MASK                          (0x40000U)
#define CAN_IR_TOO_SHIFT                         (18U)
/*! TOO - Timeout Occurred
 *  0b0..No timeout.
 *  0b1..Timeout reached.
 */
#define CAN_IR_TOO(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_TOO_SHIFT)) & CAN_IR_TOO_MASK)

#define CAN_IR_DRX_MASK                          (0x80000U)
#define CAN_IR_DRX_SHIFT                         (19U)
/*! DRX - Message Stored in Dedicated Rx Buffer
 *  0b0..No Rx buffer updated.
 *  0b1..At least one received message stored into an Rx buffer.
 */
#define CAN_IR_DRX(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_DRX_SHIFT)) & CAN_IR_DRX_MASK)

#define CAN_IR_BEC_MASK                          (0x100000U)
#define CAN_IR_BEC_SHIFT                         (20U)
/*! BEC - Bit Error Corrected
 *  0b0..No bit error detected when reading from message RAM.
 *  0b1..Bit error detected and corrected (example, ECC).
 */
#define CAN_IR_BEC(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEC_SHIFT)) & CAN_IR_BEC_MASK)

#define CAN_IR_BEU_MASK                          (0x200000U)
#define CAN_IR_BEU_SHIFT                         (21U)
/*! BEU - Bit Error Uncorrected
 *  0b0..No bit error detected when reading from message RAM.
 *  0b1..Bit error detected, uncorrected (example, parity logic).
 */
#define CAN_IR_BEU(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEU_SHIFT)) & CAN_IR_BEU_MASK)

#define CAN_IR_ELO_MASK                          (0x400000U)
#define CAN_IR_ELO_SHIFT                         (22U)
/*! ELO - Error Logging Overflow
 *  0b0..CAN error logging counter did not overflow.
 *  0b1..Overflow of CAN error logging counter occurred.
 */
#define CAN_IR_ELO(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_ELO_SHIFT)) & CAN_IR_ELO_MASK)

#define CAN_IR_EP_MASK                           (0x800000U)
#define CAN_IR_EP_SHIFT                          (23U)
/*! EP - Error Passive
 *  0b0..Error_Passive status unchanged.
 *  0b1..Error_Passive status changed.
 */
#define CAN_IR_EP(x)                             (((uint32_t)(((uint32_t)(x)) << CAN_IR_EP_SHIFT)) & CAN_IR_EP_MASK)

#define CAN_IR_EW_MASK                           (0x1000000U)
#define CAN_IR_EW_SHIFT                          (24U)
/*! EW - Warning Status
 *  0b0..Error_Warning status unchanged.
 *  0b1..Error_Warning status changed.
 */
#define CAN_IR_EW(x)                             (((uint32_t)(((uint32_t)(x)) << CAN_IR_EW_SHIFT)) & CAN_IR_EW_MASK)

#define CAN_IR_BO_MASK                           (0x2000000U)
#define CAN_IR_BO_SHIFT                          (25U)
/*! BO - Bus_Off Status
 *  0b0..Bus_Off status unchanged.
 *  0b1..Bus_Off status changed.
 */
#define CAN_IR_BO(x)                             (((uint32_t)(((uint32_t)(x)) << CAN_IR_BO_SHIFT)) & CAN_IR_BO_MASK)

#define CAN_IR_WDI_MASK                          (0x4000000U)
#define CAN_IR_WDI_SHIFT                         (26U)
/*! WDI - Watchdog Interrupt
 *  0b0..No message RAM watchdog event occurred.
 *  0b1..Message RAM watchdog event due to missing READY.
 */
#define CAN_IR_WDI(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_WDI_SHIFT)) & CAN_IR_WDI_MASK)

#define CAN_IR_PEA_MASK                          (0x8000000U)
#define CAN_IR_PEA_SHIFT                         (27U)
/*! PEA - Protocol Error in Arbitration Phase
 *  0b0..No protocol error in arbitration phase.
 *  0b1..Protocol error in arbitration phase detected.
 */
#define CAN_IR_PEA(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_PEA_SHIFT)) & CAN_IR_PEA_MASK)

#define CAN_IR_PED_MASK                          (0x10000000U)
#define CAN_IR_PED_SHIFT                         (28U)
/*! PED - Protocol Error in Data Phase
 *  0b0..No protocol error in data phase.
 *  0b1..Protocol error in data phase detected.
 */
#define CAN_IR_PED(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_PED_SHIFT)) & CAN_IR_PED_MASK)

#define CAN_IR_ARA_MASK                          (0x20000000U)
#define CAN_IR_ARA_SHIFT                         (29U)
/*! ARA - Access to Reserved Address
 *  0b0..No access to reserved address occurred.
 *  0b1..Access to reserved address occurred.
 */
#define CAN_IR_ARA(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IR_ARA_SHIFT)) & CAN_IR_ARA_MASK)
/*! @} */

/*! @name IE - Interrupt Enable */
/*! @{ */

#define CAN_IE_RF0NE_MASK                        (0x1U)
#define CAN_IE_RF0NE_SHIFT                       (0U)
/*! RF0NE - Rx FIFO 0 New Message Interrupt Enable
 *  0b0..Interrupt disabled
 *  0b1..Interrupt enabled
 */
#define CAN_IE_RF0NE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0NE_SHIFT)) & CAN_IE_RF0NE_MASK)

#define CAN_IE_RF0WE_MASK                        (0x2U)
#define CAN_IE_RF0WE_SHIFT                       (1U)
/*! RF0WE - Rx FIFO 0 Watermark Reached Interrupt Enable
 *  0b0..Interrupt disabled
 *  0b1..Interrupt enabled
 */
#define CAN_IE_RF0WE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0WE_SHIFT)) & CAN_IE_RF0WE_MASK)

#define CAN_IE_RF0FE_MASK                        (0x4U)
#define CAN_IE_RF0FE_SHIFT                       (2U)
/*! RF0FE - Rx FIFO 0 Full Interrupt Enable
 *  0b0..Interrupt disabled
 *  0b1..Interrupt enabled
 */
#define CAN_IE_RF0FE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0FE_SHIFT)) & CAN_IE_RF0FE_MASK)

#define CAN_IE_RF0LE_MASK                        (0x8U)
#define CAN_IE_RF0LE_SHIFT                       (3U)
/*! RF0LE - Rx FIFO 0 Message Lost Interrupt Enable
 *  0b0..Interrupt disabled
 *  0b1..Interrupt enabled
 */
#define CAN_IE_RF0LE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0LE_SHIFT)) & CAN_IE_RF0LE_MASK)

#define CAN_IE_RF1NE_MASK                        (0x10U)
#define CAN_IE_RF1NE_SHIFT                       (4U)
/*! RF1NE - Rx FIFO 1 New Message Interrupt Enable
 *  0b0..Interrupt disabled
 *  0b1..Interrupt enabled
 */
#define CAN_IE_RF1NE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1NE_SHIFT)) & CAN_IE_RF1NE_MASK)

#define CAN_IE_RF1WE_MASK                        (0x20U)
#define CAN_IE_RF1WE_SHIFT                       (5U)
/*! RF1WE - Rx FIFO 1 Watermark Reached Interrupt Enable
 *  0b0..Interrupt disabled
 *  0b1..Interrupt enabled
 */
#define CAN_IE_RF1WE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1WE_SHIFT)) & CAN_IE_RF1WE_MASK)

#define CAN_IE_RF1FE_MASK                        (0x40U)
#define CAN_IE_RF1FE_SHIFT                       (6U)
/*! RF1FE - Rx FIFO 1 Full Interrupt Enable
 *  0b0..Interrupt disabled
 *  0b1..Interrupt enabled
 */
#define CAN_IE_RF1FE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1FE_SHIFT)) & CAN_IE_RF1FE_MASK)

#define CAN_IE_RF1LE_MASK                        (0x80U)
#define CAN_IE_RF1LE_SHIFT                       (7U)
/*! RF1LE - Rx FIFO 1 Message Lost Interrupt Enable
 *  0b0..Interrupt disabled
 *  0b1..Interrupt enabled
 */
#define CAN_IE_RF1LE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1LE_SHIFT)) & CAN_IE_RF1LE_MASK)

#define CAN_IE_HPME_MASK                         (0x100U)
#define CAN_IE_HPME_SHIFT                        (8U)
/*! HPME - High Priority Message Interrupt Enable
 *  0b0..Interrupt disabled
 *  0b1..Interrupt enabled
 */
#define CAN_IE_HPME(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_HPME_SHIFT)) & CAN_IE_HPME_MASK)

#define CAN_IE_TCE_MASK                          (0x200U)
#define CAN_IE_TCE_SHIFT                         (9U)
/*! TCE - Transmission Completed Interrupt Enable
 *  0b0..Interrupt disabled
 *  0b1..Interrupt enabled
 */
#define CAN_IE_TCE(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCE_SHIFT)) & CAN_IE_TCE_MASK)

#define CAN_IE_TCFE_MASK                         (0x400U)
#define CAN_IE_TCFE_SHIFT                        (10U)
/*! TCFE - Transmission Cancellation Finished Interrupt Enable
 *  0b0..Interrupt disabled
 *  0b1..Interrupt enabled
 */
#define CAN_IE_TCFE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCFE_SHIFT)) & CAN_IE_TCFE_MASK)

#define CAN_IE_TFEE_MASK                         (0x800U)
#define CAN_IE_TFEE_SHIFT                        (11U)
/*! TFEE - Tx FIFO Empty Interrupt Enable
 *  0b0..Interrupt disabled
 *  0b1..Interrupt enabled
 */
#define CAN_IE_TFEE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_TFEE_SHIFT)) & CAN_IE_TFEE_MASK)

#define CAN_IE_TEFNE_MASK                        (0x1000U)
#define CAN_IE_TEFNE_SHIFT                       (12U)
/*! TEFNE - Tx Event FIFO New Entry Interrupt Enable
 *  0b0..Interrupt disabled
 *  0b1..Interrupt enabled
 */
#define CAN_IE_TEFNE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFNE_SHIFT)) & CAN_IE_TEFNE_MASK)

#define CAN_IE_TEFWE_MASK                        (0x2000U)
#define CAN_IE_TEFWE_SHIFT                       (13U)
/*! TEFWE - Tx Event FIFO Watermark Reached Interrupt Enable
 *  0b0..Interrupt disabled
 *  0b1..Interrupt enabled
 */
#define CAN_IE_TEFWE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFWE_SHIFT)) & CAN_IE_TEFWE_MASK)

#define CAN_IE_TEFFE_MASK                        (0x4000U)
#define CAN_IE_TEFFE_SHIFT                       (14U)
/*! TEFFE - Tx Event FIFO Full Interrupt Enable
 *  0b0..Interrupt disabled
 *  0b1..Interrupt enabled
 */
#define CAN_IE_TEFFE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFFE_SHIFT)) & CAN_IE_TEFFE_MASK)

#define CAN_IE_TEFLE_MASK                        (0x8000U)
#define CAN_IE_TEFLE_SHIFT                       (15U)
/*! TEFLE - Tx Event FIFO Element Lost Interrupt Enable
 *  0b0..Interrupt disabled
 *  0b1..Interrupt enabled
 */
#define CAN_IE_TEFLE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFLE_SHIFT)) & CAN_IE_TEFLE_MASK)

#define CAN_IE_TSWE_MASK                         (0x10000U)
#define CAN_IE_TSWE_SHIFT                        (16U)
/*! TSWE - Timestamp Wraparound Interrupt Enable
 *  0b0..Interrupt disabled
 *  0b1..Interrupt enabled
 */
#define CAN_IE_TSWE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_TSWE_SHIFT)) & CAN_IE_TSWE_MASK)

#define CAN_IE_MRAFE_MASK                        (0x20000U)
#define CAN_IE_MRAFE_SHIFT                       (17U)
/*! MRAFE - Message RAM Access Failure Interrupt Enable
 *  0b0..Interrupt disabled
 *  0b1..Interrupt enabled
 */
#define CAN_IE_MRAFE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_IE_MRAFE_SHIFT)) & CAN_IE_MRAFE_MASK)

#define CAN_IE_TOOE_MASK                         (0x40000U)
#define CAN_IE_TOOE_SHIFT                        (18U)
/*! TOOE - Timeout Occurred Interrupt Enable
 *  0b0..Interrupt disabled
 *  0b1..Interrupt enabled
 */
#define CAN_IE_TOOE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_TOOE_SHIFT)) & CAN_IE_TOOE_MASK)

#define CAN_IE_DRXE_MASK                         (0x80000U)
#define CAN_IE_DRXE_SHIFT                        (19U)
/*! DRXE - Message Stored in Dedicated Rx Buffer Interrupt Enable
 *  0b0..Interrupt disabled
 *  0b1..Interrupt enabled
 */
#define CAN_IE_DRXE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_DRXE_SHIFT)) & CAN_IE_DRXE_MASK)

#define CAN_IE_BECE_MASK                         (0x100000U)
#define CAN_IE_BECE_SHIFT                        (20U)
/*! BECE - Bit Error Corrected Interrupt Enable
 *  0b0..Interrupt disabled
 *  0b1..Interrupt enabled
 */
#define CAN_IE_BECE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_BECE_SHIFT)) & CAN_IE_BECE_MASK)

#define CAN_IE_BEUE_MASK                         (0x200000U)
#define CAN_IE_BEUE_SHIFT                        (21U)
/*! BEUE - Bit Error Uncorrected Interrupt Enable
 *  0b0..Interrupt disabled
 *  0b1..Interrupt enabled
 */
#define CAN_IE_BEUE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_BEUE_SHIFT)) & CAN_IE_BEUE_MASK)

#define CAN_IE_ELOE_MASK                         (0x400000U)
#define CAN_IE_ELOE_SHIFT                        (22U)
/*! ELOE - Error Logging Overflow Interrupt Enable
 *  0b0..Interrupt disabled
 *  0b1..Interrupt enabled
 */
#define CAN_IE_ELOE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_ELOE_SHIFT)) & CAN_IE_ELOE_MASK)

#define CAN_IE_EPE_MASK                          (0x800000U)
#define CAN_IE_EPE_SHIFT                         (23U)
/*! EPE - Error Passive Interrupt Enable
 *  0b0..Interrupt disabled
 *  0b1..Interrupt enabled
 */
#define CAN_IE_EPE(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IE_EPE_SHIFT)) & CAN_IE_EPE_MASK)

#define CAN_IE_EWE_MASK                          (0x1000000U)
#define CAN_IE_EWE_SHIFT                         (24U)
/*! EWE - Warning Status Interrupt Enable
 *  0b0..Interrupt disabled
 *  0b1..Interrupt enabled
 */
#define CAN_IE_EWE(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IE_EWE_SHIFT)) & CAN_IE_EWE_MASK)

#define CAN_IE_BOE_MASK                          (0x2000000U)
#define CAN_IE_BOE_SHIFT                         (25U)
/*! BOE - Bus_Off Status Interrupt Enable
 *  0b0..Interrupt disabled
 *  0b1..Interrupt enabled
 */
#define CAN_IE_BOE(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_IE_BOE_SHIFT)) & CAN_IE_BOE_MASK)

#define CAN_IE_WDIE_MASK                         (0x4000000U)
#define CAN_IE_WDIE_SHIFT                        (26U)
/*! WDIE - Watchdog Interrupt Enable
 *  0b0..Interrupt disabled
 *  0b1..Interrupt enabled
 */
#define CAN_IE_WDIE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_WDIE_SHIFT)) & CAN_IE_WDIE_MASK)

#define CAN_IE_PEAE_MASK                         (0x8000000U)
#define CAN_IE_PEAE_SHIFT                        (27U)
/*! PEAE - Protocol Error in Arbitration Phase Interrupt Enable
 *  0b0..Interrupt disabled
 *  0b1..Interrupt enabled
 */
#define CAN_IE_PEAE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEAE_SHIFT)) & CAN_IE_PEAE_MASK)

#define CAN_IE_PEDE_MASK                         (0x10000000U)
#define CAN_IE_PEDE_SHIFT                        (28U)
/*! PEDE - Protocol Error in Data Phase Interrupt Enable
 *  0b0..Interrupt disabled
 *  0b1..Interrupt enabled
 */
#define CAN_IE_PEDE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEDE_SHIFT)) & CAN_IE_PEDE_MASK)

#define CAN_IE_ARAE_MASK                         (0x20000000U)
#define CAN_IE_ARAE_SHIFT                        (29U)
/*! ARAE - Access to Reserved Address Interrupt Enable
 *  0b0..Interrupt disabled
 *  0b1..Interrupt enabled
 */
#define CAN_IE_ARAE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_IE_ARAE_SHIFT)) & CAN_IE_ARAE_MASK)
/*! @} */

/*! @name ILS - Interrupt Line Select */
/*! @{ */

#define CAN_ILS_RF0NL_MASK                       (0x1U)
#define CAN_ILS_RF0NL_SHIFT                      (0U)
/*! RF0NL - Rx FIFO 0 New Message Interrupt Line
 *  0b0..Interrupt assigned to interrupt line MCANx_INT0
 *  0b1..Interrupt assigned to interrupt line MCANx_INT1
 */
#define CAN_ILS_RF0NL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0NL_SHIFT)) & CAN_ILS_RF0NL_MASK)

#define CAN_ILS_RF0WL_MASK                       (0x2U)
#define CAN_ILS_RF0WL_SHIFT                      (1U)
/*! RF0WL - Rx FIFO 0 Watermark Reached Interrupt Line
 *  0b0..Interrupt assigned to interrupt line MCANx_INT0
 *  0b1..Interrupt assigned to interrupt line MCANx_INT1
 */
#define CAN_ILS_RF0WL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0WL_SHIFT)) & CAN_ILS_RF0WL_MASK)

#define CAN_ILS_RF0FL_MASK                       (0x4U)
#define CAN_ILS_RF0FL_SHIFT                      (2U)
/*! RF0FL - Rx FIFO 0 Full Interrupt Line
 *  0b0..Interrupt assigned to interrupt line MCANx_INT0
 *  0b1..Interrupt assigned to interrupt line MCANx_INT1
 */
#define CAN_ILS_RF0FL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0FL_SHIFT)) & CAN_ILS_RF0FL_MASK)

#define CAN_ILS_RF0LL_MASK                       (0x8U)
#define CAN_ILS_RF0LL_SHIFT                      (3U)
/*! RF0LL - Rx FIFO 0 Message Lost Interrupt Line
 *  0b0..Interrupt assigned to interrupt line MCANx_INT0
 *  0b1..Interrupt assigned to interrupt line MCANx_INT1
 */
#define CAN_ILS_RF0LL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0LL_SHIFT)) & CAN_ILS_RF0LL_MASK)

#define CAN_ILS_RF1NL_MASK                       (0x10U)
#define CAN_ILS_RF1NL_SHIFT                      (4U)
/*! RF1NL - Rx FIFO 1 New Message Interrupt Line
 *  0b0..Interrupt assigned to interrupt line MCANx_INT0
 *  0b1..Interrupt assigned to interrupt line MCANx_INT1
 */
#define CAN_ILS_RF1NL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1NL_SHIFT)) & CAN_ILS_RF1NL_MASK)

#define CAN_ILS_RF1WL_MASK                       (0x20U)
#define CAN_ILS_RF1WL_SHIFT                      (5U)
/*! RF1WL - Rx FIFO 1 Watermark Reached Interrupt Line
 *  0b0..Interrupt assigned to interrupt line MCANx_INT0
 *  0b1..Interrupt assigned to interrupt line MCANx_INT1
 */
#define CAN_ILS_RF1WL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1WL_SHIFT)) & CAN_ILS_RF1WL_MASK)

#define CAN_ILS_RF1FL_MASK                       (0x40U)
#define CAN_ILS_RF1FL_SHIFT                      (6U)
/*! RF1FL - Rx FIFO 1 Full Interrupt Line
 *  0b0..Interrupt assigned to interrupt line MCANx_INT0
 *  0b1..Interrupt assigned to interrupt line MCANx_INT1
 */
#define CAN_ILS_RF1FL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1FL_SHIFT)) & CAN_ILS_RF1FL_MASK)

#define CAN_ILS_RF1LL_MASK                       (0x80U)
#define CAN_ILS_RF1LL_SHIFT                      (7U)
/*! RF1LL - Rx FIFO 1 Message Lost Interrupt Line
 *  0b0..Interrupt assigned to interrupt line MCANx_INT0
 *  0b1..Interrupt assigned to interrupt line MCANx_INT1
 */
#define CAN_ILS_RF1LL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1LL_SHIFT)) & CAN_ILS_RF1LL_MASK)

#define CAN_ILS_HPML_MASK                        (0x100U)
#define CAN_ILS_HPML_SHIFT                       (8U)
/*! HPML - High Priority Message Interrupt Line
 *  0b0..Interrupt assigned to interrupt line MCANx_INT0
 *  0b1..Interrupt assigned to interrupt line MCANx_INT1
 */
#define CAN_ILS_HPML(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_HPML_SHIFT)) & CAN_ILS_HPML_MASK)

#define CAN_ILS_TCL_MASK                         (0x200U)
#define CAN_ILS_TCL_SHIFT                        (9U)
/*! TCL - Transmission Completed Interrupt Line
 *  0b0..Interrupt assigned to interrupt line MCANx_INT0
 *  0b1..Interrupt assigned to interrupt line MCANx_INT1
 */
#define CAN_ILS_TCL(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCL_SHIFT)) & CAN_ILS_TCL_MASK)

#define CAN_ILS_TCFL_MASK                        (0x400U)
#define CAN_ILS_TCFL_SHIFT                       (10U)
/*! TCFL - Transmission Cancellation Finished Interrupt Line
 *  0b0..Interrupt assigned to interrupt line MCANx_INT0
 *  0b1..Interrupt assigned to interrupt line MCANx_INT1
 */
#define CAN_ILS_TCFL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCFL_SHIFT)) & CAN_ILS_TCFL_MASK)

#define CAN_ILS_TFEL_MASK                        (0x800U)
#define CAN_ILS_TFEL_SHIFT                       (11U)
/*! TFEL - Tx FIFO Empty Interrupt Line
 *  0b0..Interrupt assigned to interrupt line MCANx_INT0
 *  0b1..Interrupt assigned to interrupt line MCANx_INT1
 */
#define CAN_ILS_TFEL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TFEL_SHIFT)) & CAN_ILS_TFEL_MASK)

#define CAN_ILS_TEFNL_MASK                       (0x1000U)
#define CAN_ILS_TEFNL_SHIFT                      (12U)
/*! TEFNL - Tx Event FIFO New Entry Interrupt Line
 *  0b0..Interrupt assigned to interrupt line MCANx_INT0
 *  0b1..Interrupt assigned to interrupt line MCANx_INT1
 */
#define CAN_ILS_TEFNL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFNL_SHIFT)) & CAN_ILS_TEFNL_MASK)

#define CAN_ILS_TEFWL_MASK                       (0x2000U)
#define CAN_ILS_TEFWL_SHIFT                      (13U)
/*! TEFWL - Tx Event FIFO Watermark Reached Interrupt Line
 *  0b0..Interrupt assigned to interrupt line MCANx_INT0
 *  0b1..Interrupt assigned to interrupt line MCANx_INT1
 */
#define CAN_ILS_TEFWL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFWL_SHIFT)) & CAN_ILS_TEFWL_MASK)

#define CAN_ILS_TEFFL_MASK                       (0x4000U)
#define CAN_ILS_TEFFL_SHIFT                      (14U)
/*! TEFFL - Tx Event FIFO Full Interrupt Line
 *  0b0..Interrupt assigned to interrupt line MCANx_INT0
 *  0b1..Interrupt assigned to interrupt line MCANx_INT1
 */
#define CAN_ILS_TEFFL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFFL_SHIFT)) & CAN_ILS_TEFFL_MASK)

#define CAN_ILS_TEFLL_MASK                       (0x8000U)
#define CAN_ILS_TEFLL_SHIFT                      (15U)
/*! TEFLL - Tx Event FIFO Element Lost Interrupt Line
 *  0b0..Interrupt assigned to interrupt line MCANx_INT0
 *  0b1..Interrupt assigned to interrupt line MCANx_INT1
 */
#define CAN_ILS_TEFLL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFLL_SHIFT)) & CAN_ILS_TEFLL_MASK)

#define CAN_ILS_TSWL_MASK                        (0x10000U)
#define CAN_ILS_TSWL_SHIFT                       (16U)
/*! TSWL - Timestamp Wraparound Interrupt Line
 *  0b0..Interrupt assigned to interrupt line MCANx_INT0
 *  0b1..Interrupt assigned to interrupt line MCANx_INT1
 */
#define CAN_ILS_TSWL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TSWL_SHIFT)) & CAN_ILS_TSWL_MASK)

#define CAN_ILS_MRAFL_MASK                       (0x20000U)
#define CAN_ILS_MRAFL_SHIFT                      (17U)
/*! MRAFL - Message RAM Access Failure Interrupt Line
 *  0b0..Interrupt assigned to interrupt line MCANx_INT0
 *  0b1..Interrupt assigned to interrupt line MCANx_INT1
 */
#define CAN_ILS_MRAFL(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILS_MRAFL_SHIFT)) & CAN_ILS_MRAFL_MASK)

#define CAN_ILS_TOOL_MASK                        (0x40000U)
#define CAN_ILS_TOOL_SHIFT                       (18U)
/*! TOOL - Timeout Occurred Interrupt Line
 *  0b0..Interrupt assigned to interrupt line MCANx_INT0
 *  0b1..Interrupt assigned to interrupt line MCANx_INT1
 */
#define CAN_ILS_TOOL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TOOL_SHIFT)) & CAN_ILS_TOOL_MASK)

#define CAN_ILS_DRXL_MASK                        (0x80000U)
#define CAN_ILS_DRXL_SHIFT                       (19U)
/*! DRXL - Message Stored in Dedicated Rx Buffer Interrupt Line
 *  0b0..Interrupt assigned to interrupt line MCANx_INT0
 *  0b1..Interrupt assigned to interrupt line MCANx_INT1
 */
#define CAN_ILS_DRXL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_DRXL_SHIFT)) & CAN_ILS_DRXL_MASK)

#define CAN_ILS_BECL_MASK                        (0x100000U)
#define CAN_ILS_BECL_SHIFT                       (20U)
/*! BECL - Bit Error Corrected Interrupt Line
 *  0b0..Interrupt assigned to interrupt line MCANx_INT0
 *  0b1..Interrupt assigned to interrupt line MCANx_INT1
 */
#define CAN_ILS_BECL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BECL_SHIFT)) & CAN_ILS_BECL_MASK)

#define CAN_ILS_BEUL_MASK                        (0x200000U)
#define CAN_ILS_BEUL_SHIFT                       (21U)
/*! BEUL - Bit Error Uncorrected Interrupt Line
 *  0b0..Interrupt assigned to interrupt line MCANx_INT0
 *  0b1..Interrupt assigned to interrupt line MCANx_INT1
 */
#define CAN_ILS_BEUL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BEUL_SHIFT)) & CAN_ILS_BEUL_MASK)

#define CAN_ILS_ELOL_MASK                        (0x400000U)
#define CAN_ILS_ELOL_SHIFT                       (22U)
/*! ELOL - Error Logging Overflow Interrupt Line
 *  0b0..Interrupt assigned to interrupt line MCANx_INT0
 *  0b1..Interrupt assigned to interrupt line MCANx_INT1
 */
#define CAN_ILS_ELOL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ELOL_SHIFT)) & CAN_ILS_ELOL_MASK)

#define CAN_ILS_EPL_MASK                         (0x800000U)
#define CAN_ILS_EPL_SHIFT                        (23U)
/*! EPL - Error Passive Interrupt Line
 *  0b0..Interrupt assigned to interrupt line MCANx_INT0
 *  0b1..Interrupt assigned to interrupt line MCANx_INT1
 */
#define CAN_ILS_EPL(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EPL_SHIFT)) & CAN_ILS_EPL_MASK)

#define CAN_ILS_EWL_MASK                         (0x1000000U)
#define CAN_ILS_EWL_SHIFT                        (24U)
/*! EWL - Warning Status Interrupt Line
 *  0b0..Interrupt assigned to interrupt line MCANx_INT0
 *  0b1..Interrupt assigned to interrupt line MCANx_INT1
 */
#define CAN_ILS_EWL(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EWL_SHIFT)) & CAN_ILS_EWL_MASK)

#define CAN_ILS_BOL_MASK                         (0x2000000U)
#define CAN_ILS_BOL_SHIFT                        (25U)
/*! BOL - Bus_Off Status Interrupt Line
 *  0b0..Interrupt assigned to interrupt line MCANx_INT0
 *  0b1..Interrupt assigned to interrupt line MCANx_INT1
 */
#define CAN_ILS_BOL(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BOL_SHIFT)) & CAN_ILS_BOL_MASK)

#define CAN_ILS_WDIL_MASK                        (0x4000000U)
#define CAN_ILS_WDIL_SHIFT                       (26U)
/*! WDIL - Watchdog Interrupt Line
 *  0b0..Interrupt assigned to interrupt line MCANx_INT0
 *  0b1..Interrupt assigned to interrupt line MCANx_INT1
 */
#define CAN_ILS_WDIL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_WDIL_SHIFT)) & CAN_ILS_WDIL_MASK)

#define CAN_ILS_PEAL_MASK                        (0x8000000U)
#define CAN_ILS_PEAL_SHIFT                       (27U)
/*! PEAL - Protocol Error in Arbitration Phase Interrupt Line
 *  0b0..Interrupt assigned to interrupt line MCANx_INT0
 *  0b1..Interrupt assigned to interrupt line MCANx_INT1
 */
#define CAN_ILS_PEAL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEAL_SHIFT)) & CAN_ILS_PEAL_MASK)

#define CAN_ILS_PEDL_MASK                        (0x10000000U)
#define CAN_ILS_PEDL_SHIFT                       (28U)
/*! PEDL - Protocol Error in Data Phase Interrupt Line
 *  0b0..Interrupt assigned to interrupt line MCANx_INT0
 *  0b1..Interrupt assigned to interrupt line MCANx_INT1
 */
#define CAN_ILS_PEDL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEDL_SHIFT)) & CAN_ILS_PEDL_MASK)

#define CAN_ILS_ARAL_MASK                        (0x20000000U)
#define CAN_ILS_ARAL_SHIFT                       (29U)
/*! ARAL - Access to Reserved Address Interrupt Line
 *  0b0..Interrupt assigned to interrupt line MCANx_INT0
 *  0b1..Interrupt assigned to interrupt line MCANx_INT1
 */
#define CAN_ILS_ARAL(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ARAL_SHIFT)) & CAN_ILS_ARAL_MASK)
/*! @} */

/*! @name ILE - Interrupt Line Enable */
/*! @{ */

#define CAN_ILE_EINT0_MASK                       (0x1U)
#define CAN_ILE_EINT0_SHIFT                      (0U)
/*! EINT0 - Enable Interrupt Line 0
 *  0b0..Interrupt line to MCANx_INT0 is disabled.
 *  0b1..Interrupt line to MCANx_INT0 is enabled.
 */
#define CAN_ILE_EINT0(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT0_SHIFT)) & CAN_ILE_EINT0_MASK)

#define CAN_ILE_EINT1_MASK                       (0x2U)
#define CAN_ILE_EINT1_SHIFT                      (1U)
/*! EINT1 - Enable Interrupt Line 1
 *  0b0..Interrupt line to MCANx_INT1 is disabled.
 *  0b1..Interrupt line to MCANx_INT1 is enabled.
 */
#define CAN_ILE_EINT1(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT1_SHIFT)) & CAN_ILE_EINT1_MASK)
/*! @} */

/*! @name GFC - Global Filter Configuration */
/*! @{ */

#define CAN_GFC_RRFE_MASK                        (0x1U)
#define CAN_GFC_RRFE_SHIFT                       (0U)
/*! RRFE - Reject Remote Frames Extended
 *  0b0..Filter remote frames with 29-bit extended IDs
 *  0b1..Reject all remote frames with 29-bit extended IDs
 */
#define CAN_GFC_RRFE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFE_SHIFT)) & CAN_GFC_RRFE_MASK)

#define CAN_GFC_RRFS_MASK                        (0x2U)
#define CAN_GFC_RRFS_SHIFT                       (1U)
/*! RRFS - Reject Remote Frames Standard
 *  0b0..Filter remote frames with 11-bit standard IDs
 *  0b1..Reject all remote frames with 11-bit standard IDs
 */
#define CAN_GFC_RRFS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFS_SHIFT)) & CAN_GFC_RRFS_MASK)

#define CAN_GFC_ANFE_MASK                        (0xCU)
#define CAN_GFC_ANFE_SHIFT                       (2U)
/*! ANFE - Accept Non-matching Frames Extended
 *  0b00..Accept in Rx FIFO 0
 *  0b01..Accept in Rx FIFO 1
 *  0b10, 0b11..Reject
 */
#define CAN_GFC_ANFE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFE_SHIFT)) & CAN_GFC_ANFE_MASK)

#define CAN_GFC_ANFS_MASK                        (0x30U)
#define CAN_GFC_ANFS_SHIFT                       (4U)
/*! ANFS - Accept Non-matching Frames Standard
 *  0b00..Accept in Rx FIFO 0
 *  0b01..Accept in Rx FIFO 1
 *  0b10, 0b11..Reject
 */
#define CAN_GFC_ANFS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFS_SHIFT)) & CAN_GFC_ANFS_MASK)
/*! @} */

/*! @name SIDFC - Standard ID Filter Configuration */
/*! @{ */

#define CAN_SIDFC_FLSSA_MASK                     (0xFFFCU)
#define CAN_SIDFC_FLSSA_SHIFT                    (2U)
/*! FLSSA - Filter List Standard Start Address
 */
#define CAN_SIDFC_FLSSA(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_FLSSA_SHIFT)) & CAN_SIDFC_FLSSA_MASK)

#define CAN_SIDFC_LSS_MASK                       (0xFF0000U)
#define CAN_SIDFC_LSS_SHIFT                      (16U)
/*! LSS - List Size Standard
 */
#define CAN_SIDFC_LSS(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_LSS_SHIFT)) & CAN_SIDFC_LSS_MASK)
/*! @} */

/*! @name XIDFC - Extended ID Filter Configuration */
/*! @{ */

#define CAN_XIDFC_FLESA_MASK                     (0xFFFCU)
#define CAN_XIDFC_FLESA_SHIFT                    (2U)
/*! FLESA - Filter List Extended Start Address
 */
#define CAN_XIDFC_FLESA(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_FLESA_SHIFT)) & CAN_XIDFC_FLESA_MASK)

#define CAN_XIDFC_LSE_MASK                       (0xFF0000U)
#define CAN_XIDFC_LSE_SHIFT                      (16U)
/*! LSE - List Size Extended
 */
#define CAN_XIDFC_LSE(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_LSE_SHIFT)) & CAN_XIDFC_LSE_MASK)
/*! @} */

/*! @name XIDAM - Extended ID AND Mask */
/*! @{ */

#define CAN_XIDAM_EIDM_MASK                      (0x1FFFFFFFU)
#define CAN_XIDAM_EIDM_SHIFT                     (0U)
/*! EIDM - Extended ID Mask
 */
#define CAN_XIDAM_EIDM(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_XIDAM_EIDM_SHIFT)) & CAN_XIDAM_EIDM_MASK)
/*! @} */

/*! @name HPMS - High Priority Message Status */
/*! @{ */

#define CAN_HPMS_BIDX_MASK                       (0x3FU)
#define CAN_HPMS_BIDX_SHIFT                      (0U)
/*! BIDX - Buffer Index
 */
#define CAN_HPMS_BIDX(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_BIDX_SHIFT)) & CAN_HPMS_BIDX_MASK)

#define CAN_HPMS_MSI_MASK                        (0xC0U)
#define CAN_HPMS_MSI_SHIFT                       (6U)
/*! MSI - Message Storage Indicator
 *  0b00..No FIFO selected
 *  0b01..FIFO message lost
 *  0b10..Message stored in FIFO 0
 *  0b11..Message stored in FIFO 1
 */
#define CAN_HPMS_MSI(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_MSI_SHIFT)) & CAN_HPMS_MSI_MASK)

#define CAN_HPMS_FIDX_MASK                       (0x7F00U)
#define CAN_HPMS_FIDX_SHIFT                      (8U)
/*! FIDX - Filter Index
 */
#define CAN_HPMS_FIDX(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FIDX_SHIFT)) & CAN_HPMS_FIDX_MASK)

#define CAN_HPMS_FLST_MASK                       (0x8000U)
#define CAN_HPMS_FLST_SHIFT                      (15U)
/*! FLST - Filter List
 *  0b0..Standard filter list
 *  0b1..Extended filter list
 */
#define CAN_HPMS_FLST(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FLST_SHIFT)) & CAN_HPMS_FLST_MASK)
/*! @} */

/*! @name NDAT1 - New Data 1 */
/*! @{ */

#define CAN_NDAT1_ND_MASK                        (0xFFFFFFFFU)
#define CAN_NDAT1_ND_SHIFT                       (0U)
/*! ND - New Data
 */
#define CAN_NDAT1_ND(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_NDAT1_ND_SHIFT)) & CAN_NDAT1_ND_MASK)
/*! @} */

/*! @name NDAT2 - New Data 2 */
/*! @{ */

#define CAN_NDAT2_ND_MASK                        (0xFFFFFFFFU)
#define CAN_NDAT2_ND_SHIFT                       (0U)
/*! ND - New Data
 */
#define CAN_NDAT2_ND(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_NDAT2_ND_SHIFT)) & CAN_NDAT2_ND_MASK)
/*! @} */

/*! @name RXF0C - Rx FIFO 0 Configuration */
/*! @{ */

#define CAN_RXF0C_F0SA_MASK                      (0xFFFCU)
#define CAN_RXF0C_F0SA_SHIFT                     (2U)
/*! F0SA - Rx FIFO 0 Start Address
 */
#define CAN_RXF0C_F0SA(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0SA_SHIFT)) & CAN_RXF0C_F0SA_MASK)

#define CAN_RXF0C_F0S_MASK                       (0x7F0000U)
#define CAN_RXF0C_F0S_SHIFT                      (16U)
/*! F0S - Rx FIFO 0 Size
 */
#define CAN_RXF0C_F0S(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0S_SHIFT)) & CAN_RXF0C_F0S_MASK)

#define CAN_RXF0C_F0WM_MASK                      (0x7F000000U)
#define CAN_RXF0C_F0WM_SHIFT                     (24U)
/*! F0WM - Rx FIFO 0 Watermark
 */
#define CAN_RXF0C_F0WM(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0WM_SHIFT)) & CAN_RXF0C_F0WM_MASK)

#define CAN_RXF0C_F0OM_MASK                      (0x80000000U)
#define CAN_RXF0C_F0OM_SHIFT                     (31U)
/*! F0OM - FIFO 0 Operation Mode
 *  0b0..FIFO 0 blocking mode
 *  0b1..FIFO 0 overwrite mode
 */
#define CAN_RXF0C_F0OM(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0OM_SHIFT)) & CAN_RXF0C_F0OM_MASK)
/*! @} */

/*! @name RXF0S - Rx FIFO 0 Status */
/*! @{ */

#define CAN_RXF0S_F0FL_MASK                      (0x7FU)
#define CAN_RXF0S_F0FL_SHIFT                     (0U)
/*! F0FL - Rx FIFO 0 Fill Level
 */
#define CAN_RXF0S_F0FL(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0FL_SHIFT)) & CAN_RXF0S_F0FL_MASK)

#define CAN_RXF0S_F0GI_MASK                      (0x3F00U)
#define CAN_RXF0S_F0GI_SHIFT                     (8U)
/*! F0GI - Rx FIFO 0 Get Index
 */
#define CAN_RXF0S_F0GI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0GI_SHIFT)) & CAN_RXF0S_F0GI_MASK)

#define CAN_RXF0S_F0PI_MASK                      (0x3F0000U)
#define CAN_RXF0S_F0PI_SHIFT                     (16U)
/*! F0PI - Rx FIFO 0 Put Index
 */
#define CAN_RXF0S_F0PI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0PI_SHIFT)) & CAN_RXF0S_F0PI_MASK)

#define CAN_RXF0S_F0F_MASK                       (0x1000000U)
#define CAN_RXF0S_F0F_SHIFT                      (24U)
/*! F0F - Rx FIFO 0 Full
 *  0b0..Rx FIFO 0 not full
 *  0b1..Rx FIFO 0 full
 */
#define CAN_RXF0S_F0F(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0F_SHIFT)) & CAN_RXF0S_F0F_MASK)

#define CAN_RXF0S_RF0L_MASK                      (0x2000000U)
#define CAN_RXF0S_RF0L_SHIFT                     (25U)
/*! RF0L - Rx FIFO 0 Message Lost
 */
#define CAN_RXF0S_RF0L(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_RF0L_SHIFT)) & CAN_RXF0S_RF0L_MASK)
/*! @} */

/*! @name RXF0A - Rx FIFO 0 Acknowledge */
/*! @{ */

#define CAN_RXF0A_F0AI_MASK                      (0x3FU)
#define CAN_RXF0A_F0AI_SHIFT                     (0U)
/*! F0AI - Rx FIFO 0 Acknowledge Index
 */
#define CAN_RXF0A_F0AI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF0A_F0AI_SHIFT)) & CAN_RXF0A_F0AI_MASK)
/*! @} */

/*! @name RXBC - Rx Buffer Configuration */
/*! @{ */

#define CAN_RXBC_RBSA_MASK                       (0xFFFCU)
#define CAN_RXBC_RBSA_SHIFT                      (2U)
/*! RBSA - Rx Buffer Start Address
 */
#define CAN_RXBC_RBSA(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_RXBC_RBSA_SHIFT)) & CAN_RXBC_RBSA_MASK)
/*! @} */

/*! @name RXF1C - Rx FIFO 1 Configuration */
/*! @{ */

#define CAN_RXF1C_F1SA_MASK                      (0xFFFCU)
#define CAN_RXF1C_F1SA_SHIFT                     (2U)
/*! F1SA - Rx FIFO 1 Start Address
 */
#define CAN_RXF1C_F1SA(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1SA_SHIFT)) & CAN_RXF1C_F1SA_MASK)

#define CAN_RXF1C_F1S_MASK                       (0x7F0000U)
#define CAN_RXF1C_F1S_SHIFT                      (16U)
/*! F1S - Rx FIFO 1 Size
 */
#define CAN_RXF1C_F1S(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1S_SHIFT)) & CAN_RXF1C_F1S_MASK)

#define CAN_RXF1C_F1WM_MASK                      (0x7F000000U)
#define CAN_RXF1C_F1WM_SHIFT                     (24U)
/*! F1WM - Rx FIFO 1 Watermark
 */
#define CAN_RXF1C_F1WM(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1WM_SHIFT)) & CAN_RXF1C_F1WM_MASK)

#define CAN_RXF1C_F1OM_MASK                      (0x80000000U)
#define CAN_RXF1C_F1OM_SHIFT                     (31U)
/*! F1OM - FIFO 1 Operation Mode
 *  0b0..FIFO 1 blocking mode
 *  0b1..FIFO 1 overwrite mode
 */
#define CAN_RXF1C_F1OM(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1OM_SHIFT)) & CAN_RXF1C_F1OM_MASK)
/*! @} */

/*! @name RXF1S - Rx FIFO 1 Status */
/*! @{ */

#define CAN_RXF1S_F1FL_MASK                      (0x7FU)
#define CAN_RXF1S_F1FL_SHIFT                     (0U)
/*! F1FL - Rx FIFO 1 Fill Level
 */
#define CAN_RXF1S_F1FL(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1FL_SHIFT)) & CAN_RXF1S_F1FL_MASK)

#define CAN_RXF1S_F1GI_MASK                      (0x3F00U)
#define CAN_RXF1S_F1GI_SHIFT                     (8U)
/*! F1GI - Rx FIFO 1 Get Index
 */
#define CAN_RXF1S_F1GI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1GI_SHIFT)) & CAN_RXF1S_F1GI_MASK)

#define CAN_RXF1S_F1PI_MASK                      (0x3F0000U)
#define CAN_RXF1S_F1PI_SHIFT                     (16U)
/*! F1PI - Rx FIFO 1 Put Index
 */
#define CAN_RXF1S_F1PI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1PI_SHIFT)) & CAN_RXF1S_F1PI_MASK)

#define CAN_RXF1S_F1F_MASK                       (0x1000000U)
#define CAN_RXF1S_F1F_SHIFT                      (24U)
/*! F1F - Rx FIFO 1 Full
 *  0b0..Rx FIFO 1 not full
 *  0b1..Rx FIFO 1 full
 */
#define CAN_RXF1S_F1F(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1F_SHIFT)) & CAN_RXF1S_F1F_MASK)

#define CAN_RXF1S_RF1L_MASK                      (0x2000000U)
#define CAN_RXF1S_RF1L_SHIFT                     (25U)
/*! RF1L - Rx FIFO 1 message lost.
 *  0b0..No Rx FIFO 1 message lost.
 *  0b1..Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero.
 */
#define CAN_RXF1S_RF1L(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_RF1L_SHIFT)) & CAN_RXF1S_RF1L_MASK)
/*! @} */

/*! @name RXF1A - Rx FIFO 1 Acknowledge */
/*! @{ */

#define CAN_RXF1A_F1AI_MASK                      (0x3FU)
#define CAN_RXF1A_F1AI_SHIFT                     (0U)
/*! F1AI - Rx FIFO 1 Acknowledge Index
 */
#define CAN_RXF1A_F1AI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXF1A_F1AI_SHIFT)) & CAN_RXF1A_F1AI_MASK)
/*! @} */

/*! @name RXESC - Rx Buffer and FIFO Element Size Configuration */
/*! @{ */

#define CAN_RXESC_F0DS_MASK                      (0x7U)
#define CAN_RXESC_F0DS_SHIFT                     (0U)
/*! F0DS - Rx FIFO 0 Data Field Size
 *  0b000..8 byte data field
 *  0b001..12 byte data field
 *  0b010..16 byte data field
 *  0b011..20 byte data field
 *  0b100..24 byte data field
 *  0b101..32 byte data field
 *  0b110..48 byte data field
 *  0b111..64 byte data field
 */
#define CAN_RXESC_F0DS(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F0DS_SHIFT)) & CAN_RXESC_F0DS_MASK)

#define CAN_RXESC_F1DS_MASK                      (0x70U)
#define CAN_RXESC_F1DS_SHIFT                     (4U)
/*! F1DS - Rx FIFO 1 Data Field Size
 *  0b000..8 byte data field
 *  0b001..12 byte data field
 *  0b010..16 byte data field
 *  0b011..20 byte data field
 *  0b100..24 byte data field
 *  0b101..32 byte data field
 *  0b110..48 byte data field
 *  0b111..64 byte data field
 */
#define CAN_RXESC_F1DS(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F1DS_SHIFT)) & CAN_RXESC_F1DS_MASK)

#define CAN_RXESC_RBDS_MASK                      (0x700U)
#define CAN_RXESC_RBDS_SHIFT                     (8U)
/*! RBDS - Rx Buffer Data Field Size
 *  0b000..8 byte data field
 *  0b001..12 byte data field
 *  0b010..16 byte data field
 *  0b011..20 byte data field
 *  0b100..24 byte data field
 *  0b101..32 byte data field
 *  0b110..48 byte data field
 *  0b111..64 byte data field
 */
#define CAN_RXESC_RBDS(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_RBDS_SHIFT)) & CAN_RXESC_RBDS_MASK)
/*! @} */

/*! @name TXBC - Tx Buffer Configuration */
/*! @{ */

#define CAN_TXBC_TBSA_MASK                       (0xFFFCU)
#define CAN_TXBC_TBSA_SHIFT                      (2U)
/*! TBSA - Tx Buffers Start Address
 */
#define CAN_TXBC_TBSA(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TBSA_SHIFT)) & CAN_TXBC_TBSA_MASK)

#define CAN_TXBC_NDTB_MASK                       (0x3F0000U)
#define CAN_TXBC_NDTB_SHIFT                      (16U)
/*! NDTB - Number of Dedicated Transmit Buffers
 */
#define CAN_TXBC_NDTB(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_NDTB_SHIFT)) & CAN_TXBC_NDTB_MASK)

#define CAN_TXBC_TFQS_MASK                       (0x3F000000U)
#define CAN_TXBC_TFQS_SHIFT                      (24U)
/*! TFQS - Transmit FIFO/Queue Size
 */
#define CAN_TXBC_TFQS(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQS_SHIFT)) & CAN_TXBC_TFQS_MASK)

#define CAN_TXBC_TFQM_MASK                       (0x40000000U)
#define CAN_TXBC_TFQM_SHIFT                      (30U)
/*! TFQM - Tx FIFO/Queue Mode
 *  0b0..Tx FIFO operation
 *  0b1..Tx queue operation
 */
#define CAN_TXBC_TFQM(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQM_SHIFT)) & CAN_TXBC_TFQM_MASK)
/*! @} */

/*! @name TXFQS - Tx FIFO/Queue Status */
/*! @{ */

#define CAN_TXFQS_TFGI_MASK                      (0x1F00U)
#define CAN_TXFQS_TFGI_SHIFT                     (8U)
/*! TFGI - Tx FIFO Get Index
 */
#define CAN_TXFQS_TFGI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFGI_SHIFT)) & CAN_TXFQS_TFGI_MASK)

#define CAN_TXFQS_TFQPI_MASK                     (0x1F0000U)
#define CAN_TXFQS_TFQPI_SHIFT                    (16U)
/*! TFQPI - Tx FIFO/Queue Put Index
 */
#define CAN_TXFQS_TFQPI(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQPI_SHIFT)) & CAN_TXFQS_TFQPI_MASK)

#define CAN_TXFQS_TFQF_MASK                      (0x200000U)
#define CAN_TXFQS_TFQF_SHIFT                     (21U)
/*! TFQF - Tx FIFO/Queue Full
 *  0b0..Tx FIFO/Queue not full
 *  0b1..Tx FIFO/Queue full
 */
#define CAN_TXFQS_TFQF(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQF_SHIFT)) & CAN_TXFQS_TFQF_MASK)
/*! @} */

/*! @name TXESC - Tx Buffer Element Size Configuration */
/*! @{ */

#define CAN_TXESC_TBDS_MASK                      (0x7U)
#define CAN_TXESC_TBDS_SHIFT                     (0U)
/*! TBDS - Tx Buffer Data Field Size
 *  0b000..8 byte data field
 *  0b001..12 byte data field
 *  0b010..16 byte data field
 *  0b011..20 byte data field
 *  0b100..24 byte data field
 *  0b101..32 byte data field
 *  0b110..48 byte data field
 *  0b111..64 byte data field
 */
#define CAN_TXESC_TBDS(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXESC_TBDS_SHIFT)) & CAN_TXESC_TBDS_MASK)
/*! @} */

/*! @name TXBRP - Tx Buffer Request Pending */
/*! @{ */

#define CAN_TXBRP_TRP_MASK                       (0xFFFFFFFFU)
#define CAN_TXBRP_TRP_SHIFT                      (0U)
/*! TRP - Transmission Request Pending
 */
#define CAN_TXBRP_TRP(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TXBRP_TRP_SHIFT)) & CAN_TXBRP_TRP_MASK)
/*! @} */

/*! @name TXBAR - Tx Buffer Add Request */
/*! @{ */

#define CAN_TXBAR_AR_MASK                        (0xFFFFFFFFU)
#define CAN_TXBAR_AR_SHIFT                       (0U)
/*! AR - Add Request
 */
#define CAN_TXBAR_AR(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TXBAR_AR_SHIFT)) & CAN_TXBAR_AR_MASK)
/*! @} */

/*! @name TXBCR - Tx Buffer Cancellation Request */
/*! @{ */

#define CAN_TXBCR_CR_MASK                        (0xFFFFFFFFU)
#define CAN_TXBCR_CR_SHIFT                       (0U)
/*! CR - Cancellation Request
 */
#define CAN_TXBCR_CR(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TXBCR_CR_SHIFT)) & CAN_TXBCR_CR_MASK)
/*! @} */

/*! @name TXBTO - Tx Buffer Transmission Occurred */
/*! @{ */

#define CAN_TXBTO_TO_MASK                        (0xFFFFFFFFU)
#define CAN_TXBTO_TO_SHIFT                       (0U)
/*! TO - Transmission Occurred
 */
#define CAN_TXBTO_TO(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TXBTO_TO_SHIFT)) & CAN_TXBTO_TO_MASK)
/*! @} */

/*! @name TXBCF - Tx Buffer Cancellation Finished */
/*! @{ */

#define CAN_TXBCF_TO_MASK                        (0xFFFFFFFFU)
#define CAN_TXBCF_TO_SHIFT                       (0U)
/*! TO - Cancellation Finished
 */
#define CAN_TXBCF_TO(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_TXBCF_TO_SHIFT)) & CAN_TXBCF_TO_MASK)
/*! @} */

/*! @name TXBTIE - Tx Buffer Transmission Interrupt Enable */
/*! @{ */

#define CAN_TXBTIE_TIE_MASK                      (0xFFFFFFFFU)
#define CAN_TXBTIE_TIE_SHIFT                     (0U)
/*! TIE - Transmission Interrupt Enable
 */
#define CAN_TXBTIE_TIE(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXBTIE_TIE_SHIFT)) & CAN_TXBTIE_TIE_MASK)
/*! @} */

/*! @name TXBCIE - Tx Buffer Cancellation Finished Interrupt Enable */
/*! @{ */

#define CAN_TXBCIE_CFIE_MASK                     (0xFFFFFFFFU)
#define CAN_TXBCIE_CFIE_SHIFT                    (0U)
/*! CFIE - Cancellation Finished Interrupt Enable
 */
#define CAN_TXBCIE_CFIE(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_TXBCIE_CFIE_SHIFT)) & CAN_TXBCIE_CFIE_MASK)
/*! @} */

/*! @name TXEFC - Tx Event FIFO Configuration */
/*! @{ */

#define CAN_TXEFC_EFSA_MASK                      (0xFFFCU)
#define CAN_TXEFC_EFSA_SHIFT                     (2U)
/*! EFSA - Event FIFO Start Address
 */
#define CAN_TXEFC_EFSA(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFSA_SHIFT)) & CAN_TXEFC_EFSA_MASK)

#define CAN_TXEFC_EFS_MASK                       (0x3F0000U)
#define CAN_TXEFC_EFS_SHIFT                      (16U)
/*! EFS - Event FIFO Size
 */
#define CAN_TXEFC_EFS(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFS_SHIFT)) & CAN_TXEFC_EFS_MASK)

#define CAN_TXEFC_EFWM_MASK                      (0x3F000000U)
#define CAN_TXEFC_EFWM_SHIFT                     (24U)
/*! EFWM - Event FIFO Watermark
 */
#define CAN_TXEFC_EFWM(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFWM_SHIFT)) & CAN_TXEFC_EFWM_MASK)
/*! @} */

/*! @name TXEFS - Tx Event FIFO Status */
/*! @{ */

#define CAN_TXEFS_EFFL_MASK                      (0x3FU)
#define CAN_TXEFS_EFFL_SHIFT                     (0U)
/*! EFFL - Event FIFO Fill Level
 */
#define CAN_TXEFS_EFFL(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFFL_SHIFT)) & CAN_TXEFS_EFFL_MASK)

#define CAN_TXEFS_EFGI_MASK                      (0x1F00U)
#define CAN_TXEFS_EFGI_SHIFT                     (8U)
/*! EFGI - Event FIFO Get Index
 */
#define CAN_TXEFS_EFGI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFGI_SHIFT)) & CAN_TXEFS_EFGI_MASK)

#define CAN_TXEFS_EFPI_MASK                      (0x3F0000U)
#define CAN_TXEFS_EFPI_SHIFT                     (16U)
/*! EFPI - Event FIFO Put Index
 */
#define CAN_TXEFS_EFPI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFPI_SHIFT)) & CAN_TXEFS_EFPI_MASK)

#define CAN_TXEFS_EFF_MASK                       (0x1000000U)
#define CAN_TXEFS_EFF_SHIFT                      (24U)
/*! EFF - Event FIFO Full
 *  0b0..Tx event FIFO not full
 *  0b1..Tx event FIFO full
 */
#define CAN_TXEFS_EFF(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFF_SHIFT)) & CAN_TXEFS_EFF_MASK)

#define CAN_TXEFS_TEFL_MASK                      (0x2000000U)
#define CAN_TXEFS_TEFL_SHIFT                     (25U)
/*! TEFL - Tx Event FIFO Element Lost
 *  0b0..No Tx event FIFO element lost.
 *  0b1..Tx event FIFO element lost, also set after write attempt to Tx event FIFO of size zero.
 */
#define CAN_TXEFS_TEFL(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_TEFL_SHIFT)) & CAN_TXEFS_TEFL_MASK)
/*! @} */

/*! @name TXEFA - Tx Event FIFO Acknowledge */
/*! @{ */

#define CAN_TXEFA_EFAI_MASK                      (0x1FU)
#define CAN_TXEFA_EFAI_SHIFT                     (0U)
/*! EFAI - Event FIFO Acknowledge Index
 */
#define CAN_TXEFA_EFAI(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_TXEFA_EFAI_SHIFT)) & CAN_TXEFA_EFAI_MASK)
/*! @} */

/*! @name MRBA - Message RAM Base Address */
/*! @{ */

#define CAN_MRBA_BA_MASK                         (0xFFFF0000U)
#define CAN_MRBA_BA_SHIFT                        (16U)
/*! BA - Base Address for the message RAM in the chip memory map.
 */
#define CAN_MRBA_BA(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_MRBA_BA_SHIFT)) & CAN_MRBA_BA_MASK)
/*! @} */

/*! @name ETSCC - External Timestamp Counter Configuration */
/*! @{ */

#define CAN_ETSCC_ETCP_MASK                      (0x7FFU)
#define CAN_ETSCC_ETCP_SHIFT                     (0U)
/*! ETCP - External Timestamp Prescaler Value
 */
#define CAN_ETSCC_ETCP(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCP_SHIFT)) & CAN_ETSCC_ETCP_MASK)

#define CAN_ETSCC_ETCE_MASK                      (0x80000000U)
#define CAN_ETSCC_ETCE_SHIFT                     (31U)
/*! ETCE - External Timestamp Counter Enable
 *  0b0..External timestamp counter is disabled
 *  0b1..External timestamp counter is enabled
 */
#define CAN_ETSCC_ETCE(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCE_SHIFT)) & CAN_ETSCC_ETCE_MASK)
/*! @} */

/*! @name ETSCV - External Timestamp Counter Value */
/*! @{ */

#define CAN_ETSCV_ETSC_MASK                      (0xFFFFU)
#define CAN_ETSCV_ETSC_SHIFT                     (0U)
/*! ETSC - External Timestamp Counter
 */
#define CAN_ETSCV_ETSC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ETSCV_ETSC_SHIFT)) & CAN_ETSCV_ETSC_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group CAN_Register_Masks */


/* CAN - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral CAN0 base address */
  #define CAN0_BASE                                (0x5009D000u)
  /** Peripheral CAN0 base address */
  #define CAN0_BASE_NS                             (0x4009D000u)
  /** Peripheral CAN0 base pointer */
  #define CAN0                                     ((CAN_Type *)CAN0_BASE)
  /** Peripheral CAN0 base pointer */
  #define CAN0_NS                                  ((CAN_Type *)CAN0_BASE_NS)
  /** Array initializer of CAN peripheral base addresses */
  #define CAN_BASE_ADDRS                           { CAN0_BASE }
  /** Array initializer of CAN peripheral base pointers */
  #define CAN_BASE_PTRS                            { CAN0 }
  /** Array initializer of CAN peripheral base addresses */
  #define CAN_BASE_ADDRS_NS                        { CAN0_BASE_NS }
  /** Array initializer of CAN peripheral base pointers */
  #define CAN_BASE_PTRS_NS                         { CAN0_NS }
#else
  /** Peripheral CAN0 base address */
  #define CAN0_BASE                                (0x4009D000u)
  /** Peripheral CAN0 base pointer */
  #define CAN0                                     ((CAN_Type *)CAN0_BASE)
  /** Array initializer of CAN peripheral base addresses */
  #define CAN_BASE_ADDRS                           { CAN0_BASE }
  /** Array initializer of CAN peripheral base pointers */
  #define CAN_BASE_PTRS                            { CAN0 }
#endif
/** Interrupt vectors for the CAN peripheral type */
#define CAN_IRQS                                 { { CAN0_IRQ0_IRQn, CAN0_IRQ1_IRQn } }

/*!
 * @}
 */ /* end of group CAN_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CDOG Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CDOG_Peripheral_Access_Layer CDOG Peripheral Access Layer
 * @{
 */

/** CDOG - Register Layout Typedef */
typedef struct {
  __IO uint32_t CONTROL;                           /**< Control, offset: 0x0 */
  __IO uint32_t RELOAD;                            /**< Instruction Timer reload, offset: 0x4 */
  __I  uint32_t INSTRUCTION_TIMER;                 /**< Instruction Timer, offset: 0x8 */
  __I  uint32_t SECURE_COUNTER;                    /**< Secure Counter, offset: 0xC */
  __I  uint32_t STATUS;                            /**< Status 1, offset: 0x10 */
  __I  uint32_t STATUS2;                           /**< Status 2, offset: 0x14 */
  __IO uint32_t FLAGS;                             /**< Flags, offset: 0x18 */
  __IO uint32_t PERSISTENT;                        /**< Persistent Data Storage, offset: 0x1C */
  __O  uint32_t START;                             /**< START Command, offset: 0x20 */
  __O  uint32_t STOP;                              /**< STOP Command, offset: 0x24 */
  __O  uint32_t RESTART;                           /**< RESTART Command, offset: 0x28 */
  __O  uint32_t ADD;                               /**< ADD Command, offset: 0x2C */
  __O  uint32_t ADD1;                              /**< ADD1 Command, offset: 0x30 */
  __O  uint32_t ADD16;                             /**< ADD16 Command, offset: 0x34 */
  __O  uint32_t ADD256;                            /**< ADD256 Command, offset: 0x38 */
  __O  uint32_t SUB;                               /**< SUB Command, offset: 0x3C */
  __O  uint32_t SUB1;                              /**< SUB1 Command, offset: 0x40 */
  __O  uint32_t SUB16;                             /**< SUB16 Command, offset: 0x44 */
  __O  uint32_t SUB256;                            /**< SUB256 Command, offset: 0x48 */
} CDOG_Type;

/* ----------------------------------------------------------------------------
   -- CDOG Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CDOG_Register_Masks CDOG Register Masks
 * @{
 */

/*! @name CONTROL - Control */
/*! @{ */

#define CDOG_CONTROL_LOCK_CTRL_MASK              (0x3U)
#define CDOG_CONTROL_LOCK_CTRL_SHIFT             (0U)
/*! LOCK_CTRL - Lock control
 *  0b01..Locked
 *  0b10..Unlocked
 */
#define CDOG_CONTROL_LOCK_CTRL(x)                (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_LOCK_CTRL_SHIFT)) & CDOG_CONTROL_LOCK_CTRL_MASK)

#define CDOG_CONTROL_TIMEOUT_CTRL_MASK           (0x1CU)
#define CDOG_CONTROL_TIMEOUT_CTRL_SHIFT          (2U)
/*! TIMEOUT_CTRL - TIMEOUT fault control
 *  0b100..Disable both reset and interrupt
 *  0b001..Enable reset
 *  0b010..Enable interrupt
 */
#define CDOG_CONTROL_TIMEOUT_CTRL(x)             (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_TIMEOUT_CTRL_SHIFT)) & CDOG_CONTROL_TIMEOUT_CTRL_MASK)

#define CDOG_CONTROL_MISCOMPARE_CTRL_MASK        (0xE0U)
#define CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT       (5U)
/*! MISCOMPARE_CTRL - MISCOMPARE fault control
 *  0b100..Disable both reset and interrupt
 *  0b001..Enable reset
 *  0b010..Enable interrupt
 */
#define CDOG_CONTROL_MISCOMPARE_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT)) & CDOG_CONTROL_MISCOMPARE_CTRL_MASK)

#define CDOG_CONTROL_SEQUENCE_CTRL_MASK          (0x700U)
#define CDOG_CONTROL_SEQUENCE_CTRL_SHIFT         (8U)
/*! SEQUENCE_CTRL - SEQUENCE fault control
 *  0b001..Enable reset
 *  0b010..Enable interrupt
 *  0b100..Disable both reset and interrupt
 */
#define CDOG_CONTROL_SEQUENCE_CTRL(x)            (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_SEQUENCE_CTRL_SHIFT)) & CDOG_CONTROL_SEQUENCE_CTRL_MASK)

#define CDOG_CONTROL_STATE_CTRL_MASK             (0x1C000U)
#define CDOG_CONTROL_STATE_CTRL_SHIFT            (14U)
/*! STATE_CTRL - STATE fault control
 *  0b001..Enable reset
 *  0b010..Enable interrupt
 *  0b100..Disable both reset and interrupt
 */
#define CDOG_CONTROL_STATE_CTRL(x)               (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_STATE_CTRL_SHIFT)) & CDOG_CONTROL_STATE_CTRL_MASK)

#define CDOG_CONTROL_ADDRESS_CTRL_MASK           (0xE0000U)
#define CDOG_CONTROL_ADDRESS_CTRL_SHIFT          (17U)
/*! ADDRESS_CTRL - ADDRESS fault control
 *  0b001..Enable reset
 *  0b010..Enable interrupt
 *  0b100..Disable both reset and interrupt
 */
#define CDOG_CONTROL_ADDRESS_CTRL(x)             (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_ADDRESS_CTRL_SHIFT)) & CDOG_CONTROL_ADDRESS_CTRL_MASK)

#define CDOG_CONTROL_IRQ_PAUSE_MASK              (0x30000000U)
#define CDOG_CONTROL_IRQ_PAUSE_SHIFT             (28U)
/*! IRQ_PAUSE - IRQ pause control
 *  0b01..Keep the timer running
 *  0b10..Stop the timer
 */
#define CDOG_CONTROL_IRQ_PAUSE(x)                (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_IRQ_PAUSE_SHIFT)) & CDOG_CONTROL_IRQ_PAUSE_MASK)

#define CDOG_CONTROL_DEBUG_HALT_CTRL_MASK        (0xC0000000U)
#define CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT       (30U)
/*! DEBUG_HALT_CTRL - DEBUG_HALT control
 *  0b01..Keep the timer running
 *  0b10..Stop the timer
 */
#define CDOG_CONTROL_DEBUG_HALT_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT)) & CDOG_CONTROL_DEBUG_HALT_CTRL_MASK)
/*! @} */

/*! @name RELOAD - Instruction Timer reload */
/*! @{ */

#define CDOG_RELOAD_RLOAD_MASK                   (0xFFFFFFFFU)
#define CDOG_RELOAD_RLOAD_SHIFT                  (0U)
/*! RLOAD - Instruction Timer reload value
 */
#define CDOG_RELOAD_RLOAD(x)                     (((uint32_t)(((uint32_t)(x)) << CDOG_RELOAD_RLOAD_SHIFT)) & CDOG_RELOAD_RLOAD_MASK)
/*! @} */

/*! @name INSTRUCTION_TIMER - Instruction Timer */
/*! @{ */

#define CDOG_INSTRUCTION_TIMER_INSTIM_MASK       (0xFFFFFFFFU)
#define CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT      (0U)
/*! INSTIM - Current value of the Instruction Timer
 */
#define CDOG_INSTRUCTION_TIMER_INSTIM(x)         (((uint32_t)(((uint32_t)(x)) << CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT)) & CDOG_INSTRUCTION_TIMER_INSTIM_MASK)
/*! @} */

/*! @name SECURE_COUNTER - Secure Counter */
/*! @{ */

#define CDOG_SECURE_COUNTER_SECCNT_MASK          (0xFFFFFFFFU)
#define CDOG_SECURE_COUNTER_SECCNT_SHIFT         (0U)
/*! SECCNT - Secure Counter
 */
#define CDOG_SECURE_COUNTER_SECCNT(x)            (((uint32_t)(((uint32_t)(x)) << CDOG_SECURE_COUNTER_SECCNT_SHIFT)) & CDOG_SECURE_COUNTER_SECCNT_MASK)
/*! @} */

/*! @name STATUS - Status 1 */
/*! @{ */

#define CDOG_STATUS_NUMTOF_MASK                  (0xFFU)
#define CDOG_STATUS_NUMTOF_SHIFT                 (0U)
/*! NUMTOF - Number of TIMEOUT faults since the last POR
 */
#define CDOG_STATUS_NUMTOF(x)                    (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMTOF_SHIFT)) & CDOG_STATUS_NUMTOF_MASK)

#define CDOG_STATUS_NUMMISCOMPF_MASK             (0xFF00U)
#define CDOG_STATUS_NUMMISCOMPF_SHIFT            (8U)
/*! NUMMISCOMPF - Number of MISCOMPARE faults since the last POR
 */
#define CDOG_STATUS_NUMMISCOMPF(x)               (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMMISCOMPF_SHIFT)) & CDOG_STATUS_NUMMISCOMPF_MASK)

#define CDOG_STATUS_NUMILSEQF_MASK               (0xFF0000U)
#define CDOG_STATUS_NUMILSEQF_SHIFT              (16U)
/*! NUMILSEQF - Number of SEQUENCE faults since the last POR
 */
#define CDOG_STATUS_NUMILSEQF(x)                 (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMILSEQF_SHIFT)) & CDOG_STATUS_NUMILSEQF_MASK)

#define CDOG_STATUS_CURST_MASK                   (0xF0000000U)
#define CDOG_STATUS_CURST_SHIFT                  (28U)
/*! CURST - Current State
 */
#define CDOG_STATUS_CURST(x)                     (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_CURST_SHIFT)) & CDOG_STATUS_CURST_MASK)
/*! @} */

/*! @name STATUS2 - Status 2 */
/*! @{ */

#define CDOG_STATUS2_NUMCNTF_MASK                (0xFFU)
#define CDOG_STATUS2_NUMCNTF_SHIFT               (0U)
/*! NUMCNTF - Number of CONTROL faults since the last POR
 */
#define CDOG_STATUS2_NUMCNTF(x)                  (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMCNTF_SHIFT)) & CDOG_STATUS2_NUMCNTF_MASK)

#define CDOG_STATUS2_NUMILLSTF_MASK              (0xFF00U)
#define CDOG_STATUS2_NUMILLSTF_SHIFT             (8U)
/*! NUMILLSTF - Number of STATE faults since the last POR
 */
#define CDOG_STATUS2_NUMILLSTF(x)                (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLSTF_SHIFT)) & CDOG_STATUS2_NUMILLSTF_MASK)

#define CDOG_STATUS2_NUMILLA_MASK                (0xFF0000U)
#define CDOG_STATUS2_NUMILLA_SHIFT               (16U)
/*! NUMILLA - Number of ADDRESS faults since the last POR
 */
#define CDOG_STATUS2_NUMILLA(x)                  (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLA_SHIFT)) & CDOG_STATUS2_NUMILLA_MASK)
/*! @} */

/*! @name FLAGS - Flags */
/*! @{ */

#define CDOG_FLAGS_TO_FLAG_MASK                  (0x1U)
#define CDOG_FLAGS_TO_FLAG_SHIFT                 (0U)
/*! TO_FLAG - TIMEOUT fault flag
 *  0b0..A TIMEOUT fault has not occurred
 *  0b1..A TIMEOUT fault has occurred
 */
#define CDOG_FLAGS_TO_FLAG(x)                    (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_TO_FLAG_SHIFT)) & CDOG_FLAGS_TO_FLAG_MASK)

#define CDOG_FLAGS_MISCOM_FLAG_MASK              (0x2U)
#define CDOG_FLAGS_MISCOM_FLAG_SHIFT             (1U)
/*! MISCOM_FLAG - MISCOMPARE fault flag
 *  0b0..A MISCOMPARE fault has not occurred
 *  0b1..A MISCOMPARE fault has occurred
 */
#define CDOG_FLAGS_MISCOM_FLAG(x)                (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_MISCOM_FLAG_SHIFT)) & CDOG_FLAGS_MISCOM_FLAG_MASK)

#define CDOG_FLAGS_SEQ_FLAG_MASK                 (0x4U)
#define CDOG_FLAGS_SEQ_FLAG_SHIFT                (2U)
/*! SEQ_FLAG - SEQUENCE fault flag
 *  0b0..A SEQUENCE fault has not occurred
 *  0b1..A SEQUENCE fault has occurred
 */
#define CDOG_FLAGS_SEQ_FLAG(x)                   (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_SEQ_FLAG_SHIFT)) & CDOG_FLAGS_SEQ_FLAG_MASK)

#define CDOG_FLAGS_CNT_FLAG_MASK                 (0x8U)
#define CDOG_FLAGS_CNT_FLAG_SHIFT                (3U)
/*! CNT_FLAG - CONTROL fault flag
 *  0b0..A CONTROL fault has not occurred
 *  0b1..A CONTROL fault has occurred
 */
#define CDOG_FLAGS_CNT_FLAG(x)                   (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_CNT_FLAG_SHIFT)) & CDOG_FLAGS_CNT_FLAG_MASK)

#define CDOG_FLAGS_STATE_FLAG_MASK               (0x10U)
#define CDOG_FLAGS_STATE_FLAG_SHIFT              (4U)
/*! STATE_FLAG - STATE fault flag
 *  0b0..A STATE fault has not occurred
 *  0b1..A STATE fault has occurred
 */
#define CDOG_FLAGS_STATE_FLAG(x)                 (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_STATE_FLAG_SHIFT)) & CDOG_FLAGS_STATE_FLAG_MASK)

#define CDOG_FLAGS_ADDR_FLAG_MASK                (0x20U)
#define CDOG_FLAGS_ADDR_FLAG_SHIFT               (5U)
/*! ADDR_FLAG - ADDRESS fault flag
 *  0b0..An ADDRESS fault has not occurred
 *  0b1..An ADDRESS fault has occurred
 */
#define CDOG_FLAGS_ADDR_FLAG(x)                  (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_ADDR_FLAG_SHIFT)) & CDOG_FLAGS_ADDR_FLAG_MASK)

#define CDOG_FLAGS_POR_FLAG_MASK                 (0x10000U)
#define CDOG_FLAGS_POR_FLAG_SHIFT                (16U)
/*! POR_FLAG - Power-on reset flag
 *  0b0..A Power-on reset event has not occurred
 *  0b1..A Power-on reset event has occurred
 */
#define CDOG_FLAGS_POR_FLAG(x)                   (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_POR_FLAG_SHIFT)) & CDOG_FLAGS_POR_FLAG_MASK)
/*! @} */

/*! @name PERSISTENT - Persistent Data Storage */
/*! @{ */

#define CDOG_PERSISTENT_PERSIS_MASK              (0xFFFFFFFFU)
#define CDOG_PERSISTENT_PERSIS_SHIFT             (0U)
/*! PERSIS - Persistent Storage
 */
#define CDOG_PERSISTENT_PERSIS(x)                (((uint32_t)(((uint32_t)(x)) << CDOG_PERSISTENT_PERSIS_SHIFT)) & CDOG_PERSISTENT_PERSIS_MASK)
/*! @} */

/*! @name START - START Command */
/*! @{ */

#define CDOG_START_STRT_MASK                     (0xFFFFFFFFU)
#define CDOG_START_STRT_SHIFT                    (0U)
/*! STRT - Start command
 */
#define CDOG_START_STRT(x)                       (((uint32_t)(((uint32_t)(x)) << CDOG_START_STRT_SHIFT)) & CDOG_START_STRT_MASK)
/*! @} */

/*! @name STOP - STOP Command */
/*! @{ */

#define CDOG_STOP_STP_MASK                       (0xFFFFFFFFU)
#define CDOG_STOP_STP_SHIFT                      (0U)
/*! STP - Stop command
 */
#define CDOG_STOP_STP(x)                         (((uint32_t)(((uint32_t)(x)) << CDOG_STOP_STP_SHIFT)) & CDOG_STOP_STP_MASK)
/*! @} */

/*! @name RESTART - RESTART Command */
/*! @{ */

#define CDOG_RESTART_RSTRT_MASK                  (0xFFFFFFFFU)
#define CDOG_RESTART_RSTRT_SHIFT                 (0U)
/*! RSTRT - Restart command
 */
#define CDOG_RESTART_RSTRT(x)                    (((uint32_t)(((uint32_t)(x)) << CDOG_RESTART_RSTRT_SHIFT)) & CDOG_RESTART_RSTRT_MASK)
/*! @} */

/*! @name ADD - ADD Command */
/*! @{ */

#define CDOG_ADD_AD_MASK                         (0xFFFFFFFFU)
#define CDOG_ADD_AD_SHIFT                        (0U)
/*! AD - ADD Write Value
 */
#define CDOG_ADD_AD(x)                           (((uint32_t)(((uint32_t)(x)) << CDOG_ADD_AD_SHIFT)) & CDOG_ADD_AD_MASK)
/*! @} */

/*! @name ADD1 - ADD1 Command */
/*! @{ */

#define CDOG_ADD1_AD1_MASK                       (0xFFFFFFFFU)
#define CDOG_ADD1_AD1_SHIFT                      (0U)
/*! AD1 - ADD 1
 */
#define CDOG_ADD1_AD1(x)                         (((uint32_t)(((uint32_t)(x)) << CDOG_ADD1_AD1_SHIFT)) & CDOG_ADD1_AD1_MASK)
/*! @} */

/*! @name ADD16 - ADD16 Command */
/*! @{ */

#define CDOG_ADD16_AD16_MASK                     (0xFFFFFFFFU)
#define CDOG_ADD16_AD16_SHIFT                    (0U)
/*! AD16 - ADD 16
 */
#define CDOG_ADD16_AD16(x)                       (((uint32_t)(((uint32_t)(x)) << CDOG_ADD16_AD16_SHIFT)) & CDOG_ADD16_AD16_MASK)
/*! @} */

/*! @name ADD256 - ADD256 Command */
/*! @{ */

#define CDOG_ADD256_AD256_MASK                   (0xFFFFFFFFU)
#define CDOG_ADD256_AD256_SHIFT                  (0U)
/*! AD256 - ADD 256
 */
#define CDOG_ADD256_AD256(x)                     (((uint32_t)(((uint32_t)(x)) << CDOG_ADD256_AD256_SHIFT)) & CDOG_ADD256_AD256_MASK)
/*! @} */

/*! @name SUB - SUB Command */
/*! @{ */

#define CDOG_SUB_S0B_MASK                        (0xFFFFFFFFU)
#define CDOG_SUB_S0B_SHIFT                       (0U)
/*! S0B - Subtract Write Value
 */
#define CDOG_SUB_S0B(x)                          (((uint32_t)(((uint32_t)(x)) << CDOG_SUB_S0B_SHIFT)) & CDOG_SUB_S0B_MASK)
/*! @} */

/*! @name SUB1 - SUB1 Command */
/*! @{ */

#define CDOG_SUB1_S1B_MASK                       (0xFFFFFFFFU)
#define CDOG_SUB1_S1B_SHIFT                      (0U)
/*! S1B - Subtract 1
 */
#define CDOG_SUB1_S1B(x)                         (((uint32_t)(((uint32_t)(x)) << CDOG_SUB1_S1B_SHIFT)) & CDOG_SUB1_S1B_MASK)
/*! @} */

/*! @name SUB16 - SUB16 Command */
/*! @{ */

#define CDOG_SUB16_SB16_MASK                     (0xFFFFFFFFU)
#define CDOG_SUB16_SB16_SHIFT                    (0U)
/*! SB16 - Subtract 16
 */
#define CDOG_SUB16_SB16(x)                       (((uint32_t)(((uint32_t)(x)) << CDOG_SUB16_SB16_SHIFT)) & CDOG_SUB16_SB16_MASK)
/*! @} */

/*! @name SUB256 - SUB256 Command */
/*! @{ */

#define CDOG_SUB256_SB256_MASK                   (0xFFFFFFFFU)
#define CDOG_SUB256_SB256_SHIFT                  (0U)
/*! SB256 - Subtract 256
 */
#define CDOG_SUB256_SB256(x)                     (((uint32_t)(((uint32_t)(x)) << CDOG_SUB256_SB256_SHIFT)) & CDOG_SUB256_SB256_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group CDOG_Register_Masks */


/* CDOG - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral CDOG base address */
  #define CDOG_BASE                                (0x500A1000u)
  /** Peripheral CDOG base address */
  #define CDOG_BASE_NS                             (0x400A1000u)
  /** Peripheral CDOG base pointer */
  #define CDOG                                     ((CDOG_Type *)CDOG_BASE)
  /** Peripheral CDOG base pointer */
  #define CDOG_NS                                  ((CDOG_Type *)CDOG_BASE_NS)
  /** Array initializer of CDOG peripheral base addresses */
  #define CDOG_BASE_ADDRS                          { CDOG_BASE }
  /** Array initializer of CDOG peripheral base pointers */
  #define CDOG_BASE_PTRS                           { CDOG }
  /** Array initializer of CDOG peripheral base addresses */
  #define CDOG_BASE_ADDRS_NS                       { CDOG_BASE_NS }
  /** Array initializer of CDOG peripheral base pointers */
  #define CDOG_BASE_PTRS_NS                        { CDOG_NS }
#else
  /** Peripheral CDOG base address */
  #define CDOG_BASE                                (0x400A1000u)
  /** Peripheral CDOG base pointer */
  #define CDOG                                     ((CDOG_Type *)CDOG_BASE)
  /** Array initializer of CDOG peripheral base addresses */
  #define CDOG_BASE_ADDRS                          { CDOG_BASE }
  /** Array initializer of CDOG peripheral base pointers */
  #define CDOG_BASE_PTRS                           { CDOG }
#endif
/** Interrupt vectors for the CDOG peripheral type */
#define CDOG_IRQS                                { CDOG_IRQn }

/*!
 * @}
 */ /* end of group CDOG_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CRC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
 * @{
 */

/** CRC - Register Layout Typedef */
typedef struct {
  union {                                          /* offset: 0x0 */
    struct {                                         /* offset: 0x0 */
      __IO uint8_t DATALL;                             /**< CRC_DATALL register, offset: 0x0 */
      __IO uint8_t DATALU;                             /**< CRC_DATALU register, offset: 0x1 */
      __IO uint8_t DATAHL;                             /**< CRC_DATAHL register, offset: 0x2 */
      __IO uint8_t DATAHU;                             /**< CRC_DATAHU register, offset: 0x3 */
    } ACCESS8BIT;
    struct {                                         /* offset: 0x0 */
      __IO uint16_t DATAL;                             /**< CRC_DATAL register, offset: 0x0 */
      __IO uint16_t DATAH;                             /**< CRC_DATAH register, offset: 0x2 */
    } ACCESS16BIT;
    __IO uint32_t DATA;                              /**< CRC DATA register, offset: 0x0 */
  };
  union {                                          /* offset: 0x4 */
    struct {                                         /* offset: 0x4 */
      __IO uint8_t GPOLYLL;                            /**< CRC_GPOLYLL register, offset: 0x4 */
      __IO uint8_t GPOLYLU;                            /**< CRC_GPOLYLU register, offset: 0x5 */
      __IO uint8_t GPOLYHL;                            /**< CRC_GPOLYHL register, offset: 0x6 */
      __IO uint8_t GPOLYHU;                            /**< CRC_GPOLYHU register, offset: 0x7 */
    } GPOLY_ACCESS8BIT;
    struct {                                         /* offset: 0x4 */
      __IO uint16_t GPOLYL;                            /**< CRC_GPOLYL register, offset: 0x4 */
      __IO uint16_t GPOLYH;                            /**< CRC_GPOLYH register, offset: 0x6 */
    } GPOLY_ACCESS16BIT;
    __IO uint32_t GPOLY;                             /**< CRC Polynomial register, offset: 0x4 */
  };
  union {                                          /* offset: 0x8 */
    struct {                                         /* offset: 0x8 */
           uint8_t RESERVED_0[3];
      __IO uint8_t CTRLHU;                             /**< CRC_CTRLHU register, offset: 0xB */
    } CTRL_ACCESS8BIT;
    __IO uint32_t CTRL;                              /**< CRC Control register, offset: 0x8 */
  };
} CRC_Type;

/* ----------------------------------------------------------------------------
   -- CRC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CRC_Register_Masks CRC Register Masks
 * @{
 */

/*! @name DATALL - CRC_DATALL register */
/*! @{ */

#define CRC_DATALL_DATALL_MASK                   (0xFFU)
#define CRC_DATALL_DATALL_SHIFT                  (0U)
#define CRC_DATALL_DATALL(x)                     (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK)
/*! @} */

/*! @name DATALU - CRC_DATALU register */
/*! @{ */

#define CRC_DATALU_DATALU_MASK                   (0xFFU)
#define CRC_DATALU_DATALU_SHIFT                  (0U)
#define CRC_DATALU_DATALU(x)                     (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK)
/*! @} */

/*! @name DATAHL - CRC_DATAHL register */
/*! @{ */

#define CRC_DATAHL_DATAHL_MASK                   (0xFFU)
#define CRC_DATAHL_DATAHL_SHIFT                  (0U)
#define CRC_DATAHL_DATAHL(x)                     (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK)
/*! @} */

/*! @name DATAHU - CRC_DATAHU register */
/*! @{ */

#define CRC_DATAHU_DATAHU_MASK                   (0xFFU)
#define CRC_DATAHU_DATAHU_SHIFT                  (0U)
#define CRC_DATAHU_DATAHU(x)                     (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK)
/*! @} */

/*! @name DATAL - CRC_DATAL register */
/*! @{ */

#define CRC_DATAL_DATAL_MASK                     (0xFFFFU)
#define CRC_DATAL_DATAL_SHIFT                    (0U)
#define CRC_DATAL_DATAL(x)                       (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK)
/*! @} */

/*! @name DATAH - CRC_DATAH register */
/*! @{ */

#define CRC_DATAH_DATAH_MASK                     (0xFFFFU)
#define CRC_DATAH_DATAH_SHIFT                    (0U)
#define CRC_DATAH_DATAH(x)                       (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK)
/*! @} */

/*! @name DATA - CRC DATA register */
/*! @{ */

#define CRC_DATA_LL_MASK                         (0xFFU)
#define CRC_DATA_LL_SHIFT                        (0U)
/*! LL - CRC Low Lower Byte
 */
#define CRC_DATA_LL(x)                           (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK)

#define CRC_DATA_LU_MASK                         (0xFF00U)
#define CRC_DATA_LU_SHIFT                        (8U)
/*! LU - CRC Low Upper Byte
 */
#define CRC_DATA_LU(x)                           (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK)

#define CRC_DATA_HL_MASK                         (0xFF0000U)
#define CRC_DATA_HL_SHIFT                        (16U)
/*! HL - CRC High Lower Byte
 */
#define CRC_DATA_HL(x)                           (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK)

#define CRC_DATA_HU_MASK                         (0xFF000000U)
#define CRC_DATA_HU_SHIFT                        (24U)
/*! HU - CRC High Upper Byte
 */
#define CRC_DATA_HU(x)                           (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK)
/*! @} */

/*! @name GPOLYLL - CRC_GPOLYLL register */
/*! @{ */

#define CRC_GPOLYLL_GPOLYLL_MASK                 (0xFFU)
#define CRC_GPOLYLL_GPOLYLL_SHIFT                (0U)
#define CRC_GPOLYLL_GPOLYLL(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK)
/*! @} */

/*! @name GPOLYLU - CRC_GPOLYLU register */
/*! @{ */

#define CRC_GPOLYLU_GPOLYLU_MASK                 (0xFFU)
#define CRC_GPOLYLU_GPOLYLU_SHIFT                (0U)
#define CRC_GPOLYLU_GPOLYLU(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK)
/*! @} */

/*! @name GPOLYHL - CRC_GPOLYHL register */
/*! @{ */

#define CRC_GPOLYHL_GPOLYHL_MASK                 (0xFFU)
#define CRC_GPOLYHL_GPOLYHL_SHIFT                (0U)
#define CRC_GPOLYHL_GPOLYHL(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK)
/*! @} */

/*! @name GPOLYHU - CRC_GPOLYHU register */
/*! @{ */

#define CRC_GPOLYHU_GPOLYHU_MASK                 (0xFFU)
#define CRC_GPOLYHU_GPOLYHU_SHIFT                (0U)
#define CRC_GPOLYHU_GPOLYHU(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK)
/*! @} */

/*! @name GPOLYL - CRC_GPOLYL register */
/*! @{ */

#define CRC_GPOLYL_GPOLYL_MASK                   (0xFFFFU)
#define CRC_GPOLYL_GPOLYL_SHIFT                  (0U)
#define CRC_GPOLYL_GPOLYL(x)                     (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK)
/*! @} */

/*! @name GPOLYH - CRC_GPOLYH register */
/*! @{ */

#define CRC_GPOLYH_GPOLYH_MASK                   (0xFFFFU)
#define CRC_GPOLYH_GPOLYH_SHIFT                  (0U)
#define CRC_GPOLYH_GPOLYH(x)                     (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK)
/*! @} */

/*! @name GPOLY - CRC Polynomial register */
/*! @{ */

#define CRC_GPOLY_LOW_MASK                       (0xFFFFU)
#define CRC_GPOLY_LOW_SHIFT                      (0U)
/*! LOW - Low Polynominal Half-word
 */
#define CRC_GPOLY_LOW(x)                         (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK)

#define CRC_GPOLY_HIGH_MASK                      (0xFFFF0000U)
#define CRC_GPOLY_HIGH_SHIFT                     (16U)
/*! HIGH - High Polynominal Half-word
 */
#define CRC_GPOLY_HIGH(x)                        (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK)
/*! @} */

/*! @name CTRLHU - CRC_CTRLHU register */
/*! @{ */

#define CRC_CTRLHU_TCRC_MASK                     (0x1U)
#define CRC_CTRLHU_TCRC_SHIFT                    (0U)
/*! TCRC - TCRC
 *  0b0..16-bit CRC protocol.
 *  0b1..32-bit CRC protocol.
 */
#define CRC_CTRLHU_TCRC(x)                       (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK)

#define CRC_CTRLHU_WAS_MASK                      (0x2U)
#define CRC_CTRLHU_WAS_SHIFT                     (1U)
/*! WAS - Write CRC DATA register As Seed
 *  0b0..Writes to the CRC DATA register are data values.
 *  0b1..Writes to the CRC DATA register are seed values.
 */
#define CRC_CTRLHU_WAS(x)                        (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK)

#define CRC_CTRLHU_FXOR_MASK                     (0x4U)
#define CRC_CTRLHU_FXOR_SHIFT                    (2U)
/*! FXOR - Complement Read Of CRC DATA register
 *  0b0..No XOR on reading.
 *  0b1..Invert or complement the read value of the CRC DATA register.
 */
#define CRC_CTRLHU_FXOR(x)                       (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK)

#define CRC_CTRLHU_TOTR_MASK                     (0x30U)
#define CRC_CTRLHU_TOTR_SHIFT                    (4U)
/*! TOTR - Type Of Transpose For Read
 *  0b00..No transposition.
 *  0b01..Bits in bytes are transposed; bytes are not transposed.
 *  0b10..Both bits in bytes and bytes are transposed.
 *  0b11..Only bytes are transposed; no bits in a byte are transposed.
 */
#define CRC_CTRLHU_TOTR(x)                       (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK)

#define CRC_CTRLHU_TOT_MASK                      (0xC0U)
#define CRC_CTRLHU_TOT_SHIFT                     (6U)
/*! TOT - Type Of Transpose For Writes
 *  0b00..No transposition.
 *  0b01..Bits in bytes are transposed; bytes are not transposed.
 *  0b10..Both bits in bytes and bytes are transposed.
 *  0b11..Only bytes are transposed; no bits in a byte are transposed.
 */
#define CRC_CTRLHU_TOT(x)                        (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK)
/*! @} */

/*! @name CTRL - CRC Control register */
/*! @{ */

#define CRC_CTRL_TCRC_MASK                       (0x1000000U)
#define CRC_CTRL_TCRC_SHIFT                      (24U)
/*! TCRC - TCRC
 *  0b0..16-bit CRC protocol.
 *  0b1..32-bit CRC protocol.
 */
#define CRC_CTRL_TCRC(x)                         (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK)

#define CRC_CTRL_WAS_MASK                        (0x2000000U)
#define CRC_CTRL_WAS_SHIFT                       (25U)
/*! WAS - Write CRC DATA register As Seed
 *  0b0..Writes to the CRC DATA register are data values.
 *  0b1..Writes to the CRC DATA register are seed values.
 */
#define CRC_CTRL_WAS(x)                          (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK)

#define CRC_CTRL_FXOR_MASK                       (0x4000000U)
#define CRC_CTRL_FXOR_SHIFT                      (26U)
/*! FXOR - Complement Read Of CRC DATA register
 *  0b0..No XOR on reading.
 *  0b1..Invert or complement the read value of the CRC DATA register.
 */
#define CRC_CTRL_FXOR(x)                         (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK)

#define CRC_CTRL_TOTR_MASK                       (0x30000000U)
#define CRC_CTRL_TOTR_SHIFT                      (28U)
/*! TOTR - Type Of Transpose For Read
 *  0b00..No transposition.
 *  0b01..Bits in bytes are transposed; bytes are not transposed.
 *  0b10..Both bits in bytes and bytes are transposed.
 *  0b11..Only bytes are transposed; no bits in a byte are transposed.
 */
#define CRC_CTRL_TOTR(x)                         (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK)

#define CRC_CTRL_TOT_MASK                        (0xC0000000U)
#define CRC_CTRL_TOT_SHIFT                       (30U)
/*! TOT - Type Of Transpose For Writes
 *  0b00..No transposition.
 *  0b01..Bits in bytes are transposed; bytes are not transposed.
 *  0b10..Both bits in bytes and bytes are transposed.
 *  0b11..Only bytes are transposed; no bits in a byte are transposed.
 */
#define CRC_CTRL_TOT(x)                          (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group CRC_Register_Masks */


/* CRC - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral CRC0 base address */
  #define CRC0_BASE                                (0x50095000u)
  /** Peripheral CRC0 base address */
  #define CRC0_BASE_NS                             (0x40095000u)
  /** Peripheral CRC0 base pointer */
  #define CRC0                                     ((CRC_Type *)CRC0_BASE)
  /** Peripheral CRC0 base pointer */
  #define CRC0_NS                                  ((CRC_Type *)CRC0_BASE_NS)
  /** Array initializer of CRC peripheral base addresses */
  #define CRC_BASE_ADDRS                           { CRC0_BASE }
  /** Array initializer of CRC peripheral base pointers */
  #define CRC_BASE_PTRS                            { CRC0 }
  /** Array initializer of CRC peripheral base addresses */
  #define CRC_BASE_ADDRS_NS                        { CRC0_BASE_NS }
  /** Array initializer of CRC peripheral base pointers */
  #define CRC_BASE_PTRS_NS                         { CRC0_NS }
#else
  /** Peripheral CRC0 base address */
  #define CRC0_BASE                                (0x40095000u)
  /** Peripheral CRC0 base pointer */
  #define CRC0                                     ((CRC_Type *)CRC0_BASE)
  /** Array initializer of CRC peripheral base addresses */
  #define CRC_BASE_ADDRS                           { CRC0_BASE }
  /** Array initializer of CRC peripheral base pointers */
  #define CRC_BASE_PTRS                            { CRC0 }
#endif

/*!
 * @}
 */ /* end of group CRC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CSS Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CSS_Peripheral_Access_Layer CSS Peripheral Access Layer
 * @{
 */

/** CSS - Register Layout Typedef */
typedef struct {
  __I  uint32_t CSS_STATUS;                        /**< Status register, offset: 0x0 */
  __IO uint32_t CSS_CTRL;                          /**< CSS Control register, offset: 0x4 */
  __IO uint32_t CSS_CMDCFG0;                       /**< CSS command configuration register, offset: 0x8 */
  __IO uint32_t CSS_CFG;                           /**< CSS configuration register, offset: 0xC */
  __IO uint32_t CSS_KIDX0;                         /**< Keystore index 0 - for commands that access a single key, offset: 0x10 */
  __IO uint32_t CSS_KIDX1;                         /**< Keystore index 1 - for commands that access 2 keys, offset: 0x14 */
  __IO uint32_t CSS_KPROPIN;                       /**< key properties request, offset: 0x18 */
       uint8_t RESERVED_0[4];
  __IO uint32_t CSS_DMA_SRC0;                      /**< CSS DMA Source 0, offset: 0x20 */
  __IO uint32_t CSS_DMA_SRC0_LEN;                  /**< CSS DMA Source 0 length, offset: 0x24 */
  __IO uint32_t CSS_DMA_SRC1;                      /**< CSS DMA Source 1, offset: 0x28 */
       uint8_t RESERVED_1[4];
  __IO uint32_t CSS_DMA_SRC2;                      /**< CSS DMA Source 2, offset: 0x30 */
  __IO uint32_t CSS_DMA_SRC2_LEN;                  /**< CSS DMA Source 2 length, offset: 0x34 */
  __IO uint32_t CSS_DMA_RES0;                      /**< CSS DMA Result 0, offset: 0x38 */
  __IO uint32_t CSS_DMA_RES0_LEN;                  /**< CSS DMA Result 0 Size, offset: 0x3C */
  __IO uint32_t CSS_INT_ENABLE;                    /**< Interrupt enable, offset: 0x40 */
  __O  uint32_t CSS_INT_STATUS_CLR;                /**< Interrupt status clear, offset: 0x44 */
  __O  uint32_t CSS_INT_STATUS_SET;                /**< Interrupt status set, offset: 0x48 */
  __I  uint32_t CSS_ERR_STATUS;                    /**< Status register, offset: 0x4C */
  __O  uint32_t CSS_ERR_STATUS_CLR;                /**< Interrupt status clear, offset: 0x50 */
  __I  uint32_t CSS_VERSION;                       /**< CSS Version, offset: 0x54 */
       uint8_t RESERVED_2[4];
  __I  uint32_t CSS_PRNG_DATOUT;                   /**< PRNG SW read out register, offset: 0x5C */
  __I  uint32_t CSS_GDET_EVTCNT;                   /**< CSS GDET Event Counter, offset: 0x60 */
  __O  uint32_t CSS_GDET_EVTCNT_CLR;               /**< CSS GDET Event Counter Clear, offset: 0x64 */
       uint8_t RESERVED_3[152];
  __I  uint32_t CSS_SHA2_STATUS;                   /**< CSS SHA2 Status Register, offset: 0x100 */
  __IO uint32_t CSS_SHA2_CTRL;                     /**< SHA2 Control register, offset: 0x104 */
  __IO uint32_t CSS_SHA2_DIN;                      /**< CSS SHA_DATA IN Register 0, offset: 0x108 */
  __I  uint32_t CSS_SHA2_DOUT0;                    /**< CSS CSS_SHA_DATA Out Register 0, offset: 0x10C */
  __I  uint32_t CSS_SHA2_DOUT1;                    /**< CSS SHA_DATA Out Register 1, offset: 0x110 */
  __I  uint32_t CSS_SHA2_DOUT2;                    /**< CSS SHA_DATA Out Register 2, offset: 0x114 */
  __I  uint32_t CSS_SHA2_DOUT3;                    /**< CSS SHA_DATA Out Register 3, offset: 0x118 */
  __I  uint32_t CSS_SHA2_DOUT4;                    /**< CSS SHA_DATA Out Register 4, offset: 0x11C */
  __I  uint32_t CSS_SHA2_DOUT5;                    /**< CSS SHA_DATA Out Register 5, offset: 0x120 */
  __I  uint32_t CSS_SHA2_DOUT6;                    /**< CSS SHA_DATA Out Register 6, offset: 0x124 */
  __I  uint32_t CSS_SHA2_DOUT7;                    /**< CSS SHA_DATA Out Register 7, offset: 0x128 */
  __I  uint32_t CSS_SHA2_DOUT8;                    /**< CSS CSS_SHA_DATA Out Register 8, offset: 0x12C */
  __I  uint32_t CSS_SHA2_DOUT9;                    /**< CSS SHA_DATA Out Register 9, offset: 0x130 */
  __I  uint32_t CSS_SHA2_DOUT10;                   /**< CSS SHA_DATA Out Register 10, offset: 0x134 */
  __I  uint32_t CSS_SHA2_DOUT11;                   /**< CSS SHA_DATA Out Register 11, offset: 0x138 */
  __I  uint32_t CSS_SHA2_DOUT12;                   /**< CSS SHA_DATA Out Register 12, offset: 0x13C */
  __I  uint32_t CSS_SHA2_DOUT13;                   /**< CSS SHA_DATA Out Register 13, offset: 0x140 */
  __I  uint32_t CSS_SHA2_DOUT14;                   /**< CSS SHA_DATA Out Register 14, offset: 0x144 */
  __I  uint32_t CSS_SHA2_DOUT15;                   /**< CSS SHA_DATA Out Register 15, offset: 0x148 */
       uint8_t RESERVED_4[4];
  __I  uint32_t CSS_KS0;                           /**< Status register, offset: 0x150 */
  __I  uint32_t CSS_KS1;                           /**< Status register, offset: 0x154 */
  __I  uint32_t CSS_KS2;                           /**< Status register, offset: 0x158 */
  __I  uint32_t CSS_KS3;                           /**< Status register, offset: 0x15C */
  __I  uint32_t CSS_KS4;                           /**< Status register, offset: 0x160 */
  __I  uint32_t CSS_KS5;                           /**< Status register, offset: 0x164 */
  __I  uint32_t CSS_KS6;                           /**< Status register, offset: 0x168 */
  __I  uint32_t CSS_KS7;                           /**< Status register, offset: 0x16C */
  __I  uint32_t CSS_KS8;                           /**< Status register, offset: 0x170 */
  __I  uint32_t CSS_KS9;                           /**< Status register, offset: 0x174 */
  __I  uint32_t CSS_KS10;                          /**< Status register, offset: 0x178 */
  __I  uint32_t CSS_KS11;                          /**< Status register, offset: 0x17C */
  __I  uint32_t CSS_KS12;                          /**< Status register, offset: 0x180 */
  __I  uint32_t CSS_KS13;                          /**< Status register, offset: 0x184 */
  __I  uint32_t CSS_KS14;                          /**< Status register, offset: 0x188 */
  __I  uint32_t CSS_KS15;                          /**< Status register, offset: 0x18C */
  __I  uint32_t CSS_KS16;                          /**< Status register, offset: 0x190 */
  __I  uint32_t CSS_KS17;                          /**< Status register, offset: 0x194 */
  __I  uint32_t CSS_KS18;                          /**< Status register, offset: 0x198 */
  __I  uint32_t CSS_KS19;                          /**< Status register, offset: 0x19C */
} CSS_Type;

/* ----------------------------------------------------------------------------
   -- CSS Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CSS_Register_Masks CSS Register Masks
 * @{
 */

/*! @name CSS_STATUS - Status register */
/*! @{ */

#define CSS_CSS_STATUS_css_busy_MASK             (0x1U)
#define CSS_CSS_STATUS_css_busy_SHIFT            (0U)
/*! css_busy - High to indicate the CSS is executing a Crypto Sequence
 */
#define CSS_CSS_STATUS_css_busy(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_STATUS_css_busy_SHIFT)) & CSS_CSS_STATUS_css_busy_MASK)

#define CSS_CSS_STATUS_css_irq_MASK              (0x2U)
#define CSS_CSS_STATUS_css_irq_SHIFT             (1U)
/*! css_irq - High to indicate the CSS has an active interrupt
 */
#define CSS_CSS_STATUS_css_irq(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_STATUS_css_irq_SHIFT)) & CSS_CSS_STATUS_css_irq_MASK)

#define CSS_CSS_STATUS_css_err_MASK              (0x4U)
#define CSS_CSS_STATUS_css_err_SHIFT             (2U)
/*! css_err - High to indicate the CSS has detected an internal error
 */
#define CSS_CSS_STATUS_css_err(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_STATUS_css_err_SHIFT)) & CSS_CSS_STATUS_css_err_MASK)

#define CSS_CSS_STATUS_prng_rdy_MASK             (0x8U)
#define CSS_CSS_STATUS_prng_rdy_SHIFT            (3U)
/*! prng_rdy - High to indicate the internal PRNG is ready. SFR
 */
#define CSS_CSS_STATUS_prng_rdy(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_STATUS_prng_rdy_SHIFT)) & CSS_CSS_STATUS_prng_rdy_MASK)

#define CSS_CSS_STATUS_ecdsa_vfy_status_MASK     (0x30U)
#define CSS_CSS_STATUS_ecdsa_vfy_status_SHIFT    (4U)
/*! ecdsa_vfy_status - Signature Verify Result Status
 */
#define CSS_CSS_STATUS_ecdsa_vfy_status(x)       (((uint32_t)(((uint32_t)(x)) << CSS_CSS_STATUS_ecdsa_vfy_status_SHIFT)) & CSS_CSS_STATUS_ecdsa_vfy_status_MASK)

#define CSS_CSS_STATUS_pprot_MASK                (0xC0U)
#define CSS_CSS_STATUS_pprot_SHIFT               (6U)
/*! pprot - Current command privilege level
 */
#define CSS_CSS_STATUS_pprot(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_STATUS_pprot_SHIFT)) & CSS_CSS_STATUS_pprot_MASK)

#define CSS_CSS_STATUS_drbg_ent_lvl_MASK         (0x300U)
#define CSS_CSS_STATUS_drbg_ent_lvl_SHIFT        (8U)
/*! drbg_ent_lvl - Entropy quality of the current DRBG instance. This value
 */
#define CSS_CSS_STATUS_drbg_ent_lvl(x)           (((uint32_t)(((uint32_t)(x)) << CSS_CSS_STATUS_drbg_ent_lvl_SHIFT)) & CSS_CSS_STATUS_drbg_ent_lvl_MASK)

#define CSS_CSS_STATUS_dtrng_busy_MASK           (0x400U)
#define CSS_CSS_STATUS_dtrng_busy_SHIFT          (10U)
/*! dtrng_busy - When set, it indicates the DTRNG is gathering entropy
 */
#define CSS_CSS_STATUS_dtrng_busy(x)             (((uint32_t)(((uint32_t)(x)) << CSS_CSS_STATUS_dtrng_busy_SHIFT)) & CSS_CSS_STATUS_dtrng_busy_MASK)

#define CSS_CSS_STATUS_gdet_irq_pos_MASK         (0x800U)
#define CSS_CSS_STATUS_gdet_irq_pos_SHIFT        (11U)
/*! gdet_irq_pos - IRQ for GDET has detected a negative glitch: active high irq
 */
#define CSS_CSS_STATUS_gdet_irq_pos(x)           (((uint32_t)(((uint32_t)(x)) << CSS_CSS_STATUS_gdet_irq_pos_SHIFT)) & CSS_CSS_STATUS_gdet_irq_pos_MASK)

#define CSS_CSS_STATUS_gdet_irq_neg_MASK         (0x1000U)
#define CSS_CSS_STATUS_gdet_irq_neg_SHIFT        (12U)
/*! gdet_irq_neg - IRQ for GDET has detected a positive glitch: active high irq
 */
#define CSS_CSS_STATUS_gdet_irq_neg(x)           (((uint32_t)(((uint32_t)(x)) << CSS_CSS_STATUS_gdet_irq_neg_SHIFT)) & CSS_CSS_STATUS_gdet_irq_neg_MASK)

#define CSS_CSS_STATUS_status_rsvd_MASK          (0xFFFFE000U)
#define CSS_CSS_STATUS_status_rsvd_SHIFT         (13U)
/*! status_rsvd - reserved
 */
#define CSS_CSS_STATUS_status_rsvd(x)            (((uint32_t)(((uint32_t)(x)) << CSS_CSS_STATUS_status_rsvd_SHIFT)) & CSS_CSS_STATUS_status_rsvd_MASK)
/*! @} */

/*! @name CSS_CTRL - CSS Control register */
/*! @{ */

#define CSS_CSS_CTRL_css_en_MASK                 (0x1U)
#define CSS_CSS_CTRL_css_en_SHIFT                (0U)
/*! css_en - CSS enable 0=CSS disabled, 1= CSS is enabled
 */
#define CSS_CSS_CTRL_css_en(x)                   (((uint32_t)(((uint32_t)(x)) << CSS_CSS_CTRL_css_en_SHIFT)) & CSS_CSS_CTRL_css_en_MASK)

#define CSS_CSS_CTRL_css_start_MASK              (0x2U)
#define CSS_CSS_CTRL_css_start_SHIFT             (1U)
/*! css_start - Write to 1 to start a CSS Operation
 */
#define CSS_CSS_CTRL_css_start(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_CTRL_css_start_SHIFT)) & CSS_CSS_CTRL_css_start_MASK)

#define CSS_CSS_CTRL_css_reset_MASK              (0x4U)
#define CSS_CSS_CTRL_css_reset_SHIFT             (2U)
/*! css_reset - Write to 1 to perform a CSS synchronous Reset
 */
#define CSS_CSS_CTRL_css_reset(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_CTRL_css_reset_SHIFT)) & CSS_CSS_CTRL_css_reset_MASK)

#define CSS_CSS_CTRL_css_cmd_MASK                (0xF8U)
#define CSS_CSS_CTRL_css_cmd_SHIFT               (3U)
/*! css_cmd - CSS Command Field: List of Valid commands:
 */
#define CSS_CSS_CTRL_css_cmd(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_CTRL_css_cmd_SHIFT)) & CSS_CSS_CTRL_css_cmd_MASK)

#define CSS_CSS_CTRL_byte_order_MASK             (0x100U)
#define CSS_CSS_CTRL_byte_order_SHIFT            (8U)
/*! byte_order - Defines Endianness - 1: BigEndian, 0: Little Endian
 */
#define CSS_CSS_CTRL_byte_order(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_CTRL_byte_order_SHIFT)) & CSS_CSS_CTRL_byte_order_MASK)

#define CSS_CSS_CTRL_ctrl_rfu_MASK               (0xFFFFFE00U)
#define CSS_CSS_CTRL_ctrl_rfu_SHIFT              (9U)
/*! ctrl_rfu - reserved
 */
#define CSS_CSS_CTRL_ctrl_rfu(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_CTRL_ctrl_rfu_SHIFT)) & CSS_CSS_CTRL_ctrl_rfu_MASK)
/*! @} */

/*! @name CSS_CMDCFG0 - CSS command configuration register */
/*! @{ */

#define CSS_CSS_CMDCFG0_cmdcfg0_MASK             (0xFFFFFFFFU)
#define CSS_CSS_CMDCFG0_cmdcfg0_SHIFT            (0U)
/*! cmdcfg0 - refer to reference manual for assignment of this field
 */
#define CSS_CSS_CMDCFG0_cmdcfg0(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_CMDCFG0_cmdcfg0_SHIFT)) & CSS_CSS_CMDCFG0_cmdcfg0_MASK)
/*! @} */

/*! @name CSS_CFG - CSS configuration register */
/*! @{ */

#define CSS_CSS_CFG_cfg_rsvd0_MASK               (0xFFFFU)
#define CSS_CSS_CFG_cfg_rsvd0_SHIFT              (0U)
/*! cfg_rsvd0 - reserved
 */
#define CSS_CSS_CFG_cfg_rsvd0(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_CFG_cfg_rsvd0_SHIFT)) & CSS_CSS_CFG_cfg_rsvd0_MASK)

#define CSS_CSS_CFG_adctrl_MASK                  (0x3FF0000U)
#define CSS_CSS_CFG_adctrl_SHIFT                 (16U)
/*! adctrl - maximum aes start delay
 */
#define CSS_CSS_CFG_adctrl(x)                    (((uint32_t)(((uint32_t)(x)) << CSS_CSS_CFG_adctrl_SHIFT)) & CSS_CSS_CFG_adctrl_MASK)

#define CSS_CSS_CFG_cfg_rsvd1_MASK               (0x7C000000U)
#define CSS_CSS_CFG_cfg_rsvd1_SHIFT              (26U)
/*! cfg_rsvd1 - reserved
 */
#define CSS_CSS_CFG_cfg_rsvd1(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_CFG_cfg_rsvd1_SHIFT)) & CSS_CSS_CFG_cfg_rsvd1_MASK)

#define CSS_CSS_CFG_sha2_direct_MASK             (0x80000000U)
#define CSS_CSS_CFG_sha2_direct_SHIFT            (31U)
/*! sha2_direct - 1=enable sha2 direct mode: direct access from external
 */
#define CSS_CSS_CFG_sha2_direct(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_CFG_sha2_direct_SHIFT)) & CSS_CSS_CFG_sha2_direct_MASK)
/*! @} */

/*! @name CSS_KIDX0 - Keystore index 0 - for commands that access a single key */
/*! @{ */

#define CSS_CSS_KIDX0_kidx0_MASK                 (0x7FU)
#define CSS_CSS_KIDX0_kidx0_SHIFT                (0U)
/*! kidx0 - keystore is indexed as an array of 128 bit key slots
 */
#define CSS_CSS_KIDX0_kidx0(x)                   (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KIDX0_kidx0_SHIFT)) & CSS_CSS_KIDX0_kidx0_MASK)

#define CSS_CSS_KIDX0_kidx0_rsvd_MASK            (0xFFFFFF80U)
#define CSS_CSS_KIDX0_kidx0_rsvd_SHIFT           (7U)
/*! kidx0_rsvd - reserved
 */
#define CSS_CSS_KIDX0_kidx0_rsvd(x)              (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KIDX0_kidx0_rsvd_SHIFT)) & CSS_CSS_KIDX0_kidx0_rsvd_MASK)
/*! @} */

/*! @name CSS_KIDX1 - Keystore index 1 - for commands that access 2 keys */
/*! @{ */

#define CSS_CSS_KIDX1_kidx1_MASK                 (0x7FU)
#define CSS_CSS_KIDX1_kidx1_SHIFT                (0U)
/*! kidx1 - keystore is indexed as an array of 128 bit key slots
 */
#define CSS_CSS_KIDX1_kidx1(x)                   (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KIDX1_kidx1_SHIFT)) & CSS_CSS_KIDX1_kidx1_MASK)

#define CSS_CSS_KIDX1_kidx1_rsvd_MASK            (0xFFFFFF80U)
#define CSS_CSS_KIDX1_kidx1_rsvd_SHIFT           (7U)
/*! kidx1_rsvd - reserved
 */
#define CSS_CSS_KIDX1_kidx1_rsvd(x)              (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KIDX1_kidx1_rsvd_SHIFT)) & CSS_CSS_KIDX1_kidx1_rsvd_MASK)
/*! @} */

/*! @name CSS_KPROPIN - key properties request */
/*! @{ */

#define CSS_CSS_KPROPIN_kpropin_MASK             (0xFFFFFFFFU)
#define CSS_CSS_KPROPIN_kpropin_SHIFT            (0U)
/*! kpropin - for commands that create a key - requested properties
 */
#define CSS_CSS_KPROPIN_kpropin(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KPROPIN_kpropin_SHIFT)) & CSS_CSS_KPROPIN_kpropin_MASK)
/*! @} */

/*! @name CSS_DMA_SRC0 - CSS DMA Source 0 */
/*! @{ */

#define CSS_CSS_DMA_SRC0_addr_src0_MASK          (0xFFFFFFFFU)
#define CSS_CSS_DMA_SRC0_addr_src0_SHIFT         (0U)
/*! addr_src0 - defines the System address of the start of the
 */
#define CSS_CSS_DMA_SRC0_addr_src0(x)            (((uint32_t)(((uint32_t)(x)) << CSS_CSS_DMA_SRC0_addr_src0_SHIFT)) & CSS_CSS_DMA_SRC0_addr_src0_MASK)
/*! @} */

/*! @name CSS_DMA_SRC0_LEN - CSS DMA Source 0 length */
/*! @{ */

#define CSS_CSS_DMA_SRC0_LEN_size_src0_len_MASK  (0xFFFFFFFFU)
#define CSS_CSS_DMA_SRC0_LEN_size_src0_len_SHIFT (0U)
/*! size_src0_len - Size in bytes of the data to be transferred from
 */
#define CSS_CSS_DMA_SRC0_LEN_size_src0_len(x)    (((uint32_t)(((uint32_t)(x)) << CSS_CSS_DMA_SRC0_LEN_size_src0_len_SHIFT)) & CSS_CSS_DMA_SRC0_LEN_size_src0_len_MASK)
/*! @} */

/*! @name CSS_DMA_SRC1 - CSS DMA Source 1 */
/*! @{ */

#define CSS_CSS_DMA_SRC1_addr_src1_MASK          (0xFFFFFFFFU)
#define CSS_CSS_DMA_SRC1_addr_src1_SHIFT         (0U)
/*! addr_src1 - defines the System address of the start of the
 */
#define CSS_CSS_DMA_SRC1_addr_src1(x)            (((uint32_t)(((uint32_t)(x)) << CSS_CSS_DMA_SRC1_addr_src1_SHIFT)) & CSS_CSS_DMA_SRC1_addr_src1_MASK)
/*! @} */

/*! @name CSS_DMA_SRC2 - CSS DMA Source 2 */
/*! @{ */

#define CSS_CSS_DMA_SRC2_addr_src2_MASK          (0xFFFFFFFFU)
#define CSS_CSS_DMA_SRC2_addr_src2_SHIFT         (0U)
/*! addr_src2 - defines the System address of the start of the
 */
#define CSS_CSS_DMA_SRC2_addr_src2(x)            (((uint32_t)(((uint32_t)(x)) << CSS_CSS_DMA_SRC2_addr_src2_SHIFT)) & CSS_CSS_DMA_SRC2_addr_src2_MASK)
/*! @} */

/*! @name CSS_DMA_SRC2_LEN - CSS DMA Source 2 length */
/*! @{ */

#define CSS_CSS_DMA_SRC2_LEN_size_src2_len_MASK  (0xFFFFFFFFU)
#define CSS_CSS_DMA_SRC2_LEN_size_src2_len_SHIFT (0U)
/*! size_src2_len - Size in bytes of the data to be transferred from
 */
#define CSS_CSS_DMA_SRC2_LEN_size_src2_len(x)    (((uint32_t)(((uint32_t)(x)) << CSS_CSS_DMA_SRC2_LEN_size_src2_len_SHIFT)) & CSS_CSS_DMA_SRC2_LEN_size_src2_len_MASK)
/*! @} */

/*! @name CSS_DMA_RES0 - CSS DMA Result 0 */
/*! @{ */

#define CSS_CSS_DMA_RES0_addr_res0_MASK          (0xFFFFFFFFU)
#define CSS_CSS_DMA_RES0_addr_res0_SHIFT         (0U)
/*! addr_res0 - defines the System Start address of where the result
 */
#define CSS_CSS_DMA_RES0_addr_res0(x)            (((uint32_t)(((uint32_t)(x)) << CSS_CSS_DMA_RES0_addr_res0_SHIFT)) & CSS_CSS_DMA_RES0_addr_res0_MASK)
/*! @} */

/*! @name CSS_DMA_RES0_LEN - CSS DMA Result 0 Size */
/*! @{ */

#define CSS_CSS_DMA_RES0_LEN_size_res0_len_MASK  (0xFFFFFFFFU)
#define CSS_CSS_DMA_RES0_LEN_size_res0_len_SHIFT (0U)
/*! size_res0_len - Size in bytes of the data to be transferred to
 */
#define CSS_CSS_DMA_RES0_LEN_size_res0_len(x)    (((uint32_t)(((uint32_t)(x)) << CSS_CSS_DMA_RES0_LEN_size_res0_len_SHIFT)) & CSS_CSS_DMA_RES0_LEN_size_res0_len_MASK)
/*! @} */

/*! @name CSS_INT_ENABLE - Interrupt enable */
/*! @{ */

#define CSS_CSS_INT_ENABLE_int_en_MASK           (0x1U)
#define CSS_CSS_INT_ENABLE_int_en_SHIFT          (0U)
/*! int_en - Interrupt enable bit
 */
#define CSS_CSS_INT_ENABLE_int_en(x)             (((uint32_t)(((uint32_t)(x)) << CSS_CSS_INT_ENABLE_int_en_SHIFT)) & CSS_CSS_INT_ENABLE_int_en_MASK)

#define CSS_CSS_INT_ENABLE_gdet_int_en_MASK      (0x2U)
#define CSS_CSS_INT_ENABLE_gdet_int_en_SHIFT     (1U)
/*! gdet_int_en - GDET Interrupt enable bit
 */
#define CSS_CSS_INT_ENABLE_gdet_int_en(x)        (((uint32_t)(((uint32_t)(x)) << CSS_CSS_INT_ENABLE_gdet_int_en_SHIFT)) & CSS_CSS_INT_ENABLE_gdet_int_en_MASK)

#define CSS_CSS_INT_ENABLE_int_ena_rsvd_MASK     (0xFFFFFFFCU)
#define CSS_CSS_INT_ENABLE_int_ena_rsvd_SHIFT    (2U)
/*! int_ena_rsvd - reserved
 */
#define CSS_CSS_INT_ENABLE_int_ena_rsvd(x)       (((uint32_t)(((uint32_t)(x)) << CSS_CSS_INT_ENABLE_int_ena_rsvd_SHIFT)) & CSS_CSS_INT_ENABLE_int_ena_rsvd_MASK)
/*! @} */

/*! @name CSS_INT_STATUS_CLR - Interrupt status clear */
/*! @{ */

#define CSS_CSS_INT_STATUS_CLR_int_clr_MASK      (0x1U)
#define CSS_CSS_INT_STATUS_CLR_int_clr_SHIFT     (0U)
/*! int_clr - Interrupt status clear
 */
#define CSS_CSS_INT_STATUS_CLR_int_clr(x)        (((uint32_t)(((uint32_t)(x)) << CSS_CSS_INT_STATUS_CLR_int_clr_SHIFT)) & CSS_CSS_INT_STATUS_CLR_int_clr_MASK)

#define CSS_CSS_INT_STATUS_CLR_gdet_int_clr_MASK (0x2U)
#define CSS_CSS_INT_STATUS_CLR_gdet_int_clr_SHIFT (1U)
/*! gdet_int_clr - GDET Interrupt status clear
 */
#define CSS_CSS_INT_STATUS_CLR_gdet_int_clr(x)   (((uint32_t)(((uint32_t)(x)) << CSS_CSS_INT_STATUS_CLR_gdet_int_clr_SHIFT)) & CSS_CSS_INT_STATUS_CLR_gdet_int_clr_MASK)

#define CSS_CSS_INT_STATUS_CLR_int_stsc_rsvd_MASK (0xFFFFFFFCU)
#define CSS_CSS_INT_STATUS_CLR_int_stsc_rsvd_SHIFT (2U)
/*! int_stsc_rsvd - reserved
 */
#define CSS_CSS_INT_STATUS_CLR_int_stsc_rsvd(x)  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_INT_STATUS_CLR_int_stsc_rsvd_SHIFT)) & CSS_CSS_INT_STATUS_CLR_int_stsc_rsvd_MASK)
/*! @} */

/*! @name CSS_INT_STATUS_SET - Interrupt status set */
/*! @{ */

#define CSS_CSS_INT_STATUS_SET_int_set_MASK      (0x1U)
#define CSS_CSS_INT_STATUS_SET_int_set_SHIFT     (0U)
/*! int_set - Set interrupt by software
 */
#define CSS_CSS_INT_STATUS_SET_int_set(x)        (((uint32_t)(((uint32_t)(x)) << CSS_CSS_INT_STATUS_SET_int_set_SHIFT)) & CSS_CSS_INT_STATUS_SET_int_set_MASK)

#define CSS_CSS_INT_STATUS_SET_gdet_int_neg_set_MASK (0x2U)
#define CSS_CSS_INT_STATUS_SET_gdet_int_neg_set_SHIFT (1U)
/*! gdet_int_neg_set - Set GDET interrupt by software
 */
#define CSS_CSS_INT_STATUS_SET_gdet_int_neg_set(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_INT_STATUS_SET_gdet_int_neg_set_SHIFT)) & CSS_CSS_INT_STATUS_SET_gdet_int_neg_set_MASK)

#define CSS_CSS_INT_STATUS_SET_gdet_int_pos_set_MASK (0x4U)
#define CSS_CSS_INT_STATUS_SET_gdet_int_pos_set_SHIFT (2U)
/*! gdet_int_pos_set - Set GDET interrupt by software
 */
#define CSS_CSS_INT_STATUS_SET_gdet_int_pos_set(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_INT_STATUS_SET_gdet_int_pos_set_SHIFT)) & CSS_CSS_INT_STATUS_SET_gdet_int_pos_set_MASK)

#define CSS_CSS_INT_STATUS_SET_int_stss_rsvd_MASK (0xFFFFFFF8U)
#define CSS_CSS_INT_STATUS_SET_int_stss_rsvd_SHIFT (3U)
/*! int_stss_rsvd - reserved
 */
#define CSS_CSS_INT_STATUS_SET_int_stss_rsvd(x)  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_INT_STATUS_SET_int_stss_rsvd_SHIFT)) & CSS_CSS_INT_STATUS_SET_int_stss_rsvd_MASK)
/*! @} */

/*! @name CSS_ERR_STATUS - Status register */
/*! @{ */

#define CSS_CSS_ERR_STATUS_bus_err_MASK          (0x1U)
#define CSS_CSS_ERR_STATUS_bus_err_SHIFT         (0U)
/*! bus_err - Bus access error: public or private bus
 */
#define CSS_CSS_ERR_STATUS_bus_err(x)            (((uint32_t)(((uint32_t)(x)) << CSS_CSS_ERR_STATUS_bus_err_SHIFT)) & CSS_CSS_ERR_STATUS_bus_err_MASK)

#define CSS_CSS_ERR_STATUS_opn_err_MASK          (0x2U)
#define CSS_CSS_ERR_STATUS_opn_err_SHIFT         (1U)
/*! opn_err - Operational error:
 */
#define CSS_CSS_ERR_STATUS_opn_err(x)            (((uint32_t)(((uint32_t)(x)) << CSS_CSS_ERR_STATUS_opn_err_SHIFT)) & CSS_CSS_ERR_STATUS_opn_err_MASK)

#define CSS_CSS_ERR_STATUS_alg_err_MASK          (0x4U)
#define CSS_CSS_ERR_STATUS_alg_err_SHIFT         (2U)
/*! alg_err - Algorithm error: An internal algorithm has
 */
#define CSS_CSS_ERR_STATUS_alg_err(x)            (((uint32_t)(((uint32_t)(x)) << CSS_CSS_ERR_STATUS_alg_err_SHIFT)) & CSS_CSS_ERR_STATUS_alg_err_MASK)

#define CSS_CSS_ERR_STATUS_itg_err_MASK          (0x8U)
#define CSS_CSS_ERR_STATUS_itg_err_SHIFT         (3U)
/*! itg_err - Data integrity error:
 */
#define CSS_CSS_ERR_STATUS_itg_err(x)            (((uint32_t)(((uint32_t)(x)) << CSS_CSS_ERR_STATUS_itg_err_SHIFT)) & CSS_CSS_ERR_STATUS_itg_err_MASK)

#define CSS_CSS_ERR_STATUS_flt_err_MASK          (0x10U)
#define CSS_CSS_ERR_STATUS_flt_err_SHIFT         (4U)
/*! flt_err - Hardware fault error: Attempt to change the value
 */
#define CSS_CSS_ERR_STATUS_flt_err(x)            (((uint32_t)(((uint32_t)(x)) << CSS_CSS_ERR_STATUS_flt_err_SHIFT)) & CSS_CSS_ERR_STATUS_flt_err_MASK)

#define CSS_CSS_ERR_STATUS_prng_err_MASK         (0x20U)
#define CSS_CSS_ERR_STATUS_prng_err_SHIFT        (5U)
/*! prng_err - User Read of CSS_PRNG_DATOUT when CSS_STATUS.PRNG_RDY
 */
#define CSS_CSS_ERR_STATUS_prng_err(x)           (((uint32_t)(((uint32_t)(x)) << CSS_CSS_ERR_STATUS_prng_err_SHIFT)) & CSS_CSS_ERR_STATUS_prng_err_MASK)

#define CSS_CSS_ERR_STATUS_err_lvl_MASK          (0xC0U)
#define CSS_CSS_ERR_STATUS_err_lvl_SHIFT         (6U)
/*! err_lvl - Indicates Error Level which has been triggerer. 0, 1 ,2
 */
#define CSS_CSS_ERR_STATUS_err_lvl(x)            (((uint32_t)(((uint32_t)(x)) << CSS_CSS_ERR_STATUS_err_lvl_SHIFT)) & CSS_CSS_ERR_STATUS_err_lvl_MASK)

#define CSS_CSS_ERR_STATUS_dtrng_err_MASK        (0x100U)
#define CSS_CSS_ERR_STATUS_dtrng_err_SHIFT       (8U)
/*! dtrng_err - DTRNG unable to gather entropy with the current
 */
#define CSS_CSS_ERR_STATUS_dtrng_err(x)          (((uint32_t)(((uint32_t)(x)) << CSS_CSS_ERR_STATUS_dtrng_err_SHIFT)) & CSS_CSS_ERR_STATUS_dtrng_err_MASK)

#define CSS_CSS_ERR_STATUS_err_stat_rsvd_MASK    (0xFFFFFE00U)
#define CSS_CSS_ERR_STATUS_err_stat_rsvd_SHIFT   (9U)
/*! err_stat_rsvd - reserved
 */
#define CSS_CSS_ERR_STATUS_err_stat_rsvd(x)      (((uint32_t)(((uint32_t)(x)) << CSS_CSS_ERR_STATUS_err_stat_rsvd_SHIFT)) & CSS_CSS_ERR_STATUS_err_stat_rsvd_MASK)
/*! @} */

/*! @name CSS_ERR_STATUS_CLR - Interrupt status clear */
/*! @{ */

#define CSS_CSS_ERR_STATUS_CLR_err_clr_MASK      (0x1U)
#define CSS_CSS_ERR_STATUS_CLR_err_clr_SHIFT     (0U)
/*! err_clr - 1=clear CSS error status bits and exit CSS error state
 */
#define CSS_CSS_ERR_STATUS_CLR_err_clr(x)        (((uint32_t)(((uint32_t)(x)) << CSS_CSS_ERR_STATUS_CLR_err_clr_SHIFT)) & CSS_CSS_ERR_STATUS_CLR_err_clr_MASK)

#define CSS_CSS_ERR_STATUS_CLR_err_stsc_rsvd_MASK (0xFFFFFFFEU)
#define CSS_CSS_ERR_STATUS_CLR_err_stsc_rsvd_SHIFT (1U)
/*! err_stsc_rsvd - reserved
 */
#define CSS_CSS_ERR_STATUS_CLR_err_stsc_rsvd(x)  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_ERR_STATUS_CLR_err_stsc_rsvd_SHIFT)) & CSS_CSS_ERR_STATUS_CLR_err_stsc_rsvd_MASK)
/*! @} */

/*! @name CSS_VERSION - CSS Version */
/*! @{ */

#define CSS_CSS_VERSION_z_MASK                   (0xFU)
#define CSS_CSS_VERSION_z_SHIFT                  (0U)
/*! z - extended revision version: possible values 0-9
 */
#define CSS_CSS_VERSION_z(x)                     (((uint32_t)(((uint32_t)(x)) << CSS_CSS_VERSION_z_SHIFT)) & CSS_CSS_VERSION_z_MASK)

#define CSS_CSS_VERSION_y2_MASK                  (0xF0U)
#define CSS_CSS_VERSION_y2_SHIFT                 (4U)
/*! y2 - minor release versino digit0: possible values 0-9
 */
#define CSS_CSS_VERSION_y2(x)                    (((uint32_t)(((uint32_t)(x)) << CSS_CSS_VERSION_y2_SHIFT)) & CSS_CSS_VERSION_y2_MASK)

#define CSS_CSS_VERSION_y1_MASK                  (0xF00U)
#define CSS_CSS_VERSION_y1_SHIFT                 (8U)
/*! y1 - minor release version digit1: possible values 0-9
 */
#define CSS_CSS_VERSION_y1(x)                    (((uint32_t)(((uint32_t)(x)) << CSS_CSS_VERSION_y1_SHIFT)) & CSS_CSS_VERSION_y1_MASK)

#define CSS_CSS_VERSION_x_MASK                   (0xF000U)
#define CSS_CSS_VERSION_x_SHIFT                  (12U)
/*! x - major release version: possible values 1-9
 */
#define CSS_CSS_VERSION_x(x)                     (((uint32_t)(((uint32_t)(x)) << CSS_CSS_VERSION_x_SHIFT)) & CSS_CSS_VERSION_x_MASK)

#define CSS_CSS_VERSION_version_rsvd_MASK        (0xFFFF0000U)
#define CSS_CSS_VERSION_version_rsvd_SHIFT       (16U)
/*! version_rsvd - reserved
 */
#define CSS_CSS_VERSION_version_rsvd(x)          (((uint32_t)(((uint32_t)(x)) << CSS_CSS_VERSION_version_rsvd_SHIFT)) & CSS_CSS_VERSION_version_rsvd_MASK)
/*! @} */

/*! @name CSS_PRNG_DATOUT - PRNG SW read out register */
/*! @{ */

#define CSS_CSS_PRNG_DATOUT_prng_datout_MASK     (0xFFFFFFFFU)
#define CSS_CSS_PRNG_DATOUT_prng_datout_SHIFT    (0U)
/*! prng_datout - 32-bit wide pseudo-random number
 */
#define CSS_CSS_PRNG_DATOUT_prng_datout(x)       (((uint32_t)(((uint32_t)(x)) << CSS_CSS_PRNG_DATOUT_prng_datout_SHIFT)) & CSS_CSS_PRNG_DATOUT_prng_datout_MASK)
/*! @} */

/*! @name CSS_GDET_EVTCNT - CSS GDET Event Counter */
/*! @{ */

#define CSS_CSS_GDET_EVTCNT_gdet_evtcnt_MASK     (0xFFU)
#define CSS_CSS_GDET_EVTCNT_gdet_evtcnt_SHIFT    (0U)
/*! gdet_evtcnt - Number of glitch event recorded
 */
#define CSS_CSS_GDET_EVTCNT_gdet_evtcnt(x)       (((uint32_t)(((uint32_t)(x)) << CSS_CSS_GDET_EVTCNT_gdet_evtcnt_SHIFT)) & CSS_CSS_GDET_EVTCNT_gdet_evtcnt_MASK)

#define CSS_CSS_GDET_EVTCNT_gdet_evtcnt_clr_done_MASK (0x100U)
#define CSS_CSS_GDET_EVTCNT_gdet_evtcnt_clr_done_SHIFT (8U)
/*! gdet_evtcnt_clr_done - The GDET event counter has been cleared
 */
#define CSS_CSS_GDET_EVTCNT_gdet_evtcnt_clr_done(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_GDET_EVTCNT_gdet_evtcnt_clr_done_SHIFT)) & CSS_CSS_GDET_EVTCNT_gdet_evtcnt_clr_done_MASK)

#define CSS_CSS_GDET_EVTCNT_gdet_evtcnt_rsvd_MASK (0xFFFFFE00U)
#define CSS_CSS_GDET_EVTCNT_gdet_evtcnt_rsvd_SHIFT (9U)
/*! gdet_evtcnt_rsvd - reserved
 */
#define CSS_CSS_GDET_EVTCNT_gdet_evtcnt_rsvd(x)  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_GDET_EVTCNT_gdet_evtcnt_rsvd_SHIFT)) & CSS_CSS_GDET_EVTCNT_gdet_evtcnt_rsvd_MASK)
/*! @} */

/*! @name CSS_GDET_EVTCNT_CLR - CSS GDET Event Counter Clear */
/*! @{ */

#define CSS_CSS_GDET_EVTCNT_CLR_gdet_evtcnt_clr_MASK (0x1U)
#define CSS_CSS_GDET_EVTCNT_CLR_gdet_evtcnt_clr_SHIFT (0U)
/*! gdet_evtcnt_clr - 1=clear GDET event counter clear
 */
#define CSS_CSS_GDET_EVTCNT_CLR_gdet_evtcnt_clr(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_GDET_EVTCNT_CLR_gdet_evtcnt_clr_SHIFT)) & CSS_CSS_GDET_EVTCNT_CLR_gdet_evtcnt_clr_MASK)

#define CSS_CSS_GDET_EVTCNT_CLR_gdet_evtcnt_clr_rsvd_MASK (0xFFFFFFFEU)
#define CSS_CSS_GDET_EVTCNT_CLR_gdet_evtcnt_clr_rsvd_SHIFT (1U)
/*! gdet_evtcnt_clr_rsvd - reserved
 */
#define CSS_CSS_GDET_EVTCNT_CLR_gdet_evtcnt_clr_rsvd(x) (((uint32_t)(((uint32_t)(x)) << CSS_CSS_GDET_EVTCNT_CLR_gdet_evtcnt_clr_rsvd_SHIFT)) & CSS_CSS_GDET_EVTCNT_CLR_gdet_evtcnt_clr_rsvd_MASK)
/*! @} */

/*! @name CSS_SHA2_STATUS - CSS SHA2 Status Register */
/*! @{ */

#define CSS_CSS_SHA2_STATUS_sha2_busy_MASK       (0x1U)
#define CSS_CSS_SHA2_STATUS_sha2_busy_SHIFT      (0U)
/*! sha2_busy - SHA2 busy/idle status for sha direct
 */
#define CSS_CSS_SHA2_STATUS_sha2_busy(x)         (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_STATUS_sha2_busy_SHIFT)) & CSS_CSS_SHA2_STATUS_sha2_busy_MASK)

#define CSS_CSS_SHA2_STATUS_status_rsvd1_MASK    (0xFFFFFFFEU)
#define CSS_CSS_SHA2_STATUS_status_rsvd1_SHIFT   (1U)
/*! status_rsvd1 - reserved
 */
#define CSS_CSS_SHA2_STATUS_status_rsvd1(x)      (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_STATUS_status_rsvd1_SHIFT)) & CSS_CSS_SHA2_STATUS_status_rsvd1_MASK)
/*! @} */

/*! @name CSS_SHA2_CTRL - SHA2 Control register */
/*! @{ */

#define CSS_CSS_SHA2_CTRL_sha2_start_MASK        (0x1U)
#define CSS_CSS_SHA2_CTRL_sha2_start_SHIFT       (0U)
/*! sha2_start - Write to 1 to Init the SHA2 Module
 */
#define CSS_CSS_SHA2_CTRL_sha2_start(x)          (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_CTRL_sha2_start_SHIFT)) & CSS_CSS_SHA2_CTRL_sha2_start_MASK)

#define CSS_CSS_SHA2_CTRL_sha2_rst_MASK          (0x2U)
#define CSS_CSS_SHA2_CTRL_sha2_rst_SHIFT         (1U)
/*! sha2_rst - Write to 1 to Reset a SHA2 operation
 */
#define CSS_CSS_SHA2_CTRL_sha2_rst(x)            (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_CTRL_sha2_rst_SHIFT)) & CSS_CSS_SHA2_CTRL_sha2_rst_MASK)

#define CSS_CSS_SHA2_CTRL_sha2_init_MASK         (0x4U)
#define CSS_CSS_SHA2_CTRL_sha2_init_SHIFT        (2U)
/*! sha2_init - Write to 1 to Init the SHA2 Kernel
 */
#define CSS_CSS_SHA2_CTRL_sha2_init(x)           (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_CTRL_sha2_init_SHIFT)) & CSS_CSS_SHA2_CTRL_sha2_init_MASK)

#define CSS_CSS_SHA2_CTRL_sha2_load_MASK         (0x8U)
#define CSS_CSS_SHA2_CTRL_sha2_load_SHIFT        (3U)
/*! sha2_load - Write to 1 to Load the SHA2 Kernel
 */
#define CSS_CSS_SHA2_CTRL_sha2_load(x)           (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_CTRL_sha2_load_SHIFT)) & CSS_CSS_SHA2_CTRL_sha2_load_MASK)

#define CSS_CSS_SHA2_CTRL_sha2_mode_MASK         (0x30U)
#define CSS_CSS_SHA2_CTRL_sha2_mode_SHIFT        (4U)
/*! sha2_mode - SHA2 MODE:
 */
#define CSS_CSS_SHA2_CTRL_sha2_mode(x)           (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_CTRL_sha2_mode_SHIFT)) & CSS_CSS_SHA2_CTRL_sha2_mode_MASK)

#define CSS_CSS_SHA2_CTRL_ctrl_rsvd1_MASK        (0x1C0U)
#define CSS_CSS_SHA2_CTRL_ctrl_rsvd1_SHIFT       (6U)
/*! ctrl_rsvd1 - r-eserved
 */
#define CSS_CSS_SHA2_CTRL_ctrl_rsvd1(x)          (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_CTRL_ctrl_rsvd1_SHIFT)) & CSS_CSS_SHA2_CTRL_ctrl_rsvd1_MASK)

#define CSS_CSS_SHA2_CTRL_sha2_byte_order_MASK   (0x200U)
#define CSS_CSS_SHA2_CTRL_sha2_byte_order_SHIFT  (9U)
/*! sha2_byte_order - Write to 1 to Reverse byte endianess
 */
#define CSS_CSS_SHA2_CTRL_sha2_byte_order(x)     (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_CTRL_sha2_byte_order_SHIFT)) & CSS_CSS_SHA2_CTRL_sha2_byte_order_MASK)

#define CSS_CSS_SHA2_CTRL_ctrl_rsvd_MASK         (0xFFFFFC00U)
#define CSS_CSS_SHA2_CTRL_ctrl_rsvd_SHIFT        (10U)
/*! ctrl_rsvd - r-eserved
 */
#define CSS_CSS_SHA2_CTRL_ctrl_rsvd(x)           (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_CTRL_ctrl_rsvd_SHIFT)) & CSS_CSS_SHA2_CTRL_ctrl_rsvd_MASK)
/*! @} */

/*! @name CSS_SHA2_DIN - CSS SHA_DATA IN Register 0 */
/*! @{ */

#define CSS_CSS_SHA2_DIN_sha_datin_MASK          (0xFFFFFFFFU)
#define CSS_CSS_SHA2_DIN_sha_datin_SHIFT         (0U)
/*! sha_datin - Output CSS_SHA_DATIN from CSS Application being executed
 */
#define CSS_CSS_SHA2_DIN_sha_datin(x)            (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_DIN_sha_datin_SHIFT)) & CSS_CSS_SHA2_DIN_sha_datin_MASK)
/*! @} */

/*! @name CSS_SHA2_DOUT0 - CSS CSS_SHA_DATA Out Register 0 */
/*! @{ */

#define CSS_CSS_SHA2_DOUT0_sha_data0_MASK        (0xFFFFFFFFU)
#define CSS_CSS_SHA2_DOUT0_sha_data0_SHIFT       (0U)
/*! sha_data0 - Output SHA_DATA from CSS Application being executed
 */
#define CSS_CSS_SHA2_DOUT0_sha_data0(x)          (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_DOUT0_sha_data0_SHIFT)) & CSS_CSS_SHA2_DOUT0_sha_data0_MASK)
/*! @} */

/*! @name CSS_SHA2_DOUT1 - CSS SHA_DATA Out Register 1 */
/*! @{ */

#define CSS_CSS_SHA2_DOUT1_sha_data1_MASK        (0xFFFFFFFFU)
#define CSS_CSS_SHA2_DOUT1_sha_data1_SHIFT       (0U)
/*! sha_data1 - Output SHA_DATA from CSS Application being executed
 */
#define CSS_CSS_SHA2_DOUT1_sha_data1(x)          (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_DOUT1_sha_data1_SHIFT)) & CSS_CSS_SHA2_DOUT1_sha_data1_MASK)
/*! @} */

/*! @name CSS_SHA2_DOUT2 - CSS SHA_DATA Out Register 2 */
/*! @{ */

#define CSS_CSS_SHA2_DOUT2_sha_data2_MASK        (0xFFFFFFFFU)
#define CSS_CSS_SHA2_DOUT2_sha_data2_SHIFT       (0U)
/*! sha_data2 - Output SHA_DATA from CSS Application being executed
 */
#define CSS_CSS_SHA2_DOUT2_sha_data2(x)          (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_DOUT2_sha_data2_SHIFT)) & CSS_CSS_SHA2_DOUT2_sha_data2_MASK)
/*! @} */

/*! @name CSS_SHA2_DOUT3 - CSS SHA_DATA Out Register 3 */
/*! @{ */

#define CSS_CSS_SHA2_DOUT3_sha_data3_MASK        (0xFFFFFFFFU)
#define CSS_CSS_SHA2_DOUT3_sha_data3_SHIFT       (0U)
/*! sha_data3 - Output SHA_DATA from CSS Application being executed
 */
#define CSS_CSS_SHA2_DOUT3_sha_data3(x)          (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_DOUT3_sha_data3_SHIFT)) & CSS_CSS_SHA2_DOUT3_sha_data3_MASK)
/*! @} */

/*! @name CSS_SHA2_DOUT4 - CSS SHA_DATA Out Register 4 */
/*! @{ */

#define CSS_CSS_SHA2_DOUT4_sha_data4_MASK        (0xFFFFFFFFU)
#define CSS_CSS_SHA2_DOUT4_sha_data4_SHIFT       (0U)
/*! sha_data4 - Output SHA_DATA from CSS Application being executed
 */
#define CSS_CSS_SHA2_DOUT4_sha_data4(x)          (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_DOUT4_sha_data4_SHIFT)) & CSS_CSS_SHA2_DOUT4_sha_data4_MASK)
/*! @} */

/*! @name CSS_SHA2_DOUT5 - CSS SHA_DATA Out Register 5 */
/*! @{ */

#define CSS_CSS_SHA2_DOUT5_sha_data5_MASK        (0xFFFFFFFFU)
#define CSS_CSS_SHA2_DOUT5_sha_data5_SHIFT       (0U)
/*! sha_data5 - Output SHA_DATA from CSS Application being executed
 */
#define CSS_CSS_SHA2_DOUT5_sha_data5(x)          (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_DOUT5_sha_data5_SHIFT)) & CSS_CSS_SHA2_DOUT5_sha_data5_MASK)
/*! @} */

/*! @name CSS_SHA2_DOUT6 - CSS SHA_DATA Out Register 6 */
/*! @{ */

#define CSS_CSS_SHA2_DOUT6_sha_data6_MASK        (0xFFFFFFFFU)
#define CSS_CSS_SHA2_DOUT6_sha_data6_SHIFT       (0U)
/*! sha_data6 - Output SHA_DATA from CSS Application being executed
 */
#define CSS_CSS_SHA2_DOUT6_sha_data6(x)          (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_DOUT6_sha_data6_SHIFT)) & CSS_CSS_SHA2_DOUT6_sha_data6_MASK)
/*! @} */

/*! @name CSS_SHA2_DOUT7 - CSS SHA_DATA Out Register 7 */
/*! @{ */

#define CSS_CSS_SHA2_DOUT7_sha_data7_MASK        (0xFFFFFFFFU)
#define CSS_CSS_SHA2_DOUT7_sha_data7_SHIFT       (0U)
/*! sha_data7 - Output SHA_DATA from CSS Application being executed
 */
#define CSS_CSS_SHA2_DOUT7_sha_data7(x)          (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_DOUT7_sha_data7_SHIFT)) & CSS_CSS_SHA2_DOUT7_sha_data7_MASK)
/*! @} */

/*! @name CSS_SHA2_DOUT8 - CSS CSS_SHA_DATA Out Register 8 */
/*! @{ */

#define CSS_CSS_SHA2_DOUT8_sha_data8_MASK        (0xFFFFFFFFU)
#define CSS_CSS_SHA2_DOUT8_sha_data8_SHIFT       (0U)
/*! sha_data8 - Output SHA_DATA from CSS Application being executed
 */
#define CSS_CSS_SHA2_DOUT8_sha_data8(x)          (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_DOUT8_sha_data8_SHIFT)) & CSS_CSS_SHA2_DOUT8_sha_data8_MASK)
/*! @} */

/*! @name CSS_SHA2_DOUT9 - CSS SHA_DATA Out Register 9 */
/*! @{ */

#define CSS_CSS_SHA2_DOUT9_sha_data9_MASK        (0xFFFFFFFFU)
#define CSS_CSS_SHA2_DOUT9_sha_data9_SHIFT       (0U)
/*! sha_data9 - Output SHA_DATA from CSS Application being executed
 */
#define CSS_CSS_SHA2_DOUT9_sha_data9(x)          (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_DOUT9_sha_data9_SHIFT)) & CSS_CSS_SHA2_DOUT9_sha_data9_MASK)
/*! @} */

/*! @name CSS_SHA2_DOUT10 - CSS SHA_DATA Out Register 10 */
/*! @{ */

#define CSS_CSS_SHA2_DOUT10_sha_data10_MASK      (0xFFFFFFFFU)
#define CSS_CSS_SHA2_DOUT10_sha_data10_SHIFT     (0U)
/*! sha_data10 - Output SHA_DATA from CSS Application being executed
 */
#define CSS_CSS_SHA2_DOUT10_sha_data10(x)        (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_DOUT10_sha_data10_SHIFT)) & CSS_CSS_SHA2_DOUT10_sha_data10_MASK)
/*! @} */

/*! @name CSS_SHA2_DOUT11 - CSS SHA_DATA Out Register 11 */
/*! @{ */

#define CSS_CSS_SHA2_DOUT11_sha_data11_MASK      (0xFFFFFFFFU)
#define CSS_CSS_SHA2_DOUT11_sha_data11_SHIFT     (0U)
/*! sha_data11 - Output SHA_DATA from CSS Application being executed
 */
#define CSS_CSS_SHA2_DOUT11_sha_data11(x)        (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_DOUT11_sha_data11_SHIFT)) & CSS_CSS_SHA2_DOUT11_sha_data11_MASK)
/*! @} */

/*! @name CSS_SHA2_DOUT12 - CSS SHA_DATA Out Register 12 */
/*! @{ */

#define CSS_CSS_SHA2_DOUT12_sha_data12_MASK      (0xFFFFFFFFU)
#define CSS_CSS_SHA2_DOUT12_sha_data12_SHIFT     (0U)
/*! sha_data12 - Output SHA_DATA from CSS Application being executed
 */
#define CSS_CSS_SHA2_DOUT12_sha_data12(x)        (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_DOUT12_sha_data12_SHIFT)) & CSS_CSS_SHA2_DOUT12_sha_data12_MASK)
/*! @} */

/*! @name CSS_SHA2_DOUT13 - CSS SHA_DATA Out Register 13 */
/*! @{ */

#define CSS_CSS_SHA2_DOUT13_sha_data13_MASK      (0xFFFFFFFFU)
#define CSS_CSS_SHA2_DOUT13_sha_data13_SHIFT     (0U)
/*! sha_data13 - Output SHA_DATA from CSS Application being executed
 */
#define CSS_CSS_SHA2_DOUT13_sha_data13(x)        (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_DOUT13_sha_data13_SHIFT)) & CSS_CSS_SHA2_DOUT13_sha_data13_MASK)
/*! @} */

/*! @name CSS_SHA2_DOUT14 - CSS SHA_DATA Out Register 14 */
/*! @{ */

#define CSS_CSS_SHA2_DOUT14_sha_data14_MASK      (0xFFFFFFFFU)
#define CSS_CSS_SHA2_DOUT14_sha_data14_SHIFT     (0U)
/*! sha_data14 - Output SHA_DATA from CSS Application being executed
 */
#define CSS_CSS_SHA2_DOUT14_sha_data14(x)        (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_DOUT14_sha_data14_SHIFT)) & CSS_CSS_SHA2_DOUT14_sha_data14_MASK)
/*! @} */

/*! @name CSS_SHA2_DOUT15 - CSS SHA_DATA Out Register 15 */
/*! @{ */

#define CSS_CSS_SHA2_DOUT15_sha_data15_MASK      (0xFFFFFFFFU)
#define CSS_CSS_SHA2_DOUT15_sha_data15_SHIFT     (0U)
/*! sha_data15 - Output SHA_DATA from CSS Application being executed
 */
#define CSS_CSS_SHA2_DOUT15_sha_data15(x)        (((uint32_t)(((uint32_t)(x)) << CSS_CSS_SHA2_DOUT15_sha_data15_SHIFT)) & CSS_CSS_SHA2_DOUT15_sha_data15_MASK)
/*! @} */

/*! @name CSS_KS0 - Status register */
/*! @{ */

#define CSS_CSS_KS0_ks0_ksize_MASK               (0x1U)
#define CSS_CSS_KS0_ks0_ksize_SHIFT              (0U)
/*! ks0_ksize - Key size: 0-128, 1-256
 */
#define CSS_CSS_KS0_ks0_ksize(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_ksize_SHIFT)) & CSS_CSS_KS0_ks0_ksize_MASK)

#define CSS_CSS_KS0_ks0_rsvd0_MASK               (0x1EU)
#define CSS_CSS_KS0_ks0_rsvd0_SHIFT              (1U)
/*! ks0_rsvd0 - Reserved 0
 */
#define CSS_CSS_KS0_ks0_rsvd0(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_rsvd0_SHIFT)) & CSS_CSS_KS0_ks0_rsvd0_MASK)

#define CSS_CSS_KS0_ks0_kact_MASK                (0x20U)
#define CSS_CSS_KS0_ks0_kact_SHIFT               (5U)
/*! ks0_kact - Key is active
 */
#define CSS_CSS_KS0_ks0_kact(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_kact_SHIFT)) & CSS_CSS_KS0_ks0_kact_MASK)

#define CSS_CSS_KS0_ks0_kbase_MASK               (0x40U)
#define CSS_CSS_KS0_ks0_kbase_SHIFT              (6U)
/*! ks0_kbase - First slot in a multislot key
 */
#define CSS_CSS_KS0_ks0_kbase(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_kbase_SHIFT)) & CSS_CSS_KS0_ks0_kbase_MASK)

#define CSS_CSS_KS0_ks0_fgp_MASK                 (0x80U)
#define CSS_CSS_KS0_ks0_fgp_SHIFT                (7U)
/*! ks0_fgp - Hardware Feature General Purpose
 */
#define CSS_CSS_KS0_ks0_fgp(x)                   (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_fgp_SHIFT)) & CSS_CSS_KS0_ks0_fgp_MASK)

#define CSS_CSS_KS0_ks0_frtn_MASK                (0x100U)
#define CSS_CSS_KS0_ks0_frtn_SHIFT               (8U)
/*! ks0_frtn - Hardware Feature Retention
 */
#define CSS_CSS_KS0_ks0_frtn(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_frtn_SHIFT)) & CSS_CSS_KS0_ks0_frtn_MASK)

#define CSS_CSS_KS0_ks0_fhwo_MASK                (0x200U)
#define CSS_CSS_KS0_ks0_fhwo_SHIFT               (9U)
/*! ks0_fhwo - Hardware Feature Output
 */
#define CSS_CSS_KS0_ks0_fhwo(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_fhwo_SHIFT)) & CSS_CSS_KS0_ks0_fhwo_MASK)

#define CSS_CSS_KS0_ks0_rsvd1_MASK               (0x1C00U)
#define CSS_CSS_KS0_ks0_rsvd1_SHIFT              (10U)
/*! ks0_rsvd1 - Reserved 1
 */
#define CSS_CSS_KS0_ks0_rsvd1(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_rsvd1_SHIFT)) & CSS_CSS_KS0_ks0_rsvd1_MASK)

#define CSS_CSS_KS0_ks0_ucmac_MASK               (0x2000U)
#define CSS_CSS_KS0_ks0_ucmac_SHIFT              (13U)
/*! ks0_ucmac - CMAC key
 */
#define CSS_CSS_KS0_ks0_ucmac(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_ucmac_SHIFT)) & CSS_CSS_KS0_ks0_ucmac_MASK)

#define CSS_CSS_KS0_ks0_uksk_MASK                (0x4000U)
#define CSS_CSS_KS0_ks0_uksk_SHIFT               (14U)
/*! ks0_uksk - KSK key
 */
#define CSS_CSS_KS0_ks0_uksk(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_uksk_SHIFT)) & CSS_CSS_KS0_ks0_uksk_MASK)

#define CSS_CSS_KS0_ks0_urtf_MASK                (0x8000U)
#define CSS_CSS_KS0_ks0_urtf_SHIFT               (15U)
/*! ks0_urtf - Real Time Fingerprint key
 */
#define CSS_CSS_KS0_ks0_urtf(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_urtf_SHIFT)) & CSS_CSS_KS0_ks0_urtf_MASK)

#define CSS_CSS_KS0_ks0_uckdf_MASK               (0x10000U)
#define CSS_CSS_KS0_ks0_uckdf_SHIFT              (16U)
/*! ks0_uckdf - Derivation key for CKDF command
 */
#define CSS_CSS_KS0_ks0_uckdf(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_uckdf_SHIFT)) & CSS_CSS_KS0_ks0_uckdf_MASK)

#define CSS_CSS_KS0_ks0_uhkdf_MASK               (0x20000U)
#define CSS_CSS_KS0_ks0_uhkdf_SHIFT              (17U)
/*! ks0_uhkdf - Derivation key for HKDF command
 */
#define CSS_CSS_KS0_ks0_uhkdf(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_uhkdf_SHIFT)) & CSS_CSS_KS0_ks0_uhkdf_MASK)

#define CSS_CSS_KS0_ks0_uecsg_MASK               (0x40000U)
#define CSS_CSS_KS0_ks0_uecsg_SHIFT              (18U)
/*! ks0_uecsg - Ecc signing key
 */
#define CSS_CSS_KS0_ks0_uecsg(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_uecsg_SHIFT)) & CSS_CSS_KS0_ks0_uecsg_MASK)

#define CSS_CSS_KS0_ks0_uecdh_MASK               (0x80000U)
#define CSS_CSS_KS0_ks0_uecdh_SHIFT              (19U)
/*! ks0_uecdh - Ecc diffie hellman key
 */
#define CSS_CSS_KS0_ks0_uecdh(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_uecdh_SHIFT)) & CSS_CSS_KS0_ks0_uecdh_MASK)

#define CSS_CSS_KS0_ks0_uaes_MASK                (0x100000U)
#define CSS_CSS_KS0_ks0_uaes_SHIFT               (20U)
/*! ks0_uaes - Aes key
 */
#define CSS_CSS_KS0_ks0_uaes(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_uaes_SHIFT)) & CSS_CSS_KS0_ks0_uaes_MASK)

#define CSS_CSS_KS0_ks0_uhmac_MASK               (0x200000U)
#define CSS_CSS_KS0_ks0_uhmac_SHIFT              (21U)
/*! ks0_uhmac - Hmac key
 */
#define CSS_CSS_KS0_ks0_uhmac(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_uhmac_SHIFT)) & CSS_CSS_KS0_ks0_uhmac_MASK)

#define CSS_CSS_KS0_ks0_ukwk_MASK                (0x400000U)
#define CSS_CSS_KS0_ks0_ukwk_SHIFT               (22U)
/*! ks0_ukwk - Key wrapping key
 */
#define CSS_CSS_KS0_ks0_ukwk(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_ukwk_SHIFT)) & CSS_CSS_KS0_ks0_ukwk_MASK)

#define CSS_CSS_KS0_ks0_ukuok_MASK               (0x800000U)
#define CSS_CSS_KS0_ks0_ukuok_SHIFT              (23U)
/*! ks0_ukuok - Key unwrapping key
 */
#define CSS_CSS_KS0_ks0_ukuok(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_ukuok_SHIFT)) & CSS_CSS_KS0_ks0_ukuok_MASK)

#define CSS_CSS_KS0_ks0_utlspms_MASK             (0x1000000U)
#define CSS_CSS_KS0_ks0_utlspms_SHIFT            (24U)
/*! ks0_utlspms - TLS Pre Master Secret
 */
#define CSS_CSS_KS0_ks0_utlspms(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_utlspms_SHIFT)) & CSS_CSS_KS0_ks0_utlspms_MASK)

#define CSS_CSS_KS0_ks0_utlsms_MASK              (0x2000000U)
#define CSS_CSS_KS0_ks0_utlsms_SHIFT             (25U)
/*! ks0_utlsms - TLS Master Secret
 */
#define CSS_CSS_KS0_ks0_utlsms(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_utlsms_SHIFT)) & CSS_CSS_KS0_ks0_utlsms_MASK)

#define CSS_CSS_KS0_ks0_ukgsrc_MASK              (0x4000000U)
#define CSS_CSS_KS0_ks0_ukgsrc_SHIFT             (26U)
/*! ks0_ukgsrc - Supply KEYGEN source
 */
#define CSS_CSS_KS0_ks0_ukgsrc(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_ukgsrc_SHIFT)) & CSS_CSS_KS0_ks0_ukgsrc_MASK)

#define CSS_CSS_KS0_ks0_uhwo_MASK                (0x8000000U)
#define CSS_CSS_KS0_ks0_uhwo_SHIFT               (27U)
/*! ks0_uhwo - Hardware out key
 */
#define CSS_CSS_KS0_ks0_uhwo(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_uhwo_SHIFT)) & CSS_CSS_KS0_ks0_uhwo_MASK)

#define CSS_CSS_KS0_ks0_uwrpok_MASK              (0x10000000U)
#define CSS_CSS_KS0_ks0_uwrpok_SHIFT             (28U)
/*! ks0_uwrpok - Ok to wrap key
 */
#define CSS_CSS_KS0_ks0_uwrpok(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_uwrpok_SHIFT)) & CSS_CSS_KS0_ks0_uwrpok_MASK)

#define CSS_CSS_KS0_ks0_uduk_MASK                (0x20000000U)
#define CSS_CSS_KS0_ks0_uduk_SHIFT               (29U)
/*! ks0_uduk - Device Unique Key
 */
#define CSS_CSS_KS0_ks0_uduk(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_uduk_SHIFT)) & CSS_CSS_KS0_ks0_uduk_MASK)

#define CSS_CSS_KS0_ks0_upprot_MASK              (0xC0000000U)
#define CSS_CSS_KS0_ks0_upprot_SHIFT             (30U)
/*! ks0_upprot - Priviledge level
 */
#define CSS_CSS_KS0_ks0_upprot(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS0_ks0_upprot_SHIFT)) & CSS_CSS_KS0_ks0_upprot_MASK)
/*! @} */

/*! @name CSS_KS1 - Status register */
/*! @{ */

#define CSS_CSS_KS1_ks1_ksize_MASK               (0x1U)
#define CSS_CSS_KS1_ks1_ksize_SHIFT              (0U)
/*! ks1_ksize - Key size: 0-128, 1-256
 */
#define CSS_CSS_KS1_ks1_ksize(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_ksize_SHIFT)) & CSS_CSS_KS1_ks1_ksize_MASK)

#define CSS_CSS_KS1_ks1_rsvd0_MASK               (0x1EU)
#define CSS_CSS_KS1_ks1_rsvd0_SHIFT              (1U)
/*! ks1_rsvd0 - Reserved 0
 */
#define CSS_CSS_KS1_ks1_rsvd0(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_rsvd0_SHIFT)) & CSS_CSS_KS1_ks1_rsvd0_MASK)

#define CSS_CSS_KS1_ks1_kact_MASK                (0x20U)
#define CSS_CSS_KS1_ks1_kact_SHIFT               (5U)
/*! ks1_kact - Key is active
 */
#define CSS_CSS_KS1_ks1_kact(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_kact_SHIFT)) & CSS_CSS_KS1_ks1_kact_MASK)

#define CSS_CSS_KS1_ks1_kbase_MASK               (0x40U)
#define CSS_CSS_KS1_ks1_kbase_SHIFT              (6U)
/*! ks1_kbase - First slot in a multislot key
 */
#define CSS_CSS_KS1_ks1_kbase(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_kbase_SHIFT)) & CSS_CSS_KS1_ks1_kbase_MASK)

#define CSS_CSS_KS1_ks1_fgp_MASK                 (0x80U)
#define CSS_CSS_KS1_ks1_fgp_SHIFT                (7U)
/*! ks1_fgp - Hardware Feature General Purpose
 */
#define CSS_CSS_KS1_ks1_fgp(x)                   (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_fgp_SHIFT)) & CSS_CSS_KS1_ks1_fgp_MASK)

#define CSS_CSS_KS1_ks1_frtn_MASK                (0x100U)
#define CSS_CSS_KS1_ks1_frtn_SHIFT               (8U)
/*! ks1_frtn - Hardware Feature Retention
 */
#define CSS_CSS_KS1_ks1_frtn(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_frtn_SHIFT)) & CSS_CSS_KS1_ks1_frtn_MASK)

#define CSS_CSS_KS1_ks1_fhwo_MASK                (0x200U)
#define CSS_CSS_KS1_ks1_fhwo_SHIFT               (9U)
/*! ks1_fhwo - Hardware Feature Output
 */
#define CSS_CSS_KS1_ks1_fhwo(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_fhwo_SHIFT)) & CSS_CSS_KS1_ks1_fhwo_MASK)

#define CSS_CSS_KS1_ks1_rsvd1_MASK               (0x1C00U)
#define CSS_CSS_KS1_ks1_rsvd1_SHIFT              (10U)
/*! ks1_rsvd1 - Reserved 1
 */
#define CSS_CSS_KS1_ks1_rsvd1(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_rsvd1_SHIFT)) & CSS_CSS_KS1_ks1_rsvd1_MASK)

#define CSS_CSS_KS1_ks1_ucmac_MASK               (0x2000U)
#define CSS_CSS_KS1_ks1_ucmac_SHIFT              (13U)
/*! ks1_ucmac - CMAC key
 */
#define CSS_CSS_KS1_ks1_ucmac(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_ucmac_SHIFT)) & CSS_CSS_KS1_ks1_ucmac_MASK)

#define CSS_CSS_KS1_ks1_uksk_MASK                (0x4000U)
#define CSS_CSS_KS1_ks1_uksk_SHIFT               (14U)
/*! ks1_uksk - KSK key
 */
#define CSS_CSS_KS1_ks1_uksk(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_uksk_SHIFT)) & CSS_CSS_KS1_ks1_uksk_MASK)

#define CSS_CSS_KS1_ks1_urtf_MASK                (0x8000U)
#define CSS_CSS_KS1_ks1_urtf_SHIFT               (15U)
/*! ks1_urtf - Real Time Fingerprint key
 */
#define CSS_CSS_KS1_ks1_urtf(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_urtf_SHIFT)) & CSS_CSS_KS1_ks1_urtf_MASK)

#define CSS_CSS_KS1_ks1_uckdf_MASK               (0x10000U)
#define CSS_CSS_KS1_ks1_uckdf_SHIFT              (16U)
/*! ks1_uckdf - Derivation key for CKDF command
 */
#define CSS_CSS_KS1_ks1_uckdf(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_uckdf_SHIFT)) & CSS_CSS_KS1_ks1_uckdf_MASK)

#define CSS_CSS_KS1_ks1_uhkdf_MASK               (0x20000U)
#define CSS_CSS_KS1_ks1_uhkdf_SHIFT              (17U)
/*! ks1_uhkdf - Derivation key for HKDF command
 */
#define CSS_CSS_KS1_ks1_uhkdf(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_uhkdf_SHIFT)) & CSS_CSS_KS1_ks1_uhkdf_MASK)

#define CSS_CSS_KS1_ks1_uecsg_MASK               (0x40000U)
#define CSS_CSS_KS1_ks1_uecsg_SHIFT              (18U)
/*! ks1_uecsg - Ecc signing key
 */
#define CSS_CSS_KS1_ks1_uecsg(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_uecsg_SHIFT)) & CSS_CSS_KS1_ks1_uecsg_MASK)

#define CSS_CSS_KS1_ks1_uecdh_MASK               (0x80000U)
#define CSS_CSS_KS1_ks1_uecdh_SHIFT              (19U)
/*! ks1_uecdh - Ecc diffie hellman key
 */
#define CSS_CSS_KS1_ks1_uecdh(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_uecdh_SHIFT)) & CSS_CSS_KS1_ks1_uecdh_MASK)

#define CSS_CSS_KS1_ks1_uaes_MASK                (0x100000U)
#define CSS_CSS_KS1_ks1_uaes_SHIFT               (20U)
/*! ks1_uaes - Aes key
 */
#define CSS_CSS_KS1_ks1_uaes(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_uaes_SHIFT)) & CSS_CSS_KS1_ks1_uaes_MASK)

#define CSS_CSS_KS1_ks1_uhmac_MASK               (0x200000U)
#define CSS_CSS_KS1_ks1_uhmac_SHIFT              (21U)
/*! ks1_uhmac - Hmac key
 */
#define CSS_CSS_KS1_ks1_uhmac(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_uhmac_SHIFT)) & CSS_CSS_KS1_ks1_uhmac_MASK)

#define CSS_CSS_KS1_ks1_ukwk_MASK                (0x400000U)
#define CSS_CSS_KS1_ks1_ukwk_SHIFT               (22U)
/*! ks1_ukwk - Key wrapping key
 */
#define CSS_CSS_KS1_ks1_ukwk(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_ukwk_SHIFT)) & CSS_CSS_KS1_ks1_ukwk_MASK)

#define CSS_CSS_KS1_ks1_ukuok_MASK               (0x800000U)
#define CSS_CSS_KS1_ks1_ukuok_SHIFT              (23U)
/*! ks1_ukuok - Key unwrapping key
 */
#define CSS_CSS_KS1_ks1_ukuok(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_ukuok_SHIFT)) & CSS_CSS_KS1_ks1_ukuok_MASK)

#define CSS_CSS_KS1_ks1_utlspms_MASK             (0x1000000U)
#define CSS_CSS_KS1_ks1_utlspms_SHIFT            (24U)
/*! ks1_utlspms - TLS Pre Master Secret
 */
#define CSS_CSS_KS1_ks1_utlspms(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_utlspms_SHIFT)) & CSS_CSS_KS1_ks1_utlspms_MASK)

#define CSS_CSS_KS1_ks1_utlsms_MASK              (0x2000000U)
#define CSS_CSS_KS1_ks1_utlsms_SHIFT             (25U)
/*! ks1_utlsms - TLS Master Secret
 */
#define CSS_CSS_KS1_ks1_utlsms(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_utlsms_SHIFT)) & CSS_CSS_KS1_ks1_utlsms_MASK)

#define CSS_CSS_KS1_ks1_ukgsrc_MASK              (0x4000000U)
#define CSS_CSS_KS1_ks1_ukgsrc_SHIFT             (26U)
/*! ks1_ukgsrc - Supply KEYGEN source
 */
#define CSS_CSS_KS1_ks1_ukgsrc(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_ukgsrc_SHIFT)) & CSS_CSS_KS1_ks1_ukgsrc_MASK)

#define CSS_CSS_KS1_ks1_uhwo_MASK                (0x8000000U)
#define CSS_CSS_KS1_ks1_uhwo_SHIFT               (27U)
/*! ks1_uhwo - Hardware out key
 */
#define CSS_CSS_KS1_ks1_uhwo(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_uhwo_SHIFT)) & CSS_CSS_KS1_ks1_uhwo_MASK)

#define CSS_CSS_KS1_ks1_uwrpok_MASK              (0x10000000U)
#define CSS_CSS_KS1_ks1_uwrpok_SHIFT             (28U)
/*! ks1_uwrpok - Ok to wrap key
 */
#define CSS_CSS_KS1_ks1_uwrpok(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_uwrpok_SHIFT)) & CSS_CSS_KS1_ks1_uwrpok_MASK)

#define CSS_CSS_KS1_ks1_uduk_MASK                (0x20000000U)
#define CSS_CSS_KS1_ks1_uduk_SHIFT               (29U)
/*! ks1_uduk - Device Unique Key
 */
#define CSS_CSS_KS1_ks1_uduk(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_uduk_SHIFT)) & CSS_CSS_KS1_ks1_uduk_MASK)

#define CSS_CSS_KS1_ks1_upprot_MASK              (0xC0000000U)
#define CSS_CSS_KS1_ks1_upprot_SHIFT             (30U)
/*! ks1_upprot - Priviledge level
 */
#define CSS_CSS_KS1_ks1_upprot(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS1_ks1_upprot_SHIFT)) & CSS_CSS_KS1_ks1_upprot_MASK)
/*! @} */

/*! @name CSS_KS2 - Status register */
/*! @{ */

#define CSS_CSS_KS2_ks2_ksize_MASK               (0x1U)
#define CSS_CSS_KS2_ks2_ksize_SHIFT              (0U)
/*! ks2_ksize - Key size: 0-128, 1-256
 */
#define CSS_CSS_KS2_ks2_ksize(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_ksize_SHIFT)) & CSS_CSS_KS2_ks2_ksize_MASK)

#define CSS_CSS_KS2_ks2_rsvd0_MASK               (0x1EU)
#define CSS_CSS_KS2_ks2_rsvd0_SHIFT              (1U)
/*! ks2_rsvd0 - Reserved 0
 */
#define CSS_CSS_KS2_ks2_rsvd0(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_rsvd0_SHIFT)) & CSS_CSS_KS2_ks2_rsvd0_MASK)

#define CSS_CSS_KS2_ks2_kact_MASK                (0x20U)
#define CSS_CSS_KS2_ks2_kact_SHIFT               (5U)
/*! ks2_kact - Key is active
 */
#define CSS_CSS_KS2_ks2_kact(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_kact_SHIFT)) & CSS_CSS_KS2_ks2_kact_MASK)

#define CSS_CSS_KS2_ks2_kbase_MASK               (0x40U)
#define CSS_CSS_KS2_ks2_kbase_SHIFT              (6U)
/*! ks2_kbase - First slot in a multislot key
 */
#define CSS_CSS_KS2_ks2_kbase(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_kbase_SHIFT)) & CSS_CSS_KS2_ks2_kbase_MASK)

#define CSS_CSS_KS2_ks2_fgp_MASK                 (0x80U)
#define CSS_CSS_KS2_ks2_fgp_SHIFT                (7U)
/*! ks2_fgp - Hardware Feature General Purpose
 */
#define CSS_CSS_KS2_ks2_fgp(x)                   (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_fgp_SHIFT)) & CSS_CSS_KS2_ks2_fgp_MASK)

#define CSS_CSS_KS2_ks2_frtn_MASK                (0x100U)
#define CSS_CSS_KS2_ks2_frtn_SHIFT               (8U)
/*! ks2_frtn - Hardware Feature Retention
 */
#define CSS_CSS_KS2_ks2_frtn(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_frtn_SHIFT)) & CSS_CSS_KS2_ks2_frtn_MASK)

#define CSS_CSS_KS2_ks2_fhwo_MASK                (0x200U)
#define CSS_CSS_KS2_ks2_fhwo_SHIFT               (9U)
/*! ks2_fhwo - Hardware Feature Output
 */
#define CSS_CSS_KS2_ks2_fhwo(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_fhwo_SHIFT)) & CSS_CSS_KS2_ks2_fhwo_MASK)

#define CSS_CSS_KS2_ks2_rsvd1_MASK               (0x1C00U)
#define CSS_CSS_KS2_ks2_rsvd1_SHIFT              (10U)
/*! ks2_rsvd1 - Reserved 1
 */
#define CSS_CSS_KS2_ks2_rsvd1(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_rsvd1_SHIFT)) & CSS_CSS_KS2_ks2_rsvd1_MASK)

#define CSS_CSS_KS2_ks2_ucmac_MASK               (0x2000U)
#define CSS_CSS_KS2_ks2_ucmac_SHIFT              (13U)
/*! ks2_ucmac - CMAC key
 */
#define CSS_CSS_KS2_ks2_ucmac(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_ucmac_SHIFT)) & CSS_CSS_KS2_ks2_ucmac_MASK)

#define CSS_CSS_KS2_ks2_uksk_MASK                (0x4000U)
#define CSS_CSS_KS2_ks2_uksk_SHIFT               (14U)
/*! ks2_uksk - KSK key
 */
#define CSS_CSS_KS2_ks2_uksk(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_uksk_SHIFT)) & CSS_CSS_KS2_ks2_uksk_MASK)

#define CSS_CSS_KS2_ks2_urtf_MASK                (0x8000U)
#define CSS_CSS_KS2_ks2_urtf_SHIFT               (15U)
/*! ks2_urtf - Real Time Fingerprint key
 */
#define CSS_CSS_KS2_ks2_urtf(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_urtf_SHIFT)) & CSS_CSS_KS2_ks2_urtf_MASK)

#define CSS_CSS_KS2_ks2_uckdf_MASK               (0x10000U)
#define CSS_CSS_KS2_ks2_uckdf_SHIFT              (16U)
/*! ks2_uckdf - Derivation key for CKDF command
 */
#define CSS_CSS_KS2_ks2_uckdf(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_uckdf_SHIFT)) & CSS_CSS_KS2_ks2_uckdf_MASK)

#define CSS_CSS_KS2_ks2_uhkdf_MASK               (0x20000U)
#define CSS_CSS_KS2_ks2_uhkdf_SHIFT              (17U)
/*! ks2_uhkdf - Derivation key for HKDF command
 */
#define CSS_CSS_KS2_ks2_uhkdf(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_uhkdf_SHIFT)) & CSS_CSS_KS2_ks2_uhkdf_MASK)

#define CSS_CSS_KS2_ks2_uecsg_MASK               (0x40000U)
#define CSS_CSS_KS2_ks2_uecsg_SHIFT              (18U)
/*! ks2_uecsg - Ecc signing key
 */
#define CSS_CSS_KS2_ks2_uecsg(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_uecsg_SHIFT)) & CSS_CSS_KS2_ks2_uecsg_MASK)

#define CSS_CSS_KS2_ks2_uecdh_MASK               (0x80000U)
#define CSS_CSS_KS2_ks2_uecdh_SHIFT              (19U)
/*! ks2_uecdh - Ecc diffie hellman key
 */
#define CSS_CSS_KS2_ks2_uecdh(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_uecdh_SHIFT)) & CSS_CSS_KS2_ks2_uecdh_MASK)

#define CSS_CSS_KS2_ks2_uaes_MASK                (0x100000U)
#define CSS_CSS_KS2_ks2_uaes_SHIFT               (20U)
/*! ks2_uaes - Aes key
 */
#define CSS_CSS_KS2_ks2_uaes(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_uaes_SHIFT)) & CSS_CSS_KS2_ks2_uaes_MASK)

#define CSS_CSS_KS2_ks2_uhmac_MASK               (0x200000U)
#define CSS_CSS_KS2_ks2_uhmac_SHIFT              (21U)
/*! ks2_uhmac - Hmac key
 */
#define CSS_CSS_KS2_ks2_uhmac(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_uhmac_SHIFT)) & CSS_CSS_KS2_ks2_uhmac_MASK)

#define CSS_CSS_KS2_ks2_ukwk_MASK                (0x400000U)
#define CSS_CSS_KS2_ks2_ukwk_SHIFT               (22U)
/*! ks2_ukwk - Key wrapping key
 */
#define CSS_CSS_KS2_ks2_ukwk(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_ukwk_SHIFT)) & CSS_CSS_KS2_ks2_ukwk_MASK)

#define CSS_CSS_KS2_ks2_ukuok_MASK               (0x800000U)
#define CSS_CSS_KS2_ks2_ukuok_SHIFT              (23U)
/*! ks2_ukuok - Key unwrapping key
 */
#define CSS_CSS_KS2_ks2_ukuok(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_ukuok_SHIFT)) & CSS_CSS_KS2_ks2_ukuok_MASK)

#define CSS_CSS_KS2_ks2_utlspms_MASK             (0x1000000U)
#define CSS_CSS_KS2_ks2_utlspms_SHIFT            (24U)
/*! ks2_utlspms - TLS Pre Master Secret
 */
#define CSS_CSS_KS2_ks2_utlspms(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_utlspms_SHIFT)) & CSS_CSS_KS2_ks2_utlspms_MASK)

#define CSS_CSS_KS2_ks2_utlsms_MASK              (0x2000000U)
#define CSS_CSS_KS2_ks2_utlsms_SHIFT             (25U)
/*! ks2_utlsms - TLS Master Secret
 */
#define CSS_CSS_KS2_ks2_utlsms(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_utlsms_SHIFT)) & CSS_CSS_KS2_ks2_utlsms_MASK)

#define CSS_CSS_KS2_ks2_ukgsrc_MASK              (0x4000000U)
#define CSS_CSS_KS2_ks2_ukgsrc_SHIFT             (26U)
/*! ks2_ukgsrc - Supply KEYGEN source
 */
#define CSS_CSS_KS2_ks2_ukgsrc(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_ukgsrc_SHIFT)) & CSS_CSS_KS2_ks2_ukgsrc_MASK)

#define CSS_CSS_KS2_ks2_uhwo_MASK                (0x8000000U)
#define CSS_CSS_KS2_ks2_uhwo_SHIFT               (27U)
/*! ks2_uhwo - Hardware out key
 */
#define CSS_CSS_KS2_ks2_uhwo(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_uhwo_SHIFT)) & CSS_CSS_KS2_ks2_uhwo_MASK)

#define CSS_CSS_KS2_ks2_uwrpok_MASK              (0x10000000U)
#define CSS_CSS_KS2_ks2_uwrpok_SHIFT             (28U)
/*! ks2_uwrpok - Ok to wrap key
 */
#define CSS_CSS_KS2_ks2_uwrpok(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_uwrpok_SHIFT)) & CSS_CSS_KS2_ks2_uwrpok_MASK)

#define CSS_CSS_KS2_ks2_uduk_MASK                (0x20000000U)
#define CSS_CSS_KS2_ks2_uduk_SHIFT               (29U)
/*! ks2_uduk - Device Unique Key
 */
#define CSS_CSS_KS2_ks2_uduk(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_uduk_SHIFT)) & CSS_CSS_KS2_ks2_uduk_MASK)

#define CSS_CSS_KS2_ks2_upprot_MASK              (0xC0000000U)
#define CSS_CSS_KS2_ks2_upprot_SHIFT             (30U)
/*! ks2_upprot - Priviledge level
 */
#define CSS_CSS_KS2_ks2_upprot(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS2_ks2_upprot_SHIFT)) & CSS_CSS_KS2_ks2_upprot_MASK)
/*! @} */

/*! @name CSS_KS3 - Status register */
/*! @{ */

#define CSS_CSS_KS3_ks3_ksize_MASK               (0x1U)
#define CSS_CSS_KS3_ks3_ksize_SHIFT              (0U)
/*! ks3_ksize - Key size: 0-128, 1-256
 */
#define CSS_CSS_KS3_ks3_ksize(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_ksize_SHIFT)) & CSS_CSS_KS3_ks3_ksize_MASK)

#define CSS_CSS_KS3_ks3_rsvd0_MASK               (0x1EU)
#define CSS_CSS_KS3_ks3_rsvd0_SHIFT              (1U)
/*! ks3_rsvd0 - Reserved 0
 */
#define CSS_CSS_KS3_ks3_rsvd0(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_rsvd0_SHIFT)) & CSS_CSS_KS3_ks3_rsvd0_MASK)

#define CSS_CSS_KS3_ks3_kact_MASK                (0x20U)
#define CSS_CSS_KS3_ks3_kact_SHIFT               (5U)
/*! ks3_kact - Key is active
 */
#define CSS_CSS_KS3_ks3_kact(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_kact_SHIFT)) & CSS_CSS_KS3_ks3_kact_MASK)

#define CSS_CSS_KS3_ks3_kbase_MASK               (0x40U)
#define CSS_CSS_KS3_ks3_kbase_SHIFT              (6U)
/*! ks3_kbase - First slot in a multislot key
 */
#define CSS_CSS_KS3_ks3_kbase(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_kbase_SHIFT)) & CSS_CSS_KS3_ks3_kbase_MASK)

#define CSS_CSS_KS3_ks3_fgp_MASK                 (0x80U)
#define CSS_CSS_KS3_ks3_fgp_SHIFT                (7U)
/*! ks3_fgp - Hardware Feature General Purpose
 */
#define CSS_CSS_KS3_ks3_fgp(x)                   (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_fgp_SHIFT)) & CSS_CSS_KS3_ks3_fgp_MASK)

#define CSS_CSS_KS3_ks3_frtn_MASK                (0x100U)
#define CSS_CSS_KS3_ks3_frtn_SHIFT               (8U)
/*! ks3_frtn - Hardware Feature Retention
 */
#define CSS_CSS_KS3_ks3_frtn(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_frtn_SHIFT)) & CSS_CSS_KS3_ks3_frtn_MASK)

#define CSS_CSS_KS3_ks3_fhwo_MASK                (0x200U)
#define CSS_CSS_KS3_ks3_fhwo_SHIFT               (9U)
/*! ks3_fhwo - Hardware Feature Output
 */
#define CSS_CSS_KS3_ks3_fhwo(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_fhwo_SHIFT)) & CSS_CSS_KS3_ks3_fhwo_MASK)

#define CSS_CSS_KS3_ks3_rsvd1_MASK               (0x1C00U)
#define CSS_CSS_KS3_ks3_rsvd1_SHIFT              (10U)
/*! ks3_rsvd1 - Reserved 1
 */
#define CSS_CSS_KS3_ks3_rsvd1(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_rsvd1_SHIFT)) & CSS_CSS_KS3_ks3_rsvd1_MASK)

#define CSS_CSS_KS3_ks3_ucmac_MASK               (0x2000U)
#define CSS_CSS_KS3_ks3_ucmac_SHIFT              (13U)
/*! ks3_ucmac - CMAC key
 */
#define CSS_CSS_KS3_ks3_ucmac(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_ucmac_SHIFT)) & CSS_CSS_KS3_ks3_ucmac_MASK)

#define CSS_CSS_KS3_ks3_uksk_MASK                (0x4000U)
#define CSS_CSS_KS3_ks3_uksk_SHIFT               (14U)
/*! ks3_uksk - KSK key
 */
#define CSS_CSS_KS3_ks3_uksk(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_uksk_SHIFT)) & CSS_CSS_KS3_ks3_uksk_MASK)

#define CSS_CSS_KS3_ks3_urtf_MASK                (0x8000U)
#define CSS_CSS_KS3_ks3_urtf_SHIFT               (15U)
/*! ks3_urtf - Real Time Fingerprint key
 */
#define CSS_CSS_KS3_ks3_urtf(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_urtf_SHIFT)) & CSS_CSS_KS3_ks3_urtf_MASK)

#define CSS_CSS_KS3_ks3_uckdf_MASK               (0x10000U)
#define CSS_CSS_KS3_ks3_uckdf_SHIFT              (16U)
/*! ks3_uckdf - Derivation key for CKDF command
 */
#define CSS_CSS_KS3_ks3_uckdf(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_uckdf_SHIFT)) & CSS_CSS_KS3_ks3_uckdf_MASK)

#define CSS_CSS_KS3_ks3_uhkdf_MASK               (0x20000U)
#define CSS_CSS_KS3_ks3_uhkdf_SHIFT              (17U)
/*! ks3_uhkdf - Derivation key for HKDF command
 */
#define CSS_CSS_KS3_ks3_uhkdf(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_uhkdf_SHIFT)) & CSS_CSS_KS3_ks3_uhkdf_MASK)

#define CSS_CSS_KS3_ks3_uecsg_MASK               (0x40000U)
#define CSS_CSS_KS3_ks3_uecsg_SHIFT              (18U)
/*! ks3_uecsg - Ecc signing key
 */
#define CSS_CSS_KS3_ks3_uecsg(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_uecsg_SHIFT)) & CSS_CSS_KS3_ks3_uecsg_MASK)

#define CSS_CSS_KS3_ks3_uecdh_MASK               (0x80000U)
#define CSS_CSS_KS3_ks3_uecdh_SHIFT              (19U)
/*! ks3_uecdh - Ecc diffie hellman key
 */
#define CSS_CSS_KS3_ks3_uecdh(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_uecdh_SHIFT)) & CSS_CSS_KS3_ks3_uecdh_MASK)

#define CSS_CSS_KS3_ks3_uaes_MASK                (0x100000U)
#define CSS_CSS_KS3_ks3_uaes_SHIFT               (20U)
/*! ks3_uaes - Aes key
 */
#define CSS_CSS_KS3_ks3_uaes(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_uaes_SHIFT)) & CSS_CSS_KS3_ks3_uaes_MASK)

#define CSS_CSS_KS3_ks3_uhmac_MASK               (0x200000U)
#define CSS_CSS_KS3_ks3_uhmac_SHIFT              (21U)
/*! ks3_uhmac - Hmac key
 */
#define CSS_CSS_KS3_ks3_uhmac(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_uhmac_SHIFT)) & CSS_CSS_KS3_ks3_uhmac_MASK)

#define CSS_CSS_KS3_ks3_ukwk_MASK                (0x400000U)
#define CSS_CSS_KS3_ks3_ukwk_SHIFT               (22U)
/*! ks3_ukwk - Key wrapping key
 */
#define CSS_CSS_KS3_ks3_ukwk(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_ukwk_SHIFT)) & CSS_CSS_KS3_ks3_ukwk_MASK)

#define CSS_CSS_KS3_ks3_ukuok_MASK               (0x800000U)
#define CSS_CSS_KS3_ks3_ukuok_SHIFT              (23U)
/*! ks3_ukuok - Key unwrapping key
 */
#define CSS_CSS_KS3_ks3_ukuok(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_ukuok_SHIFT)) & CSS_CSS_KS3_ks3_ukuok_MASK)

#define CSS_CSS_KS3_ks3_utlspms_MASK             (0x1000000U)
#define CSS_CSS_KS3_ks3_utlspms_SHIFT            (24U)
/*! ks3_utlspms - TLS Pre Master Secret
 */
#define CSS_CSS_KS3_ks3_utlspms(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_utlspms_SHIFT)) & CSS_CSS_KS3_ks3_utlspms_MASK)

#define CSS_CSS_KS3_ks3_utlsms_MASK              (0x2000000U)
#define CSS_CSS_KS3_ks3_utlsms_SHIFT             (25U)
/*! ks3_utlsms - TLS Master Secret
 */
#define CSS_CSS_KS3_ks3_utlsms(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_utlsms_SHIFT)) & CSS_CSS_KS3_ks3_utlsms_MASK)

#define CSS_CSS_KS3_ks3_ukgsrc_MASK              (0x4000000U)
#define CSS_CSS_KS3_ks3_ukgsrc_SHIFT             (26U)
/*! ks3_ukgsrc - Supply KEYGEN source
 */
#define CSS_CSS_KS3_ks3_ukgsrc(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_ukgsrc_SHIFT)) & CSS_CSS_KS3_ks3_ukgsrc_MASK)

#define CSS_CSS_KS3_ks3_uhwo_MASK                (0x8000000U)
#define CSS_CSS_KS3_ks3_uhwo_SHIFT               (27U)
/*! ks3_uhwo - Hardware out key
 */
#define CSS_CSS_KS3_ks3_uhwo(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_uhwo_SHIFT)) & CSS_CSS_KS3_ks3_uhwo_MASK)

#define CSS_CSS_KS3_ks3_uwrpok_MASK              (0x10000000U)
#define CSS_CSS_KS3_ks3_uwrpok_SHIFT             (28U)
/*! ks3_uwrpok - Ok to wrap key
 */
#define CSS_CSS_KS3_ks3_uwrpok(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_uwrpok_SHIFT)) & CSS_CSS_KS3_ks3_uwrpok_MASK)

#define CSS_CSS_KS3_ks3_uduk_MASK                (0x20000000U)
#define CSS_CSS_KS3_ks3_uduk_SHIFT               (29U)
/*! ks3_uduk - Device Unique Key
 */
#define CSS_CSS_KS3_ks3_uduk(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_uduk_SHIFT)) & CSS_CSS_KS3_ks3_uduk_MASK)

#define CSS_CSS_KS3_ks3_upprot_MASK              (0xC0000000U)
#define CSS_CSS_KS3_ks3_upprot_SHIFT             (30U)
/*! ks3_upprot - Priviledge level
 */
#define CSS_CSS_KS3_ks3_upprot(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS3_ks3_upprot_SHIFT)) & CSS_CSS_KS3_ks3_upprot_MASK)
/*! @} */

/*! @name CSS_KS4 - Status register */
/*! @{ */

#define CSS_CSS_KS4_ks4_ksize_MASK               (0x1U)
#define CSS_CSS_KS4_ks4_ksize_SHIFT              (0U)
/*! ks4_ksize - Key size: 0-128, 1-256
 */
#define CSS_CSS_KS4_ks4_ksize(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_ksize_SHIFT)) & CSS_CSS_KS4_ks4_ksize_MASK)

#define CSS_CSS_KS4_ks4_rsvd0_MASK               (0x1EU)
#define CSS_CSS_KS4_ks4_rsvd0_SHIFT              (1U)
/*! ks4_rsvd0 - Reserved 0
 */
#define CSS_CSS_KS4_ks4_rsvd0(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_rsvd0_SHIFT)) & CSS_CSS_KS4_ks4_rsvd0_MASK)

#define CSS_CSS_KS4_ks4_kact_MASK                (0x20U)
#define CSS_CSS_KS4_ks4_kact_SHIFT               (5U)
/*! ks4_kact - Key is active
 */
#define CSS_CSS_KS4_ks4_kact(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_kact_SHIFT)) & CSS_CSS_KS4_ks4_kact_MASK)

#define CSS_CSS_KS4_ks4_kbase_MASK               (0x40U)
#define CSS_CSS_KS4_ks4_kbase_SHIFT              (6U)
/*! ks4_kbase - First slot in a multislot key
 */
#define CSS_CSS_KS4_ks4_kbase(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_kbase_SHIFT)) & CSS_CSS_KS4_ks4_kbase_MASK)

#define CSS_CSS_KS4_ks4_fgp_MASK                 (0x80U)
#define CSS_CSS_KS4_ks4_fgp_SHIFT                (7U)
/*! ks4_fgp - Hardware Feature General Purpose
 */
#define CSS_CSS_KS4_ks4_fgp(x)                   (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_fgp_SHIFT)) & CSS_CSS_KS4_ks4_fgp_MASK)

#define CSS_CSS_KS4_ks4_frtn_MASK                (0x100U)
#define CSS_CSS_KS4_ks4_frtn_SHIFT               (8U)
/*! ks4_frtn - Hardware Feature Retention
 */
#define CSS_CSS_KS4_ks4_frtn(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_frtn_SHIFT)) & CSS_CSS_KS4_ks4_frtn_MASK)

#define CSS_CSS_KS4_ks4_fhwo_MASK                (0x200U)
#define CSS_CSS_KS4_ks4_fhwo_SHIFT               (9U)
/*! ks4_fhwo - Hardware Feature Output
 */
#define CSS_CSS_KS4_ks4_fhwo(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_fhwo_SHIFT)) & CSS_CSS_KS4_ks4_fhwo_MASK)

#define CSS_CSS_KS4_ks4_rsvd1_MASK               (0x1C00U)
#define CSS_CSS_KS4_ks4_rsvd1_SHIFT              (10U)
/*! ks4_rsvd1 - Reserved 1
 */
#define CSS_CSS_KS4_ks4_rsvd1(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_rsvd1_SHIFT)) & CSS_CSS_KS4_ks4_rsvd1_MASK)

#define CSS_CSS_KS4_ks4_ucmac_MASK               (0x2000U)
#define CSS_CSS_KS4_ks4_ucmac_SHIFT              (13U)
/*! ks4_ucmac - CMAC key
 */
#define CSS_CSS_KS4_ks4_ucmac(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_ucmac_SHIFT)) & CSS_CSS_KS4_ks4_ucmac_MASK)

#define CSS_CSS_KS4_ks4_uksk_MASK                (0x4000U)
#define CSS_CSS_KS4_ks4_uksk_SHIFT               (14U)
/*! ks4_uksk - KSK key
 */
#define CSS_CSS_KS4_ks4_uksk(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_uksk_SHIFT)) & CSS_CSS_KS4_ks4_uksk_MASK)

#define CSS_CSS_KS4_ks4_urtf_MASK                (0x8000U)
#define CSS_CSS_KS4_ks4_urtf_SHIFT               (15U)
/*! ks4_urtf - Real Time Fingerprint key
 */
#define CSS_CSS_KS4_ks4_urtf(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_urtf_SHIFT)) & CSS_CSS_KS4_ks4_urtf_MASK)

#define CSS_CSS_KS4_ks4_uckdf_MASK               (0x10000U)
#define CSS_CSS_KS4_ks4_uckdf_SHIFT              (16U)
/*! ks4_uckdf - Derivation key for CKDF command
 */
#define CSS_CSS_KS4_ks4_uckdf(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_uckdf_SHIFT)) & CSS_CSS_KS4_ks4_uckdf_MASK)

#define CSS_CSS_KS4_ks4_uhkdf_MASK               (0x20000U)
#define CSS_CSS_KS4_ks4_uhkdf_SHIFT              (17U)
/*! ks4_uhkdf - Derivation key for HKDF command
 */
#define CSS_CSS_KS4_ks4_uhkdf(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_uhkdf_SHIFT)) & CSS_CSS_KS4_ks4_uhkdf_MASK)

#define CSS_CSS_KS4_ks4_uecsg_MASK               (0x40000U)
#define CSS_CSS_KS4_ks4_uecsg_SHIFT              (18U)
/*! ks4_uecsg - Ecc signing key
 */
#define CSS_CSS_KS4_ks4_uecsg(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_uecsg_SHIFT)) & CSS_CSS_KS4_ks4_uecsg_MASK)

#define CSS_CSS_KS4_ks4_uecdh_MASK               (0x80000U)
#define CSS_CSS_KS4_ks4_uecdh_SHIFT              (19U)
/*! ks4_uecdh - Ecc diffie hellman key
 */
#define CSS_CSS_KS4_ks4_uecdh(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_uecdh_SHIFT)) & CSS_CSS_KS4_ks4_uecdh_MASK)

#define CSS_CSS_KS4_ks4_uaes_MASK                (0x100000U)
#define CSS_CSS_KS4_ks4_uaes_SHIFT               (20U)
/*! ks4_uaes - Aes key
 */
#define CSS_CSS_KS4_ks4_uaes(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_uaes_SHIFT)) & CSS_CSS_KS4_ks4_uaes_MASK)

#define CSS_CSS_KS4_ks4_uhmac_MASK               (0x200000U)
#define CSS_CSS_KS4_ks4_uhmac_SHIFT              (21U)
/*! ks4_uhmac - Hmac key
 */
#define CSS_CSS_KS4_ks4_uhmac(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_uhmac_SHIFT)) & CSS_CSS_KS4_ks4_uhmac_MASK)

#define CSS_CSS_KS4_ks4_ukwk_MASK                (0x400000U)
#define CSS_CSS_KS4_ks4_ukwk_SHIFT               (22U)
/*! ks4_ukwk - Key wrapping key
 */
#define CSS_CSS_KS4_ks4_ukwk(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_ukwk_SHIFT)) & CSS_CSS_KS4_ks4_ukwk_MASK)

#define CSS_CSS_KS4_ks4_ukuok_MASK               (0x800000U)
#define CSS_CSS_KS4_ks4_ukuok_SHIFT              (23U)
/*! ks4_ukuok - Key unwrapping key
 */
#define CSS_CSS_KS4_ks4_ukuok(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_ukuok_SHIFT)) & CSS_CSS_KS4_ks4_ukuok_MASK)

#define CSS_CSS_KS4_ks4_utlspms_MASK             (0x1000000U)
#define CSS_CSS_KS4_ks4_utlspms_SHIFT            (24U)
/*! ks4_utlspms - TLS Pre Master Secret
 */
#define CSS_CSS_KS4_ks4_utlspms(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_utlspms_SHIFT)) & CSS_CSS_KS4_ks4_utlspms_MASK)

#define CSS_CSS_KS4_ks4_utlsms_MASK              (0x2000000U)
#define CSS_CSS_KS4_ks4_utlsms_SHIFT             (25U)
/*! ks4_utlsms - TLS Master Secret
 */
#define CSS_CSS_KS4_ks4_utlsms(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_utlsms_SHIFT)) & CSS_CSS_KS4_ks4_utlsms_MASK)

#define CSS_CSS_KS4_ks4_ukgsrc_MASK              (0x4000000U)
#define CSS_CSS_KS4_ks4_ukgsrc_SHIFT             (26U)
/*! ks4_ukgsrc - Supply KEYGEN source
 */
#define CSS_CSS_KS4_ks4_ukgsrc(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_ukgsrc_SHIFT)) & CSS_CSS_KS4_ks4_ukgsrc_MASK)

#define CSS_CSS_KS4_ks4_uhwo_MASK                (0x8000000U)
#define CSS_CSS_KS4_ks4_uhwo_SHIFT               (27U)
/*! ks4_uhwo - Hardware out key
 */
#define CSS_CSS_KS4_ks4_uhwo(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_uhwo_SHIFT)) & CSS_CSS_KS4_ks4_uhwo_MASK)

#define CSS_CSS_KS4_ks4_uwrpok_MASK              (0x10000000U)
#define CSS_CSS_KS4_ks4_uwrpok_SHIFT             (28U)
/*! ks4_uwrpok - Ok to wrap key
 */
#define CSS_CSS_KS4_ks4_uwrpok(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_uwrpok_SHIFT)) & CSS_CSS_KS4_ks4_uwrpok_MASK)

#define CSS_CSS_KS4_ks4_uduk_MASK                (0x20000000U)
#define CSS_CSS_KS4_ks4_uduk_SHIFT               (29U)
/*! ks4_uduk - Device Unique Key
 */
#define CSS_CSS_KS4_ks4_uduk(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_uduk_SHIFT)) & CSS_CSS_KS4_ks4_uduk_MASK)

#define CSS_CSS_KS4_ks4_upprot_MASK              (0xC0000000U)
#define CSS_CSS_KS4_ks4_upprot_SHIFT             (30U)
/*! ks4_upprot - Priviledge level
 */
#define CSS_CSS_KS4_ks4_upprot(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS4_ks4_upprot_SHIFT)) & CSS_CSS_KS4_ks4_upprot_MASK)
/*! @} */

/*! @name CSS_KS5 - Status register */
/*! @{ */

#define CSS_CSS_KS5_ks5_ksize_MASK               (0x1U)
#define CSS_CSS_KS5_ks5_ksize_SHIFT              (0U)
/*! ks5_ksize - Key size: 0-128, 1-256
 */
#define CSS_CSS_KS5_ks5_ksize(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_ksize_SHIFT)) & CSS_CSS_KS5_ks5_ksize_MASK)

#define CSS_CSS_KS5_ks5_rsvd0_MASK               (0x1EU)
#define CSS_CSS_KS5_ks5_rsvd0_SHIFT              (1U)
/*! ks5_rsvd0 - Reserved 0
 */
#define CSS_CSS_KS5_ks5_rsvd0(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_rsvd0_SHIFT)) & CSS_CSS_KS5_ks5_rsvd0_MASK)

#define CSS_CSS_KS5_ks5_kact_MASK                (0x20U)
#define CSS_CSS_KS5_ks5_kact_SHIFT               (5U)
/*! ks5_kact - Key is active
 */
#define CSS_CSS_KS5_ks5_kact(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_kact_SHIFT)) & CSS_CSS_KS5_ks5_kact_MASK)

#define CSS_CSS_KS5_ks5_kbase_MASK               (0x40U)
#define CSS_CSS_KS5_ks5_kbase_SHIFT              (6U)
/*! ks5_kbase - First slot in a multislot key
 */
#define CSS_CSS_KS5_ks5_kbase(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_kbase_SHIFT)) & CSS_CSS_KS5_ks5_kbase_MASK)

#define CSS_CSS_KS5_ks5_fgp_MASK                 (0x80U)
#define CSS_CSS_KS5_ks5_fgp_SHIFT                (7U)
/*! ks5_fgp - Hardware Feature General Purpose
 */
#define CSS_CSS_KS5_ks5_fgp(x)                   (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_fgp_SHIFT)) & CSS_CSS_KS5_ks5_fgp_MASK)

#define CSS_CSS_KS5_ks5_frtn_MASK                (0x100U)
#define CSS_CSS_KS5_ks5_frtn_SHIFT               (8U)
/*! ks5_frtn - Hardware Feature Retention
 */
#define CSS_CSS_KS5_ks5_frtn(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_frtn_SHIFT)) & CSS_CSS_KS5_ks5_frtn_MASK)

#define CSS_CSS_KS5_ks5_fhwo_MASK                (0x200U)
#define CSS_CSS_KS5_ks5_fhwo_SHIFT               (9U)
/*! ks5_fhwo - Hardware Feature Output
 */
#define CSS_CSS_KS5_ks5_fhwo(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_fhwo_SHIFT)) & CSS_CSS_KS5_ks5_fhwo_MASK)

#define CSS_CSS_KS5_ks5_rsvd1_MASK               (0x1C00U)
#define CSS_CSS_KS5_ks5_rsvd1_SHIFT              (10U)
/*! ks5_rsvd1 - Reserved 1
 */
#define CSS_CSS_KS5_ks5_rsvd1(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_rsvd1_SHIFT)) & CSS_CSS_KS5_ks5_rsvd1_MASK)

#define CSS_CSS_KS5_ks5_ucmac_MASK               (0x2000U)
#define CSS_CSS_KS5_ks5_ucmac_SHIFT              (13U)
/*! ks5_ucmac - CMAC key
 */
#define CSS_CSS_KS5_ks5_ucmac(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_ucmac_SHIFT)) & CSS_CSS_KS5_ks5_ucmac_MASK)

#define CSS_CSS_KS5_ks5_uksk_MASK                (0x4000U)
#define CSS_CSS_KS5_ks5_uksk_SHIFT               (14U)
/*! ks5_uksk - KSK key
 */
#define CSS_CSS_KS5_ks5_uksk(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_uksk_SHIFT)) & CSS_CSS_KS5_ks5_uksk_MASK)

#define CSS_CSS_KS5_ks5_urtf_MASK                (0x8000U)
#define CSS_CSS_KS5_ks5_urtf_SHIFT               (15U)
/*! ks5_urtf - Real Time Fingerprint key
 */
#define CSS_CSS_KS5_ks5_urtf(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_urtf_SHIFT)) & CSS_CSS_KS5_ks5_urtf_MASK)

#define CSS_CSS_KS5_ks5_uckdf_MASK               (0x10000U)
#define CSS_CSS_KS5_ks5_uckdf_SHIFT              (16U)
/*! ks5_uckdf - Derivation key for CKDF command
 */
#define CSS_CSS_KS5_ks5_uckdf(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_uckdf_SHIFT)) & CSS_CSS_KS5_ks5_uckdf_MASK)

#define CSS_CSS_KS5_ks5_uhkdf_MASK               (0x20000U)
#define CSS_CSS_KS5_ks5_uhkdf_SHIFT              (17U)
/*! ks5_uhkdf - Derivation key for HKDF command
 */
#define CSS_CSS_KS5_ks5_uhkdf(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_uhkdf_SHIFT)) & CSS_CSS_KS5_ks5_uhkdf_MASK)

#define CSS_CSS_KS5_ks5_uecsg_MASK               (0x40000U)
#define CSS_CSS_KS5_ks5_uecsg_SHIFT              (18U)
/*! ks5_uecsg - Ecc signing key
 */
#define CSS_CSS_KS5_ks5_uecsg(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_uecsg_SHIFT)) & CSS_CSS_KS5_ks5_uecsg_MASK)

#define CSS_CSS_KS5_ks5_uecdh_MASK               (0x80000U)
#define CSS_CSS_KS5_ks5_uecdh_SHIFT              (19U)
/*! ks5_uecdh - Ecc diffie hellman key
 */
#define CSS_CSS_KS5_ks5_uecdh(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_uecdh_SHIFT)) & CSS_CSS_KS5_ks5_uecdh_MASK)

#define CSS_CSS_KS5_ks5_uaes_MASK                (0x100000U)
#define CSS_CSS_KS5_ks5_uaes_SHIFT               (20U)
/*! ks5_uaes - Aes key
 */
#define CSS_CSS_KS5_ks5_uaes(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_uaes_SHIFT)) & CSS_CSS_KS5_ks5_uaes_MASK)

#define CSS_CSS_KS5_ks5_uhmac_MASK               (0x200000U)
#define CSS_CSS_KS5_ks5_uhmac_SHIFT              (21U)
/*! ks5_uhmac - Hmac key
 */
#define CSS_CSS_KS5_ks5_uhmac(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_uhmac_SHIFT)) & CSS_CSS_KS5_ks5_uhmac_MASK)

#define CSS_CSS_KS5_ks5_ukwk_MASK                (0x400000U)
#define CSS_CSS_KS5_ks5_ukwk_SHIFT               (22U)
/*! ks5_ukwk - Key wrapping key
 */
#define CSS_CSS_KS5_ks5_ukwk(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_ukwk_SHIFT)) & CSS_CSS_KS5_ks5_ukwk_MASK)

#define CSS_CSS_KS5_ks5_ukuok_MASK               (0x800000U)
#define CSS_CSS_KS5_ks5_ukuok_SHIFT              (23U)
/*! ks5_ukuok - Key unwrapping key
 */
#define CSS_CSS_KS5_ks5_ukuok(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_ukuok_SHIFT)) & CSS_CSS_KS5_ks5_ukuok_MASK)

#define CSS_CSS_KS5_ks5_utlspms_MASK             (0x1000000U)
#define CSS_CSS_KS5_ks5_utlspms_SHIFT            (24U)
/*! ks5_utlspms - TLS Pre Master Secret
 */
#define CSS_CSS_KS5_ks5_utlspms(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_utlspms_SHIFT)) & CSS_CSS_KS5_ks5_utlspms_MASK)

#define CSS_CSS_KS5_ks5_utlsms_MASK              (0x2000000U)
#define CSS_CSS_KS5_ks5_utlsms_SHIFT             (25U)
/*! ks5_utlsms - TLS Master Secret
 */
#define CSS_CSS_KS5_ks5_utlsms(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_utlsms_SHIFT)) & CSS_CSS_KS5_ks5_utlsms_MASK)

#define CSS_CSS_KS5_ks5_ukgsrc_MASK              (0x4000000U)
#define CSS_CSS_KS5_ks5_ukgsrc_SHIFT             (26U)
/*! ks5_ukgsrc - Supply KEYGEN source
 */
#define CSS_CSS_KS5_ks5_ukgsrc(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_ukgsrc_SHIFT)) & CSS_CSS_KS5_ks5_ukgsrc_MASK)

#define CSS_CSS_KS5_ks5_uhwo_MASK                (0x8000000U)
#define CSS_CSS_KS5_ks5_uhwo_SHIFT               (27U)
/*! ks5_uhwo - Hardware out key
 */
#define CSS_CSS_KS5_ks5_uhwo(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_uhwo_SHIFT)) & CSS_CSS_KS5_ks5_uhwo_MASK)

#define CSS_CSS_KS5_ks5_uwrpok_MASK              (0x10000000U)
#define CSS_CSS_KS5_ks5_uwrpok_SHIFT             (28U)
/*! ks5_uwrpok - Ok to wrap key
 */
#define CSS_CSS_KS5_ks5_uwrpok(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_uwrpok_SHIFT)) & CSS_CSS_KS5_ks5_uwrpok_MASK)

#define CSS_CSS_KS5_ks5_uduk_MASK                (0x20000000U)
#define CSS_CSS_KS5_ks5_uduk_SHIFT               (29U)
/*! ks5_uduk - Device Unique Key
 */
#define CSS_CSS_KS5_ks5_uduk(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_uduk_SHIFT)) & CSS_CSS_KS5_ks5_uduk_MASK)

#define CSS_CSS_KS5_ks5_upprot_MASK              (0xC0000000U)
#define CSS_CSS_KS5_ks5_upprot_SHIFT             (30U)
/*! ks5_upprot - Priviledge level
 */
#define CSS_CSS_KS5_ks5_upprot(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS5_ks5_upprot_SHIFT)) & CSS_CSS_KS5_ks5_upprot_MASK)
/*! @} */

/*! @name CSS_KS6 - Status register */
/*! @{ */

#define CSS_CSS_KS6_ks6_ksize_MASK               (0x1U)
#define CSS_CSS_KS6_ks6_ksize_SHIFT              (0U)
/*! ks6_ksize - Key size: 0-128, 1-256
 */
#define CSS_CSS_KS6_ks6_ksize(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_ksize_SHIFT)) & CSS_CSS_KS6_ks6_ksize_MASK)

#define CSS_CSS_KS6_ks6_rsvd0_MASK               (0x1EU)
#define CSS_CSS_KS6_ks6_rsvd0_SHIFT              (1U)
/*! ks6_rsvd0 - Reserved 0
 */
#define CSS_CSS_KS6_ks6_rsvd0(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_rsvd0_SHIFT)) & CSS_CSS_KS6_ks6_rsvd0_MASK)

#define CSS_CSS_KS6_ks6_kact_MASK                (0x20U)
#define CSS_CSS_KS6_ks6_kact_SHIFT               (5U)
/*! ks6_kact - Key is active
 */
#define CSS_CSS_KS6_ks6_kact(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_kact_SHIFT)) & CSS_CSS_KS6_ks6_kact_MASK)

#define CSS_CSS_KS6_ks6_kbase_MASK               (0x40U)
#define CSS_CSS_KS6_ks6_kbase_SHIFT              (6U)
/*! ks6_kbase - First slot in a multislot key
 */
#define CSS_CSS_KS6_ks6_kbase(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_kbase_SHIFT)) & CSS_CSS_KS6_ks6_kbase_MASK)

#define CSS_CSS_KS6_ks6_fgp_MASK                 (0x80U)
#define CSS_CSS_KS6_ks6_fgp_SHIFT                (7U)
/*! ks6_fgp - Hardware Feature General Purpose
 */
#define CSS_CSS_KS6_ks6_fgp(x)                   (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_fgp_SHIFT)) & CSS_CSS_KS6_ks6_fgp_MASK)

#define CSS_CSS_KS6_ks6_frtn_MASK                (0x100U)
#define CSS_CSS_KS6_ks6_frtn_SHIFT               (8U)
/*! ks6_frtn - Hardware Feature Retention
 */
#define CSS_CSS_KS6_ks6_frtn(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_frtn_SHIFT)) & CSS_CSS_KS6_ks6_frtn_MASK)

#define CSS_CSS_KS6_ks6_fhwo_MASK                (0x200U)
#define CSS_CSS_KS6_ks6_fhwo_SHIFT               (9U)
/*! ks6_fhwo - Hardware Feature Output
 */
#define CSS_CSS_KS6_ks6_fhwo(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_fhwo_SHIFT)) & CSS_CSS_KS6_ks6_fhwo_MASK)

#define CSS_CSS_KS6_ks6_rsvd1_MASK               (0x1C00U)
#define CSS_CSS_KS6_ks6_rsvd1_SHIFT              (10U)
/*! ks6_rsvd1 - Reserved 1
 */
#define CSS_CSS_KS6_ks6_rsvd1(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_rsvd1_SHIFT)) & CSS_CSS_KS6_ks6_rsvd1_MASK)

#define CSS_CSS_KS6_ks6_ucmac_MASK               (0x2000U)
#define CSS_CSS_KS6_ks6_ucmac_SHIFT              (13U)
/*! ks6_ucmac - CMAC key
 */
#define CSS_CSS_KS6_ks6_ucmac(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_ucmac_SHIFT)) & CSS_CSS_KS6_ks6_ucmac_MASK)

#define CSS_CSS_KS6_ks6_uksk_MASK                (0x4000U)
#define CSS_CSS_KS6_ks6_uksk_SHIFT               (14U)
/*! ks6_uksk - KSK key
 */
#define CSS_CSS_KS6_ks6_uksk(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_uksk_SHIFT)) & CSS_CSS_KS6_ks6_uksk_MASK)

#define CSS_CSS_KS6_ks6_urtf_MASK                (0x8000U)
#define CSS_CSS_KS6_ks6_urtf_SHIFT               (15U)
/*! ks6_urtf - Real Time Fingerprint key
 */
#define CSS_CSS_KS6_ks6_urtf(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_urtf_SHIFT)) & CSS_CSS_KS6_ks6_urtf_MASK)

#define CSS_CSS_KS6_ks6_uckdf_MASK               (0x10000U)
#define CSS_CSS_KS6_ks6_uckdf_SHIFT              (16U)
/*! ks6_uckdf - Derivation key for CKDF command
 */
#define CSS_CSS_KS6_ks6_uckdf(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_uckdf_SHIFT)) & CSS_CSS_KS6_ks6_uckdf_MASK)

#define CSS_CSS_KS6_ks6_uhkdf_MASK               (0x20000U)
#define CSS_CSS_KS6_ks6_uhkdf_SHIFT              (17U)
/*! ks6_uhkdf - Derivation key for HKDF command
 */
#define CSS_CSS_KS6_ks6_uhkdf(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_uhkdf_SHIFT)) & CSS_CSS_KS6_ks6_uhkdf_MASK)

#define CSS_CSS_KS6_ks6_uecsg_MASK               (0x40000U)
#define CSS_CSS_KS6_ks6_uecsg_SHIFT              (18U)
/*! ks6_uecsg - Ecc signing key
 */
#define CSS_CSS_KS6_ks6_uecsg(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_uecsg_SHIFT)) & CSS_CSS_KS6_ks6_uecsg_MASK)

#define CSS_CSS_KS6_ks6_uecdh_MASK               (0x80000U)
#define CSS_CSS_KS6_ks6_uecdh_SHIFT              (19U)
/*! ks6_uecdh - Ecc diffie hellman key
 */
#define CSS_CSS_KS6_ks6_uecdh(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_uecdh_SHIFT)) & CSS_CSS_KS6_ks6_uecdh_MASK)

#define CSS_CSS_KS6_ks6_uaes_MASK                (0x100000U)
#define CSS_CSS_KS6_ks6_uaes_SHIFT               (20U)
/*! ks6_uaes - Aes key
 */
#define CSS_CSS_KS6_ks6_uaes(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_uaes_SHIFT)) & CSS_CSS_KS6_ks6_uaes_MASK)

#define CSS_CSS_KS6_ks6_uhmac_MASK               (0x200000U)
#define CSS_CSS_KS6_ks6_uhmac_SHIFT              (21U)
/*! ks6_uhmac - Hmac key
 */
#define CSS_CSS_KS6_ks6_uhmac(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_uhmac_SHIFT)) & CSS_CSS_KS6_ks6_uhmac_MASK)

#define CSS_CSS_KS6_ks6_ukwk_MASK                (0x400000U)
#define CSS_CSS_KS6_ks6_ukwk_SHIFT               (22U)
/*! ks6_ukwk - Key wrapping key
 */
#define CSS_CSS_KS6_ks6_ukwk(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_ukwk_SHIFT)) & CSS_CSS_KS6_ks6_ukwk_MASK)

#define CSS_CSS_KS6_ks6_ukuok_MASK               (0x800000U)
#define CSS_CSS_KS6_ks6_ukuok_SHIFT              (23U)
/*! ks6_ukuok - Key unwrapping key
 */
#define CSS_CSS_KS6_ks6_ukuok(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_ukuok_SHIFT)) & CSS_CSS_KS6_ks6_ukuok_MASK)

#define CSS_CSS_KS6_ks6_utlspms_MASK             (0x1000000U)
#define CSS_CSS_KS6_ks6_utlspms_SHIFT            (24U)
/*! ks6_utlspms - TLS Pre Master Secret
 */
#define CSS_CSS_KS6_ks6_utlspms(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_utlspms_SHIFT)) & CSS_CSS_KS6_ks6_utlspms_MASK)

#define CSS_CSS_KS6_ks6_utlsms_MASK              (0x2000000U)
#define CSS_CSS_KS6_ks6_utlsms_SHIFT             (25U)
/*! ks6_utlsms - TLS Master Secret
 */
#define CSS_CSS_KS6_ks6_utlsms(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_utlsms_SHIFT)) & CSS_CSS_KS6_ks6_utlsms_MASK)

#define CSS_CSS_KS6_ks6_ukgsrc_MASK              (0x4000000U)
#define CSS_CSS_KS6_ks6_ukgsrc_SHIFT             (26U)
/*! ks6_ukgsrc - Supply KEYGEN source
 */
#define CSS_CSS_KS6_ks6_ukgsrc(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_ukgsrc_SHIFT)) & CSS_CSS_KS6_ks6_ukgsrc_MASK)

#define CSS_CSS_KS6_ks6_uhwo_MASK                (0x8000000U)
#define CSS_CSS_KS6_ks6_uhwo_SHIFT               (27U)
/*! ks6_uhwo - Hardware out key
 */
#define CSS_CSS_KS6_ks6_uhwo(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_uhwo_SHIFT)) & CSS_CSS_KS6_ks6_uhwo_MASK)

#define CSS_CSS_KS6_ks6_uwrpok_MASK              (0x10000000U)
#define CSS_CSS_KS6_ks6_uwrpok_SHIFT             (28U)
/*! ks6_uwrpok - Ok to wrap key
 */
#define CSS_CSS_KS6_ks6_uwrpok(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_uwrpok_SHIFT)) & CSS_CSS_KS6_ks6_uwrpok_MASK)

#define CSS_CSS_KS6_ks6_uduk_MASK                (0x20000000U)
#define CSS_CSS_KS6_ks6_uduk_SHIFT               (29U)
/*! ks6_uduk - Device Unique Key
 */
#define CSS_CSS_KS6_ks6_uduk(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_uduk_SHIFT)) & CSS_CSS_KS6_ks6_uduk_MASK)

#define CSS_CSS_KS6_ks6_upprot_MASK              (0xC0000000U)
#define CSS_CSS_KS6_ks6_upprot_SHIFT             (30U)
/*! ks6_upprot - Priviledge level
 */
#define CSS_CSS_KS6_ks6_upprot(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS6_ks6_upprot_SHIFT)) & CSS_CSS_KS6_ks6_upprot_MASK)
/*! @} */

/*! @name CSS_KS7 - Status register */
/*! @{ */

#define CSS_CSS_KS7_ks7_ksize_MASK               (0x1U)
#define CSS_CSS_KS7_ks7_ksize_SHIFT              (0U)
/*! ks7_ksize - Key size: 0-128, 1-256
 */
#define CSS_CSS_KS7_ks7_ksize(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_ksize_SHIFT)) & CSS_CSS_KS7_ks7_ksize_MASK)

#define CSS_CSS_KS7_ks7_rsvd0_MASK               (0x1EU)
#define CSS_CSS_KS7_ks7_rsvd0_SHIFT              (1U)
/*! ks7_rsvd0 - Reserved 0
 */
#define CSS_CSS_KS7_ks7_rsvd0(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_rsvd0_SHIFT)) & CSS_CSS_KS7_ks7_rsvd0_MASK)

#define CSS_CSS_KS7_ks7_kact_MASK                (0x20U)
#define CSS_CSS_KS7_ks7_kact_SHIFT               (5U)
/*! ks7_kact - Key is active
 */
#define CSS_CSS_KS7_ks7_kact(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_kact_SHIFT)) & CSS_CSS_KS7_ks7_kact_MASK)

#define CSS_CSS_KS7_ks7_kbase_MASK               (0x40U)
#define CSS_CSS_KS7_ks7_kbase_SHIFT              (6U)
/*! ks7_kbase - First slot in a multislot key
 */
#define CSS_CSS_KS7_ks7_kbase(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_kbase_SHIFT)) & CSS_CSS_KS7_ks7_kbase_MASK)

#define CSS_CSS_KS7_ks7_fgp_MASK                 (0x80U)
#define CSS_CSS_KS7_ks7_fgp_SHIFT                (7U)
/*! ks7_fgp - Hardware Feature General Purpose
 */
#define CSS_CSS_KS7_ks7_fgp(x)                   (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_fgp_SHIFT)) & CSS_CSS_KS7_ks7_fgp_MASK)

#define CSS_CSS_KS7_ks7_frtn_MASK                (0x100U)
#define CSS_CSS_KS7_ks7_frtn_SHIFT               (8U)
/*! ks7_frtn - Hardware Feature Retention
 */
#define CSS_CSS_KS7_ks7_frtn(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_frtn_SHIFT)) & CSS_CSS_KS7_ks7_frtn_MASK)

#define CSS_CSS_KS7_ks7_fhwo_MASK                (0x200U)
#define CSS_CSS_KS7_ks7_fhwo_SHIFT               (9U)
/*! ks7_fhwo - Hardware Feature Output
 */
#define CSS_CSS_KS7_ks7_fhwo(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_fhwo_SHIFT)) & CSS_CSS_KS7_ks7_fhwo_MASK)

#define CSS_CSS_KS7_ks7_rsvd1_MASK               (0x1C00U)
#define CSS_CSS_KS7_ks7_rsvd1_SHIFT              (10U)
/*! ks7_rsvd1 - Reserved 1
 */
#define CSS_CSS_KS7_ks7_rsvd1(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_rsvd1_SHIFT)) & CSS_CSS_KS7_ks7_rsvd1_MASK)

#define CSS_CSS_KS7_ks7_ucmac_MASK               (0x2000U)
#define CSS_CSS_KS7_ks7_ucmac_SHIFT              (13U)
/*! ks7_ucmac - CMAC key
 */
#define CSS_CSS_KS7_ks7_ucmac(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_ucmac_SHIFT)) & CSS_CSS_KS7_ks7_ucmac_MASK)

#define CSS_CSS_KS7_ks7_uksk_MASK                (0x4000U)
#define CSS_CSS_KS7_ks7_uksk_SHIFT               (14U)
/*! ks7_uksk - KSK key
 */
#define CSS_CSS_KS7_ks7_uksk(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_uksk_SHIFT)) & CSS_CSS_KS7_ks7_uksk_MASK)

#define CSS_CSS_KS7_ks7_urtf_MASK                (0x8000U)
#define CSS_CSS_KS7_ks7_urtf_SHIFT               (15U)
/*! ks7_urtf - Real Time Fingerprint key
 */
#define CSS_CSS_KS7_ks7_urtf(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_urtf_SHIFT)) & CSS_CSS_KS7_ks7_urtf_MASK)

#define CSS_CSS_KS7_ks7_uckdf_MASK               (0x10000U)
#define CSS_CSS_KS7_ks7_uckdf_SHIFT              (16U)
/*! ks7_uckdf - Derivation key for CKDF command
 */
#define CSS_CSS_KS7_ks7_uckdf(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_uckdf_SHIFT)) & CSS_CSS_KS7_ks7_uckdf_MASK)

#define CSS_CSS_KS7_ks7_uhkdf_MASK               (0x20000U)
#define CSS_CSS_KS7_ks7_uhkdf_SHIFT              (17U)
/*! ks7_uhkdf - Derivation key for HKDF command
 */
#define CSS_CSS_KS7_ks7_uhkdf(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_uhkdf_SHIFT)) & CSS_CSS_KS7_ks7_uhkdf_MASK)

#define CSS_CSS_KS7_ks7_uecsg_MASK               (0x40000U)
#define CSS_CSS_KS7_ks7_uecsg_SHIFT              (18U)
/*! ks7_uecsg - Ecc signing key
 */
#define CSS_CSS_KS7_ks7_uecsg(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_uecsg_SHIFT)) & CSS_CSS_KS7_ks7_uecsg_MASK)

#define CSS_CSS_KS7_ks7_uecdh_MASK               (0x80000U)
#define CSS_CSS_KS7_ks7_uecdh_SHIFT              (19U)
/*! ks7_uecdh - Ecc diffie hellman key
 */
#define CSS_CSS_KS7_ks7_uecdh(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_uecdh_SHIFT)) & CSS_CSS_KS7_ks7_uecdh_MASK)

#define CSS_CSS_KS7_ks7_uaes_MASK                (0x100000U)
#define CSS_CSS_KS7_ks7_uaes_SHIFT               (20U)
/*! ks7_uaes - Aes key
 */
#define CSS_CSS_KS7_ks7_uaes(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_uaes_SHIFT)) & CSS_CSS_KS7_ks7_uaes_MASK)

#define CSS_CSS_KS7_ks7_uhmac_MASK               (0x200000U)
#define CSS_CSS_KS7_ks7_uhmac_SHIFT              (21U)
/*! ks7_uhmac - Hmac key
 */
#define CSS_CSS_KS7_ks7_uhmac(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_uhmac_SHIFT)) & CSS_CSS_KS7_ks7_uhmac_MASK)

#define CSS_CSS_KS7_ks7_ukwk_MASK                (0x400000U)
#define CSS_CSS_KS7_ks7_ukwk_SHIFT               (22U)
/*! ks7_ukwk - Key wrapping key
 */
#define CSS_CSS_KS7_ks7_ukwk(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_ukwk_SHIFT)) & CSS_CSS_KS7_ks7_ukwk_MASK)

#define CSS_CSS_KS7_ks7_ukuok_MASK               (0x800000U)
#define CSS_CSS_KS7_ks7_ukuok_SHIFT              (23U)
/*! ks7_ukuok - Key unwrapping key
 */
#define CSS_CSS_KS7_ks7_ukuok(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_ukuok_SHIFT)) & CSS_CSS_KS7_ks7_ukuok_MASK)

#define CSS_CSS_KS7_ks7_utlspms_MASK             (0x1000000U)
#define CSS_CSS_KS7_ks7_utlspms_SHIFT            (24U)
/*! ks7_utlspms - TLS Pre Master Secret
 */
#define CSS_CSS_KS7_ks7_utlspms(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_utlspms_SHIFT)) & CSS_CSS_KS7_ks7_utlspms_MASK)

#define CSS_CSS_KS7_ks7_utlsms_MASK              (0x2000000U)
#define CSS_CSS_KS7_ks7_utlsms_SHIFT             (25U)
/*! ks7_utlsms - TLS Master Secret
 */
#define CSS_CSS_KS7_ks7_utlsms(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_utlsms_SHIFT)) & CSS_CSS_KS7_ks7_utlsms_MASK)

#define CSS_CSS_KS7_ks7_ukgsrc_MASK              (0x4000000U)
#define CSS_CSS_KS7_ks7_ukgsrc_SHIFT             (26U)
/*! ks7_ukgsrc - Supply KEYGEN source
 */
#define CSS_CSS_KS7_ks7_ukgsrc(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_ukgsrc_SHIFT)) & CSS_CSS_KS7_ks7_ukgsrc_MASK)

#define CSS_CSS_KS7_ks7_uhwo_MASK                (0x8000000U)
#define CSS_CSS_KS7_ks7_uhwo_SHIFT               (27U)
/*! ks7_uhwo - Hardware out key
 */
#define CSS_CSS_KS7_ks7_uhwo(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_uhwo_SHIFT)) & CSS_CSS_KS7_ks7_uhwo_MASK)

#define CSS_CSS_KS7_ks7_uwrpok_MASK              (0x10000000U)
#define CSS_CSS_KS7_ks7_uwrpok_SHIFT             (28U)
/*! ks7_uwrpok - Ok to wrap key
 */
#define CSS_CSS_KS7_ks7_uwrpok(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_uwrpok_SHIFT)) & CSS_CSS_KS7_ks7_uwrpok_MASK)

#define CSS_CSS_KS7_ks7_uduk_MASK                (0x20000000U)
#define CSS_CSS_KS7_ks7_uduk_SHIFT               (29U)
/*! ks7_uduk - Device Unique Key
 */
#define CSS_CSS_KS7_ks7_uduk(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_uduk_SHIFT)) & CSS_CSS_KS7_ks7_uduk_MASK)

#define CSS_CSS_KS7_ks7_upprot_MASK              (0xC0000000U)
#define CSS_CSS_KS7_ks7_upprot_SHIFT             (30U)
/*! ks7_upprot - Priviledge level
 */
#define CSS_CSS_KS7_ks7_upprot(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS7_ks7_upprot_SHIFT)) & CSS_CSS_KS7_ks7_upprot_MASK)
/*! @} */

/*! @name CSS_KS8 - Status register */
/*! @{ */

#define CSS_CSS_KS8_ks8_ksize_MASK               (0x1U)
#define CSS_CSS_KS8_ks8_ksize_SHIFT              (0U)
/*! ks8_ksize - Key size: 0-128, 1-256
 */
#define CSS_CSS_KS8_ks8_ksize(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_ksize_SHIFT)) & CSS_CSS_KS8_ks8_ksize_MASK)

#define CSS_CSS_KS8_ks8_rsvd0_MASK               (0x1EU)
#define CSS_CSS_KS8_ks8_rsvd0_SHIFT              (1U)
/*! ks8_rsvd0 - Reserved 0
 */
#define CSS_CSS_KS8_ks8_rsvd0(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_rsvd0_SHIFT)) & CSS_CSS_KS8_ks8_rsvd0_MASK)

#define CSS_CSS_KS8_ks8_kact_MASK                (0x20U)
#define CSS_CSS_KS8_ks8_kact_SHIFT               (5U)
/*! ks8_kact - Key is active
 */
#define CSS_CSS_KS8_ks8_kact(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_kact_SHIFT)) & CSS_CSS_KS8_ks8_kact_MASK)

#define CSS_CSS_KS8_ks8_kbase_MASK               (0x40U)
#define CSS_CSS_KS8_ks8_kbase_SHIFT              (6U)
/*! ks8_kbase - First slot in a multislot key
 */
#define CSS_CSS_KS8_ks8_kbase(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_kbase_SHIFT)) & CSS_CSS_KS8_ks8_kbase_MASK)

#define CSS_CSS_KS8_ks8_fgp_MASK                 (0x80U)
#define CSS_CSS_KS8_ks8_fgp_SHIFT                (7U)
/*! ks8_fgp - Hardware Feature General Purpose
 */
#define CSS_CSS_KS8_ks8_fgp(x)                   (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_fgp_SHIFT)) & CSS_CSS_KS8_ks8_fgp_MASK)

#define CSS_CSS_KS8_ks8_frtn_MASK                (0x100U)
#define CSS_CSS_KS8_ks8_frtn_SHIFT               (8U)
/*! ks8_frtn - Hardware Feature Retention
 */
#define CSS_CSS_KS8_ks8_frtn(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_frtn_SHIFT)) & CSS_CSS_KS8_ks8_frtn_MASK)

#define CSS_CSS_KS8_ks8_fhwo_MASK                (0x200U)
#define CSS_CSS_KS8_ks8_fhwo_SHIFT               (9U)
/*! ks8_fhwo - Hardware Feature Output
 */
#define CSS_CSS_KS8_ks8_fhwo(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_fhwo_SHIFT)) & CSS_CSS_KS8_ks8_fhwo_MASK)

#define CSS_CSS_KS8_ks8_rsvd1_MASK               (0x1C00U)
#define CSS_CSS_KS8_ks8_rsvd1_SHIFT              (10U)
/*! ks8_rsvd1 - Reserved 1
 */
#define CSS_CSS_KS8_ks8_rsvd1(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_rsvd1_SHIFT)) & CSS_CSS_KS8_ks8_rsvd1_MASK)

#define CSS_CSS_KS8_ks8_ucmac_MASK               (0x2000U)
#define CSS_CSS_KS8_ks8_ucmac_SHIFT              (13U)
/*! ks8_ucmac - CMAC key
 */
#define CSS_CSS_KS8_ks8_ucmac(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_ucmac_SHIFT)) & CSS_CSS_KS8_ks8_ucmac_MASK)

#define CSS_CSS_KS8_ks8_uksk_MASK                (0x4000U)
#define CSS_CSS_KS8_ks8_uksk_SHIFT               (14U)
/*! ks8_uksk - KSK key
 */
#define CSS_CSS_KS8_ks8_uksk(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_uksk_SHIFT)) & CSS_CSS_KS8_ks8_uksk_MASK)

#define CSS_CSS_KS8_ks8_urtf_MASK                (0x8000U)
#define CSS_CSS_KS8_ks8_urtf_SHIFT               (15U)
/*! ks8_urtf - Real Time Fingerprint key
 */
#define CSS_CSS_KS8_ks8_urtf(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_urtf_SHIFT)) & CSS_CSS_KS8_ks8_urtf_MASK)

#define CSS_CSS_KS8_ks8_uckdf_MASK               (0x10000U)
#define CSS_CSS_KS8_ks8_uckdf_SHIFT              (16U)
/*! ks8_uckdf - Derivation key for CKDF command
 */
#define CSS_CSS_KS8_ks8_uckdf(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_uckdf_SHIFT)) & CSS_CSS_KS8_ks8_uckdf_MASK)

#define CSS_CSS_KS8_ks8_uhkdf_MASK               (0x20000U)
#define CSS_CSS_KS8_ks8_uhkdf_SHIFT              (17U)
/*! ks8_uhkdf - Derivation key for HKDF command
 */
#define CSS_CSS_KS8_ks8_uhkdf(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_uhkdf_SHIFT)) & CSS_CSS_KS8_ks8_uhkdf_MASK)

#define CSS_CSS_KS8_ks8_uecsg_MASK               (0x40000U)
#define CSS_CSS_KS8_ks8_uecsg_SHIFT              (18U)
/*! ks8_uecsg - Ecc signing key
 */
#define CSS_CSS_KS8_ks8_uecsg(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_uecsg_SHIFT)) & CSS_CSS_KS8_ks8_uecsg_MASK)

#define CSS_CSS_KS8_ks8_uecdh_MASK               (0x80000U)
#define CSS_CSS_KS8_ks8_uecdh_SHIFT              (19U)
/*! ks8_uecdh - Ecc diffie hellman key
 */
#define CSS_CSS_KS8_ks8_uecdh(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_uecdh_SHIFT)) & CSS_CSS_KS8_ks8_uecdh_MASK)

#define CSS_CSS_KS8_ks8_uaes_MASK                (0x100000U)
#define CSS_CSS_KS8_ks8_uaes_SHIFT               (20U)
/*! ks8_uaes - Aes key
 */
#define CSS_CSS_KS8_ks8_uaes(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_uaes_SHIFT)) & CSS_CSS_KS8_ks8_uaes_MASK)

#define CSS_CSS_KS8_ks8_uhmac_MASK               (0x200000U)
#define CSS_CSS_KS8_ks8_uhmac_SHIFT              (21U)
/*! ks8_uhmac - Hmac key
 */
#define CSS_CSS_KS8_ks8_uhmac(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_uhmac_SHIFT)) & CSS_CSS_KS8_ks8_uhmac_MASK)

#define CSS_CSS_KS8_ks8_ukwk_MASK                (0x400000U)
#define CSS_CSS_KS8_ks8_ukwk_SHIFT               (22U)
/*! ks8_ukwk - Key wrapping key
 */
#define CSS_CSS_KS8_ks8_ukwk(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_ukwk_SHIFT)) & CSS_CSS_KS8_ks8_ukwk_MASK)

#define CSS_CSS_KS8_ks8_ukuok_MASK               (0x800000U)
#define CSS_CSS_KS8_ks8_ukuok_SHIFT              (23U)
/*! ks8_ukuok - Key unwrapping key
 */
#define CSS_CSS_KS8_ks8_ukuok(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_ukuok_SHIFT)) & CSS_CSS_KS8_ks8_ukuok_MASK)

#define CSS_CSS_KS8_ks8_utlspms_MASK             (0x1000000U)
#define CSS_CSS_KS8_ks8_utlspms_SHIFT            (24U)
/*! ks8_utlspms - TLS Pre Master Secret
 */
#define CSS_CSS_KS8_ks8_utlspms(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_utlspms_SHIFT)) & CSS_CSS_KS8_ks8_utlspms_MASK)

#define CSS_CSS_KS8_ks8_utlsms_MASK              (0x2000000U)
#define CSS_CSS_KS8_ks8_utlsms_SHIFT             (25U)
/*! ks8_utlsms - TLS Master Secret
 */
#define CSS_CSS_KS8_ks8_utlsms(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_utlsms_SHIFT)) & CSS_CSS_KS8_ks8_utlsms_MASK)

#define CSS_CSS_KS8_ks8_ukgsrc_MASK              (0x4000000U)
#define CSS_CSS_KS8_ks8_ukgsrc_SHIFT             (26U)
/*! ks8_ukgsrc - Supply KEYGEN source
 */
#define CSS_CSS_KS8_ks8_ukgsrc(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_ukgsrc_SHIFT)) & CSS_CSS_KS8_ks8_ukgsrc_MASK)

#define CSS_CSS_KS8_ks8_uhwo_MASK                (0x8000000U)
#define CSS_CSS_KS8_ks8_uhwo_SHIFT               (27U)
/*! ks8_uhwo - Hardware out key
 */
#define CSS_CSS_KS8_ks8_uhwo(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_uhwo_SHIFT)) & CSS_CSS_KS8_ks8_uhwo_MASK)

#define CSS_CSS_KS8_ks8_uwrpok_MASK              (0x10000000U)
#define CSS_CSS_KS8_ks8_uwrpok_SHIFT             (28U)
/*! ks8_uwrpok - Ok to wrap key
 */
#define CSS_CSS_KS8_ks8_uwrpok(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_uwrpok_SHIFT)) & CSS_CSS_KS8_ks8_uwrpok_MASK)

#define CSS_CSS_KS8_ks8_uduk_MASK                (0x20000000U)
#define CSS_CSS_KS8_ks8_uduk_SHIFT               (29U)
/*! ks8_uduk - Device Unique Key
 */
#define CSS_CSS_KS8_ks8_uduk(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_uduk_SHIFT)) & CSS_CSS_KS8_ks8_uduk_MASK)

#define CSS_CSS_KS8_ks8_upprot_MASK              (0xC0000000U)
#define CSS_CSS_KS8_ks8_upprot_SHIFT             (30U)
/*! ks8_upprot - Priviledge level
 */
#define CSS_CSS_KS8_ks8_upprot(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS8_ks8_upprot_SHIFT)) & CSS_CSS_KS8_ks8_upprot_MASK)
/*! @} */

/*! @name CSS_KS9 - Status register */
/*! @{ */

#define CSS_CSS_KS9_ks9_ksize_MASK               (0x1U)
#define CSS_CSS_KS9_ks9_ksize_SHIFT              (0U)
/*! ks9_ksize - Key size: 0-128, 1-256
 */
#define CSS_CSS_KS9_ks9_ksize(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_ksize_SHIFT)) & CSS_CSS_KS9_ks9_ksize_MASK)

#define CSS_CSS_KS9_ks9_rsvd0_MASK               (0x1EU)
#define CSS_CSS_KS9_ks9_rsvd0_SHIFT              (1U)
/*! ks9_rsvd0 - Reserved 0
 */
#define CSS_CSS_KS9_ks9_rsvd0(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_rsvd0_SHIFT)) & CSS_CSS_KS9_ks9_rsvd0_MASK)

#define CSS_CSS_KS9_ks9_kact_MASK                (0x20U)
#define CSS_CSS_KS9_ks9_kact_SHIFT               (5U)
/*! ks9_kact - Key is active
 */
#define CSS_CSS_KS9_ks9_kact(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_kact_SHIFT)) & CSS_CSS_KS9_ks9_kact_MASK)

#define CSS_CSS_KS9_ks9_kbase_MASK               (0x40U)
#define CSS_CSS_KS9_ks9_kbase_SHIFT              (6U)
/*! ks9_kbase - First slot in a multislot key
 */
#define CSS_CSS_KS9_ks9_kbase(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_kbase_SHIFT)) & CSS_CSS_KS9_ks9_kbase_MASK)

#define CSS_CSS_KS9_ks9_fgp_MASK                 (0x80U)
#define CSS_CSS_KS9_ks9_fgp_SHIFT                (7U)
/*! ks9_fgp - Hardware Feature General Purpose
 */
#define CSS_CSS_KS9_ks9_fgp(x)                   (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_fgp_SHIFT)) & CSS_CSS_KS9_ks9_fgp_MASK)

#define CSS_CSS_KS9_ks9_frtn_MASK                (0x100U)
#define CSS_CSS_KS9_ks9_frtn_SHIFT               (8U)
/*! ks9_frtn - Hardware Feature Retention
 */
#define CSS_CSS_KS9_ks9_frtn(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_frtn_SHIFT)) & CSS_CSS_KS9_ks9_frtn_MASK)

#define CSS_CSS_KS9_ks9_fhwo_MASK                (0x200U)
#define CSS_CSS_KS9_ks9_fhwo_SHIFT               (9U)
/*! ks9_fhwo - Hardware Feature Output
 */
#define CSS_CSS_KS9_ks9_fhwo(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_fhwo_SHIFT)) & CSS_CSS_KS9_ks9_fhwo_MASK)

#define CSS_CSS_KS9_ks9_rsvd1_MASK               (0x1C00U)
#define CSS_CSS_KS9_ks9_rsvd1_SHIFT              (10U)
/*! ks9_rsvd1 - Reserved 1
 */
#define CSS_CSS_KS9_ks9_rsvd1(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_rsvd1_SHIFT)) & CSS_CSS_KS9_ks9_rsvd1_MASK)

#define CSS_CSS_KS9_ks9_ucmac_MASK               (0x2000U)
#define CSS_CSS_KS9_ks9_ucmac_SHIFT              (13U)
/*! ks9_ucmac - CMAC key
 */
#define CSS_CSS_KS9_ks9_ucmac(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_ucmac_SHIFT)) & CSS_CSS_KS9_ks9_ucmac_MASK)

#define CSS_CSS_KS9_ks9_uksk_MASK                (0x4000U)
#define CSS_CSS_KS9_ks9_uksk_SHIFT               (14U)
/*! ks9_uksk - KSK key
 */
#define CSS_CSS_KS9_ks9_uksk(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_uksk_SHIFT)) & CSS_CSS_KS9_ks9_uksk_MASK)

#define CSS_CSS_KS9_ks9_urtf_MASK                (0x8000U)
#define CSS_CSS_KS9_ks9_urtf_SHIFT               (15U)
/*! ks9_urtf - Real Time Fingerprint key
 */
#define CSS_CSS_KS9_ks9_urtf(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_urtf_SHIFT)) & CSS_CSS_KS9_ks9_urtf_MASK)

#define CSS_CSS_KS9_ks9_uckdf_MASK               (0x10000U)
#define CSS_CSS_KS9_ks9_uckdf_SHIFT              (16U)
/*! ks9_uckdf - Derivation key for CKDF command
 */
#define CSS_CSS_KS9_ks9_uckdf(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_uckdf_SHIFT)) & CSS_CSS_KS9_ks9_uckdf_MASK)

#define CSS_CSS_KS9_ks9_uhkdf_MASK               (0x20000U)
#define CSS_CSS_KS9_ks9_uhkdf_SHIFT              (17U)
/*! ks9_uhkdf - Derivation key for HKDF command
 */
#define CSS_CSS_KS9_ks9_uhkdf(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_uhkdf_SHIFT)) & CSS_CSS_KS9_ks9_uhkdf_MASK)

#define CSS_CSS_KS9_ks9_uecsg_MASK               (0x40000U)
#define CSS_CSS_KS9_ks9_uecsg_SHIFT              (18U)
/*! ks9_uecsg - Ecc signing key
 */
#define CSS_CSS_KS9_ks9_uecsg(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_uecsg_SHIFT)) & CSS_CSS_KS9_ks9_uecsg_MASK)

#define CSS_CSS_KS9_ks9_uecdh_MASK               (0x80000U)
#define CSS_CSS_KS9_ks9_uecdh_SHIFT              (19U)
/*! ks9_uecdh - Ecc diffie hellman key
 */
#define CSS_CSS_KS9_ks9_uecdh(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_uecdh_SHIFT)) & CSS_CSS_KS9_ks9_uecdh_MASK)

#define CSS_CSS_KS9_ks9_uaes_MASK                (0x100000U)
#define CSS_CSS_KS9_ks9_uaes_SHIFT               (20U)
/*! ks9_uaes - Aes key
 */
#define CSS_CSS_KS9_ks9_uaes(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_uaes_SHIFT)) & CSS_CSS_KS9_ks9_uaes_MASK)

#define CSS_CSS_KS9_ks9_uhmac_MASK               (0x200000U)
#define CSS_CSS_KS9_ks9_uhmac_SHIFT              (21U)
/*! ks9_uhmac - Hmac key
 */
#define CSS_CSS_KS9_ks9_uhmac(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_uhmac_SHIFT)) & CSS_CSS_KS9_ks9_uhmac_MASK)

#define CSS_CSS_KS9_ks9_ukwk_MASK                (0x400000U)
#define CSS_CSS_KS9_ks9_ukwk_SHIFT               (22U)
/*! ks9_ukwk - Key wrapping key
 */
#define CSS_CSS_KS9_ks9_ukwk(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_ukwk_SHIFT)) & CSS_CSS_KS9_ks9_ukwk_MASK)

#define CSS_CSS_KS9_ks9_ukuok_MASK               (0x800000U)
#define CSS_CSS_KS9_ks9_ukuok_SHIFT              (23U)
/*! ks9_ukuok - Key unwrapping key
 */
#define CSS_CSS_KS9_ks9_ukuok(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_ukuok_SHIFT)) & CSS_CSS_KS9_ks9_ukuok_MASK)

#define CSS_CSS_KS9_ks9_utlspms_MASK             (0x1000000U)
#define CSS_CSS_KS9_ks9_utlspms_SHIFT            (24U)
/*! ks9_utlspms - TLS Pre Master Secret
 */
#define CSS_CSS_KS9_ks9_utlspms(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_utlspms_SHIFT)) & CSS_CSS_KS9_ks9_utlspms_MASK)

#define CSS_CSS_KS9_ks9_utlsms_MASK              (0x2000000U)
#define CSS_CSS_KS9_ks9_utlsms_SHIFT             (25U)
/*! ks9_utlsms - TLS Master Secret
 */
#define CSS_CSS_KS9_ks9_utlsms(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_utlsms_SHIFT)) & CSS_CSS_KS9_ks9_utlsms_MASK)

#define CSS_CSS_KS9_ks9_ukgsrc_MASK              (0x4000000U)
#define CSS_CSS_KS9_ks9_ukgsrc_SHIFT             (26U)
/*! ks9_ukgsrc - Supply KEYGEN source
 */
#define CSS_CSS_KS9_ks9_ukgsrc(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_ukgsrc_SHIFT)) & CSS_CSS_KS9_ks9_ukgsrc_MASK)

#define CSS_CSS_KS9_ks9_uhwo_MASK                (0x8000000U)
#define CSS_CSS_KS9_ks9_uhwo_SHIFT               (27U)
/*! ks9_uhwo - Hardware out key
 */
#define CSS_CSS_KS9_ks9_uhwo(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_uhwo_SHIFT)) & CSS_CSS_KS9_ks9_uhwo_MASK)

#define CSS_CSS_KS9_ks9_uwrpok_MASK              (0x10000000U)
#define CSS_CSS_KS9_ks9_uwrpok_SHIFT             (28U)
/*! ks9_uwrpok - Ok to wrap key
 */
#define CSS_CSS_KS9_ks9_uwrpok(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_uwrpok_SHIFT)) & CSS_CSS_KS9_ks9_uwrpok_MASK)

#define CSS_CSS_KS9_ks9_uduk_MASK                (0x20000000U)
#define CSS_CSS_KS9_ks9_uduk_SHIFT               (29U)
/*! ks9_uduk - Device Unique Key
 */
#define CSS_CSS_KS9_ks9_uduk(x)                  (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_uduk_SHIFT)) & CSS_CSS_KS9_ks9_uduk_MASK)

#define CSS_CSS_KS9_ks9_upprot_MASK              (0xC0000000U)
#define CSS_CSS_KS9_ks9_upprot_SHIFT             (30U)
/*! ks9_upprot - Priviledge level
 */
#define CSS_CSS_KS9_ks9_upprot(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS9_ks9_upprot_SHIFT)) & CSS_CSS_KS9_ks9_upprot_MASK)
/*! @} */

/*! @name CSS_KS10 - Status register */
/*! @{ */

#define CSS_CSS_KS10_ks10_ksize_MASK             (0x1U)
#define CSS_CSS_KS10_ks10_ksize_SHIFT            (0U)
/*! ks10_ksize - Key size: 0-128, 1-256
 */
#define CSS_CSS_KS10_ks10_ksize(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_ksize_SHIFT)) & CSS_CSS_KS10_ks10_ksize_MASK)

#define CSS_CSS_KS10_ks10_rsvd0_MASK             (0x1EU)
#define CSS_CSS_KS10_ks10_rsvd0_SHIFT            (1U)
/*! ks10_rsvd0 - Reserved 0
 */
#define CSS_CSS_KS10_ks10_rsvd0(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_rsvd0_SHIFT)) & CSS_CSS_KS10_ks10_rsvd0_MASK)

#define CSS_CSS_KS10_ks10_kact_MASK              (0x20U)
#define CSS_CSS_KS10_ks10_kact_SHIFT             (5U)
/*! ks10_kact - Key is active
 */
#define CSS_CSS_KS10_ks10_kact(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_kact_SHIFT)) & CSS_CSS_KS10_ks10_kact_MASK)

#define CSS_CSS_KS10_ks10_kbase_MASK             (0x40U)
#define CSS_CSS_KS10_ks10_kbase_SHIFT            (6U)
/*! ks10_kbase - First slot in a multislot key
 */
#define CSS_CSS_KS10_ks10_kbase(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_kbase_SHIFT)) & CSS_CSS_KS10_ks10_kbase_MASK)

#define CSS_CSS_KS10_ks10_fgp_MASK               (0x80U)
#define CSS_CSS_KS10_ks10_fgp_SHIFT              (7U)
/*! ks10_fgp - Hardware Feature General Purpose
 */
#define CSS_CSS_KS10_ks10_fgp(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_fgp_SHIFT)) & CSS_CSS_KS10_ks10_fgp_MASK)

#define CSS_CSS_KS10_ks10_frtn_MASK              (0x100U)
#define CSS_CSS_KS10_ks10_frtn_SHIFT             (8U)
/*! ks10_frtn - Hardware Feature Retention
 */
#define CSS_CSS_KS10_ks10_frtn(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_frtn_SHIFT)) & CSS_CSS_KS10_ks10_frtn_MASK)

#define CSS_CSS_KS10_ks10_fhwo_MASK              (0x200U)
#define CSS_CSS_KS10_ks10_fhwo_SHIFT             (9U)
/*! ks10_fhwo - Hardware Feature Output
 */
#define CSS_CSS_KS10_ks10_fhwo(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_fhwo_SHIFT)) & CSS_CSS_KS10_ks10_fhwo_MASK)

#define CSS_CSS_KS10_ks10_rsvd1_MASK             (0x1C00U)
#define CSS_CSS_KS10_ks10_rsvd1_SHIFT            (10U)
/*! ks10_rsvd1 - Reserved 1
 */
#define CSS_CSS_KS10_ks10_rsvd1(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_rsvd1_SHIFT)) & CSS_CSS_KS10_ks10_rsvd1_MASK)

#define CSS_CSS_KS10_ks10_ucmac_MASK             (0x2000U)
#define CSS_CSS_KS10_ks10_ucmac_SHIFT            (13U)
/*! ks10_ucmac - CMAC key
 */
#define CSS_CSS_KS10_ks10_ucmac(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_ucmac_SHIFT)) & CSS_CSS_KS10_ks10_ucmac_MASK)

#define CSS_CSS_KS10_ks10_uksk_MASK              (0x4000U)
#define CSS_CSS_KS10_ks10_uksk_SHIFT             (14U)
/*! ks10_uksk - KSK key
 */
#define CSS_CSS_KS10_ks10_uksk(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_uksk_SHIFT)) & CSS_CSS_KS10_ks10_uksk_MASK)

#define CSS_CSS_KS10_ks10_urtf_MASK              (0x8000U)
#define CSS_CSS_KS10_ks10_urtf_SHIFT             (15U)
/*! ks10_urtf - Real Time Fingerprint key
 */
#define CSS_CSS_KS10_ks10_urtf(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_urtf_SHIFT)) & CSS_CSS_KS10_ks10_urtf_MASK)

#define CSS_CSS_KS10_ks10_uckdf_MASK             (0x10000U)
#define CSS_CSS_KS10_ks10_uckdf_SHIFT            (16U)
/*! ks10_uckdf - Derivation key for CKDF command
 */
#define CSS_CSS_KS10_ks10_uckdf(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_uckdf_SHIFT)) & CSS_CSS_KS10_ks10_uckdf_MASK)

#define CSS_CSS_KS10_ks10_uhkdf_MASK             (0x20000U)
#define CSS_CSS_KS10_ks10_uhkdf_SHIFT            (17U)
/*! ks10_uhkdf - Derivation key for HKDF command
 */
#define CSS_CSS_KS10_ks10_uhkdf(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_uhkdf_SHIFT)) & CSS_CSS_KS10_ks10_uhkdf_MASK)

#define CSS_CSS_KS10_ks10_uecsg_MASK             (0x40000U)
#define CSS_CSS_KS10_ks10_uecsg_SHIFT            (18U)
/*! ks10_uecsg - Ecc signing key
 */
#define CSS_CSS_KS10_ks10_uecsg(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_uecsg_SHIFT)) & CSS_CSS_KS10_ks10_uecsg_MASK)

#define CSS_CSS_KS10_ks10_uecdh_MASK             (0x80000U)
#define CSS_CSS_KS10_ks10_uecdh_SHIFT            (19U)
/*! ks10_uecdh - Ecc diffie hellman key
 */
#define CSS_CSS_KS10_ks10_uecdh(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_uecdh_SHIFT)) & CSS_CSS_KS10_ks10_uecdh_MASK)

#define CSS_CSS_KS10_ks10_uaes_MASK              (0x100000U)
#define CSS_CSS_KS10_ks10_uaes_SHIFT             (20U)
/*! ks10_uaes - Aes key
 */
#define CSS_CSS_KS10_ks10_uaes(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_uaes_SHIFT)) & CSS_CSS_KS10_ks10_uaes_MASK)

#define CSS_CSS_KS10_ks10_uhmac_MASK             (0x200000U)
#define CSS_CSS_KS10_ks10_uhmac_SHIFT            (21U)
/*! ks10_uhmac - Hmac key
 */
#define CSS_CSS_KS10_ks10_uhmac(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_uhmac_SHIFT)) & CSS_CSS_KS10_ks10_uhmac_MASK)

#define CSS_CSS_KS10_ks10_ukwk_MASK              (0x400000U)
#define CSS_CSS_KS10_ks10_ukwk_SHIFT             (22U)
/*! ks10_ukwk - Key wrapping key
 */
#define CSS_CSS_KS10_ks10_ukwk(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_ukwk_SHIFT)) & CSS_CSS_KS10_ks10_ukwk_MASK)

#define CSS_CSS_KS10_ks10_ukuok_MASK             (0x800000U)
#define CSS_CSS_KS10_ks10_ukuok_SHIFT            (23U)
/*! ks10_ukuok - Key unwrapping key
 */
#define CSS_CSS_KS10_ks10_ukuok(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_ukuok_SHIFT)) & CSS_CSS_KS10_ks10_ukuok_MASK)

#define CSS_CSS_KS10_ks10_utlspms_MASK           (0x1000000U)
#define CSS_CSS_KS10_ks10_utlspms_SHIFT          (24U)
/*! ks10_utlspms - TLS Pre Master Secret
 */
#define CSS_CSS_KS10_ks10_utlspms(x)             (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_utlspms_SHIFT)) & CSS_CSS_KS10_ks10_utlspms_MASK)

#define CSS_CSS_KS10_ks10_utlsms_MASK            (0x2000000U)
#define CSS_CSS_KS10_ks10_utlsms_SHIFT           (25U)
/*! ks10_utlsms - TLS Master Secret
 */
#define CSS_CSS_KS10_ks10_utlsms(x)              (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_utlsms_SHIFT)) & CSS_CSS_KS10_ks10_utlsms_MASK)

#define CSS_CSS_KS10_ks10_ukgsrc_MASK            (0x4000000U)
#define CSS_CSS_KS10_ks10_ukgsrc_SHIFT           (26U)
/*! ks10_ukgsrc - Supply KEYGEN source
 */
#define CSS_CSS_KS10_ks10_ukgsrc(x)              (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_ukgsrc_SHIFT)) & CSS_CSS_KS10_ks10_ukgsrc_MASK)

#define CSS_CSS_KS10_ks10_uhwo_MASK              (0x8000000U)
#define CSS_CSS_KS10_ks10_uhwo_SHIFT             (27U)
/*! ks10_uhwo - Hardware out key
 */
#define CSS_CSS_KS10_ks10_uhwo(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_uhwo_SHIFT)) & CSS_CSS_KS10_ks10_uhwo_MASK)

#define CSS_CSS_KS10_ks10_uwrpok_MASK            (0x10000000U)
#define CSS_CSS_KS10_ks10_uwrpok_SHIFT           (28U)
/*! ks10_uwrpok - Ok to wrap key
 */
#define CSS_CSS_KS10_ks10_uwrpok(x)              (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_uwrpok_SHIFT)) & CSS_CSS_KS10_ks10_uwrpok_MASK)

#define CSS_CSS_KS10_ks10_uduk_MASK              (0x20000000U)
#define CSS_CSS_KS10_ks10_uduk_SHIFT             (29U)
/*! ks10_uduk - Device Unique Key
 */
#define CSS_CSS_KS10_ks10_uduk(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_uduk_SHIFT)) & CSS_CSS_KS10_ks10_uduk_MASK)

#define CSS_CSS_KS10_ks10_upprot_MASK            (0xC0000000U)
#define CSS_CSS_KS10_ks10_upprot_SHIFT           (30U)
/*! ks10_upprot - Priviledge level
 */
#define CSS_CSS_KS10_ks10_upprot(x)              (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS10_ks10_upprot_SHIFT)) & CSS_CSS_KS10_ks10_upprot_MASK)
/*! @} */

/*! @name CSS_KS11 - Status register */
/*! @{ */

#define CSS_CSS_KS11_ks11_ksize_MASK             (0x1U)
#define CSS_CSS_KS11_ks11_ksize_SHIFT            (0U)
/*! ks11_ksize - Key size: 0-128, 1-256
 */
#define CSS_CSS_KS11_ks11_ksize(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_ksize_SHIFT)) & CSS_CSS_KS11_ks11_ksize_MASK)

#define CSS_CSS_KS11_ks11_rsvd0_MASK             (0x1EU)
#define CSS_CSS_KS11_ks11_rsvd0_SHIFT            (1U)
/*! ks11_rsvd0 - Reserved 0
 */
#define CSS_CSS_KS11_ks11_rsvd0(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_rsvd0_SHIFT)) & CSS_CSS_KS11_ks11_rsvd0_MASK)

#define CSS_CSS_KS11_ks11_kact_MASK              (0x20U)
#define CSS_CSS_KS11_ks11_kact_SHIFT             (5U)
/*! ks11_kact - Key is active
 */
#define CSS_CSS_KS11_ks11_kact(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_kact_SHIFT)) & CSS_CSS_KS11_ks11_kact_MASK)

#define CSS_CSS_KS11_ks11_kbase_MASK             (0x40U)
#define CSS_CSS_KS11_ks11_kbase_SHIFT            (6U)
/*! ks11_kbase - First slot in a multislot key
 */
#define CSS_CSS_KS11_ks11_kbase(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_kbase_SHIFT)) & CSS_CSS_KS11_ks11_kbase_MASK)

#define CSS_CSS_KS11_ks11_fgp_MASK               (0x80U)
#define CSS_CSS_KS11_ks11_fgp_SHIFT              (7U)
/*! ks11_fgp - Hardware Feature General Purpose
 */
#define CSS_CSS_KS11_ks11_fgp(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_fgp_SHIFT)) & CSS_CSS_KS11_ks11_fgp_MASK)

#define CSS_CSS_KS11_ks11_frtn_MASK              (0x100U)
#define CSS_CSS_KS11_ks11_frtn_SHIFT             (8U)
/*! ks11_frtn - Hardware Feature Retention
 */
#define CSS_CSS_KS11_ks11_frtn(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_frtn_SHIFT)) & CSS_CSS_KS11_ks11_frtn_MASK)

#define CSS_CSS_KS11_ks11_fhwo_MASK              (0x200U)
#define CSS_CSS_KS11_ks11_fhwo_SHIFT             (9U)
/*! ks11_fhwo - Hardware Feature Output
 */
#define CSS_CSS_KS11_ks11_fhwo(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_fhwo_SHIFT)) & CSS_CSS_KS11_ks11_fhwo_MASK)

#define CSS_CSS_KS11_ks11_rsvd1_MASK             (0x1C00U)
#define CSS_CSS_KS11_ks11_rsvd1_SHIFT            (10U)
/*! ks11_rsvd1 - Reserved 1
 */
#define CSS_CSS_KS11_ks11_rsvd1(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_rsvd1_SHIFT)) & CSS_CSS_KS11_ks11_rsvd1_MASK)

#define CSS_CSS_KS11_ks11_ucmac_MASK             (0x2000U)
#define CSS_CSS_KS11_ks11_ucmac_SHIFT            (13U)
/*! ks11_ucmac - CMAC key
 */
#define CSS_CSS_KS11_ks11_ucmac(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_ucmac_SHIFT)) & CSS_CSS_KS11_ks11_ucmac_MASK)

#define CSS_CSS_KS11_ks11_uksk_MASK              (0x4000U)
#define CSS_CSS_KS11_ks11_uksk_SHIFT             (14U)
/*! ks11_uksk - KSK key
 */
#define CSS_CSS_KS11_ks11_uksk(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_uksk_SHIFT)) & CSS_CSS_KS11_ks11_uksk_MASK)

#define CSS_CSS_KS11_ks11_urtf_MASK              (0x8000U)
#define CSS_CSS_KS11_ks11_urtf_SHIFT             (15U)
/*! ks11_urtf - Real Time Fingerprint key
 */
#define CSS_CSS_KS11_ks11_urtf(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_urtf_SHIFT)) & CSS_CSS_KS11_ks11_urtf_MASK)

#define CSS_CSS_KS11_ks11_uckdf_MASK             (0x10000U)
#define CSS_CSS_KS11_ks11_uckdf_SHIFT            (16U)
/*! ks11_uckdf - Derivation key for CKDF command
 */
#define CSS_CSS_KS11_ks11_uckdf(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_uckdf_SHIFT)) & CSS_CSS_KS11_ks11_uckdf_MASK)

#define CSS_CSS_KS11_ks11_uhkdf_MASK             (0x20000U)
#define CSS_CSS_KS11_ks11_uhkdf_SHIFT            (17U)
/*! ks11_uhkdf - Derivation key for HKDF command
 */
#define CSS_CSS_KS11_ks11_uhkdf(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_uhkdf_SHIFT)) & CSS_CSS_KS11_ks11_uhkdf_MASK)

#define CSS_CSS_KS11_ks11_uecsg_MASK             (0x40000U)
#define CSS_CSS_KS11_ks11_uecsg_SHIFT            (18U)
/*! ks11_uecsg - Ecc signing key
 */
#define CSS_CSS_KS11_ks11_uecsg(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_uecsg_SHIFT)) & CSS_CSS_KS11_ks11_uecsg_MASK)

#define CSS_CSS_KS11_ks11_uecdh_MASK             (0x80000U)
#define CSS_CSS_KS11_ks11_uecdh_SHIFT            (19U)
/*! ks11_uecdh - Ecc diffie hellman key
 */
#define CSS_CSS_KS11_ks11_uecdh(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_uecdh_SHIFT)) & CSS_CSS_KS11_ks11_uecdh_MASK)

#define CSS_CSS_KS11_ks11_uaes_MASK              (0x100000U)
#define CSS_CSS_KS11_ks11_uaes_SHIFT             (20U)
/*! ks11_uaes - Aes key
 */
#define CSS_CSS_KS11_ks11_uaes(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_uaes_SHIFT)) & CSS_CSS_KS11_ks11_uaes_MASK)

#define CSS_CSS_KS11_ks11_uhmac_MASK             (0x200000U)
#define CSS_CSS_KS11_ks11_uhmac_SHIFT            (21U)
/*! ks11_uhmac - Hmac key
 */
#define CSS_CSS_KS11_ks11_uhmac(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_uhmac_SHIFT)) & CSS_CSS_KS11_ks11_uhmac_MASK)

#define CSS_CSS_KS11_ks11_ukwk_MASK              (0x400000U)
#define CSS_CSS_KS11_ks11_ukwk_SHIFT             (22U)
/*! ks11_ukwk - Key wrapping key
 */
#define CSS_CSS_KS11_ks11_ukwk(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_ukwk_SHIFT)) & CSS_CSS_KS11_ks11_ukwk_MASK)

#define CSS_CSS_KS11_ks11_ukuok_MASK             (0x800000U)
#define CSS_CSS_KS11_ks11_ukuok_SHIFT            (23U)
/*! ks11_ukuok - Key unwrapping key
 */
#define CSS_CSS_KS11_ks11_ukuok(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_ukuok_SHIFT)) & CSS_CSS_KS11_ks11_ukuok_MASK)

#define CSS_CSS_KS11_ks11_utlspms_MASK           (0x1000000U)
#define CSS_CSS_KS11_ks11_utlspms_SHIFT          (24U)
/*! ks11_utlspms - TLS Pre Master Secret
 */
#define CSS_CSS_KS11_ks11_utlspms(x)             (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_utlspms_SHIFT)) & CSS_CSS_KS11_ks11_utlspms_MASK)

#define CSS_CSS_KS11_ks11_utlsms_MASK            (0x2000000U)
#define CSS_CSS_KS11_ks11_utlsms_SHIFT           (25U)
/*! ks11_utlsms - TLS Master Secret
 */
#define CSS_CSS_KS11_ks11_utlsms(x)              (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_utlsms_SHIFT)) & CSS_CSS_KS11_ks11_utlsms_MASK)

#define CSS_CSS_KS11_ks11_ukgsrc_MASK            (0x4000000U)
#define CSS_CSS_KS11_ks11_ukgsrc_SHIFT           (26U)
/*! ks11_ukgsrc - Supply KEYGEN source
 */
#define CSS_CSS_KS11_ks11_ukgsrc(x)              (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_ukgsrc_SHIFT)) & CSS_CSS_KS11_ks11_ukgsrc_MASK)

#define CSS_CSS_KS11_ks11_uhwo_MASK              (0x8000000U)
#define CSS_CSS_KS11_ks11_uhwo_SHIFT             (27U)
/*! ks11_uhwo - Hardware out key
 */
#define CSS_CSS_KS11_ks11_uhwo(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_uhwo_SHIFT)) & CSS_CSS_KS11_ks11_uhwo_MASK)

#define CSS_CSS_KS11_ks11_uwrpok_MASK            (0x10000000U)
#define CSS_CSS_KS11_ks11_uwrpok_SHIFT           (28U)
/*! ks11_uwrpok - Ok to wrap key
 */
#define CSS_CSS_KS11_ks11_uwrpok(x)              (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_uwrpok_SHIFT)) & CSS_CSS_KS11_ks11_uwrpok_MASK)

#define CSS_CSS_KS11_ks11_uduk_MASK              (0x20000000U)
#define CSS_CSS_KS11_ks11_uduk_SHIFT             (29U)
/*! ks11_uduk - Device Unique Key
 */
#define CSS_CSS_KS11_ks11_uduk(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_uduk_SHIFT)) & CSS_CSS_KS11_ks11_uduk_MASK)

#define CSS_CSS_KS11_ks11_upprot_MASK            (0xC0000000U)
#define CSS_CSS_KS11_ks11_upprot_SHIFT           (30U)
/*! ks11_upprot - Priviledge level
 */
#define CSS_CSS_KS11_ks11_upprot(x)              (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS11_ks11_upprot_SHIFT)) & CSS_CSS_KS11_ks11_upprot_MASK)
/*! @} */

/*! @name CSS_KS12 - Status register */
/*! @{ */

#define CSS_CSS_KS12_ks12_ksize_MASK             (0x1U)
#define CSS_CSS_KS12_ks12_ksize_SHIFT            (0U)
/*! ks12_ksize - Key size: 0-128, 1-256
 */
#define CSS_CSS_KS12_ks12_ksize(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_ksize_SHIFT)) & CSS_CSS_KS12_ks12_ksize_MASK)

#define CSS_CSS_KS12_ks12_rsvd0_MASK             (0x1EU)
#define CSS_CSS_KS12_ks12_rsvd0_SHIFT            (1U)
/*! ks12_rsvd0 - Reserved 0
 */
#define CSS_CSS_KS12_ks12_rsvd0(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_rsvd0_SHIFT)) & CSS_CSS_KS12_ks12_rsvd0_MASK)

#define CSS_CSS_KS12_ks12_kact_MASK              (0x20U)
#define CSS_CSS_KS12_ks12_kact_SHIFT             (5U)
/*! ks12_kact - Key is active
 */
#define CSS_CSS_KS12_ks12_kact(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_kact_SHIFT)) & CSS_CSS_KS12_ks12_kact_MASK)

#define CSS_CSS_KS12_ks12_kbase_MASK             (0x40U)
#define CSS_CSS_KS12_ks12_kbase_SHIFT            (6U)
/*! ks12_kbase - First slot in a multislot key
 */
#define CSS_CSS_KS12_ks12_kbase(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_kbase_SHIFT)) & CSS_CSS_KS12_ks12_kbase_MASK)

#define CSS_CSS_KS12_ks12_fgp_MASK               (0x80U)
#define CSS_CSS_KS12_ks12_fgp_SHIFT              (7U)
/*! ks12_fgp - Hardware Feature General Purpose
 */
#define CSS_CSS_KS12_ks12_fgp(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_fgp_SHIFT)) & CSS_CSS_KS12_ks12_fgp_MASK)

#define CSS_CSS_KS12_ks12_frtn_MASK              (0x100U)
#define CSS_CSS_KS12_ks12_frtn_SHIFT             (8U)
/*! ks12_frtn - Hardware Feature Retention
 */
#define CSS_CSS_KS12_ks12_frtn(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_frtn_SHIFT)) & CSS_CSS_KS12_ks12_frtn_MASK)

#define CSS_CSS_KS12_ks12_fhwo_MASK              (0x200U)
#define CSS_CSS_KS12_ks12_fhwo_SHIFT             (9U)
/*! ks12_fhwo - Hardware Feature Output
 */
#define CSS_CSS_KS12_ks12_fhwo(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_fhwo_SHIFT)) & CSS_CSS_KS12_ks12_fhwo_MASK)

#define CSS_CSS_KS12_ks12_rsvd1_MASK             (0x1C00U)
#define CSS_CSS_KS12_ks12_rsvd1_SHIFT            (10U)
/*! ks12_rsvd1 - Reserved 1
 */
#define CSS_CSS_KS12_ks12_rsvd1(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_rsvd1_SHIFT)) & CSS_CSS_KS12_ks12_rsvd1_MASK)

#define CSS_CSS_KS12_ks12_ucmac_MASK             (0x2000U)
#define CSS_CSS_KS12_ks12_ucmac_SHIFT            (13U)
/*! ks12_ucmac - CMAC key
 */
#define CSS_CSS_KS12_ks12_ucmac(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_ucmac_SHIFT)) & CSS_CSS_KS12_ks12_ucmac_MASK)

#define CSS_CSS_KS12_ks12_uksk_MASK              (0x4000U)
#define CSS_CSS_KS12_ks12_uksk_SHIFT             (14U)
/*! ks12_uksk - KSK key
 */
#define CSS_CSS_KS12_ks12_uksk(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_uksk_SHIFT)) & CSS_CSS_KS12_ks12_uksk_MASK)

#define CSS_CSS_KS12_ks12_urtf_MASK              (0x8000U)
#define CSS_CSS_KS12_ks12_urtf_SHIFT             (15U)
/*! ks12_urtf - Real Time Fingerprint key
 */
#define CSS_CSS_KS12_ks12_urtf(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_urtf_SHIFT)) & CSS_CSS_KS12_ks12_urtf_MASK)

#define CSS_CSS_KS12_ks12_uckdf_MASK             (0x10000U)
#define CSS_CSS_KS12_ks12_uckdf_SHIFT            (16U)
/*! ks12_uckdf - Derivation key for CKDF command
 */
#define CSS_CSS_KS12_ks12_uckdf(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_uckdf_SHIFT)) & CSS_CSS_KS12_ks12_uckdf_MASK)

#define CSS_CSS_KS12_ks12_uhkdf_MASK             (0x20000U)
#define CSS_CSS_KS12_ks12_uhkdf_SHIFT            (17U)
/*! ks12_uhkdf - Derivation key for HKDF command
 */
#define CSS_CSS_KS12_ks12_uhkdf(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_uhkdf_SHIFT)) & CSS_CSS_KS12_ks12_uhkdf_MASK)

#define CSS_CSS_KS12_ks12_uecsg_MASK             (0x40000U)
#define CSS_CSS_KS12_ks12_uecsg_SHIFT            (18U)
/*! ks12_uecsg - Ecc signing key
 */
#define CSS_CSS_KS12_ks12_uecsg(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_uecsg_SHIFT)) & CSS_CSS_KS12_ks12_uecsg_MASK)

#define CSS_CSS_KS12_ks12_uecdh_MASK             (0x80000U)
#define CSS_CSS_KS12_ks12_uecdh_SHIFT            (19U)
/*! ks12_uecdh - Ecc diffie hellman key
 */
#define CSS_CSS_KS12_ks12_uecdh(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_uecdh_SHIFT)) & CSS_CSS_KS12_ks12_uecdh_MASK)

#define CSS_CSS_KS12_ks12_uaes_MASK              (0x100000U)
#define CSS_CSS_KS12_ks12_uaes_SHIFT             (20U)
/*! ks12_uaes - Aes key
 */
#define CSS_CSS_KS12_ks12_uaes(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_uaes_SHIFT)) & CSS_CSS_KS12_ks12_uaes_MASK)

#define CSS_CSS_KS12_ks12_uhmac_MASK             (0x200000U)
#define CSS_CSS_KS12_ks12_uhmac_SHIFT            (21U)
/*! ks12_uhmac - Hmac key
 */
#define CSS_CSS_KS12_ks12_uhmac(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_uhmac_SHIFT)) & CSS_CSS_KS12_ks12_uhmac_MASK)

#define CSS_CSS_KS12_ks12_ukwk_MASK              (0x400000U)
#define CSS_CSS_KS12_ks12_ukwk_SHIFT             (22U)
/*! ks12_ukwk - Key wrapping key
 */
#define CSS_CSS_KS12_ks12_ukwk(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_ukwk_SHIFT)) & CSS_CSS_KS12_ks12_ukwk_MASK)

#define CSS_CSS_KS12_ks12_ukuok_MASK             (0x800000U)
#define CSS_CSS_KS12_ks12_ukuok_SHIFT            (23U)
/*! ks12_ukuok - Key unwrapping key
 */
#define CSS_CSS_KS12_ks12_ukuok(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_ukuok_SHIFT)) & CSS_CSS_KS12_ks12_ukuok_MASK)

#define CSS_CSS_KS12_ks12_utlspms_MASK           (0x1000000U)
#define CSS_CSS_KS12_ks12_utlspms_SHIFT          (24U)
/*! ks12_utlspms - TLS Pre Master Secret
 */
#define CSS_CSS_KS12_ks12_utlspms(x)             (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_utlspms_SHIFT)) & CSS_CSS_KS12_ks12_utlspms_MASK)

#define CSS_CSS_KS12_ks12_utlsms_MASK            (0x2000000U)
#define CSS_CSS_KS12_ks12_utlsms_SHIFT           (25U)
/*! ks12_utlsms - TLS Master Secret
 */
#define CSS_CSS_KS12_ks12_utlsms(x)              (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_utlsms_SHIFT)) & CSS_CSS_KS12_ks12_utlsms_MASK)

#define CSS_CSS_KS12_ks12_ukgsrc_MASK            (0x4000000U)
#define CSS_CSS_KS12_ks12_ukgsrc_SHIFT           (26U)
/*! ks12_ukgsrc - Supply KEYGEN source
 */
#define CSS_CSS_KS12_ks12_ukgsrc(x)              (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_ukgsrc_SHIFT)) & CSS_CSS_KS12_ks12_ukgsrc_MASK)

#define CSS_CSS_KS12_ks12_uhwo_MASK              (0x8000000U)
#define CSS_CSS_KS12_ks12_uhwo_SHIFT             (27U)
/*! ks12_uhwo - Hardware out key
 */
#define CSS_CSS_KS12_ks12_uhwo(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_uhwo_SHIFT)) & CSS_CSS_KS12_ks12_uhwo_MASK)

#define CSS_CSS_KS12_ks12_uwrpok_MASK            (0x10000000U)
#define CSS_CSS_KS12_ks12_uwrpok_SHIFT           (28U)
/*! ks12_uwrpok - Ok to wrap key
 */
#define CSS_CSS_KS12_ks12_uwrpok(x)              (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_uwrpok_SHIFT)) & CSS_CSS_KS12_ks12_uwrpok_MASK)

#define CSS_CSS_KS12_ks12_uduk_MASK              (0x20000000U)
#define CSS_CSS_KS12_ks12_uduk_SHIFT             (29U)
/*! ks12_uduk - Device Unique Key
 */
#define CSS_CSS_KS12_ks12_uduk(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_uduk_SHIFT)) & CSS_CSS_KS12_ks12_uduk_MASK)

#define CSS_CSS_KS12_ks12_upprot_MASK            (0xC0000000U)
#define CSS_CSS_KS12_ks12_upprot_SHIFT           (30U)
/*! ks12_upprot - Priviledge level
 */
#define CSS_CSS_KS12_ks12_upprot(x)              (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS12_ks12_upprot_SHIFT)) & CSS_CSS_KS12_ks12_upprot_MASK)
/*! @} */

/*! @name CSS_KS13 - Status register */
/*! @{ */

#define CSS_CSS_KS13_ks13_ksize_MASK             (0x1U)
#define CSS_CSS_KS13_ks13_ksize_SHIFT            (0U)
/*! ks13_ksize - Key size: 0-128, 1-256
 */
#define CSS_CSS_KS13_ks13_ksize(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_ksize_SHIFT)) & CSS_CSS_KS13_ks13_ksize_MASK)

#define CSS_CSS_KS13_ks13_rsvd0_MASK             (0x1EU)
#define CSS_CSS_KS13_ks13_rsvd0_SHIFT            (1U)
/*! ks13_rsvd0 - Reserved 0
 */
#define CSS_CSS_KS13_ks13_rsvd0(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_rsvd0_SHIFT)) & CSS_CSS_KS13_ks13_rsvd0_MASK)

#define CSS_CSS_KS13_ks13_kact_MASK              (0x20U)
#define CSS_CSS_KS13_ks13_kact_SHIFT             (5U)
/*! ks13_kact - Key is active
 */
#define CSS_CSS_KS13_ks13_kact(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_kact_SHIFT)) & CSS_CSS_KS13_ks13_kact_MASK)

#define CSS_CSS_KS13_ks13_kbase_MASK             (0x40U)
#define CSS_CSS_KS13_ks13_kbase_SHIFT            (6U)
/*! ks13_kbase - First slot in a multislot key
 */
#define CSS_CSS_KS13_ks13_kbase(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_kbase_SHIFT)) & CSS_CSS_KS13_ks13_kbase_MASK)

#define CSS_CSS_KS13_ks13_fgp_MASK               (0x80U)
#define CSS_CSS_KS13_ks13_fgp_SHIFT              (7U)
/*! ks13_fgp - Hardware Feature General Purpose
 */
#define CSS_CSS_KS13_ks13_fgp(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_fgp_SHIFT)) & CSS_CSS_KS13_ks13_fgp_MASK)

#define CSS_CSS_KS13_ks13_frtn_MASK              (0x100U)
#define CSS_CSS_KS13_ks13_frtn_SHIFT             (8U)
/*! ks13_frtn - Hardware Feature Retention
 */
#define CSS_CSS_KS13_ks13_frtn(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_frtn_SHIFT)) & CSS_CSS_KS13_ks13_frtn_MASK)

#define CSS_CSS_KS13_ks13_fhwo_MASK              (0x200U)
#define CSS_CSS_KS13_ks13_fhwo_SHIFT             (9U)
/*! ks13_fhwo - Hardware Feature Output
 */
#define CSS_CSS_KS13_ks13_fhwo(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_fhwo_SHIFT)) & CSS_CSS_KS13_ks13_fhwo_MASK)

#define CSS_CSS_KS13_ks13_rsvd1_MASK             (0x1C00U)
#define CSS_CSS_KS13_ks13_rsvd1_SHIFT            (10U)
/*! ks13_rsvd1 - Reserved 1
 */
#define CSS_CSS_KS13_ks13_rsvd1(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_rsvd1_SHIFT)) & CSS_CSS_KS13_ks13_rsvd1_MASK)

#define CSS_CSS_KS13_ks13_ucmac_MASK             (0x2000U)
#define CSS_CSS_KS13_ks13_ucmac_SHIFT            (13U)
/*! ks13_ucmac - CMAC key
 */
#define CSS_CSS_KS13_ks13_ucmac(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_ucmac_SHIFT)) & CSS_CSS_KS13_ks13_ucmac_MASK)

#define CSS_CSS_KS13_ks13_uksk_MASK              (0x4000U)
#define CSS_CSS_KS13_ks13_uksk_SHIFT             (14U)
/*! ks13_uksk - KSK key
 */
#define CSS_CSS_KS13_ks13_uksk(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_uksk_SHIFT)) & CSS_CSS_KS13_ks13_uksk_MASK)

#define CSS_CSS_KS13_ks13_urtf_MASK              (0x8000U)
#define CSS_CSS_KS13_ks13_urtf_SHIFT             (15U)
/*! ks13_urtf - Real Time Fingerprint key
 */
#define CSS_CSS_KS13_ks13_urtf(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_urtf_SHIFT)) & CSS_CSS_KS13_ks13_urtf_MASK)

#define CSS_CSS_KS13_ks13_uckdf_MASK             (0x10000U)
#define CSS_CSS_KS13_ks13_uckdf_SHIFT            (16U)
/*! ks13_uckdf - Derivation key for CKDF command
 */
#define CSS_CSS_KS13_ks13_uckdf(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_uckdf_SHIFT)) & CSS_CSS_KS13_ks13_uckdf_MASK)

#define CSS_CSS_KS13_ks13_uhkdf_MASK             (0x20000U)
#define CSS_CSS_KS13_ks13_uhkdf_SHIFT            (17U)
/*! ks13_uhkdf - Derivation key for HKDF command
 */
#define CSS_CSS_KS13_ks13_uhkdf(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_uhkdf_SHIFT)) & CSS_CSS_KS13_ks13_uhkdf_MASK)

#define CSS_CSS_KS13_ks13_uecsg_MASK             (0x40000U)
#define CSS_CSS_KS13_ks13_uecsg_SHIFT            (18U)
/*! ks13_uecsg - Ecc signing key
 */
#define CSS_CSS_KS13_ks13_uecsg(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_uecsg_SHIFT)) & CSS_CSS_KS13_ks13_uecsg_MASK)

#define CSS_CSS_KS13_ks13_uecdh_MASK             (0x80000U)
#define CSS_CSS_KS13_ks13_uecdh_SHIFT            (19U)
/*! ks13_uecdh - Ecc diffie hellman key
 */
#define CSS_CSS_KS13_ks13_uecdh(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_uecdh_SHIFT)) & CSS_CSS_KS13_ks13_uecdh_MASK)

#define CSS_CSS_KS13_ks13_uaes_MASK              (0x100000U)
#define CSS_CSS_KS13_ks13_uaes_SHIFT             (20U)
/*! ks13_uaes - Aes key
 */
#define CSS_CSS_KS13_ks13_uaes(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_uaes_SHIFT)) & CSS_CSS_KS13_ks13_uaes_MASK)

#define CSS_CSS_KS13_ks13_uhmac_MASK             (0x200000U)
#define CSS_CSS_KS13_ks13_uhmac_SHIFT            (21U)
/*! ks13_uhmac - Hmac key
 */
#define CSS_CSS_KS13_ks13_uhmac(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_uhmac_SHIFT)) & CSS_CSS_KS13_ks13_uhmac_MASK)

#define CSS_CSS_KS13_ks13_ukwk_MASK              (0x400000U)
#define CSS_CSS_KS13_ks13_ukwk_SHIFT             (22U)
/*! ks13_ukwk - Key wrapping key
 */
#define CSS_CSS_KS13_ks13_ukwk(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_ukwk_SHIFT)) & CSS_CSS_KS13_ks13_ukwk_MASK)

#define CSS_CSS_KS13_ks13_ukuok_MASK             (0x800000U)
#define CSS_CSS_KS13_ks13_ukuok_SHIFT            (23U)
/*! ks13_ukuok - Key unwrapping key
 */
#define CSS_CSS_KS13_ks13_ukuok(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_ukuok_SHIFT)) & CSS_CSS_KS13_ks13_ukuok_MASK)

#define CSS_CSS_KS13_ks13_utlspms_MASK           (0x1000000U)
#define CSS_CSS_KS13_ks13_utlspms_SHIFT          (24U)
/*! ks13_utlspms - TLS Pre Master Secret
 */
#define CSS_CSS_KS13_ks13_utlspms(x)             (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_utlspms_SHIFT)) & CSS_CSS_KS13_ks13_utlspms_MASK)

#define CSS_CSS_KS13_ks13_utlsms_MASK            (0x2000000U)
#define CSS_CSS_KS13_ks13_utlsms_SHIFT           (25U)
/*! ks13_utlsms - TLS Master Secret
 */
#define CSS_CSS_KS13_ks13_utlsms(x)              (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_utlsms_SHIFT)) & CSS_CSS_KS13_ks13_utlsms_MASK)

#define CSS_CSS_KS13_ks13_ukgsrc_MASK            (0x4000000U)
#define CSS_CSS_KS13_ks13_ukgsrc_SHIFT           (26U)
/*! ks13_ukgsrc - Supply KEYGEN source
 */
#define CSS_CSS_KS13_ks13_ukgsrc(x)              (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_ukgsrc_SHIFT)) & CSS_CSS_KS13_ks13_ukgsrc_MASK)

#define CSS_CSS_KS13_ks13_uhwo_MASK              (0x8000000U)
#define CSS_CSS_KS13_ks13_uhwo_SHIFT             (27U)
/*! ks13_uhwo - Hardware out key
 */
#define CSS_CSS_KS13_ks13_uhwo(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_uhwo_SHIFT)) & CSS_CSS_KS13_ks13_uhwo_MASK)

#define CSS_CSS_KS13_ks13_uwrpok_MASK            (0x10000000U)
#define CSS_CSS_KS13_ks13_uwrpok_SHIFT           (28U)
/*! ks13_uwrpok - Ok to wrap key
 */
#define CSS_CSS_KS13_ks13_uwrpok(x)              (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_uwrpok_SHIFT)) & CSS_CSS_KS13_ks13_uwrpok_MASK)

#define CSS_CSS_KS13_ks13_uduk_MASK              (0x20000000U)
#define CSS_CSS_KS13_ks13_uduk_SHIFT             (29U)
/*! ks13_uduk - Device Unique Key
 */
#define CSS_CSS_KS13_ks13_uduk(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_uduk_SHIFT)) & CSS_CSS_KS13_ks13_uduk_MASK)

#define CSS_CSS_KS13_ks13_upprot_MASK            (0xC0000000U)
#define CSS_CSS_KS13_ks13_upprot_SHIFT           (30U)
/*! ks13_upprot - Priviledge level
 */
#define CSS_CSS_KS13_ks13_upprot(x)              (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS13_ks13_upprot_SHIFT)) & CSS_CSS_KS13_ks13_upprot_MASK)
/*! @} */

/*! @name CSS_KS14 - Status register */
/*! @{ */

#define CSS_CSS_KS14_ks14_ksize_MASK             (0x1U)
#define CSS_CSS_KS14_ks14_ksize_SHIFT            (0U)
/*! ks14_ksize - Key size: 0-128, 1-256
 */
#define CSS_CSS_KS14_ks14_ksize(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_ksize_SHIFT)) & CSS_CSS_KS14_ks14_ksize_MASK)

#define CSS_CSS_KS14_ks14_rsvd0_MASK             (0x1EU)
#define CSS_CSS_KS14_ks14_rsvd0_SHIFT            (1U)
/*! ks14_rsvd0 - Reserved 0
 */
#define CSS_CSS_KS14_ks14_rsvd0(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_rsvd0_SHIFT)) & CSS_CSS_KS14_ks14_rsvd0_MASK)

#define CSS_CSS_KS14_ks14_kact_MASK              (0x20U)
#define CSS_CSS_KS14_ks14_kact_SHIFT             (5U)
/*! ks14_kact - Key is active
 */
#define CSS_CSS_KS14_ks14_kact(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_kact_SHIFT)) & CSS_CSS_KS14_ks14_kact_MASK)

#define CSS_CSS_KS14_ks14_kbase_MASK             (0x40U)
#define CSS_CSS_KS14_ks14_kbase_SHIFT            (6U)
/*! ks14_kbase - First slot in a multislot key
 */
#define CSS_CSS_KS14_ks14_kbase(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_kbase_SHIFT)) & CSS_CSS_KS14_ks14_kbase_MASK)

#define CSS_CSS_KS14_ks14_fgp_MASK               (0x80U)
#define CSS_CSS_KS14_ks14_fgp_SHIFT              (7U)
/*! ks14_fgp - Hardware Feature General Purpose
 */
#define CSS_CSS_KS14_ks14_fgp(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_fgp_SHIFT)) & CSS_CSS_KS14_ks14_fgp_MASK)

#define CSS_CSS_KS14_ks14_frtn_MASK              (0x100U)
#define CSS_CSS_KS14_ks14_frtn_SHIFT             (8U)
/*! ks14_frtn - Hardware Feature Retention
 */
#define CSS_CSS_KS14_ks14_frtn(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_frtn_SHIFT)) & CSS_CSS_KS14_ks14_frtn_MASK)

#define CSS_CSS_KS14_ks14_fhwo_MASK              (0x200U)
#define CSS_CSS_KS14_ks14_fhwo_SHIFT             (9U)
/*! ks14_fhwo - Hardware Feature Output
 */
#define CSS_CSS_KS14_ks14_fhwo(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_fhwo_SHIFT)) & CSS_CSS_KS14_ks14_fhwo_MASK)

#define CSS_CSS_KS14_ks14_rsvd1_MASK             (0x1C00U)
#define CSS_CSS_KS14_ks14_rsvd1_SHIFT            (10U)
/*! ks14_rsvd1 - Reserved 1
 */
#define CSS_CSS_KS14_ks14_rsvd1(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_rsvd1_SHIFT)) & CSS_CSS_KS14_ks14_rsvd1_MASK)

#define CSS_CSS_KS14_ks14_ucmac_MASK             (0x2000U)
#define CSS_CSS_KS14_ks14_ucmac_SHIFT            (13U)
/*! ks14_ucmac - CMAC key
 */
#define CSS_CSS_KS14_ks14_ucmac(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_ucmac_SHIFT)) & CSS_CSS_KS14_ks14_ucmac_MASK)

#define CSS_CSS_KS14_ks14_uksk_MASK              (0x4000U)
#define CSS_CSS_KS14_ks14_uksk_SHIFT             (14U)
/*! ks14_uksk - KSK key
 */
#define CSS_CSS_KS14_ks14_uksk(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_uksk_SHIFT)) & CSS_CSS_KS14_ks14_uksk_MASK)

#define CSS_CSS_KS14_ks14_urtf_MASK              (0x8000U)
#define CSS_CSS_KS14_ks14_urtf_SHIFT             (15U)
/*! ks14_urtf - Real Time Fingerprint key
 */
#define CSS_CSS_KS14_ks14_urtf(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_urtf_SHIFT)) & CSS_CSS_KS14_ks14_urtf_MASK)

#define CSS_CSS_KS14_ks14_uckdf_MASK             (0x10000U)
#define CSS_CSS_KS14_ks14_uckdf_SHIFT            (16U)
/*! ks14_uckdf - Derivation key for CKDF command
 */
#define CSS_CSS_KS14_ks14_uckdf(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_uckdf_SHIFT)) & CSS_CSS_KS14_ks14_uckdf_MASK)

#define CSS_CSS_KS14_ks14_uhkdf_MASK             (0x20000U)
#define CSS_CSS_KS14_ks14_uhkdf_SHIFT            (17U)
/*! ks14_uhkdf - Derivation key for HKDF command
 */
#define CSS_CSS_KS14_ks14_uhkdf(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_uhkdf_SHIFT)) & CSS_CSS_KS14_ks14_uhkdf_MASK)

#define CSS_CSS_KS14_ks14_uecsg_MASK             (0x40000U)
#define CSS_CSS_KS14_ks14_uecsg_SHIFT            (18U)
/*! ks14_uecsg - Ecc signing key
 */
#define CSS_CSS_KS14_ks14_uecsg(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_uecsg_SHIFT)) & CSS_CSS_KS14_ks14_uecsg_MASK)

#define CSS_CSS_KS14_ks14_uecdh_MASK             (0x80000U)
#define CSS_CSS_KS14_ks14_uecdh_SHIFT            (19U)
/*! ks14_uecdh - Ecc diffie hellman key
 */
#define CSS_CSS_KS14_ks14_uecdh(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_uecdh_SHIFT)) & CSS_CSS_KS14_ks14_uecdh_MASK)

#define CSS_CSS_KS14_ks14_uaes_MASK              (0x100000U)
#define CSS_CSS_KS14_ks14_uaes_SHIFT             (20U)
/*! ks14_uaes - Aes key
 */
#define CSS_CSS_KS14_ks14_uaes(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_uaes_SHIFT)) & CSS_CSS_KS14_ks14_uaes_MASK)

#define CSS_CSS_KS14_ks14_uhmac_MASK             (0x200000U)
#define CSS_CSS_KS14_ks14_uhmac_SHIFT            (21U)
/*! ks14_uhmac - Hmac key
 */
#define CSS_CSS_KS14_ks14_uhmac(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_uhmac_SHIFT)) & CSS_CSS_KS14_ks14_uhmac_MASK)

#define CSS_CSS_KS14_ks14_ukwk_MASK              (0x400000U)
#define CSS_CSS_KS14_ks14_ukwk_SHIFT             (22U)
/*! ks14_ukwk - Key wrapping key
 */
#define CSS_CSS_KS14_ks14_ukwk(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_ukwk_SHIFT)) & CSS_CSS_KS14_ks14_ukwk_MASK)

#define CSS_CSS_KS14_ks14_ukuok_MASK             (0x800000U)
#define CSS_CSS_KS14_ks14_ukuok_SHIFT            (23U)
/*! ks14_ukuok - Key unwrapping key
 */
#define CSS_CSS_KS14_ks14_ukuok(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_ukuok_SHIFT)) & CSS_CSS_KS14_ks14_ukuok_MASK)

#define CSS_CSS_KS14_ks14_utlspms_MASK           (0x1000000U)
#define CSS_CSS_KS14_ks14_utlspms_SHIFT          (24U)
/*! ks14_utlspms - TLS Pre Master Secret
 */
#define CSS_CSS_KS14_ks14_utlspms(x)             (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_utlspms_SHIFT)) & CSS_CSS_KS14_ks14_utlspms_MASK)

#define CSS_CSS_KS14_ks14_utlsms_MASK            (0x2000000U)
#define CSS_CSS_KS14_ks14_utlsms_SHIFT           (25U)
/*! ks14_utlsms - TLS Master Secret
 */
#define CSS_CSS_KS14_ks14_utlsms(x)              (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_utlsms_SHIFT)) & CSS_CSS_KS14_ks14_utlsms_MASK)

#define CSS_CSS_KS14_ks14_ukgsrc_MASK            (0x4000000U)
#define CSS_CSS_KS14_ks14_ukgsrc_SHIFT           (26U)
/*! ks14_ukgsrc - Supply KEYGEN source
 */
#define CSS_CSS_KS14_ks14_ukgsrc(x)              (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_ukgsrc_SHIFT)) & CSS_CSS_KS14_ks14_ukgsrc_MASK)

#define CSS_CSS_KS14_ks14_uhwo_MASK              (0x8000000U)
#define CSS_CSS_KS14_ks14_uhwo_SHIFT             (27U)
/*! ks14_uhwo - Hardware out key
 */
#define CSS_CSS_KS14_ks14_uhwo(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_uhwo_SHIFT)) & CSS_CSS_KS14_ks14_uhwo_MASK)

#define CSS_CSS_KS14_ks14_uwrpok_MASK            (0x10000000U)
#define CSS_CSS_KS14_ks14_uwrpok_SHIFT           (28U)
/*! ks14_uwrpok - Ok to wrap key
 */
#define CSS_CSS_KS14_ks14_uwrpok(x)              (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_uwrpok_SHIFT)) & CSS_CSS_KS14_ks14_uwrpok_MASK)

#define CSS_CSS_KS14_ks14_uduk_MASK              (0x20000000U)
#define CSS_CSS_KS14_ks14_uduk_SHIFT             (29U)
/*! ks14_uduk - Device Unique Key
 */
#define CSS_CSS_KS14_ks14_uduk(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_uduk_SHIFT)) & CSS_CSS_KS14_ks14_uduk_MASK)

#define CSS_CSS_KS14_ks14_upprot_MASK            (0xC0000000U)
#define CSS_CSS_KS14_ks14_upprot_SHIFT           (30U)
/*! ks14_upprot - Priviledge level
 */
#define CSS_CSS_KS14_ks14_upprot(x)              (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS14_ks14_upprot_SHIFT)) & CSS_CSS_KS14_ks14_upprot_MASK)
/*! @} */

/*! @name CSS_KS15 - Status register */
/*! @{ */

#define CSS_CSS_KS15_ks15_ksize_MASK             (0x1U)
#define CSS_CSS_KS15_ks15_ksize_SHIFT            (0U)
/*! ks15_ksize - Key size: 0-128, 1-256
 */
#define CSS_CSS_KS15_ks15_ksize(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_ksize_SHIFT)) & CSS_CSS_KS15_ks15_ksize_MASK)

#define CSS_CSS_KS15_ks15_rsvd0_MASK             (0x1EU)
#define CSS_CSS_KS15_ks15_rsvd0_SHIFT            (1U)
/*! ks15_rsvd0 - Reserved 0
 */
#define CSS_CSS_KS15_ks15_rsvd0(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_rsvd0_SHIFT)) & CSS_CSS_KS15_ks15_rsvd0_MASK)

#define CSS_CSS_KS15_ks15_kact_MASK              (0x20U)
#define CSS_CSS_KS15_ks15_kact_SHIFT             (5U)
/*! ks15_kact - Key is active
 */
#define CSS_CSS_KS15_ks15_kact(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_kact_SHIFT)) & CSS_CSS_KS15_ks15_kact_MASK)

#define CSS_CSS_KS15_ks15_kbase_MASK             (0x40U)
#define CSS_CSS_KS15_ks15_kbase_SHIFT            (6U)
/*! ks15_kbase - First slot in a multislot key
 */
#define CSS_CSS_KS15_ks15_kbase(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_kbase_SHIFT)) & CSS_CSS_KS15_ks15_kbase_MASK)

#define CSS_CSS_KS15_ks15_fgp_MASK               (0x80U)
#define CSS_CSS_KS15_ks15_fgp_SHIFT              (7U)
/*! ks15_fgp - Hardware Feature General Purpose
 */
#define CSS_CSS_KS15_ks15_fgp(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_fgp_SHIFT)) & CSS_CSS_KS15_ks15_fgp_MASK)

#define CSS_CSS_KS15_ks15_frtn_MASK              (0x100U)
#define CSS_CSS_KS15_ks15_frtn_SHIFT             (8U)
/*! ks15_frtn - Hardware Feature Retention
 */
#define CSS_CSS_KS15_ks15_frtn(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_frtn_SHIFT)) & CSS_CSS_KS15_ks15_frtn_MASK)

#define CSS_CSS_KS15_ks15_fhwo_MASK              (0x200U)
#define CSS_CSS_KS15_ks15_fhwo_SHIFT             (9U)
/*! ks15_fhwo - Hardware Feature Output
 */
#define CSS_CSS_KS15_ks15_fhwo(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_fhwo_SHIFT)) & CSS_CSS_KS15_ks15_fhwo_MASK)

#define CSS_CSS_KS15_ks15_rsvd1_MASK             (0x1C00U)
#define CSS_CSS_KS15_ks15_rsvd1_SHIFT            (10U)
/*! ks15_rsvd1 - Reserved 1
 */
#define CSS_CSS_KS15_ks15_rsvd1(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_rsvd1_SHIFT)) & CSS_CSS_KS15_ks15_rsvd1_MASK)

#define CSS_CSS_KS15_ks15_ucmac_MASK             (0x2000U)
#define CSS_CSS_KS15_ks15_ucmac_SHIFT            (13U)
/*! ks15_ucmac - CMAC key
 */
#define CSS_CSS_KS15_ks15_ucmac(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_ucmac_SHIFT)) & CSS_CSS_KS15_ks15_ucmac_MASK)

#define CSS_CSS_KS15_ks15_uksk_MASK              (0x4000U)
#define CSS_CSS_KS15_ks15_uksk_SHIFT             (14U)
/*! ks15_uksk - KSK key
 */
#define CSS_CSS_KS15_ks15_uksk(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_uksk_SHIFT)) & CSS_CSS_KS15_ks15_uksk_MASK)

#define CSS_CSS_KS15_ks15_urtf_MASK              (0x8000U)
#define CSS_CSS_KS15_ks15_urtf_SHIFT             (15U)
/*! ks15_urtf - Real Time Fingerprint key
 */
#define CSS_CSS_KS15_ks15_urtf(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_urtf_SHIFT)) & CSS_CSS_KS15_ks15_urtf_MASK)

#define CSS_CSS_KS15_ks15_uckdf_MASK             (0x10000U)
#define CSS_CSS_KS15_ks15_uckdf_SHIFT            (16U)
/*! ks15_uckdf - Derivation key for CKDF command
 */
#define CSS_CSS_KS15_ks15_uckdf(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_uckdf_SHIFT)) & CSS_CSS_KS15_ks15_uckdf_MASK)

#define CSS_CSS_KS15_ks15_uhkdf_MASK             (0x20000U)
#define CSS_CSS_KS15_ks15_uhkdf_SHIFT            (17U)
/*! ks15_uhkdf - Derivation key for HKDF command
 */
#define CSS_CSS_KS15_ks15_uhkdf(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_uhkdf_SHIFT)) & CSS_CSS_KS15_ks15_uhkdf_MASK)

#define CSS_CSS_KS15_ks15_uecsg_MASK             (0x40000U)
#define CSS_CSS_KS15_ks15_uecsg_SHIFT            (18U)
/*! ks15_uecsg - Ecc signing key
 */
#define CSS_CSS_KS15_ks15_uecsg(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_uecsg_SHIFT)) & CSS_CSS_KS15_ks15_uecsg_MASK)

#define CSS_CSS_KS15_ks15_uecdh_MASK             (0x80000U)
#define CSS_CSS_KS15_ks15_uecdh_SHIFT            (19U)
/*! ks15_uecdh - Ecc diffie hellman key
 */
#define CSS_CSS_KS15_ks15_uecdh(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_uecdh_SHIFT)) & CSS_CSS_KS15_ks15_uecdh_MASK)

#define CSS_CSS_KS15_ks15_uaes_MASK              (0x100000U)
#define CSS_CSS_KS15_ks15_uaes_SHIFT             (20U)
/*! ks15_uaes - Aes key
 */
#define CSS_CSS_KS15_ks15_uaes(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_uaes_SHIFT)) & CSS_CSS_KS15_ks15_uaes_MASK)

#define CSS_CSS_KS15_ks15_uhmac_MASK             (0x200000U)
#define CSS_CSS_KS15_ks15_uhmac_SHIFT            (21U)
/*! ks15_uhmac - Hmac key
 */
#define CSS_CSS_KS15_ks15_uhmac(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_uhmac_SHIFT)) & CSS_CSS_KS15_ks15_uhmac_MASK)

#define CSS_CSS_KS15_ks15_ukwk_MASK              (0x400000U)
#define CSS_CSS_KS15_ks15_ukwk_SHIFT             (22U)
/*! ks15_ukwk - Key wrapping key
 */
#define CSS_CSS_KS15_ks15_ukwk(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_ukwk_SHIFT)) & CSS_CSS_KS15_ks15_ukwk_MASK)

#define CSS_CSS_KS15_ks15_ukuok_MASK             (0x800000U)
#define CSS_CSS_KS15_ks15_ukuok_SHIFT            (23U)
/*! ks15_ukuok - Key unwrapping key
 */
#define CSS_CSS_KS15_ks15_ukuok(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_ukuok_SHIFT)) & CSS_CSS_KS15_ks15_ukuok_MASK)

#define CSS_CSS_KS15_ks15_utlspms_MASK           (0x1000000U)
#define CSS_CSS_KS15_ks15_utlspms_SHIFT          (24U)
/*! ks15_utlspms - TLS Pre Master Secret
 */
#define CSS_CSS_KS15_ks15_utlspms(x)             (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_utlspms_SHIFT)) & CSS_CSS_KS15_ks15_utlspms_MASK)

#define CSS_CSS_KS15_ks15_utlsms_MASK            (0x2000000U)
#define CSS_CSS_KS15_ks15_utlsms_SHIFT           (25U)
/*! ks15_utlsms - TLS Master Secret
 */
#define CSS_CSS_KS15_ks15_utlsms(x)              (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_utlsms_SHIFT)) & CSS_CSS_KS15_ks15_utlsms_MASK)

#define CSS_CSS_KS15_ks15_ukgsrc_MASK            (0x4000000U)
#define CSS_CSS_KS15_ks15_ukgsrc_SHIFT           (26U)
/*! ks15_ukgsrc - Supply KEYGEN source
 */
#define CSS_CSS_KS15_ks15_ukgsrc(x)              (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_ukgsrc_SHIFT)) & CSS_CSS_KS15_ks15_ukgsrc_MASK)

#define CSS_CSS_KS15_ks15_uhwo_MASK              (0x8000000U)
#define CSS_CSS_KS15_ks15_uhwo_SHIFT             (27U)
/*! ks15_uhwo - Hardware out key
 */
#define CSS_CSS_KS15_ks15_uhwo(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_uhwo_SHIFT)) & CSS_CSS_KS15_ks15_uhwo_MASK)

#define CSS_CSS_KS15_ks15_uwrpok_MASK            (0x10000000U)
#define CSS_CSS_KS15_ks15_uwrpok_SHIFT           (28U)
/*! ks15_uwrpok - Ok to wrap key
 */
#define CSS_CSS_KS15_ks15_uwrpok(x)              (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_uwrpok_SHIFT)) & CSS_CSS_KS15_ks15_uwrpok_MASK)

#define CSS_CSS_KS15_ks15_uduk_MASK              (0x20000000U)
#define CSS_CSS_KS15_ks15_uduk_SHIFT             (29U)
/*! ks15_uduk - Device Unique Key
 */
#define CSS_CSS_KS15_ks15_uduk(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_uduk_SHIFT)) & CSS_CSS_KS15_ks15_uduk_MASK)

#define CSS_CSS_KS15_ks15_upprot_MASK            (0xC0000000U)
#define CSS_CSS_KS15_ks15_upprot_SHIFT           (30U)
/*! ks15_upprot - Priviledge level
 */
#define CSS_CSS_KS15_ks15_upprot(x)              (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS15_ks15_upprot_SHIFT)) & CSS_CSS_KS15_ks15_upprot_MASK)
/*! @} */

/*! @name CSS_KS16 - Status register */
/*! @{ */

#define CSS_CSS_KS16_ks16_ksize_MASK             (0x1U)
#define CSS_CSS_KS16_ks16_ksize_SHIFT            (0U)
/*! ks16_ksize - Key size: 0-128, 1-256
 */
#define CSS_CSS_KS16_ks16_ksize(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_ksize_SHIFT)) & CSS_CSS_KS16_ks16_ksize_MASK)

#define CSS_CSS_KS16_ks16_rsvd0_MASK             (0x1EU)
#define CSS_CSS_KS16_ks16_rsvd0_SHIFT            (1U)
/*! ks16_rsvd0 - Reserved 0
 */
#define CSS_CSS_KS16_ks16_rsvd0(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_rsvd0_SHIFT)) & CSS_CSS_KS16_ks16_rsvd0_MASK)

#define CSS_CSS_KS16_ks16_kact_MASK              (0x20U)
#define CSS_CSS_KS16_ks16_kact_SHIFT             (5U)
/*! ks16_kact - Key is active
 */
#define CSS_CSS_KS16_ks16_kact(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_kact_SHIFT)) & CSS_CSS_KS16_ks16_kact_MASK)

#define CSS_CSS_KS16_ks16_kbase_MASK             (0x40U)
#define CSS_CSS_KS16_ks16_kbase_SHIFT            (6U)
/*! ks16_kbase - First slot in a multislot key
 */
#define CSS_CSS_KS16_ks16_kbase(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_kbase_SHIFT)) & CSS_CSS_KS16_ks16_kbase_MASK)

#define CSS_CSS_KS16_ks16_fgp_MASK               (0x80U)
#define CSS_CSS_KS16_ks16_fgp_SHIFT              (7U)
/*! ks16_fgp - Hardware Feature General Purpose
 */
#define CSS_CSS_KS16_ks16_fgp(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_fgp_SHIFT)) & CSS_CSS_KS16_ks16_fgp_MASK)

#define CSS_CSS_KS16_ks16_frtn_MASK              (0x100U)
#define CSS_CSS_KS16_ks16_frtn_SHIFT             (8U)
/*! ks16_frtn - Hardware Feature Retention
 */
#define CSS_CSS_KS16_ks16_frtn(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_frtn_SHIFT)) & CSS_CSS_KS16_ks16_frtn_MASK)

#define CSS_CSS_KS16_ks16_fhwo_MASK              (0x200U)
#define CSS_CSS_KS16_ks16_fhwo_SHIFT             (9U)
/*! ks16_fhwo - Hardware Feature Output
 */
#define CSS_CSS_KS16_ks16_fhwo(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_fhwo_SHIFT)) & CSS_CSS_KS16_ks16_fhwo_MASK)

#define CSS_CSS_KS16_ks16_rsvd1_MASK             (0x1C00U)
#define CSS_CSS_KS16_ks16_rsvd1_SHIFT            (10U)
/*! ks16_rsvd1 - Reserved 1
 */
#define CSS_CSS_KS16_ks16_rsvd1(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_rsvd1_SHIFT)) & CSS_CSS_KS16_ks16_rsvd1_MASK)

#define CSS_CSS_KS16_ks16_ucmac_MASK             (0x2000U)
#define CSS_CSS_KS16_ks16_ucmac_SHIFT            (13U)
/*! ks16_ucmac - CMAC key
 */
#define CSS_CSS_KS16_ks16_ucmac(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_ucmac_SHIFT)) & CSS_CSS_KS16_ks16_ucmac_MASK)

#define CSS_CSS_KS16_ks16_uksk_MASK              (0x4000U)
#define CSS_CSS_KS16_ks16_uksk_SHIFT             (14U)
/*! ks16_uksk - KSK key
 */
#define CSS_CSS_KS16_ks16_uksk(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_uksk_SHIFT)) & CSS_CSS_KS16_ks16_uksk_MASK)

#define CSS_CSS_KS16_ks16_urtf_MASK              (0x8000U)
#define CSS_CSS_KS16_ks16_urtf_SHIFT             (15U)
/*! ks16_urtf - Real Time Fingerprint key
 */
#define CSS_CSS_KS16_ks16_urtf(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_urtf_SHIFT)) & CSS_CSS_KS16_ks16_urtf_MASK)

#define CSS_CSS_KS16_ks16_uckdf_MASK             (0x10000U)
#define CSS_CSS_KS16_ks16_uckdf_SHIFT            (16U)
/*! ks16_uckdf - Derivation key for CKDF command
 */
#define CSS_CSS_KS16_ks16_uckdf(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_uckdf_SHIFT)) & CSS_CSS_KS16_ks16_uckdf_MASK)

#define CSS_CSS_KS16_ks16_uhkdf_MASK             (0x20000U)
#define CSS_CSS_KS16_ks16_uhkdf_SHIFT            (17U)
/*! ks16_uhkdf - Derivation key for HKDF command
 */
#define CSS_CSS_KS16_ks16_uhkdf(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_uhkdf_SHIFT)) & CSS_CSS_KS16_ks16_uhkdf_MASK)

#define CSS_CSS_KS16_ks16_uecsg_MASK             (0x40000U)
#define CSS_CSS_KS16_ks16_uecsg_SHIFT            (18U)
/*! ks16_uecsg - Ecc signing key
 */
#define CSS_CSS_KS16_ks16_uecsg(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_uecsg_SHIFT)) & CSS_CSS_KS16_ks16_uecsg_MASK)

#define CSS_CSS_KS16_ks16_uecdh_MASK             (0x80000U)
#define CSS_CSS_KS16_ks16_uecdh_SHIFT            (19U)
/*! ks16_uecdh - Ecc diffie hellman key
 */
#define CSS_CSS_KS16_ks16_uecdh(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_uecdh_SHIFT)) & CSS_CSS_KS16_ks16_uecdh_MASK)

#define CSS_CSS_KS16_ks16_uaes_MASK              (0x100000U)
#define CSS_CSS_KS16_ks16_uaes_SHIFT             (20U)
/*! ks16_uaes - Aes key
 */
#define CSS_CSS_KS16_ks16_uaes(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_uaes_SHIFT)) & CSS_CSS_KS16_ks16_uaes_MASK)

#define CSS_CSS_KS16_ks16_uhmac_MASK             (0x200000U)
#define CSS_CSS_KS16_ks16_uhmac_SHIFT            (21U)
/*! ks16_uhmac - Hmac key
 */
#define CSS_CSS_KS16_ks16_uhmac(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_uhmac_SHIFT)) & CSS_CSS_KS16_ks16_uhmac_MASK)

#define CSS_CSS_KS16_ks16_ukwk_MASK              (0x400000U)
#define CSS_CSS_KS16_ks16_ukwk_SHIFT             (22U)
/*! ks16_ukwk - Key wrapping key
 */
#define CSS_CSS_KS16_ks16_ukwk(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_ukwk_SHIFT)) & CSS_CSS_KS16_ks16_ukwk_MASK)

#define CSS_CSS_KS16_ks16_ukuok_MASK             (0x800000U)
#define CSS_CSS_KS16_ks16_ukuok_SHIFT            (23U)
/*! ks16_ukuok - Key unwrapping key
 */
#define CSS_CSS_KS16_ks16_ukuok(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_ukuok_SHIFT)) & CSS_CSS_KS16_ks16_ukuok_MASK)

#define CSS_CSS_KS16_ks16_utlspms_MASK           (0x1000000U)
#define CSS_CSS_KS16_ks16_utlspms_SHIFT          (24U)
/*! ks16_utlspms - TLS Pre Master Secret
 */
#define CSS_CSS_KS16_ks16_utlspms(x)             (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_utlspms_SHIFT)) & CSS_CSS_KS16_ks16_utlspms_MASK)

#define CSS_CSS_KS16_ks16_utlsms_MASK            (0x2000000U)
#define CSS_CSS_KS16_ks16_utlsms_SHIFT           (25U)
/*! ks16_utlsms - TLS Master Secret
 */
#define CSS_CSS_KS16_ks16_utlsms(x)              (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_utlsms_SHIFT)) & CSS_CSS_KS16_ks16_utlsms_MASK)

#define CSS_CSS_KS16_ks16_ukgsrc_MASK            (0x4000000U)
#define CSS_CSS_KS16_ks16_ukgsrc_SHIFT           (26U)
/*! ks16_ukgsrc - Supply KEYGEN source
 */
#define CSS_CSS_KS16_ks16_ukgsrc(x)              (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_ukgsrc_SHIFT)) & CSS_CSS_KS16_ks16_ukgsrc_MASK)

#define CSS_CSS_KS16_ks16_uhwo_MASK              (0x8000000U)
#define CSS_CSS_KS16_ks16_uhwo_SHIFT             (27U)
/*! ks16_uhwo - Hardware out key
 */
#define CSS_CSS_KS16_ks16_uhwo(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_uhwo_SHIFT)) & CSS_CSS_KS16_ks16_uhwo_MASK)

#define CSS_CSS_KS16_ks16_uwrpok_MASK            (0x10000000U)
#define CSS_CSS_KS16_ks16_uwrpok_SHIFT           (28U)
/*! ks16_uwrpok - Ok to wrap key
 */
#define CSS_CSS_KS16_ks16_uwrpok(x)              (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_uwrpok_SHIFT)) & CSS_CSS_KS16_ks16_uwrpok_MASK)

#define CSS_CSS_KS16_ks16_uduk_MASK              (0x20000000U)
#define CSS_CSS_KS16_ks16_uduk_SHIFT             (29U)
/*! ks16_uduk - Device Unique Key
 */
#define CSS_CSS_KS16_ks16_uduk(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_uduk_SHIFT)) & CSS_CSS_KS16_ks16_uduk_MASK)

#define CSS_CSS_KS16_ks16_upprot_MASK            (0xC0000000U)
#define CSS_CSS_KS16_ks16_upprot_SHIFT           (30U)
/*! ks16_upprot - Priviledge level
 */
#define CSS_CSS_KS16_ks16_upprot(x)              (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS16_ks16_upprot_SHIFT)) & CSS_CSS_KS16_ks16_upprot_MASK)
/*! @} */

/*! @name CSS_KS17 - Status register */
/*! @{ */

#define CSS_CSS_KS17_ks17_ksize_MASK             (0x1U)
#define CSS_CSS_KS17_ks17_ksize_SHIFT            (0U)
/*! ks17_ksize - Key size: 0-128, 1-256
 */
#define CSS_CSS_KS17_ks17_ksize(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_ksize_SHIFT)) & CSS_CSS_KS17_ks17_ksize_MASK)

#define CSS_CSS_KS17_ks17_rsvd0_MASK             (0x1EU)
#define CSS_CSS_KS17_ks17_rsvd0_SHIFT            (1U)
/*! ks17_rsvd0 - Reserved 0
 */
#define CSS_CSS_KS17_ks17_rsvd0(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_rsvd0_SHIFT)) & CSS_CSS_KS17_ks17_rsvd0_MASK)

#define CSS_CSS_KS17_ks17_kact_MASK              (0x20U)
#define CSS_CSS_KS17_ks17_kact_SHIFT             (5U)
/*! ks17_kact - Key is active
 */
#define CSS_CSS_KS17_ks17_kact(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_kact_SHIFT)) & CSS_CSS_KS17_ks17_kact_MASK)

#define CSS_CSS_KS17_ks17_kbase_MASK             (0x40U)
#define CSS_CSS_KS17_ks17_kbase_SHIFT            (6U)
/*! ks17_kbase - First slot in a multislot key
 */
#define CSS_CSS_KS17_ks17_kbase(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_kbase_SHIFT)) & CSS_CSS_KS17_ks17_kbase_MASK)

#define CSS_CSS_KS17_ks17_fgp_MASK               (0x80U)
#define CSS_CSS_KS17_ks17_fgp_SHIFT              (7U)
/*! ks17_fgp - Hardware Feature General Purpose
 */
#define CSS_CSS_KS17_ks17_fgp(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_fgp_SHIFT)) & CSS_CSS_KS17_ks17_fgp_MASK)

#define CSS_CSS_KS17_ks17_frtn_MASK              (0x100U)
#define CSS_CSS_KS17_ks17_frtn_SHIFT             (8U)
/*! ks17_frtn - Hardware Feature Retention
 */
#define CSS_CSS_KS17_ks17_frtn(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_frtn_SHIFT)) & CSS_CSS_KS17_ks17_frtn_MASK)

#define CSS_CSS_KS17_ks17_fhwo_MASK              (0x200U)
#define CSS_CSS_KS17_ks17_fhwo_SHIFT             (9U)
/*! ks17_fhwo - Hardware Feature Output
 */
#define CSS_CSS_KS17_ks17_fhwo(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_fhwo_SHIFT)) & CSS_CSS_KS17_ks17_fhwo_MASK)

#define CSS_CSS_KS17_ks17_rsvd1_MASK             (0x1C00U)
#define CSS_CSS_KS17_ks17_rsvd1_SHIFT            (10U)
/*! ks17_rsvd1 - Reserved 1
 */
#define CSS_CSS_KS17_ks17_rsvd1(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_rsvd1_SHIFT)) & CSS_CSS_KS17_ks17_rsvd1_MASK)

#define CSS_CSS_KS17_ks17_ucmac_MASK             (0x2000U)
#define CSS_CSS_KS17_ks17_ucmac_SHIFT            (13U)
/*! ks17_ucmac - CMAC key
 */
#define CSS_CSS_KS17_ks17_ucmac(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_ucmac_SHIFT)) & CSS_CSS_KS17_ks17_ucmac_MASK)

#define CSS_CSS_KS17_ks17_uksk_MASK              (0x4000U)
#define CSS_CSS_KS17_ks17_uksk_SHIFT             (14U)
/*! ks17_uksk - KSK key
 */
#define CSS_CSS_KS17_ks17_uksk(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_uksk_SHIFT)) & CSS_CSS_KS17_ks17_uksk_MASK)

#define CSS_CSS_KS17_ks17_urtf_MASK              (0x8000U)
#define CSS_CSS_KS17_ks17_urtf_SHIFT             (15U)
/*! ks17_urtf - Real Time Fingerprint key
 */
#define CSS_CSS_KS17_ks17_urtf(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_urtf_SHIFT)) & CSS_CSS_KS17_ks17_urtf_MASK)

#define CSS_CSS_KS17_ks17_uckdf_MASK             (0x10000U)
#define CSS_CSS_KS17_ks17_uckdf_SHIFT            (16U)
/*! ks17_uckdf - Derivation key for CKDF command
 */
#define CSS_CSS_KS17_ks17_uckdf(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_uckdf_SHIFT)) & CSS_CSS_KS17_ks17_uckdf_MASK)

#define CSS_CSS_KS17_ks17_uhkdf_MASK             (0x20000U)
#define CSS_CSS_KS17_ks17_uhkdf_SHIFT            (17U)
/*! ks17_uhkdf - Derivation key for HKDF command
 */
#define CSS_CSS_KS17_ks17_uhkdf(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_uhkdf_SHIFT)) & CSS_CSS_KS17_ks17_uhkdf_MASK)

#define CSS_CSS_KS17_ks17_uecsg_MASK             (0x40000U)
#define CSS_CSS_KS17_ks17_uecsg_SHIFT            (18U)
/*! ks17_uecsg - Ecc signing key
 */
#define CSS_CSS_KS17_ks17_uecsg(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_uecsg_SHIFT)) & CSS_CSS_KS17_ks17_uecsg_MASK)

#define CSS_CSS_KS17_ks17_uecdh_MASK             (0x80000U)
#define CSS_CSS_KS17_ks17_uecdh_SHIFT            (19U)
/*! ks17_uecdh - Ecc diffie hellman key
 */
#define CSS_CSS_KS17_ks17_uecdh(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_uecdh_SHIFT)) & CSS_CSS_KS17_ks17_uecdh_MASK)

#define CSS_CSS_KS17_ks17_uaes_MASK              (0x100000U)
#define CSS_CSS_KS17_ks17_uaes_SHIFT             (20U)
/*! ks17_uaes - Aes key
 */
#define CSS_CSS_KS17_ks17_uaes(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_uaes_SHIFT)) & CSS_CSS_KS17_ks17_uaes_MASK)

#define CSS_CSS_KS17_ks17_uhmac_MASK             (0x200000U)
#define CSS_CSS_KS17_ks17_uhmac_SHIFT            (21U)
/*! ks17_uhmac - Hmac key
 */
#define CSS_CSS_KS17_ks17_uhmac(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_uhmac_SHIFT)) & CSS_CSS_KS17_ks17_uhmac_MASK)

#define CSS_CSS_KS17_ks17_ukwk_MASK              (0x400000U)
#define CSS_CSS_KS17_ks17_ukwk_SHIFT             (22U)
/*! ks17_ukwk - Key wrapping key
 */
#define CSS_CSS_KS17_ks17_ukwk(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_ukwk_SHIFT)) & CSS_CSS_KS17_ks17_ukwk_MASK)

#define CSS_CSS_KS17_ks17_ukuok_MASK             (0x800000U)
#define CSS_CSS_KS17_ks17_ukuok_SHIFT            (23U)
/*! ks17_ukuok - Key unwrapping key
 */
#define CSS_CSS_KS17_ks17_ukuok(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_ukuok_SHIFT)) & CSS_CSS_KS17_ks17_ukuok_MASK)

#define CSS_CSS_KS17_ks17_utlspms_MASK           (0x1000000U)
#define CSS_CSS_KS17_ks17_utlspms_SHIFT          (24U)
/*! ks17_utlspms - TLS Pre Master Secret
 */
#define CSS_CSS_KS17_ks17_utlspms(x)             (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_utlspms_SHIFT)) & CSS_CSS_KS17_ks17_utlspms_MASK)

#define CSS_CSS_KS17_ks17_utlsms_MASK            (0x2000000U)
#define CSS_CSS_KS17_ks17_utlsms_SHIFT           (25U)
/*! ks17_utlsms - TLS Master Secret
 */
#define CSS_CSS_KS17_ks17_utlsms(x)              (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_utlsms_SHIFT)) & CSS_CSS_KS17_ks17_utlsms_MASK)

#define CSS_CSS_KS17_ks17_ukgsrc_MASK            (0x4000000U)
#define CSS_CSS_KS17_ks17_ukgsrc_SHIFT           (26U)
/*! ks17_ukgsrc - Supply KEYGEN source
 */
#define CSS_CSS_KS17_ks17_ukgsrc(x)              (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_ukgsrc_SHIFT)) & CSS_CSS_KS17_ks17_ukgsrc_MASK)

#define CSS_CSS_KS17_ks17_uhwo_MASK              (0x8000000U)
#define CSS_CSS_KS17_ks17_uhwo_SHIFT             (27U)
/*! ks17_uhwo - Hardware out key
 */
#define CSS_CSS_KS17_ks17_uhwo(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_uhwo_SHIFT)) & CSS_CSS_KS17_ks17_uhwo_MASK)

#define CSS_CSS_KS17_ks17_uwrpok_MASK            (0x10000000U)
#define CSS_CSS_KS17_ks17_uwrpok_SHIFT           (28U)
/*! ks17_uwrpok - Ok to wrap key
 */
#define CSS_CSS_KS17_ks17_uwrpok(x)              (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_uwrpok_SHIFT)) & CSS_CSS_KS17_ks17_uwrpok_MASK)

#define CSS_CSS_KS17_ks17_uduk_MASK              (0x20000000U)
#define CSS_CSS_KS17_ks17_uduk_SHIFT             (29U)
/*! ks17_uduk - Device Unique Key
 */
#define CSS_CSS_KS17_ks17_uduk(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_uduk_SHIFT)) & CSS_CSS_KS17_ks17_uduk_MASK)

#define CSS_CSS_KS17_ks17_upprot_MASK            (0xC0000000U)
#define CSS_CSS_KS17_ks17_upprot_SHIFT           (30U)
/*! ks17_upprot - Priviledge level
 */
#define CSS_CSS_KS17_ks17_upprot(x)              (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS17_ks17_upprot_SHIFT)) & CSS_CSS_KS17_ks17_upprot_MASK)
/*! @} */

/*! @name CSS_KS18 - Status register */
/*! @{ */

#define CSS_CSS_KS18_ks18_ksize_MASK             (0x1U)
#define CSS_CSS_KS18_ks18_ksize_SHIFT            (0U)
/*! ks18_ksize - Key size: 0-128, 1-256
 */
#define CSS_CSS_KS18_ks18_ksize(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_ksize_SHIFT)) & CSS_CSS_KS18_ks18_ksize_MASK)

#define CSS_CSS_KS18_ks18_rsvd0_MASK             (0x1EU)
#define CSS_CSS_KS18_ks18_rsvd0_SHIFT            (1U)
/*! ks18_rsvd0 - Reserved 0
 */
#define CSS_CSS_KS18_ks18_rsvd0(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_rsvd0_SHIFT)) & CSS_CSS_KS18_ks18_rsvd0_MASK)

#define CSS_CSS_KS18_ks18_kact_MASK              (0x20U)
#define CSS_CSS_KS18_ks18_kact_SHIFT             (5U)
/*! ks18_kact - Key is active
 */
#define CSS_CSS_KS18_ks18_kact(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_kact_SHIFT)) & CSS_CSS_KS18_ks18_kact_MASK)

#define CSS_CSS_KS18_ks18_kbase_MASK             (0x40U)
#define CSS_CSS_KS18_ks18_kbase_SHIFT            (6U)
/*! ks18_kbase - First slot in a multislot key
 */
#define CSS_CSS_KS18_ks18_kbase(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_kbase_SHIFT)) & CSS_CSS_KS18_ks18_kbase_MASK)

#define CSS_CSS_KS18_ks18_fgp_MASK               (0x80U)
#define CSS_CSS_KS18_ks18_fgp_SHIFT              (7U)
/*! ks18_fgp - Hardware Feature General Purpose
 */
#define CSS_CSS_KS18_ks18_fgp(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_fgp_SHIFT)) & CSS_CSS_KS18_ks18_fgp_MASK)

#define CSS_CSS_KS18_ks18_frtn_MASK              (0x100U)
#define CSS_CSS_KS18_ks18_frtn_SHIFT             (8U)
/*! ks18_frtn - Hardware Feature Retention
 */
#define CSS_CSS_KS18_ks18_frtn(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_frtn_SHIFT)) & CSS_CSS_KS18_ks18_frtn_MASK)

#define CSS_CSS_KS18_ks18_fhwo_MASK              (0x200U)
#define CSS_CSS_KS18_ks18_fhwo_SHIFT             (9U)
/*! ks18_fhwo - Hardware Feature Output
 */
#define CSS_CSS_KS18_ks18_fhwo(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_fhwo_SHIFT)) & CSS_CSS_KS18_ks18_fhwo_MASK)

#define CSS_CSS_KS18_ks18_rsvd1_MASK             (0x1C00U)
#define CSS_CSS_KS18_ks18_rsvd1_SHIFT            (10U)
/*! ks18_rsvd1 - Reserved 1
 */
#define CSS_CSS_KS18_ks18_rsvd1(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_rsvd1_SHIFT)) & CSS_CSS_KS18_ks18_rsvd1_MASK)

#define CSS_CSS_KS18_ks18_ucmac_MASK             (0x2000U)
#define CSS_CSS_KS18_ks18_ucmac_SHIFT            (13U)
/*! ks18_ucmac - CMAC key
 */
#define CSS_CSS_KS18_ks18_ucmac(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_ucmac_SHIFT)) & CSS_CSS_KS18_ks18_ucmac_MASK)

#define CSS_CSS_KS18_ks18_uksk_MASK              (0x4000U)
#define CSS_CSS_KS18_ks18_uksk_SHIFT             (14U)
/*! ks18_uksk - KSK key
 */
#define CSS_CSS_KS18_ks18_uksk(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_uksk_SHIFT)) & CSS_CSS_KS18_ks18_uksk_MASK)

#define CSS_CSS_KS18_ks18_urtf_MASK              (0x8000U)
#define CSS_CSS_KS18_ks18_urtf_SHIFT             (15U)
/*! ks18_urtf - Real Time Fingerprint key
 */
#define CSS_CSS_KS18_ks18_urtf(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_urtf_SHIFT)) & CSS_CSS_KS18_ks18_urtf_MASK)

#define CSS_CSS_KS18_ks18_uckdf_MASK             (0x10000U)
#define CSS_CSS_KS18_ks18_uckdf_SHIFT            (16U)
/*! ks18_uckdf - Derivation key for CKDF command
 */
#define CSS_CSS_KS18_ks18_uckdf(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_uckdf_SHIFT)) & CSS_CSS_KS18_ks18_uckdf_MASK)

#define CSS_CSS_KS18_ks18_uhkdf_MASK             (0x20000U)
#define CSS_CSS_KS18_ks18_uhkdf_SHIFT            (17U)
/*! ks18_uhkdf - Derivation key for HKDF command
 */
#define CSS_CSS_KS18_ks18_uhkdf(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_uhkdf_SHIFT)) & CSS_CSS_KS18_ks18_uhkdf_MASK)

#define CSS_CSS_KS18_ks18_uecsg_MASK             (0x40000U)
#define CSS_CSS_KS18_ks18_uecsg_SHIFT            (18U)
/*! ks18_uecsg - Ecc signing key
 */
#define CSS_CSS_KS18_ks18_uecsg(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_uecsg_SHIFT)) & CSS_CSS_KS18_ks18_uecsg_MASK)

#define CSS_CSS_KS18_ks18_uecdh_MASK             (0x80000U)
#define CSS_CSS_KS18_ks18_uecdh_SHIFT            (19U)
/*! ks18_uecdh - Ecc diffie hellman key
 */
#define CSS_CSS_KS18_ks18_uecdh(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_uecdh_SHIFT)) & CSS_CSS_KS18_ks18_uecdh_MASK)

#define CSS_CSS_KS18_ks18_uaes_MASK              (0x100000U)
#define CSS_CSS_KS18_ks18_uaes_SHIFT             (20U)
/*! ks18_uaes - Aes key
 */
#define CSS_CSS_KS18_ks18_uaes(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_uaes_SHIFT)) & CSS_CSS_KS18_ks18_uaes_MASK)

#define CSS_CSS_KS18_ks18_uhmac_MASK             (0x200000U)
#define CSS_CSS_KS18_ks18_uhmac_SHIFT            (21U)
/*! ks18_uhmac - Hmac key
 */
#define CSS_CSS_KS18_ks18_uhmac(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_uhmac_SHIFT)) & CSS_CSS_KS18_ks18_uhmac_MASK)

#define CSS_CSS_KS18_ks18_ukwk_MASK              (0x400000U)
#define CSS_CSS_KS18_ks18_ukwk_SHIFT             (22U)
/*! ks18_ukwk - Key wrapping key
 */
#define CSS_CSS_KS18_ks18_ukwk(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_ukwk_SHIFT)) & CSS_CSS_KS18_ks18_ukwk_MASK)

#define CSS_CSS_KS18_ks18_ukuok_MASK             (0x800000U)
#define CSS_CSS_KS18_ks18_ukuok_SHIFT            (23U)
/*! ks18_ukuok - Key unwrapping key
 */
#define CSS_CSS_KS18_ks18_ukuok(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_ukuok_SHIFT)) & CSS_CSS_KS18_ks18_ukuok_MASK)

#define CSS_CSS_KS18_ks18_utlspms_MASK           (0x1000000U)
#define CSS_CSS_KS18_ks18_utlspms_SHIFT          (24U)
/*! ks18_utlspms - TLS Pre Master Secret
 */
#define CSS_CSS_KS18_ks18_utlspms(x)             (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_utlspms_SHIFT)) & CSS_CSS_KS18_ks18_utlspms_MASK)

#define CSS_CSS_KS18_ks18_utlsms_MASK            (0x2000000U)
#define CSS_CSS_KS18_ks18_utlsms_SHIFT           (25U)
/*! ks18_utlsms - TLS Master Secret
 */
#define CSS_CSS_KS18_ks18_utlsms(x)              (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_utlsms_SHIFT)) & CSS_CSS_KS18_ks18_utlsms_MASK)

#define CSS_CSS_KS18_ks18_ukgsrc_MASK            (0x4000000U)
#define CSS_CSS_KS18_ks18_ukgsrc_SHIFT           (26U)
/*! ks18_ukgsrc - Supply KEYGEN source
 */
#define CSS_CSS_KS18_ks18_ukgsrc(x)              (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_ukgsrc_SHIFT)) & CSS_CSS_KS18_ks18_ukgsrc_MASK)

#define CSS_CSS_KS18_ks18_uhwo_MASK              (0x8000000U)
#define CSS_CSS_KS18_ks18_uhwo_SHIFT             (27U)
/*! ks18_uhwo - Hardware out key
 */
#define CSS_CSS_KS18_ks18_uhwo(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_uhwo_SHIFT)) & CSS_CSS_KS18_ks18_uhwo_MASK)

#define CSS_CSS_KS18_ks18_uwrpok_MASK            (0x10000000U)
#define CSS_CSS_KS18_ks18_uwrpok_SHIFT           (28U)
/*! ks18_uwrpok - Ok to wrap key
 */
#define CSS_CSS_KS18_ks18_uwrpok(x)              (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_uwrpok_SHIFT)) & CSS_CSS_KS18_ks18_uwrpok_MASK)

#define CSS_CSS_KS18_ks18_uduk_MASK              (0x20000000U)
#define CSS_CSS_KS18_ks18_uduk_SHIFT             (29U)
/*! ks18_uduk - Device Unique Key
 */
#define CSS_CSS_KS18_ks18_uduk(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_uduk_SHIFT)) & CSS_CSS_KS18_ks18_uduk_MASK)

#define CSS_CSS_KS18_ks18_upprot_MASK            (0xC0000000U)
#define CSS_CSS_KS18_ks18_upprot_SHIFT           (30U)
/*! ks18_upprot - Priviledge level
 */
#define CSS_CSS_KS18_ks18_upprot(x)              (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS18_ks18_upprot_SHIFT)) & CSS_CSS_KS18_ks18_upprot_MASK)
/*! @} */

/*! @name CSS_KS19 - Status register */
/*! @{ */

#define CSS_CSS_KS19_ks19_ksize_MASK             (0x1U)
#define CSS_CSS_KS19_ks19_ksize_SHIFT            (0U)
/*! ks19_ksize - Key size: 0-128, 1-256
 */
#define CSS_CSS_KS19_ks19_ksize(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_ksize_SHIFT)) & CSS_CSS_KS19_ks19_ksize_MASK)

#define CSS_CSS_KS19_ks19_rsvd0_MASK             (0x1EU)
#define CSS_CSS_KS19_ks19_rsvd0_SHIFT            (1U)
/*! ks19_rsvd0 - Reserved 0
 */
#define CSS_CSS_KS19_ks19_rsvd0(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_rsvd0_SHIFT)) & CSS_CSS_KS19_ks19_rsvd0_MASK)

#define CSS_CSS_KS19_ks19_kact_MASK              (0x20U)
#define CSS_CSS_KS19_ks19_kact_SHIFT             (5U)
/*! ks19_kact - Key is active
 */
#define CSS_CSS_KS19_ks19_kact(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_kact_SHIFT)) & CSS_CSS_KS19_ks19_kact_MASK)

#define CSS_CSS_KS19_ks19_kbase_MASK             (0x40U)
#define CSS_CSS_KS19_ks19_kbase_SHIFT            (6U)
/*! ks19_kbase - First slot in a multislot key
 */
#define CSS_CSS_KS19_ks19_kbase(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_kbase_SHIFT)) & CSS_CSS_KS19_ks19_kbase_MASK)

#define CSS_CSS_KS19_ks19_fgp_MASK               (0x80U)
#define CSS_CSS_KS19_ks19_fgp_SHIFT              (7U)
/*! ks19_fgp - Hardware Feature General Purpose
 */
#define CSS_CSS_KS19_ks19_fgp(x)                 (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_fgp_SHIFT)) & CSS_CSS_KS19_ks19_fgp_MASK)

#define CSS_CSS_KS19_ks19_frtn_MASK              (0x100U)
#define CSS_CSS_KS19_ks19_frtn_SHIFT             (8U)
/*! ks19_frtn - Hardware Feature Retention
 */
#define CSS_CSS_KS19_ks19_frtn(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_frtn_SHIFT)) & CSS_CSS_KS19_ks19_frtn_MASK)

#define CSS_CSS_KS19_ks19_fhwo_MASK              (0x200U)
#define CSS_CSS_KS19_ks19_fhwo_SHIFT             (9U)
/*! ks19_fhwo - Hardware Feature Output
 */
#define CSS_CSS_KS19_ks19_fhwo(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_fhwo_SHIFT)) & CSS_CSS_KS19_ks19_fhwo_MASK)

#define CSS_CSS_KS19_ks19_rsvd1_MASK             (0x1C00U)
#define CSS_CSS_KS19_ks19_rsvd1_SHIFT            (10U)
/*! ks19_rsvd1 - Reserved 1
 */
#define CSS_CSS_KS19_ks19_rsvd1(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_rsvd1_SHIFT)) & CSS_CSS_KS19_ks19_rsvd1_MASK)

#define CSS_CSS_KS19_ks19_ucmac_MASK             (0x2000U)
#define CSS_CSS_KS19_ks19_ucmac_SHIFT            (13U)
/*! ks19_ucmac - CMAC key
 */
#define CSS_CSS_KS19_ks19_ucmac(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_ucmac_SHIFT)) & CSS_CSS_KS19_ks19_ucmac_MASK)

#define CSS_CSS_KS19_ks19_uksk_MASK              (0x4000U)
#define CSS_CSS_KS19_ks19_uksk_SHIFT             (14U)
/*! ks19_uksk - KSK key
 */
#define CSS_CSS_KS19_ks19_uksk(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_uksk_SHIFT)) & CSS_CSS_KS19_ks19_uksk_MASK)

#define CSS_CSS_KS19_ks19_urtf_MASK              (0x8000U)
#define CSS_CSS_KS19_ks19_urtf_SHIFT             (15U)
/*! ks19_urtf - Real Time Fingerprint key
 */
#define CSS_CSS_KS19_ks19_urtf(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_urtf_SHIFT)) & CSS_CSS_KS19_ks19_urtf_MASK)

#define CSS_CSS_KS19_ks19_uckdf_MASK             (0x10000U)
#define CSS_CSS_KS19_ks19_uckdf_SHIFT            (16U)
/*! ks19_uckdf - Derivation key for CKDF command
 */
#define CSS_CSS_KS19_ks19_uckdf(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_uckdf_SHIFT)) & CSS_CSS_KS19_ks19_uckdf_MASK)

#define CSS_CSS_KS19_ks19_uhkdf_MASK             (0x20000U)
#define CSS_CSS_KS19_ks19_uhkdf_SHIFT            (17U)
/*! ks19_uhkdf - Derivation key for HKDF command
 */
#define CSS_CSS_KS19_ks19_uhkdf(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_uhkdf_SHIFT)) & CSS_CSS_KS19_ks19_uhkdf_MASK)

#define CSS_CSS_KS19_ks19_uecsg_MASK             (0x40000U)
#define CSS_CSS_KS19_ks19_uecsg_SHIFT            (18U)
/*! ks19_uecsg - Ecc signing key
 */
#define CSS_CSS_KS19_ks19_uecsg(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_uecsg_SHIFT)) & CSS_CSS_KS19_ks19_uecsg_MASK)

#define CSS_CSS_KS19_ks19_uecdh_MASK             (0x80000U)
#define CSS_CSS_KS19_ks19_uecdh_SHIFT            (19U)
/*! ks19_uecdh - Ecc diffie hellman key
 */
#define CSS_CSS_KS19_ks19_uecdh(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_uecdh_SHIFT)) & CSS_CSS_KS19_ks19_uecdh_MASK)

#define CSS_CSS_KS19_ks19_uaes_MASK              (0x100000U)
#define CSS_CSS_KS19_ks19_uaes_SHIFT             (20U)
/*! ks19_uaes - Aes key
 */
#define CSS_CSS_KS19_ks19_uaes(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_uaes_SHIFT)) & CSS_CSS_KS19_ks19_uaes_MASK)

#define CSS_CSS_KS19_ks19_uhmac_MASK             (0x200000U)
#define CSS_CSS_KS19_ks19_uhmac_SHIFT            (21U)
/*! ks19_uhmac - Hmac key
 */
#define CSS_CSS_KS19_ks19_uhmac(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_uhmac_SHIFT)) & CSS_CSS_KS19_ks19_uhmac_MASK)

#define CSS_CSS_KS19_ks19_ukwk_MASK              (0x400000U)
#define CSS_CSS_KS19_ks19_ukwk_SHIFT             (22U)
/*! ks19_ukwk - Key wrapping key
 */
#define CSS_CSS_KS19_ks19_ukwk(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_ukwk_SHIFT)) & CSS_CSS_KS19_ks19_ukwk_MASK)

#define CSS_CSS_KS19_ks19_ukuok_MASK             (0x800000U)
#define CSS_CSS_KS19_ks19_ukuok_SHIFT            (23U)
/*! ks19_ukuok - Key unwrapping key
 */
#define CSS_CSS_KS19_ks19_ukuok(x)               (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_ukuok_SHIFT)) & CSS_CSS_KS19_ks19_ukuok_MASK)

#define CSS_CSS_KS19_ks19_utlspms_MASK           (0x1000000U)
#define CSS_CSS_KS19_ks19_utlspms_SHIFT          (24U)
/*! ks19_utlspms - TLS Pre Master Secret
 */
#define CSS_CSS_KS19_ks19_utlspms(x)             (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_utlspms_SHIFT)) & CSS_CSS_KS19_ks19_utlspms_MASK)

#define CSS_CSS_KS19_ks19_utlsms_MASK            (0x2000000U)
#define CSS_CSS_KS19_ks19_utlsms_SHIFT           (25U)
/*! ks19_utlsms - TLS Master Secret
 */
#define CSS_CSS_KS19_ks19_utlsms(x)              (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_utlsms_SHIFT)) & CSS_CSS_KS19_ks19_utlsms_MASK)

#define CSS_CSS_KS19_ks19_ukgsrc_MASK            (0x4000000U)
#define CSS_CSS_KS19_ks19_ukgsrc_SHIFT           (26U)
/*! ks19_ukgsrc - Supply KEYGEN source
 */
#define CSS_CSS_KS19_ks19_ukgsrc(x)              (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_ukgsrc_SHIFT)) & CSS_CSS_KS19_ks19_ukgsrc_MASK)

#define CSS_CSS_KS19_ks19_uhwo_MASK              (0x8000000U)
#define CSS_CSS_KS19_ks19_uhwo_SHIFT             (27U)
/*! ks19_uhwo - Hardware out key
 */
#define CSS_CSS_KS19_ks19_uhwo(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_uhwo_SHIFT)) & CSS_CSS_KS19_ks19_uhwo_MASK)

#define CSS_CSS_KS19_ks19_uwrpok_MASK            (0x10000000U)
#define CSS_CSS_KS19_ks19_uwrpok_SHIFT           (28U)
/*! ks19_uwrpok - Ok to wrap key
 */
#define CSS_CSS_KS19_ks19_uwrpok(x)              (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_uwrpok_SHIFT)) & CSS_CSS_KS19_ks19_uwrpok_MASK)

#define CSS_CSS_KS19_ks19_uduk_MASK              (0x20000000U)
#define CSS_CSS_KS19_ks19_uduk_SHIFT             (29U)
/*! ks19_uduk - Device Unique Key
 */
#define CSS_CSS_KS19_ks19_uduk(x)                (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_uduk_SHIFT)) & CSS_CSS_KS19_ks19_uduk_MASK)

#define CSS_CSS_KS19_ks19_upprot_MASK            (0xC0000000U)
#define CSS_CSS_KS19_ks19_upprot_SHIFT           (30U)
/*! ks19_upprot - Priviledge level
 */
#define CSS_CSS_KS19_ks19_upprot(x)              (((uint32_t)(((uint32_t)(x)) << CSS_CSS_KS19_ks19_upprot_SHIFT)) & CSS_CSS_KS19_ks19_upprot_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group CSS_Register_Masks */


/* CSS - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral CSS base address */
  #define CSS_BASE                                 (0x50030000u)
  /** Peripheral CSS base address */
  #define CSS_BASE_NS                              (0x40030000u)
  /** Peripheral CSS base pointer */
  #define CSS                                      ((CSS_Type *)CSS_BASE)
  /** Peripheral CSS base pointer */
  #define CSS_NS                                   ((CSS_Type *)CSS_BASE_NS)
  /** Array initializer of CSS peripheral base addresses */
  #define CSS_BASE_ADDRS                           { CSS_BASE }
  /** Array initializer of CSS peripheral base pointers */
  #define CSS_BASE_PTRS                            { CSS }
  /** Array initializer of CSS peripheral base addresses */
  #define CSS_BASE_ADDRS_NS                        { CSS_BASE_NS }
  /** Array initializer of CSS peripheral base pointers */
  #define CSS_BASE_PTRS_NS                         { CSS_NS }
#else
  /** Peripheral CSS base address */
  #define CSS_BASE                                 (0x40030000u)
  /** Peripheral CSS base pointer */
  #define CSS                                      ((CSS_Type *)CSS_BASE)
  /** Array initializer of CSS peripheral base addresses */
  #define CSS_BASE_ADDRS                           { CSS_BASE }
  /** Array initializer of CSS peripheral base pointers */
  #define CSS_BASE_PTRS                            { CSS }
#endif

/*!
 * @}
 */ /* end of group CSS_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CTIMER Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer
 * @{
 */

/** CTIMER - Register Layout Typedef */
typedef struct {
  __IO uint32_t IR;                                /**< Interrupt Register, offset: 0x0 */
  __IO uint32_t TCR;                               /**< Timer Control Register, offset: 0x4 */
  __IO uint32_t TC;                                /**< Timer Counter, offset: 0x8 */
  __IO uint32_t PR;                                /**< Prescale Register, offset: 0xC */
  __IO uint32_t PC;                                /**< Prescale Counter, offset: 0x10 */
  __IO uint32_t MCR;                               /**< Match Control Register, offset: 0x14 */
  __IO uint32_t MR[4];                             /**< Match Register, array offset: 0x18, array step: 0x4 */
  __IO uint32_t CCR;                               /**< Capture Control Register, offset: 0x28 */
  __I  uint32_t CR[4];                             /**< Capture Register, array offset: 0x2C, array step: 0x4 */
  __IO uint32_t EMR;                               /**< External Match Register, offset: 0x3C */
       uint8_t RESERVED_0[48];
  __IO uint32_t CTCR;                              /**< Count Control Register, offset: 0x70 */
  __IO uint32_t PWMC;                              /**< PWM Control Register, offset: 0x74 */
  __IO uint32_t MSR[4];                            /**< Match Shadow Register, array offset: 0x78, array step: 0x4 */
} CTIMER_Type;

/* ----------------------------------------------------------------------------
   -- CTIMER Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CTIMER_Register_Masks CTIMER Register Masks
 * @{
 */

/*! @name IR - Interrupt Register */
/*! @{ */

#define CTIMER_IR_MR0INT_MASK                    (0x1U)
#define CTIMER_IR_MR0INT_SHIFT                   (0U)
/*! MR0INT - Interrupt flag for match channel 0
 */
#define CTIMER_IR_MR0INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK)

#define CTIMER_IR_MR1INT_MASK                    (0x2U)
#define CTIMER_IR_MR1INT_SHIFT                   (1U)
/*! MR1INT - Interrupt flag for match channel 1
 */
#define CTIMER_IR_MR1INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK)

#define CTIMER_IR_MR2INT_MASK                    (0x4U)
#define CTIMER_IR_MR2INT_SHIFT                   (2U)
/*! MR2INT - Interrupt flag for match channel 2
 */
#define CTIMER_IR_MR2INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK)

#define CTIMER_IR_MR3INT_MASK                    (0x8U)
#define CTIMER_IR_MR3INT_SHIFT                   (3U)
/*! MR3INT - Interrupt flag for match channel 3
 */
#define CTIMER_IR_MR3INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK)

#define CTIMER_IR_CR0INT_MASK                    (0x10U)
#define CTIMER_IR_CR0INT_SHIFT                   (4U)
/*! CR0INT - Interrupt flag for capture channel 0 event
 */
#define CTIMER_IR_CR0INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK)

#define CTIMER_IR_CR1INT_MASK                    (0x20U)
#define CTIMER_IR_CR1INT_SHIFT                   (5U)
/*! CR1INT - Interrupt flag for capture channel 1 event
 */
#define CTIMER_IR_CR1INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK)

#define CTIMER_IR_CR2INT_MASK                    (0x40U)
#define CTIMER_IR_CR2INT_SHIFT                   (6U)
/*! CR2INT - Interrupt flag for capture channel 2 event
 */
#define CTIMER_IR_CR2INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK)

#define CTIMER_IR_CR3INT_MASK                    (0x80U)
#define CTIMER_IR_CR3INT_SHIFT                   (7U)
/*! CR3INT - Interrupt flag for capture channel 3 event
 */
#define CTIMER_IR_CR3INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK)
/*! @} */

/*! @name TCR - Timer Control Register */
/*! @{ */

#define CTIMER_TCR_CEN_MASK                      (0x1U)
#define CTIMER_TCR_CEN_SHIFT                     (0U)
/*! CEN - Counter enable
 *  0b0..Disabled. The counters are disabled
 *  0b1..Enabled. The Timer Counter and Prescale Counter are enabled. When the timer is enabled by an external
 *       trigger or globally enabled by the external global start enable register, the CEN bit will automatically be
 *       set to 1
 */
#define CTIMER_TCR_CEN(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK)

#define CTIMER_TCR_CRST_MASK                     (0x2U)
#define CTIMER_TCR_CRST_SHIFT                    (1U)
/*! CRST - Counter reset
 *  0b0..Disabled. Do nothing
 *  0b1..Enabled
 */
#define CTIMER_TCR_CRST(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK)

#define CTIMER_TCR_AGCEN_MASK                    (0x10U)
#define CTIMER_TCR_AGCEN_SHIFT                   (4U)
/*! AGCEN - Allow Global Count Enable
 *  0b0..Not allowed
 *  0b1..Allow input global_enable=1 action to take effect
 */
#define CTIMER_TCR_AGCEN(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_AGCEN_SHIFT)) & CTIMER_TCR_AGCEN_MASK)

#define CTIMER_TCR_ATCEN_MASK                    (0x20U)
#define CTIMER_TCR_ATCEN_SHIFT                   (5U)
/*! ATCEN - Allow Trigger Count Enable
 *  0b0..Not allowed
 *  0b1..Allow input trigger_enable=1 action to take effect
 */
#define CTIMER_TCR_ATCEN(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_ATCEN_SHIFT)) & CTIMER_TCR_ATCEN_MASK)
/*! @} */

/*! @name TC - Timer Counter */
/*! @{ */

#define CTIMER_TC_TCVAL_MASK                     (0xFFFFFFFFU)
#define CTIMER_TC_TCVAL_SHIFT                    (0U)
/*! TCVAL - Timer counter value
 */
#define CTIMER_TC_TCVAL(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK)
/*! @} */

/*! @name PR - Prescale Register */
/*! @{ */

#define CTIMER_PR_PRVAL_MASK                     (0xFFFFFFFFU)
#define CTIMER_PR_PRVAL_SHIFT                    (0U)
/*! PRVAL - Prescale reload value
 */
#define CTIMER_PR_PRVAL(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK)
/*! @} */

/*! @name PC - Prescale Counter */
/*! @{ */

#define CTIMER_PC_PCVAL_MASK                     (0xFFFFFFFFU)
#define CTIMER_PC_PCVAL_SHIFT                    (0U)
/*! PCVAL - Prescale counter value
 */
#define CTIMER_PC_PCVAL(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK)
/*! @} */

/*! @name MCR - Match Control Register */
/*! @{ */

#define CTIMER_MCR_MR0I_MASK                     (0x1U)
#define CTIMER_MCR_MR0I_SHIFT                    (0U)
/*! MR0I - Interrupt on MR0
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_MCR_MR0I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)

#define CTIMER_MCR_MR0R_MASK                     (0x2U)
#define CTIMER_MCR_MR0R_SHIFT                    (1U)
/*! MR0R - Reset on MR0
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_MCR_MR0R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK)

#define CTIMER_MCR_MR0S_MASK                     (0x4U)
#define CTIMER_MCR_MR0S_SHIFT                    (2U)
/*! MR0S - Stop on MR0
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_MCR_MR0S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK)

#define CTIMER_MCR_MR1I_MASK                     (0x8U)
#define CTIMER_MCR_MR1I_SHIFT                    (3U)
/*! MR1I - Interrupt on MR1
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_MCR_MR1I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK)

#define CTIMER_MCR_MR1R_MASK                     (0x10U)
#define CTIMER_MCR_MR1R_SHIFT                    (4U)
/*! MR1R - Reset on MR1
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_MCR_MR1R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK)

#define CTIMER_MCR_MR1S_MASK                     (0x20U)
#define CTIMER_MCR_MR1S_SHIFT                    (5U)
/*! MR1S - Stop on MR1
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_MCR_MR1S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK)

#define CTIMER_MCR_MR2I_MASK                     (0x40U)
#define CTIMER_MCR_MR2I_SHIFT                    (6U)
/*! MR2I - Interrupt on MR2
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_MCR_MR2I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK)

#define CTIMER_MCR_MR2R_MASK                     (0x80U)
#define CTIMER_MCR_MR2R_SHIFT                    (7U)
/*! MR2R - Reset on MR2
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_MCR_MR2R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK)

#define CTIMER_MCR_MR2S_MASK                     (0x100U)
#define CTIMER_MCR_MR2S_SHIFT                    (8U)
/*! MR2S - Stop on MR2
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_MCR_MR2S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK)

#define CTIMER_MCR_MR3I_MASK                     (0x200U)
#define CTIMER_MCR_MR3I_SHIFT                    (9U)
/*! MR3I - Interrupt on MR3
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_MCR_MR3I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK)

#define CTIMER_MCR_MR3R_MASK                     (0x400U)
#define CTIMER_MCR_MR3R_SHIFT                    (10U)
/*! MR3R - Reset on MR3
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_MCR_MR3R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK)

#define CTIMER_MCR_MR3S_MASK                     (0x800U)
#define CTIMER_MCR_MR3S_SHIFT                    (11U)
/*! MR3S - Stop on MR3
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_MCR_MR3S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK)

#define CTIMER_MCR_MR0RL_MASK                    (0x1000000U)
#define CTIMER_MCR_MR0RL_SHIFT                   (24U)
/*! MR0RL - Reload MR0
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_MCR_MR0RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK)

#define CTIMER_MCR_MR1RL_MASK                    (0x2000000U)
#define CTIMER_MCR_MR1RL_SHIFT                   (25U)
/*! MR1RL - Reload MR1
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_MCR_MR1RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK)

#define CTIMER_MCR_MR2RL_MASK                    (0x4000000U)
#define CTIMER_MCR_MR2RL_SHIFT                   (26U)
/*! MR2RL - Reload MR2
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_MCR_MR2RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK)

#define CTIMER_MCR_MR3RL_MASK                    (0x8000000U)
#define CTIMER_MCR_MR3RL_SHIFT                   (27U)
/*! MR3RL - Reload MR3
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_MCR_MR3RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK)
/*! @} */

/*! @name MR - Match Register */
/*! @{ */

#define CTIMER_MR_MATCH_MASK                     (0xFFFFFFFFU)
#define CTIMER_MR_MATCH_SHIFT                    (0U)
/*! MATCH - Timer counter match value
 */
#define CTIMER_MR_MATCH(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK)
/*! @} */

/* The count of CTIMER_MR */
#define CTIMER_MR_COUNT                          (4U)

/*! @name CCR - Capture Control Register */
/*! @{ */

#define CTIMER_CCR_CAP0RE_MASK                   (0x1U)
#define CTIMER_CCR_CAP0RE_SHIFT                  (0U)
/*! CAP0RE - Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_CCR_CAP0RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK)

#define CTIMER_CCR_CAP0FE_MASK                   (0x2U)
#define CTIMER_CCR_CAP0FE_SHIFT                  (1U)
/*! CAP0FE - Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_CCR_CAP0FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK)

#define CTIMER_CCR_CAP0I_MASK                    (0x4U)
#define CTIMER_CCR_CAP0I_SHIFT                   (2U)
/*! CAP0I - Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_CCR_CAP0I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)

#define CTIMER_CCR_CAP1RE_MASK                   (0x8U)
#define CTIMER_CCR_CAP1RE_SHIFT                  (3U)
/*! CAP1RE - Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_CCR_CAP1RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK)

#define CTIMER_CCR_CAP1FE_MASK                   (0x10U)
#define CTIMER_CCR_CAP1FE_SHIFT                  (4U)
/*! CAP1FE - Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_CCR_CAP1FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK)

#define CTIMER_CCR_CAP1I_MASK                    (0x20U)
#define CTIMER_CCR_CAP1I_SHIFT                   (5U)
/*! CAP1I - Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_CCR_CAP1I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK)

#define CTIMER_CCR_CAP2RE_MASK                   (0x40U)
#define CTIMER_CCR_CAP2RE_SHIFT                  (6U)
/*! CAP2RE - Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_CCR_CAP2RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK)

#define CTIMER_CCR_CAP2FE_MASK                   (0x80U)
#define CTIMER_CCR_CAP2FE_SHIFT                  (7U)
/*! CAP2FE - Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_CCR_CAP2FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK)

#define CTIMER_CCR_CAP2I_MASK                    (0x100U)
#define CTIMER_CCR_CAP2I_SHIFT                   (8U)
/*! CAP2I - Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_CCR_CAP2I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK)

#define CTIMER_CCR_CAP3RE_MASK                   (0x200U)
#define CTIMER_CCR_CAP3RE_SHIFT                  (9U)
/*! CAP3RE - Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_CCR_CAP3RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK)

#define CTIMER_CCR_CAP3FE_MASK                   (0x400U)
#define CTIMER_CCR_CAP3FE_SHIFT                  (10U)
/*! CAP3FE - Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_CCR_CAP3FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK)

#define CTIMER_CCR_CAP3I_MASK                    (0x800U)
#define CTIMER_CCR_CAP3I_SHIFT                   (11U)
/*! CAP3I - Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_CCR_CAP3I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK)
/*! @} */

/*! @name CR - Capture Register */
/*! @{ */

#define CTIMER_CR_CAP_MASK                       (0xFFFFFFFFU)
#define CTIMER_CR_CAP_SHIFT                      (0U)
/*! CAP - Timer counter capture value
 */
#define CTIMER_CR_CAP(x)                         (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK)
/*! @} */

/* The count of CTIMER_CR */
#define CTIMER_CR_COUNT                          (4U)

/*! @name EMR - External Match Register */
/*! @{ */

#define CTIMER_EMR_EM0_MASK                      (0x1U)
#define CTIMER_EMR_EM0_SHIFT                     (0U)
/*! EM0 - External Match 0
 */
#define CTIMER_EMR_EM0(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK)

#define CTIMER_EMR_EM1_MASK                      (0x2U)
#define CTIMER_EMR_EM1_SHIFT                     (1U)
/*! EM1 - External Match 1
 */
#define CTIMER_EMR_EM1(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK)

#define CTIMER_EMR_EM2_MASK                      (0x4U)
#define CTIMER_EMR_EM2_SHIFT                     (2U)
/*! EM2 - External Match 2
 */
#define CTIMER_EMR_EM2(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK)

#define CTIMER_EMR_EM3_MASK                      (0x8U)
#define CTIMER_EMR_EM3_SHIFT                     (3U)
/*! EM3 - External Match 3
 */
#define CTIMER_EMR_EM3(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK)

#define CTIMER_EMR_EMC0_MASK                     (0x30U)
#define CTIMER_EMR_EMC0_SHIFT                    (4U)
/*! EMC0 - External Match Control 0
 *  0b00..Do Nothing
 *  0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out)
 *  0b10..Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out)
 *  0b11..Toggle. Toggle the corresponding External Match bit/output
 */
#define CTIMER_EMR_EMC0(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK)

#define CTIMER_EMR_EMC1_MASK                     (0xC0U)
#define CTIMER_EMR_EMC1_SHIFT                    (6U)
/*! EMC1 - External Match Control 1
 *  0b00..Do Nothing
 *  0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out)
 *  0b10..Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out)
 *  0b11..Toggle. Toggle the corresponding External Match bit/output
 */
#define CTIMER_EMR_EMC1(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK)

#define CTIMER_EMR_EMC2_MASK                     (0x300U)
#define CTIMER_EMR_EMC2_SHIFT                    (8U)
/*! EMC2 - External Match Control 2
 *  0b00..Do Nothing
 *  0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out)
 *  0b10..Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out)
 *  0b11..Toggle. Toggle the corresponding External Match bit/output
 */
#define CTIMER_EMR_EMC2(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK)

#define CTIMER_EMR_EMC3_MASK                     (0xC00U)
#define CTIMER_EMR_EMC3_SHIFT                    (10U)
/*! EMC3 - External Match Control 3
 *  0b00..Do Nothing
 *  0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out)
 *  0b10..Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out)
 *  0b11..Toggle. Toggle the corresponding External Match bit/output
 */
#define CTIMER_EMR_EMC3(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK)
/*! @} */

/*! @name CTCR - Count Control Register */
/*! @{ */

#define CTIMER_CTCR_CTMODE_MASK                  (0x3U)
#define CTIMER_CTCR_CTMODE_SHIFT                 (0U)
/*! CTMODE - The Count Control Register (CTCR) is used to select between Timer and Counter mode, and
 *    in Counter mode to select the pin and edge(s) for counting.
 *  0b00..Timer Mode
 *  0b01..Counter Mode rising edge
 *  0b10..Counter Mode falling edge
 *  0b11..Counter Mode dual edge
 */
#define CTIMER_CTCR_CTMODE(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK)

#define CTIMER_CTCR_CINSEL_MASK                  (0xCU)
#define CTIMER_CTCR_CINSEL_SHIFT                 (2U)
/*! CINSEL - Count Input Select
 *  0b00..Channel 0. CAPn[0] for CTIMERn
 *  0b01..Channel 1. CAPn[1] for CTIMERn
 *  0b10..Channel 2. CAPn[2] for CTIMERn
 *  0b11..Channel 3. CAPn[3] for CTIMERn
 */
#define CTIMER_CTCR_CINSEL(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK)

#define CTIMER_CTCR_ENCC_MASK                    (0x10U)
#define CTIMER_CTCR_ENCC_SHIFT                   (4U)
#define CTIMER_CTCR_ENCC(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK)

#define CTIMER_CTCR_SELCC_MASK                   (0xE0U)
#define CTIMER_CTCR_SELCC_SHIFT                  (5U)
/*! SELCC - Edge select
 *  0b000..Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set)
 *  0b001..Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set)
 *  0b010..Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set)
 *  0b011..Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set)
 *  0b100..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set)
 *  0b101..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set)
 */
#define CTIMER_CTCR_SELCC(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK)
/*! @} */

/*! @name PWMC - PWM Control Register */
/*! @{ */

#define CTIMER_PWMC_PWMEN0_MASK                  (0x1U)
#define CTIMER_PWMC_PWMEN0_SHIFT                 (0U)
/*! PWMEN0 - PWM mode enable for channel 0
 *  0b0..Match. CTIMERn_MAT0 is controlled by EM0
 *  0b1..PWM. PWM mode is enabled for CTIMERn_MAT0
 */
#define CTIMER_PWMC_PWMEN0(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK)

#define CTIMER_PWMC_PWMEN1_MASK                  (0x2U)
#define CTIMER_PWMC_PWMEN1_SHIFT                 (1U)
/*! PWMEN1 - PWM mode enable for channel 1
 *  0b0..Match. CTIMERn_MAT01 is controlled by EM1
 *  0b1..PWM. PWM mode is enabled for CTIMERn_MAT1
 */
#define CTIMER_PWMC_PWMEN1(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK)

#define CTIMER_PWMC_PWMEN2_MASK                  (0x4U)
#define CTIMER_PWMC_PWMEN2_SHIFT                 (2U)
/*! PWMEN2 - PWM mode enable for channel 2
 *  0b0..Match. CTIMERn_MAT2 is controlled by EM2
 *  0b1..PWM. PWM mode is enabled for CTIMERn_MAT2
 */
#define CTIMER_PWMC_PWMEN2(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK)

#define CTIMER_PWMC_PWMEN3_MASK                  (0x8U)
#define CTIMER_PWMC_PWMEN3_SHIFT                 (3U)
/*! PWMEN3 - PWM mode enable for channel 3. It is recommended to use match channel 3 to set the PWM cycle
 *  0b0..Match. CTIMERn_MAT3 is controlled by EM3
 *  0b1..PWM. PWM mode is enabled for CT132Bn_MAT3
 */
#define CTIMER_PWMC_PWMEN3(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK)
/*! @} */

/*! @name MSR - Match Shadow Register */
/*! @{ */

#define CTIMER_MSR_MATCH_SHADOW_MASK             (0xFFFFFFFFU)
#define CTIMER_MSR_MATCH_SHADOW_SHIFT            (0U)
/*! MATCH_SHADOW - Timer counter match shadow value
 */
#define CTIMER_MSR_MATCH_SHADOW(x)               (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_MATCH_SHADOW_SHIFT)) & CTIMER_MSR_MATCH_SHADOW_MASK)
/*! @} */

/* The count of CTIMER_MSR */
#define CTIMER_MSR_COUNT                         (4U)


/*!
 * @}
 */ /* end of group CTIMER_Register_Masks */


/* CTIMER - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral CTIMER0 base address */
  #define CTIMER0_BASE                             (0x50008000u)
  /** Peripheral CTIMER0 base address */
  #define CTIMER0_BASE_NS                          (0x40008000u)
  /** Peripheral CTIMER0 base pointer */
  #define CTIMER0                                  ((CTIMER_Type *)CTIMER0_BASE)
  /** Peripheral CTIMER0 base pointer */
  #define CTIMER0_NS                               ((CTIMER_Type *)CTIMER0_BASE_NS)
  /** Peripheral CTIMER1 base address */
  #define CTIMER1_BASE                             (0x50009000u)
  /** Peripheral CTIMER1 base address */
  #define CTIMER1_BASE_NS                          (0x40009000u)
  /** Peripheral CTIMER1 base pointer */
  #define CTIMER1                                  ((CTIMER_Type *)CTIMER1_BASE)
  /** Peripheral CTIMER1 base pointer */
  #define CTIMER1_NS                               ((CTIMER_Type *)CTIMER1_BASE_NS)
  /** Peripheral CTIMER2 base address */
  #define CTIMER2_BASE                             (0x50028000u)
  /** Peripheral CTIMER2 base address */
  #define CTIMER2_BASE_NS                          (0x40028000u)
  /** Peripheral CTIMER2 base pointer */
  #define CTIMER2                                  ((CTIMER_Type *)CTIMER2_BASE)
  /** Peripheral CTIMER2 base pointer */
  #define CTIMER2_NS                               ((CTIMER_Type *)CTIMER2_BASE_NS)
  /** Peripheral CTIMER3 base address */
  #define CTIMER3_BASE                             (0x50029000u)
  /** Peripheral CTIMER3 base address */
  #define CTIMER3_BASE_NS                          (0x40029000u)
  /** Peripheral CTIMER3 base pointer */
  #define CTIMER3                                  ((CTIMER_Type *)CTIMER3_BASE)
  /** Peripheral CTIMER3 base pointer */
  #define CTIMER3_NS                               ((CTIMER_Type *)CTIMER3_BASE_NS)
  /** Peripheral CTIMER4 base address */
  #define CTIMER4_BASE                             (0x5002A000u)
  /** Peripheral CTIMER4 base address */
  #define CTIMER4_BASE_NS                          (0x4002A000u)
  /** Peripheral CTIMER4 base pointer */
  #define CTIMER4                                  ((CTIMER_Type *)CTIMER4_BASE)
  /** Peripheral CTIMER4 base pointer */
  #define CTIMER4_NS                               ((CTIMER_Type *)CTIMER4_BASE_NS)
  /** Array initializer of CTIMER peripheral base addresses */
  #define CTIMER_BASE_ADDRS                        { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE }
  /** Array initializer of CTIMER peripheral base pointers */
  #define CTIMER_BASE_PTRS                         { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 }
  /** Array initializer of CTIMER peripheral base addresses */
  #define CTIMER_BASE_ADDRS_NS                     { CTIMER0_BASE_NS, CTIMER1_BASE_NS, CTIMER2_BASE_NS, CTIMER3_BASE_NS, CTIMER4_BASE_NS }
  /** Array initializer of CTIMER peripheral base pointers */
  #define CTIMER_BASE_PTRS_NS                      { CTIMER0_NS, CTIMER1_NS, CTIMER2_NS, CTIMER3_NS, CTIMER4_NS }
#else
  /** Peripheral CTIMER0 base address */
  #define CTIMER0_BASE                             (0x40008000u)
  /** Peripheral CTIMER0 base pointer */
  #define CTIMER0                                  ((CTIMER_Type *)CTIMER0_BASE)
  /** Peripheral CTIMER1 base address */
  #define CTIMER1_BASE                             (0x40009000u)
  /** Peripheral CTIMER1 base pointer */
  #define CTIMER1                                  ((CTIMER_Type *)CTIMER1_BASE)
  /** Peripheral CTIMER2 base address */
  #define CTIMER2_BASE                             (0x40028000u)
  /** Peripheral CTIMER2 base pointer */
  #define CTIMER2                                  ((CTIMER_Type *)CTIMER2_BASE)
  /** Peripheral CTIMER3 base address */
  #define CTIMER3_BASE                             (0x40029000u)
  /** Peripheral CTIMER3 base pointer */
  #define CTIMER3                                  ((CTIMER_Type *)CTIMER3_BASE)
  /** Peripheral CTIMER4 base address */
  #define CTIMER4_BASE                             (0x4002A000u)
  /** Peripheral CTIMER4 base pointer */
  #define CTIMER4                                  ((CTIMER_Type *)CTIMER4_BASE)
  /** Array initializer of CTIMER peripheral base addresses */
  #define CTIMER_BASE_ADDRS                        { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE }
  /** Array initializer of CTIMER peripheral base pointers */
  #define CTIMER_BASE_PTRS                         { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 }
#endif
/** Interrupt vectors for the CTIMER peripheral type */
#define CTIMER_IRQS                              { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn }

/*!
 * @}
 */ /* end of group CTIMER_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DEBUGGER_MAILBOX Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DEBUGGER_MAILBOX_Peripheral_Access_Layer DEBUGGER_MAILBOX Peripheral Access Layer
 * @{
 */

/** DEBUGGER_MAILBOX - Register Layout Typedef */
typedef struct {
  __IO uint32_t CSW;                               /**< Command and status word, offset: 0x0 */
  __IO uint32_t REQUEST;                           /**< Request Value, offset: 0x4 */
  __IO uint32_t RETURN;                            /**< Return Value, offset: 0x8 */
       uint8_t RESERVED_0[240];
  __I  uint32_t ID;                                /**< Identification, offset: 0xFC */
} DEBUGGER_MAILBOX_Type;

/* ----------------------------------------------------------------------------
   -- DEBUGGER_MAILBOX Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DEBUGGER_MAILBOX_Register_Masks DEBUGGER_MAILBOX Register Masks
 * @{
 */

/*! @name CSW - Command and status word */
/*! @{ */

#define DEBUGGER_MAILBOX_CSW_RESYNCH_REQ_MASK    (0x1U)
#define DEBUGGER_MAILBOX_CSW_RESYNCH_REQ_SHIFT   (0U)
/*! RESYNCH_REQ - Re-synchronization Request
 *  0b0..No Request
 *  0b1..Request for re-synchronization
 */
#define DEBUGGER_MAILBOX_CSW_RESYNCH_REQ(x)      (((uint32_t)(((uint32_t)(x)) << DEBUGGER_MAILBOX_CSW_RESYNCH_REQ_SHIFT)) & DEBUGGER_MAILBOX_CSW_RESYNCH_REQ_MASK)

#define DEBUGGER_MAILBOX_CSW_REQ_PENDING_MASK    (0x2U)
#define DEBUGGER_MAILBOX_CSW_REQ_PENDING_SHIFT   (1U)
/*! REQ_PENDING - Request Pending
 *  0b0..No Request Pending
 *  0b1..Request for Re-synchronization Pending
 */
#define DEBUGGER_MAILBOX_CSW_REQ_PENDING(x)      (((uint32_t)(((uint32_t)(x)) << DEBUGGER_MAILBOX_CSW_REQ_PENDING_SHIFT)) & DEBUGGER_MAILBOX_CSW_REQ_PENDING_MASK)

#define DEBUGGER_MAILBOX_CSW_DBG_OR_ERR_MASK     (0x4U)
#define DEBUGGER_MAILBOX_CSW_DBG_OR_ERR_SHIFT    (2U)
/*! DBG_OR_ERR - Debug Overrun Error
 *  0b0..No Debug Overrun error
 *  0b1..Debug Overrun Error. A debug overrun occurred.
 */
#define DEBUGGER_MAILBOX_CSW_DBG_OR_ERR(x)       (((uint32_t)(((uint32_t)(x)) << DEBUGGER_MAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DEBUGGER_MAILBOX_CSW_DBG_OR_ERR_MASK)

#define DEBUGGER_MAILBOX_CSW_AHB_OR_ERR_MASK     (0x8U)
#define DEBUGGER_MAILBOX_CSW_AHB_OR_ERR_SHIFT    (3U)
/*! AHB_OR_ERR - AHB Overrun Error
 *  0b0..No AHB Overrun Error
 *  0b1..AHB Overrun Error. An AHB overrun occurred.
 */
#define DEBUGGER_MAILBOX_CSW_AHB_OR_ERR(x)       (((uint32_t)(((uint32_t)(x)) << DEBUGGER_MAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DEBUGGER_MAILBOX_CSW_AHB_OR_ERR_MASK)

#define DEBUGGER_MAILBOX_CSW_SOFT_RESET_MASK     (0x10U)
#define DEBUGGER_MAILBOX_CSW_SOFT_RESET_SHIFT    (4U)
/*! SOFT_RESET - Soft Reset
 */
#define DEBUGGER_MAILBOX_CSW_SOFT_RESET(x)       (((uint32_t)(((uint32_t)(x)) << DEBUGGER_MAILBOX_CSW_SOFT_RESET_SHIFT)) & DEBUGGER_MAILBOX_CSW_SOFT_RESET_MASK)

#define DEBUGGER_MAILBOX_CSW_CHIP_RESET_REQ_MASK (0x20U)
#define DEBUGGER_MAILBOX_CSW_CHIP_RESET_REQ_SHIFT (5U)
/*! CHIP_RESET_REQ - Chip Reset Request
 */
#define DEBUGGER_MAILBOX_CSW_CHIP_RESET_REQ(x)   (((uint32_t)(((uint32_t)(x)) << DEBUGGER_MAILBOX_CSW_CHIP_RESET_REQ_SHIFT)) & DEBUGGER_MAILBOX_CSW_CHIP_RESET_REQ_MASK)
/*! @} */

/*! @name REQUEST - Request Value */
/*! @{ */

#define DEBUGGER_MAILBOX_REQUEST_REQUEST_MASK    (0xFFFFFFFFU)
#define DEBUGGER_MAILBOX_REQUEST_REQUEST_SHIFT   (0U)
/*! REQUEST - Request Value
 */
#define DEBUGGER_MAILBOX_REQUEST_REQUEST(x)      (((uint32_t)(((uint32_t)(x)) << DEBUGGER_MAILBOX_REQUEST_REQUEST_SHIFT)) & DEBUGGER_MAILBOX_REQUEST_REQUEST_MASK)
/*! @} */

/*! @name RETURN - Return Value */
/*! @{ */

#define DEBUGGER_MAILBOX_RETURN_RET_MASK         (0xFFFFFFFFU)
#define DEBUGGER_MAILBOX_RETURN_RET_SHIFT        (0U)
/*! RET - Return Value
 */
#define DEBUGGER_MAILBOX_RETURN_RET(x)           (((uint32_t)(((uint32_t)(x)) << DEBUGGER_MAILBOX_RETURN_RET_SHIFT)) & DEBUGGER_MAILBOX_RETURN_RET_MASK)
/*! @} */

/*! @name ID - Identification */
/*! @{ */

#define DEBUGGER_MAILBOX_ID_ID_MASK              (0xFFFFFFFFU)
#define DEBUGGER_MAILBOX_ID_ID_SHIFT             (0U)
/*! ID - Identification Value
 */
#define DEBUGGER_MAILBOX_ID_ID(x)                (((uint32_t)(((uint32_t)(x)) << DEBUGGER_MAILBOX_ID_ID_SHIFT)) & DEBUGGER_MAILBOX_ID_ID_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group DEBUGGER_MAILBOX_Register_Masks */


/* DEBUGGER_MAILBOX - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral DEBUGGER_MAILBOX0 base address */
  #define DEBUGGER_MAILBOX0_BASE                   (0x5009C000u)
  /** Peripheral DEBUGGER_MAILBOX0 base address */
  #define DEBUGGER_MAILBOX0_BASE_NS                (0x4009C000u)
  /** Peripheral DEBUGGER_MAILBOX0 base pointer */
  #define DEBUGGER_MAILBOX0                        ((DEBUGGER_MAILBOX_Type *)DEBUGGER_MAILBOX0_BASE)
  /** Peripheral DEBUGGER_MAILBOX0 base pointer */
  #define DEBUGGER_MAILBOX0_NS                     ((DEBUGGER_MAILBOX_Type *)DEBUGGER_MAILBOX0_BASE_NS)
  /** Array initializer of DEBUGGER_MAILBOX peripheral base addresses */
  #define DEBUGGER_MAILBOX_BASE_ADDRS              { DEBUGGER_MAILBOX0_BASE }
  /** Array initializer of DEBUGGER_MAILBOX peripheral base pointers */
  #define DEBUGGER_MAILBOX_BASE_PTRS               { DEBUGGER_MAILBOX0 }
  /** Array initializer of DEBUGGER_MAILBOX peripheral base addresses */
  #define DEBUGGER_MAILBOX_BASE_ADDRS_NS           { DEBUGGER_MAILBOX0_BASE_NS }
  /** Array initializer of DEBUGGER_MAILBOX peripheral base pointers */
  #define DEBUGGER_MAILBOX_BASE_PTRS_NS            { DEBUGGER_MAILBOX0_NS }
#else
  /** Peripheral DEBUGGER_MAILBOX0 base address */
  #define DEBUGGER_MAILBOX0_BASE                   (0x4009C000u)
  /** Peripheral DEBUGGER_MAILBOX0 base pointer */
  #define DEBUGGER_MAILBOX0                        ((DEBUGGER_MAILBOX_Type *)DEBUGGER_MAILBOX0_BASE)
  /** Array initializer of DEBUGGER_MAILBOX peripheral base addresses */
  #define DEBUGGER_MAILBOX_BASE_ADDRS              { DEBUGGER_MAILBOX0_BASE }
  /** Array initializer of DEBUGGER_MAILBOX peripheral base pointers */
  #define DEBUGGER_MAILBOX_BASE_PTRS               { DEBUGGER_MAILBOX0 }
#endif

/*!
 * @}
 */ /* end of group DEBUGGER_MAILBOX_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DMA Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
 * @{
 */

/** DMA - Register Layout Typedef */
typedef struct {
  __IO uint32_t CTRL;                              /**< DMA control, offset: 0x0 */
  __I  uint32_t INTSTAT;                           /**< Interrupt status, offset: 0x4 */
  __IO uint32_t SRAMBASE;                          /**< SRAM address of the channel configuration table, offset: 0x8 */
       uint8_t RESERVED_0[20];
  struct {                                         /* offset: 0x20, array step: 0x60 */
    __IO uint32_t ENABLESET;                         /**< Channel Enable read and set for all DMA channels, array offset: 0x20, array step: 0x60 */
    __IO uint32_t ENABLESET1;                        /**< Channel Enable read and set for all DMA channels, array offset: 0x24, array step: 0x60 */
    __IO uint32_t ENABLECLR;                         /**< Channel Enable Clear for all DMA channels, array offset: 0x28, array step: 0x60 */
    __IO uint32_t ENABLECLR1;                        /**< Channel Enable Clear for all DMA channels, array offset: 0x2C, array step: 0x60 */
    __I  uint32_t ACTIVE;                            /**< Channel Active status for all DMA channels, array offset: 0x30, array step: 0x60 */
    __I  uint32_t ACTIVE1;                           /**< Channel Active status for all DMA channels, array offset: 0x34, array step: 0x60 */
    __I  uint32_t BUSY;                              /**< Channel Busy status for all DMA channels, array offset: 0x38, array step: 0x60 */
    __I  uint32_t BUSY1;                             /**< Channel Busy status for all DMA channels, array offset: 0x3C, array step: 0x60 */
    __IO uint32_t ERRINT;                            /**< Error Interrupt status for all DMA channels, array offset: 0x40, array step: 0x60 */
    __IO uint32_t ERRINT1;                           /**< Error Interrupt status for all DMA channels, array offset: 0x44, array step: 0x60 */
    __IO uint32_t INTENSET;                          /**< Interrupt Enable read and Set for all DMA channels, array offset: 0x48, array step: 0x60 */
    __IO uint32_t INTENSET1;                         /**< Interrupt Enable read and Set for all DMA channels, array offset: 0x4C, array step: 0x60 */
    __O  uint32_t INTENCLR;                          /**< Interrupt Enable Clear for all DMA channels, array offset: 0x50, array step: 0x60 */
    __O  uint32_t INTENCLR1;                         /**< Interrupt Enable Clear for all DMA channels, array offset: 0x54, array step: 0x60 */
    __IO uint32_t INTA;                              /**< Interrupt A status for all DMA channels, array offset: 0x58, array step: 0x60 */
    __IO uint32_t INTA1;                             /**< Interrupt A status for all DMA channels, array offset: 0x5C, array step: 0x60 */
    __IO uint32_t INTB;                              /**< Interrupt B status for all DMA channels, array offset: 0x60, array step: 0x60 */
    __IO uint32_t INTB1;                             /**< Interrupt B status for all DMA channels, array offset: 0x64, array step: 0x60 */
    __O  uint32_t SETVALID;                          /**< Set ValidPending control bits for all DMA channels, array offset: 0x68, array step: 0x60 */
    __O  uint32_t SETVALID1;                         /**< Set ValidPending control bits for all DMA channels, array offset: 0x6C, array step: 0x60 */
    __O  uint32_t SETTRIG;                           /**< Set Trigger control bits for all DMA channels, array offset: 0x70, array step: 0x60 */
    __O  uint32_t SETTRIG1;                          /**< Set Trigger control bits for all DMA channels, array offset: 0x74, array step: 0x60 */
    __O  uint32_t ABORT;                             /**< Channel Abort control for all DMA channels, array offset: 0x78, array step: 0x60 */
    __O  uint32_t ABORT1;                            /**< Channel Abort control for all DMA channels, array offset: 0x7C, array step: 0x60 */
  } COMMON[1];
       uint8_t RESERVED_1[896];
  struct {                                         /* offset: 0x400, array step: 0x10 */
    __IO uint32_t CFG;                               /**< Configuration register for DMA channel, array offset: 0x400, array step: 0x10 */
    __I  uint32_t CTLSTAT;                           /**< Control and status register for DMA channel, array offset: 0x404, array step: 0x10 */
    __IO uint32_t XFERCFG;                           /**< Transfer configuration register for DMA channel, array offset: 0x408, array step: 0x10 */
         uint8_t RESERVED_0[4];
  } CHANNEL[52];
} DMA_Type;

/* ----------------------------------------------------------------------------
   -- DMA Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_Register_Masks DMA Register Masks
 * @{
 */

/*! @name CTRL - DMA control */
/*! @{ */

#define DMA_CTRL_ENABLE_MASK                     (0x1U)
#define DMA_CTRL_ENABLE_SHIFT                    (0U)
/*! ENABLE - DMA controller master enable.
 *  0b0..DMA controller is disabled.
 *  0b1..Enabled.
 */
#define DMA_CTRL_ENABLE(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK)
/*! @} */

/*! @name INTSTAT - Interrupt status */
/*! @{ */

#define DMA_INTSTAT_ACTIVEINT_MASK               (0x2U)
#define DMA_INTSTAT_ACTIVEINT_SHIFT              (1U)
/*! ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending.
 *  0b0..No enabled interrupts are pending.
 *  0b1..At least one enabled interrupt is pending.
 */
#define DMA_INTSTAT_ACTIVEINT(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK)

#define DMA_INTSTAT_ACTIVEERRINT_MASK            (0x4U)
#define DMA_INTSTAT_ACTIVEERRINT_SHIFT           (2U)
/*! ACTIVEERRINT - Summarizes whether any error interrupts are pending.
 *  0b0..No error interrupts are pending.
 *  0b1..At least one error interrupt is pending.
 */
#define DMA_INTSTAT_ACTIVEERRINT(x)              (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK)
/*! @} */

/*! @name SRAMBASE - SRAM address of the channel configuration table */
/*! @{ */

#define DMA_SRAMBASE_OFFSET_MASK                 (0xFFFFFF00U)  /* Merged from fields with different position or width, of widths (22, 24), largest definition used */
#define DMA_SRAMBASE_OFFSET_SHIFT                (8U)
/*! OFFSET - Offset
 */
#define DMA_SRAMBASE_OFFSET(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK)  /* Merged from fields with different position or width, of widths (22, 24), largest definition used */
/*! @} */

/*! @name COMMON_ENABLESET - Channel Enable read and set for all DMA channels */
/*! @{ */

#define DMA_COMMON_ENABLESET_ENABLE0_MASK        (0x1U)
#define DMA_COMMON_ENABLESET_ENABLE0_SHIFT       (0U)
/*! ENABLE0 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE0(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE0_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE0_MASK)

#define DMA_COMMON_ENABLESET_ENABLE1_MASK        (0x2U)
#define DMA_COMMON_ENABLESET_ENABLE1_SHIFT       (1U)
/*! ENABLE1 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE1(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE1_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE1_MASK)

#define DMA_COMMON_ENABLESET_ENABLE2_MASK        (0x4U)
#define DMA_COMMON_ENABLESET_ENABLE2_SHIFT       (2U)
/*! ENABLE2 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE2(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE2_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE2_MASK)

#define DMA_COMMON_ENABLESET_ENABLE3_MASK        (0x8U)
#define DMA_COMMON_ENABLESET_ENABLE3_SHIFT       (3U)
/*! ENABLE3 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE3(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE3_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE3_MASK)

#define DMA_COMMON_ENABLESET_ENABLE4_MASK        (0x10U)
#define DMA_COMMON_ENABLESET_ENABLE4_SHIFT       (4U)
/*! ENABLE4 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE4(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE4_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE4_MASK)

#define DMA_COMMON_ENABLESET_ENABLE5_MASK        (0x20U)
#define DMA_COMMON_ENABLESET_ENABLE5_SHIFT       (5U)
/*! ENABLE5 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE5(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE5_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE5_MASK)

#define DMA_COMMON_ENABLESET_ENABLE6_MASK        (0x40U)
#define DMA_COMMON_ENABLESET_ENABLE6_SHIFT       (6U)
/*! ENABLE6 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE6(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE6_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE6_MASK)

#define DMA_COMMON_ENABLESET_ENABLE7_MASK        (0x80U)
#define DMA_COMMON_ENABLESET_ENABLE7_SHIFT       (7U)
/*! ENABLE7 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE7(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE7_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE7_MASK)

#define DMA_COMMON_ENABLESET_ENABLE8_MASK        (0x100U)
#define DMA_COMMON_ENABLESET_ENABLE8_SHIFT       (8U)
/*! ENABLE8 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE8(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE8_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE8_MASK)

#define DMA_COMMON_ENABLESET_ENABLE9_MASK        (0x200U)
#define DMA_COMMON_ENABLESET_ENABLE9_SHIFT       (9U)
/*! ENABLE9 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE9(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE9_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE9_MASK)

#define DMA_COMMON_ENABLESET_ENABLE10_MASK       (0x400U)
#define DMA_COMMON_ENABLESET_ENABLE10_SHIFT      (10U)
/*! ENABLE10 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE10(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE10_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE10_MASK)

#define DMA_COMMON_ENABLESET_ENABLE11_MASK       (0x800U)
#define DMA_COMMON_ENABLESET_ENABLE11_SHIFT      (11U)
/*! ENABLE11 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE11(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE11_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE11_MASK)

#define DMA_COMMON_ENABLESET_ENABLE12_MASK       (0x1000U)
#define DMA_COMMON_ENABLESET_ENABLE12_SHIFT      (12U)
/*! ENABLE12 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE12(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE12_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE12_MASK)

#define DMA_COMMON_ENABLESET_ENABLE13_MASK       (0x2000U)
#define DMA_COMMON_ENABLESET_ENABLE13_SHIFT      (13U)
/*! ENABLE13 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE13(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE13_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE13_MASK)

#define DMA_COMMON_ENABLESET_ENABLE14_MASK       (0x4000U)
#define DMA_COMMON_ENABLESET_ENABLE14_SHIFT      (14U)
/*! ENABLE14 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE14(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE14_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE14_MASK)

#define DMA_COMMON_ENABLESET_ENABLE15_MASK       (0x8000U)
#define DMA_COMMON_ENABLESET_ENABLE15_SHIFT      (15U)
/*! ENABLE15 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE15(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE15_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE15_MASK)

#define DMA_COMMON_ENABLESET_ENABLE16_MASK       (0x10000U)
#define DMA_COMMON_ENABLESET_ENABLE16_SHIFT      (16U)
/*! ENABLE16 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE16(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE16_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE16_MASK)

#define DMA_COMMON_ENABLESET_ENABLE17_MASK       (0x20000U)
#define DMA_COMMON_ENABLESET_ENABLE17_SHIFT      (17U)
/*! ENABLE17 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE17(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE17_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE17_MASK)

#define DMA_COMMON_ENABLESET_ENABLE18_MASK       (0x40000U)
#define DMA_COMMON_ENABLESET_ENABLE18_SHIFT      (18U)
/*! ENABLE18 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE18(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE18_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE18_MASK)

#define DMA_COMMON_ENABLESET_ENABLE19_MASK       (0x80000U)
#define DMA_COMMON_ENABLESET_ENABLE19_SHIFT      (19U)
/*! ENABLE19 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE19(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE19_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE19_MASK)

#define DMA_COMMON_ENABLESET_ENABLE20_MASK       (0x100000U)
#define DMA_COMMON_ENABLESET_ENABLE20_SHIFT      (20U)
/*! ENABLE20 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE20(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE20_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE20_MASK)

#define DMA_COMMON_ENABLESET_ENABLE21_MASK       (0x200000U)
#define DMA_COMMON_ENABLESET_ENABLE21_SHIFT      (21U)
/*! ENABLE21 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE21(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE21_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE21_MASK)

#define DMA_COMMON_ENABLESET_ENABLE22_MASK       (0x400000U)
#define DMA_COMMON_ENABLESET_ENABLE22_SHIFT      (22U)
/*! ENABLE22 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE22(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE22_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE22_MASK)

#define DMA_COMMON_ENABLESET_ENABLE23_MASK       (0x800000U)
#define DMA_COMMON_ENABLESET_ENABLE23_SHIFT      (23U)
/*! ENABLE23 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE23(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE23_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE23_MASK)

#define DMA_COMMON_ENABLESET_ENABLE24_MASK       (0x1000000U)
#define DMA_COMMON_ENABLESET_ENABLE24_SHIFT      (24U)
/*! ENABLE24 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE24(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE24_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE24_MASK)

#define DMA_COMMON_ENABLESET_ENABLE25_MASK       (0x2000000U)
#define DMA_COMMON_ENABLESET_ENABLE25_SHIFT      (25U)
/*! ENABLE25 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE25(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE25_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE25_MASK)

#define DMA_COMMON_ENABLESET_ENABLE26_MASK       (0x4000000U)
#define DMA_COMMON_ENABLESET_ENABLE26_SHIFT      (26U)
/*! ENABLE26 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE26(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE26_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE26_MASK)

#define DMA_COMMON_ENABLESET_ENABLE27_MASK       (0x8000000U)
#define DMA_COMMON_ENABLESET_ENABLE27_SHIFT      (27U)
/*! ENABLE27 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE27(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE27_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE27_MASK)

#define DMA_COMMON_ENABLESET_ENABLE28_MASK       (0x10000000U)
#define DMA_COMMON_ENABLESET_ENABLE28_SHIFT      (28U)
/*! ENABLE28 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE28(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE28_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE28_MASK)

#define DMA_COMMON_ENABLESET_ENABLE29_MASK       (0x20000000U)
#define DMA_COMMON_ENABLESET_ENABLE29_SHIFT      (29U)
/*! ENABLE29 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE29(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE29_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE29_MASK)

#define DMA_COMMON_ENABLESET_ENABLE30_MASK       (0x40000000U)
#define DMA_COMMON_ENABLESET_ENABLE30_SHIFT      (30U)
/*! ENABLE30 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE30(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE30_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE30_MASK)

#define DMA_COMMON_ENABLESET_ENABLE31_MASK       (0x80000000U)
#define DMA_COMMON_ENABLESET_ENABLE31_SHIFT      (31U)
/*! ENABLE31 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE31(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE31_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE31_MASK)
/*! @} */

/* The count of DMA_COMMON_ENABLESET */
#define DMA_COMMON_ENABLESET_COUNT               (1U)

/*! @name COMMON_ENABLESET1 - Channel Enable read and set for all DMA channels */
/*! @{ */

#define DMA_COMMON_ENABLESET1_ENABLE32_MASK      (0x1U)
#define DMA_COMMON_ENABLESET1_ENABLE32_SHIFT     (0U)
/*! ENABLE32 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET1_ENABLE32(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE32_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE32_MASK)

#define DMA_COMMON_ENABLESET1_ENABLE33_MASK      (0x2U)
#define DMA_COMMON_ENABLESET1_ENABLE33_SHIFT     (1U)
/*! ENABLE33 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET1_ENABLE33(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE33_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE33_MASK)

#define DMA_COMMON_ENABLESET1_ENABLE34_MASK      (0x4U)
#define DMA_COMMON_ENABLESET1_ENABLE34_SHIFT     (2U)
/*! ENABLE34 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET1_ENABLE34(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE34_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE34_MASK)

#define DMA_COMMON_ENABLESET1_ENABLE35_MASK      (0x8U)
#define DMA_COMMON_ENABLESET1_ENABLE35_SHIFT     (3U)
/*! ENABLE35 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET1_ENABLE35(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE35_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE35_MASK)

#define DMA_COMMON_ENABLESET1_ENABLE36_MASK      (0x10U)
#define DMA_COMMON_ENABLESET1_ENABLE36_SHIFT     (4U)
/*! ENABLE36 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET1_ENABLE36(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE36_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE36_MASK)

#define DMA_COMMON_ENABLESET1_ENABLE37_MASK      (0x20U)
#define DMA_COMMON_ENABLESET1_ENABLE37_SHIFT     (5U)
/*! ENABLE37 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET1_ENABLE37(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE37_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE37_MASK)

#define DMA_COMMON_ENABLESET1_ENABLE38_MASK      (0x40U)
#define DMA_COMMON_ENABLESET1_ENABLE38_SHIFT     (6U)
/*! ENABLE38 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET1_ENABLE38(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE38_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE38_MASK)

#define DMA_COMMON_ENABLESET1_ENABLE39_MASK      (0x80U)
#define DMA_COMMON_ENABLESET1_ENABLE39_SHIFT     (7U)
/*! ENABLE39 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET1_ENABLE39(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE39_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE39_MASK)

#define DMA_COMMON_ENABLESET1_ENABLE40_MASK      (0x100U)
#define DMA_COMMON_ENABLESET1_ENABLE40_SHIFT     (8U)
/*! ENABLE40 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET1_ENABLE40(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE40_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE40_MASK)

#define DMA_COMMON_ENABLESET1_ENABLE41_MASK      (0x200U)
#define DMA_COMMON_ENABLESET1_ENABLE41_SHIFT     (9U)
/*! ENABLE41 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET1_ENABLE41(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE41_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE41_MASK)

#define DMA_COMMON_ENABLESET1_ENABLE42_MASK      (0x400U)
#define DMA_COMMON_ENABLESET1_ENABLE42_SHIFT     (10U)
/*! ENABLE42 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET1_ENABLE42(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE42_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE42_MASK)

#define DMA_COMMON_ENABLESET1_ENABLE43_MASK      (0x800U)
#define DMA_COMMON_ENABLESET1_ENABLE43_SHIFT     (11U)
/*! ENABLE43 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET1_ENABLE43(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE43_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE43_MASK)

#define DMA_COMMON_ENABLESET1_ENABLE44_MASK      (0x1000U)
#define DMA_COMMON_ENABLESET1_ENABLE44_SHIFT     (12U)
/*! ENABLE44 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET1_ENABLE44(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE44_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE44_MASK)

#define DMA_COMMON_ENABLESET1_ENABLE45_MASK      (0x2000U)
#define DMA_COMMON_ENABLESET1_ENABLE45_SHIFT     (13U)
/*! ENABLE45 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET1_ENABLE45(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE45_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE45_MASK)

#define DMA_COMMON_ENABLESET1_ENABLE46_MASK      (0x4000U)
#define DMA_COMMON_ENABLESET1_ENABLE46_SHIFT     (14U)
/*! ENABLE46 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET1_ENABLE46(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE46_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE46_MASK)

#define DMA_COMMON_ENABLESET1_ENABLE47_MASK      (0x8000U)
#define DMA_COMMON_ENABLESET1_ENABLE47_SHIFT     (15U)
/*! ENABLE47 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET1_ENABLE47(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE47_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE47_MASK)

#define DMA_COMMON_ENABLESET1_ENABLE48_MASK      (0x10000U)
#define DMA_COMMON_ENABLESET1_ENABLE48_SHIFT     (16U)
/*! ENABLE48 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET1_ENABLE48(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE48_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE48_MASK)

#define DMA_COMMON_ENABLESET1_ENABLE49_MASK      (0x20000U)
#define DMA_COMMON_ENABLESET1_ENABLE49_SHIFT     (17U)
/*! ENABLE49 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET1_ENABLE49(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE49_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE49_MASK)

#define DMA_COMMON_ENABLESET1_ENABLE50_MASK      (0x40000U)
#define DMA_COMMON_ENABLESET1_ENABLE50_SHIFT     (18U)
/*! ENABLE50 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET1_ENABLE50(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE50_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE50_MASK)

#define DMA_COMMON_ENABLESET1_ENABLE51_MASK      (0x80000U)
#define DMA_COMMON_ENABLESET1_ENABLE51_SHIFT     (19U)
/*! ENABLE51 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET1_ENABLE51(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE51_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE51_MASK)
/*! @} */

/* The count of DMA_COMMON_ENABLESET1 */
#define DMA_COMMON_ENABLESET1_COUNT              (1U)

/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels */
/*! @{ */

#define DMA_COMMON_ENABLECLR_CLR0_MASK           (0x1U)
#define DMA_COMMON_ENABLECLR_CLR0_SHIFT          (0U)
/*! CLR0 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR0(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR0_SHIFT)) & DMA_COMMON_ENABLECLR_CLR0_MASK)

#define DMA_COMMON_ENABLECLR_CLR1_MASK           (0x2U)
#define DMA_COMMON_ENABLECLR_CLR1_SHIFT          (1U)
/*! CLR1 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR1(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR1_SHIFT)) & DMA_COMMON_ENABLECLR_CLR1_MASK)

#define DMA_COMMON_ENABLECLR_CLR2_MASK           (0x4U)
#define DMA_COMMON_ENABLECLR_CLR2_SHIFT          (2U)
/*! CLR2 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR2(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR2_SHIFT)) & DMA_COMMON_ENABLECLR_CLR2_MASK)

#define DMA_COMMON_ENABLECLR_CLR3_MASK           (0x8U)
#define DMA_COMMON_ENABLECLR_CLR3_SHIFT          (3U)
/*! CLR3 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR3(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR3_SHIFT)) & DMA_COMMON_ENABLECLR_CLR3_MASK)

#define DMA_COMMON_ENABLECLR_CLR4_MASK           (0x10U)
#define DMA_COMMON_ENABLECLR_CLR4_SHIFT          (4U)
/*! CLR4 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR4(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR4_SHIFT)) & DMA_COMMON_ENABLECLR_CLR4_MASK)

#define DMA_COMMON_ENABLECLR_CLR5_MASK           (0x20U)
#define DMA_COMMON_ENABLECLR_CLR5_SHIFT          (5U)
/*! CLR5 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR5(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR5_SHIFT)) & DMA_COMMON_ENABLECLR_CLR5_MASK)

#define DMA_COMMON_ENABLECLR_CLR6_MASK           (0x40U)
#define DMA_COMMON_ENABLECLR_CLR6_SHIFT          (6U)
/*! CLR6 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR6(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR6_SHIFT)) & DMA_COMMON_ENABLECLR_CLR6_MASK)

#define DMA_COMMON_ENABLECLR_CLR7_MASK           (0x80U)
#define DMA_COMMON_ENABLECLR_CLR7_SHIFT          (7U)
/*! CLR7 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR7(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR7_SHIFT)) & DMA_COMMON_ENABLECLR_CLR7_MASK)

#define DMA_COMMON_ENABLECLR_CLR8_MASK           (0x100U)
#define DMA_COMMON_ENABLECLR_CLR8_SHIFT          (8U)
/*! CLR8 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR8(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR8_SHIFT)) & DMA_COMMON_ENABLECLR_CLR8_MASK)

#define DMA_COMMON_ENABLECLR_CLR9_MASK           (0x200U)
#define DMA_COMMON_ENABLECLR_CLR9_SHIFT          (9U)
/*! CLR9 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR9(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR9_SHIFT)) & DMA_COMMON_ENABLECLR_CLR9_MASK)

#define DMA_COMMON_ENABLECLR_CLR10_MASK          (0x400U)
#define DMA_COMMON_ENABLECLR_CLR10_SHIFT         (10U)
/*! CLR10 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR10(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR10_SHIFT)) & DMA_COMMON_ENABLECLR_CLR10_MASK)

#define DMA_COMMON_ENABLECLR_CLR11_MASK          (0x800U)
#define DMA_COMMON_ENABLECLR_CLR11_SHIFT         (11U)
/*! CLR11 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR11(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR11_SHIFT)) & DMA_COMMON_ENABLECLR_CLR11_MASK)

#define DMA_COMMON_ENABLECLR_CLR12_MASK          (0x1000U)
#define DMA_COMMON_ENABLECLR_CLR12_SHIFT         (12U)
/*! CLR12 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR12(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR12_SHIFT)) & DMA_COMMON_ENABLECLR_CLR12_MASK)

#define DMA_COMMON_ENABLECLR_CLR13_MASK          (0x2000U)
#define DMA_COMMON_ENABLECLR_CLR13_SHIFT         (13U)
/*! CLR13 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR13(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR13_SHIFT)) & DMA_COMMON_ENABLECLR_CLR13_MASK)

#define DMA_COMMON_ENABLECLR_CLR14_MASK          (0x4000U)
#define DMA_COMMON_ENABLECLR_CLR14_SHIFT         (14U)
/*! CLR14 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR14(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR14_SHIFT)) & DMA_COMMON_ENABLECLR_CLR14_MASK)

#define DMA_COMMON_ENABLECLR_CLR15_MASK          (0x8000U)
#define DMA_COMMON_ENABLECLR_CLR15_SHIFT         (15U)
/*! CLR15 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR15(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR15_SHIFT)) & DMA_COMMON_ENABLECLR_CLR15_MASK)

#define DMA_COMMON_ENABLECLR_CLR16_MASK          (0x10000U)
#define DMA_COMMON_ENABLECLR_CLR16_SHIFT         (16U)
/*! CLR16 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR16(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR16_SHIFT)) & DMA_COMMON_ENABLECLR_CLR16_MASK)

#define DMA_COMMON_ENABLECLR_CLR17_MASK          (0x20000U)
#define DMA_COMMON_ENABLECLR_CLR17_SHIFT         (17U)
/*! CLR17 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR17(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR17_SHIFT)) & DMA_COMMON_ENABLECLR_CLR17_MASK)

#define DMA_COMMON_ENABLECLR_CLR18_MASK          (0x40000U)
#define DMA_COMMON_ENABLECLR_CLR18_SHIFT         (18U)
/*! CLR18 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR18(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR18_SHIFT)) & DMA_COMMON_ENABLECLR_CLR18_MASK)

#define DMA_COMMON_ENABLECLR_CLR19_MASK          (0x80000U)
#define DMA_COMMON_ENABLECLR_CLR19_SHIFT         (19U)
/*! CLR19 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR19(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR19_SHIFT)) & DMA_COMMON_ENABLECLR_CLR19_MASK)

#define DMA_COMMON_ENABLECLR_CLR20_MASK          (0x100000U)
#define DMA_COMMON_ENABLECLR_CLR20_SHIFT         (20U)
/*! CLR20 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR20(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR20_SHIFT)) & DMA_COMMON_ENABLECLR_CLR20_MASK)

#define DMA_COMMON_ENABLECLR_CLR21_MASK          (0x200000U)
#define DMA_COMMON_ENABLECLR_CLR21_SHIFT         (21U)
/*! CLR21 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR21(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR21_SHIFT)) & DMA_COMMON_ENABLECLR_CLR21_MASK)

#define DMA_COMMON_ENABLECLR_CLR22_MASK          (0x400000U)
#define DMA_COMMON_ENABLECLR_CLR22_SHIFT         (22U)
/*! CLR22 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR22(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR22_SHIFT)) & DMA_COMMON_ENABLECLR_CLR22_MASK)

#define DMA_COMMON_ENABLECLR_CLR23_MASK          (0x800000U)
#define DMA_COMMON_ENABLECLR_CLR23_SHIFT         (23U)
/*! CLR23 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR23(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR23_SHIFT)) & DMA_COMMON_ENABLECLR_CLR23_MASK)

#define DMA_COMMON_ENABLECLR_CLR24_MASK          (0x1000000U)
#define DMA_COMMON_ENABLECLR_CLR24_SHIFT         (24U)
/*! CLR24 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR24(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR24_SHIFT)) & DMA_COMMON_ENABLECLR_CLR24_MASK)

#define DMA_COMMON_ENABLECLR_CLR25_MASK          (0x2000000U)
#define DMA_COMMON_ENABLECLR_CLR25_SHIFT         (25U)
/*! CLR25 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR25(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR25_SHIFT)) & DMA_COMMON_ENABLECLR_CLR25_MASK)

#define DMA_COMMON_ENABLECLR_CLR26_MASK          (0x4000000U)
#define DMA_COMMON_ENABLECLR_CLR26_SHIFT         (26U)
/*! CLR26 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR26(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR26_SHIFT)) & DMA_COMMON_ENABLECLR_CLR26_MASK)

#define DMA_COMMON_ENABLECLR_CLR27_MASK          (0x8000000U)
#define DMA_COMMON_ENABLECLR_CLR27_SHIFT         (27U)
/*! CLR27 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR27(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR27_SHIFT)) & DMA_COMMON_ENABLECLR_CLR27_MASK)

#define DMA_COMMON_ENABLECLR_CLR28_MASK          (0x10000000U)
#define DMA_COMMON_ENABLECLR_CLR28_SHIFT         (28U)
/*! CLR28 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR28(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR28_SHIFT)) & DMA_COMMON_ENABLECLR_CLR28_MASK)

#define DMA_COMMON_ENABLECLR_CLR29_MASK          (0x20000000U)
#define DMA_COMMON_ENABLECLR_CLR29_SHIFT         (29U)
/*! CLR29 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR29(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR29_SHIFT)) & DMA_COMMON_ENABLECLR_CLR29_MASK)

#define DMA_COMMON_ENABLECLR_CLR30_MASK          (0x40000000U)
#define DMA_COMMON_ENABLECLR_CLR30_SHIFT         (30U)
/*! CLR30 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR30(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR30_SHIFT)) & DMA_COMMON_ENABLECLR_CLR30_MASK)

#define DMA_COMMON_ENABLECLR_CLR31_MASK          (0x80000000U)
#define DMA_COMMON_ENABLECLR_CLR31_SHIFT         (31U)
/*! CLR31 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR31(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR31_SHIFT)) & DMA_COMMON_ENABLECLR_CLR31_MASK)
/*! @} */

/* The count of DMA_COMMON_ENABLECLR */
#define DMA_COMMON_ENABLECLR_COUNT               (1U)

/*! @name COMMON_ENABLECLR1 - Channel Enable Clear for all DMA channels */
/*! @{ */

#define DMA_COMMON_ENABLECLR1_CLR32_MASK         (0x1U)
#define DMA_COMMON_ENABLECLR1_CLR32_SHIFT        (0U)
/*! CLR32 - Writing ones to this register clears the corresponding bits in ENABLESET1.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR1_CLR32(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR32_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR32_MASK)

#define DMA_COMMON_ENABLECLR1_CLR33_MASK         (0x2U)
#define DMA_COMMON_ENABLECLR1_CLR33_SHIFT        (1U)
/*! CLR33 - Writing ones to this register clears the corresponding bits in ENABLESET1.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR1_CLR33(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR33_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR33_MASK)

#define DMA_COMMON_ENABLECLR1_CLR34_MASK         (0x4U)
#define DMA_COMMON_ENABLECLR1_CLR34_SHIFT        (2U)
/*! CLR34 - Writing ones to this register clears the corresponding bits in ENABLESET1.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR1_CLR34(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR34_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR34_MASK)

#define DMA_COMMON_ENABLECLR1_CLR35_MASK         (0x8U)
#define DMA_COMMON_ENABLECLR1_CLR35_SHIFT        (3U)
/*! CLR35 - Writing ones to this register clears the corresponding bits in ENABLESET1.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR1_CLR35(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR35_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR35_MASK)

#define DMA_COMMON_ENABLECLR1_CLR36_MASK         (0x10U)
#define DMA_COMMON_ENABLECLR1_CLR36_SHIFT        (4U)
/*! CLR36 - Writing ones to this register clears the corresponding bits in ENABLESET1.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR1_CLR36(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR36_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR36_MASK)

#define DMA_COMMON_ENABLECLR1_CLR37_MASK         (0x20U)
#define DMA_COMMON_ENABLECLR1_CLR37_SHIFT        (5U)
/*! CLR37 - Writing ones to this register clears the corresponding bits in ENABLESET1.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR1_CLR37(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR37_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR37_MASK)

#define DMA_COMMON_ENABLECLR1_CLR38_MASK         (0x40U)
#define DMA_COMMON_ENABLECLR1_CLR38_SHIFT        (6U)
/*! CLR38 - Writing ones to this register clears the corresponding bits in ENABLESET1.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR1_CLR38(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR38_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR38_MASK)

#define DMA_COMMON_ENABLECLR1_CLR39_MASK         (0x80U)
#define DMA_COMMON_ENABLECLR1_CLR39_SHIFT        (7U)
/*! CLR39 - Writing ones to this register clears the corresponding bits in ENABLESET1.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR1_CLR39(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR39_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR39_MASK)

#define DMA_COMMON_ENABLECLR1_CLR40_MASK         (0x100U)
#define DMA_COMMON_ENABLECLR1_CLR40_SHIFT        (8U)
/*! CLR40 - Writing ones to this register clears the corresponding bits in ENABLESET1.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR1_CLR40(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR40_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR40_MASK)

#define DMA_COMMON_ENABLECLR1_CLR41_MASK         (0x200U)
#define DMA_COMMON_ENABLECLR1_CLR41_SHIFT        (9U)
/*! CLR41 - Writing ones to this register clears the corresponding bits in ENABLESET1.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR1_CLR41(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR41_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR41_MASK)

#define DMA_COMMON_ENABLECLR1_CLR42_MASK         (0x400U)
#define DMA_COMMON_ENABLECLR1_CLR42_SHIFT        (10U)
/*! CLR42 - Writing ones to this register clears the corresponding bits in ENABLESET1.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR1_CLR42(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR42_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR42_MASK)

#define DMA_COMMON_ENABLECLR1_CLR43_MASK         (0x800U)
#define DMA_COMMON_ENABLECLR1_CLR43_SHIFT        (11U)
/*! CLR43 - Writing ones to this register clears the corresponding bits in ENABLESET1.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR1_CLR43(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR43_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR43_MASK)

#define DMA_COMMON_ENABLECLR1_CLR44_MASK         (0x1000U)
#define DMA_COMMON_ENABLECLR1_CLR44_SHIFT        (12U)
/*! CLR44 - Writing ones to this register clears the corresponding bits in ENABLESET1.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR1_CLR44(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR44_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR44_MASK)

#define DMA_COMMON_ENABLECLR1_CLR45_MASK         (0x2000U)
#define DMA_COMMON_ENABLECLR1_CLR45_SHIFT        (13U)
/*! CLR45 - Writing ones to this register clears the corresponding bits in ENABLESET1.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR1_CLR45(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR45_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR45_MASK)

#define DMA_COMMON_ENABLECLR1_CLR46_MASK         (0x4000U)
#define DMA_COMMON_ENABLECLR1_CLR46_SHIFT        (14U)
/*! CLR46 - Writing ones to this register clears the corresponding bits in ENABLESET1.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR1_CLR46(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR46_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR46_MASK)

#define DMA_COMMON_ENABLECLR1_CLR47_MASK         (0x8000U)
#define DMA_COMMON_ENABLECLR1_CLR47_SHIFT        (15U)
/*! CLR47 - Writing ones to this register clears the corresponding bits in ENABLESET1.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR1_CLR47(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR47_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR47_MASK)

#define DMA_COMMON_ENABLECLR1_CLR48_MASK         (0x10000U)
#define DMA_COMMON_ENABLECLR1_CLR48_SHIFT        (16U)
/*! CLR48 - Writing ones to this register clears the corresponding bits in ENABLESET1.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR1_CLR48(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR48_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR48_MASK)

#define DMA_COMMON_ENABLECLR1_CLR49_MASK         (0x20000U)
#define DMA_COMMON_ENABLECLR1_CLR49_SHIFT        (17U)
/*! CLR49 - Writing ones to this register clears the corresponding bits in ENABLESET1.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR1_CLR49(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR49_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR49_MASK)

#define DMA_COMMON_ENABLECLR1_CLR50_MASK         (0x40000U)
#define DMA_COMMON_ENABLECLR1_CLR50_SHIFT        (18U)
/*! CLR50 - Writing ones to this register clears the corresponding bits in ENABLESET1.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR1_CLR50(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR50_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR50_MASK)

#define DMA_COMMON_ENABLECLR1_CLR51_MASK         (0x80000U)
#define DMA_COMMON_ENABLECLR1_CLR51_SHIFT        (19U)
/*! CLR51 - Writing ones to this register clears the corresponding bits in ENABLESET1.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR1_CLR51(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR51_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR51_MASK)
/*! @} */

/* The count of DMA_COMMON_ENABLECLR1 */
#define DMA_COMMON_ENABLECLR1_COUNT              (1U)

/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels */
/*! @{ */

#define DMA_COMMON_ACTIVE_ACTIVE0_MASK           (0x1U)
#define DMA_COMMON_ACTIVE_ACTIVE0_SHIFT          (0U)
/*! ACTIVE0 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE0(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE0_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE0_MASK)

#define DMA_COMMON_ACTIVE_ACTIVE1_MASK           (0x2U)
#define DMA_COMMON_ACTIVE_ACTIVE1_SHIFT          (1U)
/*! ACTIVE1 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE1(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE1_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE1_MASK)

#define DMA_COMMON_ACTIVE_ACTIVE2_MASK           (0x4U)
#define DMA_COMMON_ACTIVE_ACTIVE2_SHIFT          (2U)
/*! ACTIVE2 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE2(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE2_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE2_MASK)

#define DMA_COMMON_ACTIVE_ACTIVE3_MASK           (0x8U)
#define DMA_COMMON_ACTIVE_ACTIVE3_SHIFT          (3U)
/*! ACTIVE3 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE3(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE3_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE3_MASK)

#define DMA_COMMON_ACTIVE_ACTIVE4_MASK           (0x10U)
#define DMA_COMMON_ACTIVE_ACTIVE4_SHIFT          (4U)
/*! ACTIVE4 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE4(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE4_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE4_MASK)

#define DMA_COMMON_ACTIVE_ACTIVE5_MASK           (0x20U)
#define DMA_COMMON_ACTIVE_ACTIVE5_SHIFT          (5U)
/*! ACTIVE5 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE5(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE5_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE5_MASK)

#define DMA_COMMON_ACTIVE_ACTIVE6_MASK           (0x40U)
#define DMA_COMMON_ACTIVE_ACTIVE6_SHIFT          (6U)
/*! ACTIVE6 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE6(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE6_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE6_MASK)

#define DMA_COMMON_ACTIVE_ACTIVE7_MASK           (0x80U)
#define DMA_COMMON_ACTIVE_ACTIVE7_SHIFT          (7U)
/*! ACTIVE7 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE7(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE7_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE7_MASK)

#define DMA_COMMON_ACTIVE_ACTIVE8_MASK           (0x100U)
#define DMA_COMMON_ACTIVE_ACTIVE8_SHIFT          (8U)
/*! ACTIVE8 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE8(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE8_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE8_MASK)

#define DMA_COMMON_ACTIVE_ACTIVE9_MASK           (0x200U)
#define DMA_COMMON_ACTIVE_ACTIVE9_SHIFT          (9U)
/*! ACTIVE9 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE9(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE9_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE9_MASK)

#define DMA_COMMON_ACTIVE_ACTIVE10_MASK          (0x400U)
#define DMA_COMMON_ACTIVE_ACTIVE10_SHIFT         (10U)
/*! ACTIVE10 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE10(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE10_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE10_MASK)

#define DMA_COMMON_ACTIVE_ACTIVE11_MASK          (0x800U)
#define DMA_COMMON_ACTIVE_ACTIVE11_SHIFT         (11U)
/*! ACTIVE11 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE11(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE11_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE11_MASK)

#define DMA_COMMON_ACTIVE_ACTIVE12_MASK          (0x1000U)
#define DMA_COMMON_ACTIVE_ACTIVE12_SHIFT         (12U)
/*! ACTIVE12 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE12(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE12_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE12_MASK)

#define DMA_COMMON_ACTIVE_ACTIVE13_MASK          (0x2000U)
#define DMA_COMMON_ACTIVE_ACTIVE13_SHIFT         (13U)
/*! ACTIVE13 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE13(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE13_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE13_MASK)

#define DMA_COMMON_ACTIVE_ACTIVE14_MASK          (0x4000U)
#define DMA_COMMON_ACTIVE_ACTIVE14_SHIFT         (14U)
/*! ACTIVE14 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE14(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE14_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE14_MASK)

#define DMA_COMMON_ACTIVE_ACTIVE15_MASK          (0x8000U)
#define DMA_COMMON_ACTIVE_ACTIVE15_SHIFT         (15U)
/*! ACTIVE15 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE15(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE15_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE15_MASK)

#define DMA_COMMON_ACTIVE_ACTIVE16_MASK          (0x10000U)
#define DMA_COMMON_ACTIVE_ACTIVE16_SHIFT         (16U)
/*! ACTIVE16 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE16(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE16_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE16_MASK)

#define DMA_COMMON_ACTIVE_ACTIVE17_MASK          (0x20000U)
#define DMA_COMMON_ACTIVE_ACTIVE17_SHIFT         (17U)
/*! ACTIVE17 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE17(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE17_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE17_MASK)

#define DMA_COMMON_ACTIVE_ACTIVE18_MASK          (0x40000U)
#define DMA_COMMON_ACTIVE_ACTIVE18_SHIFT         (18U)
/*! ACTIVE18 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE18(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE18_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE18_MASK)

#define DMA_COMMON_ACTIVE_ACTIVE19_MASK          (0x80000U)
#define DMA_COMMON_ACTIVE_ACTIVE19_SHIFT         (19U)
/*! ACTIVE19 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE19(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE19_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE19_MASK)

#define DMA_COMMON_ACTIVE_ACTIVE20_MASK          (0x100000U)
#define DMA_COMMON_ACTIVE_ACTIVE20_SHIFT         (20U)
/*! ACTIVE20 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE20(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE20_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE20_MASK)

#define DMA_COMMON_ACTIVE_ACTIVE21_MASK          (0x200000U)
#define DMA_COMMON_ACTIVE_ACTIVE21_SHIFT         (21U)
/*! ACTIVE21 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE21(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE21_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE21_MASK)

#define DMA_COMMON_ACTIVE_ACTIVE22_MASK          (0x400000U)
#define DMA_COMMON_ACTIVE_ACTIVE22_SHIFT         (22U)
/*! ACTIVE22 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE22(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE22_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE22_MASK)

#define DMA_COMMON_ACTIVE_ACTIVE23_MASK          (0x800000U)
#define DMA_COMMON_ACTIVE_ACTIVE23_SHIFT         (23U)
/*! ACTIVE23 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE23(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE23_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE23_MASK)

#define DMA_COMMON_ACTIVE_ACTIVE24_MASK          (0x1000000U)
#define DMA_COMMON_ACTIVE_ACTIVE24_SHIFT         (24U)
/*! ACTIVE24 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE24(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE24_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE24_MASK)

#define DMA_COMMON_ACTIVE_ACTIVE25_MASK          (0x2000000U)
#define DMA_COMMON_ACTIVE_ACTIVE25_SHIFT         (25U)
/*! ACTIVE25 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE25(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE25_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE25_MASK)

#define DMA_COMMON_ACTIVE_ACTIVE26_MASK          (0x4000000U)
#define DMA_COMMON_ACTIVE_ACTIVE26_SHIFT         (26U)
/*! ACTIVE26 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE26(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE26_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE26_MASK)

#define DMA_COMMON_ACTIVE_ACTIVE27_MASK          (0x8000000U)
#define DMA_COMMON_ACTIVE_ACTIVE27_SHIFT         (27U)
/*! ACTIVE27 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE27(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE27_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE27_MASK)

#define DMA_COMMON_ACTIVE_ACTIVE28_MASK          (0x10000000U)
#define DMA_COMMON_ACTIVE_ACTIVE28_SHIFT         (28U)
/*! ACTIVE28 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE28(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE28_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE28_MASK)

#define DMA_COMMON_ACTIVE_ACTIVE29_MASK          (0x20000000U)
#define DMA_COMMON_ACTIVE_ACTIVE29_SHIFT         (29U)
/*! ACTIVE29 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE29(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE29_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE29_MASK)

#define DMA_COMMON_ACTIVE_ACTIVE30_MASK          (0x40000000U)
#define DMA_COMMON_ACTIVE_ACTIVE30_SHIFT         (30U)
/*! ACTIVE30 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE30(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE30_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE30_MASK)

#define DMA_COMMON_ACTIVE_ACTIVE31_MASK          (0x80000000U)
#define DMA_COMMON_ACTIVE_ACTIVE31_SHIFT         (31U)
/*! ACTIVE31 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE31(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE31_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE31_MASK)
/*! @} */

/* The count of DMA_COMMON_ACTIVE */
#define DMA_COMMON_ACTIVE_COUNT                  (1U)

/*! @name COMMON_ACTIVE1 - Channel Active status for all DMA channels */
/*! @{ */

#define DMA_COMMON_ACTIVE1_ACTIVE32_MASK         (0x1U)
#define DMA_COMMON_ACTIVE1_ACTIVE32_SHIFT        (0U)
/*! ACTIVE32 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE1_ACTIVE32(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE32_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE32_MASK)

#define DMA_COMMON_ACTIVE1_ACTIVE33_MASK         (0x2U)
#define DMA_COMMON_ACTIVE1_ACTIVE33_SHIFT        (1U)
/*! ACTIVE33 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE1_ACTIVE33(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE33_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE33_MASK)

#define DMA_COMMON_ACTIVE1_ACTIVE34_MASK         (0x4U)
#define DMA_COMMON_ACTIVE1_ACTIVE34_SHIFT        (2U)
/*! ACTIVE34 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE1_ACTIVE34(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE34_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE34_MASK)

#define DMA_COMMON_ACTIVE1_ACTIVE35_MASK         (0x8U)
#define DMA_COMMON_ACTIVE1_ACTIVE35_SHIFT        (3U)
/*! ACTIVE35 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE1_ACTIVE35(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE35_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE35_MASK)

#define DMA_COMMON_ACTIVE1_ACTIVE36_MASK         (0x10U)
#define DMA_COMMON_ACTIVE1_ACTIVE36_SHIFT        (4U)
/*! ACTIVE36 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE1_ACTIVE36(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE36_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE36_MASK)

#define DMA_COMMON_ACTIVE1_ACTIVE37_MASK         (0x20U)
#define DMA_COMMON_ACTIVE1_ACTIVE37_SHIFT        (5U)
/*! ACTIVE37 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE1_ACTIVE37(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE37_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE37_MASK)

#define DMA_COMMON_ACTIVE1_ACTIVE38_MASK         (0x40U)
#define DMA_COMMON_ACTIVE1_ACTIVE38_SHIFT        (6U)
/*! ACTIVE38 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE1_ACTIVE38(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE38_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE38_MASK)

#define DMA_COMMON_ACTIVE1_ACTIVE39_MASK         (0x80U)
#define DMA_COMMON_ACTIVE1_ACTIVE39_SHIFT        (7U)
/*! ACTIVE39 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE1_ACTIVE39(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE39_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE39_MASK)

#define DMA_COMMON_ACTIVE1_ACTIVE40_MASK         (0x100U)
#define DMA_COMMON_ACTIVE1_ACTIVE40_SHIFT        (8U)
/*! ACTIVE40 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE1_ACTIVE40(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE40_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE40_MASK)

#define DMA_COMMON_ACTIVE1_ACTIVE41_MASK         (0x200U)
#define DMA_COMMON_ACTIVE1_ACTIVE41_SHIFT        (9U)
/*! ACTIVE41 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE1_ACTIVE41(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE41_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE41_MASK)

#define DMA_COMMON_ACTIVE1_ACTIVE42_MASK         (0x400U)
#define DMA_COMMON_ACTIVE1_ACTIVE42_SHIFT        (10U)
/*! ACTIVE42 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE1_ACTIVE42(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE42_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE42_MASK)

#define DMA_COMMON_ACTIVE1_ACTIVE43_MASK         (0x800U)
#define DMA_COMMON_ACTIVE1_ACTIVE43_SHIFT        (11U)
/*! ACTIVE43 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE1_ACTIVE43(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE43_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE43_MASK)

#define DMA_COMMON_ACTIVE1_ACTIVE44_MASK         (0x1000U)
#define DMA_COMMON_ACTIVE1_ACTIVE44_SHIFT        (12U)
/*! ACTIVE44 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE1_ACTIVE44(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE44_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE44_MASK)

#define DMA_COMMON_ACTIVE1_ACTIVE45_MASK         (0x2000U)
#define DMA_COMMON_ACTIVE1_ACTIVE45_SHIFT        (13U)
/*! ACTIVE45 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE1_ACTIVE45(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE45_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE45_MASK)

#define DMA_COMMON_ACTIVE1_ACTIVE46_MASK         (0x4000U)
#define DMA_COMMON_ACTIVE1_ACTIVE46_SHIFT        (14U)
/*! ACTIVE46 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE1_ACTIVE46(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE46_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE46_MASK)

#define DMA_COMMON_ACTIVE1_ACTIVE47_MASK         (0x8000U)
#define DMA_COMMON_ACTIVE1_ACTIVE47_SHIFT        (15U)
/*! ACTIVE47 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE1_ACTIVE47(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE47_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE47_MASK)

#define DMA_COMMON_ACTIVE1_ACTIVE48_MASK         (0x10000U)
#define DMA_COMMON_ACTIVE1_ACTIVE48_SHIFT        (16U)
/*! ACTIVE48 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE1_ACTIVE48(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE48_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE48_MASK)

#define DMA_COMMON_ACTIVE1_ACTIVE49_MASK         (0x20000U)
#define DMA_COMMON_ACTIVE1_ACTIVE49_SHIFT        (17U)
/*! ACTIVE49 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE1_ACTIVE49(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE49_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE49_MASK)

#define DMA_COMMON_ACTIVE1_ACTIVE50_MASK         (0x40000U)
#define DMA_COMMON_ACTIVE1_ACTIVE50_SHIFT        (18U)
/*! ACTIVE50 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE1_ACTIVE50(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE50_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE50_MASK)

#define DMA_COMMON_ACTIVE1_ACTIVE51_MASK         (0x80000U)
#define DMA_COMMON_ACTIVE1_ACTIVE51_SHIFT        (19U)
/*! ACTIVE51 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE1_ACTIVE51(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE51_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE51_MASK)
/*! @} */

/* The count of DMA_COMMON_ACTIVE1 */
#define DMA_COMMON_ACTIVE1_COUNT                 (1U)

/*! @name COMMON_BUSY - Channel Busy status for all DMA channels */
/*! @{ */

#define DMA_COMMON_BUSY_BUSY0_MASK               (0x1U)
#define DMA_COMMON_BUSY_BUSY0_SHIFT              (0U)
/*! BUSY0 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY0(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY0_SHIFT)) & DMA_COMMON_BUSY_BUSY0_MASK)

#define DMA_COMMON_BUSY_BUSY1_MASK               (0x2U)
#define DMA_COMMON_BUSY_BUSY1_SHIFT              (1U)
/*! BUSY1 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY1(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY1_SHIFT)) & DMA_COMMON_BUSY_BUSY1_MASK)

#define DMA_COMMON_BUSY_BUSY2_MASK               (0x4U)
#define DMA_COMMON_BUSY_BUSY2_SHIFT              (2U)
/*! BUSY2 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY2(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY2_SHIFT)) & DMA_COMMON_BUSY_BUSY2_MASK)

#define DMA_COMMON_BUSY_BUSY3_MASK               (0x8U)
#define DMA_COMMON_BUSY_BUSY3_SHIFT              (3U)
/*! BUSY3 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY3(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY3_SHIFT)) & DMA_COMMON_BUSY_BUSY3_MASK)

#define DMA_COMMON_BUSY_BUSY4_MASK               (0x10U)
#define DMA_COMMON_BUSY_BUSY4_SHIFT              (4U)
/*! BUSY4 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY4(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY4_SHIFT)) & DMA_COMMON_BUSY_BUSY4_MASK)

#define DMA_COMMON_BUSY_BUSY5_MASK               (0x20U)
#define DMA_COMMON_BUSY_BUSY5_SHIFT              (5U)
/*! BUSY5 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY5(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY5_SHIFT)) & DMA_COMMON_BUSY_BUSY5_MASK)

#define DMA_COMMON_BUSY_BUSY6_MASK               (0x40U)
#define DMA_COMMON_BUSY_BUSY6_SHIFT              (6U)
/*! BUSY6 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY6(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY6_SHIFT)) & DMA_COMMON_BUSY_BUSY6_MASK)

#define DMA_COMMON_BUSY_BUSY7_MASK               (0x80U)
#define DMA_COMMON_BUSY_BUSY7_SHIFT              (7U)
/*! BUSY7 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY7(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY7_SHIFT)) & DMA_COMMON_BUSY_BUSY7_MASK)

#define DMA_COMMON_BUSY_BUSY8_MASK               (0x100U)
#define DMA_COMMON_BUSY_BUSY8_SHIFT              (8U)
/*! BUSY8 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY8(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY8_SHIFT)) & DMA_COMMON_BUSY_BUSY8_MASK)

#define DMA_COMMON_BUSY_BUSY9_MASK               (0x200U)
#define DMA_COMMON_BUSY_BUSY9_SHIFT              (9U)
/*! BUSY9 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY9(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY9_SHIFT)) & DMA_COMMON_BUSY_BUSY9_MASK)

#define DMA_COMMON_BUSY_BUSY10_MASK              (0x400U)
#define DMA_COMMON_BUSY_BUSY10_SHIFT             (10U)
/*! BUSY10 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY10(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY10_SHIFT)) & DMA_COMMON_BUSY_BUSY10_MASK)

#define DMA_COMMON_BUSY_BUSY11_MASK              (0x800U)
#define DMA_COMMON_BUSY_BUSY11_SHIFT             (11U)
/*! BUSY11 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY11(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY11_SHIFT)) & DMA_COMMON_BUSY_BUSY11_MASK)

#define DMA_COMMON_BUSY_BUSY12_MASK              (0x1000U)
#define DMA_COMMON_BUSY_BUSY12_SHIFT             (12U)
/*! BUSY12 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY12(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY12_SHIFT)) & DMA_COMMON_BUSY_BUSY12_MASK)

#define DMA_COMMON_BUSY_BUSY13_MASK              (0x2000U)
#define DMA_COMMON_BUSY_BUSY13_SHIFT             (13U)
/*! BUSY13 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY13(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY13_SHIFT)) & DMA_COMMON_BUSY_BUSY13_MASK)

#define DMA_COMMON_BUSY_BUSY14_MASK              (0x4000U)
#define DMA_COMMON_BUSY_BUSY14_SHIFT             (14U)
/*! BUSY14 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY14(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY14_SHIFT)) & DMA_COMMON_BUSY_BUSY14_MASK)

#define DMA_COMMON_BUSY_BUSY15_MASK              (0x8000U)
#define DMA_COMMON_BUSY_BUSY15_SHIFT             (15U)
/*! BUSY15 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY15(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY15_SHIFT)) & DMA_COMMON_BUSY_BUSY15_MASK)

#define DMA_COMMON_BUSY_BUSY16_MASK              (0x10000U)
#define DMA_COMMON_BUSY_BUSY16_SHIFT             (16U)
/*! BUSY16 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY16(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY16_SHIFT)) & DMA_COMMON_BUSY_BUSY16_MASK)

#define DMA_COMMON_BUSY_BUSY17_MASK              (0x20000U)
#define DMA_COMMON_BUSY_BUSY17_SHIFT             (17U)
/*! BUSY17 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY17(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY17_SHIFT)) & DMA_COMMON_BUSY_BUSY17_MASK)

#define DMA_COMMON_BUSY_BUSY18_MASK              (0x40000U)
#define DMA_COMMON_BUSY_BUSY18_SHIFT             (18U)
/*! BUSY18 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY18(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY18_SHIFT)) & DMA_COMMON_BUSY_BUSY18_MASK)

#define DMA_COMMON_BUSY_BUSY19_MASK              (0x80000U)
#define DMA_COMMON_BUSY_BUSY19_SHIFT             (19U)
/*! BUSY19 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY19(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY19_SHIFT)) & DMA_COMMON_BUSY_BUSY19_MASK)

#define DMA_COMMON_BUSY_BUSY20_MASK              (0x100000U)
#define DMA_COMMON_BUSY_BUSY20_SHIFT             (20U)
/*! BUSY20 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY20(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY20_SHIFT)) & DMA_COMMON_BUSY_BUSY20_MASK)

#define DMA_COMMON_BUSY_BUSY21_MASK              (0x200000U)
#define DMA_COMMON_BUSY_BUSY21_SHIFT             (21U)
/*! BUSY21 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY21(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY21_SHIFT)) & DMA_COMMON_BUSY_BUSY21_MASK)

#define DMA_COMMON_BUSY_BUSY22_MASK              (0x400000U)
#define DMA_COMMON_BUSY_BUSY22_SHIFT             (22U)
/*! BUSY22 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY22(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY22_SHIFT)) & DMA_COMMON_BUSY_BUSY22_MASK)

#define DMA_COMMON_BUSY_BUSY23_MASK              (0x800000U)
#define DMA_COMMON_BUSY_BUSY23_SHIFT             (23U)
/*! BUSY23 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY23(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY23_SHIFT)) & DMA_COMMON_BUSY_BUSY23_MASK)

#define DMA_COMMON_BUSY_BUSY24_MASK              (0x1000000U)
#define DMA_COMMON_BUSY_BUSY24_SHIFT             (24U)
/*! BUSY24 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY24(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY24_SHIFT)) & DMA_COMMON_BUSY_BUSY24_MASK)

#define DMA_COMMON_BUSY_BUSY25_MASK              (0x2000000U)
#define DMA_COMMON_BUSY_BUSY25_SHIFT             (25U)
/*! BUSY25 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY25(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY25_SHIFT)) & DMA_COMMON_BUSY_BUSY25_MASK)

#define DMA_COMMON_BUSY_BUSY26_MASK              (0x4000000U)
#define DMA_COMMON_BUSY_BUSY26_SHIFT             (26U)
/*! BUSY26 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY26(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY26_SHIFT)) & DMA_COMMON_BUSY_BUSY26_MASK)

#define DMA_COMMON_BUSY_BUSY27_MASK              (0x8000000U)
#define DMA_COMMON_BUSY_BUSY27_SHIFT             (27U)
/*! BUSY27 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY27(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY27_SHIFT)) & DMA_COMMON_BUSY_BUSY27_MASK)

#define DMA_COMMON_BUSY_BUSY28_MASK              (0x10000000U)
#define DMA_COMMON_BUSY_BUSY28_SHIFT             (28U)
/*! BUSY28 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY28(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY28_SHIFT)) & DMA_COMMON_BUSY_BUSY28_MASK)

#define DMA_COMMON_BUSY_BUSY29_MASK              (0x20000000U)
#define DMA_COMMON_BUSY_BUSY29_SHIFT             (29U)
/*! BUSY29 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY29(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY29_SHIFT)) & DMA_COMMON_BUSY_BUSY29_MASK)

#define DMA_COMMON_BUSY_BUSY30_MASK              (0x40000000U)
#define DMA_COMMON_BUSY_BUSY30_SHIFT             (30U)
/*! BUSY30 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY30(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY30_SHIFT)) & DMA_COMMON_BUSY_BUSY30_MASK)

#define DMA_COMMON_BUSY_BUSY31_MASK              (0x80000000U)
#define DMA_COMMON_BUSY_BUSY31_SHIFT             (31U)
/*! BUSY31 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY31(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY31_SHIFT)) & DMA_COMMON_BUSY_BUSY31_MASK)
/*! @} */

/* The count of DMA_COMMON_BUSY */
#define DMA_COMMON_BUSY_COUNT                    (1U)

/*! @name COMMON_BUSY1 - Channel Busy status for all DMA channels */
/*! @{ */

#define DMA_COMMON_BUSY1_BUSY32_MASK             (0x1U)
#define DMA_COMMON_BUSY1_BUSY32_SHIFT            (0U)
/*! BUSY32 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY1_BUSY32(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY32_SHIFT)) & DMA_COMMON_BUSY1_BUSY32_MASK)

#define DMA_COMMON_BUSY1_BUSY33_MASK             (0x2U)
#define DMA_COMMON_BUSY1_BUSY33_SHIFT            (1U)
/*! BUSY33 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY1_BUSY33(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY33_SHIFT)) & DMA_COMMON_BUSY1_BUSY33_MASK)

#define DMA_COMMON_BUSY1_BUSY34_MASK             (0x4U)
#define DMA_COMMON_BUSY1_BUSY34_SHIFT            (2U)
/*! BUSY34 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY1_BUSY34(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY34_SHIFT)) & DMA_COMMON_BUSY1_BUSY34_MASK)

#define DMA_COMMON_BUSY1_BUSY35_MASK             (0x8U)
#define DMA_COMMON_BUSY1_BUSY35_SHIFT            (3U)
/*! BUSY35 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY1_BUSY35(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY35_SHIFT)) & DMA_COMMON_BUSY1_BUSY35_MASK)

#define DMA_COMMON_BUSY1_BUSY36_MASK             (0x10U)
#define DMA_COMMON_BUSY1_BUSY36_SHIFT            (4U)
/*! BUSY36 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY1_BUSY36(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY36_SHIFT)) & DMA_COMMON_BUSY1_BUSY36_MASK)

#define DMA_COMMON_BUSY1_BUSY37_MASK             (0x20U)
#define DMA_COMMON_BUSY1_BUSY37_SHIFT            (5U)
/*! BUSY37 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY1_BUSY37(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY37_SHIFT)) & DMA_COMMON_BUSY1_BUSY37_MASK)

#define DMA_COMMON_BUSY1_BUSY38_MASK             (0x40U)
#define DMA_COMMON_BUSY1_BUSY38_SHIFT            (6U)
/*! BUSY38 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY1_BUSY38(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY38_SHIFT)) & DMA_COMMON_BUSY1_BUSY38_MASK)

#define DMA_COMMON_BUSY1_BUSY39_MASK             (0x80U)
#define DMA_COMMON_BUSY1_BUSY39_SHIFT            (7U)
/*! BUSY39 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY1_BUSY39(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY39_SHIFT)) & DMA_COMMON_BUSY1_BUSY39_MASK)

#define DMA_COMMON_BUSY1_BUSY40_MASK             (0x100U)
#define DMA_COMMON_BUSY1_BUSY40_SHIFT            (8U)
/*! BUSY40 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY1_BUSY40(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY40_SHIFT)) & DMA_COMMON_BUSY1_BUSY40_MASK)

#define DMA_COMMON_BUSY1_BUSY41_MASK             (0x200U)
#define DMA_COMMON_BUSY1_BUSY41_SHIFT            (9U)
/*! BUSY41 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY1_BUSY41(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY41_SHIFT)) & DMA_COMMON_BUSY1_BUSY41_MASK)

#define DMA_COMMON_BUSY1_BUSY42_MASK             (0x400U)
#define DMA_COMMON_BUSY1_BUSY42_SHIFT            (10U)
/*! BUSY42 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY1_BUSY42(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY42_SHIFT)) & DMA_COMMON_BUSY1_BUSY42_MASK)

#define DMA_COMMON_BUSY1_BUSY43_MASK             (0x800U)
#define DMA_COMMON_BUSY1_BUSY43_SHIFT            (11U)
/*! BUSY43 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY1_BUSY43(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY43_SHIFT)) & DMA_COMMON_BUSY1_BUSY43_MASK)

#define DMA_COMMON_BUSY1_BUSY44_MASK             (0x1000U)
#define DMA_COMMON_BUSY1_BUSY44_SHIFT            (12U)
/*! BUSY44 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY1_BUSY44(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY44_SHIFT)) & DMA_COMMON_BUSY1_BUSY44_MASK)

#define DMA_COMMON_BUSY1_BUSY45_MASK             (0x2000U)
#define DMA_COMMON_BUSY1_BUSY45_SHIFT            (13U)
/*! BUSY45 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY1_BUSY45(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY45_SHIFT)) & DMA_COMMON_BUSY1_BUSY45_MASK)

#define DMA_COMMON_BUSY1_BUSY46_MASK             (0x4000U)
#define DMA_COMMON_BUSY1_BUSY46_SHIFT            (14U)
/*! BUSY46 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY1_BUSY46(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY46_SHIFT)) & DMA_COMMON_BUSY1_BUSY46_MASK)

#define DMA_COMMON_BUSY1_BUSY47_MASK             (0x8000U)
#define DMA_COMMON_BUSY1_BUSY47_SHIFT            (15U)
/*! BUSY47 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY1_BUSY47(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY47_SHIFT)) & DMA_COMMON_BUSY1_BUSY47_MASK)

#define DMA_COMMON_BUSY1_BUSY48_MASK             (0x10000U)
#define DMA_COMMON_BUSY1_BUSY48_SHIFT            (16U)
/*! BUSY48 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY1_BUSY48(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY48_SHIFT)) & DMA_COMMON_BUSY1_BUSY48_MASK)

#define DMA_COMMON_BUSY1_BUSY49_MASK             (0x20000U)
#define DMA_COMMON_BUSY1_BUSY49_SHIFT            (17U)
/*! BUSY49 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY1_BUSY49(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY49_SHIFT)) & DMA_COMMON_BUSY1_BUSY49_MASK)

#define DMA_COMMON_BUSY1_BUSY50_MASK             (0x40000U)
#define DMA_COMMON_BUSY1_BUSY50_SHIFT            (18U)
/*! BUSY50 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY1_BUSY50(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY50_SHIFT)) & DMA_COMMON_BUSY1_BUSY50_MASK)

#define DMA_COMMON_BUSY1_BUSY51_MASK             (0x80000U)
#define DMA_COMMON_BUSY1_BUSY51_SHIFT            (19U)
/*! BUSY51 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY1_BUSY51(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY51_SHIFT)) & DMA_COMMON_BUSY1_BUSY51_MASK)
/*! @} */

/* The count of DMA_COMMON_BUSY1 */
#define DMA_COMMON_BUSY1_COUNT                   (1U)

/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels */
/*! @{ */

#define DMA_COMMON_ERRINT_ERR0_MASK              (0x1U)
#define DMA_COMMON_ERRINT_ERR0_SHIFT             (0U)
/*! ERR0 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR0(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR0_SHIFT)) & DMA_COMMON_ERRINT_ERR0_MASK)

#define DMA_COMMON_ERRINT_ERR1_MASK              (0x2U)
#define DMA_COMMON_ERRINT_ERR1_SHIFT             (1U)
/*! ERR1 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR1(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR1_SHIFT)) & DMA_COMMON_ERRINT_ERR1_MASK)

#define DMA_COMMON_ERRINT_ERR2_MASK              (0x4U)
#define DMA_COMMON_ERRINT_ERR2_SHIFT             (2U)
/*! ERR2 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR2(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR2_SHIFT)) & DMA_COMMON_ERRINT_ERR2_MASK)

#define DMA_COMMON_ERRINT_ERR3_MASK              (0x8U)
#define DMA_COMMON_ERRINT_ERR3_SHIFT             (3U)
/*! ERR3 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR3(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR3_SHIFT)) & DMA_COMMON_ERRINT_ERR3_MASK)

#define DMA_COMMON_ERRINT_ERR4_MASK              (0x10U)
#define DMA_COMMON_ERRINT_ERR4_SHIFT             (4U)
/*! ERR4 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR4(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR4_SHIFT)) & DMA_COMMON_ERRINT_ERR4_MASK)

#define DMA_COMMON_ERRINT_ERR5_MASK              (0x20U)
#define DMA_COMMON_ERRINT_ERR5_SHIFT             (5U)
/*! ERR5 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR5(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR5_SHIFT)) & DMA_COMMON_ERRINT_ERR5_MASK)

#define DMA_COMMON_ERRINT_ERR6_MASK              (0x40U)
#define DMA_COMMON_ERRINT_ERR6_SHIFT             (6U)
/*! ERR6 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR6(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR6_SHIFT)) & DMA_COMMON_ERRINT_ERR6_MASK)

#define DMA_COMMON_ERRINT_ERR7_MASK              (0x80U)
#define DMA_COMMON_ERRINT_ERR7_SHIFT             (7U)
/*! ERR7 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR7(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR7_SHIFT)) & DMA_COMMON_ERRINT_ERR7_MASK)

#define DMA_COMMON_ERRINT_ERR8_MASK              (0x100U)
#define DMA_COMMON_ERRINT_ERR8_SHIFT             (8U)
/*! ERR8 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR8(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR8_SHIFT)) & DMA_COMMON_ERRINT_ERR8_MASK)

#define DMA_COMMON_ERRINT_ERR9_MASK              (0x200U)
#define DMA_COMMON_ERRINT_ERR9_SHIFT             (9U)
/*! ERR9 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR9(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR9_SHIFT)) & DMA_COMMON_ERRINT_ERR9_MASK)

#define DMA_COMMON_ERRINT_ERR10_MASK             (0x400U)
#define DMA_COMMON_ERRINT_ERR10_SHIFT            (10U)
/*! ERR10 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR10(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR10_SHIFT)) & DMA_COMMON_ERRINT_ERR10_MASK)

#define DMA_COMMON_ERRINT_ERR11_MASK             (0x800U)
#define DMA_COMMON_ERRINT_ERR11_SHIFT            (11U)
/*! ERR11 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR11(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR11_SHIFT)) & DMA_COMMON_ERRINT_ERR11_MASK)

#define DMA_COMMON_ERRINT_ERR12_MASK             (0x1000U)
#define DMA_COMMON_ERRINT_ERR12_SHIFT            (12U)
/*! ERR12 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR12(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR12_SHIFT)) & DMA_COMMON_ERRINT_ERR12_MASK)

#define DMA_COMMON_ERRINT_ERR13_MASK             (0x2000U)
#define DMA_COMMON_ERRINT_ERR13_SHIFT            (13U)
/*! ERR13 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR13(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR13_SHIFT)) & DMA_COMMON_ERRINT_ERR13_MASK)

#define DMA_COMMON_ERRINT_ERR14_MASK             (0x4000U)
#define DMA_COMMON_ERRINT_ERR14_SHIFT            (14U)
/*! ERR14 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR14(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR14_SHIFT)) & DMA_COMMON_ERRINT_ERR14_MASK)

#define DMA_COMMON_ERRINT_ERR15_MASK             (0x8000U)
#define DMA_COMMON_ERRINT_ERR15_SHIFT            (15U)
/*! ERR15 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR15(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR15_SHIFT)) & DMA_COMMON_ERRINT_ERR15_MASK)

#define DMA_COMMON_ERRINT_ERR16_MASK             (0x10000U)
#define DMA_COMMON_ERRINT_ERR16_SHIFT            (16U)
/*! ERR16 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR16(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR16_SHIFT)) & DMA_COMMON_ERRINT_ERR16_MASK)

#define DMA_COMMON_ERRINT_ERR17_MASK             (0x20000U)
#define DMA_COMMON_ERRINT_ERR17_SHIFT            (17U)
/*! ERR17 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR17(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR17_SHIFT)) & DMA_COMMON_ERRINT_ERR17_MASK)

#define DMA_COMMON_ERRINT_ERR18_MASK             (0x40000U)
#define DMA_COMMON_ERRINT_ERR18_SHIFT            (18U)
/*! ERR18 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR18(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR18_SHIFT)) & DMA_COMMON_ERRINT_ERR18_MASK)

#define DMA_COMMON_ERRINT_ERR19_MASK             (0x80000U)
#define DMA_COMMON_ERRINT_ERR19_SHIFT            (19U)
/*! ERR19 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR19(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR19_SHIFT)) & DMA_COMMON_ERRINT_ERR19_MASK)

#define DMA_COMMON_ERRINT_ERR20_MASK             (0x100000U)
#define DMA_COMMON_ERRINT_ERR20_SHIFT            (20U)
/*! ERR20 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR20(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR20_SHIFT)) & DMA_COMMON_ERRINT_ERR20_MASK)

#define DMA_COMMON_ERRINT_ERR21_MASK             (0x200000U)
#define DMA_COMMON_ERRINT_ERR21_SHIFT            (21U)
/*! ERR21 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR21(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR21_SHIFT)) & DMA_COMMON_ERRINT_ERR21_MASK)

#define DMA_COMMON_ERRINT_ERR22_MASK             (0x400000U)
#define DMA_COMMON_ERRINT_ERR22_SHIFT            (22U)
/*! ERR22 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR22(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR22_SHIFT)) & DMA_COMMON_ERRINT_ERR22_MASK)

#define DMA_COMMON_ERRINT_ERR23_MASK             (0x800000U)
#define DMA_COMMON_ERRINT_ERR23_SHIFT            (23U)
/*! ERR23 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR23(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR23_SHIFT)) & DMA_COMMON_ERRINT_ERR23_MASK)

#define DMA_COMMON_ERRINT_ERR24_MASK             (0x1000000U)
#define DMA_COMMON_ERRINT_ERR24_SHIFT            (24U)
/*! ERR24 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR24(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR24_SHIFT)) & DMA_COMMON_ERRINT_ERR24_MASK)

#define DMA_COMMON_ERRINT_ERR25_MASK             (0x2000000U)
#define DMA_COMMON_ERRINT_ERR25_SHIFT            (25U)
/*! ERR25 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR25(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR25_SHIFT)) & DMA_COMMON_ERRINT_ERR25_MASK)

#define DMA_COMMON_ERRINT_ERR26_MASK             (0x4000000U)
#define DMA_COMMON_ERRINT_ERR26_SHIFT            (26U)
/*! ERR26 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR26(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR26_SHIFT)) & DMA_COMMON_ERRINT_ERR26_MASK)

#define DMA_COMMON_ERRINT_ERR27_MASK             (0x8000000U)
#define DMA_COMMON_ERRINT_ERR27_SHIFT            (27U)
/*! ERR27 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR27(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR27_SHIFT)) & DMA_COMMON_ERRINT_ERR27_MASK)

#define DMA_COMMON_ERRINT_ERR28_MASK             (0x10000000U)
#define DMA_COMMON_ERRINT_ERR28_SHIFT            (28U)
/*! ERR28 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR28(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR28_SHIFT)) & DMA_COMMON_ERRINT_ERR28_MASK)

#define DMA_COMMON_ERRINT_ERR29_MASK             (0x20000000U)
#define DMA_COMMON_ERRINT_ERR29_SHIFT            (29U)
/*! ERR29 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR29(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR29_SHIFT)) & DMA_COMMON_ERRINT_ERR29_MASK)

#define DMA_COMMON_ERRINT_ERR30_MASK             (0x40000000U)
#define DMA_COMMON_ERRINT_ERR30_SHIFT            (30U)
/*! ERR30 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR30(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR30_SHIFT)) & DMA_COMMON_ERRINT_ERR30_MASK)

#define DMA_COMMON_ERRINT_ERR31_MASK             (0x80000000U)
#define DMA_COMMON_ERRINT_ERR31_SHIFT            (31U)
/*! ERR31 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR31(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR31_SHIFT)) & DMA_COMMON_ERRINT_ERR31_MASK)
/*! @} */

/* The count of DMA_COMMON_ERRINT */
#define DMA_COMMON_ERRINT_COUNT                  (1U)

/*! @name COMMON_ERRINT1 - Error Interrupt status for all DMA channels */
/*! @{ */

#define DMA_COMMON_ERRINT1_ERR32_MASK            (0x1U)
#define DMA_COMMON_ERRINT1_ERR32_SHIFT           (0U)
/*! ERR32 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT1_ERR32(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR32_SHIFT)) & DMA_COMMON_ERRINT1_ERR32_MASK)

#define DMA_COMMON_ERRINT1_ERR33_MASK            (0x2U)
#define DMA_COMMON_ERRINT1_ERR33_SHIFT           (1U)
/*! ERR33 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT1_ERR33(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR33_SHIFT)) & DMA_COMMON_ERRINT1_ERR33_MASK)

#define DMA_COMMON_ERRINT1_ERR34_MASK            (0x4U)
#define DMA_COMMON_ERRINT1_ERR34_SHIFT           (2U)
/*! ERR34 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT1_ERR34(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR34_SHIFT)) & DMA_COMMON_ERRINT1_ERR34_MASK)

#define DMA_COMMON_ERRINT1_ERR35_MASK            (0x8U)
#define DMA_COMMON_ERRINT1_ERR35_SHIFT           (3U)
/*! ERR35 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT1_ERR35(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR35_SHIFT)) & DMA_COMMON_ERRINT1_ERR35_MASK)

#define DMA_COMMON_ERRINT1_ERR36_MASK            (0x10U)
#define DMA_COMMON_ERRINT1_ERR36_SHIFT           (4U)
/*! ERR36 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT1_ERR36(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR36_SHIFT)) & DMA_COMMON_ERRINT1_ERR36_MASK)

#define DMA_COMMON_ERRINT1_ERR37_MASK            (0x20U)
#define DMA_COMMON_ERRINT1_ERR37_SHIFT           (5U)
/*! ERR37 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT1_ERR37(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR37_SHIFT)) & DMA_COMMON_ERRINT1_ERR37_MASK)

#define DMA_COMMON_ERRINT1_ERR38_MASK            (0x40U)
#define DMA_COMMON_ERRINT1_ERR38_SHIFT           (6U)
/*! ERR38 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT1_ERR38(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR38_SHIFT)) & DMA_COMMON_ERRINT1_ERR38_MASK)

#define DMA_COMMON_ERRINT1_ERR39_MASK            (0x80U)
#define DMA_COMMON_ERRINT1_ERR39_SHIFT           (7U)
/*! ERR39 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT1_ERR39(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR39_SHIFT)) & DMA_COMMON_ERRINT1_ERR39_MASK)

#define DMA_COMMON_ERRINT1_ERR40_MASK            (0x100U)
#define DMA_COMMON_ERRINT1_ERR40_SHIFT           (8U)
/*! ERR40 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT1_ERR40(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR40_SHIFT)) & DMA_COMMON_ERRINT1_ERR40_MASK)

#define DMA_COMMON_ERRINT1_ERR41_MASK            (0x200U)
#define DMA_COMMON_ERRINT1_ERR41_SHIFT           (9U)
/*! ERR41 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT1_ERR41(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR41_SHIFT)) & DMA_COMMON_ERRINT1_ERR41_MASK)

#define DMA_COMMON_ERRINT1_ERR42_MASK            (0x400U)
#define DMA_COMMON_ERRINT1_ERR42_SHIFT           (10U)
/*! ERR42 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT1_ERR42(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR42_SHIFT)) & DMA_COMMON_ERRINT1_ERR42_MASK)

#define DMA_COMMON_ERRINT1_ERR43_MASK            (0x800U)
#define DMA_COMMON_ERRINT1_ERR43_SHIFT           (11U)
/*! ERR43 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT1_ERR43(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR43_SHIFT)) & DMA_COMMON_ERRINT1_ERR43_MASK)

#define DMA_COMMON_ERRINT1_ERR44_MASK            (0x1000U)
#define DMA_COMMON_ERRINT1_ERR44_SHIFT           (12U)
/*! ERR44 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT1_ERR44(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR44_SHIFT)) & DMA_COMMON_ERRINT1_ERR44_MASK)

#define DMA_COMMON_ERRINT1_ERR45_MASK            (0x2000U)
#define DMA_COMMON_ERRINT1_ERR45_SHIFT           (13U)
/*! ERR45 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT1_ERR45(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR45_SHIFT)) & DMA_COMMON_ERRINT1_ERR45_MASK)

#define DMA_COMMON_ERRINT1_ERR46_MASK            (0x4000U)
#define DMA_COMMON_ERRINT1_ERR46_SHIFT           (14U)
/*! ERR46 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT1_ERR46(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR46_SHIFT)) & DMA_COMMON_ERRINT1_ERR46_MASK)

#define DMA_COMMON_ERRINT1_ERR47_MASK            (0x8000U)
#define DMA_COMMON_ERRINT1_ERR47_SHIFT           (15U)
/*! ERR47 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT1_ERR47(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR47_SHIFT)) & DMA_COMMON_ERRINT1_ERR47_MASK)

#define DMA_COMMON_ERRINT1_ERR48_MASK            (0x10000U)
#define DMA_COMMON_ERRINT1_ERR48_SHIFT           (16U)
/*! ERR48 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT1_ERR48(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR48_SHIFT)) & DMA_COMMON_ERRINT1_ERR48_MASK)

#define DMA_COMMON_ERRINT1_ERR49_MASK            (0x20000U)
#define DMA_COMMON_ERRINT1_ERR49_SHIFT           (17U)
/*! ERR49 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT1_ERR49(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR49_SHIFT)) & DMA_COMMON_ERRINT1_ERR49_MASK)

#define DMA_COMMON_ERRINT1_ERR50_MASK            (0x40000U)
#define DMA_COMMON_ERRINT1_ERR50_SHIFT           (18U)
/*! ERR50 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT1_ERR50(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR50_SHIFT)) & DMA_COMMON_ERRINT1_ERR50_MASK)

#define DMA_COMMON_ERRINT1_ERR51_MASK            (0x80000U)
#define DMA_COMMON_ERRINT1_ERR51_SHIFT           (19U)
/*! ERR51 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT1_ERR51(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR51_SHIFT)) & DMA_COMMON_ERRINT1_ERR51_MASK)
/*! @} */

/* The count of DMA_COMMON_ERRINT1 */
#define DMA_COMMON_ERRINT1_COUNT                 (1U)

/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels */
/*! @{ */

#define DMA_COMMON_INTENSET_INTEN0_MASK          (0x1U)
#define DMA_COMMON_INTENSET_INTEN0_SHIFT         (0U)
/*! INTEN0 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN0(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN0_SHIFT)) & DMA_COMMON_INTENSET_INTEN0_MASK)

#define DMA_COMMON_INTENSET_INTEN1_MASK          (0x2U)
#define DMA_COMMON_INTENSET_INTEN1_SHIFT         (1U)
/*! INTEN1 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN1(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN1_SHIFT)) & DMA_COMMON_INTENSET_INTEN1_MASK)

#define DMA_COMMON_INTENSET_INTEN2_MASK          (0x4U)
#define DMA_COMMON_INTENSET_INTEN2_SHIFT         (2U)
/*! INTEN2 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN2(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN2_SHIFT)) & DMA_COMMON_INTENSET_INTEN2_MASK)

#define DMA_COMMON_INTENSET_INTEN3_MASK          (0x8U)
#define DMA_COMMON_INTENSET_INTEN3_SHIFT         (3U)
/*! INTEN3 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN3(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN3_SHIFT)) & DMA_COMMON_INTENSET_INTEN3_MASK)

#define DMA_COMMON_INTENSET_INTEN4_MASK          (0x10U)
#define DMA_COMMON_INTENSET_INTEN4_SHIFT         (4U)
/*! INTEN4 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN4(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN4_SHIFT)) & DMA_COMMON_INTENSET_INTEN4_MASK)

#define DMA_COMMON_INTENSET_INTEN5_MASK          (0x20U)
#define DMA_COMMON_INTENSET_INTEN5_SHIFT         (5U)
/*! INTEN5 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN5(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN5_SHIFT)) & DMA_COMMON_INTENSET_INTEN5_MASK)

#define DMA_COMMON_INTENSET_INTEN6_MASK          (0x40U)
#define DMA_COMMON_INTENSET_INTEN6_SHIFT         (6U)
/*! INTEN6 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN6(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN6_SHIFT)) & DMA_COMMON_INTENSET_INTEN6_MASK)

#define DMA_COMMON_INTENSET_INTEN7_MASK          (0x80U)
#define DMA_COMMON_INTENSET_INTEN7_SHIFT         (7U)
/*! INTEN7 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN7(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN7_SHIFT)) & DMA_COMMON_INTENSET_INTEN7_MASK)

#define DMA_COMMON_INTENSET_INTEN8_MASK          (0x100U)
#define DMA_COMMON_INTENSET_INTEN8_SHIFT         (8U)
/*! INTEN8 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN8(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN8_SHIFT)) & DMA_COMMON_INTENSET_INTEN8_MASK)

#define DMA_COMMON_INTENSET_INTEN9_MASK          (0x200U)
#define DMA_COMMON_INTENSET_INTEN9_SHIFT         (9U)
/*! INTEN9 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN9(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN9_SHIFT)) & DMA_COMMON_INTENSET_INTEN9_MASK)

#define DMA_COMMON_INTENSET_INTEN10_MASK         (0x400U)
#define DMA_COMMON_INTENSET_INTEN10_SHIFT        (10U)
/*! INTEN10 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN10(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN10_SHIFT)) & DMA_COMMON_INTENSET_INTEN10_MASK)

#define DMA_COMMON_INTENSET_INTEN11_MASK         (0x800U)
#define DMA_COMMON_INTENSET_INTEN11_SHIFT        (11U)
/*! INTEN11 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN11(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN11_SHIFT)) & DMA_COMMON_INTENSET_INTEN11_MASK)

#define DMA_COMMON_INTENSET_INTEN12_MASK         (0x1000U)
#define DMA_COMMON_INTENSET_INTEN12_SHIFT        (12U)
/*! INTEN12 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN12(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN12_SHIFT)) & DMA_COMMON_INTENSET_INTEN12_MASK)

#define DMA_COMMON_INTENSET_INTEN13_MASK         (0x2000U)
#define DMA_COMMON_INTENSET_INTEN13_SHIFT        (13U)
/*! INTEN13 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN13(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN13_SHIFT)) & DMA_COMMON_INTENSET_INTEN13_MASK)

#define DMA_COMMON_INTENSET_INTEN14_MASK         (0x4000U)
#define DMA_COMMON_INTENSET_INTEN14_SHIFT        (14U)
/*! INTEN14 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN14(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN14_SHIFT)) & DMA_COMMON_INTENSET_INTEN14_MASK)

#define DMA_COMMON_INTENSET_INTEN15_MASK         (0x8000U)
#define DMA_COMMON_INTENSET_INTEN15_SHIFT        (15U)
/*! INTEN15 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN15(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN15_SHIFT)) & DMA_COMMON_INTENSET_INTEN15_MASK)

#define DMA_COMMON_INTENSET_INTEN16_MASK         (0x10000U)
#define DMA_COMMON_INTENSET_INTEN16_SHIFT        (16U)
/*! INTEN16 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN16(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN16_SHIFT)) & DMA_COMMON_INTENSET_INTEN16_MASK)

#define DMA_COMMON_INTENSET_INTEN17_MASK         (0x20000U)
#define DMA_COMMON_INTENSET_INTEN17_SHIFT        (17U)
/*! INTEN17 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN17(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN17_SHIFT)) & DMA_COMMON_INTENSET_INTEN17_MASK)

#define DMA_COMMON_INTENSET_INTEN18_MASK         (0x40000U)
#define DMA_COMMON_INTENSET_INTEN18_SHIFT        (18U)
/*! INTEN18 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN18(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN18_SHIFT)) & DMA_COMMON_INTENSET_INTEN18_MASK)

#define DMA_COMMON_INTENSET_INTEN19_MASK         (0x80000U)
#define DMA_COMMON_INTENSET_INTEN19_SHIFT        (19U)
/*! INTEN19 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN19(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN19_SHIFT)) & DMA_COMMON_INTENSET_INTEN19_MASK)

#define DMA_COMMON_INTENSET_INTEN20_MASK         (0x100000U)
#define DMA_COMMON_INTENSET_INTEN20_SHIFT        (20U)
/*! INTEN20 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN20(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN20_SHIFT)) & DMA_COMMON_INTENSET_INTEN20_MASK)

#define DMA_COMMON_INTENSET_INTEN21_MASK         (0x200000U)
#define DMA_COMMON_INTENSET_INTEN21_SHIFT        (21U)
/*! INTEN21 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN21(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN21_SHIFT)) & DMA_COMMON_INTENSET_INTEN21_MASK)

#define DMA_COMMON_INTENSET_INTEN22_MASK         (0x400000U)
#define DMA_COMMON_INTENSET_INTEN22_SHIFT        (22U)
/*! INTEN22 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN22(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN22_SHIFT)) & DMA_COMMON_INTENSET_INTEN22_MASK)

#define DMA_COMMON_INTENSET_INTEN23_MASK         (0x800000U)
#define DMA_COMMON_INTENSET_INTEN23_SHIFT        (23U)
/*! INTEN23 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN23(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN23_SHIFT)) & DMA_COMMON_INTENSET_INTEN23_MASK)

#define DMA_COMMON_INTENSET_INTEN24_MASK         (0x1000000U)
#define DMA_COMMON_INTENSET_INTEN24_SHIFT        (24U)
/*! INTEN24 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN24(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN24_SHIFT)) & DMA_COMMON_INTENSET_INTEN24_MASK)

#define DMA_COMMON_INTENSET_INTEN25_MASK         (0x2000000U)
#define DMA_COMMON_INTENSET_INTEN25_SHIFT        (25U)
/*! INTEN25 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN25(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN25_SHIFT)) & DMA_COMMON_INTENSET_INTEN25_MASK)

#define DMA_COMMON_INTENSET_INTEN26_MASK         (0x4000000U)
#define DMA_COMMON_INTENSET_INTEN26_SHIFT        (26U)
/*! INTEN26 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN26(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN26_SHIFT)) & DMA_COMMON_INTENSET_INTEN26_MASK)

#define DMA_COMMON_INTENSET_INTEN27_MASK         (0x8000000U)
#define DMA_COMMON_INTENSET_INTEN27_SHIFT        (27U)
/*! INTEN27 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN27(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN27_SHIFT)) & DMA_COMMON_INTENSET_INTEN27_MASK)

#define DMA_COMMON_INTENSET_INTEN28_MASK         (0x10000000U)
#define DMA_COMMON_INTENSET_INTEN28_SHIFT        (28U)
/*! INTEN28 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN28(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN28_SHIFT)) & DMA_COMMON_INTENSET_INTEN28_MASK)

#define DMA_COMMON_INTENSET_INTEN29_MASK         (0x20000000U)
#define DMA_COMMON_INTENSET_INTEN29_SHIFT        (29U)
/*! INTEN29 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN29(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN29_SHIFT)) & DMA_COMMON_INTENSET_INTEN29_MASK)

#define DMA_COMMON_INTENSET_INTEN30_MASK         (0x40000000U)
#define DMA_COMMON_INTENSET_INTEN30_SHIFT        (30U)
/*! INTEN30 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN30(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN30_SHIFT)) & DMA_COMMON_INTENSET_INTEN30_MASK)

#define DMA_COMMON_INTENSET_INTEN31_MASK         (0x80000000U)
#define DMA_COMMON_INTENSET_INTEN31_SHIFT        (31U)
/*! INTEN31 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN31(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN31_SHIFT)) & DMA_COMMON_INTENSET_INTEN31_MASK)
/*! @} */

/* The count of DMA_COMMON_INTENSET */
#define DMA_COMMON_INTENSET_COUNT                (1U)

/*! @name COMMON_INTENSET1 - Interrupt Enable read and Set for all DMA channels */
/*! @{ */

#define DMA_COMMON_INTENSET1_INTEN32_MASK        (0x1U)
#define DMA_COMMON_INTENSET1_INTEN32_SHIFT       (0U)
/*! INTEN32 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET1_INTEN32(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN32_SHIFT)) & DMA_COMMON_INTENSET1_INTEN32_MASK)

#define DMA_COMMON_INTENSET1_INTEN33_MASK        (0x2U)
#define DMA_COMMON_INTENSET1_INTEN33_SHIFT       (1U)
/*! INTEN33 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET1_INTEN33(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN33_SHIFT)) & DMA_COMMON_INTENSET1_INTEN33_MASK)

#define DMA_COMMON_INTENSET1_INTEN34_MASK        (0x4U)
#define DMA_COMMON_INTENSET1_INTEN34_SHIFT       (2U)
/*! INTEN34 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET1_INTEN34(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN34_SHIFT)) & DMA_COMMON_INTENSET1_INTEN34_MASK)

#define DMA_COMMON_INTENSET1_INTEN35_MASK        (0x8U)
#define DMA_COMMON_INTENSET1_INTEN35_SHIFT       (3U)
/*! INTEN35 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET1_INTEN35(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN35_SHIFT)) & DMA_COMMON_INTENSET1_INTEN35_MASK)

#define DMA_COMMON_INTENSET1_INTEN36_MASK        (0x10U)
#define DMA_COMMON_INTENSET1_INTEN36_SHIFT       (4U)
/*! INTEN36 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET1_INTEN36(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN36_SHIFT)) & DMA_COMMON_INTENSET1_INTEN36_MASK)

#define DMA_COMMON_INTENSET1_INTEN37_MASK        (0x20U)
#define DMA_COMMON_INTENSET1_INTEN37_SHIFT       (5U)
/*! INTEN37 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET1_INTEN37(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN37_SHIFT)) & DMA_COMMON_INTENSET1_INTEN37_MASK)

#define DMA_COMMON_INTENSET1_INTEN38_MASK        (0x40U)
#define DMA_COMMON_INTENSET1_INTEN38_SHIFT       (6U)
/*! INTEN38 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET1_INTEN38(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN38_SHIFT)) & DMA_COMMON_INTENSET1_INTEN38_MASK)

#define DMA_COMMON_INTENSET1_INTEN39_MASK        (0x80U)
#define DMA_COMMON_INTENSET1_INTEN39_SHIFT       (7U)
/*! INTEN39 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET1_INTEN39(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN39_SHIFT)) & DMA_COMMON_INTENSET1_INTEN39_MASK)

#define DMA_COMMON_INTENSET1_INTEN40_MASK        (0x100U)
#define DMA_COMMON_INTENSET1_INTEN40_SHIFT       (8U)
/*! INTEN40 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET1_INTEN40(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN40_SHIFT)) & DMA_COMMON_INTENSET1_INTEN40_MASK)

#define DMA_COMMON_INTENSET1_INTEN41_MASK        (0x200U)
#define DMA_COMMON_INTENSET1_INTEN41_SHIFT       (9U)
/*! INTEN41 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET1_INTEN41(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN41_SHIFT)) & DMA_COMMON_INTENSET1_INTEN41_MASK)

#define DMA_COMMON_INTENSET1_INTEN42_MASK        (0x400U)
#define DMA_COMMON_INTENSET1_INTEN42_SHIFT       (10U)
/*! INTEN42 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET1_INTEN42(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN42_SHIFT)) & DMA_COMMON_INTENSET1_INTEN42_MASK)

#define DMA_COMMON_INTENSET1_INTEN43_MASK        (0x800U)
#define DMA_COMMON_INTENSET1_INTEN43_SHIFT       (11U)
/*! INTEN43 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET1_INTEN43(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN43_SHIFT)) & DMA_COMMON_INTENSET1_INTEN43_MASK)

#define DMA_COMMON_INTENSET1_INTEN44_MASK        (0x1000U)
#define DMA_COMMON_INTENSET1_INTEN44_SHIFT       (12U)
/*! INTEN44 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET1_INTEN44(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN44_SHIFT)) & DMA_COMMON_INTENSET1_INTEN44_MASK)

#define DMA_COMMON_INTENSET1_INTEN45_MASK        (0x2000U)
#define DMA_COMMON_INTENSET1_INTEN45_SHIFT       (13U)
/*! INTEN45 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET1_INTEN45(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN45_SHIFT)) & DMA_COMMON_INTENSET1_INTEN45_MASK)

#define DMA_COMMON_INTENSET1_INTEN46_MASK        (0x4000U)
#define DMA_COMMON_INTENSET1_INTEN46_SHIFT       (14U)
/*! INTEN46 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET1_INTEN46(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN46_SHIFT)) & DMA_COMMON_INTENSET1_INTEN46_MASK)

#define DMA_COMMON_INTENSET1_INTEN47_MASK        (0x8000U)
#define DMA_COMMON_INTENSET1_INTEN47_SHIFT       (15U)
/*! INTEN47 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET1_INTEN47(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN47_SHIFT)) & DMA_COMMON_INTENSET1_INTEN47_MASK)

#define DMA_COMMON_INTENSET1_INTEN48_MASK        (0x10000U)
#define DMA_COMMON_INTENSET1_INTEN48_SHIFT       (16U)
/*! INTEN48 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET1_INTEN48(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN48_SHIFT)) & DMA_COMMON_INTENSET1_INTEN48_MASK)

#define DMA_COMMON_INTENSET1_INTEN49_MASK        (0x20000U)
#define DMA_COMMON_INTENSET1_INTEN49_SHIFT       (17U)
/*! INTEN49 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET1_INTEN49(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN49_SHIFT)) & DMA_COMMON_INTENSET1_INTEN49_MASK)

#define DMA_COMMON_INTENSET1_INTEN50_MASK        (0x40000U)
#define DMA_COMMON_INTENSET1_INTEN50_SHIFT       (18U)
/*! INTEN50 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET1_INTEN50(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN50_SHIFT)) & DMA_COMMON_INTENSET1_INTEN50_MASK)

#define DMA_COMMON_INTENSET1_INTEN51_MASK        (0x80000U)
#define DMA_COMMON_INTENSET1_INTEN51_SHIFT       (19U)
/*! INTEN51 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET1_INTEN51(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN51_SHIFT)) & DMA_COMMON_INTENSET1_INTEN51_MASK)
/*! @} */

/* The count of DMA_COMMON_INTENSET1 */
#define DMA_COMMON_INTENSET1_COUNT               (1U)

/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels */
/*! @{ */

#define DMA_COMMON_INTENCLR_CLR0_MASK            (0x1U)
#define DMA_COMMON_INTENCLR_CLR0_SHIFT           (0U)
/*! CLR0 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR0(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR0_SHIFT)) & DMA_COMMON_INTENCLR_CLR0_MASK)

#define DMA_COMMON_INTENCLR_CLR1_MASK            (0x2U)
#define DMA_COMMON_INTENCLR_CLR1_SHIFT           (1U)
/*! CLR1 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR1(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR1_SHIFT)) & DMA_COMMON_INTENCLR_CLR1_MASK)

#define DMA_COMMON_INTENCLR_CLR2_MASK            (0x4U)
#define DMA_COMMON_INTENCLR_CLR2_SHIFT           (2U)
/*! CLR2 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR2(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR2_SHIFT)) & DMA_COMMON_INTENCLR_CLR2_MASK)

#define DMA_COMMON_INTENCLR_CLR3_MASK            (0x8U)
#define DMA_COMMON_INTENCLR_CLR3_SHIFT           (3U)
/*! CLR3 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR3(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR3_SHIFT)) & DMA_COMMON_INTENCLR_CLR3_MASK)

#define DMA_COMMON_INTENCLR_CLR4_MASK            (0x10U)
#define DMA_COMMON_INTENCLR_CLR4_SHIFT           (4U)
/*! CLR4 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR4(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR4_SHIFT)) & DMA_COMMON_INTENCLR_CLR4_MASK)

#define DMA_COMMON_INTENCLR_CLR5_MASK            (0x20U)
#define DMA_COMMON_INTENCLR_CLR5_SHIFT           (5U)
/*! CLR5 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR5(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR5_SHIFT)) & DMA_COMMON_INTENCLR_CLR5_MASK)

#define DMA_COMMON_INTENCLR_CLR6_MASK            (0x40U)
#define DMA_COMMON_INTENCLR_CLR6_SHIFT           (6U)
/*! CLR6 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR6(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR6_SHIFT)) & DMA_COMMON_INTENCLR_CLR6_MASK)

#define DMA_COMMON_INTENCLR_CLR7_MASK            (0x80U)
#define DMA_COMMON_INTENCLR_CLR7_SHIFT           (7U)
/*! CLR7 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR7(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR7_SHIFT)) & DMA_COMMON_INTENCLR_CLR7_MASK)

#define DMA_COMMON_INTENCLR_CLR8_MASK            (0x100U)
#define DMA_COMMON_INTENCLR_CLR8_SHIFT           (8U)
/*! CLR8 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR8(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR8_SHIFT)) & DMA_COMMON_INTENCLR_CLR8_MASK)

#define DMA_COMMON_INTENCLR_CLR9_MASK            (0x200U)
#define DMA_COMMON_INTENCLR_CLR9_SHIFT           (9U)
/*! CLR9 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR9(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR9_SHIFT)) & DMA_COMMON_INTENCLR_CLR9_MASK)

#define DMA_COMMON_INTENCLR_CLR10_MASK           (0x400U)
#define DMA_COMMON_INTENCLR_CLR10_SHIFT          (10U)
/*! CLR10 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR10(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR10_SHIFT)) & DMA_COMMON_INTENCLR_CLR10_MASK)

#define DMA_COMMON_INTENCLR_CLR11_MASK           (0x800U)
#define DMA_COMMON_INTENCLR_CLR11_SHIFT          (11U)
/*! CLR11 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR11(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR11_SHIFT)) & DMA_COMMON_INTENCLR_CLR11_MASK)

#define DMA_COMMON_INTENCLR_CLR12_MASK           (0x1000U)
#define DMA_COMMON_INTENCLR_CLR12_SHIFT          (12U)
/*! CLR12 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR12(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR12_SHIFT)) & DMA_COMMON_INTENCLR_CLR12_MASK)

#define DMA_COMMON_INTENCLR_CLR13_MASK           (0x2000U)
#define DMA_COMMON_INTENCLR_CLR13_SHIFT          (13U)
/*! CLR13 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR13(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR13_SHIFT)) & DMA_COMMON_INTENCLR_CLR13_MASK)

#define DMA_COMMON_INTENCLR_CLR14_MASK           (0x4000U)
#define DMA_COMMON_INTENCLR_CLR14_SHIFT          (14U)
/*! CLR14 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR14(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR14_SHIFT)) & DMA_COMMON_INTENCLR_CLR14_MASK)

#define DMA_COMMON_INTENCLR_CLR15_MASK           (0x8000U)
#define DMA_COMMON_INTENCLR_CLR15_SHIFT          (15U)
/*! CLR15 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR15(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR15_SHIFT)) & DMA_COMMON_INTENCLR_CLR15_MASK)

#define DMA_COMMON_INTENCLR_CLR16_MASK           (0x10000U)
#define DMA_COMMON_INTENCLR_CLR16_SHIFT          (16U)
/*! CLR16 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR16(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR16_SHIFT)) & DMA_COMMON_INTENCLR_CLR16_MASK)

#define DMA_COMMON_INTENCLR_CLR17_MASK           (0x20000U)
#define DMA_COMMON_INTENCLR_CLR17_SHIFT          (17U)
/*! CLR17 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR17(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR17_SHIFT)) & DMA_COMMON_INTENCLR_CLR17_MASK)

#define DMA_COMMON_INTENCLR_CLR18_MASK           (0x40000U)
#define DMA_COMMON_INTENCLR_CLR18_SHIFT          (18U)
/*! CLR18 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR18(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR18_SHIFT)) & DMA_COMMON_INTENCLR_CLR18_MASK)

#define DMA_COMMON_INTENCLR_CLR19_MASK           (0x80000U)
#define DMA_COMMON_INTENCLR_CLR19_SHIFT          (19U)
/*! CLR19 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR19(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR19_SHIFT)) & DMA_COMMON_INTENCLR_CLR19_MASK)

#define DMA_COMMON_INTENCLR_CLR20_MASK           (0x100000U)
#define DMA_COMMON_INTENCLR_CLR20_SHIFT          (20U)
/*! CLR20 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR20(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR20_SHIFT)) & DMA_COMMON_INTENCLR_CLR20_MASK)

#define DMA_COMMON_INTENCLR_CLR21_MASK           (0x200000U)
#define DMA_COMMON_INTENCLR_CLR21_SHIFT          (21U)
/*! CLR21 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR21(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR21_SHIFT)) & DMA_COMMON_INTENCLR_CLR21_MASK)

#define DMA_COMMON_INTENCLR_CLR22_MASK           (0x400000U)
#define DMA_COMMON_INTENCLR_CLR22_SHIFT          (22U)
/*! CLR22 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR22(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR22_SHIFT)) & DMA_COMMON_INTENCLR_CLR22_MASK)

#define DMA_COMMON_INTENCLR_CLR23_MASK           (0x800000U)
#define DMA_COMMON_INTENCLR_CLR23_SHIFT          (23U)
/*! CLR23 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR23(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR23_SHIFT)) & DMA_COMMON_INTENCLR_CLR23_MASK)

#define DMA_COMMON_INTENCLR_CLR24_MASK           (0x1000000U)
#define DMA_COMMON_INTENCLR_CLR24_SHIFT          (24U)
/*! CLR24 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR24(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR24_SHIFT)) & DMA_COMMON_INTENCLR_CLR24_MASK)

#define DMA_COMMON_INTENCLR_CLR25_MASK           (0x2000000U)
#define DMA_COMMON_INTENCLR_CLR25_SHIFT          (25U)
/*! CLR25 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR25(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR25_SHIFT)) & DMA_COMMON_INTENCLR_CLR25_MASK)

#define DMA_COMMON_INTENCLR_CLR26_MASK           (0x4000000U)
#define DMA_COMMON_INTENCLR_CLR26_SHIFT          (26U)
/*! CLR26 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR26(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR26_SHIFT)) & DMA_COMMON_INTENCLR_CLR26_MASK)

#define DMA_COMMON_INTENCLR_CLR27_MASK           (0x8000000U)
#define DMA_COMMON_INTENCLR_CLR27_SHIFT          (27U)
/*! CLR27 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR27(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR27_SHIFT)) & DMA_COMMON_INTENCLR_CLR27_MASK)

#define DMA_COMMON_INTENCLR_CLR28_MASK           (0x10000000U)
#define DMA_COMMON_INTENCLR_CLR28_SHIFT          (28U)
/*! CLR28 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR28(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR28_SHIFT)) & DMA_COMMON_INTENCLR_CLR28_MASK)

#define DMA_COMMON_INTENCLR_CLR29_MASK           (0x20000000U)
#define DMA_COMMON_INTENCLR_CLR29_SHIFT          (29U)
/*! CLR29 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR29(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR29_SHIFT)) & DMA_COMMON_INTENCLR_CLR29_MASK)

#define DMA_COMMON_INTENCLR_CLR30_MASK           (0x40000000U)
#define DMA_COMMON_INTENCLR_CLR30_SHIFT          (30U)
/*! CLR30 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR30(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR30_SHIFT)) & DMA_COMMON_INTENCLR_CLR30_MASK)

#define DMA_COMMON_INTENCLR_CLR31_MASK           (0x80000000U)
#define DMA_COMMON_INTENCLR_CLR31_SHIFT          (31U)
/*! CLR31 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR31(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR31_SHIFT)) & DMA_COMMON_INTENCLR_CLR31_MASK)
/*! @} */

/* The count of DMA_COMMON_INTENCLR */
#define DMA_COMMON_INTENCLR_COUNT                (1U)

/*! @name COMMON_INTENCLR1 - Interrupt Enable Clear for all DMA channels */
/*! @{ */

#define DMA_COMMON_INTENCLR1_CLR32_MASK          (0x1U)
#define DMA_COMMON_INTENCLR1_CLR32_SHIFT         (0U)
/*! CLR32 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1.
 */
#define DMA_COMMON_INTENCLR1_CLR32(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR32_SHIFT)) & DMA_COMMON_INTENCLR1_CLR32_MASK)

#define DMA_COMMON_INTENCLR1_CLR33_MASK          (0x2U)
#define DMA_COMMON_INTENCLR1_CLR33_SHIFT         (1U)
/*! CLR33 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1.
 */
#define DMA_COMMON_INTENCLR1_CLR33(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR33_SHIFT)) & DMA_COMMON_INTENCLR1_CLR33_MASK)

#define DMA_COMMON_INTENCLR1_CLR34_MASK          (0x4U)
#define DMA_COMMON_INTENCLR1_CLR34_SHIFT         (2U)
/*! CLR34 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1.
 */
#define DMA_COMMON_INTENCLR1_CLR34(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR34_SHIFT)) & DMA_COMMON_INTENCLR1_CLR34_MASK)

#define DMA_COMMON_INTENCLR1_CLR35_MASK          (0x8U)
#define DMA_COMMON_INTENCLR1_CLR35_SHIFT         (3U)
/*! CLR35 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1.
 */
#define DMA_COMMON_INTENCLR1_CLR35(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR35_SHIFT)) & DMA_COMMON_INTENCLR1_CLR35_MASK)

#define DMA_COMMON_INTENCLR1_CLR36_MASK          (0x10U)
#define DMA_COMMON_INTENCLR1_CLR36_SHIFT         (4U)
/*! CLR36 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1.
 */
#define DMA_COMMON_INTENCLR1_CLR36(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR36_SHIFT)) & DMA_COMMON_INTENCLR1_CLR36_MASK)

#define DMA_COMMON_INTENCLR1_CLR37_MASK          (0x20U)
#define DMA_COMMON_INTENCLR1_CLR37_SHIFT         (5U)
/*! CLR37 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1.
 */
#define DMA_COMMON_INTENCLR1_CLR37(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR37_SHIFT)) & DMA_COMMON_INTENCLR1_CLR37_MASK)

#define DMA_COMMON_INTENCLR1_CLR38_MASK          (0x40U)
#define DMA_COMMON_INTENCLR1_CLR38_SHIFT         (6U)
/*! CLR38 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1.
 */
#define DMA_COMMON_INTENCLR1_CLR38(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR38_SHIFT)) & DMA_COMMON_INTENCLR1_CLR38_MASK)

#define DMA_COMMON_INTENCLR1_CLR39_MASK          (0x80U)
#define DMA_COMMON_INTENCLR1_CLR39_SHIFT         (7U)
/*! CLR39 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1.
 */
#define DMA_COMMON_INTENCLR1_CLR39(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR39_SHIFT)) & DMA_COMMON_INTENCLR1_CLR39_MASK)

#define DMA_COMMON_INTENCLR1_CLR40_MASK          (0x100U)
#define DMA_COMMON_INTENCLR1_CLR40_SHIFT         (8U)
/*! CLR40 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1.
 */
#define DMA_COMMON_INTENCLR1_CLR40(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR40_SHIFT)) & DMA_COMMON_INTENCLR1_CLR40_MASK)

#define DMA_COMMON_INTENCLR1_CLR41_MASK          (0x200U)
#define DMA_COMMON_INTENCLR1_CLR41_SHIFT         (9U)
/*! CLR41 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1.
 */
#define DMA_COMMON_INTENCLR1_CLR41(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR41_SHIFT)) & DMA_COMMON_INTENCLR1_CLR41_MASK)

#define DMA_COMMON_INTENCLR1_CLR42_MASK          (0x400U)
#define DMA_COMMON_INTENCLR1_CLR42_SHIFT         (10U)
/*! CLR42 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1.
 */
#define DMA_COMMON_INTENCLR1_CLR42(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR42_SHIFT)) & DMA_COMMON_INTENCLR1_CLR42_MASK)

#define DMA_COMMON_INTENCLR1_CLR43_MASK          (0x800U)
#define DMA_COMMON_INTENCLR1_CLR43_SHIFT         (11U)
/*! CLR43 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1.
 */
#define DMA_COMMON_INTENCLR1_CLR43(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR43_SHIFT)) & DMA_COMMON_INTENCLR1_CLR43_MASK)

#define DMA_COMMON_INTENCLR1_CLR44_MASK          (0x1000U)
#define DMA_COMMON_INTENCLR1_CLR44_SHIFT         (12U)
/*! CLR44 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1.
 */
#define DMA_COMMON_INTENCLR1_CLR44(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR44_SHIFT)) & DMA_COMMON_INTENCLR1_CLR44_MASK)

#define DMA_COMMON_INTENCLR1_CLR45_MASK          (0x2000U)
#define DMA_COMMON_INTENCLR1_CLR45_SHIFT         (13U)
/*! CLR45 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1.
 */
#define DMA_COMMON_INTENCLR1_CLR45(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR45_SHIFT)) & DMA_COMMON_INTENCLR1_CLR45_MASK)

#define DMA_COMMON_INTENCLR1_CLR46_MASK          (0x4000U)
#define DMA_COMMON_INTENCLR1_CLR46_SHIFT         (14U)
/*! CLR46 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1.
 */
#define DMA_COMMON_INTENCLR1_CLR46(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR46_SHIFT)) & DMA_COMMON_INTENCLR1_CLR46_MASK)

#define DMA_COMMON_INTENCLR1_CLR47_MASK          (0x8000U)
#define DMA_COMMON_INTENCLR1_CLR47_SHIFT         (15U)
/*! CLR47 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1.
 */
#define DMA_COMMON_INTENCLR1_CLR47(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR47_SHIFT)) & DMA_COMMON_INTENCLR1_CLR47_MASK)

#define DMA_COMMON_INTENCLR1_CLR48_MASK          (0x10000U)
#define DMA_COMMON_INTENCLR1_CLR48_SHIFT         (16U)
/*! CLR48 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1.
 */
#define DMA_COMMON_INTENCLR1_CLR48(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR48_SHIFT)) & DMA_COMMON_INTENCLR1_CLR48_MASK)

#define DMA_COMMON_INTENCLR1_CLR49_MASK          (0x20000U)
#define DMA_COMMON_INTENCLR1_CLR49_SHIFT         (17U)
/*! CLR49 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1.
 */
#define DMA_COMMON_INTENCLR1_CLR49(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR49_SHIFT)) & DMA_COMMON_INTENCLR1_CLR49_MASK)

#define DMA_COMMON_INTENCLR1_CLR50_MASK          (0x40000U)
#define DMA_COMMON_INTENCLR1_CLR50_SHIFT         (18U)
/*! CLR50 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1.
 */
#define DMA_COMMON_INTENCLR1_CLR50(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR50_SHIFT)) & DMA_COMMON_INTENCLR1_CLR50_MASK)

#define DMA_COMMON_INTENCLR1_CLR51_MASK          (0x80000U)
#define DMA_COMMON_INTENCLR1_CLR51_SHIFT         (19U)
/*! CLR51 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1.
 */
#define DMA_COMMON_INTENCLR1_CLR51(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR51_SHIFT)) & DMA_COMMON_INTENCLR1_CLR51_MASK)
/*! @} */

/* The count of DMA_COMMON_INTENCLR1 */
#define DMA_COMMON_INTENCLR1_COUNT               (1U)

/*! @name COMMON_INTA - Interrupt A status for all DMA channels */
/*! @{ */

#define DMA_COMMON_INTA_INTA0_MASK               (0x1U)
#define DMA_COMMON_INTA_INTA0_SHIFT              (0U)
/*! INTA0 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA0(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA0_SHIFT)) & DMA_COMMON_INTA_INTA0_MASK)

#define DMA_COMMON_INTA_INTA1_MASK               (0x2U)
#define DMA_COMMON_INTA_INTA1_SHIFT              (1U)
/*! INTA1 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA1(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA1_SHIFT)) & DMA_COMMON_INTA_INTA1_MASK)

#define DMA_COMMON_INTA_INTA2_MASK               (0x4U)
#define DMA_COMMON_INTA_INTA2_SHIFT              (2U)
/*! INTA2 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA2(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA2_SHIFT)) & DMA_COMMON_INTA_INTA2_MASK)

#define DMA_COMMON_INTA_INTA3_MASK               (0x8U)
#define DMA_COMMON_INTA_INTA3_SHIFT              (3U)
/*! INTA3 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA3(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA3_SHIFT)) & DMA_COMMON_INTA_INTA3_MASK)

#define DMA_COMMON_INTA_INTA4_MASK               (0x10U)
#define DMA_COMMON_INTA_INTA4_SHIFT              (4U)
/*! INTA4 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA4(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA4_SHIFT)) & DMA_COMMON_INTA_INTA4_MASK)

#define DMA_COMMON_INTA_INTA5_MASK               (0x20U)
#define DMA_COMMON_INTA_INTA5_SHIFT              (5U)
/*! INTA5 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA5(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA5_SHIFT)) & DMA_COMMON_INTA_INTA5_MASK)

#define DMA_COMMON_INTA_INTA6_MASK               (0x40U)
#define DMA_COMMON_INTA_INTA6_SHIFT              (6U)
/*! INTA6 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA6(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA6_SHIFT)) & DMA_COMMON_INTA_INTA6_MASK)

#define DMA_COMMON_INTA_INTA7_MASK               (0x80U)
#define DMA_COMMON_INTA_INTA7_SHIFT              (7U)
/*! INTA7 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA7(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA7_SHIFT)) & DMA_COMMON_INTA_INTA7_MASK)

#define DMA_COMMON_INTA_INTA8_MASK               (0x100U)
#define DMA_COMMON_INTA_INTA8_SHIFT              (8U)
/*! INTA8 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA8(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA8_SHIFT)) & DMA_COMMON_INTA_INTA8_MASK)

#define DMA_COMMON_INTA_INTA9_MASK               (0x200U)
#define DMA_COMMON_INTA_INTA9_SHIFT              (9U)
/*! INTA9 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA9(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA9_SHIFT)) & DMA_COMMON_INTA_INTA9_MASK)

#define DMA_COMMON_INTA_INTA10_MASK              (0x400U)
#define DMA_COMMON_INTA_INTA10_SHIFT             (10U)
/*! INTA10 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA10(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA10_SHIFT)) & DMA_COMMON_INTA_INTA10_MASK)

#define DMA_COMMON_INTA_INTA11_MASK              (0x800U)
#define DMA_COMMON_INTA_INTA11_SHIFT             (11U)
/*! INTA11 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA11(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA11_SHIFT)) & DMA_COMMON_INTA_INTA11_MASK)

#define DMA_COMMON_INTA_INTA12_MASK              (0x1000U)
#define DMA_COMMON_INTA_INTA12_SHIFT             (12U)
/*! INTA12 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA12(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA12_SHIFT)) & DMA_COMMON_INTA_INTA12_MASK)

#define DMA_COMMON_INTA_INTA13_MASK              (0x2000U)
#define DMA_COMMON_INTA_INTA13_SHIFT             (13U)
/*! INTA13 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA13(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA13_SHIFT)) & DMA_COMMON_INTA_INTA13_MASK)

#define DMA_COMMON_INTA_INTA14_MASK              (0x4000U)
#define DMA_COMMON_INTA_INTA14_SHIFT             (14U)
/*! INTA14 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA14(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA14_SHIFT)) & DMA_COMMON_INTA_INTA14_MASK)

#define DMA_COMMON_INTA_INTA15_MASK              (0x8000U)
#define DMA_COMMON_INTA_INTA15_SHIFT             (15U)
/*! INTA15 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA15(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA15_SHIFT)) & DMA_COMMON_INTA_INTA15_MASK)

#define DMA_COMMON_INTA_INTA16_MASK              (0x10000U)
#define DMA_COMMON_INTA_INTA16_SHIFT             (16U)
/*! INTA16 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA16(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA16_SHIFT)) & DMA_COMMON_INTA_INTA16_MASK)

#define DMA_COMMON_INTA_INTA17_MASK              (0x20000U)
#define DMA_COMMON_INTA_INTA17_SHIFT             (17U)
/*! INTA17 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA17(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA17_SHIFT)) & DMA_COMMON_INTA_INTA17_MASK)

#define DMA_COMMON_INTA_INTA18_MASK              (0x40000U)
#define DMA_COMMON_INTA_INTA18_SHIFT             (18U)
/*! INTA18 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA18(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA18_SHIFT)) & DMA_COMMON_INTA_INTA18_MASK)

#define DMA_COMMON_INTA_INTA19_MASK              (0x80000U)
#define DMA_COMMON_INTA_INTA19_SHIFT             (19U)
/*! INTA19 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA19(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA19_SHIFT)) & DMA_COMMON_INTA_INTA19_MASK)

#define DMA_COMMON_INTA_INTA20_MASK              (0x100000U)
#define DMA_COMMON_INTA_INTA20_SHIFT             (20U)
/*! INTA20 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA20(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA20_SHIFT)) & DMA_COMMON_INTA_INTA20_MASK)

#define DMA_COMMON_INTA_INTA21_MASK              (0x200000U)
#define DMA_COMMON_INTA_INTA21_SHIFT             (21U)
/*! INTA21 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA21(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA21_SHIFT)) & DMA_COMMON_INTA_INTA21_MASK)

#define DMA_COMMON_INTA_INTA22_MASK              (0x400000U)
#define DMA_COMMON_INTA_INTA22_SHIFT             (22U)
/*! INTA22 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA22(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA22_SHIFT)) & DMA_COMMON_INTA_INTA22_MASK)

#define DMA_COMMON_INTA_INTA23_MASK              (0x800000U)
#define DMA_COMMON_INTA_INTA23_SHIFT             (23U)
/*! INTA23 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA23(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA23_SHIFT)) & DMA_COMMON_INTA_INTA23_MASK)

#define DMA_COMMON_INTA_INTA24_MASK              (0x1000000U)
#define DMA_COMMON_INTA_INTA24_SHIFT             (24U)
/*! INTA24 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA24(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA24_SHIFT)) & DMA_COMMON_INTA_INTA24_MASK)

#define DMA_COMMON_INTA_INTA25_MASK              (0x2000000U)
#define DMA_COMMON_INTA_INTA25_SHIFT             (25U)
/*! INTA25 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA25(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA25_SHIFT)) & DMA_COMMON_INTA_INTA25_MASK)

#define DMA_COMMON_INTA_INTA26_MASK              (0x4000000U)
#define DMA_COMMON_INTA_INTA26_SHIFT             (26U)
/*! INTA26 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA26(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA26_SHIFT)) & DMA_COMMON_INTA_INTA26_MASK)

#define DMA_COMMON_INTA_INTA27_MASK              (0x8000000U)
#define DMA_COMMON_INTA_INTA27_SHIFT             (27U)
/*! INTA27 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA27(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA27_SHIFT)) & DMA_COMMON_INTA_INTA27_MASK)

#define DMA_COMMON_INTA_INTA28_MASK              (0x10000000U)
#define DMA_COMMON_INTA_INTA28_SHIFT             (28U)
/*! INTA28 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA28(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA28_SHIFT)) & DMA_COMMON_INTA_INTA28_MASK)

#define DMA_COMMON_INTA_INTA29_MASK              (0x20000000U)
#define DMA_COMMON_INTA_INTA29_SHIFT             (29U)
/*! INTA29 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA29(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA29_SHIFT)) & DMA_COMMON_INTA_INTA29_MASK)

#define DMA_COMMON_INTA_INTA30_MASK              (0x40000000U)
#define DMA_COMMON_INTA_INTA30_SHIFT             (30U)
/*! INTA30 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA30(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA30_SHIFT)) & DMA_COMMON_INTA_INTA30_MASK)

#define DMA_COMMON_INTA_INTA31_MASK              (0x80000000U)
#define DMA_COMMON_INTA_INTA31_SHIFT             (31U)
/*! INTA31 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA31(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA31_SHIFT)) & DMA_COMMON_INTA_INTA31_MASK)
/*! @} */

/* The count of DMA_COMMON_INTA */
#define DMA_COMMON_INTA_COUNT                    (1U)

/*! @name COMMON_INTA1 - Interrupt A status for all DMA channels */
/*! @{ */

#define DMA_COMMON_INTA1_INTA32_MASK             (0x1U)
#define DMA_COMMON_INTA1_INTA32_SHIFT            (0U)
/*! INTA32 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA1_INTA32(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA32_SHIFT)) & DMA_COMMON_INTA1_INTA32_MASK)

#define DMA_COMMON_INTA1_INTA33_MASK             (0x2U)
#define DMA_COMMON_INTA1_INTA33_SHIFT            (1U)
/*! INTA33 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA1_INTA33(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA33_SHIFT)) & DMA_COMMON_INTA1_INTA33_MASK)

#define DMA_COMMON_INTA1_INTA34_MASK             (0x4U)
#define DMA_COMMON_INTA1_INTA34_SHIFT            (2U)
/*! INTA34 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA1_INTA34(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA34_SHIFT)) & DMA_COMMON_INTA1_INTA34_MASK)

#define DMA_COMMON_INTA1_INTA35_MASK             (0x8U)
#define DMA_COMMON_INTA1_INTA35_SHIFT            (3U)
/*! INTA35 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA1_INTA35(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA35_SHIFT)) & DMA_COMMON_INTA1_INTA35_MASK)

#define DMA_COMMON_INTA1_INTA36_MASK             (0x10U)
#define DMA_COMMON_INTA1_INTA36_SHIFT            (4U)
/*! INTA36 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA1_INTA36(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA36_SHIFT)) & DMA_COMMON_INTA1_INTA36_MASK)

#define DMA_COMMON_INTA1_INTA37_MASK             (0x20U)
#define DMA_COMMON_INTA1_INTA37_SHIFT            (5U)
/*! INTA37 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA1_INTA37(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA37_SHIFT)) & DMA_COMMON_INTA1_INTA37_MASK)

#define DMA_COMMON_INTA1_INTA38_MASK             (0x40U)
#define DMA_COMMON_INTA1_INTA38_SHIFT            (6U)
/*! INTA38 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA1_INTA38(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA38_SHIFT)) & DMA_COMMON_INTA1_INTA38_MASK)

#define DMA_COMMON_INTA1_INTA39_MASK             (0x80U)
#define DMA_COMMON_INTA1_INTA39_SHIFT            (7U)
/*! INTA39 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA1_INTA39(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA39_SHIFT)) & DMA_COMMON_INTA1_INTA39_MASK)

#define DMA_COMMON_INTA1_INTA40_MASK             (0x100U)
#define DMA_COMMON_INTA1_INTA40_SHIFT            (8U)
/*! INTA40 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA1_INTA40(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA40_SHIFT)) & DMA_COMMON_INTA1_INTA40_MASK)

#define DMA_COMMON_INTA1_INTA41_MASK             (0x200U)
#define DMA_COMMON_INTA1_INTA41_SHIFT            (9U)
/*! INTA41 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA1_INTA41(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA41_SHIFT)) & DMA_COMMON_INTA1_INTA41_MASK)

#define DMA_COMMON_INTA1_INTA42_MASK             (0x400U)
#define DMA_COMMON_INTA1_INTA42_SHIFT            (10U)
/*! INTA42 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA1_INTA42(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA42_SHIFT)) & DMA_COMMON_INTA1_INTA42_MASK)

#define DMA_COMMON_INTA1_INTA43_MASK             (0x800U)
#define DMA_COMMON_INTA1_INTA43_SHIFT            (11U)
/*! INTA43 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA1_INTA43(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA43_SHIFT)) & DMA_COMMON_INTA1_INTA43_MASK)

#define DMA_COMMON_INTA1_INTA44_MASK             (0x1000U)
#define DMA_COMMON_INTA1_INTA44_SHIFT            (12U)
/*! INTA44 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA1_INTA44(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA44_SHIFT)) & DMA_COMMON_INTA1_INTA44_MASK)

#define DMA_COMMON_INTA1_INTA45_MASK             (0x2000U)
#define DMA_COMMON_INTA1_INTA45_SHIFT            (13U)
/*! INTA45 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA1_INTA45(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA45_SHIFT)) & DMA_COMMON_INTA1_INTA45_MASK)

#define DMA_COMMON_INTA1_INTA46_MASK             (0x4000U)
#define DMA_COMMON_INTA1_INTA46_SHIFT            (14U)
/*! INTA46 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA1_INTA46(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA46_SHIFT)) & DMA_COMMON_INTA1_INTA46_MASK)

#define DMA_COMMON_INTA1_INTA47_MASK             (0x8000U)
#define DMA_COMMON_INTA1_INTA47_SHIFT            (15U)
/*! INTA47 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA1_INTA47(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA47_SHIFT)) & DMA_COMMON_INTA1_INTA47_MASK)

#define DMA_COMMON_INTA1_INTA48_MASK             (0x10000U)
#define DMA_COMMON_INTA1_INTA48_SHIFT            (16U)
/*! INTA48 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA1_INTA48(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA48_SHIFT)) & DMA_COMMON_INTA1_INTA48_MASK)

#define DMA_COMMON_INTA1_INTA49_MASK             (0x20000U)
#define DMA_COMMON_INTA1_INTA49_SHIFT            (17U)
/*! INTA49 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA1_INTA49(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA49_SHIFT)) & DMA_COMMON_INTA1_INTA49_MASK)

#define DMA_COMMON_INTA1_INTA50_MASK             (0x40000U)
#define DMA_COMMON_INTA1_INTA50_SHIFT            (18U)
/*! INTA50 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA1_INTA50(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA50_SHIFT)) & DMA_COMMON_INTA1_INTA50_MASK)

#define DMA_COMMON_INTA1_INTA51_MASK             (0x80000U)
#define DMA_COMMON_INTA1_INTA51_SHIFT            (19U)
/*! INTA51 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA1_INTA51(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA51_SHIFT)) & DMA_COMMON_INTA1_INTA51_MASK)
/*! @} */

/* The count of DMA_COMMON_INTA1 */
#define DMA_COMMON_INTA1_COUNT                   (1U)

/*! @name COMMON_INTB - Interrupt B status for all DMA channels */
/*! @{ */

#define DMA_COMMON_INTB_INTB0_MASK               (0x1U)
#define DMA_COMMON_INTB_INTB0_SHIFT              (0U)
/*! INTB0 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB0(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB0_SHIFT)) & DMA_COMMON_INTB_INTB0_MASK)

#define DMA_COMMON_INTB_INTB1_MASK               (0x2U)
#define DMA_COMMON_INTB_INTB1_SHIFT              (1U)
/*! INTB1 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB1(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB1_SHIFT)) & DMA_COMMON_INTB_INTB1_MASK)

#define DMA_COMMON_INTB_INTB2_MASK               (0x4U)
#define DMA_COMMON_INTB_INTB2_SHIFT              (2U)
/*! INTB2 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB2(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB2_SHIFT)) & DMA_COMMON_INTB_INTB2_MASK)

#define DMA_COMMON_INTB_INTB3_MASK               (0x8U)
#define DMA_COMMON_INTB_INTB3_SHIFT              (3U)
/*! INTB3 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB3(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB3_SHIFT)) & DMA_COMMON_INTB_INTB3_MASK)

#define DMA_COMMON_INTB_INTB4_MASK               (0x10U)
#define DMA_COMMON_INTB_INTB4_SHIFT              (4U)
/*! INTB4 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB4(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB4_SHIFT)) & DMA_COMMON_INTB_INTB4_MASK)

#define DMA_COMMON_INTB_INTB5_MASK               (0x20U)
#define DMA_COMMON_INTB_INTB5_SHIFT              (5U)
/*! INTB5 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB5(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB5_SHIFT)) & DMA_COMMON_INTB_INTB5_MASK)

#define DMA_COMMON_INTB_INTB6_MASK               (0x40U)
#define DMA_COMMON_INTB_INTB6_SHIFT              (6U)
/*! INTB6 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB6(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB6_SHIFT)) & DMA_COMMON_INTB_INTB6_MASK)

#define DMA_COMMON_INTB_INTB7_MASK               (0x80U)
#define DMA_COMMON_INTB_INTB7_SHIFT              (7U)
/*! INTB7 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB7(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB7_SHIFT)) & DMA_COMMON_INTB_INTB7_MASK)

#define DMA_COMMON_INTB_INTB8_MASK               (0x100U)
#define DMA_COMMON_INTB_INTB8_SHIFT              (8U)
/*! INTB8 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB8(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB8_SHIFT)) & DMA_COMMON_INTB_INTB8_MASK)

#define DMA_COMMON_INTB_INTB9_MASK               (0x200U)
#define DMA_COMMON_INTB_INTB9_SHIFT              (9U)
/*! INTB9 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB9(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB9_SHIFT)) & DMA_COMMON_INTB_INTB9_MASK)

#define DMA_COMMON_INTB_INTB10_MASK              (0x400U)
#define DMA_COMMON_INTB_INTB10_SHIFT             (10U)
/*! INTB10 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB10(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB10_SHIFT)) & DMA_COMMON_INTB_INTB10_MASK)

#define DMA_COMMON_INTB_INTB11_MASK              (0x800U)
#define DMA_COMMON_INTB_INTB11_SHIFT             (11U)
/*! INTB11 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB11(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB11_SHIFT)) & DMA_COMMON_INTB_INTB11_MASK)

#define DMA_COMMON_INTB_INTB12_MASK              (0x1000U)
#define DMA_COMMON_INTB_INTB12_SHIFT             (12U)
/*! INTB12 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB12(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB12_SHIFT)) & DMA_COMMON_INTB_INTB12_MASK)

#define DMA_COMMON_INTB_INTB13_MASK              (0x2000U)
#define DMA_COMMON_INTB_INTB13_SHIFT             (13U)
/*! INTB13 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB13(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB13_SHIFT)) & DMA_COMMON_INTB_INTB13_MASK)

#define DMA_COMMON_INTB_INTB14_MASK              (0x4000U)
#define DMA_COMMON_INTB_INTB14_SHIFT             (14U)
/*! INTB14 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB14(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB14_SHIFT)) & DMA_COMMON_INTB_INTB14_MASK)

#define DMA_COMMON_INTB_INTB15_MASK              (0x8000U)
#define DMA_COMMON_INTB_INTB15_SHIFT             (15U)
/*! INTB15 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB15(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB15_SHIFT)) & DMA_COMMON_INTB_INTB15_MASK)

#define DMA_COMMON_INTB_INTB16_MASK              (0x10000U)
#define DMA_COMMON_INTB_INTB16_SHIFT             (16U)
/*! INTB16 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB16(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB16_SHIFT)) & DMA_COMMON_INTB_INTB16_MASK)

#define DMA_COMMON_INTB_INTB17_MASK              (0x20000U)
#define DMA_COMMON_INTB_INTB17_SHIFT             (17U)
/*! INTB17 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB17(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB17_SHIFT)) & DMA_COMMON_INTB_INTB17_MASK)

#define DMA_COMMON_INTB_INTB18_MASK              (0x40000U)
#define DMA_COMMON_INTB_INTB18_SHIFT             (18U)
/*! INTB18 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB18(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB18_SHIFT)) & DMA_COMMON_INTB_INTB18_MASK)

#define DMA_COMMON_INTB_INTB19_MASK              (0x80000U)
#define DMA_COMMON_INTB_INTB19_SHIFT             (19U)
/*! INTB19 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB19(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB19_SHIFT)) & DMA_COMMON_INTB_INTB19_MASK)

#define DMA_COMMON_INTB_INTB20_MASK              (0x100000U)
#define DMA_COMMON_INTB_INTB20_SHIFT             (20U)
/*! INTB20 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB20(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB20_SHIFT)) & DMA_COMMON_INTB_INTB20_MASK)

#define DMA_COMMON_INTB_INTB21_MASK              (0x200000U)
#define DMA_COMMON_INTB_INTB21_SHIFT             (21U)
/*! INTB21 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB21(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB21_SHIFT)) & DMA_COMMON_INTB_INTB21_MASK)

#define DMA_COMMON_INTB_INTB22_MASK              (0x400000U)
#define DMA_COMMON_INTB_INTB22_SHIFT             (22U)
/*! INTB22 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB22(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB22_SHIFT)) & DMA_COMMON_INTB_INTB22_MASK)

#define DMA_COMMON_INTB_INTB23_MASK              (0x800000U)
#define DMA_COMMON_INTB_INTB23_SHIFT             (23U)
/*! INTB23 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB23(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB23_SHIFT)) & DMA_COMMON_INTB_INTB23_MASK)

#define DMA_COMMON_INTB_INTB24_MASK              (0x1000000U)
#define DMA_COMMON_INTB_INTB24_SHIFT             (24U)
/*! INTB24 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB24(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB24_SHIFT)) & DMA_COMMON_INTB_INTB24_MASK)

#define DMA_COMMON_INTB_INTB25_MASK              (0x2000000U)
#define DMA_COMMON_INTB_INTB25_SHIFT             (25U)
/*! INTB25 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB25(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB25_SHIFT)) & DMA_COMMON_INTB_INTB25_MASK)

#define DMA_COMMON_INTB_INTB26_MASK              (0x4000000U)
#define DMA_COMMON_INTB_INTB26_SHIFT             (26U)
/*! INTB26 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB26(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB26_SHIFT)) & DMA_COMMON_INTB_INTB26_MASK)

#define DMA_COMMON_INTB_INTB27_MASK              (0x8000000U)
#define DMA_COMMON_INTB_INTB27_SHIFT             (27U)
/*! INTB27 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB27(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB27_SHIFT)) & DMA_COMMON_INTB_INTB27_MASK)

#define DMA_COMMON_INTB_INTB28_MASK              (0x10000000U)
#define DMA_COMMON_INTB_INTB28_SHIFT             (28U)
/*! INTB28 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB28(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB28_SHIFT)) & DMA_COMMON_INTB_INTB28_MASK)

#define DMA_COMMON_INTB_INTB29_MASK              (0x20000000U)
#define DMA_COMMON_INTB_INTB29_SHIFT             (29U)
/*! INTB29 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB29(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB29_SHIFT)) & DMA_COMMON_INTB_INTB29_MASK)

#define DMA_COMMON_INTB_INTB30_MASK              (0x40000000U)
#define DMA_COMMON_INTB_INTB30_SHIFT             (30U)
/*! INTB30 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB30(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB30_SHIFT)) & DMA_COMMON_INTB_INTB30_MASK)

#define DMA_COMMON_INTB_INTB31_MASK              (0x80000000U)
#define DMA_COMMON_INTB_INTB31_SHIFT             (31U)
/*! INTB31 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB31(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB31_SHIFT)) & DMA_COMMON_INTB_INTB31_MASK)
/*! @} */

/* The count of DMA_COMMON_INTB */
#define DMA_COMMON_INTB_COUNT                    (1U)

/*! @name COMMON_INTB1 - Interrupt B status for all DMA channels */
/*! @{ */

#define DMA_COMMON_INTB1_INTB0_MASK              (0x1U)
#define DMA_COMMON_INTB1_INTB0_SHIFT             (0U)
/*! INTB0 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB1_INTB0(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB0_SHIFT)) & DMA_COMMON_INTB1_INTB0_MASK)

#define DMA_COMMON_INTB1_INTB1_MASK              (0x2U)
#define DMA_COMMON_INTB1_INTB1_SHIFT             (1U)
/*! INTB1 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB1_INTB1(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB1_SHIFT)) & DMA_COMMON_INTB1_INTB1_MASK)

#define DMA_COMMON_INTB1_INTB2_MASK              (0x4U)
#define DMA_COMMON_INTB1_INTB2_SHIFT             (2U)
/*! INTB2 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB1_INTB2(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB2_SHIFT)) & DMA_COMMON_INTB1_INTB2_MASK)

#define DMA_COMMON_INTB1_INTB3_MASK              (0x8U)
#define DMA_COMMON_INTB1_INTB3_SHIFT             (3U)
/*! INTB3 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB1_INTB3(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB3_SHIFT)) & DMA_COMMON_INTB1_INTB3_MASK)

#define DMA_COMMON_INTB1_INTB4_MASK              (0x10U)
#define DMA_COMMON_INTB1_INTB4_SHIFT             (4U)
/*! INTB4 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB1_INTB4(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB4_SHIFT)) & DMA_COMMON_INTB1_INTB4_MASK)

#define DMA_COMMON_INTB1_INTB5_MASK              (0x20U)
#define DMA_COMMON_INTB1_INTB5_SHIFT             (5U)
/*! INTB5 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB1_INTB5(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB5_SHIFT)) & DMA_COMMON_INTB1_INTB5_MASK)

#define DMA_COMMON_INTB1_INTB6_MASK              (0x40U)
#define DMA_COMMON_INTB1_INTB6_SHIFT             (6U)
/*! INTB6 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB1_INTB6(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB6_SHIFT)) & DMA_COMMON_INTB1_INTB6_MASK)

#define DMA_COMMON_INTB1_INTB7_MASK              (0x80U)
#define DMA_COMMON_INTB1_INTB7_SHIFT             (7U)
/*! INTB7 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB1_INTB7(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB7_SHIFT)) & DMA_COMMON_INTB1_INTB7_MASK)

#define DMA_COMMON_INTB1_INTB8_MASK              (0x100U)
#define DMA_COMMON_INTB1_INTB8_SHIFT             (8U)
/*! INTB8 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB1_INTB8(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB8_SHIFT)) & DMA_COMMON_INTB1_INTB8_MASK)

#define DMA_COMMON_INTB1_INTB9_MASK              (0x200U)
#define DMA_COMMON_INTB1_INTB9_SHIFT             (9U)
/*! INTB9 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB1_INTB9(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB9_SHIFT)) & DMA_COMMON_INTB1_INTB9_MASK)

#define DMA_COMMON_INTB1_INTB10_MASK             (0x400U)
#define DMA_COMMON_INTB1_INTB10_SHIFT            (10U)
/*! INTB10 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB1_INTB10(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB10_SHIFT)) & DMA_COMMON_INTB1_INTB10_MASK)

#define DMA_COMMON_INTB1_INTB11_MASK             (0x800U)
#define DMA_COMMON_INTB1_INTB11_SHIFT            (11U)
/*! INTB11 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB1_INTB11(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB11_SHIFT)) & DMA_COMMON_INTB1_INTB11_MASK)

#define DMA_COMMON_INTB1_INTB12_MASK             (0x1000U)
#define DMA_COMMON_INTB1_INTB12_SHIFT            (12U)
/*! INTB12 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB1_INTB12(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB12_SHIFT)) & DMA_COMMON_INTB1_INTB12_MASK)

#define DMA_COMMON_INTB1_INTB13_MASK             (0x2000U)
#define DMA_COMMON_INTB1_INTB13_SHIFT            (13U)
/*! INTB13 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB1_INTB13(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB13_SHIFT)) & DMA_COMMON_INTB1_INTB13_MASK)

#define DMA_COMMON_INTB1_INTB14_MASK             (0x4000U)
#define DMA_COMMON_INTB1_INTB14_SHIFT            (14U)
/*! INTB14 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB1_INTB14(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB14_SHIFT)) & DMA_COMMON_INTB1_INTB14_MASK)

#define DMA_COMMON_INTB1_INTB15_MASK             (0x8000U)
#define DMA_COMMON_INTB1_INTB15_SHIFT            (15U)
/*! INTB15 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB1_INTB15(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB15_SHIFT)) & DMA_COMMON_INTB1_INTB15_MASK)

#define DMA_COMMON_INTB1_INTB16_MASK             (0x10000U)
#define DMA_COMMON_INTB1_INTB16_SHIFT            (16U)
/*! INTB16 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB1_INTB16(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB16_SHIFT)) & DMA_COMMON_INTB1_INTB16_MASK)

#define DMA_COMMON_INTB1_INTB17_MASK             (0x20000U)
#define DMA_COMMON_INTB1_INTB17_SHIFT            (17U)
/*! INTB17 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB1_INTB17(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB17_SHIFT)) & DMA_COMMON_INTB1_INTB17_MASK)

#define DMA_COMMON_INTB1_INTB18_MASK             (0x40000U)
#define DMA_COMMON_INTB1_INTB18_SHIFT            (18U)
/*! INTB18 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB1_INTB18(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB18_SHIFT)) & DMA_COMMON_INTB1_INTB18_MASK)

#define DMA_COMMON_INTB1_INTB19_MASK             (0x80000U)
#define DMA_COMMON_INTB1_INTB19_SHIFT            (19U)
/*! INTB19 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB1_INTB19(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB19_SHIFT)) & DMA_COMMON_INTB1_INTB19_MASK)
/*! @} */

/* The count of DMA_COMMON_INTB1 */
#define DMA_COMMON_INTB1_COUNT                   (1U)

/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels */
/*! @{ */

#define DMA_COMMON_SETVALID_SETVALID0_MASK       (0x1U)
#define DMA_COMMON_SETVALID_SETVALID0_SHIFT      (0U)
/*! SETVALID0 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID0(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID0_SHIFT)) & DMA_COMMON_SETVALID_SETVALID0_MASK)

#define DMA_COMMON_SETVALID_SETVALID1_MASK       (0x2U)
#define DMA_COMMON_SETVALID_SETVALID1_SHIFT      (1U)
/*! SETVALID1 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID1(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID1_SHIFT)) & DMA_COMMON_SETVALID_SETVALID1_MASK)

#define DMA_COMMON_SETVALID_SETVALID2_MASK       (0x4U)
#define DMA_COMMON_SETVALID_SETVALID2_SHIFT      (2U)
/*! SETVALID2 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID2(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID2_SHIFT)) & DMA_COMMON_SETVALID_SETVALID2_MASK)

#define DMA_COMMON_SETVALID_SETVALID3_MASK       (0x8U)
#define DMA_COMMON_SETVALID_SETVALID3_SHIFT      (3U)
/*! SETVALID3 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID3(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID3_SHIFT)) & DMA_COMMON_SETVALID_SETVALID3_MASK)

#define DMA_COMMON_SETVALID_SETVALID4_MASK       (0x10U)
#define DMA_COMMON_SETVALID_SETVALID4_SHIFT      (4U)
/*! SETVALID4 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID4(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID4_SHIFT)) & DMA_COMMON_SETVALID_SETVALID4_MASK)

#define DMA_COMMON_SETVALID_SETVALID5_MASK       (0x20U)
#define DMA_COMMON_SETVALID_SETVALID5_SHIFT      (5U)
/*! SETVALID5 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID5(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID5_SHIFT)) & DMA_COMMON_SETVALID_SETVALID5_MASK)

#define DMA_COMMON_SETVALID_SETVALID6_MASK       (0x40U)
#define DMA_COMMON_SETVALID_SETVALID6_SHIFT      (6U)
/*! SETVALID6 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID6(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID6_SHIFT)) & DMA_COMMON_SETVALID_SETVALID6_MASK)

#define DMA_COMMON_SETVALID_SETVALID7_MASK       (0x80U)
#define DMA_COMMON_SETVALID_SETVALID7_SHIFT      (7U)
/*! SETVALID7 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID7(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID7_SHIFT)) & DMA_COMMON_SETVALID_SETVALID7_MASK)

#define DMA_COMMON_SETVALID_SETVALID8_MASK       (0x100U)
#define DMA_COMMON_SETVALID_SETVALID8_SHIFT      (8U)
/*! SETVALID8 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID8(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID8_SHIFT)) & DMA_COMMON_SETVALID_SETVALID8_MASK)

#define DMA_COMMON_SETVALID_SETVALID9_MASK       (0x200U)
#define DMA_COMMON_SETVALID_SETVALID9_SHIFT      (9U)
/*! SETVALID9 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID9(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID9_SHIFT)) & DMA_COMMON_SETVALID_SETVALID9_MASK)

#define DMA_COMMON_SETVALID_SETVALID10_MASK      (0x400U)
#define DMA_COMMON_SETVALID_SETVALID10_SHIFT     (10U)
/*! SETVALID10 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID10(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID10_SHIFT)) & DMA_COMMON_SETVALID_SETVALID10_MASK)

#define DMA_COMMON_SETVALID_SETVALID11_MASK      (0x800U)
#define DMA_COMMON_SETVALID_SETVALID11_SHIFT     (11U)
/*! SETVALID11 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID11(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID11_SHIFT)) & DMA_COMMON_SETVALID_SETVALID11_MASK)

#define DMA_COMMON_SETVALID_SETVALID12_MASK      (0x1000U)
#define DMA_COMMON_SETVALID_SETVALID12_SHIFT     (12U)
/*! SETVALID12 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID12(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID12_SHIFT)) & DMA_COMMON_SETVALID_SETVALID12_MASK)

#define DMA_COMMON_SETVALID_SETVALID13_MASK      (0x2000U)
#define DMA_COMMON_SETVALID_SETVALID13_SHIFT     (13U)
/*! SETVALID13 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID13(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID13_SHIFT)) & DMA_COMMON_SETVALID_SETVALID13_MASK)

#define DMA_COMMON_SETVALID_SETVALID14_MASK      (0x4000U)
#define DMA_COMMON_SETVALID_SETVALID14_SHIFT     (14U)
/*! SETVALID14 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID14(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID14_SHIFT)) & DMA_COMMON_SETVALID_SETVALID14_MASK)

#define DMA_COMMON_SETVALID_SETVALID15_MASK      (0x8000U)
#define DMA_COMMON_SETVALID_SETVALID15_SHIFT     (15U)
/*! SETVALID15 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID15(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID15_SHIFT)) & DMA_COMMON_SETVALID_SETVALID15_MASK)

#define DMA_COMMON_SETVALID_SETVALID16_MASK      (0x10000U)
#define DMA_COMMON_SETVALID_SETVALID16_SHIFT     (16U)
/*! SETVALID16 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID16(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID16_SHIFT)) & DMA_COMMON_SETVALID_SETVALID16_MASK)

#define DMA_COMMON_SETVALID_SETVALID17_MASK      (0x20000U)
#define DMA_COMMON_SETVALID_SETVALID17_SHIFT     (17U)
/*! SETVALID17 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID17(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID17_SHIFT)) & DMA_COMMON_SETVALID_SETVALID17_MASK)

#define DMA_COMMON_SETVALID_SETVALID18_MASK      (0x40000U)
#define DMA_COMMON_SETVALID_SETVALID18_SHIFT     (18U)
/*! SETVALID18 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID18(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID18_SHIFT)) & DMA_COMMON_SETVALID_SETVALID18_MASK)

#define DMA_COMMON_SETVALID_SETVALID19_MASK      (0x80000U)
#define DMA_COMMON_SETVALID_SETVALID19_SHIFT     (19U)
/*! SETVALID19 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID19(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID19_SHIFT)) & DMA_COMMON_SETVALID_SETVALID19_MASK)

#define DMA_COMMON_SETVALID_SETVALID20_MASK      (0x100000U)
#define DMA_COMMON_SETVALID_SETVALID20_SHIFT     (20U)
/*! SETVALID20 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID20(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID20_SHIFT)) & DMA_COMMON_SETVALID_SETVALID20_MASK)

#define DMA_COMMON_SETVALID_SETVALID21_MASK      (0x200000U)
#define DMA_COMMON_SETVALID_SETVALID21_SHIFT     (21U)
/*! SETVALID21 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID21(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID21_SHIFT)) & DMA_COMMON_SETVALID_SETVALID21_MASK)

#define DMA_COMMON_SETVALID_SETVALID22_MASK      (0x400000U)
#define DMA_COMMON_SETVALID_SETVALID22_SHIFT     (22U)
/*! SETVALID22 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID22(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID22_SHIFT)) & DMA_COMMON_SETVALID_SETVALID22_MASK)

#define DMA_COMMON_SETVALID_SETVALID23_MASK      (0x800000U)
#define DMA_COMMON_SETVALID_SETVALID23_SHIFT     (23U)
/*! SETVALID23 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID23(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID23_SHIFT)) & DMA_COMMON_SETVALID_SETVALID23_MASK)

#define DMA_COMMON_SETVALID_SETVALID24_MASK      (0x1000000U)
#define DMA_COMMON_SETVALID_SETVALID24_SHIFT     (24U)
/*! SETVALID24 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID24(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID24_SHIFT)) & DMA_COMMON_SETVALID_SETVALID24_MASK)

#define DMA_COMMON_SETVALID_SETVALID25_MASK      (0x2000000U)
#define DMA_COMMON_SETVALID_SETVALID25_SHIFT     (25U)
/*! SETVALID25 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID25(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID25_SHIFT)) & DMA_COMMON_SETVALID_SETVALID25_MASK)

#define DMA_COMMON_SETVALID_SETVALID26_MASK      (0x4000000U)
#define DMA_COMMON_SETVALID_SETVALID26_SHIFT     (26U)
/*! SETVALID26 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID26(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID26_SHIFT)) & DMA_COMMON_SETVALID_SETVALID26_MASK)

#define DMA_COMMON_SETVALID_SETVALID27_MASK      (0x8000000U)
#define DMA_COMMON_SETVALID_SETVALID27_SHIFT     (27U)
/*! SETVALID27 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID27(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID27_SHIFT)) & DMA_COMMON_SETVALID_SETVALID27_MASK)

#define DMA_COMMON_SETVALID_SETVALID28_MASK      (0x10000000U)
#define DMA_COMMON_SETVALID_SETVALID28_SHIFT     (28U)
/*! SETVALID28 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID28(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID28_SHIFT)) & DMA_COMMON_SETVALID_SETVALID28_MASK)

#define DMA_COMMON_SETVALID_SETVALID29_MASK      (0x20000000U)
#define DMA_COMMON_SETVALID_SETVALID29_SHIFT     (29U)
/*! SETVALID29 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID29(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID29_SHIFT)) & DMA_COMMON_SETVALID_SETVALID29_MASK)

#define DMA_COMMON_SETVALID_SETVALID30_MASK      (0x40000000U)
#define DMA_COMMON_SETVALID_SETVALID30_SHIFT     (30U)
/*! SETVALID30 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID30(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID30_SHIFT)) & DMA_COMMON_SETVALID_SETVALID30_MASK)

#define DMA_COMMON_SETVALID_SETVALID31_MASK      (0x80000000U)
#define DMA_COMMON_SETVALID_SETVALID31_SHIFT     (31U)
/*! SETVALID31 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID31(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID31_SHIFT)) & DMA_COMMON_SETVALID_SETVALID31_MASK)
/*! @} */

/* The count of DMA_COMMON_SETVALID */
#define DMA_COMMON_SETVALID_COUNT                (1U)

/*! @name COMMON_SETVALID1 - Set ValidPending control bits for all DMA channels */
/*! @{ */

#define DMA_COMMON_SETVALID1_SETVALID32_MASK     (0x1U)
#define DMA_COMMON_SETVALID1_SETVALID32_SHIFT    (0U)
/*! SETVALID32 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID1_SETVALID32(x)       (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID32_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID32_MASK)

#define DMA_COMMON_SETVALID1_SETVALID33_MASK     (0x2U)
#define DMA_COMMON_SETVALID1_SETVALID33_SHIFT    (1U)
/*! SETVALID33 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID1_SETVALID33(x)       (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID33_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID33_MASK)

#define DMA_COMMON_SETVALID1_SETVALID34_MASK     (0x4U)
#define DMA_COMMON_SETVALID1_SETVALID34_SHIFT    (2U)
/*! SETVALID34 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID1_SETVALID34(x)       (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID34_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID34_MASK)

#define DMA_COMMON_SETVALID1_SETVALID35_MASK     (0x8U)
#define DMA_COMMON_SETVALID1_SETVALID35_SHIFT    (3U)
/*! SETVALID35 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID1_SETVALID35(x)       (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID35_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID35_MASK)

#define DMA_COMMON_SETVALID1_SETVALID36_MASK     (0x10U)
#define DMA_COMMON_SETVALID1_SETVALID36_SHIFT    (4U)
/*! SETVALID36 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID1_SETVALID36(x)       (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID36_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID36_MASK)

#define DMA_COMMON_SETVALID1_SETVALID37_MASK     (0x20U)
#define DMA_COMMON_SETVALID1_SETVALID37_SHIFT    (5U)
/*! SETVALID37 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID1_SETVALID37(x)       (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID37_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID37_MASK)

#define DMA_COMMON_SETVALID1_SETVALID38_MASK     (0x40U)
#define DMA_COMMON_SETVALID1_SETVALID38_SHIFT    (6U)
/*! SETVALID38 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID1_SETVALID38(x)       (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID38_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID38_MASK)

#define DMA_COMMON_SETVALID1_SETVALID39_MASK     (0x80U)
#define DMA_COMMON_SETVALID1_SETVALID39_SHIFT    (7U)
/*! SETVALID39 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID1_SETVALID39(x)       (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID39_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID39_MASK)

#define DMA_COMMON_SETVALID1_SETVALID40_MASK     (0x100U)
#define DMA_COMMON_SETVALID1_SETVALID40_SHIFT    (8U)
/*! SETVALID40 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID1_SETVALID40(x)       (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID40_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID40_MASK)

#define DMA_COMMON_SETVALID1_SETVALID41_MASK     (0x200U)
#define DMA_COMMON_SETVALID1_SETVALID41_SHIFT    (9U)
/*! SETVALID41 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID1_SETVALID41(x)       (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID41_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID41_MASK)

#define DMA_COMMON_SETVALID1_SETVALID42_MASK     (0x400U)
#define DMA_COMMON_SETVALID1_SETVALID42_SHIFT    (10U)
/*! SETVALID42 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID1_SETVALID42(x)       (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID42_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID42_MASK)

#define DMA_COMMON_SETVALID1_SETVALID43_MASK     (0x800U)
#define DMA_COMMON_SETVALID1_SETVALID43_SHIFT    (11U)
/*! SETVALID43 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID1_SETVALID43(x)       (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID43_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID43_MASK)

#define DMA_COMMON_SETVALID1_SETVALID44_MASK     (0x1000U)
#define DMA_COMMON_SETVALID1_SETVALID44_SHIFT    (12U)
/*! SETVALID44 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID1_SETVALID44(x)       (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID44_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID44_MASK)

#define DMA_COMMON_SETVALID1_SETVALID45_MASK     (0x2000U)
#define DMA_COMMON_SETVALID1_SETVALID45_SHIFT    (13U)
/*! SETVALID45 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID1_SETVALID45(x)       (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID45_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID45_MASK)

#define DMA_COMMON_SETVALID1_SETVALID46_MASK     (0x4000U)
#define DMA_COMMON_SETVALID1_SETVALID46_SHIFT    (14U)
/*! SETVALID46 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID1_SETVALID46(x)       (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID46_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID46_MASK)

#define DMA_COMMON_SETVALID1_SETVALID47_MASK     (0x8000U)
#define DMA_COMMON_SETVALID1_SETVALID47_SHIFT    (15U)
/*! SETVALID47 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID1_SETVALID47(x)       (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID47_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID47_MASK)

#define DMA_COMMON_SETVALID1_SETVALID48_MASK     (0x10000U)
#define DMA_COMMON_SETVALID1_SETVALID48_SHIFT    (16U)
/*! SETVALID48 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID1_SETVALID48(x)       (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID48_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID48_MASK)

#define DMA_COMMON_SETVALID1_SETVALID49_MASK     (0x20000U)
#define DMA_COMMON_SETVALID1_SETVALID49_SHIFT    (17U)
/*! SETVALID49 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID1_SETVALID49(x)       (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID49_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID49_MASK)

#define DMA_COMMON_SETVALID1_SETVALID50_MASK     (0x40000U)
#define DMA_COMMON_SETVALID1_SETVALID50_SHIFT    (18U)
/*! SETVALID50 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID1_SETVALID50(x)       (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID50_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID50_MASK)

#define DMA_COMMON_SETVALID1_SETVALID51_MASK     (0x80000U)
#define DMA_COMMON_SETVALID1_SETVALID51_SHIFT    (19U)
/*! SETVALID51 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID1_SETVALID51(x)       (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID51_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID51_MASK)
/*! @} */

/* The count of DMA_COMMON_SETVALID1 */
#define DMA_COMMON_SETVALID1_COUNT               (1U)

/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels */
/*! @{ */

#define DMA_COMMON_SETTRIG_SETTRIG0_MASK         (0x1U)
#define DMA_COMMON_SETTRIG_SETTRIG0_SHIFT        (0U)
/*! SETTRIG0 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG0(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG0_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG0_MASK)

#define DMA_COMMON_SETTRIG_SETTRIG1_MASK         (0x2U)
#define DMA_COMMON_SETTRIG_SETTRIG1_SHIFT        (1U)
/*! SETTRIG1 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG1(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG1_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG1_MASK)

#define DMA_COMMON_SETTRIG_SETTRIG2_MASK         (0x4U)
#define DMA_COMMON_SETTRIG_SETTRIG2_SHIFT        (2U)
/*! SETTRIG2 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG2(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG2_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG2_MASK)

#define DMA_COMMON_SETTRIG_SETTRIG3_MASK         (0x8U)
#define DMA_COMMON_SETTRIG_SETTRIG3_SHIFT        (3U)
/*! SETTRIG3 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG3(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG3_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG3_MASK)

#define DMA_COMMON_SETTRIG_SETTRIG4_MASK         (0x10U)
#define DMA_COMMON_SETTRIG_SETTRIG4_SHIFT        (4U)
/*! SETTRIG4 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG4(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG4_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG4_MASK)

#define DMA_COMMON_SETTRIG_SETTRIG5_MASK         (0x20U)
#define DMA_COMMON_SETTRIG_SETTRIG5_SHIFT        (5U)
/*! SETTRIG5 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG5(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG5_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG5_MASK)

#define DMA_COMMON_SETTRIG_SETTRIG6_MASK         (0x40U)
#define DMA_COMMON_SETTRIG_SETTRIG6_SHIFT        (6U)
/*! SETTRIG6 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG6(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG6_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG6_MASK)

#define DMA_COMMON_SETTRIG_SETTRIG7_MASK         (0x80U)
#define DMA_COMMON_SETTRIG_SETTRIG7_SHIFT        (7U)
/*! SETTRIG7 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG7(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG7_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG7_MASK)

#define DMA_COMMON_SETTRIG_SETTRIG8_MASK         (0x100U)
#define DMA_COMMON_SETTRIG_SETTRIG8_SHIFT        (8U)
/*! SETTRIG8 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG8(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG8_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG8_MASK)

#define DMA_COMMON_SETTRIG_SETTRIG9_MASK         (0x200U)
#define DMA_COMMON_SETTRIG_SETTRIG9_SHIFT        (9U)
/*! SETTRIG9 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG9(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG9_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG9_MASK)

#define DMA_COMMON_SETTRIG_SETTRIG10_MASK        (0x400U)
#define DMA_COMMON_SETTRIG_SETTRIG10_SHIFT       (10U)
/*! SETTRIG10 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG10(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG10_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG10_MASK)

#define DMA_COMMON_SETTRIG_SETTRIG11_MASK        (0x800U)
#define DMA_COMMON_SETTRIG_SETTRIG11_SHIFT       (11U)
/*! SETTRIG11 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG11(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG11_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG11_MASK)

#define DMA_COMMON_SETTRIG_SETTRIG12_MASK        (0x1000U)
#define DMA_COMMON_SETTRIG_SETTRIG12_SHIFT       (12U)
/*! SETTRIG12 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG12(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG12_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG12_MASK)

#define DMA_COMMON_SETTRIG_SETTRIG13_MASK        (0x2000U)
#define DMA_COMMON_SETTRIG_SETTRIG13_SHIFT       (13U)
/*! SETTRIG13 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG13(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG13_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG13_MASK)

#define DMA_COMMON_SETTRIG_SETTRIG14_MASK        (0x4000U)
#define DMA_COMMON_SETTRIG_SETTRIG14_SHIFT       (14U)
/*! SETTRIG14 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG14(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG14_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG14_MASK)

#define DMA_COMMON_SETTRIG_SETTRIG15_MASK        (0x8000U)
#define DMA_COMMON_SETTRIG_SETTRIG15_SHIFT       (15U)
/*! SETTRIG15 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG15(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG15_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG15_MASK)

#define DMA_COMMON_SETTRIG_SETTRIG16_MASK        (0x10000U)
#define DMA_COMMON_SETTRIG_SETTRIG16_SHIFT       (16U)
/*! SETTRIG16 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG16(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG16_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG16_MASK)

#define DMA_COMMON_SETTRIG_SETTRIG17_MASK        (0x20000U)
#define DMA_COMMON_SETTRIG_SETTRIG17_SHIFT       (17U)
/*! SETTRIG17 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG17(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG17_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG17_MASK)

#define DMA_COMMON_SETTRIG_SETTRIG18_MASK        (0x40000U)
#define DMA_COMMON_SETTRIG_SETTRIG18_SHIFT       (18U)
/*! SETTRIG18 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG18(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG18_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG18_MASK)

#define DMA_COMMON_SETTRIG_SETTRIG19_MASK        (0x80000U)
#define DMA_COMMON_SETTRIG_SETTRIG19_SHIFT       (19U)
/*! SETTRIG19 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG19(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG19_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG19_MASK)

#define DMA_COMMON_SETTRIG_SETTRIG20_MASK        (0x100000U)
#define DMA_COMMON_SETTRIG_SETTRIG20_SHIFT       (20U)
/*! SETTRIG20 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG20(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG20_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG20_MASK)

#define DMA_COMMON_SETTRIG_SETTRIG21_MASK        (0x200000U)
#define DMA_COMMON_SETTRIG_SETTRIG21_SHIFT       (21U)
/*! SETTRIG21 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG21(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG21_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG21_MASK)

#define DMA_COMMON_SETTRIG_SETTRIG22_MASK        (0x400000U)
#define DMA_COMMON_SETTRIG_SETTRIG22_SHIFT       (22U)
/*! SETTRIG22 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG22(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG22_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG22_MASK)

#define DMA_COMMON_SETTRIG_SETTRIG23_MASK        (0x800000U)
#define DMA_COMMON_SETTRIG_SETTRIG23_SHIFT       (23U)
/*! SETTRIG23 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG23(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG23_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG23_MASK)

#define DMA_COMMON_SETTRIG_SETTRIG24_MASK        (0x1000000U)
#define DMA_COMMON_SETTRIG_SETTRIG24_SHIFT       (24U)
/*! SETTRIG24 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG24(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG24_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG24_MASK)

#define DMA_COMMON_SETTRIG_SETTRIG25_MASK        (0x2000000U)
#define DMA_COMMON_SETTRIG_SETTRIG25_SHIFT       (25U)
/*! SETTRIG25 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG25(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG25_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG25_MASK)

#define DMA_COMMON_SETTRIG_SETTRIG26_MASK        (0x4000000U)
#define DMA_COMMON_SETTRIG_SETTRIG26_SHIFT       (26U)
/*! SETTRIG26 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG26(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG26_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG26_MASK)

#define DMA_COMMON_SETTRIG_SETTRIG27_MASK        (0x8000000U)
#define DMA_COMMON_SETTRIG_SETTRIG27_SHIFT       (27U)
/*! SETTRIG27 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG27(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG27_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG27_MASK)

#define DMA_COMMON_SETTRIG_SETTRIG28_MASK        (0x10000000U)
#define DMA_COMMON_SETTRIG_SETTRIG28_SHIFT       (28U)
/*! SETTRIG28 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG28(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG28_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG28_MASK)

#define DMA_COMMON_SETTRIG_SETTRIG29_MASK        (0x20000000U)
#define DMA_COMMON_SETTRIG_SETTRIG29_SHIFT       (29U)
/*! SETTRIG29 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG29(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG29_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG29_MASK)

#define DMA_COMMON_SETTRIG_SETTRIG30_MASK        (0x40000000U)
#define DMA_COMMON_SETTRIG_SETTRIG30_SHIFT       (30U)
/*! SETTRIG30 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG30(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG30_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG30_MASK)

#define DMA_COMMON_SETTRIG_SETTRIG31_MASK        (0x80000000U)
#define DMA_COMMON_SETTRIG_SETTRIG31_SHIFT       (31U)
/*! SETTRIG31 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG31(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG31_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG31_MASK)
/*! @} */

/* The count of DMA_COMMON_SETTRIG */
#define DMA_COMMON_SETTRIG_COUNT                 (1U)

/*! @name COMMON_SETTRIG1 - Set Trigger control bits for all DMA channels */
/*! @{ */

#define DMA_COMMON_SETTRIG1_SETTRIG32_MASK       (0x1U)
#define DMA_COMMON_SETTRIG1_SETTRIG32_SHIFT      (0U)
/*! SETTRIG32 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG1_SETTRIG32(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG32_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG32_MASK)

#define DMA_COMMON_SETTRIG1_SETTRIG33_MASK       (0x2U)
#define DMA_COMMON_SETTRIG1_SETTRIG33_SHIFT      (1U)
/*! SETTRIG33 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG1_SETTRIG33(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG33_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG33_MASK)

#define DMA_COMMON_SETTRIG1_SETTRIG34_MASK       (0x4U)
#define DMA_COMMON_SETTRIG1_SETTRIG34_SHIFT      (2U)
/*! SETTRIG34 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG1_SETTRIG34(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG34_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG34_MASK)

#define DMA_COMMON_SETTRIG1_SETTRIG35_MASK       (0x8U)
#define DMA_COMMON_SETTRIG1_SETTRIG35_SHIFT      (3U)
/*! SETTRIG35 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG1_SETTRIG35(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG35_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG35_MASK)

#define DMA_COMMON_SETTRIG1_SETTRIG36_MASK       (0x10U)
#define DMA_COMMON_SETTRIG1_SETTRIG36_SHIFT      (4U)
/*! SETTRIG36 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG1_SETTRIG36(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG36_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG36_MASK)

#define DMA_COMMON_SETTRIG1_SETTRIG37_MASK       (0x20U)
#define DMA_COMMON_SETTRIG1_SETTRIG37_SHIFT      (5U)
/*! SETTRIG37 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG1_SETTRIG37(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG37_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG37_MASK)

#define DMA_COMMON_SETTRIG1_SETTRIG38_MASK       (0x40U)
#define DMA_COMMON_SETTRIG1_SETTRIG38_SHIFT      (6U)
/*! SETTRIG38 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG1_SETTRIG38(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG38_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG38_MASK)

#define DMA_COMMON_SETTRIG1_SETTRIG39_MASK       (0x80U)
#define DMA_COMMON_SETTRIG1_SETTRIG39_SHIFT      (7U)
/*! SETTRIG39 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG1_SETTRIG39(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG39_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG39_MASK)

#define DMA_COMMON_SETTRIG1_SETTRIG40_MASK       (0x100U)
#define DMA_COMMON_SETTRIG1_SETTRIG40_SHIFT      (8U)
/*! SETTRIG40 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG1_SETTRIG40(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG40_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG40_MASK)

#define DMA_COMMON_SETTRIG1_SETTRIG41_MASK       (0x200U)
#define DMA_COMMON_SETTRIG1_SETTRIG41_SHIFT      (9U)
/*! SETTRIG41 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG1_SETTRIG41(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG41_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG41_MASK)

#define DMA_COMMON_SETTRIG1_SETTRIG42_MASK       (0x400U)
#define DMA_COMMON_SETTRIG1_SETTRIG42_SHIFT      (10U)
/*! SETTRIG42 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG1_SETTRIG42(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG42_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG42_MASK)

#define DMA_COMMON_SETTRIG1_SETTRIG43_MASK       (0x800U)
#define DMA_COMMON_SETTRIG1_SETTRIG43_SHIFT      (11U)
/*! SETTRIG43 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG1_SETTRIG43(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG43_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG43_MASK)

#define DMA_COMMON_SETTRIG1_SETTRIG44_MASK       (0x1000U)
#define DMA_COMMON_SETTRIG1_SETTRIG44_SHIFT      (12U)
/*! SETTRIG44 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG1_SETTRIG44(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG44_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG44_MASK)

#define DMA_COMMON_SETTRIG1_SETTRIG45_MASK       (0x2000U)
#define DMA_COMMON_SETTRIG1_SETTRIG45_SHIFT      (13U)
/*! SETTRIG45 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG1_SETTRIG45(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG45_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG45_MASK)

#define DMA_COMMON_SETTRIG1_SETTRIG46_MASK       (0x4000U)
#define DMA_COMMON_SETTRIG1_SETTRIG46_SHIFT      (14U)
/*! SETTRIG46 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG1_SETTRIG46(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG46_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG46_MASK)

#define DMA_COMMON_SETTRIG1_SETTRIG47_MASK       (0x8000U)
#define DMA_COMMON_SETTRIG1_SETTRIG47_SHIFT      (15U)
/*! SETTRIG47 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG1_SETTRIG47(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG47_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG47_MASK)

#define DMA_COMMON_SETTRIG1_SETTRIG48_MASK       (0x10000U)
#define DMA_COMMON_SETTRIG1_SETTRIG48_SHIFT      (16U)
/*! SETTRIG48 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG1_SETTRIG48(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG48_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG48_MASK)

#define DMA_COMMON_SETTRIG1_SETTRIG49_MASK       (0x20000U)
#define DMA_COMMON_SETTRIG1_SETTRIG49_SHIFT      (17U)
/*! SETTRIG49 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG1_SETTRIG49(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG49_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG49_MASK)

#define DMA_COMMON_SETTRIG1_SETTRIG50_MASK       (0x40000U)
#define DMA_COMMON_SETTRIG1_SETTRIG50_SHIFT      (18U)
/*! SETTRIG50 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG1_SETTRIG50(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG50_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG50_MASK)

#define DMA_COMMON_SETTRIG1_SETTRIG51_MASK       (0x80000U)
#define DMA_COMMON_SETTRIG1_SETTRIG51_SHIFT      (19U)
/*! SETTRIG51 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG1_SETTRIG51(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG51_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG51_MASK)
/*! @} */

/* The count of DMA_COMMON_SETTRIG1 */
#define DMA_COMMON_SETTRIG1_COUNT                (1U)

/*! @name COMMON_ABORT - Channel Abort control for all DMA channels */
/*! @{ */

#define DMA_COMMON_ABORT_ABORT0_MASK             (0x1U)
#define DMA_COMMON_ABORT_ABORT0_SHIFT            (0U)
/*! ABORT0 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT0(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT0_SHIFT)) & DMA_COMMON_ABORT_ABORT0_MASK)

#define DMA_COMMON_ABORT_ABORT1_MASK             (0x2U)
#define DMA_COMMON_ABORT_ABORT1_SHIFT            (1U)
/*! ABORT1 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT1(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT1_SHIFT)) & DMA_COMMON_ABORT_ABORT1_MASK)

#define DMA_COMMON_ABORT_ABORT2_MASK             (0x4U)
#define DMA_COMMON_ABORT_ABORT2_SHIFT            (2U)
/*! ABORT2 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT2(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT2_SHIFT)) & DMA_COMMON_ABORT_ABORT2_MASK)

#define DMA_COMMON_ABORT_ABORT3_MASK             (0x8U)
#define DMA_COMMON_ABORT_ABORT3_SHIFT            (3U)
/*! ABORT3 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT3(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT3_SHIFT)) & DMA_COMMON_ABORT_ABORT3_MASK)

#define DMA_COMMON_ABORT_ABORT4_MASK             (0x10U)
#define DMA_COMMON_ABORT_ABORT4_SHIFT            (4U)
/*! ABORT4 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT4(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT4_SHIFT)) & DMA_COMMON_ABORT_ABORT4_MASK)

#define DMA_COMMON_ABORT_ABORT5_MASK             (0x20U)
#define DMA_COMMON_ABORT_ABORT5_SHIFT            (5U)
/*! ABORT5 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT5(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT5_SHIFT)) & DMA_COMMON_ABORT_ABORT5_MASK)

#define DMA_COMMON_ABORT_ABORT6_MASK             (0x40U)
#define DMA_COMMON_ABORT_ABORT6_SHIFT            (6U)
/*! ABORT6 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT6(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT6_SHIFT)) & DMA_COMMON_ABORT_ABORT6_MASK)

#define DMA_COMMON_ABORT_ABORT7_MASK             (0x80U)
#define DMA_COMMON_ABORT_ABORT7_SHIFT            (7U)
/*! ABORT7 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT7(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT7_SHIFT)) & DMA_COMMON_ABORT_ABORT7_MASK)

#define DMA_COMMON_ABORT_ABORT8_MASK             (0x100U)
#define DMA_COMMON_ABORT_ABORT8_SHIFT            (8U)
/*! ABORT8 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT8(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT8_SHIFT)) & DMA_COMMON_ABORT_ABORT8_MASK)

#define DMA_COMMON_ABORT_ABORT9_MASK             (0x200U)
#define DMA_COMMON_ABORT_ABORT9_SHIFT            (9U)
/*! ABORT9 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT9(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT9_SHIFT)) & DMA_COMMON_ABORT_ABORT9_MASK)

#define DMA_COMMON_ABORT_ABORT10_MASK            (0x400U)
#define DMA_COMMON_ABORT_ABORT10_SHIFT           (10U)
/*! ABORT10 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT10(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT10_SHIFT)) & DMA_COMMON_ABORT_ABORT10_MASK)

#define DMA_COMMON_ABORT_ABORT11_MASK            (0x800U)
#define DMA_COMMON_ABORT_ABORT11_SHIFT           (11U)
/*! ABORT11 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT11(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT11_SHIFT)) & DMA_COMMON_ABORT_ABORT11_MASK)

#define DMA_COMMON_ABORT_ABORT12_MASK            (0x1000U)
#define DMA_COMMON_ABORT_ABORT12_SHIFT           (12U)
/*! ABORT12 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT12(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT12_SHIFT)) & DMA_COMMON_ABORT_ABORT12_MASK)

#define DMA_COMMON_ABORT_ABORT13_MASK            (0x2000U)
#define DMA_COMMON_ABORT_ABORT13_SHIFT           (13U)
/*! ABORT13 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT13(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT13_SHIFT)) & DMA_COMMON_ABORT_ABORT13_MASK)

#define DMA_COMMON_ABORT_ABORT14_MASK            (0x4000U)
#define DMA_COMMON_ABORT_ABORT14_SHIFT           (14U)
/*! ABORT14 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT14(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT14_SHIFT)) & DMA_COMMON_ABORT_ABORT14_MASK)

#define DMA_COMMON_ABORT_ABORT15_MASK            (0x8000U)
#define DMA_COMMON_ABORT_ABORT15_SHIFT           (15U)
/*! ABORT15 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT15(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT15_SHIFT)) & DMA_COMMON_ABORT_ABORT15_MASK)

#define DMA_COMMON_ABORT_ABORT16_MASK            (0x10000U)
#define DMA_COMMON_ABORT_ABORT16_SHIFT           (16U)
/*! ABORT16 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT16(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT16_SHIFT)) & DMA_COMMON_ABORT_ABORT16_MASK)

#define DMA_COMMON_ABORT_ABORT17_MASK            (0x20000U)
#define DMA_COMMON_ABORT_ABORT17_SHIFT           (17U)
/*! ABORT17 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT17(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT17_SHIFT)) & DMA_COMMON_ABORT_ABORT17_MASK)

#define DMA_COMMON_ABORT_ABORT18_MASK            (0x40000U)
#define DMA_COMMON_ABORT_ABORT18_SHIFT           (18U)
/*! ABORT18 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT18(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT18_SHIFT)) & DMA_COMMON_ABORT_ABORT18_MASK)

#define DMA_COMMON_ABORT_ABORT19_MASK            (0x80000U)
#define DMA_COMMON_ABORT_ABORT19_SHIFT           (19U)
/*! ABORT19 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT19(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT19_SHIFT)) & DMA_COMMON_ABORT_ABORT19_MASK)

#define DMA_COMMON_ABORT_ABORT20_MASK            (0x100000U)
#define DMA_COMMON_ABORT_ABORT20_SHIFT           (20U)
/*! ABORT20 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT20(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT20_SHIFT)) & DMA_COMMON_ABORT_ABORT20_MASK)

#define DMA_COMMON_ABORT_ABORT21_MASK            (0x200000U)
#define DMA_COMMON_ABORT_ABORT21_SHIFT           (21U)
/*! ABORT21 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT21(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT21_SHIFT)) & DMA_COMMON_ABORT_ABORT21_MASK)

#define DMA_COMMON_ABORT_ABORT22_MASK            (0x400000U)
#define DMA_COMMON_ABORT_ABORT22_SHIFT           (22U)
/*! ABORT22 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT22(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT22_SHIFT)) & DMA_COMMON_ABORT_ABORT22_MASK)

#define DMA_COMMON_ABORT_ABORT23_MASK            (0x800000U)
#define DMA_COMMON_ABORT_ABORT23_SHIFT           (23U)
/*! ABORT23 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT23(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT23_SHIFT)) & DMA_COMMON_ABORT_ABORT23_MASK)

#define DMA_COMMON_ABORT_ABORT24_MASK            (0x1000000U)
#define DMA_COMMON_ABORT_ABORT24_SHIFT           (24U)
/*! ABORT24 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT24(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT24_SHIFT)) & DMA_COMMON_ABORT_ABORT24_MASK)

#define DMA_COMMON_ABORT_ABORT25_MASK            (0x2000000U)
#define DMA_COMMON_ABORT_ABORT25_SHIFT           (25U)
/*! ABORT25 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT25(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT25_SHIFT)) & DMA_COMMON_ABORT_ABORT25_MASK)

#define DMA_COMMON_ABORT_ABORT26_MASK            (0x4000000U)
#define DMA_COMMON_ABORT_ABORT26_SHIFT           (26U)
/*! ABORT26 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT26(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT26_SHIFT)) & DMA_COMMON_ABORT_ABORT26_MASK)

#define DMA_COMMON_ABORT_ABORT27_MASK            (0x8000000U)
#define DMA_COMMON_ABORT_ABORT27_SHIFT           (27U)
/*! ABORT27 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT27(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT27_SHIFT)) & DMA_COMMON_ABORT_ABORT27_MASK)

#define DMA_COMMON_ABORT_ABORT28_MASK            (0x10000000U)
#define DMA_COMMON_ABORT_ABORT28_SHIFT           (28U)
/*! ABORT28 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT28(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT28_SHIFT)) & DMA_COMMON_ABORT_ABORT28_MASK)

#define DMA_COMMON_ABORT_ABORT29_MASK            (0x20000000U)
#define DMA_COMMON_ABORT_ABORT29_SHIFT           (29U)
/*! ABORT29 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT29(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT29_SHIFT)) & DMA_COMMON_ABORT_ABORT29_MASK)

#define DMA_COMMON_ABORT_ABORT30_MASK            (0x40000000U)
#define DMA_COMMON_ABORT_ABORT30_SHIFT           (30U)
/*! ABORT30 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT30(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT30_SHIFT)) & DMA_COMMON_ABORT_ABORT30_MASK)

#define DMA_COMMON_ABORT_ABORT31_MASK            (0x80000000U)
#define DMA_COMMON_ABORT_ABORT31_SHIFT           (31U)
/*! ABORT31 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT31(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT31_SHIFT)) & DMA_COMMON_ABORT_ABORT31_MASK)
/*! @} */

/* The count of DMA_COMMON_ABORT */
#define DMA_COMMON_ABORT_COUNT                   (1U)

/*! @name COMMON_ABORT1 - Channel Abort control for all DMA channels */
/*! @{ */

#define DMA_COMMON_ABORT1_ABORT32_MASK           (0x1U)
#define DMA_COMMON_ABORT1_ABORT32_SHIFT          (0U)
/*! ABORT32 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT1_ABORT32(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT32_SHIFT)) & DMA_COMMON_ABORT1_ABORT32_MASK)

#define DMA_COMMON_ABORT1_ABORT33_MASK           (0x2U)
#define DMA_COMMON_ABORT1_ABORT33_SHIFT          (1U)
/*! ABORT33 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT1_ABORT33(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT33_SHIFT)) & DMA_COMMON_ABORT1_ABORT33_MASK)

#define DMA_COMMON_ABORT1_ABORT34_MASK           (0x4U)
#define DMA_COMMON_ABORT1_ABORT34_SHIFT          (2U)
/*! ABORT34 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT1_ABORT34(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT34_SHIFT)) & DMA_COMMON_ABORT1_ABORT34_MASK)

#define DMA_COMMON_ABORT1_ABORT35_MASK           (0x8U)
#define DMA_COMMON_ABORT1_ABORT35_SHIFT          (3U)
/*! ABORT35 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT1_ABORT35(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT35_SHIFT)) & DMA_COMMON_ABORT1_ABORT35_MASK)

#define DMA_COMMON_ABORT1_ABORT36_MASK           (0x10U)
#define DMA_COMMON_ABORT1_ABORT36_SHIFT          (4U)
/*! ABORT36 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT1_ABORT36(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT36_SHIFT)) & DMA_COMMON_ABORT1_ABORT36_MASK)

#define DMA_COMMON_ABORT1_ABORT37_MASK           (0x20U)
#define DMA_COMMON_ABORT1_ABORT37_SHIFT          (5U)
/*! ABORT37 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT1_ABORT37(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT37_SHIFT)) & DMA_COMMON_ABORT1_ABORT37_MASK)

#define DMA_COMMON_ABORT1_ABORT38_MASK           (0x40U)
#define DMA_COMMON_ABORT1_ABORT38_SHIFT          (6U)
/*! ABORT38 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT1_ABORT38(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT38_SHIFT)) & DMA_COMMON_ABORT1_ABORT38_MASK)

#define DMA_COMMON_ABORT1_ABORT39_MASK           (0x80U)
#define DMA_COMMON_ABORT1_ABORT39_SHIFT          (7U)
/*! ABORT39 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT1_ABORT39(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT39_SHIFT)) & DMA_COMMON_ABORT1_ABORT39_MASK)

#define DMA_COMMON_ABORT1_ABORT40_MASK           (0x100U)
#define DMA_COMMON_ABORT1_ABORT40_SHIFT          (8U)
/*! ABORT40 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT1_ABORT40(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT40_SHIFT)) & DMA_COMMON_ABORT1_ABORT40_MASK)

#define DMA_COMMON_ABORT1_ABORT41_MASK           (0x200U)
#define DMA_COMMON_ABORT1_ABORT41_SHIFT          (9U)
/*! ABORT41 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT1_ABORT41(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT41_SHIFT)) & DMA_COMMON_ABORT1_ABORT41_MASK)

#define DMA_COMMON_ABORT1_ABORT42_MASK           (0x400U)
#define DMA_COMMON_ABORT1_ABORT42_SHIFT          (10U)
/*! ABORT42 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT1_ABORT42(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT42_SHIFT)) & DMA_COMMON_ABORT1_ABORT42_MASK)

#define DMA_COMMON_ABORT1_ABORT43_MASK           (0x800U)
#define DMA_COMMON_ABORT1_ABORT43_SHIFT          (11U)
/*! ABORT43 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT1_ABORT43(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT43_SHIFT)) & DMA_COMMON_ABORT1_ABORT43_MASK)

#define DMA_COMMON_ABORT1_ABORT44_MASK           (0x1000U)
#define DMA_COMMON_ABORT1_ABORT44_SHIFT          (12U)
/*! ABORT44 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT1_ABORT44(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT44_SHIFT)) & DMA_COMMON_ABORT1_ABORT44_MASK)

#define DMA_COMMON_ABORT1_ABORT45_MASK           (0x2000U)
#define DMA_COMMON_ABORT1_ABORT45_SHIFT          (13U)
/*! ABORT45 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT1_ABORT45(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT45_SHIFT)) & DMA_COMMON_ABORT1_ABORT45_MASK)

#define DMA_COMMON_ABORT1_ABORT46_MASK           (0x4000U)
#define DMA_COMMON_ABORT1_ABORT46_SHIFT          (14U)
/*! ABORT46 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT1_ABORT46(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT46_SHIFT)) & DMA_COMMON_ABORT1_ABORT46_MASK)

#define DMA_COMMON_ABORT1_ABORT47_MASK           (0x8000U)
#define DMA_COMMON_ABORT1_ABORT47_SHIFT          (15U)
/*! ABORT47 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT1_ABORT47(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT47_SHIFT)) & DMA_COMMON_ABORT1_ABORT47_MASK)

#define DMA_COMMON_ABORT1_ABORT48_MASK           (0x10000U)
#define DMA_COMMON_ABORT1_ABORT48_SHIFT          (16U)
/*! ABORT48 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT1_ABORT48(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT48_SHIFT)) & DMA_COMMON_ABORT1_ABORT48_MASK)

#define DMA_COMMON_ABORT1_ABORT49_MASK           (0x20000U)
#define DMA_COMMON_ABORT1_ABORT49_SHIFT          (17U)
/*! ABORT49 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT1_ABORT49(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT49_SHIFT)) & DMA_COMMON_ABORT1_ABORT49_MASK)

#define DMA_COMMON_ABORT1_ABORT50_MASK           (0x40000U)
#define DMA_COMMON_ABORT1_ABORT50_SHIFT          (18U)
/*! ABORT50 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT1_ABORT50(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT50_SHIFT)) & DMA_COMMON_ABORT1_ABORT50_MASK)

#define DMA_COMMON_ABORT1_ABORT51_MASK           (0x80000U)
#define DMA_COMMON_ABORT1_ABORT51_SHIFT          (19U)
/*! ABORT51 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT1_ABORT51(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT51_SHIFT)) & DMA_COMMON_ABORT1_ABORT51_MASK)
/*! @} */

/* The count of DMA_COMMON_ABORT1 */
#define DMA_COMMON_ABORT1_COUNT                  (1U)

/*! @name CHANNEL_CFG - Configuration register for DMA channel */
/*! @{ */

#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK         (0x1U)
#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT        (0U)
/*! PERIPHREQEN - Peripheral request Enable.
 *  0b0..Peripheral DMA requests disabled.
 *  0b1..Peripheral DMA requests enabled.
 */
#define DMA_CHANNEL_CFG_PERIPHREQEN(x)           (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK)

#define DMA_CHANNEL_CFG_HWTRIGEN_MASK            (0x2U)
#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT           (1U)
/*! HWTRIGEN - Hardware Triggering Enable for channel.
 *  0b0..Hardware triggering not used for channel.
 *  0b1..Hardware triggering used for channel.
 */
#define DMA_CHANNEL_CFG_HWTRIGEN(x)              (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK)

#define DMA_CHANNEL_CFG_TRIGPOL_MASK             (0x10U)
#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT            (4U)
/*! TRIGPOL - Trigger Polarity.
 *  0b0..Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
 *  0b1..Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
 */
#define DMA_CHANNEL_CFG_TRIGPOL(x)               (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK)

#define DMA_CHANNEL_CFG_TRIGTYPE_MASK            (0x20U)
#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT           (5U)
/*! TRIGTYPE - Trigger Type.
 *  0b0..Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
 *  0b1..Level.
 */
#define DMA_CHANNEL_CFG_TRIGTYPE(x)              (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK)

#define DMA_CHANNEL_CFG_TRIGBURST_MASK           (0x40U)
#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT          (6U)
/*! TRIGBURST - Trigger Burst.
 *  0b0..Single transfer.
 *  0b1..Burst transfer.
 */
#define DMA_CHANNEL_CFG_TRIGBURST(x)             (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK)

#define DMA_CHANNEL_CFG_BURSTPOWER_MASK          (0xF00U)
#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT         (8U)
/*! BURSTPOWER - Burst Power.
 */
#define DMA_CHANNEL_CFG_BURSTPOWER(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK)

#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK        (0x4000U)
#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT       (14U)
/*! SRCBURSTWRAP - Source Burst Wrap.
 *  0b0..Disabled.
 *  0b1..Enabled.
 */
#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x)          (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK)

#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK        (0x8000U)
#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT       (15U)
/*! DSTBURSTWRAP - Destination Burst Wrap.
 *  0b0..Disabled. Destination burst wrapping is not enabled for this DMA channel.
 *  0b1..Enabled. Destination burst wrapping is enabled for this DMA channel.
 */
#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x)          (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK)

#define DMA_CHANNEL_CFG_CHPRIORITY_MASK          (0x70000U)
#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT         (16U)
/*! CHPRIORITY - Priority of channel when multiple DMA requests are pending.
 */
#define DMA_CHANNEL_CFG_CHPRIORITY(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK)
/*! @} */

/* The count of DMA_CHANNEL_CFG */
#define DMA_CHANNEL_CFG_COUNT                    (52U)

/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel */
/*! @{ */

#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK    (0x1U)
#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT   (0U)
/*! VALIDPENDING - Valid pending flag for this channel.
 *  0b0..No effect on DMA operation.
 *  0b1..Valid pending.
 */
#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x)      (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK)

#define DMA_CHANNEL_CTLSTAT_TRIG_MASK            (0x4U)
#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT           (2U)
/*! TRIG - Trigger flag.
 *  0b0..Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
 *  0b1..Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
 */
#define DMA_CHANNEL_CTLSTAT_TRIG(x)              (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK)
/*! @} */

/* The count of DMA_CHANNEL_CTLSTAT */
#define DMA_CHANNEL_CTLSTAT_COUNT                (52U)

/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel */
/*! @{ */

#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK        (0x1U)
#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT       (0U)
/*! CFGVALID - Configuration Valid flag.
 *  0b0..Not valid.
 *  0b1..Valid.
 */
#define DMA_CHANNEL_XFERCFG_CFGVALID(x)          (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK)

#define DMA_CHANNEL_XFERCFG_RELOAD_MASK          (0x2U)
#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT         (1U)
/*! RELOAD - Reload.
 *  0b0..Disabled. The channels' control structure should not be reloaded when the current descriptor is exhausted.
 *  0b1..Enabled. The channels' control structure should be reloaded when the current descriptor is exhausted.
 */
#define DMA_CHANNEL_XFERCFG_RELOAD(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK)

#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK          (0x4U)
#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT         (2U)
/*! SWTRIG - Software Trigger.
 *  0b0..Not set.
 *  0b1..Set.
 */
#define DMA_CHANNEL_XFERCFG_SWTRIG(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK)

#define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK         (0x8U)
#define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT        (3U)
/*! CLRTRIG - Clear Trigger.
 *  0b0..Not cleared.
 *  0b1..Cleared.
 */
#define DMA_CHANNEL_XFERCFG_CLRTRIG(x)           (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK)

#define DMA_CHANNEL_XFERCFG_SETINTA_MASK         (0x10U)
#define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT        (4U)
/*! SETINTA - Set Interrupt flag A for channel.
 *  0b0..No effect.
 *  0b1..Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
 */
#define DMA_CHANNEL_XFERCFG_SETINTA(x)           (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK)

#define DMA_CHANNEL_XFERCFG_SETINTB_MASK         (0x20U)
#define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT        (5U)
/*! SETINTB - Set Interrupt flag B for channel.
 *  0b0..No effect.
 *  0b1..Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
 */
#define DMA_CHANNEL_XFERCFG_SETINTB(x)           (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK)

#define DMA_CHANNEL_XFERCFG_WIDTH_MASK           (0x300U)
#define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT          (8U)
/*! WIDTH - Transfer width used for this DMA channel.
 *  0b00..8-bit.
 *  0b01..16-bit.
 *  0b10..32-bit.
 *  0b11..Reserved.
 */
#define DMA_CHANNEL_XFERCFG_WIDTH(x)             (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK)

#define DMA_CHANNEL_XFERCFG_SRCINC_MASK          (0x3000U)
#define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT         (12U)
/*! SRCINC - Source address increment
 *  0b00..No increment.
 *  0b01..1 x width.
 *  0b10..2 x width.
 *  0b11..4 x width.
 */
#define DMA_CHANNEL_XFERCFG_SRCINC(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK)

#define DMA_CHANNEL_XFERCFG_DSTINC_MASK          (0xC000U)
#define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT         (14U)
/*! DSTINC - Destination address increment
 *  0b00..No increment.
 *  0b01..1 x width.
 *  0b10..2 x width.
 *  0b11..4 x width.
 */
#define DMA_CHANNEL_XFERCFG_DSTINC(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK)

#define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK       (0x3FF0000U)
#define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT      (16U)
/*! XFERCOUNT - Total number of transfers to be performed, minus 1 encoded.
 */
#define DMA_CHANNEL_XFERCFG_XFERCOUNT(x)         (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK)
/*! @} */

/* The count of DMA_CHANNEL_XFERCFG */
#define DMA_CHANNEL_XFERCFG_COUNT                (52U)


/*!
 * @}
 */ /* end of group DMA_Register_Masks */


/* DMA - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral DMA0 base address */
  #define DMA0_BASE                                (0x50082000u)
  /** Peripheral DMA0 base address */
  #define DMA0_BASE_NS                             (0x40082000u)
  /** Peripheral DMA0 base pointer */
  #define DMA0                                     ((DMA_Type *)DMA0_BASE)
  /** Peripheral DMA0 base pointer */
  #define DMA0_NS                                  ((DMA_Type *)DMA0_BASE_NS)
  /** Peripheral DMA1 base address */
  #define DMA1_BASE                                (0x500A7000u)
  /** Peripheral DMA1 base address */
  #define DMA1_BASE_NS                             (0x400A7000u)
  /** Peripheral DMA1 base pointer */
  #define DMA1                                     ((DMA_Type *)DMA1_BASE)
  /** Peripheral DMA1 base pointer */
  #define DMA1_NS                                  ((DMA_Type *)DMA1_BASE_NS)
  /** Array initializer of DMA peripheral base addresses */
  #define DMA_BASE_ADDRS                           { DMA0_BASE, DMA1_BASE }
  /** Array initializer of DMA peripheral base pointers */
  #define DMA_BASE_PTRS                            { DMA0, DMA1 }
  /** Array initializer of DMA peripheral base addresses */
  #define DMA_BASE_ADDRS_NS                        { DMA0_BASE_NS, DMA1_BASE_NS }
  /** Array initializer of DMA peripheral base pointers */
  #define DMA_BASE_PTRS_NS                         { DMA0_NS, DMA1_NS }
#else
  /** Peripheral DMA0 base address */
  #define DMA0_BASE                                (0x40082000u)
  /** Peripheral DMA0 base pointer */
  #define DMA0                                     ((DMA_Type *)DMA0_BASE)
  /** Peripheral DMA1 base address */
  #define DMA1_BASE                                (0x400A7000u)
  /** Peripheral DMA1 base pointer */
  #define DMA1                                     ((DMA_Type *)DMA1_BASE)
  /** Array initializer of DMA peripheral base addresses */
  #define DMA_BASE_ADDRS                           { DMA0_BASE, DMA1_BASE }
  /** Array initializer of DMA peripheral base pointers */
  #define DMA_BASE_PTRS                            { DMA0, DMA1 }
#endif
/** Interrupt vectors for the DMA peripheral type */
#define DMA_IRQS                                 { DMA0_IRQn, DMA1_IRQn }

/*!
 * @}
 */ /* end of group DMA_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DMIC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMIC_Peripheral_Access_Layer DMIC Peripheral Access Layer
 * @{
 */

/** DMIC - Register Layout Typedef */
typedef struct {
  struct {                                         /* offset: 0x0, array step: 0x100 */
    __IO uint32_t OSR;                               /**< Oversample Rate, array offset: 0x0, array step: 0x100 */
    __IO uint32_t DIVHFCLK;                          /**< DMIC Clock, array offset: 0x4, array step: 0x100 */
    __IO uint32_t PREAC2FSCOEF;                      /**< Compensation Filter for 2 FS, array offset: 0x8, array step: 0x100 */
    __IO uint32_t PREAC4FSCOEF;                      /**< Compensation Filter for 4 FS, array offset: 0xC, array step: 0x100 */
    __IO uint32_t GAINSHIFT;                         /**< Decimator Gain Shift, array offset: 0x10, array step: 0x100 */
         uint8_t RESERVED_0[108];
    __IO uint32_t FIFO_CTRL;                         /**< FIFO Control, array offset: 0x80, array step: 0x100 */
    __IO uint32_t FIFO_STATUS;                       /**< FIFO Status, array offset: 0x84, array step: 0x100 */
    __I  uint32_t FIFO_DATA;                         /**< FIFO Data, array offset: 0x88, array step: 0x100 */
    __IO uint32_t PHY_CTRL;                          /**< Physical Control, array offset: 0x8C, array step: 0x100 */
    __IO uint32_t DC_CTRL;                           /**< DC Filter Control, array offset: 0x90, array step: 0x100 */
         uint8_t RESERVED_1[108];
  } CHANNEL[2];
       uint8_t RESERVED_0[3328];
  __IO uint32_t CHANEN;                            /**< Channel Enable, offset: 0xF00 */
       uint8_t RESERVED_1[12];
  __IO uint32_t USE2FS;                            /**< Use 2 FS register, offset: 0xF10 */
  __IO uint32_t GLOBAL_SYNC_EN;                    /**< Global Channel Synchronization Enable, offset: 0xF14 */
  __IO uint32_t GLOBAL_COUNT_VAL;                  /**< Global channel synchronization counter value, offset: 0xF18 */
  __IO uint32_t DECRESET;                          /**< DMIC decimator reset, offset: 0xF1C */
       uint8_t RESERVED_2[96];
  __IO uint32_t HWVADGAIN;                         /**< HWVAD Input Gain, offset: 0xF80 */
  __IO uint32_t HWVADHPFS;                         /**< HWVAD Filter Control, offset: 0xF84 */
  __IO uint32_t HWVADST10;                         /**< HWVAD Control, offset: 0xF88 */
  __IO uint32_t HWVADRSTT;                         /**< HWVAD Filter Reset, offset: 0xF8C */
  __IO uint32_t HWVADTHGN;                         /**< HWVAD Noise Estimator Gain, offset: 0xF90 */
  __IO uint32_t HWVADTHGS;                         /**< HWVAD Signal Estimator Gain, offset: 0xF94 */
  __I  uint32_t HWVADLOWZ;                         /**< HWVAD Noise Envelope Estimator, offset: 0xF98 */
} DMIC_Type;

/* ----------------------------------------------------------------------------
   -- DMIC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMIC_Register_Masks DMIC Register Masks
 * @{
 */

/*! @name CHANNEL_OSR - Oversample Rate */
/*! @{ */

#define DMIC_CHANNEL_OSR_OSR_MASK                (0xFFU)
#define DMIC_CHANNEL_OSR_OSR_SHIFT               (0U)
/*! OSR - Oversample Rate
 */
#define DMIC_CHANNEL_OSR_OSR(x)                  (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_OSR_OSR_SHIFT)) & DMIC_CHANNEL_OSR_OSR_MASK)
/*! @} */

/* The count of DMIC_CHANNEL_OSR */
#define DMIC_CHANNEL_OSR_COUNT                   (2U)

/*! @name CHANNEL_DIVHFCLK - DMIC Clock */
/*! @{ */

#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK        (0xFU)
#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT       (0U)
/*! PDMDIV - PDM Clock Divider Value
 *  0b0000..Divide by 1
 *  0b0001..Divide by 2
 *  0b0010..Divide by 3
 *  0b0011..Divide by 4
 *  0b0100..Divide by 6
 *  0b0101..Divide by 8
 *  0b0110..Divide by 12
 *  0b0111..Divide by 16
 *  0b1000..Divide by 24
 *  0b1001..Divide by 32
 *  0b1010..Divide by 48
 *  0b1011..Divide by 64
 *  0b1100..Divide by 96
 *  0b1101..Divide by 128
 *  0b1110-0b1111..Reserved
 */
#define DMIC_CHANNEL_DIVHFCLK_PDMDIV(x)          (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT)) & DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK)
/*! @} */

/* The count of DMIC_CHANNEL_DIVHFCLK */
#define DMIC_CHANNEL_DIVHFCLK_COUNT              (2U)

/*! @name CHANNEL_PREAC2FSCOEF - Compensation Filter for 2 FS */
/*! @{ */

#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK      (0x3U)
#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT     (0U)
/*! COMP - Compensation value
 *  0b00..Compensation = 0. This is the recommended setting.
 *  0b01..Compensation = -0.16
 *  0b10..Compensation = -0.15
 *  0b11..Compensation = -0.13
 */
#define DMIC_CHANNEL_PREAC2FSCOEF_COMP(x)        (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK)
/*! @} */

/* The count of DMIC_CHANNEL_PREAC2FSCOEF */
#define DMIC_CHANNEL_PREAC2FSCOEF_COUNT          (2U)

/*! @name CHANNEL_PREAC4FSCOEF - Compensation Filter for 4 FS */
/*! @{ */

#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK      (0x3U)
#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT     (0U)
/*! COMP - Compensation value
 *  0b00..Compensation = 0. This is the recommended setting.
 *  0b01..Compensation = -0.16
 *  0b10..Compensation = -0.15
 *  0b11..Compensation = -0.13
 */
#define DMIC_CHANNEL_PREAC4FSCOEF_COMP(x)        (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK)
/*! @} */

/* The count of DMIC_CHANNEL_PREAC4FSCOEF */
#define DMIC_CHANNEL_PREAC4FSCOEF_COUNT          (2U)

/*! @name CHANNEL_GAINSHIFT - Decimator Gain Shift */
/*! @{ */

#define DMIC_CHANNEL_GAINSHIFT_GAIN_MASK         (0x1FU)
#define DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT        (0U)
/*! GAIN - Gain
 */
#define DMIC_CHANNEL_GAINSHIFT_GAIN(x)           (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT)) & DMIC_CHANNEL_GAINSHIFT_GAIN_MASK)
/*! @} */

/* The count of DMIC_CHANNEL_GAINSHIFT */
#define DMIC_CHANNEL_GAINSHIFT_COUNT             (2U)

/*! @name CHANNEL_FIFO_CTRL - FIFO Control */
/*! @{ */

#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK       (0x1U)
#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT      (0U)
/*! ENABLE - FIFO Enable.
 *  0b0..Disabled.
 *  0b1..FIFO is enabled. The FIFO must be enabled in order for the CPU or DMA to read data from the DMIC via the FIFODATA register.
 */
#define DMIC_CHANNEL_FIFO_CTRL_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK)

#define DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK       (0x2U)
#define DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT      (1U)
/*! RESETN - FIFO Reset
 *  0b0..Reset the FIFO. This must be cleared before resuming operation.
 *  0b1..Normal operation
 */
#define DMIC_CHANNEL_FIFO_CTRL_RESETN(x)         (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK)

#define DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK        (0x4U)
#define DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT       (2U)
/*! INTEN - Interrupt Enable.
 *  0b0..FIFO level interrupts are not enabled.
 *  0b1..FIFO level interrupts are enabled.
 */
#define DMIC_CHANNEL_FIFO_CTRL_INTEN(x)          (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK)

#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK        (0x8U)
#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT       (3U)
/*! DMAEN - DMA Enable
 *  0b0..DMA requests are not enabled.
 *  0b1..DMA requests based on FIFO level are enabled.
 */
#define DMIC_CHANNEL_FIFO_CTRL_DMAEN(x)          (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK)

#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK      (0x1F0000U)
#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT     (16U)
/*! TRIGLVL - FIFO Trigger Level for Interrupt
 *  0b00000..Trigger when the FIFO has received one entry (is no longer empty).
 *  0b00001..Trigger when the FIFO has received two entries.
 *  0b01110..Trigger when the FIFO has received 15 entries.
 *  0b01111..Trigger when the FIFO has received 16 entries (has become full).
 */
#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL(x)        (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK)
/*! @} */

/* The count of DMIC_CHANNEL_FIFO_CTRL */
#define DMIC_CHANNEL_FIFO_CTRL_COUNT             (2U)

/*! @name CHANNEL_FIFO_STATUS - FIFO Status */
/*! @{ */

#define DMIC_CHANNEL_FIFO_STATUS_INT_MASK        (0x1U)
#define DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT       (0U)
/*! INT - Status of Interrupt (write 1 to clear)
 */
#define DMIC_CHANNEL_FIFO_STATUS_INT(x)          (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_INT_MASK)

#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK    (0x2U)
#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT   (1U)
/*! OVERRUN - Overrun Detected (write 1 to clear)
 */
#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN(x)      (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK)

#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK   (0x4U)
#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT  (2U)
/*! UNDERRUN - Underrun Detected (write 1 to clear)
 */
#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN(x)     (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK)
/*! @} */

/* The count of DMIC_CHANNEL_FIFO_STATUS */
#define DMIC_CHANNEL_FIFO_STATUS_COUNT           (2U)

/*! @name CHANNEL_FIFO_DATA - FIFO Data */
/*! @{ */

#define DMIC_CHANNEL_FIFO_DATA_DATA_MASK         (0xFFFFFFU)
#define DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT        (0U)
/*! DATA - PCM Data
 */
#define DMIC_CHANNEL_FIFO_DATA_DATA(x)           (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT)) & DMIC_CHANNEL_FIFO_DATA_DATA_MASK)
/*! @} */

/* The count of DMIC_CHANNEL_FIFO_DATA */
#define DMIC_CHANNEL_FIFO_DATA_COUNT             (2U)

/*! @name CHANNEL_PHY_CTRL - Physical Control */
/*! @{ */

#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK      (0x1U)
#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT     (0U)
/*! PHY_FALL - Capture DMIC on Falling edge (0 means on rising)
 *  0b0..Capture PDM_DATA on the rising edge of PDM_CLK.
 *  0b1..Capture PDM_DATA on the falling edge of PDM_CLK.
 */
#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL(x)        (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK)

#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK      (0x2U)
#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT     (1U)
/*! PHY_HALF - Use Half rate sampling (ie Clock to dmic is sent at half the speed than the decimator is providing)
 *  0b0..Standard half rate sampling. The clock to the DMIC is sent at the same rate as the decimator is providing.
 *  0b1..Use half rate sampling. The clock to the DMIC is sent at half the rate that the decimator is providing.
 */
#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF(x)        (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK)
/*! @} */

/* The count of DMIC_CHANNEL_PHY_CTRL */
#define DMIC_CHANNEL_PHY_CTRL_COUNT              (2U)

/*! @name CHANNEL_DC_CTRL - DC Filter Control */
/*! @{ */

#define DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK         (0x3U)
#define DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT        (0U)
/*! DCPOLE - DC Block Filter
 *  0b00..Flat Response, no filter
 *  0b01..155 Hz
 *  0b10..78 Hz
 *  0b11..39 Hz
 */
#define DMIC_CHANNEL_DC_CTRL_DCPOLE(x)           (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK)

#define DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK         (0xF0U)
#define DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT        (4U)
/*! DCGAIN - DC Gain
 */
#define DMIC_CHANNEL_DC_CTRL_DCGAIN(x)           (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK)

#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK (0x100U)
#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT (8U)
/*! SATURATEAT16BIT - Saturate at 16 Bit
 *  0b0..Do not Saturate. Results roll over if out range and do not saturate.
 *  0b1..Saturate. If the result overflows, it saturates at 0xFFFF for positive overflow and 0x8000 for negative overflow.
 */
#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(x)  (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT)) & DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK)

#define DMIC_CHANNEL_DC_CTRL_SIGNEXTEND_MASK     (0x200U)
#define DMIC_CHANNEL_DC_CTRL_SIGNEXTEND_SHIFT    (9U)
/*! SIGNEXTEND - Sign Extend
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define DMIC_CHANNEL_DC_CTRL_SIGNEXTEND(x)       (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_SIGNEXTEND_SHIFT)) & DMIC_CHANNEL_DC_CTRL_SIGNEXTEND_MASK)
/*! @} */

/* The count of DMIC_CHANNEL_DC_CTRL */
#define DMIC_CHANNEL_DC_CTRL_COUNT               (2U)

/*! @name CHANEN - Channel Enable */
/*! @{ */

#define DMIC_CHANEN_EN_CH0_MASK                  (0x1U)
#define DMIC_CHANEN_EN_CH0_SHIFT                 (0U)
/*! EN_CH0 - Enable Channel n
 *  0b0..PDM channel n is disabled.
 *  0b1..PDM channel n is enabled.
 */
#define DMIC_CHANEN_EN_CH0(x)                    (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH0_SHIFT)) & DMIC_CHANEN_EN_CH0_MASK)

#define DMIC_CHANEN_EN_CH1_MASK                  (0x2U)
#define DMIC_CHANEN_EN_CH1_SHIFT                 (1U)
/*! EN_CH1 - Enable Channel n
 *  0b0..PDM channel n is disabled.
 *  0b1..PDM channel n is enabled.
 */
#define DMIC_CHANEN_EN_CH1(x)                    (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH1_SHIFT)) & DMIC_CHANEN_EN_CH1_MASK)
/*! @} */

/*! @name USE2FS - Use 2 FS register */
/*! @{ */

#define DMIC_USE2FS_USE2FS_MASK                  (0x1U)
#define DMIC_USE2FS_USE2FS_SHIFT                 (0U)
/*! USE2FS - Use 2FS register
 *  0b0..Use 1 FS output for PCM data.
 *  0b1..Use 2 FS output for PCM data.
 */
#define DMIC_USE2FS_USE2FS(x)                    (((uint32_t)(((uint32_t)(x)) << DMIC_USE2FS_USE2FS_SHIFT)) & DMIC_USE2FS_USE2FS_MASK)
/*! @} */

/*! @name GLOBAL_SYNC_EN - Global Channel Synchronization Enable */
/*! @{ */

#define DMIC_GLOBAL_SYNC_EN_CH_SYNC_EN_MASK      (0x3U)
#define DMIC_GLOBAL_SYNC_EN_CH_SYNC_EN_SHIFT     (0U)
/*! CH_SYNC_EN - Channel synch enable
 */
#define DMIC_GLOBAL_SYNC_EN_CH_SYNC_EN(x)        (((uint32_t)(((uint32_t)(x)) << DMIC_GLOBAL_SYNC_EN_CH_SYNC_EN_SHIFT)) & DMIC_GLOBAL_SYNC_EN_CH_SYNC_EN_MASK)
/*! @} */

/*! @name GLOBAL_COUNT_VAL - Global channel synchronization counter value */
/*! @{ */

#define DMIC_GLOBAL_COUNT_VAL_CCOUNTVAL_MASK     (0xFFFFFFFFU)
#define DMIC_GLOBAL_COUNT_VAL_CCOUNTVAL_SHIFT    (0U)
/*! CCOUNTVAL - Channel Counter Value
 */
#define DMIC_GLOBAL_COUNT_VAL_CCOUNTVAL(x)       (((uint32_t)(((uint32_t)(x)) << DMIC_GLOBAL_COUNT_VAL_CCOUNTVAL_SHIFT)) & DMIC_GLOBAL_COUNT_VAL_CCOUNTVAL_MASK)
/*! @} */

/*! @name DECRESET - DMIC decimator reset */
/*! @{ */

#define DMIC_DECRESET_DECRESET_MASK              (0x3U)
#define DMIC_DECRESET_DECRESET_SHIFT             (0U)
/*! DECRESET - Decimator reset
 *  0b00..Disable
 *  0b01..Enable
 */
#define DMIC_DECRESET_DECRESET(x)                (((uint32_t)(((uint32_t)(x)) << DMIC_DECRESET_DECRESET_SHIFT)) & DMIC_DECRESET_DECRESET_MASK)
/*! @} */

/*! @name HWVADGAIN - HWVAD Input Gain */
/*! @{ */

#define DMIC_HWVADGAIN_INPUTGAIN_MASK            (0xFU)
#define DMIC_HWVADGAIN_INPUTGAIN_SHIFT           (0U)
/*! INPUTGAIN - Input Gain
 *  0b0000..-10 bits
 *  0b0001..-8 bits
 *  0b0010..-6 bits
 *  0b0011..-4 bits
 *  0b0100..-2 bits
 *  0b0101..0 bits (default)
 *  0b0110..+2 bits
 *  0b0111..+4 bits
 *  0b1000..+6 bits
 *  0b1001..+8 bits
 *  0b1010..+10 bits
 *  0b1011..+12 bits
 *  0b1100..+14 bits
 *  0b1101-0b1111..Reserved
 */
#define DMIC_HWVADGAIN_INPUTGAIN(x)              (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADGAIN_INPUTGAIN_SHIFT)) & DMIC_HWVADGAIN_INPUTGAIN_MASK)
/*! @} */

/*! @name HWVADHPFS - HWVAD Filter Control */
/*! @{ */

#define DMIC_HWVADHPFS_HPFS_MASK                 (0x3U)
#define DMIC_HWVADHPFS_HPFS_SHIFT                (0U)
/*! HPFS - The HPFS field chooses the High Pass filter in first part of HWVAD.
 *  0b00..Bypass
 *  0b01..High Pass 1750 Hz
 *  0b10..High Pass 215 Hz
 *  0b11..Reserved
 */
#define DMIC_HWVADHPFS_HPFS(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADHPFS_HPFS_SHIFT)) & DMIC_HWVADHPFS_HPFS_MASK)
/*! @} */

/*! @name HWVADST10 - HWVAD Control */
/*! @{ */

#define DMIC_HWVADST10_ST10_MASK                 (0x1U)
#define DMIC_HWVADST10_ST10_SHIFT                (0U)
/*! ST10 - STAGE 1
 *  0b0..Normal operation, waiting for HWVAD trigger event (stage 0).
 *  0b1..Reset internal interrupt flag by writing a '1' (stage 1) pulse.
 */
#define DMIC_HWVADST10_ST10(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADST10_ST10_SHIFT)) & DMIC_HWVADST10_ST10_MASK)
/*! @} */

/*! @name HWVADRSTT - HWVAD Filter Reset */
/*! @{ */

#define DMIC_HWVADRSTT_RSST_MASK                 (0x1U)
#define DMIC_HWVADRSTT_RSST_SHIFT                (0U)
/*! RSST - Reset HWVAD
 */
#define DMIC_HWVADRSTT_RSST(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADRSTT_RSST_SHIFT)) & DMIC_HWVADRSTT_RSST_MASK)
/*! @} */

/*! @name HWVADTHGN - HWVAD Noise Estimator Gain */
/*! @{ */

#define DMIC_HWVADTHGN_THGN_MASK                 (0xFU)
#define DMIC_HWVADTHGN_THGN_SHIFT                (0U)
/*! THGN - Gain Factor for Noise Estimator
 */
#define DMIC_HWVADTHGN_THGN(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGN_THGN_SHIFT)) & DMIC_HWVADTHGN_THGN_MASK)
/*! @} */

/*! @name HWVADTHGS - HWVAD Signal Estimator Gain */
/*! @{ */

#define DMIC_HWVADTHGS_THGS_MASK                 (0xFU)
#define DMIC_HWVADTHGS_THGS_SHIFT                (0U)
/*! THGS - Signal Gain Factor
 */
#define DMIC_HWVADTHGS_THGS(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGS_THGS_SHIFT)) & DMIC_HWVADTHGS_THGS_MASK)
/*! @} */

/*! @name HWVADLOWZ - HWVAD Noise Envelope Estimator */
/*! @{ */

#define DMIC_HWVADLOWZ_LOWZ_MASK                 (0xFFFFU)
#define DMIC_HWVADLOWZ_LOWZ_SHIFT                (0U)
/*! LOWZ - Average Noise-floor Value
 */
#define DMIC_HWVADLOWZ_LOWZ(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADLOWZ_LOWZ_SHIFT)) & DMIC_HWVADLOWZ_LOWZ_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group DMIC_Register_Masks */


/* DMIC - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral DMIC0 base address */
  #define DMIC0_BASE                               (0x50090000u)
  /** Peripheral DMIC0 base address */
  #define DMIC0_BASE_NS                            (0x40090000u)
  /** Peripheral DMIC0 base pointer */
  #define DMIC0                                    ((DMIC_Type *)DMIC0_BASE)
  /** Peripheral DMIC0 base pointer */
  #define DMIC0_NS                                 ((DMIC_Type *)DMIC0_BASE_NS)
  /** Array initializer of DMIC peripheral base addresses */
  #define DMIC_BASE_ADDRS                          { DMIC0_BASE }
  /** Array initializer of DMIC peripheral base pointers */
  #define DMIC_BASE_PTRS                           { DMIC0 }
  /** Array initializer of DMIC peripheral base addresses */
  #define DMIC_BASE_ADDRS_NS                       { DMIC0_BASE_NS }
  /** Array initializer of DMIC peripheral base pointers */
  #define DMIC_BASE_PTRS_NS                        { DMIC0_NS }
#else
  /** Peripheral DMIC0 base address */
  #define DMIC0_BASE                               (0x40090000u)
  /** Peripheral DMIC0 base pointer */
  #define DMIC0                                    ((DMIC_Type *)DMIC0_BASE)
  /** Array initializer of DMIC peripheral base addresses */
  #define DMIC_BASE_ADDRS                          { DMIC0_BASE }
  /** Array initializer of DMIC peripheral base pointers */
  #define DMIC_BASE_PTRS                           { DMIC0 }
#endif
/** Interrupt vectors for the DMIC peripheral type */
#define DMIC_IRQS                                { DMIC_IRQn }
#define DMIC_HWVAD_IRQS                          { HWVAD0_IRQn }

/*!
 * @}
 */ /* end of group DMIC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- ENC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup ENC_Peripheral_Access_Layer ENC Peripheral Access Layer
 * @{
 */

/** ENC - Register Layout Typedef */
typedef struct {
  __IO uint16_t CTRL;                              /**< Control Register, offset: 0x0 */
  __IO uint16_t FILT;                              /**< Input Filter Register, offset: 0x2 */
  __IO uint16_t WTR;                               /**< Watchdog Timeout Register, offset: 0x4 */
  __IO uint16_t POSD;                              /**< Position Difference Counter Register, offset: 0x6 */
  __I  uint16_t POSDH;                             /**< Position Difference Hold Register, offset: 0x8 */
  __IO uint16_t REV;                               /**< Revolution Counter Register, offset: 0xA */
  __I  uint16_t REVH;                              /**< Revolution Hold Register, offset: 0xC */
  __IO uint16_t UPOS;                              /**< Upper Position Counter Register, offset: 0xE */
  __IO uint16_t LPOS;                              /**< Lower Position Counter Register, offset: 0x10 */
  __I  uint16_t UPOSH;                             /**< Upper Position Hold Register, offset: 0x12 */
  __I  uint16_t LPOSH;                             /**< Lower Position Hold Register, offset: 0x14 */
  __IO uint16_t UINIT;                             /**< Upper Initialization Register, offset: 0x16 */
  __IO uint16_t LINIT;                             /**< Lower Initialization Register, offset: 0x18 */
  __I  uint16_t IMR;                               /**< Input Monitor Register, offset: 0x1A */
  __IO uint16_t TST;                               /**< Test Register, offset: 0x1C */
  __IO uint16_t CTRL2;                             /**< Control 2 Register, offset: 0x1E */
  __IO uint16_t UMOD;                              /**< Upper Modulus Register, offset: 0x20 */
  __IO uint16_t LMOD;                              /**< Lower Modulus Register, offset: 0x22 */
  __IO uint16_t UCOMP;                             /**< Upper Position Compare Register, offset: 0x24 */
  __IO uint16_t LCOMP;                             /**< Lower Position Compare Register, offset: 0x26 */
  __I  uint16_t LASTEDGE;                          /**< Last Edge Time Register, offset: 0x28 */
  __I  uint16_t LASTEDGEH;                         /**< Last Edge Time Hold Register, offset: 0x2A */
  __I  uint16_t POSDPER;                           /**< Position Difference Period Counter Register, offset: 0x2C */
  __I  uint16_t POSDPERBFR;                        /**< Position Difference Period Buffer Register, offset: 0x2E */
  __I  uint16_t POSDPERH;                          /**< Position Difference Period Hold Register, offset: 0x30 */
  __IO uint16_t CTRL3;                             /**< Control 3 Register, offset: 0x32 */
} ENC_Type;

/* ----------------------------------------------------------------------------
   -- ENC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup ENC_Register_Masks ENC Register Masks
 * @{
 */

/*! @name CTRL - Control Register */
/*! @{ */

#define ENC_CTRL_CMPIE_MASK                      (0x1U)
#define ENC_CTRL_CMPIE_SHIFT                     (0U)
/*! CMPIE - Compare Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define ENC_CTRL_CMPIE(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIE_SHIFT)) & ENC_CTRL_CMPIE_MASK)

#define ENC_CTRL_CMPIRQ_MASK                     (0x2U)
#define ENC_CTRL_CMPIRQ_SHIFT                    (1U)
/*! CMPIRQ - Compare Interrupt Request
 *  0b0..No match has occurred (the counter does not match the COMP value)
 *  0b1..COMP match has occurred (the counter matches the COMP value)
 */
#define ENC_CTRL_CMPIRQ(x)                       (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIRQ_SHIFT)) & ENC_CTRL_CMPIRQ_MASK)

#define ENC_CTRL_WDE_MASK                        (0x4U)
#define ENC_CTRL_WDE_SHIFT                       (2U)
/*! WDE - Watchdog Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define ENC_CTRL_WDE(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_WDE_SHIFT)) & ENC_CTRL_WDE_MASK)

#define ENC_CTRL_DIE_MASK                        (0x8U)
#define ENC_CTRL_DIE_SHIFT                       (3U)
/*! DIE - Watchdog Timeout Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define ENC_CTRL_DIE(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIE_SHIFT)) & ENC_CTRL_DIE_MASK)

#define ENC_CTRL_DIRQ_MASK                       (0x10U)
#define ENC_CTRL_DIRQ_SHIFT                      (4U)
/*! DIRQ - Watchdog Timeout Interrupt Request
 *  0b0..No Watchdog timeout interrupt has occurred
 *  0b1..Watchdog timeout interrupt has occurred
 */
#define ENC_CTRL_DIRQ(x)                         (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIRQ_SHIFT)) & ENC_CTRL_DIRQ_MASK)

#define ENC_CTRL_XNE_MASK                        (0x20U)
#define ENC_CTRL_XNE_SHIFT                       (5U)
/*! XNE - Use Negative Edge of INDEX Pulse
 *  0b0..Use positive edge of INDEX pulse
 *  0b1..Use negative edge of INDEX pulse
 */
#define ENC_CTRL_XNE(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XNE_SHIFT)) & ENC_CTRL_XNE_MASK)

#define ENC_CTRL_XIP_MASK                        (0x40U)
#define ENC_CTRL_XIP_SHIFT                       (6U)
/*! XIP - INDEX Triggered Initialization of Position Counters UPOS and LPOS
 *  0b0..INDEX pulse does not initialize the position counter
 *  0b1..INDEX pulse initializes the position counter
 */
#define ENC_CTRL_XIP(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIP_SHIFT)) & ENC_CTRL_XIP_MASK)

#define ENC_CTRL_XIE_MASK                        (0x80U)
#define ENC_CTRL_XIE_SHIFT                       (7U)
/*! XIE - INDEX Pulse Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define ENC_CTRL_XIE(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIE_SHIFT)) & ENC_CTRL_XIE_MASK)

#define ENC_CTRL_XIRQ_MASK                       (0x100U)
#define ENC_CTRL_XIRQ_SHIFT                      (8U)
/*! XIRQ - INDEX Pulse Interrupt Request
 *  0b0..INDEX pulse has not occurred
 *  0b1..INDEX pulse has occurred
 */
#define ENC_CTRL_XIRQ(x)                         (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIRQ_SHIFT)) & ENC_CTRL_XIRQ_MASK)

#define ENC_CTRL_PH1_MASK                        (0x200U)
#define ENC_CTRL_PH1_SHIFT                       (9U)
/*! PH1 - Enable Signal Phase Count Mode
 *  0b0..Use the standard quadrature decoder, where PHASEA and PHASEB represent a two-phase quadrature signal.
 *  0b1..Bypass the quadrature decoder. A positive transition of the PHASEA input generates a count signal. The
 *       PHASEB input and the REV bit control the counter direction: If CTRL[REV] = 0, PHASEB = 0, then count up If
 *       CTRL[REV] = 1, PHASEB = 1, then count up If CTRL[REV] = 0, PHASEB = 1, then count down If CTRL[REV] = 1,
 *       PHASEB = 0, then count down
 */
#define ENC_CTRL_PH1(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_PH1_SHIFT)) & ENC_CTRL_PH1_MASK)

#define ENC_CTRL_REV_MASK                        (0x400U)
#define ENC_CTRL_REV_SHIFT                       (10U)
/*! REV - Enable Reverse Direction Counting
 *  0b0..Count normally
 *  0b1..Count in the reverse direction
 */
#define ENC_CTRL_REV(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_REV_SHIFT)) & ENC_CTRL_REV_MASK)

#define ENC_CTRL_SWIP_MASK                       (0x800U)
#define ENC_CTRL_SWIP_SHIFT                      (11U)
/*! SWIP - Software-Triggered Initialization of Position Counters UPOS and LPOS
 *  0b0..No action
 *  0b1..Initialize position counter (using upper and lower initialization registers, UINIT and LINIT)
 */
#define ENC_CTRL_SWIP(x)                         (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_SWIP_SHIFT)) & ENC_CTRL_SWIP_MASK)

#define ENC_CTRL_HNE_MASK                        (0x1000U)
#define ENC_CTRL_HNE_SHIFT                       (12U)
/*! HNE - Use Negative Edge of HOME Input
 *  0b0..Use positive-going edge-to-trigger initialization of position counters UPOS and LPOS
 *  0b1..Use negative-going edge-to-trigger initialization of position counters UPOS and LPOS
 */
#define ENC_CTRL_HNE(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HNE_SHIFT)) & ENC_CTRL_HNE_MASK)

#define ENC_CTRL_HIP_MASK                        (0x2000U)
#define ENC_CTRL_HIP_SHIFT                       (13U)
/*! HIP - Enable HOME to Initialize Position Counters UPOS and LPOS
 *  0b0..No action
 *  0b1..HOME signal initializes the position counter
 */
#define ENC_CTRL_HIP(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIP_SHIFT)) & ENC_CTRL_HIP_MASK)

#define ENC_CTRL_HIE_MASK                        (0x4000U)
#define ENC_CTRL_HIE_SHIFT                       (14U)
/*! HIE - HOME Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define ENC_CTRL_HIE(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIE_SHIFT)) & ENC_CTRL_HIE_MASK)

#define ENC_CTRL_HIRQ_MASK                       (0x8000U)
#define ENC_CTRL_HIRQ_SHIFT                      (15U)
/*! HIRQ - HOME Signal Transition Interrupt Request
 *  0b0..No transition on the HOME signal has occurred
 *  0b1..A transition on the HOME signal has occurred
 */
#define ENC_CTRL_HIRQ(x)                         (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIRQ_SHIFT)) & ENC_CTRL_HIRQ_MASK)
/*! @} */

/*! @name FILT - Input Filter Register */
/*! @{ */

#define ENC_FILT_FILT_PER_MASK                   (0xFFU)
#define ENC_FILT_FILT_PER_SHIFT                  (0U)
/*! FILT_PER - Input Filter Sample Period
 */
#define ENC_FILT_FILT_PER(x)                     (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_PER_SHIFT)) & ENC_FILT_FILT_PER_MASK)

#define ENC_FILT_FILT_CNT_MASK                   (0x700U)
#define ENC_FILT_FILT_CNT_SHIFT                  (8U)
/*! FILT_CNT - Input Filter Sample Count
 */
#define ENC_FILT_FILT_CNT(x)                     (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_CNT_SHIFT)) & ENC_FILT_FILT_CNT_MASK)

#define ENC_FILT_FILT_PRSC_MASK                  (0xE000U)
#define ENC_FILT_FILT_PRSC_SHIFT                 (13U)
/*! FILT_PRSC - prescaler divide IPbus clock to FILT clk
 */
#define ENC_FILT_FILT_PRSC(x)                    (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_PRSC_SHIFT)) & ENC_FILT_FILT_PRSC_MASK)
/*! @} */

/*! @name WTR - Watchdog Timeout Register */
/*! @{ */

#define ENC_WTR_WDOG_MASK                        (0xFFFFU)
#define ENC_WTR_WDOG_SHIFT                       (0U)
/*! WDOG - WDOG
 */
#define ENC_WTR_WDOG(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_WTR_WDOG_SHIFT)) & ENC_WTR_WDOG_MASK)
/*! @} */

/*! @name POSD - Position Difference Counter Register */
/*! @{ */

#define ENC_POSD_POSD_MASK                       (0xFFFFU)
#define ENC_POSD_POSD_SHIFT                      (0U)
/*! POSD - POSD
 */
#define ENC_POSD_POSD(x)                         (((uint16_t)(((uint16_t)(x)) << ENC_POSD_POSD_SHIFT)) & ENC_POSD_POSD_MASK)
/*! @} */

/*! @name POSDH - Position Difference Hold Register */
/*! @{ */

#define ENC_POSDH_POSDH_MASK                     (0xFFFFU)
#define ENC_POSDH_POSDH_SHIFT                    (0U)
/*! POSDH - POSDH
 */
#define ENC_POSDH_POSDH(x)                       (((uint16_t)(((uint16_t)(x)) << ENC_POSDH_POSDH_SHIFT)) & ENC_POSDH_POSDH_MASK)
/*! @} */

/*! @name REV - Revolution Counter Register */
/*! @{ */

#define ENC_REV_REV_MASK                         (0xFFFFU)
#define ENC_REV_REV_SHIFT                        (0U)
/*! REV - REV
 */
#define ENC_REV_REV(x)                           (((uint16_t)(((uint16_t)(x)) << ENC_REV_REV_SHIFT)) & ENC_REV_REV_MASK)
/*! @} */

/*! @name REVH - Revolution Hold Register */
/*! @{ */

#define ENC_REVH_REVH_MASK                       (0xFFFFU)
#define ENC_REVH_REVH_SHIFT                      (0U)
/*! REVH - REVH
 */
#define ENC_REVH_REVH(x)                         (((uint16_t)(((uint16_t)(x)) << ENC_REVH_REVH_SHIFT)) & ENC_REVH_REVH_MASK)
/*! @} */

/*! @name UPOS - Upper Position Counter Register */
/*! @{ */

#define ENC_UPOS_POS_MASK                        (0xFFFFU)
#define ENC_UPOS_POS_SHIFT                       (0U)
/*! POS - POS
 */
#define ENC_UPOS_POS(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_UPOS_POS_SHIFT)) & ENC_UPOS_POS_MASK)
/*! @} */

/*! @name LPOS - Lower Position Counter Register */
/*! @{ */

#define ENC_LPOS_POS_MASK                        (0xFFFFU)
#define ENC_LPOS_POS_SHIFT                       (0U)
/*! POS - POS
 */
#define ENC_LPOS_POS(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_LPOS_POS_SHIFT)) & ENC_LPOS_POS_MASK)
/*! @} */

/*! @name UPOSH - Upper Position Hold Register */
/*! @{ */

#define ENC_UPOSH_POSH_MASK                      (0xFFFFU)
#define ENC_UPOSH_POSH_SHIFT                     (0U)
/*! POSH - POSH
 */
#define ENC_UPOSH_POSH(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_UPOSH_POSH_SHIFT)) & ENC_UPOSH_POSH_MASK)
/*! @} */

/*! @name LPOSH - Lower Position Hold Register */
/*! @{ */

#define ENC_LPOSH_POSH_MASK                      (0xFFFFU)
#define ENC_LPOSH_POSH_SHIFT                     (0U)
/*! POSH - POSH
 */
#define ENC_LPOSH_POSH(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_LPOSH_POSH_SHIFT)) & ENC_LPOSH_POSH_MASK)
/*! @} */

/*! @name UINIT - Upper Initialization Register */
/*! @{ */

#define ENC_UINIT_INIT_MASK                      (0xFFFFU)
#define ENC_UINIT_INIT_SHIFT                     (0U)
/*! INIT - INIT
 */
#define ENC_UINIT_INIT(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_UINIT_INIT_SHIFT)) & ENC_UINIT_INIT_MASK)
/*! @} */

/*! @name LINIT - Lower Initialization Register */
/*! @{ */

#define ENC_LINIT_INIT_MASK                      (0xFFFFU)
#define ENC_LINIT_INIT_SHIFT                     (0U)
/*! INIT - INIT
 */
#define ENC_LINIT_INIT(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_LINIT_INIT_SHIFT)) & ENC_LINIT_INIT_MASK)
/*! @} */

/*! @name IMR - Input Monitor Register */
/*! @{ */

#define ENC_IMR_HOME_MASK                        (0x1U)
#define ENC_IMR_HOME_SHIFT                       (0U)
/*! HOME - HOME
 */
#define ENC_IMR_HOME(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_IMR_HOME_SHIFT)) & ENC_IMR_HOME_MASK)

#define ENC_IMR_INDEX_MASK                       (0x2U)
#define ENC_IMR_INDEX_SHIFT                      (1U)
/*! INDEX - INDEX
 */
#define ENC_IMR_INDEX(x)                         (((uint16_t)(((uint16_t)(x)) << ENC_IMR_INDEX_SHIFT)) & ENC_IMR_INDEX_MASK)

#define ENC_IMR_PHB_MASK                         (0x4U)
#define ENC_IMR_PHB_SHIFT                        (2U)
/*! PHB - PHB
 */
#define ENC_IMR_PHB(x)                           (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHB_SHIFT)) & ENC_IMR_PHB_MASK)

#define ENC_IMR_PHA_MASK                         (0x8U)
#define ENC_IMR_PHA_SHIFT                        (3U)
/*! PHA - PHA
 */
#define ENC_IMR_PHA(x)                           (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHA_SHIFT)) & ENC_IMR_PHA_MASK)

#define ENC_IMR_FHOM_MASK                        (0x10U)
#define ENC_IMR_FHOM_SHIFT                       (4U)
/*! FHOM - FHOM
 */
#define ENC_IMR_FHOM(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FHOM_SHIFT)) & ENC_IMR_FHOM_MASK)

#define ENC_IMR_FIND_MASK                        (0x20U)
#define ENC_IMR_FIND_SHIFT                       (5U)
/*! FIND - FIND
 */
#define ENC_IMR_FIND(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FIND_SHIFT)) & ENC_IMR_FIND_MASK)

#define ENC_IMR_FPHB_MASK                        (0x40U)
#define ENC_IMR_FPHB_SHIFT                       (6U)
/*! FPHB - FPHB
 */
#define ENC_IMR_FPHB(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHB_SHIFT)) & ENC_IMR_FPHB_MASK)

#define ENC_IMR_FPHA_MASK                        (0x80U)
#define ENC_IMR_FPHA_SHIFT                       (7U)
/*! FPHA - FPHA
 */
#define ENC_IMR_FPHA(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHA_SHIFT)) & ENC_IMR_FPHA_MASK)
/*! @} */

/*! @name TST - Test Register */
/*! @{ */

#define ENC_TST_TEST_COUNT_MASK                  (0xFFU)
#define ENC_TST_TEST_COUNT_SHIFT                 (0U)
/*! TEST_COUNT - TEST_COUNT
 */
#define ENC_TST_TEST_COUNT(x)                    (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_COUNT_SHIFT)) & ENC_TST_TEST_COUNT_MASK)

#define ENC_TST_TEST_PERIOD_MASK                 (0x1F00U)
#define ENC_TST_TEST_PERIOD_SHIFT                (8U)
/*! TEST_PERIOD - TEST_PERIOD
 */
#define ENC_TST_TEST_PERIOD(x)                   (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_PERIOD_SHIFT)) & ENC_TST_TEST_PERIOD_MASK)

#define ENC_TST_QDN_MASK                         (0x2000U)
#define ENC_TST_QDN_SHIFT                        (13U)
/*! QDN - Quadrature Decoder Negative Signal
 *  0b0..Generates a positive quadrature decoder signal
 *  0b1..Generates a negative quadrature decoder signal
 */
#define ENC_TST_QDN(x)                           (((uint16_t)(((uint16_t)(x)) << ENC_TST_QDN_SHIFT)) & ENC_TST_QDN_MASK)

#define ENC_TST_TCE_MASK                         (0x4000U)
#define ENC_TST_TCE_SHIFT                        (14U)
/*! TCE - Test Counter Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define ENC_TST_TCE(x)                           (((uint16_t)(((uint16_t)(x)) << ENC_TST_TCE_SHIFT)) & ENC_TST_TCE_MASK)

#define ENC_TST_TEN_MASK                         (0x8000U)
#define ENC_TST_TEN_SHIFT                        (15U)
/*! TEN - Test Mode Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define ENC_TST_TEN(x)                           (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEN_SHIFT)) & ENC_TST_TEN_MASK)
/*! @} */

/*! @name CTRL2 - Control 2 Register */
/*! @{ */

#define ENC_CTRL2_UPDHLD_MASK                    (0x1U)
#define ENC_CTRL2_UPDHLD_SHIFT                   (0U)
/*! UPDHLD - Update Hold Registers
 *  0b0..Disable updates of hold registers on the rising edge of TRIGGER input signal
 *  0b1..Enable updates of hold registers on the rising edge of TRIGGER input signal
 */
#define ENC_CTRL2_UPDHLD(x)                      (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDHLD_SHIFT)) & ENC_CTRL2_UPDHLD_MASK)

#define ENC_CTRL2_UPDPOS_MASK                    (0x2U)
#define ENC_CTRL2_UPDPOS_SHIFT                   (1U)
/*! UPDPOS - Update Position Registers
 *  0b0..No action for POSD, REV, UPOS and LPOS registers on rising edge of TRIGGER
 *  0b1..Clear POSD, REV, UPOS and LPOS registers on rising edge of TRIGGER
 */
#define ENC_CTRL2_UPDPOS(x)                      (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDPOS_SHIFT)) & ENC_CTRL2_UPDPOS_MASK)

#define ENC_CTRL2_MOD_MASK                       (0x4U)
#define ENC_CTRL2_MOD_SHIFT                      (2U)
/*! MOD - Enable Modulo Counting
 *  0b0..Disable modulo counting
 *  0b1..Enable modulo counting
 */
#define ENC_CTRL2_MOD(x)                         (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_MOD_SHIFT)) & ENC_CTRL2_MOD_MASK)

#define ENC_CTRL2_DIR_MASK                       (0x8U)
#define ENC_CTRL2_DIR_SHIFT                      (3U)
/*! DIR - Count Direction Flag
 *  0b0..Last count was in the down direction
 *  0b1..Last count was in the up direction
 */
#define ENC_CTRL2_DIR(x)                         (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_DIR_SHIFT)) & ENC_CTRL2_DIR_MASK)

#define ENC_CTRL2_RUIE_MASK                      (0x10U)
#define ENC_CTRL2_RUIE_SHIFT                     (4U)
/*! RUIE - Roll-under Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define ENC_CTRL2_RUIE(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIE_SHIFT)) & ENC_CTRL2_RUIE_MASK)

#define ENC_CTRL2_RUIRQ_MASK                     (0x20U)
#define ENC_CTRL2_RUIRQ_SHIFT                    (5U)
/*! RUIRQ - Roll-under Interrupt Request
 *  0b0..No roll-under has occurred
 *  0b1..Roll-under has occurred
 */
#define ENC_CTRL2_RUIRQ(x)                       (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIRQ_SHIFT)) & ENC_CTRL2_RUIRQ_MASK)

#define ENC_CTRL2_ROIE_MASK                      (0x40U)
#define ENC_CTRL2_ROIE_SHIFT                     (6U)
/*! ROIE - Roll-over Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define ENC_CTRL2_ROIE(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIE_SHIFT)) & ENC_CTRL2_ROIE_MASK)

#define ENC_CTRL2_ROIRQ_MASK                     (0x80U)
#define ENC_CTRL2_ROIRQ_SHIFT                    (7U)
/*! ROIRQ - Roll-over Interrupt Request
 *  0b0..No roll-over has occurred
 *  0b1..Roll-over has occurred
 */
#define ENC_CTRL2_ROIRQ(x)                       (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIRQ_SHIFT)) & ENC_CTRL2_ROIRQ_MASK)

#define ENC_CTRL2_REVMOD_MASK                    (0x100U)
#define ENC_CTRL2_REVMOD_SHIFT                   (8U)
/*! REVMOD - Revolution Counter Modulus Enable
 *  0b0..Use INDEX pulse to increment/decrement revolution counter (REV)
 *  0b1..Use modulus counting roll-over/under to increment/decrement revolution counter (REV)
 */
#define ENC_CTRL2_REVMOD(x)                      (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_REVMOD_SHIFT)) & ENC_CTRL2_REVMOD_MASK)

#define ENC_CTRL2_OUTCTL_MASK                    (0x200U)
#define ENC_CTRL2_OUTCTL_SHIFT                   (9U)
/*! OUTCTL - Output Control
 *  0b0..POSMATCH pulses when a match occurs between the position counters (POS) and the corresponding compare value (COMP )
 *  0b1..POSMATCH pulses when the UPOS, LPOS, REV, or POSD registers are read
 */
#define ENC_CTRL2_OUTCTL(x)                      (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_OUTCTL_SHIFT)) & ENC_CTRL2_OUTCTL_MASK)

#define ENC_CTRL2_SABIE_MASK                     (0x400U)
#define ENC_CTRL2_SABIE_SHIFT                    (10U)
/*! SABIE - Simultaneous PHASEA and PHASEB Change Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define ENC_CTRL2_SABIE(x)                       (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIE_SHIFT)) & ENC_CTRL2_SABIE_MASK)

#define ENC_CTRL2_SABIRQ_MASK                    (0x800U)
#define ENC_CTRL2_SABIRQ_SHIFT                   (11U)
/*! SABIRQ - Simultaneous PHASEA and PHASEB Change Interrupt Request
 *  0b0..No simultaneous change of PHASEA and PHASEB has occurred
 *  0b1..A simultaneous change of PHASEA and PHASEB has occurred
 */
#define ENC_CTRL2_SABIRQ(x)                      (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIRQ_SHIFT)) & ENC_CTRL2_SABIRQ_MASK)
/*! @} */

/*! @name UMOD - Upper Modulus Register */
/*! @{ */

#define ENC_UMOD_MOD_MASK                        (0xFFFFU)
#define ENC_UMOD_MOD_SHIFT                       (0U)
/*! MOD - MOD
 */
#define ENC_UMOD_MOD(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_UMOD_MOD_SHIFT)) & ENC_UMOD_MOD_MASK)
/*! @} */

/*! @name LMOD - Lower Modulus Register */
/*! @{ */

#define ENC_LMOD_MOD_MASK                        (0xFFFFU)
#define ENC_LMOD_MOD_SHIFT                       (0U)
/*! MOD - MOD
 */
#define ENC_LMOD_MOD(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_LMOD_MOD_SHIFT)) & ENC_LMOD_MOD_MASK)
/*! @} */

/*! @name UCOMP - Upper Position Compare Register */
/*! @{ */

#define ENC_UCOMP_COMP_MASK                      (0xFFFFU)
#define ENC_UCOMP_COMP_SHIFT                     (0U)
/*! COMP - COMP
 */
#define ENC_UCOMP_COMP(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_UCOMP_COMP_SHIFT)) & ENC_UCOMP_COMP_MASK)
/*! @} */

/*! @name LCOMP - Lower Position Compare Register */
/*! @{ */

#define ENC_LCOMP_COMP_MASK                      (0xFFFFU)
#define ENC_LCOMP_COMP_SHIFT                     (0U)
/*! COMP - COMP
 */
#define ENC_LCOMP_COMP(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_LCOMP_COMP_SHIFT)) & ENC_LCOMP_COMP_MASK)
/*! @} */

/*! @name LASTEDGE - Last Edge Time Register */
/*! @{ */

#define ENC_LASTEDGE_LASTEDGE_MASK               (0xFFFFU)
#define ENC_LASTEDGE_LASTEDGE_SHIFT              (0U)
/*! LASTEDGE - Last Edge Time Counter
 */
#define ENC_LASTEDGE_LASTEDGE(x)                 (((uint16_t)(((uint16_t)(x)) << ENC_LASTEDGE_LASTEDGE_SHIFT)) & ENC_LASTEDGE_LASTEDGE_MASK)
/*! @} */

/*! @name LASTEDGEH - Last Edge Time Hold Register */
/*! @{ */

#define ENC_LASTEDGEH_LASTEDGEH_MASK             (0xFFFFU)
#define ENC_LASTEDGEH_LASTEDGEH_SHIFT            (0U)
/*! LASTEDGEH - Last Edge Time Hold
 */
#define ENC_LASTEDGEH_LASTEDGEH(x)               (((uint16_t)(((uint16_t)(x)) << ENC_LASTEDGEH_LASTEDGEH_SHIFT)) & ENC_LASTEDGEH_LASTEDGEH_MASK)
/*! @} */

/*! @name POSDPER - Position Difference Period Counter Register */
/*! @{ */

#define ENC_POSDPER_POSDPER_MASK                 (0xFFFFU)
#define ENC_POSDPER_POSDPER_SHIFT                (0U)
/*! POSDPER - Position difference period
 */
#define ENC_POSDPER_POSDPER(x)                   (((uint16_t)(((uint16_t)(x)) << ENC_POSDPER_POSDPER_SHIFT)) & ENC_POSDPER_POSDPER_MASK)
/*! @} */

/*! @name POSDPERBFR - Position Difference Period Buffer Register */
/*! @{ */

#define ENC_POSDPERBFR_POSDPERBFR_MASK           (0xFFFFU)
#define ENC_POSDPERBFR_POSDPERBFR_SHIFT          (0U)
/*! POSDPERBFR - Position difference period buffer
 */
#define ENC_POSDPERBFR_POSDPERBFR(x)             (((uint16_t)(((uint16_t)(x)) << ENC_POSDPERBFR_POSDPERBFR_SHIFT)) & ENC_POSDPERBFR_POSDPERBFR_MASK)
/*! @} */

/*! @name POSDPERH - Position Difference Period Hold Register */
/*! @{ */

#define ENC_POSDPERH_POSDPERH_MASK               (0xFFFFU)
#define ENC_POSDPERH_POSDPERH_SHIFT              (0U)
/*! POSDPERH - Position difference period hold
 */
#define ENC_POSDPERH_POSDPERH(x)                 (((uint16_t)(((uint16_t)(x)) << ENC_POSDPERH_POSDPERH_SHIFT)) & ENC_POSDPERH_POSDPERH_MASK)
/*! @} */

/*! @name CTRL3 - Control 3 Register */
/*! @{ */

#define ENC_CTRL3_PMEN_MASK                      (0x1U)
#define ENC_CTRL3_PMEN_SHIFT                     (0U)
/*! PMEN - Period measurement function enable
 *  0b0..Period measurement functions are not used. POSD is loaded to POSDH and then cleared whenever POSD, UPOS, LPOS, or REV is read.
 *  0b1..Period measurement functions are used. POSD is loaded to POSDH and then cleared only when POSD is read.
 */
#define ENC_CTRL3_PMEN(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_CTRL3_PMEN_SHIFT)) & ENC_CTRL3_PMEN_MASK)

#define ENC_CTRL3_PRSC_MASK                      (0xF0U)
#define ENC_CTRL3_PRSC_SHIFT                     (4U)
/*! PRSC - Prescaler
 */
#define ENC_CTRL3_PRSC(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_CTRL3_PRSC_SHIFT)) & ENC_CTRL3_PRSC_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group ENC_Register_Masks */


/* ENC - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral ENC0 base address */
  #define ENC0_BASE                                (0x500C4000u)
  /** Peripheral ENC0 base address */
  #define ENC0_BASE_NS                             (0x400C4000u)
  /** Peripheral ENC0 base pointer */
  #define ENC0                                     ((ENC_Type *)ENC0_BASE)
  /** Peripheral ENC0 base pointer */
  #define ENC0_NS                                  ((ENC_Type *)ENC0_BASE_NS)
  /** Peripheral ENC1 base address */
  #define ENC1_BASE                                (0x500C6000u)
  /** Peripheral ENC1 base address */
  #define ENC1_BASE_NS                             (0x400C6000u)
  /** Peripheral ENC1 base pointer */
  #define ENC1                                     ((ENC_Type *)ENC1_BASE)
  /** Peripheral ENC1 base pointer */
  #define ENC1_NS                                  ((ENC_Type *)ENC1_BASE_NS)
  /** Array initializer of ENC peripheral base addresses */
  #define ENC_BASE_ADDRS                           { ENC0_BASE, ENC1_BASE }
  /** Array initializer of ENC peripheral base pointers */
  #define ENC_BASE_PTRS                            { ENC0, ENC1 }
  /** Array initializer of ENC peripheral base addresses */
  #define ENC_BASE_ADDRS_NS                        { ENC0_BASE_NS, ENC1_BASE_NS }
  /** Array initializer of ENC peripheral base pointers */
  #define ENC_BASE_PTRS_NS                         { ENC0_NS, ENC1_NS }
#else
  /** Peripheral ENC0 base address */
  #define ENC0_BASE                                (0x400C4000u)
  /** Peripheral ENC0 base pointer */
  #define ENC0                                     ((ENC_Type *)ENC0_BASE)
  /** Peripheral ENC1 base address */
  #define ENC1_BASE                                (0x400C6000u)
  /** Peripheral ENC1 base pointer */
  #define ENC1                                     ((ENC_Type *)ENC1_BASE)
  /** Array initializer of ENC peripheral base addresses */
  #define ENC_BASE_ADDRS                           { ENC0_BASE, ENC1_BASE }
  /** Array initializer of ENC peripheral base pointers */
  #define ENC_BASE_PTRS                            { ENC0, ENC1 }
#endif
/** Interrupt vectors for the ENC peripheral type */
#define ENC_COMPARE_IRQS                         { ENC0_COMPARE_IRQn, ENC1_COMPARE_IRQn }
#define ENC_HOME_IRQS                            { ENC0_HOME_IRQn, ENC1_HOME_IRQn }
#define ENC_WDOG_IRQS                            { ENC0_WDG_IRQn, ENC1_WDG_IRQn }
#define ENC_INDEX_IRQS                           { ENC0_IDX_IRQn, ENC1_IDX_IRQn }

/*!
 * @}
 */ /* end of group ENC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- FLASH Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup FLASH_Peripheral_Access_Layer FLASH Peripheral Access Layer
 * @{
 */

/** FLASH - Register Layout Typedef */
typedef struct {
  __O  uint32_t CMD;                               /**< Command, offset: 0x0 */
  __O  uint32_t EVENT;                             /**< Event, offset: 0x4 */
       uint8_t RESERVED_0[8];
  __IO uint32_t STARTA;                            /**< Start address for next flash command, offset: 0x10 */
  __IO uint32_t STOPA;                             /**< End address for next flash command, offset: 0x14 */
       uint8_t RESERVED_1[104];
  __IO uint32_t DATAW[4];                          /**< Data register, array offset: 0x80, array step: 0x4 */
       uint8_t RESERVED_2[3912];
  __O  uint32_t INTEN_CLR;                         /**< Clear interrupt enables, offset: 0xFD8 */
  __O  uint32_t INTEN_SET;                         /**< Set interrupt enables, offset: 0xFDC */
  __I  uint32_t INTSTAT;                           /**< Interrupt status, offset: 0xFE0 */
  __I  uint32_t INTEN;                             /**< Interrupt enable, offset: 0xFE4 */
  __O  uint32_t INTSTAT_CLR;                       /**< Clear interrupt status, offset: 0xFE8 */
  __O  uint32_t INTSTAT_SET;                       /**< Set interrupt status, offset: 0xFEC */
       uint8_t RESERVED_3[12];
  __I  uint32_t MODULE_ID;                         /**< Module identification, offset: 0xFFC */
} FLASH_Type;

/* ----------------------------------------------------------------------------
   -- FLASH Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup FLASH_Register_Masks FLASH Register Masks
 * @{
 */

/*! @name CMD - Command */
/*! @{ */

#define FLASH_CMD_CMD_MASK                       (0xFFFFFFFFU)
#define FLASH_CMD_CMD_SHIFT                      (0U)
/*! CMD - command register.
 */
#define FLASH_CMD_CMD(x)                         (((uint32_t)(((uint32_t)(x)) << FLASH_CMD_CMD_SHIFT)) & FLASH_CMD_CMD_MASK)
/*! @} */

/*! @name EVENT - Event */
/*! @{ */

#define FLASH_EVENT_RST_MASK                     (0x1U)
#define FLASH_EVENT_RST_SHIFT                    (0U)
/*! RST - When bit is set, the controller and flash are reset.
 */
#define FLASH_EVENT_RST(x)                       (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_RST_SHIFT)) & FLASH_EVENT_RST_MASK)

#define FLASH_EVENT_WAKEUP_MASK                  (0x2U)
#define FLASH_EVENT_WAKEUP_SHIFT                 (1U)
/*! WAKEUP - When bit is set, the controller wakes up from whatever low power or powerdown mode was active.
 */
#define FLASH_EVENT_WAKEUP(x)                    (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_WAKEUP_SHIFT)) & FLASH_EVENT_WAKEUP_MASK)

#define FLASH_EVENT_ABORT_MASK                   (0x4U)
#define FLASH_EVENT_ABORT_SHIFT                  (2U)
/*! ABORT - When bit is set, a running program/erase command is aborted.
 */
#define FLASH_EVENT_ABORT(x)                     (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_ABORT_SHIFT)) & FLASH_EVENT_ABORT_MASK)
/*! @} */

/*! @name STARTA - Start address for next flash command */
/*! @{ */

#define FLASH_STARTA_STARTA_MASK                 (0x3FFFU)
#define FLASH_STARTA_STARTA_SHIFT                (0U)
/*! STARTA - Address / Start address for commands that take an address (range) as a parameter.
 */
#define FLASH_STARTA_STARTA(x)                   (((uint32_t)(((uint32_t)(x)) << FLASH_STARTA_STARTA_SHIFT)) & FLASH_STARTA_STARTA_MASK)
/*! @} */

/*! @name STOPA - End address for next flash command */
/*! @{ */

#define FLASH_STOPA_STOPA_MASK                   (0x3FFFFU)
#define FLASH_STOPA_STOPA_SHIFT                  (0U)
/*! STOPA - Stop address for commands that take an address range as a parameter (the word specified
 *    by STOPA is included in the address range).
 */
#define FLASH_STOPA_STOPA(x)                     (((uint32_t)(((uint32_t)(x)) << FLASH_STOPA_STOPA_SHIFT)) & FLASH_STOPA_STOPA_MASK)
/*! @} */

/*! @name DATAW - Data register */
/*! @{ */

#define FLASH_DATAW_DATAW_MASK                   (0xFFFFFFFFU)
#define FLASH_DATAW_DATAW_SHIFT                  (0U)
/*! DATAW - Memory data, or command parameter, or command result.
 */
#define FLASH_DATAW_DATAW(x)                     (((uint32_t)(((uint32_t)(x)) << FLASH_DATAW_DATAW_SHIFT)) & FLASH_DATAW_DATAW_MASK)
/*! @} */

/* The count of FLASH_DATAW */
#define FLASH_DATAW_COUNT                        (4U)

/*! @name INTEN_CLR - Clear interrupt enables */
/*! @{ */

#define FLASH_INTEN_CLR_FAIL_MASK                (0x1U)
#define FLASH_INTEN_CLR_FAIL_SHIFT               (0U)
/*! FAIL - Clears the fail interrupt.
 */
#define FLASH_INTEN_CLR_FAIL(x)                  (((uint32_t)(((uint32_t)(x)) << FLASH_INTEN_CLR_FAIL_SHIFT)) & FLASH_INTEN_CLR_FAIL_MASK)

#define FLASH_INTEN_CLR_ERR_MASK                 (0x2U)
#define FLASH_INTEN_CLR_ERR_SHIFT                (1U)
/*! ERR - Clears the error interrupt.
 */
#define FLASH_INTEN_CLR_ERR(x)                   (((uint32_t)(((uint32_t)(x)) << FLASH_INTEN_CLR_ERR_SHIFT)) & FLASH_INTEN_CLR_ERR_MASK)

#define FLASH_INTEN_CLR_DONE_MASK                (0x4U)
#define FLASH_INTEN_CLR_DONE_SHIFT               (2U)
/*! DONE - Clears the done interrupt.
 */
#define FLASH_INTEN_CLR_DONE(x)                  (((uint32_t)(((uint32_t)(x)) << FLASH_INTEN_CLR_DONE_SHIFT)) & FLASH_INTEN_CLR_DONE_MASK)

#define FLASH_INTEN_CLR_ECC_ERR_MASK             (0x8U)
#define FLASH_INTEN_CLR_ECC_ERR_SHIFT            (3U)
/*! ECC_ERR - Clears the ECC error interrupt.
 */
#define FLASH_INTEN_CLR_ECC_ERR(x)               (((uint32_t)(((uint32_t)(x)) << FLASH_INTEN_CLR_ECC_ERR_SHIFT)) & FLASH_INTEN_CLR_ECC_ERR_MASK)
/*! @} */

/*! @name INTEN_SET - Set interrupt enables */
/*! @{ */

#define FLASH_INTEN_SET_FAIL_MASK                (0x1U)
#define FLASH_INTEN_SET_FAIL_SHIFT               (0U)
/*! FAIL - Sets Fail interrupt.
 */
#define FLASH_INTEN_SET_FAIL(x)                  (((uint32_t)(((uint32_t)(x)) << FLASH_INTEN_SET_FAIL_SHIFT)) & FLASH_INTEN_SET_FAIL_MASK)

#define FLASH_INTEN_SET_ERR_MASK                 (0x2U)
#define FLASH_INTEN_SET_ERR_SHIFT                (1U)
/*! ERR - Sets error interrupt
 */
#define FLASH_INTEN_SET_ERR(x)                   (((uint32_t)(((uint32_t)(x)) << FLASH_INTEN_SET_ERR_SHIFT)) & FLASH_INTEN_SET_ERR_MASK)

#define FLASH_INTEN_SET_DONE_MASK                (0x4U)
#define FLASH_INTEN_SET_DONE_SHIFT               (2U)
/*! DONE - Sets done interrupt.
 */
#define FLASH_INTEN_SET_DONE(x)                  (((uint32_t)(((uint32_t)(x)) << FLASH_INTEN_SET_DONE_SHIFT)) & FLASH_INTEN_SET_DONE_MASK)

#define FLASH_INTEN_SET_ECC_ERR_MASK             (0x8U)
#define FLASH_INTEN_SET_ECC_ERR_SHIFT            (3U)
/*! ECC_ERR - Sets ECC error interrupt.
 */
#define FLASH_INTEN_SET_ECC_ERR(x)               (((uint32_t)(((uint32_t)(x)) << FLASH_INTEN_SET_ECC_ERR_SHIFT)) & FLASH_INTEN_SET_ECC_ERR_MASK)
/*! @} */

/*! @name INTSTAT - Interrupt status */
/*! @{ */

#define FLASH_INTSTAT_FAIL_MASK                  (0x1U)
#define FLASH_INTSTAT_FAIL_SHIFT                 (0U)
/*! FAIL - This status bit is set if execution of a (legal) command failed.
 */
#define FLASH_INTSTAT_FAIL(x)                    (((uint32_t)(((uint32_t)(x)) << FLASH_INTSTAT_FAIL_SHIFT)) & FLASH_INTSTAT_FAIL_MASK)

#define FLASH_INTSTAT_ERR_MASK                   (0x2U)
#define FLASH_INTSTAT_ERR_SHIFT                  (1U)
/*! ERR - This status bit is set if execution of an illegal command is detected.
 */
#define FLASH_INTSTAT_ERR(x)                     (((uint32_t)(((uint32_t)(x)) << FLASH_INTSTAT_ERR_SHIFT)) & FLASH_INTSTAT_ERR_MASK)

#define FLASH_INTSTAT_DONE_MASK                  (0x4U)
#define FLASH_INTSTAT_DONE_SHIFT                 (2U)
/*! DONE - This status bit is set at the end of command execution.
 */
#define FLASH_INTSTAT_DONE(x)                    (((uint32_t)(((uint32_t)(x)) << FLASH_INTSTAT_DONE_SHIFT)) & FLASH_INTSTAT_DONE_MASK)

#define FLASH_INTSTAT_ECC_ERR_MASK               (0x8U)
#define FLASH_INTSTAT_ECC_ERR_SHIFT              (3U)
/*! ECC_ERR - This status bit is set if, during a memory read operation (either a user-requested
 *    read, or a speculative read, or reads performed by a controller command), a correctable or
 *    uncorrectable error is detected by ECC decoding logic.
 */
#define FLASH_INTSTAT_ECC_ERR(x)                 (((uint32_t)(((uint32_t)(x)) << FLASH_INTSTAT_ECC_ERR_SHIFT)) & FLASH_INTSTAT_ECC_ERR_MASK)
/*! @} */

/*! @name INTEN - Interrupt enable */
/*! @{ */

#define FLASH_INTEN_FAIL_MASK                    (0x1U)
#define FLASH_INTEN_FAIL_SHIFT                   (0U)
/*! FAIL - Enables fail interrupt.
 */
#define FLASH_INTEN_FAIL(x)                      (((uint32_t)(((uint32_t)(x)) << FLASH_INTEN_FAIL_SHIFT)) & FLASH_INTEN_FAIL_MASK)

#define FLASH_INTEN_ERR_MASK                     (0x2U)
#define FLASH_INTEN_ERR_SHIFT                    (1U)
/*! ERR - Enables error interrupt.
 */
#define FLASH_INTEN_ERR(x)                       (((uint32_t)(((uint32_t)(x)) << FLASH_INTEN_ERR_SHIFT)) & FLASH_INTEN_ERR_MASK)

#define FLASH_INTEN_DONE_MASK                    (0x4U)
#define FLASH_INTEN_DONE_SHIFT                   (2U)
/*! DONE - Enables done interrupt.
 */
#define FLASH_INTEN_DONE(x)                      (((uint32_t)(((uint32_t)(x)) << FLASH_INTEN_DONE_SHIFT)) & FLASH_INTEN_DONE_MASK)

#define FLASH_INTEN_ECC_ERR_MASK                 (0x8U)
#define FLASH_INTEN_ECC_ERR_SHIFT                (3U)
/*! ECC_ERR - Enables ECC error interrupt.
 */
#define FLASH_INTEN_ECC_ERR(x)                   (((uint32_t)(((uint32_t)(x)) << FLASH_INTEN_ECC_ERR_SHIFT)) & FLASH_INTEN_ECC_ERR_MASK)
/*! @} */

/*! @name INTSTAT_CLR - Clear interrupt status */
/*! @{ */

#define FLASH_INTSTAT_CLR_FAIL_MASK              (0x1U)
#define FLASH_INTSTAT_CLR_FAIL_SHIFT             (0U)
/*! FAIL - Clears fail interrupt status.
 */
#define FLASH_INTSTAT_CLR_FAIL(x)                (((uint32_t)(((uint32_t)(x)) << FLASH_INTSTAT_CLR_FAIL_SHIFT)) & FLASH_INTSTAT_CLR_FAIL_MASK)

#define FLASH_INTSTAT_CLR_ERR_MASK               (0x2U)
#define FLASH_INTSTAT_CLR_ERR_SHIFT              (1U)
/*! ERR - Clears error interrupt status.
 */
#define FLASH_INTSTAT_CLR_ERR(x)                 (((uint32_t)(((uint32_t)(x)) << FLASH_INTSTAT_CLR_ERR_SHIFT)) & FLASH_INTSTAT_CLR_ERR_MASK)

#define FLASH_INTSTAT_CLR_DONE_MASK              (0x4U)
#define FLASH_INTSTAT_CLR_DONE_SHIFT             (2U)
/*! DONE - Clears done interrupt status.
 */
#define FLASH_INTSTAT_CLR_DONE(x)                (((uint32_t)(((uint32_t)(x)) << FLASH_INTSTAT_CLR_DONE_SHIFT)) & FLASH_INTSTAT_CLR_DONE_MASK)

#define FLASH_INTSTAT_CLR_ECC_ERR_MASK           (0x8U)
#define FLASH_INTSTAT_CLR_ECC_ERR_SHIFT          (3U)
/*! ECC_ERR - Clears ECC error interrupt status.
 */
#define FLASH_INTSTAT_CLR_ECC_ERR(x)             (((uint32_t)(((uint32_t)(x)) << FLASH_INTSTAT_CLR_ECC_ERR_SHIFT)) & FLASH_INTSTAT_CLR_ECC_ERR_MASK)
/*! @} */

/*! @name INTSTAT_SET - Set interrupt status */
/*! @{ */

#define FLASH_INTSTAT_SET_FAIL_MASK              (0x1U)
#define FLASH_INTSTAT_SET_FAIL_SHIFT             (0U)
/*! FAIL - Sets fail interrupt status.
 */
#define FLASH_INTSTAT_SET_FAIL(x)                (((uint32_t)(((uint32_t)(x)) << FLASH_INTSTAT_SET_FAIL_SHIFT)) & FLASH_INTSTAT_SET_FAIL_MASK)

#define FLASH_INTSTAT_SET_ERR_MASK               (0x2U)
#define FLASH_INTSTAT_SET_ERR_SHIFT              (1U)
/*! ERR - Sets error interrupt status.
 */
#define FLASH_INTSTAT_SET_ERR(x)                 (((uint32_t)(((uint32_t)(x)) << FLASH_INTSTAT_SET_ERR_SHIFT)) & FLASH_INTSTAT_SET_ERR_MASK)

#define FLASH_INTSTAT_SET_DONE_MASK              (0x4U)
#define FLASH_INTSTAT_SET_DONE_SHIFT             (2U)
/*! DONE - Sets done interrupt status.
 */
#define FLASH_INTSTAT_SET_DONE(x)                (((uint32_t)(((uint32_t)(x)) << FLASH_INTSTAT_SET_DONE_SHIFT)) & FLASH_INTSTAT_SET_DONE_MASK)

#define FLASH_INTSTAT_SET_ECC_ERR_MASK           (0x8U)
#define FLASH_INTSTAT_SET_ECC_ERR_SHIFT          (3U)
/*! ECC_ERR - Sets ECC error interrupt status.
 */
#define FLASH_INTSTAT_SET_ECC_ERR(x)             (((uint32_t)(((uint32_t)(x)) << FLASH_INTSTAT_SET_ECC_ERR_SHIFT)) & FLASH_INTSTAT_SET_ECC_ERR_MASK)
/*! @} */

/*! @name MODULE_ID - Module identification */
/*! @{ */

#define FLASH_MODULE_ID_MINOR_REV_MASK           (0xF00U)
#define FLASH_MODULE_ID_MINOR_REV_SHIFT          (8U)
/*! MINOR_REV - Minor revision i.
 */
#define FLASH_MODULE_ID_MINOR_REV(x)             (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_MINOR_REV_SHIFT)) & FLASH_MODULE_ID_MINOR_REV_MASK)

#define FLASH_MODULE_ID_MAJOR_REV_MASK           (0xF000U)
#define FLASH_MODULE_ID_MAJOR_REV_SHIFT          (12U)
/*! MAJOR_REV - Major revision i.
 */
#define FLASH_MODULE_ID_MAJOR_REV(x)             (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_MAJOR_REV_SHIFT)) & FLASH_MODULE_ID_MAJOR_REV_MASK)

#define FLASH_MODULE_ID_ID_MASK                  (0xFFFF0000U)
#define FLASH_MODULE_ID_ID_SHIFT                 (16U)
/*! ID - Identifier.
 */
#define FLASH_MODULE_ID_ID(x)                    (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_ID_SHIFT)) & FLASH_MODULE_ID_ID_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group FLASH_Register_Masks */


/* FLASH - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral FLASH base address */
  #define FLASH_BASE                               (0x50034000u)
  /** Peripheral FLASH base address */
  #define FLASH_BASE_NS                            (0x40034000u)
  /** Peripheral FLASH base pointer */
  #define FLASH                                    ((FLASH_Type *)FLASH_BASE)
  /** Peripheral FLASH base pointer */
  #define FLASH_NS                                 ((FLASH_Type *)FLASH_BASE_NS)
  /** Array initializer of FLASH peripheral base addresses */
  #define FLASH_BASE_ADDRS                         { FLASH_BASE }
  /** Array initializer of FLASH peripheral base pointers */
  #define FLASH_BASE_PTRS                          { FLASH }
  /** Array initializer of FLASH peripheral base addresses */
  #define FLASH_BASE_ADDRS_NS                      { FLASH_BASE_NS }
  /** Array initializer of FLASH peripheral base pointers */
  #define FLASH_BASE_PTRS_NS                       { FLASH_NS }
#else
  /** Peripheral FLASH base address */
  #define FLASH_BASE                               (0x40034000u)
  /** Peripheral FLASH base pointer */
  #define FLASH                                    ((FLASH_Type *)FLASH_BASE)
  /** Array initializer of FLASH peripheral base addresses */
  #define FLASH_BASE_ADDRS                         { FLASH_BASE }
  /** Array initializer of FLASH peripheral base pointers */
  #define FLASH_BASE_PTRS                          { FLASH }
#endif

/*!
 * @}
 */ /* end of group FLASH_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- FLEXCOMM Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer
 * @{
 */

/** FLEXCOMM - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[4088];
  __IO uint32_t PSELID;                            /**< Peripheral Select and Flexcomm module ID, offset: 0xFF8 */
  __I  uint32_t PID;                               /**< Peripheral Identification, offset: 0xFFC */
} FLEXCOMM_Type;

/* ----------------------------------------------------------------------------
   -- FLEXCOMM Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks
 * @{
 */

/*! @name PSELID - Peripheral Select and Flexcomm module ID */
/*! @{ */

#define FLEXCOMM_PSELID_PERSEL_MASK              (0x7U)
#define FLEXCOMM_PSELID_PERSEL_SHIFT             (0U)
/*! PERSEL - Peripheral Select
 *  0b000..No peripheral selected.
 *  0b001..USART function selected
 *  0b010..SPI function selected
 *  0b011..I2C
 *  0b100..I2S Transmit
 *  0b101..I2S Receive
 *  0b110..Reserved
 *  0b111..Reserved
 */
#define FLEXCOMM_PSELID_PERSEL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK)

#define FLEXCOMM_PSELID_LOCK_MASK                (0x8U)
#define FLEXCOMM_PSELID_LOCK_SHIFT               (3U)
/*! LOCK - Lock the peripheral select
 *  0b0..Peripheral select can be changed by software.
 *  0b1..Peripheral select is locked and cannot be changed until this Flexcomm module or the entire device is reset.
 */
#define FLEXCOMM_PSELID_LOCK(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK)

#define FLEXCOMM_PSELID_USARTPRESENT_MASK        (0x10U)
#define FLEXCOMM_PSELID_USARTPRESENT_SHIFT       (4U)
/*! USARTPRESENT - USART present indicator
 *  0b0..This Flexcomm module does not include the USART function.
 *  0b1..This Flexcomm module includes the USART function.
 */
#define FLEXCOMM_PSELID_USARTPRESENT(x)          (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK)

#define FLEXCOMM_PSELID_SPIPRESENT_MASK          (0x20U)
#define FLEXCOMM_PSELID_SPIPRESENT_SHIFT         (5U)
/*! SPIPRESENT - SPI present indicator
 *  0b0..This Flexcomm module does not include the SPI function.
 *  0b1..This Flexcomm module includes the SPI function.
 */
#define FLEXCOMM_PSELID_SPIPRESENT(x)            (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK)

#define FLEXCOMM_PSELID_I2CPRESENT_MASK          (0x40U)
#define FLEXCOMM_PSELID_I2CPRESENT_SHIFT         (6U)
/*! I2CPRESENT - I2C present indicator
 *  0b0..I2C Not Present
 *  0b1..I2C Present
 */
#define FLEXCOMM_PSELID_I2CPRESENT(x)            (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK)

#define FLEXCOMM_PSELID_I2SPRESENT_MASK          (0x80U)
#define FLEXCOMM_PSELID_I2SPRESENT_SHIFT         (7U)
/*! I2SPRESENT - I2S Present
 *  0b0..I2S Not Present
 *  0b1..I2S Present
 */
#define FLEXCOMM_PSELID_I2SPRESENT(x)            (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK)

#define FLEXCOMM_PSELID_ID_MASK                  (0xFFFFF000U)
#define FLEXCOMM_PSELID_ID_SHIFT                 (12U)
/*! ID - Flexcomm ID
 */
#define FLEXCOMM_PSELID_ID(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK)
/*! @} */

/*! @name PID - Peripheral Identification */
/*! @{ */

#define FLEXCOMM_PID_Minor_Rev_MASK              (0xF00U)
#define FLEXCOMM_PID_Minor_Rev_SHIFT             (8U)
/*! Minor_Rev - Minor revision of module implementation
 */
#define FLEXCOMM_PID_Minor_Rev(x)                (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Minor_Rev_SHIFT)) & FLEXCOMM_PID_Minor_Rev_MASK)

#define FLEXCOMM_PID_Major_Rev_MASK              (0xF000U)
#define FLEXCOMM_PID_Major_Rev_SHIFT             (12U)
/*! Major_Rev - Major revision of module implementation
 */
#define FLEXCOMM_PID_Major_Rev(x)                (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Major_Rev_SHIFT)) & FLEXCOMM_PID_Major_Rev_MASK)

#define FLEXCOMM_PID_ID_MASK                     (0xFFFF0000U)
#define FLEXCOMM_PID_ID_SHIFT                    (16U)
/*! ID - Module identifier for the selected function
 */
#define FLEXCOMM_PID_ID(x)                       (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group FLEXCOMM_Register_Masks */


/* FLEXCOMM - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral FLEXCOMM0 base address */
  #define FLEXCOMM0_BASE                           (0x50086000u)
  /** Peripheral FLEXCOMM0 base address */
  #define FLEXCOMM0_BASE_NS                        (0x40086000u)
  /** Peripheral FLEXCOMM0 base pointer */
  #define FLEXCOMM0                                ((FLEXCOMM_Type *)FLEXCOMM0_BASE)
  /** Peripheral FLEXCOMM0 base pointer */
  #define FLEXCOMM0_NS                             ((FLEXCOMM_Type *)FLEXCOMM0_BASE_NS)
  /** Peripheral FLEXCOMM1 base address */
  #define FLEXCOMM1_BASE                           (0x50087000u)
  /** Peripheral FLEXCOMM1 base address */
  #define FLEXCOMM1_BASE_NS                        (0x40087000u)
  /** Peripheral FLEXCOMM1 base pointer */
  #define FLEXCOMM1                                ((FLEXCOMM_Type *)FLEXCOMM1_BASE)
  /** Peripheral FLEXCOMM1 base pointer */
  #define FLEXCOMM1_NS                             ((FLEXCOMM_Type *)FLEXCOMM1_BASE_NS)
  /** Peripheral FLEXCOMM2 base address */
  #define FLEXCOMM2_BASE                           (0x50088000u)
  /** Peripheral FLEXCOMM2 base address */
  #define FLEXCOMM2_BASE_NS                        (0x40088000u)
  /** Peripheral FLEXCOMM2 base pointer */
  #define FLEXCOMM2                                ((FLEXCOMM_Type *)FLEXCOMM2_BASE)
  /** Peripheral FLEXCOMM2 base pointer */
  #define FLEXCOMM2_NS                             ((FLEXCOMM_Type *)FLEXCOMM2_BASE_NS)
  /** Peripheral FLEXCOMM3 base address */
  #define FLEXCOMM3_BASE                           (0x50089000u)
  /** Peripheral FLEXCOMM3 base address */
  #define FLEXCOMM3_BASE_NS                        (0x40089000u)
  /** Peripheral FLEXCOMM3 base pointer */
  #define FLEXCOMM3                                ((FLEXCOMM_Type *)FLEXCOMM3_BASE)
  /** Peripheral FLEXCOMM3 base pointer */
  #define FLEXCOMM3_NS                             ((FLEXCOMM_Type *)FLEXCOMM3_BASE_NS)
  /** Peripheral FLEXCOMM4 base address */
  #define FLEXCOMM4_BASE                           (0x5008A000u)
  /** Peripheral FLEXCOMM4 base address */
  #define FLEXCOMM4_BASE_NS                        (0x4008A000u)
  /** Peripheral FLEXCOMM4 base pointer */
  #define FLEXCOMM4                                ((FLEXCOMM_Type *)FLEXCOMM4_BASE)
  /** Peripheral FLEXCOMM4 base pointer */
  #define FLEXCOMM4_NS                             ((FLEXCOMM_Type *)FLEXCOMM4_BASE_NS)
  /** Peripheral FLEXCOMM5 base address */
  #define FLEXCOMM5_BASE                           (0x50096000u)
  /** Peripheral FLEXCOMM5 base address */
  #define FLEXCOMM5_BASE_NS                        (0x40096000u)
  /** Peripheral FLEXCOMM5 base pointer */
  #define FLEXCOMM5                                ((FLEXCOMM_Type *)FLEXCOMM5_BASE)
  /** Peripheral FLEXCOMM5 base pointer */
  #define FLEXCOMM5_NS                             ((FLEXCOMM_Type *)FLEXCOMM5_BASE_NS)
  /** Peripheral FLEXCOMM6 base address */
  #define FLEXCOMM6_BASE                           (0x50097000u)
  /** Peripheral FLEXCOMM6 base address */
  #define FLEXCOMM6_BASE_NS                        (0x40097000u)
  /** Peripheral FLEXCOMM6 base pointer */
  #define FLEXCOMM6                                ((FLEXCOMM_Type *)FLEXCOMM6_BASE)
  /** Peripheral FLEXCOMM6 base pointer */
  #define FLEXCOMM6_NS                             ((FLEXCOMM_Type *)FLEXCOMM6_BASE_NS)
  /** Peripheral FLEXCOMM7 base address */
  #define FLEXCOMM7_BASE                           (0x50098000u)
  /** Peripheral FLEXCOMM7 base address */
  #define FLEXCOMM7_BASE_NS                        (0x40098000u)
  /** Peripheral FLEXCOMM7 base pointer */
  #define FLEXCOMM7                                ((FLEXCOMM_Type *)FLEXCOMM7_BASE)
  /** Peripheral FLEXCOMM7 base pointer */
  #define FLEXCOMM7_NS                             ((FLEXCOMM_Type *)FLEXCOMM7_BASE_NS)
  /** Peripheral FLEXCOMM8 base address */
  #define FLEXCOMM8_BASE                           (0x5009F000u)
  /** Peripheral FLEXCOMM8 base address */
  #define FLEXCOMM8_BASE_NS                        (0x4009F000u)
  /** Peripheral FLEXCOMM8 base pointer */
  #define FLEXCOMM8                                ((FLEXCOMM_Type *)FLEXCOMM8_BASE)
  /** Peripheral FLEXCOMM8 base pointer */
  #define FLEXCOMM8_NS                             ((FLEXCOMM_Type *)FLEXCOMM8_BASE_NS)
  /** Array initializer of FLEXCOMM peripheral base addresses */
  #define FLEXCOMM_BASE_ADDRS                      { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE }
  /** Array initializer of FLEXCOMM peripheral base pointers */
  #define FLEXCOMM_BASE_PTRS                       { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8 }
  /** Array initializer of FLEXCOMM peripheral base addresses */
  #define FLEXCOMM_BASE_ADDRS_NS                   { FLEXCOMM0_BASE_NS, FLEXCOMM1_BASE_NS, FLEXCOMM2_BASE_NS, FLEXCOMM3_BASE_NS, FLEXCOMM4_BASE_NS, FLEXCOMM5_BASE_NS, FLEXCOMM6_BASE_NS, FLEXCOMM7_BASE_NS, FLEXCOMM8_BASE_NS }
  /** Array initializer of FLEXCOMM peripheral base pointers */
  #define FLEXCOMM_BASE_PTRS_NS                    { FLEXCOMM0_NS, FLEXCOMM1_NS, FLEXCOMM2_NS, FLEXCOMM3_NS, FLEXCOMM4_NS, FLEXCOMM5_NS, FLEXCOMM6_NS, FLEXCOMM7_NS, FLEXCOMM8_NS }
#else
  /** Peripheral FLEXCOMM0 base address */
  #define FLEXCOMM0_BASE                           (0x40086000u)
  /** Peripheral FLEXCOMM0 base pointer */
  #define FLEXCOMM0                                ((FLEXCOMM_Type *)FLEXCOMM0_BASE)
  /** Peripheral FLEXCOMM1 base address */
  #define FLEXCOMM1_BASE                           (0x40087000u)
  /** Peripheral FLEXCOMM1 base pointer */
  #define FLEXCOMM1                                ((FLEXCOMM_Type *)FLEXCOMM1_BASE)
  /** Peripheral FLEXCOMM2 base address */
  #define FLEXCOMM2_BASE                           (0x40088000u)
  /** Peripheral FLEXCOMM2 base pointer */
  #define FLEXCOMM2                                ((FLEXCOMM_Type *)FLEXCOMM2_BASE)
  /** Peripheral FLEXCOMM3 base address */
  #define FLEXCOMM3_BASE                           (0x40089000u)
  /** Peripheral FLEXCOMM3 base pointer */
  #define FLEXCOMM3                                ((FLEXCOMM_Type *)FLEXCOMM3_BASE)
  /** Peripheral FLEXCOMM4 base address */
  #define FLEXCOMM4_BASE                           (0x4008A000u)
  /** Peripheral FLEXCOMM4 base pointer */
  #define FLEXCOMM4                                ((FLEXCOMM_Type *)FLEXCOMM4_BASE)
  /** Peripheral FLEXCOMM5 base address */
  #define FLEXCOMM5_BASE                           (0x40096000u)
  /** Peripheral FLEXCOMM5 base pointer */
  #define FLEXCOMM5                                ((FLEXCOMM_Type *)FLEXCOMM5_BASE)
  /** Peripheral FLEXCOMM6 base address */
  #define FLEXCOMM6_BASE                           (0x40097000u)
  /** Peripheral FLEXCOMM6 base pointer */
  #define FLEXCOMM6                                ((FLEXCOMM_Type *)FLEXCOMM6_BASE)
  /** Peripheral FLEXCOMM7 base address */
  #define FLEXCOMM7_BASE                           (0x40098000u)
  /** Peripheral FLEXCOMM7 base pointer */
  #define FLEXCOMM7                                ((FLEXCOMM_Type *)FLEXCOMM7_BASE)
  /** Peripheral FLEXCOMM8 base address */
  #define FLEXCOMM8_BASE                           (0x4009F000u)
  /** Peripheral FLEXCOMM8 base pointer */
  #define FLEXCOMM8                                ((FLEXCOMM_Type *)FLEXCOMM8_BASE)
  /** Array initializer of FLEXCOMM peripheral base addresses */
  #define FLEXCOMM_BASE_ADDRS                      { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE }
  /** Array initializer of FLEXCOMM peripheral base pointers */
  #define FLEXCOMM_BASE_PTRS                       { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8 }
#endif
/** Interrupt vectors for the FLEXCOMM peripheral type */
#define FLEXCOMM_IRQS                            { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn }

/*!
 * @}
 */ /* end of group FLEXCOMM_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- FLEXSPI Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup FLEXSPI_Peripheral_Access_Layer FLEXSPI Peripheral Access Layer
 * @{
 */

/** FLEXSPI - Register Layout Typedef */
typedef struct {
  __IO uint32_t MCR0;                              /**< Module Control Register 0, offset: 0x0 */
  __IO uint32_t MCR1;                              /**< Module Control Register 1, offset: 0x4 */
  __IO uint32_t MCR2;                              /**< Module Control Register 2, offset: 0x8 */
  __IO uint32_t AHBCR;                             /**< AHB Bus Control Register, offset: 0xC */
  __IO uint32_t INTEN;                             /**< Interrupt Enable Register, offset: 0x10 */
  __IO uint32_t INTR;                              /**< Interrupt Register, offset: 0x14 */
  __I  uint32_t LUTKEY;                            /**< LUT Key Register, offset: 0x18 */
  __IO uint32_t LUTCR;                             /**< LUT Control Register, offset: 0x1C */
  __IO uint32_t AHBRXBUFCR0[8];                    /**< AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0, array offset: 0x20, array step: 0x4 */
       uint8_t RESERVED_0[32];
  __IO uint32_t FLSHCR0[2];                        /**< Flash Control Register 0, array offset: 0x60, array step: 0x4 */
       uint8_t RESERVED_1[8];
  __IO uint32_t FLSHCR1[2];                        /**< Flash Control Register 1, array offset: 0x70, array step: 0x4 */
       uint8_t RESERVED_2[8];
  __IO uint32_t FLSHCR2[2];                        /**< Flash Control Register 2, array offset: 0x80, array step: 0x4 */
       uint8_t RESERVED_3[12];
  __IO uint32_t FLSHCR4;                           /**< Flash Control Register 4, offset: 0x94 */
       uint8_t RESERVED_4[8];
  __IO uint32_t IPCR0;                             /**< IP Control Register 0, offset: 0xA0 */
  __IO uint32_t IPCR1;                             /**< IP Control Register 1, offset: 0xA4 */
       uint8_t RESERVED_5[8];
  __IO uint32_t IPCMD;                             /**< IP Command Register, offset: 0xB0 */
  __IO uint32_t DLPR;                              /**< Data Learn Pattern Register, offset: 0xB4 */
  __IO uint32_t IPRXFCR;                           /**< IP RX FIFO Control Register, offset: 0xB8 */
  __IO uint32_t IPTXFCR;                           /**< IP TX FIFO Control Register, offset: 0xBC */
  __IO uint32_t DLLCR[2];                          /**< DLL Control Register 0, array offset: 0xC0, array step: 0x4 */
       uint8_t RESERVED_6[24];
  __I  uint32_t STS0;                              /**< Status Register 0, offset: 0xE0 */
  __I  uint32_t STS1;                              /**< Status Register 1, offset: 0xE4 */
  __I  uint32_t STS2;                              /**< Status Register 2, offset: 0xE8 */
  __I  uint32_t AHBSPNDSTS;                        /**< AHB Suspend Status Register, offset: 0xEC */
  __I  uint32_t IPRXFSTS;                          /**< IP RX FIFO Status Register, offset: 0xF0 */
  __I  uint32_t IPTXFSTS;                          /**< IP TX FIFO Status Register, offset: 0xF4 */
       uint8_t RESERVED_7[8];
  __I  uint32_t RFDR[32];                          /**< IP RX FIFO Data Register 0..IP RX FIFO Data Register 31, array offset: 0x100, array step: 0x4 */
  __O  uint32_t TFDR[32];                          /**< IP TX FIFO Data Register 0..IP TX FIFO Data Register 31, array offset: 0x180, array step: 0x4 */
  __IO uint32_t LUT[64];                           /**< LUT 0..LUT 63, array offset: 0x200, array step: 0x4 */
       uint8_t RESERVED_8[288];
  __IO uint32_t HADDRSTART;                        /**< HADDR REMAP START ADDR, offset: 0x420 */
  __IO uint32_t HADDREND;                          /**< HADDR REMAP END ADDR, offset: 0x424 */
  __IO uint32_t HADDROFFSET;                       /**< HADDR REMAP OFFSET, offset: 0x428 */
  __IO uint32_t IPEDCTRL;                          /**< IPED function control, offset: 0x42C */
       uint8_t RESERVED_9[208];
  __IO uint32_t IPEDCTXCTRL[2];                    /**< IPED context control 0..IPED context control 1, array offset: 0x500, array step: 0x4 */
       uint8_t RESERVED_10[24];
  __IO uint32_t IPEDCTX0IV0;                       /**< IPED context0 IV0, offset: 0x520 */
  __IO uint32_t IPEDCTX0IV1;                       /**< IPED context0 IV1, offset: 0x524 */
  __IO uint32_t IPEDCTX0START;                     /**< Start address of region 0, offset: 0x528 */
  __IO uint32_t IPEDCTX0END;                       /**< End address of region 0, offset: 0x52C */
  __IO uint32_t IPEDCTX0AAD0;                      /**< IPED context0 AAD0, offset: 0x530 */
  __IO uint32_t IPEDCTX0AAD1;                      /**< IPED context0 AAD1, offset: 0x534 */
       uint8_t RESERVED_11[8];
  __IO uint32_t IPEDCTX1IV0;                       /**< IPED context1 IV0, offset: 0x540 */
  __IO uint32_t IPEDCTX1IV1;                       /**< IPED context1 IV1, offset: 0x544 */
  __IO uint32_t IPEDCTX1START;                     /**< Start address of region 1, offset: 0x548 */
  __IO uint32_t IPEDCTX1END;                       /**< End address of region 1, offset: 0x54C */
  __IO uint32_t IPEDCTX1AAD0;                      /**< IPED context1 AAD0, offset: 0x550 */
  __IO uint32_t IPEDCTX1AAD1;                      /**< IPED context1 AAD1, offset: 0x554 */
       uint8_t RESERVED_12[8];
  __IO uint32_t IPEDCTX2IV0;                       /**< IPED context2 IV0, offset: 0x560 */
  __IO uint32_t IPEDCTX2IV1;                       /**< IPED context2 IV1, offset: 0x564 */
  __IO uint32_t IPEDCTX2START;                     /**< Start address of region 2, offset: 0x568 */
  __IO uint32_t IPEDCTX2END;                       /**< End address of region 2, offset: 0x56C */
  __IO uint32_t IPEDCTX2AAD0;                      /**< IPED context2 AAD0, offset: 0x570 */
  __IO uint32_t IPEDCTX2AAD1;                      /**< IPED context2 AAD1, offset: 0x574 */
       uint8_t RESERVED_13[8];
  __IO uint32_t IPEDCTX3IV0;                       /**< IPED context3 IV0, offset: 0x580 */
  __IO uint32_t IPEDCTX3IV1;                       /**< IPED context3 IV1, offset: 0x584 */
  __IO uint32_t IPEDCTX3START;                     /**< Start address of region 3, offset: 0x588 */
  __IO uint32_t IPEDCTX3END;                       /**< End address of region 3, offset: 0x58C */
  __IO uint32_t IPEDCTX3AAD0;                      /**< IPED context3 AAD0, offset: 0x590 */
  __IO uint32_t IPEDCTX3AAD1;                      /**< IPED context3 AAD1, offset: 0x594 */
} FLEXSPI_Type;

/* ----------------------------------------------------------------------------
   -- FLEXSPI Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup FLEXSPI_Register_Masks FLEXSPI Register Masks
 * @{
 */

/*! @name MCR0 - Module Control Register 0 */
/*! @{ */

#define FLEXSPI_MCR0_SWRESET_MASK                (0x1U)
#define FLEXSPI_MCR0_SWRESET_SHIFT               (0U)
/*! SWRESET - Software Reset
 */
#define FLEXSPI_MCR0_SWRESET(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK)

#define FLEXSPI_MCR0_MDIS_MASK                   (0x2U)
#define FLEXSPI_MCR0_MDIS_SHIFT                  (1U)
/*! MDIS - Module Disable
 */
#define FLEXSPI_MCR0_MDIS(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK)

#define FLEXSPI_MCR0_RXCLKSRC_MASK               (0x30U)
#define FLEXSPI_MCR0_RXCLKSRC_SHIFT              (4U)
/*! RXCLKSRC - Sample Clock source selection for Flash Reading
 *  0b00..Dummy Read strobe generated by FlexSPI Controller and loopback internally.
 *  0b01..Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad.
 *  0b10..SCLK output clock and loopback from SCLK pad
 *  0b11..Flash provided Read strobe and input from DQS pad
 */
#define FLEXSPI_MCR0_RXCLKSRC(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK)

#define FLEXSPI_MCR0_SERCLKDIV_MASK              (0x700U)
#define FLEXSPI_MCR0_SERCLKDIV_SHIFT             (8U)
/*! SERCLKDIV - Serial root clock
 *  0b000..Divided by 1
 *  0b001..Divided by 2
 *  0b010..Divided by 3
 *  0b011..Divided by 4
 *  0b100..Divided by 5
 *  0b101..Divided by 6
 *  0b110..Divided by 7
 *  0b111..Divided by 8
 */
#define FLEXSPI_MCR0_SERCLKDIV(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SERCLKDIV_SHIFT)) & FLEXSPI_MCR0_SERCLKDIV_MASK)

#define FLEXSPI_MCR0_HSEN_MASK                   (0x800U)
#define FLEXSPI_MCR0_HSEN_SHIFT                  (11U)
/*! HSEN - Half Speed Serial Flash access Enable.
 *  0b0..Disable divide by 2 of serial flash clock for half speed commands.
 *  0b1..Enable divide by 2 of serial flash clock for half speed commands.
 */
#define FLEXSPI_MCR0_HSEN(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK)

#define FLEXSPI_MCR0_DOZEEN_MASK                 (0x1000U)
#define FLEXSPI_MCR0_DOZEEN_SHIFT                (12U)
/*! DOZEEN - Doze mode enable bit
 *  0b0..Doze mode support disabled. AHB clock and serial clock will not be gated off when there is doze mode request from system.
 *  0b1..Doze mode support enabled. AHB clock and serial clock will be gated off when there is doze mode request from system.
 */
#define FLEXSPI_MCR0_DOZEEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK)

#define FLEXSPI_MCR0_SCKFREERUNEN_MASK           (0x4000U)
#define FLEXSPI_MCR0_SCKFREERUNEN_SHIFT          (14U)
/*! SCKFREERUNEN - This bit is used to force SCLK output free-running. For FPGA applications,
 *    external device may use SCLK as reference clock to its internal PLL. If SCLK free-running is
 *    enabled, data sampling with loopback clock from SCLK pad is not supported (MCR0[RXCLKSRC]=2).
 *  0b0..Disable.
 *  0b1..Enable.
 */
#define FLEXSPI_MCR0_SCKFREERUNEN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK)

#define FLEXSPI_MCR0_LEARNEN_MASK                (0x8000U)
#define FLEXSPI_MCR0_LEARNEN_SHIFT               (15U)
/*! LEARNEN - This bit is used to enable/disable data learning feature. When data learning is
 *    disabled, the sampling clock phase 0 is always used for RX data sampling even if LEARN instruction
 *    is correctly executed.
 *  0b0..Disable.
 *  0b1..Enable.
 */
#define FLEXSPI_MCR0_LEARNEN(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_LEARNEN_SHIFT)) & FLEXSPI_MCR0_LEARNEN_MASK)

#define FLEXSPI_MCR0_IPGRANTWAIT_MASK            (0xFF0000U)
#define FLEXSPI_MCR0_IPGRANTWAIT_SHIFT           (16U)
/*! IPGRANTWAIT - Timeout wait cycle for IP command grant.
 */
#define FLEXSPI_MCR0_IPGRANTWAIT(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK)

#define FLEXSPI_MCR0_AHBGRANTWAIT_MASK           (0xFF000000U)
#define FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT          (24U)
/*! AHBGRANTWAIT - Timeout wait cycle for AHB command grant.
 */
#define FLEXSPI_MCR0_AHBGRANTWAIT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK)
/*! @} */

/*! @name MCR1 - Module Control Register 1 */
/*! @{ */

#define FLEXSPI_MCR1_AHBBUSWAIT_MASK             (0xFFFFU)
#define FLEXSPI_MCR1_AHBBUSWAIT_SHIFT            (0U)
/*! AHBBUSWAIT - AHB Bus wait
 */
#define FLEXSPI_MCR1_AHBBUSWAIT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK)

#define FLEXSPI_MCR1_SEQWAIT_MASK                (0xFFFF0000U)
#define FLEXSPI_MCR1_SEQWAIT_SHIFT               (16U)
/*! SEQWAIT - Command Sequence Execution will timeout and abort after SEQWAIT * 1024 Serial Root
 *    Clock cycles. When sequence execution timeout occurs, there will be an interrupt generated
 *    (INTR[SEQTIMEOUT]) if this interrupt is enabled (INTEN[SEQTIMEOUTEN] is set 0x1) and AHB command is
 *    ignored by arbitrator.
 */
#define FLEXSPI_MCR1_SEQWAIT(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK)
/*! @} */

/*! @name MCR2 - Module Control Register 2 */
/*! @{ */

#define FLEXSPI_MCR2_CLRAHBBUFOPT_MASK           (0x800U)
#define FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT          (11U)
/*! CLRAHBBUFOPT - Clear AHB buffer
 *  0b0..AHB RX/TX Buffer will not be cleaned automatically when FlexSPI return Stop mode ACK.
 *  0b1..AHB RX/TX Buffer will be cleaned automatically when FlexSPI return Stop mode ACK.
 */
#define FLEXSPI_MCR2_CLRAHBBUFOPT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK)

#define FLEXSPI_MCR2_CLRLEARNPHASE_MASK          (0x4000U)
#define FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT         (14U)
/*! CLRLEARNPHASE - The sampling clock phase selection will be reset to phase 0 when this bit is
 *    written with 0x1. This bit will be auto-cleared immediately.
 */
#define FLEXSPI_MCR2_CLRLEARNPHASE(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FLEXSPI_MCR2_CLRLEARNPHASE_MASK)

#define FLEXSPI_MCR2_SAMEDEVICEEN_MASK           (0x8000U)
#define FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT          (15U)
/*! SAMEDEVICEEN - All external devices are same devices (both in types and size) for A1/A2/B1/B2.
 *  0b0..In Individual mode, FLSHA1CRx/FLSHA2CRx register setting will be applied to Flash A1/A2 separately. Disabled.
 *  0b1..FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register settings will be applied to Flash A1/A2. FLSHA2CRx will be ignored.
 */
#define FLEXSPI_MCR2_SAMEDEVICEEN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK)

#define FLEXSPI_MCR2_RESUMEWAIT_MASK             (0xFF000000U)
#define FLEXSPI_MCR2_RESUMEWAIT_SHIFT            (24U)
/*! RESUMEWAIT - Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed.
 */
#define FLEXSPI_MCR2_RESUMEWAIT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK)
/*! @} */

/*! @name AHBCR - AHB Bus Control Register */
/*! @{ */

#define FLEXSPI_AHBCR_CLRAHBRXBUF_MASK           (0x2U)
#define FLEXSPI_AHBCR_CLRAHBRXBUF_SHIFT          (1U)
/*! CLRAHBRXBUF - Clear the status/pointers of AHB RX Buffer. Auto-cleared.
 */
#define FLEXSPI_AHBCR_CLRAHBRXBUF(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CLRAHBRXBUF_SHIFT)) & FLEXSPI_AHBCR_CLRAHBRXBUF_MASK)

#define FLEXSPI_AHBCR_CLRAHBTXBUF_MASK           (0x4U)
#define FLEXSPI_AHBCR_CLRAHBTXBUF_SHIFT          (2U)
/*! CLRAHBTXBUF - Clear the status/pointers of AHB TX Buffer. Auto-cleared.
 */
#define FLEXSPI_AHBCR_CLRAHBTXBUF(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CLRAHBTXBUF_SHIFT)) & FLEXSPI_AHBCR_CLRAHBTXBUF_MASK)

#define FLEXSPI_AHBCR_CACHABLEEN_MASK            (0x8U)
#define FLEXSPI_AHBCR_CACHABLEEN_SHIFT           (3U)
/*! CACHABLEEN - Enable AHB bus cachable read access support.
 *  0b0..Disabled. When there is AHB bus cachable read access, FlexSPI will not check whether it hit AHB TX Buffer.
 *  0b1..Enabled. When there is AHB bus cachable read access, FlexSPI will check whether it hit AHB TX Buffer first.
 */
#define FLEXSPI_AHBCR_CACHABLEEN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK)

#define FLEXSPI_AHBCR_BUFFERABLEEN_MASK          (0x10U)
#define FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT         (4U)
/*! BUFFERABLEEN - Enable AHB bus bufferable write access support.
 *  0b0..Disabled. For all AHB write access (no matter bufferable or non-bufferable ), FlexSPI will return AHB Bus
 *       ready after all data is transmitted to External device and AHB command finished.
 *  0b1..Enabled. For AHB bufferable write access, FlexSPI will return AHB Bus ready when the AHB command is
 *       granted by arbitrator and will not wait for AHB command finished.
 */
#define FLEXSPI_AHBCR_BUFFERABLEEN(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK)

#define FLEXSPI_AHBCR_PREFETCHEN_MASK            (0x20U)
#define FLEXSPI_AHBCR_PREFETCHEN_SHIFT           (5U)
/*! PREFETCHEN - AHB Read Prefetch Enable.
 */
#define FLEXSPI_AHBCR_PREFETCHEN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK)

#define FLEXSPI_AHBCR_READADDROPT_MASK           (0x40U)
#define FLEXSPI_AHBCR_READADDROPT_SHIFT          (6U)
/*! READADDROPT - AHB Read Address option bit. This option bit is intend to remove AHB burst start address alignment limitation.
 *  0b0..There is AHB read burst start address alignment limitation when flash is accessed in flash is word-addressable.
 *  0b1..There is no AHB read burst start address alignment limitation. FlexSPI will fetch more data than AHB
 *       burst required to meet the alignment requirement.
 */
#define FLEXSPI_AHBCR_READADDROPT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK)

#define FLEXSPI_AHBCR_READSZALIGN_MASK           (0x400U)
#define FLEXSPI_AHBCR_READSZALIGN_SHIFT          (10U)
/*! READSZALIGN - AHB Read Size Alignment
 *  0b0..AHB read size will be decided by other register setting like PREFETCH_EN
 *  0b1..AHB read size to up size to 8 bytes aligned, no prefetching
 */
#define FLEXSPI_AHBCR_READSZALIGN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READSZALIGN_SHIFT)) & FLEXSPI_AHBCR_READSZALIGN_MASK)

#define FLEXSPI_AHBCR_ALIGNMENT_MASK             (0x300000U)
#define FLEXSPI_AHBCR_ALIGNMENT_SHIFT            (20U)
/*! ALIGNMENT - Decides all AHB read/write boundary. All access cross the boundary will be divided into smaller sub accesses.
 *  0b00..No limit
 *  0b01..1 KBytes
 *  0b10..512 Bytes
 *  0b11..256 Bytes
 */
#define FLEXSPI_AHBCR_ALIGNMENT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ALIGNMENT_SHIFT)) & FLEXSPI_AHBCR_ALIGNMENT_MASK)
/*! @} */

/*! @name INTEN - Interrupt Enable Register */
/*! @{ */

#define FLEXSPI_INTEN_IPCMDDONEEN_MASK           (0x1U)
#define FLEXSPI_INTEN_IPCMDDONEEN_SHIFT          (0U)
/*! IPCMDDONEEN - IP triggered Command Sequences Execution finished interrupt enable.
 */
#define FLEXSPI_INTEN_IPCMDDONEEN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK)

#define FLEXSPI_INTEN_IPCMDGEEN_MASK             (0x2U)
#define FLEXSPI_INTEN_IPCMDGEEN_SHIFT            (1U)
/*! IPCMDGEEN - IP triggered Command Sequences Grant Timeout interrupt enable.
 */
#define FLEXSPI_INTEN_IPCMDGEEN(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK)

#define FLEXSPI_INTEN_AHBCMDGEEN_MASK            (0x4U)
#define FLEXSPI_INTEN_AHBCMDGEEN_SHIFT           (2U)
/*! AHBCMDGEEN - AHB triggered Command Sequences Grant Timeout interrupt enable.
 */
#define FLEXSPI_INTEN_AHBCMDGEEN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK)

#define FLEXSPI_INTEN_IPCMDERREN_MASK            (0x8U)
#define FLEXSPI_INTEN_IPCMDERREN_SHIFT           (3U)
/*! IPCMDERREN - IP triggered Command Sequences Error Detected interrupt enable.
 */
#define FLEXSPI_INTEN_IPCMDERREN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK)

#define FLEXSPI_INTEN_AHBCMDERREN_MASK           (0x10U)
#define FLEXSPI_INTEN_AHBCMDERREN_SHIFT          (4U)
/*! AHBCMDERREN - AHB triggered Command Sequences Error Detected interrupt enable.
 */
#define FLEXSPI_INTEN_AHBCMDERREN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK)

#define FLEXSPI_INTEN_IPRXWAEN_MASK              (0x20U)
#define FLEXSPI_INTEN_IPRXWAEN_SHIFT             (5U)
/*! IPRXWAEN - IP RX FIFO WaterMark available interrupt enable.
 */
#define FLEXSPI_INTEN_IPRXWAEN(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK)

#define FLEXSPI_INTEN_IPTXWEEN_MASK              (0x40U)
#define FLEXSPI_INTEN_IPTXWEEN_SHIFT             (6U)
/*! IPTXWEEN - IP TX FIFO WaterMark empty interrupt enable.
 */
#define FLEXSPI_INTEN_IPTXWEEN(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK)

#define FLEXSPI_INTEN_DATALEARNFAILEN_MASK       (0x80U)
#define FLEXSPI_INTEN_DATALEARNFAILEN_SHIFT      (7U)
/*! DATALEARNFAILEN - Data Learning failed interrupt enable.
 */
#define FLEXSPI_INTEN_DATALEARNFAILEN(x)         (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_DATALEARNFAILEN_SHIFT)) & FLEXSPI_INTEN_DATALEARNFAILEN_MASK)

#define FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK         (0x100U)
#define FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT        (8U)
/*! SCKSTOPBYRDEN - SCLK is stopped during command sequence because Async RX FIFO full interrupt enable.
 */
#define FLEXSPI_INTEN_SCKSTOPBYRDEN(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK)

#define FLEXSPI_INTEN_SCKSTOPBYWREN_MASK         (0x200U)
#define FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT        (9U)
/*! SCKSTOPBYWREN - SCLK is stopped during command sequence because Async TX FIFO empty interrupt enable.
 */
#define FLEXSPI_INTEN_SCKSTOPBYWREN(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK)

#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK       (0x400U)
#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT      (10U)
/*! AHBBUSTIMEOUTEN - AHB Bus timeout interrupt.
 */
#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN(x)         (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK)

#define FLEXSPI_INTEN_SEQTIMEOUTEN_MASK          (0x800U)
#define FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT         (11U)
/*! SEQTIMEOUTEN - Sequence execution timeout interrupt enable.
 */
#define FLEXSPI_INTEN_SEQTIMEOUTEN(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK)

#define FLEXSPI_INTEN_IPCMDSECUREVIOEN_MASK      (0x10000U)
#define FLEXSPI_INTEN_IPCMDSECUREVIOEN_SHIFT     (16U)
/*! IPCMDSECUREVIOEN - IP command security violation interrupt enable.
 */
#define FLEXSPI_INTEN_IPCMDSECUREVIOEN(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDSECUREVIOEN_SHIFT)) & FLEXSPI_INTEN_IPCMDSECUREVIOEN_MASK)

#define FLEXSPI_INTEN_AHBGCMERREN_MASK           (0x20000U)
#define FLEXSPI_INTEN_AHBGCMERREN_SHIFT          (17U)
/*! AHBGCMERREN - AHB read gcm error interrupt enable.
 */
#define FLEXSPI_INTEN_AHBGCMERREN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBGCMERREN_SHIFT)) & FLEXSPI_INTEN_AHBGCMERREN_MASK)
/*! @} */

/*! @name INTR - Interrupt Register */
/*! @{ */

#define FLEXSPI_INTR_IPCMDDONE_MASK              (0x1U)
#define FLEXSPI_INTR_IPCMDDONE_SHIFT             (0U)
/*! IPCMDDONE - IP triggered Command Sequences Execution finished interrupt. This interrupt is also
 *    generated when there is IPCMDGE or IPCMDERR interrupt generated.
 */
#define FLEXSPI_INTR_IPCMDDONE(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK)

#define FLEXSPI_INTR_IPCMDGE_MASK                (0x2U)
#define FLEXSPI_INTR_IPCMDGE_SHIFT               (1U)
/*! IPCMDGE - IP triggered Command Sequences Grant Timeout interrupt.
 */
#define FLEXSPI_INTR_IPCMDGE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK)

#define FLEXSPI_INTR_AHBCMDGE_MASK               (0x4U)
#define FLEXSPI_INTR_AHBCMDGE_SHIFT              (2U)
/*! AHBCMDGE - AHB triggered Command Sequences Grant Timeout interrupt.
 */
#define FLEXSPI_INTR_AHBCMDGE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)

#define FLEXSPI_INTR_IPCMDERR_MASK               (0x8U)
#define FLEXSPI_INTR_IPCMDERR_SHIFT              (3U)
/*! IPCMDERR - IP triggered Command Sequences Error Detected interrupt. When an error detected for
 *    IP command, this command will be ignored and not executed at all.
 */
#define FLEXSPI_INTR_IPCMDERR(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK)

#define FLEXSPI_INTR_AHBCMDERR_MASK              (0x10U)
#define FLEXSPI_INTR_AHBCMDERR_SHIFT             (4U)
/*! AHBCMDERR - AHB triggered Command Sequences Error Detected interrupt. When an error detected for
 *    AHB command, this command will be ignored and not executed at all.
 */
#define FLEXSPI_INTR_AHBCMDERR(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK)

#define FLEXSPI_INTR_IPRXWA_MASK                 (0x20U)
#define FLEXSPI_INTR_IPRXWA_SHIFT                (5U)
/*! IPRXWA - IP RX FIFO watermark available interrupt.
 */
#define FLEXSPI_INTR_IPRXWA(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK)

#define FLEXSPI_INTR_IPTXWE_MASK                 (0x40U)
#define FLEXSPI_INTR_IPTXWE_SHIFT                (6U)
/*! IPTXWE - IP TX FIFO watermark empty interrupt.
 */
#define FLEXSPI_INTR_IPTXWE(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK)

#define FLEXSPI_INTR_DATALEARNFAIL_MASK          (0x80U)
#define FLEXSPI_INTR_DATALEARNFAIL_SHIFT         (7U)
/*! DATALEARNFAIL - Data Learning failed interrupt.
 */
#define FLEXSPI_INTR_DATALEARNFAIL(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_DATALEARNFAIL_SHIFT)) & FLEXSPI_INTR_DATALEARNFAIL_MASK)

#define FLEXSPI_INTR_SCKSTOPBYRD_MASK            (0x100U)
#define FLEXSPI_INTR_SCKSTOPBYRD_SHIFT           (8U)
/*! SCKSTOPBYRD - SCLK is stopped during command sequence because Async RX FIFO full interrupt.
 */
#define FLEXSPI_INTR_SCKSTOPBYRD(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK)

#define FLEXSPI_INTR_SCKSTOPBYWR_MASK            (0x200U)
#define FLEXSPI_INTR_SCKSTOPBYWR_SHIFT           (9U)
/*! SCKSTOPBYWR - SCLK is stopped during command sequence because Async TX FIFO empty interrupt.
 */
#define FLEXSPI_INTR_SCKSTOPBYWR(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK)

#define FLEXSPI_INTR_AHBBUSTIMEOUT_MASK          (0x400U)
#define FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT         (10U)
/*! AHBBUSTIMEOUT - AHB Bus timeout interrupt.
 */
#define FLEXSPI_INTR_AHBBUSTIMEOUT(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT)) & FLEXSPI_INTR_AHBBUSTIMEOUT_MASK)

#define FLEXSPI_INTR_SEQTIMEOUT_MASK             (0x800U)
#define FLEXSPI_INTR_SEQTIMEOUT_SHIFT            (11U)
/*! SEQTIMEOUT - Sequence execution timeout interrupt.
 */
#define FLEXSPI_INTR_SEQTIMEOUT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK)

#define FLEXSPI_INTR_IPCMDSECUREVIO_MASK         (0x10000U)
#define FLEXSPI_INTR_IPCMDSECUREVIO_SHIFT        (16U)
/*! IPCMDSECUREVIO - IP command security violation interrupt.
 */
#define FLEXSPI_INTR_IPCMDSECUREVIO(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDSECUREVIO_SHIFT)) & FLEXSPI_INTR_IPCMDSECUREVIO_MASK)

#define FLEXSPI_INTR_AHBGCMERR_MASK              (0x20000U)
#define FLEXSPI_INTR_AHBGCMERR_SHIFT             (17U)
/*! AHBGCMERR - AHB read gcm error interrupt.
 */
#define FLEXSPI_INTR_AHBGCMERR(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBGCMERR_SHIFT)) & FLEXSPI_INTR_AHBGCMERR_MASK)
/*! @} */

/*! @name LUTKEY - LUT Key Register */
/*! @{ */

#define FLEXSPI_LUTKEY_KEY_MASK                  (0xFFFFFFFFU)
#define FLEXSPI_LUTKEY_KEY_SHIFT                 (0U)
/*! KEY - The Key to lock or unlock LUT.
 */
#define FLEXSPI_LUTKEY_KEY(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK)
/*! @} */

/*! @name LUTCR - LUT Control Register */
/*! @{ */

#define FLEXSPI_LUTCR_LOCK_MASK                  (0x1U)
#define FLEXSPI_LUTCR_LOCK_SHIFT                 (0U)
/*! LOCK - Lock LUT
 */
#define FLEXSPI_LUTCR_LOCK(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK)

#define FLEXSPI_LUTCR_UNLOCK_MASK                (0x2U)
#define FLEXSPI_LUTCR_UNLOCK_SHIFT               (1U)
/*! UNLOCK - Unlock LUT
 */
#define FLEXSPI_LUTCR_UNLOCK(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK)

#define FLEXSPI_LUTCR_PROTECT_MASK               (0x4U)
#define FLEXSPI_LUTCR_PROTECT_SHIFT              (2U)
/*! PROTECT - LUT protection
 */
#define FLEXSPI_LUTCR_PROTECT(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_PROTECT_SHIFT)) & FLEXSPI_LUTCR_PROTECT_MASK)
/*! @} */

/*! @name AHBRXBUFCR0 - AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0 */
/*! @{ */

#define FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK           (0xFFU)
#define FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT          (0U)
/*! BUFSZ - AHB RX Buffer Size in 64 bits.
 */
#define FLEXSPI_AHBRXBUFCR0_BUFSZ(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK)

#define FLEXSPI_AHBRXBUFCR0_MSTRID_MASK          (0xF0000U)
#define FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT         (16U)
/*! MSTRID - This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID).
 */
#define FLEXSPI_AHBRXBUFCR0_MSTRID(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK)

#define FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK        (0x7000000U)
#define FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT       (24U)
/*! PRIORITY - This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the highest priority, 0 the lowest.
 */
#define FLEXSPI_AHBRXBUFCR0_PRIORITY(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK)

#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK      (0x80000000U)
#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT     (31U)
/*! PREFETCHEN - AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master.
 */
#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK)
/*! @} */

/* The count of FLEXSPI_AHBRXBUFCR0 */
#define FLEXSPI_AHBRXBUFCR0_COUNT                (8U)

/*! @name FLSHCR0 - Flash Control Register 0 */
/*! @{ */

#define FLEXSPI_FLSHCR0_FLSHSZ_MASK              (0x7FFFFFU)
#define FLEXSPI_FLSHCR0_FLSHSZ_SHIFT             (0U)
/*! FLSHSZ - Flash Size in KByte.
 */
#define FLEXSPI_FLSHCR0_FLSHSZ(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK)

#define FLEXSPI_FLSHCR0_SPLITWREN_MASK           (0x40000000U)
#define FLEXSPI_FLSHCR0_SPLITWREN_SHIFT          (30U)
/*! SPLITWREN - AHB write access split function control.
 */
#define FLEXSPI_FLSHCR0_SPLITWREN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_SPLITWREN_SHIFT)) & FLEXSPI_FLSHCR0_SPLITWREN_MASK)

#define FLEXSPI_FLSHCR0_SPLITRDEN_MASK           (0x80000000U)
#define FLEXSPI_FLSHCR0_SPLITRDEN_SHIFT          (31U)
/*! SPLITRDEN - AHB read access split function control.
 */
#define FLEXSPI_FLSHCR0_SPLITRDEN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_SPLITRDEN_SHIFT)) & FLEXSPI_FLSHCR0_SPLITRDEN_MASK)
/*! @} */

/* The count of FLEXSPI_FLSHCR0 */
#define FLEXSPI_FLSHCR0_COUNT                    (2U)

/*! @name FLSHCR1 - Flash Control Register 1 */
/*! @{ */

#define FLEXSPI_FLSHCR1_TCSS_MASK                (0x1FU)
#define FLEXSPI_FLSHCR1_TCSS_SHIFT               (0U)
/*! TCSS - Serial Flash CS setup time.
 */
#define FLEXSPI_FLSHCR1_TCSS(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK)

#define FLEXSPI_FLSHCR1_TCSH_MASK                (0x3E0U)
#define FLEXSPI_FLSHCR1_TCSH_SHIFT               (5U)
/*! TCSH - Serial Flash CS Hold time.
 */
#define FLEXSPI_FLSHCR1_TCSH(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK)

#define FLEXSPI_FLSHCR1_WA_MASK                  (0x400U)
#define FLEXSPI_FLSHCR1_WA_SHIFT                 (10U)
/*! WA - Word Addressable.
 */
#define FLEXSPI_FLSHCR1_WA(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK)

#define FLEXSPI_FLSHCR1_CAS_MASK                 (0x7800U)
#define FLEXSPI_FLSHCR1_CAS_SHIFT                (11U)
/*! CAS - Column Address Size.
 */
#define FLEXSPI_FLSHCR1_CAS(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK)

#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK      (0x8000U)
#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT     (15U)
/*! CSINTERVALUNIT - CS interval unit
 *  0b0..The CS interval unit is 1 serial clock cycle
 *  0b1..The CS interval unit is 256 serial clock cycle
 */
#define FLEXSPI_FLSHCR1_CSINTERVALUNIT(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK)

#define FLEXSPI_FLSHCR1_CSINTERVAL_MASK          (0xFFFF0000U)
#define FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT         (16U)
/*! CSINTERVAL - This field is used to set the minimum interval between flash device Chip selection
 *    deassertion and flash device Chip selection assertion. If external flash has a limitation on
 *    the interval between command sequences, this field should be set accordingly. If there is no
 *    limitation, set this field with value 0x0.
 */
#define FLEXSPI_FLSHCR1_CSINTERVAL(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK)
/*! @} */

/* The count of FLEXSPI_FLSHCR1 */
#define FLEXSPI_FLSHCR1_COUNT                    (2U)

/*! @name FLSHCR2 - Flash Control Register 2 */
/*! @{ */

#define FLEXSPI_FLSHCR2_ARDSEQID_MASK            (0xFU)
#define FLEXSPI_FLSHCR2_ARDSEQID_SHIFT           (0U)
/*! ARDSEQID - Sequence Index for AHB Read triggered Command in LUT.
 */
#define FLEXSPI_FLSHCR2_ARDSEQID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK)

#define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK           (0xE0U)
#define FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT          (5U)
/*! ARDSEQNUM - Sequence Number for AHB Read triggered Command in LUT.
 */
#define FLEXSPI_FLSHCR2_ARDSEQNUM(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)

#define FLEXSPI_FLSHCR2_AWRSEQID_MASK            (0xF00U)
#define FLEXSPI_FLSHCR2_AWRSEQID_SHIFT           (8U)
/*! AWRSEQID - Sequence Index for AHB Write triggered Command.
 */
#define FLEXSPI_FLSHCR2_AWRSEQID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK)

#define FLEXSPI_FLSHCR2_AWRSEQNUM_MASK           (0xE000U)
#define FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT          (13U)
/*! AWRSEQNUM - Sequence Number for AHB Write triggered Command.
 */
#define FLEXSPI_FLSHCR2_AWRSEQNUM(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK)

#define FLEXSPI_FLSHCR2_AWRWAIT_MASK             (0xFFF0000U)
#define FLEXSPI_FLSHCR2_AWRWAIT_SHIFT            (16U)
/*! AWRWAIT - For certain devices (such as FPGA), it need some time to write data into internal
 *    memory after the command sequences finished on FlexSPI interface. If another Read command sequence
 *    comes before previous programming finished internally, the read data may be wrong. This field
 *    is used to hold AHB Bus ready for AHB write access to wait the programming finished in
 *    external device. Then there will be no AHB read command triggered before the programming finished in
 *    external device. The Wait cycle between AHB triggered command sequences finished on FlexSPI
 *    interface and AHB return Bus ready: AWRWAIT * AWRWAITUNIT
 */
#define FLEXSPI_FLSHCR2_AWRWAIT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK)

#define FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK         (0x70000000U)
#define FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT        (28U)
/*! AWRWAITUNIT - AWRWAIT unit
 *  0b000..The AWRWAIT unit is 2 ahb clock cycle
 *  0b001..The AWRWAIT unit is 8 ahb clock cycle
 *  0b010..The AWRWAIT unit is 32 ahb clock cycle
 *  0b011..The AWRWAIT unit is 128 ahb clock cycle
 *  0b100..The AWRWAIT unit is 512 ahb clock cycle
 *  0b101..The AWRWAIT unit is 2048 ahb clock cycle
 *  0b110..The AWRWAIT unit is 8192 ahb clock cycle
 *  0b111..The AWRWAIT unit is 32768 ahb clock cycle
 */
#define FLEXSPI_FLSHCR2_AWRWAITUNIT(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK)

#define FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK         (0x80000000U)
#define FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT        (31U)
/*! CLRINSTRPTR - Clear the instruction pointer which is internally saved pointer by JMP_ON_CS.
 */
#define FLEXSPI_FLSHCR2_CLRINSTRPTR(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK)
/*! @} */

/* The count of FLEXSPI_FLSHCR2 */
#define FLEXSPI_FLSHCR2_COUNT                    (2U)

/*! @name FLSHCR4 - Flash Control Register 4 */
/*! @{ */

#define FLEXSPI_FLSHCR4_WMOPT1_MASK              (0x1U)
#define FLEXSPI_FLSHCR4_WMOPT1_SHIFT             (0U)
/*! WMOPT1 - Write mask option bit 1. This option bit could be used to remove AHB write burst start address alignment limitation.
 *  0b0..DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB write
 *       burst start address alignment when flash is accessed in individual mode.
 *  0b1..DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB write
 *       burst start address alignment when flash is accessed in individual mode.
 */
#define FLEXSPI_FLSHCR4_WMOPT1(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK)

#define FLEXSPI_FLSHCR4_WMENA_MASK               (0x4U)
#define FLEXSPI_FLSHCR4_WMENA_SHIFT              (2U)
/*! WMENA - Write mask enable bit for flash device on port A. When write mask function is needed for
 *    memory device on port A, this bit must be set.
 *  0b0..Write mask is disabled, DQS(RWDS) pin will not be driven when writing to external device.
 *  0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device.
 */
#define FLEXSPI_FLSHCR4_WMENA(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK)
/*! @} */

/*! @name IPCR0 - IP Control Register 0 */
/*! @{ */

#define FLEXSPI_IPCR0_SFAR_MASK                  (0xFFFFFFFFU)
#define FLEXSPI_IPCR0_SFAR_SHIFT                 (0U)
/*! SFAR - Serial Flash Address for IP command.
 */
#define FLEXSPI_IPCR0_SFAR(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK)
/*! @} */

/*! @name IPCR1 - IP Control Register 1 */
/*! @{ */

#define FLEXSPI_IPCR1_IDATSZ_MASK                (0xFFFFU)
#define FLEXSPI_IPCR1_IDATSZ_SHIFT               (0U)
/*! IDATSZ - Flash Read/Program Data Size (in Bytes) for IP command.
 */
#define FLEXSPI_IPCR1_IDATSZ(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK)

#define FLEXSPI_IPCR1_ISEQID_MASK                (0xF0000U)
#define FLEXSPI_IPCR1_ISEQID_SHIFT               (16U)
/*! ISEQID - Sequence Index in LUT for IP command.
 */
#define FLEXSPI_IPCR1_ISEQID(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK)

#define FLEXSPI_IPCR1_ISEQNUM_MASK               (0x7000000U)
#define FLEXSPI_IPCR1_ISEQNUM_SHIFT              (24U)
/*! ISEQNUM - Sequence Number for IP command: ISEQNUM+1.
 */
#define FLEXSPI_IPCR1_ISEQNUM(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK)
/*! @} */

/*! @name IPCMD - IP Command Register */
/*! @{ */

#define FLEXSPI_IPCMD_TRG_MASK                   (0x1U)
#define FLEXSPI_IPCMD_TRG_SHIFT                  (0U)
/*! TRG - Setting this bit will trigger an IP Command.
 */
#define FLEXSPI_IPCMD_TRG(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK)
/*! @} */

/*! @name DLPR - Data Learn Pattern Register */
/*! @{ */

#define FLEXSPI_DLPR_DLP_MASK                    (0xFFFFFFFFU)
#define FLEXSPI_DLPR_DLP_SHIFT                   (0U)
/*! DLP - Data Learning Pattern.
 */
#define FLEXSPI_DLPR_DLP(x)                      (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLPR_DLP_SHIFT)) & FLEXSPI_DLPR_DLP_MASK)
/*! @} */

/*! @name IPRXFCR - IP RX FIFO Control Register */
/*! @{ */

#define FLEXSPI_IPRXFCR_CLRIPRXF_MASK            (0x1U)
#define FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT           (0U)
/*! CLRIPRXF - Clear all valid data entries in IP RX FIFO.
 */
#define FLEXSPI_IPRXFCR_CLRIPRXF(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK)

#define FLEXSPI_IPRXFCR_RXDMAEN_MASK             (0x2U)
#define FLEXSPI_IPRXFCR_RXDMAEN_SHIFT            (1U)
/*! RXDMAEN - IP RX FIFO reading by DMA enabled.
 *  0b0..IP RX FIFO would be read by processor.
 *  0b1..IP RX FIFO would be read by DMA.
 */
#define FLEXSPI_IPRXFCR_RXDMAEN(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK)

#define FLEXSPI_IPRXFCR_RXWMRK_MASK              (0x1FCU)
#define FLEXSPI_IPRXFCR_RXWMRK_SHIFT             (2U)
/*! RXWMRK - Watermark level is (RXWMRK+1)*64 Bits.
 */
#define FLEXSPI_IPRXFCR_RXWMRK(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK)
/*! @} */

/*! @name IPTXFCR - IP TX FIFO Control Register */
/*! @{ */

#define FLEXSPI_IPTXFCR_CLRIPTXF_MASK            (0x1U)
#define FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT           (0U)
/*! CLRIPTXF - Clear all valid data entries in IP TX FIFO.
 */
#define FLEXSPI_IPTXFCR_CLRIPTXF(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK)

#define FLEXSPI_IPTXFCR_TXDMAEN_MASK             (0x2U)
#define FLEXSPI_IPTXFCR_TXDMAEN_SHIFT            (1U)
/*! TXDMAEN - IP TX FIFO filling by DMA enabled.
 *  0b0..IP TX FIFO would be filled by processor.
 *  0b1..IP TX FIFO would be filled by DMA.
 */
#define FLEXSPI_IPTXFCR_TXDMAEN(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK)

#define FLEXSPI_IPTXFCR_TXWMRK_MASK              (0x1FCU)
#define FLEXSPI_IPTXFCR_TXWMRK_SHIFT             (2U)
/*! TXWMRK - Watermark level is (TXWMRK+1)*64 Bits.
 */
#define FLEXSPI_IPTXFCR_TXWMRK(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK)
/*! @} */

/*! @name DLLCR - DLL Control Register 0 */
/*! @{ */

#define FLEXSPI_DLLCR_DLLEN_MASK                 (0x1U)
#define FLEXSPI_DLLCR_DLLEN_SHIFT                (0U)
/*! DLLEN - DLL calibration enable.
 */
#define FLEXSPI_DLLCR_DLLEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK)

#define FLEXSPI_DLLCR_DLLRESET_MASK              (0x2U)
#define FLEXSPI_DLLCR_DLLRESET_SHIFT             (1U)
/*! DLLRESET - DLL reset
 */
#define FLEXSPI_DLLCR_DLLRESET(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK)

#define FLEXSPI_DLLCR_SLVDLYTARGET_MASK          (0x78U)
#define FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT         (3U)
/*! SLVDLYTARGET - The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle
 *    of reference clock (serial root clock). If serial root clock is >= 100 MHz, DLLEN set to 0x1,
 *    OVRDEN set to =0x0, then SLVDLYTARGET setting of 0xF is recommended.
 */
#define FLEXSPI_DLLCR_SLVDLYTARGET(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK)

#define FLEXSPI_DLLCR_OVRDEN_MASK                (0x100U)
#define FLEXSPI_DLLCR_OVRDEN_SHIFT               (8U)
/*! OVRDEN - Slave clock delay line delay cell number selection override enable.
 */
#define FLEXSPI_DLLCR_OVRDEN(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK)

#define FLEXSPI_DLLCR_OVRDVAL_MASK               (0x7E00U)
#define FLEXSPI_DLLCR_OVRDVAL_SHIFT              (9U)
/*! OVRDVAL - Slave clock delay line delay cell number selection override value.
 */
#define FLEXSPI_DLLCR_OVRDVAL(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK)
/*! @} */

/* The count of FLEXSPI_DLLCR */
#define FLEXSPI_DLLCR_COUNT                      (2U)

/*! @name STS0 - Status Register 0 */
/*! @{ */

#define FLEXSPI_STS0_SEQIDLE_MASK                (0x1U)
#define FLEXSPI_STS0_SEQIDLE_SHIFT               (0U)
/*! SEQIDLE - This status bit indicates the state machine in SEQ_CTL is idle and there is command
 *    sequence executing on FlexSPI interface.
 */
#define FLEXSPI_STS0_SEQIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK)

#define FLEXSPI_STS0_ARBIDLE_MASK                (0x2U)
#define FLEXSPI_STS0_ARBIDLE_SHIFT               (1U)
/*! ARBIDLE - This status bit indicates the state machine in ARB_CTL is busy and there is command
 *    sequence granted by arbitrator and not finished yet on FlexSPI interface. When ARB_CTL state
 *    (ARBIDLE=0x1) is idle, there will be no transaction on FlexSPI interface also (SEQIDLE=0x1). So
 *    this bit should be polled to wait for FlexSPI controller become idle instead of SEQIDLE.
 */
#define FLEXSPI_STS0_ARBIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK)

#define FLEXSPI_STS0_ARBCMDSRC_MASK              (0xCU)
#define FLEXSPI_STS0_ARBCMDSRC_SHIFT             (2U)
/*! ARBCMDSRC - This status field indicates the trigger source of current command sequence granted
 *    by arbitrator. This field value is meaningless when ARB_CTL is not busy (STS0[ARBIDLE]=0x1).
 *  0b00..Triggered by AHB read command (triggered by AHB read).
 *  0b01..Triggered by AHB write command (triggered by AHB Write).
 *  0b10..Triggered by IP command (triggered by setting register bit IPCMD.TRG).
 *  0b11..Triggered by suspended command (resumed).
 */
#define FLEXSPI_STS0_ARBCMDSRC(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK)

#define FLEXSPI_STS0_DATALEARNPHASEA_MASK        (0xF0U)
#define FLEXSPI_STS0_DATALEARNPHASEA_SHIFT       (4U)
/*! DATALEARNPHASEA - Indicate the sampling clock phase selection on Port A after Data Learning.
 */
#define FLEXSPI_STS0_DATALEARNPHASEA(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_DATALEARNPHASEA_SHIFT)) & FLEXSPI_STS0_DATALEARNPHASEA_MASK)
/*! @} */

/*! @name STS1 - Status Register 1 */
/*! @{ */

#define FLEXSPI_STS1_AHBCMDERRID_MASK            (0xFU)
#define FLEXSPI_STS1_AHBCMDERRID_SHIFT           (0U)
/*! AHBCMDERRID - Indicates the sequence index when an AHB command error is detected. This field
 *    will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c).
 */
#define FLEXSPI_STS1_AHBCMDERRID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK)

#define FLEXSPI_STS1_AHBCMDERRCODE_MASK          (0xF00U)
#define FLEXSPI_STS1_AHBCMDERRCODE_SHIFT         (8U)
/*! AHBCMDERRCODE - Indicates the Error Code when AHB command Error detected. This field will be
 *    cleared when INTR[AHBCMDERR] is write-1-clear(w1c).
 *  0b0000..No error.
 *  0b0010..AHB Write command with JMP_ON_CS instruction used in the sequence.
 *  0b0011..There is unknown instruction opcode in the sequence.
 *  0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.
 *  0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.
 *  0b1110..Sequence execution timeout.
 */
#define FLEXSPI_STS1_AHBCMDERRCODE(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK)

#define FLEXSPI_STS1_IPCMDERRID_MASK             (0xF0000U)
#define FLEXSPI_STS1_IPCMDERRID_SHIFT            (16U)
/*! IPCMDERRID - Indicates the sequence Index when IP command error detected.
 */
#define FLEXSPI_STS1_IPCMDERRID(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK)

#define FLEXSPI_STS1_IPCMDERRCODE_MASK           (0xF000000U)
#define FLEXSPI_STS1_IPCMDERRCODE_SHIFT          (24U)
/*! IPCMDERRCODE - Indicates the Error Code when IP command Error detected. This field will be
 *    cleared when INTR[IPCMDERR] is write-1-clear(w1c).
 *  0b0000..No error.
 *  0b0010..IP command with JMP_ON_CS instruction used in the sequence.
 *  0b0011..There is unknown instruction opcode in the sequence.
 *  0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.
 *  0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.
 *  0b0110..Flash access start address exceed the whole flash address range (A1/A2/B1/B2).
 *  0b1110..Sequence execution timeout.
 *  0b1111..Flash boundary crossed.
 */
#define FLEXSPI_STS1_IPCMDERRCODE(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK)
/*! @} */

/*! @name STS2 - Status Register 2 */
/*! @{ */

#define FLEXSPI_STS2_ASLVLOCK_MASK               (0x1U)
#define FLEXSPI_STS2_ASLVLOCK_SHIFT              (0U)
/*! ASLVLOCK - Flash A sample clock slave delay line locked.
 */
#define FLEXSPI_STS2_ASLVLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK)

#define FLEXSPI_STS2_AREFLOCK_MASK               (0x2U)
#define FLEXSPI_STS2_AREFLOCK_SHIFT              (1U)
/*! AREFLOCK - Flash A sample clock reference delay line locked.
 */
#define FLEXSPI_STS2_AREFLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK)

#define FLEXSPI_STS2_ASLVSEL_MASK                (0xFCU)
#define FLEXSPI_STS2_ASLVSEL_SHIFT               (2U)
/*! ASLVSEL - Flash A sample clock slave delay line delay cell number selection .
 */
#define FLEXSPI_STS2_ASLVSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK)

#define FLEXSPI_STS2_AREFSEL_MASK                (0x3F00U)
#define FLEXSPI_STS2_AREFSEL_SHIFT               (8U)
/*! AREFSEL - Flash A sample clock reference delay line delay cell number selection.
 */
#define FLEXSPI_STS2_AREFSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK)
/*! @} */

/*! @name AHBSPNDSTS - AHB Suspend Status Register */
/*! @{ */

#define FLEXSPI_AHBSPNDSTS_ACTIVE_MASK           (0x1U)
#define FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT          (0U)
/*! ACTIVE - Indicates if an AHB read prefetch command sequence has been suspended.
 */
#define FLEXSPI_AHBSPNDSTS_ACTIVE(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK)

#define FLEXSPI_AHBSPNDSTS_BUFID_MASK            (0xEU)
#define FLEXSPI_AHBSPNDSTS_BUFID_SHIFT           (1U)
/*! BUFID - AHB RX BUF ID for suspended command sequence.
 */
#define FLEXSPI_AHBSPNDSTS_BUFID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK)

#define FLEXSPI_AHBSPNDSTS_DATLFT_MASK           (0xFFFF0000U)
#define FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT          (16U)
/*! DATLFT - Left Data size for suspended command sequence (in byte).
 */
#define FLEXSPI_AHBSPNDSTS_DATLFT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK)
/*! @} */

/*! @name IPRXFSTS - IP RX FIFO Status Register */
/*! @{ */

#define FLEXSPI_IPRXFSTS_FILL_MASK               (0xFFU)
#define FLEXSPI_IPRXFSTS_FILL_SHIFT              (0U)
/*! FILL - Fill level of IP RX FIFO.
 */
#define FLEXSPI_IPRXFSTS_FILL(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK)

#define FLEXSPI_IPRXFSTS_RDCNTR_MASK             (0xFFFF0000U)
#define FLEXSPI_IPRXFSTS_RDCNTR_SHIFT            (16U)
/*! RDCNTR - Total Read Data Counter: RDCNTR * 64 Bits.
 */
#define FLEXSPI_IPRXFSTS_RDCNTR(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK)
/*! @} */

/*! @name IPTXFSTS - IP TX FIFO Status Register */
/*! @{ */

#define FLEXSPI_IPTXFSTS_FILL_MASK               (0xFFU)
#define FLEXSPI_IPTXFSTS_FILL_SHIFT              (0U)
/*! FILL - Fill level of IP TX FIFO.
 */
#define FLEXSPI_IPTXFSTS_FILL(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK)

#define FLEXSPI_IPTXFSTS_WRCNTR_MASK             (0xFFFF0000U)
#define FLEXSPI_IPTXFSTS_WRCNTR_SHIFT            (16U)
/*! WRCNTR - Total Write Data Counter: WRCNTR * 64 Bits.
 */
#define FLEXSPI_IPTXFSTS_WRCNTR(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK)
/*! @} */

/*! @name RFDR - IP RX FIFO Data Register 0..IP RX FIFO Data Register 31 */
/*! @{ */

#define FLEXSPI_RFDR_RXDATA_MASK                 (0xFFFFFFFFU)
#define FLEXSPI_RFDR_RXDATA_SHIFT                (0U)
/*! RXDATA - RX Data
 */
#define FLEXSPI_RFDR_RXDATA(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK)
/*! @} */

/* The count of FLEXSPI_RFDR */
#define FLEXSPI_RFDR_COUNT                       (32U)

/*! @name TFDR - IP TX FIFO Data Register 0..IP TX FIFO Data Register 31 */
/*! @{ */

#define FLEXSPI_TFDR_TXDATA_MASK                 (0xFFFFFFFFU)
#define FLEXSPI_TFDR_TXDATA_SHIFT                (0U)
/*! TXDATA - TX Data
 */
#define FLEXSPI_TFDR_TXDATA(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK)
/*! @} */

/* The count of FLEXSPI_TFDR */
#define FLEXSPI_TFDR_COUNT                       (32U)

/*! @name LUT - LUT 0..LUT 63 */
/*! @{ */

#define FLEXSPI_LUT_OPERAND0_MASK                (0xFFU)
#define FLEXSPI_LUT_OPERAND0_SHIFT               (0U)
/*! OPERAND0 - OPERAND0
 */
#define FLEXSPI_LUT_OPERAND0(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK)

#define FLEXSPI_LUT_NUM_PADS0_MASK               (0x300U)
#define FLEXSPI_LUT_NUM_PADS0_SHIFT              (8U)
/*! NUM_PADS0 - NUM_PADS0
 */
#define FLEXSPI_LUT_NUM_PADS0(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK)

#define FLEXSPI_LUT_OPCODE0_MASK                 (0xFC00U)
#define FLEXSPI_LUT_OPCODE0_SHIFT                (10U)
/*! OPCODE0 - OPCODE
 */
#define FLEXSPI_LUT_OPCODE0(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK)

#define FLEXSPI_LUT_OPERAND1_MASK                (0xFF0000U)
#define FLEXSPI_LUT_OPERAND1_SHIFT               (16U)
/*! OPERAND1 - OPERAND1
 */
#define FLEXSPI_LUT_OPERAND1(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK)

#define FLEXSPI_LUT_NUM_PADS1_MASK               (0x3000000U)
#define FLEXSPI_LUT_NUM_PADS1_SHIFT              (24U)
/*! NUM_PADS1 - NUM_PADS1
 */
#define FLEXSPI_LUT_NUM_PADS1(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK)

#define FLEXSPI_LUT_OPCODE1_MASK                 (0xFC000000U)
#define FLEXSPI_LUT_OPCODE1_SHIFT                (26U)
/*! OPCODE1 - OPCODE1
 */
#define FLEXSPI_LUT_OPCODE1(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK)
/*! @} */

/* The count of FLEXSPI_LUT */
#define FLEXSPI_LUT_COUNT                        (64U)

/*! @name HADDRSTART - HADDR REMAP START ADDR */
/*! @{ */

#define FLEXSPI_HADDRSTART_REMAPEN_MASK          (0x1U)
#define FLEXSPI_HADDRSTART_REMAPEN_SHIFT         (0U)
/*! REMAPEN - AHB Bus address remap function enable
 *  0b0..HADDR REMAP Disabled
 *  0b1..HADDR REMAP Enabled
 */
#define FLEXSPI_HADDRSTART_REMAPEN(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDRSTART_REMAPEN_SHIFT)) & FLEXSPI_HADDRSTART_REMAPEN_MASK)

#define FLEXSPI_HADDRSTART_ADDRSTART_MASK        (0xFFFFF000U)
#define FLEXSPI_HADDRSTART_ADDRSTART_SHIFT       (12U)
/*! ADDRSTART - HADDR start address
 */
#define FLEXSPI_HADDRSTART_ADDRSTART(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDRSTART_ADDRSTART_SHIFT)) & FLEXSPI_HADDRSTART_ADDRSTART_MASK)
/*! @} */

/*! @name HADDREND - HADDR REMAP END ADDR */
/*! @{ */

#define FLEXSPI_HADDREND_ENDSTART_MASK           (0xFFFFF000U)
#define FLEXSPI_HADDREND_ENDSTART_SHIFT          (12U)
/*! ENDSTART - HADDR remap range's end addr, 4K aligned
 */
#define FLEXSPI_HADDREND_ENDSTART(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDREND_ENDSTART_SHIFT)) & FLEXSPI_HADDREND_ENDSTART_MASK)
/*! @} */

/*! @name HADDROFFSET - HADDR REMAP OFFSET */
/*! @{ */

#define FLEXSPI_HADDROFFSET_ADDROFFSET_MASK      (0xFFFFF000U)
#define FLEXSPI_HADDROFFSET_ADDROFFSET_SHIFT     (12U)
/*! ADDROFFSET - HADDR offset field, remapped address will be ADDR[31:12]=ADDR_original[31:12]+ADDROFFSET
 */
#define FLEXSPI_HADDROFFSET_ADDROFFSET(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDROFFSET_ADDROFFSET_SHIFT)) & FLEXSPI_HADDROFFSET_ADDROFFSET_MASK)
/*! @} */

/*! @name IPEDCTRL - IPED function control */
/*! @{ */

#define FLEXSPI_IPEDCTRL_CONFIG_MASK             (0x1U)
#define FLEXSPI_IPEDCTRL_CONFIG_SHIFT            (0U)
/*! CONFIG - Drive IPED interface i_config.
 */
#define FLEXSPI_IPEDCTRL_CONFIG(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_CONFIG_SHIFT)) & FLEXSPI_IPEDCTRL_CONFIG_MASK)

#define FLEXSPI_IPEDCTRL_IPED_EN_MASK            (0x2U)
#define FLEXSPI_IPEDCTRL_IPED_EN_SHIFT           (1U)
/*! IPED_EN - Drive IPED interface i_enable
 */
#define FLEXSPI_IPEDCTRL_IPED_EN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_IPED_EN_SHIFT)) & FLEXSPI_IPEDCTRL_IPED_EN_MASK)

#define FLEXSPI_IPEDCTRL_IPWR_EN_MASK            (0x4U)
#define FLEXSPI_IPEDCTRL_IPWR_EN_SHIFT           (2U)
/*! IPWR_EN - IP write IPED CTR mode encryption enable
 */
#define FLEXSPI_IPEDCTRL_IPWR_EN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_IPWR_EN_SHIFT)) & FLEXSPI_IPEDCTRL_IPWR_EN_MASK)

#define FLEXSPI_IPEDCTRL_AHBWR_EN_MASK           (0x8U)
#define FLEXSPI_IPEDCTRL_AHBWR_EN_SHIFT          (3U)
/*! AHBWR_EN - AHB write IPED CTR mode encryption enable
 */
#define FLEXSPI_IPEDCTRL_AHBWR_EN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_AHBWR_EN_SHIFT)) & FLEXSPI_IPEDCTRL_AHBWR_EN_MASK)

#define FLEXSPI_IPEDCTRL_AHBRD_EN_MASK           (0x10U)
#define FLEXSPI_IPEDCTRL_AHBRD_EN_SHIFT          (4U)
/*! AHBRD_EN - AHB read IPED CTR mode decryption enable
 */
#define FLEXSPI_IPEDCTRL_AHBRD_EN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_AHBRD_EN_SHIFT)) & FLEXSPI_IPEDCTRL_AHBRD_EN_MASK)

#define FLEXSPI_IPEDCTRL_IPGCMWR_MASK            (0x40U)
#define FLEXSPI_IPEDCTRL_IPGCMWR_SHIFT           (6U)
/*! IPGCMWR - IP write GCM mode enable
 */
#define FLEXSPI_IPEDCTRL_IPGCMWR(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_IPGCMWR_SHIFT)) & FLEXSPI_IPEDCTRL_IPGCMWR_MASK)

#define FLEXSPI_IPEDCTRL_AHGCMWR_MASK            (0x80U)
#define FLEXSPI_IPEDCTRL_AHGCMWR_SHIFT           (7U)
/*! AHGCMWR - AHB write IPED GCM mode encryption enable
 */
#define FLEXSPI_IPEDCTRL_AHGCMWR(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_AHGCMWR_SHIFT)) & FLEXSPI_IPEDCTRL_AHGCMWR_MASK)

#define FLEXSPI_IPEDCTRL_AHBGCMRD_MASK           (0x100U)
#define FLEXSPI_IPEDCTRL_AHBGCMRD_SHIFT          (8U)
/*! AHBGCMRD - AHB read IPED GCM mode decryption enable
 */
#define FLEXSPI_IPEDCTRL_AHBGCMRD(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_AHBGCMRD_SHIFT)) & FLEXSPI_IPEDCTRL_AHBGCMRD_MASK)

#define FLEXSPI_IPEDCTRL_IPED_PROTECT_MASK       (0x200U)
#define FLEXSPI_IPEDCTRL_IPED_PROTECT_SHIFT      (9U)
/*! IPED_PROTECT - when ipedctrl protect = 0 or priviledge access, no restriction when ipedctrl
 *    protect = 1, only priviledge access can write.
 */
#define FLEXSPI_IPEDCTRL_IPED_PROTECT(x)         (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_IPED_PROTECT_SHIFT)) & FLEXSPI_IPEDCTRL_IPED_PROTECT_MASK)

#define FLEXSPI_IPEDCTRL_IPED_SWRESET_MASK       (0x400U)
#define FLEXSPI_IPEDCTRL_IPED_SWRESET_SHIFT      (10U)
/*! IPED_SWRESET - Drive IPED interface i_abort.
 */
#define FLEXSPI_IPEDCTRL_IPED_SWRESET(x)         (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTRL_IPED_SWRESET_SHIFT)) & FLEXSPI_IPEDCTRL_IPED_SWRESET_MASK)
/*! @} */

/*! @name IPEDCTXCTRLX_IPEDCTXCTRL - IPED context control 0..IPED context control 1 */
/*! @{ */

#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE0_MASK (0x3U)
#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE0_SHIFT (0U)
/*! CTX0_FREEZE0 - Controls the RW properties of this field and region 0 context registers (CTX0_xxxx).
 */
#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE0_SHIFT)) & FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE0_MASK)

#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE1_MASK (0x3U)
#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE1_SHIFT (0U)
/*! CTX0_FREEZE1 - Controls the RW properties of this field and region 0 context registers (CTX0_xxxx).
 */
#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE1_SHIFT)) & FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX0_FREEZE1_MASK)

#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX1_FREEZE0_MASK (0xCU)
#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX1_FREEZE0_SHIFT (2U)
/*! CTX1_FREEZE0 - Controls the RW properties of this field and region 1 context registers (CTX1_xxxx).
 */
#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX1_FREEZE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX1_FREEZE0_SHIFT)) & FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX1_FREEZE0_MASK)

#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX1_FREEZE1_MASK (0xCU)
#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX1_FREEZE1_SHIFT (2U)
/*! CTX1_FREEZE1 - Controls the RW properties of this field and region 1 context registers (CTX1_xxxx).
 */
#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX1_FREEZE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX1_FREEZE1_SHIFT)) & FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX1_FREEZE1_MASK)

#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX2_FREEZE0_MASK (0x30U)
#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX2_FREEZE0_SHIFT (4U)
/*! CTX2_FREEZE0 - Controls the RW properties of this field and region 2 context registers (CTX2_xxxx).
 */
#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX2_FREEZE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX2_FREEZE0_SHIFT)) & FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX2_FREEZE0_MASK)

#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX2_FREEZE1_MASK (0x30U)
#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX2_FREEZE1_SHIFT (4U)
/*! CTX2_FREEZE1 - Controls the RW properties of this field and region 2 context registers (CTX2_xxxx).
 */
#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX2_FREEZE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX2_FREEZE1_SHIFT)) & FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX2_FREEZE1_MASK)

#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX3_FREEZE0_MASK (0xC0U)
#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX3_FREEZE0_SHIFT (6U)
/*! CTX3_FREEZE0 - Controls the RW properties of this field and region 3 context registers (CTX3_xxxx).
 */
#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX3_FREEZE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX3_FREEZE0_SHIFT)) & FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX3_FREEZE0_MASK)

#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX3_FREEZE1_MASK (0xC0U)
#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX3_FREEZE1_SHIFT (6U)
/*! CTX3_FREEZE1 - Controls the RW properties of this field and region 3 context registers (CTX3_xxxx).
 */
#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX3_FREEZE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX3_FREEZE1_SHIFT)) & FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_CTX3_FREEZE1_MASK)
/*! @} */

/* The count of FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL */
#define FLEXSPI_IPEDCTXCTRLX_IPEDCTXCTRL_COUNT   (2U)

/*! @name IPEDCTX0IV0 - IPED context0 IV0 */
/*! @{ */

#define FLEXSPI_IPEDCTX0IV0_CTX0_IV0_MASK        (0xFFFFFFFFU)
#define FLEXSPI_IPEDCTX0IV0_CTX0_IV0_SHIFT       (0U)
/*! CTX0_IV0 - Lowest 32 bits of IV for region 0.
 */
#define FLEXSPI_IPEDCTX0IV0_CTX0_IV0(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX0IV0_CTX0_IV0_SHIFT)) & FLEXSPI_IPEDCTX0IV0_CTX0_IV0_MASK)
/*! @} */

/*! @name IPEDCTX0IV1 - IPED context0 IV1 */
/*! @{ */

#define FLEXSPI_IPEDCTX0IV1_CTX0_IV1_MASK        (0xFFFFFFFFU)
#define FLEXSPI_IPEDCTX0IV1_CTX0_IV1_SHIFT       (0U)
/*! CTX0_IV1 - Highest 32 bits of IV for region 0.
 */
#define FLEXSPI_IPEDCTX0IV1_CTX0_IV1(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX0IV1_CTX0_IV1_SHIFT)) & FLEXSPI_IPEDCTX0IV1_CTX0_IV1_MASK)
/*! @} */

/*! @name IPEDCTX0START - Start address of region 0 */
/*! @{ */

#define FLEXSPI_IPEDCTX0START_GCM_MASK           (0x1U)
#define FLEXSPI_IPEDCTX0START_GCM_SHIFT          (0U)
/*! GCM - If this bit is 1, current region is GCM mode region.
 */
#define FLEXSPI_IPEDCTX0START_GCM(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX0START_GCM_SHIFT)) & FLEXSPI_IPEDCTX0START_GCM_MASK)

#define FLEXSPI_IPEDCTX0START_ahbbuserror_dis_MASK (0x2U)
#define FLEXSPI_IPEDCTX0START_ahbbuserror_dis_SHIFT (1U)
/*! ahbbuserror_dis - If this bit is 1, ahb bus error is disable.
 */
#define FLEXSPI_IPEDCTX0START_ahbbuserror_dis(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX0START_ahbbuserror_dis_SHIFT)) & FLEXSPI_IPEDCTX0START_ahbbuserror_dis_MASK)

#define FLEXSPI_IPEDCTX0START_start_address_MASK (0xFFFFFF00U)
#define FLEXSPI_IPEDCTX0START_start_address_SHIFT (8U)
/*! start_address - Start address of region 0. Minimal 256 Bytes aligned. It is system address.
 */
#define FLEXSPI_IPEDCTX0START_start_address(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX0START_start_address_SHIFT)) & FLEXSPI_IPEDCTX0START_start_address_MASK)
/*! @} */

/*! @name IPEDCTX0END - End address of region 0 */
/*! @{ */

#define FLEXSPI_IPEDCTX0END_end_address_MASK     (0xFFFFFF00U)
#define FLEXSPI_IPEDCTX0END_end_address_SHIFT    (8U)
/*! end_address - End address of region 0. Minimal 256 Bytes aligned. It is system address.
 */
#define FLEXSPI_IPEDCTX0END_end_address(x)       (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX0END_end_address_SHIFT)) & FLEXSPI_IPEDCTX0END_end_address_MASK)
/*! @} */

/*! @name IPEDCTX0AAD0 - IPED context0 AAD0 */
/*! @{ */

#define FLEXSPI_IPEDCTX0AAD0_CTX0_AAD0_MASK      (0xFFFFFFFFU)
#define FLEXSPI_IPEDCTX0AAD0_CTX0_AAD0_SHIFT     (0U)
/*! CTX0_AAD0 - Lowest 32 bits of AAD for region 0.
 */
#define FLEXSPI_IPEDCTX0AAD0_CTX0_AAD0(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX0AAD0_CTX0_AAD0_SHIFT)) & FLEXSPI_IPEDCTX0AAD0_CTX0_AAD0_MASK)
/*! @} */

/*! @name IPEDCTX0AAD1 - IPED context0 AAD1 */
/*! @{ */

#define FLEXSPI_IPEDCTX0AAD1_CTX0_AAD1_MASK      (0xFFFFFFFFU)
#define FLEXSPI_IPEDCTX0AAD1_CTX0_AAD1_SHIFT     (0U)
/*! CTX0_AAD1 - Highest 32 bits of AAD for region 0.
 */
#define FLEXSPI_IPEDCTX0AAD1_CTX0_AAD1(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX0AAD1_CTX0_AAD1_SHIFT)) & FLEXSPI_IPEDCTX0AAD1_CTX0_AAD1_MASK)
/*! @} */

/*! @name IPEDCTX1IV0 - IPED context1 IV0 */
/*! @{ */

#define FLEXSPI_IPEDCTX1IV0_CTX1_IV0_MASK        (0xFFFFFFFFU)
#define FLEXSPI_IPEDCTX1IV0_CTX1_IV0_SHIFT       (0U)
/*! CTX1_IV0 - Lowest 32 bits of IV for region 1.
 */
#define FLEXSPI_IPEDCTX1IV0_CTX1_IV0(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX1IV0_CTX1_IV0_SHIFT)) & FLEXSPI_IPEDCTX1IV0_CTX1_IV0_MASK)
/*! @} */

/*! @name IPEDCTX1IV1 - IPED context1 IV1 */
/*! @{ */

#define FLEXSPI_IPEDCTX1IV1_CTX1_IV1_MASK        (0xFFFFFFFFU)
#define FLEXSPI_IPEDCTX1IV1_CTX1_IV1_SHIFT       (0U)
/*! CTX1_IV1 - Highest 32 bits of IV for region 1.
 */
#define FLEXSPI_IPEDCTX1IV1_CTX1_IV1(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX1IV1_CTX1_IV1_SHIFT)) & FLEXSPI_IPEDCTX1IV1_CTX1_IV1_MASK)
/*! @} */

/*! @name IPEDCTX1START - Start address of region 1 */
/*! @{ */

#define FLEXSPI_IPEDCTX1START_GCM_MASK           (0x1U)
#define FLEXSPI_IPEDCTX1START_GCM_SHIFT          (0U)
/*! GCM - If this bit is 1, current region is GCM mode region.
 */
#define FLEXSPI_IPEDCTX1START_GCM(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX1START_GCM_SHIFT)) & FLEXSPI_IPEDCTX1START_GCM_MASK)

#define FLEXSPI_IPEDCTX1START_ahbbuserror_dis_MASK (0x2U)
#define FLEXSPI_IPEDCTX1START_ahbbuserror_dis_SHIFT (1U)
/*! ahbbuserror_dis - If this bit is 1, ahb bus error is disable.
 */
#define FLEXSPI_IPEDCTX1START_ahbbuserror_dis(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX1START_ahbbuserror_dis_SHIFT)) & FLEXSPI_IPEDCTX1START_ahbbuserror_dis_MASK)

#define FLEXSPI_IPEDCTX1START_start_address_MASK (0xFFFFFF00U)
#define FLEXSPI_IPEDCTX1START_start_address_SHIFT (8U)
/*! start_address - Start address of region 1. Minimal 256 Bytes aligned. It is system address.
 */
#define FLEXSPI_IPEDCTX1START_start_address(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX1START_start_address_SHIFT)) & FLEXSPI_IPEDCTX1START_start_address_MASK)
/*! @} */

/*! @name IPEDCTX1END - End address of region 1 */
/*! @{ */

#define FLEXSPI_IPEDCTX1END_end_address_MASK     (0xFFFFFF00U)
#define FLEXSPI_IPEDCTX1END_end_address_SHIFT    (8U)
/*! end_address - End address of region 1. Minimal 256 Bytes aligned. It is system address.
 */
#define FLEXSPI_IPEDCTX1END_end_address(x)       (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX1END_end_address_SHIFT)) & FLEXSPI_IPEDCTX1END_end_address_MASK)
/*! @} */

/*! @name IPEDCTX1AAD0 - IPED context1 AAD0 */
/*! @{ */

#define FLEXSPI_IPEDCTX1AAD0_CTX1_AAD0_MASK      (0xFFFFFFFFU)
#define FLEXSPI_IPEDCTX1AAD0_CTX1_AAD0_SHIFT     (0U)
/*! CTX1_AAD0 - Lowest 32 bits of AAD for region 1.
 */
#define FLEXSPI_IPEDCTX1AAD0_CTX1_AAD0(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX1AAD0_CTX1_AAD0_SHIFT)) & FLEXSPI_IPEDCTX1AAD0_CTX1_AAD0_MASK)
/*! @} */

/*! @name IPEDCTX1AAD1 - IPED context1 AAD1 */
/*! @{ */

#define FLEXSPI_IPEDCTX1AAD1_CTX1_AAD1_MASK      (0xFFFFFFFFU)
#define FLEXSPI_IPEDCTX1AAD1_CTX1_AAD1_SHIFT     (0U)
/*! CTX1_AAD1 - Highest 32 bits of AAD for region 1.
 */
#define FLEXSPI_IPEDCTX1AAD1_CTX1_AAD1(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX1AAD1_CTX1_AAD1_SHIFT)) & FLEXSPI_IPEDCTX1AAD1_CTX1_AAD1_MASK)
/*! @} */

/*! @name IPEDCTX2IV0 - IPED context2 IV0 */
/*! @{ */

#define FLEXSPI_IPEDCTX2IV0_CTX2_IV0_MASK        (0xFFFFFFFFU)
#define FLEXSPI_IPEDCTX2IV0_CTX2_IV0_SHIFT       (0U)
/*! CTX2_IV0 - Lowest 32 bits of IV for region 2.
 */
#define FLEXSPI_IPEDCTX2IV0_CTX2_IV0(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX2IV0_CTX2_IV0_SHIFT)) & FLEXSPI_IPEDCTX2IV0_CTX2_IV0_MASK)
/*! @} */

/*! @name IPEDCTX2IV1 - IPED context2 IV1 */
/*! @{ */

#define FLEXSPI_IPEDCTX2IV1_CTX2_IV1_MASK        (0xFFFFFFFFU)
#define FLEXSPI_IPEDCTX2IV1_CTX2_IV1_SHIFT       (0U)
/*! CTX2_IV1 - Highest 32 bits of IV for region 2.
 */
#define FLEXSPI_IPEDCTX2IV1_CTX2_IV1(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX2IV1_CTX2_IV1_SHIFT)) & FLEXSPI_IPEDCTX2IV1_CTX2_IV1_MASK)
/*! @} */

/*! @name IPEDCTX2START - Start address of region 2 */
/*! @{ */

#define FLEXSPI_IPEDCTX2START_GCM_MASK           (0x1U)
#define FLEXSPI_IPEDCTX2START_GCM_SHIFT          (0U)
/*! GCM - If this bit is 1, current region is GCM mode region.
 */
#define FLEXSPI_IPEDCTX2START_GCM(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX2START_GCM_SHIFT)) & FLEXSPI_IPEDCTX2START_GCM_MASK)

#define FLEXSPI_IPEDCTX2START_ahbbuserror_dis_MASK (0x2U)
#define FLEXSPI_IPEDCTX2START_ahbbuserror_dis_SHIFT (1U)
/*! ahbbuserror_dis - If this bit is 1, ahb bus error is disable.
 */
#define FLEXSPI_IPEDCTX2START_ahbbuserror_dis(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX2START_ahbbuserror_dis_SHIFT)) & FLEXSPI_IPEDCTX2START_ahbbuserror_dis_MASK)

#define FLEXSPI_IPEDCTX2START_start_address_MASK (0xFFFFFF00U)
#define FLEXSPI_IPEDCTX2START_start_address_SHIFT (8U)
/*! start_address - Start address of region 2. Minimal 256 Bytes aligned. It is system address.
 */
#define FLEXSPI_IPEDCTX2START_start_address(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX2START_start_address_SHIFT)) & FLEXSPI_IPEDCTX2START_start_address_MASK)
/*! @} */

/*! @name IPEDCTX2END - End address of region 2 */
/*! @{ */

#define FLEXSPI_IPEDCTX2END_end_address_MASK     (0xFFFFFF00U)
#define FLEXSPI_IPEDCTX2END_end_address_SHIFT    (8U)
/*! end_address - End address of region 2. Minimal 256 Bytes aligned. It is system address.
 */
#define FLEXSPI_IPEDCTX2END_end_address(x)       (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX2END_end_address_SHIFT)) & FLEXSPI_IPEDCTX2END_end_address_MASK)
/*! @} */

/*! @name IPEDCTX2AAD0 - IPED context2 AAD0 */
/*! @{ */

#define FLEXSPI_IPEDCTX2AAD0_CTX2_AAD0_MASK      (0xFFFFFFFFU)
#define FLEXSPI_IPEDCTX2AAD0_CTX2_AAD0_SHIFT     (0U)
/*! CTX2_AAD0 - Lowest 32 bits of AAD for region 2.
 */
#define FLEXSPI_IPEDCTX2AAD0_CTX2_AAD0(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX2AAD0_CTX2_AAD0_SHIFT)) & FLEXSPI_IPEDCTX2AAD0_CTX2_AAD0_MASK)
/*! @} */

/*! @name IPEDCTX2AAD1 - IPED context2 AAD1 */
/*! @{ */

#define FLEXSPI_IPEDCTX2AAD1_CTX2_AAD1_MASK      (0xFFFFFFFFU)
#define FLEXSPI_IPEDCTX2AAD1_CTX2_AAD1_SHIFT     (0U)
/*! CTX2_AAD1 - Highest 32 bits of AAD for region 2.
 */
#define FLEXSPI_IPEDCTX2AAD1_CTX2_AAD1(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX2AAD1_CTX2_AAD1_SHIFT)) & FLEXSPI_IPEDCTX2AAD1_CTX2_AAD1_MASK)
/*! @} */

/*! @name IPEDCTX3IV0 - IPED context3 IV0 */
/*! @{ */

#define FLEXSPI_IPEDCTX3IV0_CTX3_IV0_MASK        (0xFFFFFFFFU)
#define FLEXSPI_IPEDCTX3IV0_CTX3_IV0_SHIFT       (0U)
/*! CTX3_IV0 - Lowest 32 bits of IV for region 3.
 */
#define FLEXSPI_IPEDCTX3IV0_CTX3_IV0(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX3IV0_CTX3_IV0_SHIFT)) & FLEXSPI_IPEDCTX3IV0_CTX3_IV0_MASK)
/*! @} */

/*! @name IPEDCTX3IV1 - IPED context3 IV1 */
/*! @{ */

#define FLEXSPI_IPEDCTX3IV1_CTX3_IV1_MASK        (0xFFFFFFFFU)
#define FLEXSPI_IPEDCTX3IV1_CTX3_IV1_SHIFT       (0U)
/*! CTX3_IV1 - Highest 32 bits of IV for region 3.
 */
#define FLEXSPI_IPEDCTX3IV1_CTX3_IV1(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX3IV1_CTX3_IV1_SHIFT)) & FLEXSPI_IPEDCTX3IV1_CTX3_IV1_MASK)
/*! @} */

/*! @name IPEDCTX3START - Start address of region 3 */
/*! @{ */

#define FLEXSPI_IPEDCTX3START_GCM_MASK           (0x1U)
#define FLEXSPI_IPEDCTX3START_GCM_SHIFT          (0U)
/*! GCM - If this bit is 1, current region is GCM mode region.
 */
#define FLEXSPI_IPEDCTX3START_GCM(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX3START_GCM_SHIFT)) & FLEXSPI_IPEDCTX3START_GCM_MASK)

#define FLEXSPI_IPEDCTX3START_ahbbuserror_dis_MASK (0x2U)
#define FLEXSPI_IPEDCTX3START_ahbbuserror_dis_SHIFT (1U)
/*! ahbbuserror_dis - If this bit is 1, ahb bus error is disable.
 */
#define FLEXSPI_IPEDCTX3START_ahbbuserror_dis(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX3START_ahbbuserror_dis_SHIFT)) & FLEXSPI_IPEDCTX3START_ahbbuserror_dis_MASK)

#define FLEXSPI_IPEDCTX3START_start_address_MASK (0xFFFFFF00U)
#define FLEXSPI_IPEDCTX3START_start_address_SHIFT (8U)
/*! start_address - Start address of region 3. Minimal 256 Bytes aligned. It is system address.
 */
#define FLEXSPI_IPEDCTX3START_start_address(x)   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX3START_start_address_SHIFT)) & FLEXSPI_IPEDCTX3START_start_address_MASK)
/*! @} */

/*! @name IPEDCTX3END - End address of region 3 */
/*! @{ */

#define FLEXSPI_IPEDCTX3END_end_address_MASK     (0xFFFFFF00U)
#define FLEXSPI_IPEDCTX3END_end_address_SHIFT    (8U)
/*! end_address - End address of region 3. Minimal 256 Bytes aligned. It is system address.
 */
#define FLEXSPI_IPEDCTX3END_end_address(x)       (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX3END_end_address_SHIFT)) & FLEXSPI_IPEDCTX3END_end_address_MASK)
/*! @} */

/*! @name IPEDCTX3AAD0 - IPED context3 AAD0 */
/*! @{ */

#define FLEXSPI_IPEDCTX3AAD0_CTX3_AAD0_MASK      (0xFFFFFFFFU)
#define FLEXSPI_IPEDCTX3AAD0_CTX3_AAD0_SHIFT     (0U)
/*! CTX3_AAD0 - Lowest 32 bits of AAD for region 3.
 */
#define FLEXSPI_IPEDCTX3AAD0_CTX3_AAD0(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX3AAD0_CTX3_AAD0_SHIFT)) & FLEXSPI_IPEDCTX3AAD0_CTX3_AAD0_MASK)
/*! @} */

/*! @name IPEDCTX3AAD1 - IPED context3 AAD1 */
/*! @{ */

#define FLEXSPI_IPEDCTX3AAD1_CTX3_AAD1_MASK      (0xFFFFFFFFU)
#define FLEXSPI_IPEDCTX3AAD1_CTX3_AAD1_SHIFT     (0U)
/*! CTX3_AAD1 - Highest 32 bits of AAD for region 3.
 */
#define FLEXSPI_IPEDCTX3AAD1_CTX3_AAD1(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPEDCTX3AAD1_CTX3_AAD1_SHIFT)) & FLEXSPI_IPEDCTX3AAD1_CTX3_AAD1_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group FLEXSPI_Register_Masks */


/* FLEXSPI - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral FLEXSPI0 base address */
  #define FLEXSPI0_BASE                            (0x500C0000u)
  /** Peripheral FLEXSPI0 base address */
  #define FLEXSPI0_BASE_NS                         (0x400C0000u)
  /** Peripheral FLEXSPI0 base pointer */
  #define FLEXSPI0                                 ((FLEXSPI_Type *)FLEXSPI0_BASE)
  /** Peripheral FLEXSPI0 base pointer */
  #define FLEXSPI0_NS                              ((FLEXSPI_Type *)FLEXSPI0_BASE_NS)
  /** Array initializer of FLEXSPI peripheral base addresses */
  #define FLEXSPI_BASE_ADDRS                       { FLEXSPI0_BASE }
  /** Array initializer of FLEXSPI peripheral base pointers */
  #define FLEXSPI_BASE_PTRS                        { FLEXSPI0 }
  /** Array initializer of FLEXSPI peripheral base addresses */
  #define FLEXSPI_BASE_ADDRS_NS                    { FLEXSPI0_BASE_NS }
  /** Array initializer of FLEXSPI peripheral base pointers */
  #define FLEXSPI_BASE_PTRS_NS                     { FLEXSPI0_NS }
#else
  /** Peripheral FLEXSPI0 base address */
  #define FLEXSPI0_BASE                            (0x400C0000u)
  /** Peripheral FLEXSPI0 base pointer */
  #define FLEXSPI0                                 ((FLEXSPI_Type *)FLEXSPI0_BASE)
  /** Array initializer of FLEXSPI peripheral base addresses */
  #define FLEXSPI_BASE_ADDRS                       { FLEXSPI0_BASE }
  /** Array initializer of FLEXSPI peripheral base pointers */
  #define FLEXSPI_BASE_PTRS                        { FLEXSPI0 }
#endif
/** Interrupt vectors for the FLEXSPI peripheral type */
#define FLEXSPI_IRQS                             { FlexSPI0_IRQn }
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
/** FlexSPI0 AMBA address */
#define FlexSPI0_AMBA_BASE                        (0x18000000u)
/** FlexSPI0 AMBA address */
#define FlexSPI0_AMBA_BASE_NS                     (0x08000000u)
#else
/** FlexSPI0 AMBA address */
#define FlexSPI0_AMBA_BASE                        (0x08000000u)
#endif


/*!
 * @}
 */ /* end of group FLEXSPI_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- FREQME Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup FREQME_Peripheral_Access_Layer FREQME Peripheral Access Layer
 * @{
 */

/** FREQME - Register Layout Typedef */
typedef struct {
  union {                                          /* offset: 0x0 */
    __I  uint32_t FREQMECTRL_R;                      /**< Frequency Measurement (in Read mode), offset: 0x0 */
    __O  uint32_t FREQMECTRL_W;                      /**< Frequency Measurement (in Write mode), offset: 0x0 */
  };
  __IO uint32_t FREQMECTRLSTAT;                    /**< Frequency Measurement Control Status, offset: 0x4 */
  __IO uint32_t FREQMEMIN;                         /**< Frequency Measurement Minimum, offset: 0x8 */
  __IO uint32_t FREQMEMAX;                         /**< Frequency Measurement Maximum, offset: 0xC */
} FREQME_Type;

/* ----------------------------------------------------------------------------
   -- FREQME Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup FREQME_Register_Masks FREQME Register Masks
 * @{
 */

/*! @name FREQMECTRL_R - Frequency Measurement (in Read mode) */
/*! @{ */

#define FREQME_FREQMECTRL_R_RESULT_MASK          (0x7FFFFFFFU)
#define FREQME_FREQMECTRL_R_RESULT_SHIFT         (0U)
/*! RESULT - Result
 */
#define FREQME_FREQMECTRL_R_RESULT(x)            (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRL_R_RESULT_SHIFT)) & FREQME_FREQMECTRL_R_RESULT_MASK)

#define FREQME_FREQMECTRL_R_MEASURE_IN_PROGRESS_MASK (0x80000000U)
#define FREQME_FREQMECTRL_R_MEASURE_IN_PROGRESS_SHIFT (31U)
/*! MEASURE_IN_PROGRESS - Measure in Progress
 *  0b0..Process complete. Measurement cycle is complete. The results are ready in the RESULT field.
 *  0b1..In Progress. Measurement cycle is in progress.
 */
#define FREQME_FREQMECTRL_R_MEASURE_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRL_R_MEASURE_IN_PROGRESS_SHIFT)) & FREQME_FREQMECTRL_R_MEASURE_IN_PROGRESS_MASK)
/*! @} */

/*! @name FREQMECTRL_W - Frequency Measurement (in Write mode) */
/*! @{ */

#define FREQME_FREQMECTRL_W_REF_SCALE_MASK       (0x1FU)
#define FREQME_FREQMECTRL_W_REF_SCALE_SHIFT      (0U)
/*! REF_SCALE - Reference Clock Scaling Factor
 *  0b00000..Count cycle = 2 ^ 0 = 1
 *  0b00001..Count cycle = 2 ^ 1 = 2
 *  0b00010..Count cycle = 2 ^ 2 = 4
 *  0b11111..Count cycle = 2 ^ 31 = 2,147,483,648
 */
#define FREQME_FREQMECTRL_W_REF_SCALE(x)         (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRL_W_REF_SCALE_SHIFT)) & FREQME_FREQMECTRL_W_REF_SCALE_MASK)

#define FREQME_FREQMECTRL_W_PULSE_MODE_MASK      (0x100U)
#define FREQME_FREQMECTRL_W_PULSE_MODE_SHIFT     (8U)
/*! PULSE_MODE - Pulse Width Measurement mode select
 *  0b0..Frequency Measurement Mode. FREQMECTRL works in a Frequency Measurement mode. Once the measurement starts
 *       (real count start is aligned at rising edge arrival on reference clock), the target counter increments by
 *       the target clock until the reference counter running by the reference clock reaches the count end point
 *       selected by REF_SCALE.
 *  0b1..Pulse Width Measurement mode. FREQMECTRL works in a Pulse Width Measurement mode, measuring the high or
 *       low period of reference clock input selected by PULSE_POL. The target counter starts incrementing by the
 *       target clock once a corresponding trigger edge (rising edge for high period measurement and falling edge for
 *       low period) occurs.
 */
#define FREQME_FREQMECTRL_W_PULSE_MODE(x)        (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRL_W_PULSE_MODE_SHIFT)) & FREQME_FREQMECTRL_W_PULSE_MODE_MASK)

#define FREQME_FREQMECTRL_W_PULSE_POL_MASK       (0x200U)
#define FREQME_FREQMECTRL_W_PULSE_POL_SHIFT      (9U)
/*! PULSE_POL - Pulse Polarity
 *  0b0..High Period. High period of reference clock is measured in Pulse Width Measurement mode triggered by the
 *       rising edge on the reference clock input.
 *  0b1..Low Period. Low period of reference clock is measured in Pulse Width Measurement mode triggered by the
 *       falling edge on the reference clock input.
 */
#define FREQME_FREQMECTRL_W_PULSE_POL(x)         (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRL_W_PULSE_POL_SHIFT)) & FREQME_FREQMECTRL_W_PULSE_POL_MASK)

#define FREQME_FREQMECTRL_W_LT_MIN_INT_EN_MASK   (0x1000U)
#define FREQME_FREQMECTRL_W_LT_MIN_INT_EN_SHIFT  (12U)
/*! LT_MIN_INT_EN - Less Than Minimum Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define FREQME_FREQMECTRL_W_LT_MIN_INT_EN(x)     (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRL_W_LT_MIN_INT_EN_SHIFT)) & FREQME_FREQMECTRL_W_LT_MIN_INT_EN_MASK)

#define FREQME_FREQMECTRL_W_GT_MAX_INT_EN_MASK   (0x2000U)
#define FREQME_FREQMECTRL_W_GT_MAX_INT_EN_SHIFT  (13U)
/*! GT_MAX_INT_EN - Greater Than Maximum Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define FREQME_FREQMECTRL_W_GT_MAX_INT_EN(x)     (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRL_W_GT_MAX_INT_EN_SHIFT)) & FREQME_FREQMECTRL_W_GT_MAX_INT_EN_MASK)

#define FREQME_FREQMECTRL_W_RESULT_READY_INT_EN_MASK (0x4000U)
#define FREQME_FREQMECTRL_W_RESULT_READY_INT_EN_SHIFT (14U)
/*! RESULT_READY_INT_EN - Result Ready Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define FREQME_FREQMECTRL_W_RESULT_READY_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRL_W_RESULT_READY_INT_EN_SHIFT)) & FREQME_FREQMECTRL_W_RESULT_READY_INT_EN_MASK)

#define FREQME_FREQMECTRL_W_CONTINUOUS_MODE_EN_MASK (0x40000000U)
#define FREQME_FREQMECTRL_W_CONTINUOUS_MODE_EN_SHIFT (30U)
/*! CONTINUOUS_MODE_EN - Continuous Mode Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define FREQME_FREQMECTRL_W_CONTINUOUS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRL_W_CONTINUOUS_MODE_EN_SHIFT)) & FREQME_FREQMECTRL_W_CONTINUOUS_MODE_EN_MASK)

#define FREQME_FREQMECTRL_W_MEASURE_IN_PROGRESS_MASK (0x80000000U)
#define FREQME_FREQMECTRL_W_MEASURE_IN_PROGRESS_SHIFT (31U)
/*! MEASURE_IN_PROGRESS - Measure in Progress
 *  0b0..Force Terminate
 *  0b1..Initiates Measurement Cycle
 */
#define FREQME_FREQMECTRL_W_MEASURE_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRL_W_MEASURE_IN_PROGRESS_SHIFT)) & FREQME_FREQMECTRL_W_MEASURE_IN_PROGRESS_MASK)
/*! @} */

/*! @name FREQMECTRLSTAT - Frequency Measurement Control Status */
/*! @{ */

#define FREQME_FREQMECTRLSTAT_REF_SCALE_MASK     (0x1FU)
#define FREQME_FREQMECTRLSTAT_REF_SCALE_SHIFT    (0U)
/*! REF_SCALE - Reference Scale Value
 */
#define FREQME_FREQMECTRLSTAT_REF_SCALE(x)       (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRLSTAT_REF_SCALE_SHIFT)) & FREQME_FREQMECTRLSTAT_REF_SCALE_MASK)

#define FREQME_FREQMECTRLSTAT_PULSE_MODE_MASK    (0x100U)
#define FREQME_FREQMECTRLSTAT_PULSE_MODE_SHIFT   (8U)
/*! PULSE_MODE - Pulse Mode Status
 */
#define FREQME_FREQMECTRLSTAT_PULSE_MODE(x)      (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRLSTAT_PULSE_MODE_SHIFT)) & FREQME_FREQMECTRLSTAT_PULSE_MODE_MASK)

#define FREQME_FREQMECTRLSTAT_PULSE_POL_MASK     (0x200U)
#define FREQME_FREQMECTRLSTAT_PULSE_POL_SHIFT    (9U)
/*! PULSE_POL - Pulse Polarity Status
 */
#define FREQME_FREQMECTRLSTAT_PULSE_POL(x)       (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRLSTAT_PULSE_POL_SHIFT)) & FREQME_FREQMECTRLSTAT_PULSE_POL_MASK)

#define FREQME_FREQMECTRLSTAT_LT_MIN_INT_EN_MASK (0x1000U)
#define FREQME_FREQMECTRLSTAT_LT_MIN_INT_EN_SHIFT (12U)
/*! LT_MIN_INT_EN - Less Than Minimum Interrupt Enable Status
 */
#define FREQME_FREQMECTRLSTAT_LT_MIN_INT_EN(x)   (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRLSTAT_LT_MIN_INT_EN_SHIFT)) & FREQME_FREQMECTRLSTAT_LT_MIN_INT_EN_MASK)

#define FREQME_FREQMECTRLSTAT_GT_MAX_INT_EN_MASK (0x2000U)
#define FREQME_FREQMECTRLSTAT_GT_MAX_INT_EN_SHIFT (13U)
/*! GT_MAX_INT_EN - Greater Then Maximum Interrupt Enable Status
 */
#define FREQME_FREQMECTRLSTAT_GT_MAX_INT_EN(x)   (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRLSTAT_GT_MAX_INT_EN_SHIFT)) & FREQME_FREQMECTRLSTAT_GT_MAX_INT_EN_MASK)

#define FREQME_FREQMECTRLSTAT_RESULT_READY_INT_EN_MASK (0x4000U)
#define FREQME_FREQMECTRLSTAT_RESULT_READY_INT_EN_SHIFT (14U)
/*! RESULT_READY_INT_EN - Result Ready Interrupt Enable Status
 */
#define FREQME_FREQMECTRLSTAT_RESULT_READY_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRLSTAT_RESULT_READY_INT_EN_SHIFT)) & FREQME_FREQMECTRLSTAT_RESULT_READY_INT_EN_MASK)

#define FREQME_FREQMECTRLSTAT_LT_MIN_STAT_MASK   (0x1000000U)
#define FREQME_FREQMECTRLSTAT_LT_MIN_STAT_SHIFT  (24U)
/*! LT_MIN_STAT - Less Than Minimum Results Status
 */
#define FREQME_FREQMECTRLSTAT_LT_MIN_STAT(x)     (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRLSTAT_LT_MIN_STAT_SHIFT)) & FREQME_FREQMECTRLSTAT_LT_MIN_STAT_MASK)

#define FREQME_FREQMECTRLSTAT_GT_MAX_STAT_MASK   (0x2000000U)
#define FREQME_FREQMECTRLSTAT_GT_MAX_STAT_SHIFT  (25U)
/*! GT_MAX_STAT - Greater Than Maximum Result Status
 */
#define FREQME_FREQMECTRLSTAT_GT_MAX_STAT(x)     (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRLSTAT_GT_MAX_STAT_SHIFT)) & FREQME_FREQMECTRLSTAT_GT_MAX_STAT_MASK)

#define FREQME_FREQMECTRLSTAT_RESULT_READY_STAT_MASK (0x4000000U)
#define FREQME_FREQMECTRLSTAT_RESULT_READY_STAT_SHIFT (26U)
/*! RESULT_READY_STAT - Result Ready Status
 */
#define FREQME_FREQMECTRLSTAT_RESULT_READY_STAT(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRLSTAT_RESULT_READY_STAT_SHIFT)) & FREQME_FREQMECTRLSTAT_RESULT_READY_STAT_MASK)

#define FREQME_FREQMECTRLSTAT_CONTINUOUS_MODE_EN_MASK (0x40000000U)
#define FREQME_FREQMECTRLSTAT_CONTINUOUS_MODE_EN_SHIFT (30U)
/*! CONTINUOUS_MODE_EN - Continuous Mode Enable Status
 */
#define FREQME_FREQMECTRLSTAT_CONTINUOUS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRLSTAT_CONTINUOUS_MODE_EN_SHIFT)) & FREQME_FREQMECTRLSTAT_CONTINUOUS_MODE_EN_MASK)

#define FREQME_FREQMECTRLSTAT_MEASURE_IN_PROGRESS_MASK (0x80000000U)
#define FREQME_FREQMECTRLSTAT_MEASURE_IN_PROGRESS_SHIFT (31U)
/*! MEASURE_IN_PROGRESS - Measure in Progress Status
 */
#define FREQME_FREQMECTRLSTAT_MEASURE_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRLSTAT_MEASURE_IN_PROGRESS_SHIFT)) & FREQME_FREQMECTRLSTAT_MEASURE_IN_PROGRESS_MASK)
/*! @} */

/*! @name FREQMEMIN - Frequency Measurement Minimum */
/*! @{ */

#define FREQME_FREQMEMIN_MIN_VALUE_MASK          (0x7FFFFFFFU)
#define FREQME_FREQMEMIN_MIN_VALUE_SHIFT         (0U)
/*! MIN_VALUE - Minumum Value
 */
#define FREQME_FREQMEMIN_MIN_VALUE(x)            (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMEMIN_MIN_VALUE_SHIFT)) & FREQME_FREQMEMIN_MIN_VALUE_MASK)
/*! @} */

/*! @name FREQMEMAX - Frequency Measurement Maximum */
/*! @{ */

#define FREQME_FREQMEMAX_MAX_VALUE_MASK          (0x7FFFFFFFU)
#define FREQME_FREQMEMAX_MAX_VALUE_SHIFT         (0U)
/*! MAX_VALUE - Maximum Value
 */
#define FREQME_FREQMEMAX_MAX_VALUE(x)            (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMEMAX_MAX_VALUE_SHIFT)) & FREQME_FREQMEMAX_MAX_VALUE_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group FREQME_Register_Masks */


/* FREQME - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral FREQME base address */
  #define FREQME_BASE                              (0x50013140u)
  /** Peripheral FREQME base address */
  #define FREQME_BASE_NS                           (0x40013140u)
  /** Peripheral FREQME base pointer */
  #define FREQME                                   ((FREQME_Type *)FREQME_BASE)
  /** Peripheral FREQME base pointer */
  #define FREQME_NS                                ((FREQME_Type *)FREQME_BASE_NS)
  /** Array initializer of FREQME peripheral base addresses */
  #define FREQME_BASE_ADDRS                        { FREQME_BASE }
  /** Array initializer of FREQME peripheral base pointers */
  #define FREQME_BASE_PTRS                         { FREQME }
  /** Array initializer of FREQME peripheral base addresses */
  #define FREQME_BASE_ADDRS_NS                     { FREQME_BASE_NS }
  /** Array initializer of FREQME peripheral base pointers */
  #define FREQME_BASE_PTRS_NS                      { FREQME_NS }
#else
  /** Peripheral FREQME base address */
  #define FREQME_BASE                              (0x40013140u)
  /** Peripheral FREQME base pointer */
  #define FREQME                                   ((FREQME_Type *)FREQME_BASE)
  /** Array initializer of FREQME peripheral base addresses */
  #define FREQME_BASE_ADDRS                        { FREQME_BASE }
  /** Array initializer of FREQME peripheral base pointers */
  #define FREQME_BASE_PTRS                         { FREQME }
#endif
/** Interrupt vectors for the FREQME peripheral type */
#define FREQME_IRQS                              { Freqme_IRQn }

/*!
 * @}
 */ /* end of group FREQME_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- GINT Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup GINT_Peripheral_Access_Layer GINT Peripheral Access Layer
 * @{
 */

/** GINT - Register Layout Typedef */
typedef struct {
  __IO uint32_t CTRL;                              /**< GPIO grouped interrupt control, offset: 0x0 */
       uint8_t RESERVED_0[28];
  __IO uint32_t PORT_POL[2];                       /**< Port polarity, array offset: 0x20, array step: 0x4 */
       uint8_t RESERVED_1[24];
  __IO uint32_t PORT_ENA[2];                       /**< GPIO grouped interrupt port 0 enable register, array offset: 0x40, array step: 0x4 */
} GINT_Type;

/* ----------------------------------------------------------------------------
   -- GINT Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup GINT_Register_Masks GINT Register Masks
 * @{
 */

/*! @name CTRL - GPIO grouped interrupt control */
/*! @{ */

#define GINT_CTRL_INT_MASK                       (0x1U)
#define GINT_CTRL_INT_SHIFT                      (0U)
/*! INT - Group interrupt status
 *  0b0..No interrupt request is pending.
 *  0b1..Interrupt request is pending.
 */
#define GINT_CTRL_INT(x)                         (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK)

#define GINT_CTRL_COMB_MASK                      (0x2U)
#define GINT_CTRL_COMB_SHIFT                     (1U)
/*! COMB - Combine enabled inputs for group interrupt
 *  0b0..OR functionality
 *  0b1..AND functionality
 */
#define GINT_CTRL_COMB(x)                        (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_COMB_SHIFT)) & GINT_CTRL_COMB_MASK)

#define GINT_CTRL_TRIG_MASK                      (0x4U)
#define GINT_CTRL_TRIG_SHIFT                     (2U)
/*! TRIG - Group interrupt trigger
 *  0b0..Edge-triggered
 *  0b1..Level-triggered
 */
#define GINT_CTRL_TRIG(x)                        (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_TRIG_SHIFT)) & GINT_CTRL_TRIG_MASK)
/*! @} */

/*! @name PORT_POL - Port polarity */
/*! @{ */

#define GINT_PORT_POL_POL0_MASK                  (0x1U)
#define GINT_PORT_POL_POL0_SHIFT                 (0U)
/*! POL0 - Polarity of pin n of the port
 *  0b0..Pin is active LOW
 *  0b1..Pin is active HIGH
 */
#define GINT_PORT_POL_POL0(x)                    (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL0_SHIFT)) & GINT_PORT_POL_POL0_MASK)

#define GINT_PORT_POL_POL1_MASK                  (0x2U)
#define GINT_PORT_POL_POL1_SHIFT                 (1U)
/*! POL1 - Polarity of pin n of the port
 *  0b0..Pin is active LOW
 *  0b1..Pin is active HIGH
 */
#define GINT_PORT_POL_POL1(x)                    (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL1_SHIFT)) & GINT_PORT_POL_POL1_MASK)

#define GINT_PORT_POL_POL2_MASK                  (0x4U)
#define GINT_PORT_POL_POL2_SHIFT                 (2U)
/*! POL2 - Polarity of pin n of the port
 *  0b0..Pin is active LOW
 *  0b1..Pin is active HIGH
 */
#define GINT_PORT_POL_POL2(x)                    (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL2_SHIFT)) & GINT_PORT_POL_POL2_MASK)

#define GINT_PORT_POL_POL3_MASK                  (0x8U)
#define GINT_PORT_POL_POL3_SHIFT                 (3U)
/*! POL3 - Polarity of pin n of the port
 *  0b0..Pin is active LOW
 *  0b1..Pin is active HIGH
 */
#define GINT_PORT_POL_POL3(x)                    (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL3_SHIFT)) & GINT_PORT_POL_POL3_MASK)

#define GINT_PORT_POL_POL4_MASK                  (0x10U)
#define GINT_PORT_POL_POL4_SHIFT                 (4U)
/*! POL4 - Polarity of pin n of the port
 *  0b0..Pin is active LOW
 *  0b1..Pin is active HIGH
 */
#define GINT_PORT_POL_POL4(x)                    (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL4_SHIFT)) & GINT_PORT_POL_POL4_MASK)

#define GINT_PORT_POL_POL5_MASK                  (0x20U)
#define GINT_PORT_POL_POL5_SHIFT                 (5U)
/*! POL5 - Polarity of pin n of the port
 *  0b0..Pin is active LOW
 *  0b1..Pin is active HIGH
 */
#define GINT_PORT_POL_POL5(x)                    (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL5_SHIFT)) & GINT_PORT_POL_POL5_MASK)

#define GINT_PORT_POL_POL6_MASK                  (0x40U)
#define GINT_PORT_POL_POL6_SHIFT                 (6U)
/*! POL6 - Polarity of pin n of the port
 *  0b0..Pin is active LOW
 *  0b1..Pin is active HIGH
 */
#define GINT_PORT_POL_POL6(x)                    (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL6_SHIFT)) & GINT_PORT_POL_POL6_MASK)

#define GINT_PORT_POL_POL7_MASK                  (0x80U)
#define GINT_PORT_POL_POL7_SHIFT                 (7U)
/*! POL7 - Polarity of pin n of the port
 *  0b0..Pin is active LOW
 *  0b1..Pin is active HIGH
 */
#define GINT_PORT_POL_POL7(x)                    (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL7_SHIFT)) & GINT_PORT_POL_POL7_MASK)

#define GINT_PORT_POL_POL8_MASK                  (0x100U)
#define GINT_PORT_POL_POL8_SHIFT                 (8U)
/*! POL8 - Polarity of pin n of the port
 *  0b0..Pin is active LOW
 *  0b1..Pin is active HIGH
 */
#define GINT_PORT_POL_POL8(x)                    (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL8_SHIFT)) & GINT_PORT_POL_POL8_MASK)

#define GINT_PORT_POL_POL9_MASK                  (0x200U)
#define GINT_PORT_POL_POL9_SHIFT                 (9U)
/*! POL9 - Polarity of pin n of the port
 *  0b0..Pin is active LOW
 *  0b1..Pin is active HIGH
 */
#define GINT_PORT_POL_POL9(x)                    (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL9_SHIFT)) & GINT_PORT_POL_POL9_MASK)

#define GINT_PORT_POL_POL10_MASK                 (0x400U)
#define GINT_PORT_POL_POL10_SHIFT                (10U)
/*! POL10 - Polarity of pin n of the port
 *  0b0..Pin is active LOW
 *  0b1..Pin is active HIGH
 */
#define GINT_PORT_POL_POL10(x)                   (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL10_SHIFT)) & GINT_PORT_POL_POL10_MASK)

#define GINT_PORT_POL_POL11_MASK                 (0x800U)
#define GINT_PORT_POL_POL11_SHIFT                (11U)
/*! POL11 - Polarity of pin n of the port
 *  0b0..Pin is active LOW
 *  0b1..Pin is active HIGH
 */
#define GINT_PORT_POL_POL11(x)                   (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL11_SHIFT)) & GINT_PORT_POL_POL11_MASK)

#define GINT_PORT_POL_POL12_MASK                 (0x1000U)
#define GINT_PORT_POL_POL12_SHIFT                (12U)
/*! POL12 - Polarity of pin n of the port
 *  0b0..Pin is active LOW
 *  0b1..Pin is active HIGH
 */
#define GINT_PORT_POL_POL12(x)                   (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL12_SHIFT)) & GINT_PORT_POL_POL12_MASK)

#define GINT_PORT_POL_POL13_MASK                 (0x2000U)
#define GINT_PORT_POL_POL13_SHIFT                (13U)
/*! POL13 - Polarity of pin n of the port
 *  0b0..Pin is active LOW
 *  0b1..Pin is active HIGH
 */
#define GINT_PORT_POL_POL13(x)                   (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL13_SHIFT)) & GINT_PORT_POL_POL13_MASK)

#define GINT_PORT_POL_POL14_MASK                 (0x4000U)
#define GINT_PORT_POL_POL14_SHIFT                (14U)
/*! POL14 - Polarity of pin n of the port
 *  0b0..Pin is active LOW
 *  0b1..Pin is active HIGH
 */
#define GINT_PORT_POL_POL14(x)                   (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL14_SHIFT)) & GINT_PORT_POL_POL14_MASK)

#define GINT_PORT_POL_POL15_MASK                 (0x8000U)
#define GINT_PORT_POL_POL15_SHIFT                (15U)
/*! POL15 - Polarity of pin n of the port
 *  0b0..Pin is active LOW
 *  0b1..Pin is active HIGH
 */
#define GINT_PORT_POL_POL15(x)                   (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL15_SHIFT)) & GINT_PORT_POL_POL15_MASK)

#define GINT_PORT_POL_POL16_MASK                 (0x10000U)
#define GINT_PORT_POL_POL16_SHIFT                (16U)
/*! POL16 - Polarity of pin n of the port
 *  0b0..Pin is active LOW
 *  0b1..Pin is active HIGH
 */
#define GINT_PORT_POL_POL16(x)                   (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL16_SHIFT)) & GINT_PORT_POL_POL16_MASK)

#define GINT_PORT_POL_POL17_MASK                 (0x20000U)
#define GINT_PORT_POL_POL17_SHIFT                (17U)
/*! POL17 - Polarity of pin n of the port
 *  0b0..Pin is active LOW
 *  0b1..Pin is active HIGH
 */
#define GINT_PORT_POL_POL17(x)                   (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL17_SHIFT)) & GINT_PORT_POL_POL17_MASK)

#define GINT_PORT_POL_POL18_MASK                 (0x40000U)
#define GINT_PORT_POL_POL18_SHIFT                (18U)
/*! POL18 - Polarity of pin n of the port
 *  0b0..Pin is active LOW
 *  0b1..Pin is active HIGH
 */
#define GINT_PORT_POL_POL18(x)                   (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL18_SHIFT)) & GINT_PORT_POL_POL18_MASK)

#define GINT_PORT_POL_POL19_MASK                 (0x80000U)
#define GINT_PORT_POL_POL19_SHIFT                (19U)
/*! POL19 - Polarity of pin n of the port
 *  0b0..Pin is active LOW
 *  0b1..Pin is active HIGH
 */
#define GINT_PORT_POL_POL19(x)                   (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL19_SHIFT)) & GINT_PORT_POL_POL19_MASK)

#define GINT_PORT_POL_POL20_MASK                 (0x100000U)
#define GINT_PORT_POL_POL20_SHIFT                (20U)
/*! POL20 - Polarity of pin n of the port
 *  0b0..Pin is active LOW
 *  0b1..Pin is active HIGH
 */
#define GINT_PORT_POL_POL20(x)                   (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL20_SHIFT)) & GINT_PORT_POL_POL20_MASK)

#define GINT_PORT_POL_POL21_MASK                 (0x200000U)
#define GINT_PORT_POL_POL21_SHIFT                (21U)
/*! POL21 - Polarity of pin n of the port
 *  0b0..Pin is active LOW
 *  0b1..Pin is active HIGH
 */
#define GINT_PORT_POL_POL21(x)                   (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL21_SHIFT)) & GINT_PORT_POL_POL21_MASK)

#define GINT_PORT_POL_POL22_MASK                 (0x400000U)
#define GINT_PORT_POL_POL22_SHIFT                (22U)
/*! POL22 - Polarity of pin n of the port
 *  0b0..Pin is active LOW
 *  0b1..Pin is active HIGH
 */
#define GINT_PORT_POL_POL22(x)                   (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL22_SHIFT)) & GINT_PORT_POL_POL22_MASK)

#define GINT_PORT_POL_POL23_MASK                 (0x800000U)
#define GINT_PORT_POL_POL23_SHIFT                (23U)
/*! POL23 - Polarity of pin n of the port
 *  0b0..Pin is active LOW
 *  0b1..Pin is active HIGH
 */
#define GINT_PORT_POL_POL23(x)                   (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL23_SHIFT)) & GINT_PORT_POL_POL23_MASK)

#define GINT_PORT_POL_POL24_MASK                 (0x1000000U)
#define GINT_PORT_POL_POL24_SHIFT                (24U)
/*! POL24 - Polarity of pin n of the port
 *  0b0..Pin is active LOW
 *  0b1..Pin is active HIGH
 */
#define GINT_PORT_POL_POL24(x)                   (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL24_SHIFT)) & GINT_PORT_POL_POL24_MASK)

#define GINT_PORT_POL_POL25_MASK                 (0x2000000U)
#define GINT_PORT_POL_POL25_SHIFT                (25U)
/*! POL25 - Polarity of pin n of the port
 *  0b0..Pin is active LOW
 *  0b1..Pin is active HIGH
 */
#define GINT_PORT_POL_POL25(x)                   (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL25_SHIFT)) & GINT_PORT_POL_POL25_MASK)

#define GINT_PORT_POL_POL26_MASK                 (0x4000000U)
#define GINT_PORT_POL_POL26_SHIFT                (26U)
/*! POL26 - Polarity of pin n of the port
 *  0b0..Pin is active LOW
 *  0b1..Pin is active HIGH
 */
#define GINT_PORT_POL_POL26(x)                   (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL26_SHIFT)) & GINT_PORT_POL_POL26_MASK)

#define GINT_PORT_POL_POL27_MASK                 (0x8000000U)
#define GINT_PORT_POL_POL27_SHIFT                (27U)
/*! POL27 - Polarity of pin n of the port
 *  0b0..Pin is active LOW
 *  0b1..Pin is active HIGH
 */
#define GINT_PORT_POL_POL27(x)                   (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL27_SHIFT)) & GINT_PORT_POL_POL27_MASK)

#define GINT_PORT_POL_POL28_MASK                 (0x10000000U)
#define GINT_PORT_POL_POL28_SHIFT                (28U)
/*! POL28 - Polarity of pin n of the port
 *  0b0..Pin is active LOW
 *  0b1..Pin is active HIGH
 */
#define GINT_PORT_POL_POL28(x)                   (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL28_SHIFT)) & GINT_PORT_POL_POL28_MASK)

#define GINT_PORT_POL_POL29_MASK                 (0x20000000U)
#define GINT_PORT_POL_POL29_SHIFT                (29U)
/*! POL29 - Polarity of pin n of the port
 *  0b0..Pin is active LOW
 *  0b1..Pin is active HIGH
 */
#define GINT_PORT_POL_POL29(x)                   (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL29_SHIFT)) & GINT_PORT_POL_POL29_MASK)

#define GINT_PORT_POL_POL30_MASK                 (0x40000000U)
#define GINT_PORT_POL_POL30_SHIFT                (30U)
/*! POL30 - Polarity of pin n of the port
 *  0b0..Pin is active LOW
 *  0b1..Pin is active HIGH
 */
#define GINT_PORT_POL_POL30(x)                   (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL30_SHIFT)) & GINT_PORT_POL_POL30_MASK)

#define GINT_PORT_POL_POL31_MASK                 (0x80000000U)
#define GINT_PORT_POL_POL31_SHIFT                (31U)
/*! POL31 - Polarity of pin n of the port
 *  0b0..Pin is active LOW
 *  0b1..Pin is active HIGH
 */
#define GINT_PORT_POL_POL31(x)                   (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL31_SHIFT)) & GINT_PORT_POL_POL31_MASK)
/*! @} */

/* The count of GINT_PORT_POL */
#define GINT_PORT_POL_COUNT                      (2U)

/*! @name PORT_ENA - GPIO grouped interrupt port 0 enable register */
/*! @{ */

#define GINT_PORT_ENA_ENA0_MASK                  (0x1U)
#define GINT_PORT_ENA_ENA0_SHIFT                 (0U)
/*! ENA0 - Enables port pin n to contribute to the group interrupt
 *  0b0..Pin is disabled and does not contribute to the grouped interrupt
 *  0b1..Pin is enabled and contributes to the grouped interrupt
 */
#define GINT_PORT_ENA_ENA0(x)                    (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA0_SHIFT)) & GINT_PORT_ENA_ENA0_MASK)

#define GINT_PORT_ENA_ENA1_MASK                  (0x2U)
#define GINT_PORT_ENA_ENA1_SHIFT                 (1U)
/*! ENA1 - Enables port pin n to contribute to the group interrupt
 *  0b0..Pin is disabled and does not contribute to the grouped interrupt
 *  0b1..Pin is enabled and contributes to the grouped interrupt
 */
#define GINT_PORT_ENA_ENA1(x)                    (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA1_SHIFT)) & GINT_PORT_ENA_ENA1_MASK)

#define GINT_PORT_ENA_ENA2_MASK                  (0x4U)
#define GINT_PORT_ENA_ENA2_SHIFT                 (2U)
/*! ENA2 - Enables port pin n to contribute to the group interrupt
 *  0b0..Pin is disabled and does not contribute to the grouped interrupt
 *  0b1..Pin is enabled and contributes to the grouped interrupt
 */
#define GINT_PORT_ENA_ENA2(x)                    (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA2_SHIFT)) & GINT_PORT_ENA_ENA2_MASK)

#define GINT_PORT_ENA_ENA3_MASK                  (0x8U)
#define GINT_PORT_ENA_ENA3_SHIFT                 (3U)
/*! ENA3 - Enables port pin n to contribute to the group interrupt
 *  0b0..Pin is disabled and does not contribute to the grouped interrupt
 *  0b1..Pin is enabled and contributes to the grouped interrupt
 */
#define GINT_PORT_ENA_ENA3(x)                    (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA3_SHIFT)) & GINT_PORT_ENA_ENA3_MASK)

#define GINT_PORT_ENA_ENA4_MASK                  (0x10U)
#define GINT_PORT_ENA_ENA4_SHIFT                 (4U)
/*! ENA4 - Enables port pin n to contribute to the group interrupt
 *  0b0..Pin is disabled and does not contribute to the grouped interrupt
 *  0b1..Pin is enabled and contributes to the grouped interrupt
 */
#define GINT_PORT_ENA_ENA4(x)                    (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA4_SHIFT)) & GINT_PORT_ENA_ENA4_MASK)

#define GINT_PORT_ENA_ENA5_MASK                  (0x20U)
#define GINT_PORT_ENA_ENA5_SHIFT                 (5U)
/*! ENA5 - Enables port pin n to contribute to the group interrupt
 *  0b0..Pin is disabled and does not contribute to the grouped interrupt
 *  0b1..Pin is enabled and contributes to the grouped interrupt
 */
#define GINT_PORT_ENA_ENA5(x)                    (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA5_SHIFT)) & GINT_PORT_ENA_ENA5_MASK)

#define GINT_PORT_ENA_ENA6_MASK                  (0x40U)
#define GINT_PORT_ENA_ENA6_SHIFT                 (6U)
/*! ENA6 - Enables port pin n to contribute to the group interrupt
 *  0b0..Pin is disabled and does not contribute to the grouped interrupt
 *  0b1..Pin is enabled and contributes to the grouped interrupt
 */
#define GINT_PORT_ENA_ENA6(x)                    (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA6_SHIFT)) & GINT_PORT_ENA_ENA6_MASK)

#define GINT_PORT_ENA_ENA7_MASK                  (0x80U)
#define GINT_PORT_ENA_ENA7_SHIFT                 (7U)
/*! ENA7 - Enables port pin n to contribute to the group interrupt
 *  0b0..Pin is disabled and does not contribute to the grouped interrupt
 *  0b1..Pin is enabled and contributes to the grouped interrupt
 */
#define GINT_PORT_ENA_ENA7(x)                    (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA7_SHIFT)) & GINT_PORT_ENA_ENA7_MASK)

#define GINT_PORT_ENA_ENA8_MASK                  (0x100U)
#define GINT_PORT_ENA_ENA8_SHIFT                 (8U)
/*! ENA8 - Enables port pin n to contribute to the group interrupt
 *  0b0..Pin is disabled and does not contribute to the grouped interrupt
 *  0b1..Pin is enabled and contributes to the grouped interrupt
 */
#define GINT_PORT_ENA_ENA8(x)                    (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA8_SHIFT)) & GINT_PORT_ENA_ENA8_MASK)

#define GINT_PORT_ENA_ENA9_MASK                  (0x200U)
#define GINT_PORT_ENA_ENA9_SHIFT                 (9U)
/*! ENA9 - Enables port pin n to contribute to the group interrupt
 *  0b0..Pin is disabled and does not contribute to the grouped interrupt
 *  0b1..Pin is enabled and contributes to the grouped interrupt
 */
#define GINT_PORT_ENA_ENA9(x)                    (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA9_SHIFT)) & GINT_PORT_ENA_ENA9_MASK)

#define GINT_PORT_ENA_ENA10_MASK                 (0x400U)
#define GINT_PORT_ENA_ENA10_SHIFT                (10U)
/*! ENA10 - Enables port pin n to contribute to the group interrupt
 *  0b0..Pin is disabled and does not contribute to the grouped interrupt
 *  0b1..Pin is enabled and contributes to the grouped interrupt
 */
#define GINT_PORT_ENA_ENA10(x)                   (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA10_SHIFT)) & GINT_PORT_ENA_ENA10_MASK)

#define GINT_PORT_ENA_ENA11_MASK                 (0x800U)
#define GINT_PORT_ENA_ENA11_SHIFT                (11U)
/*! ENA11 - Enables port pin n to contribute to the group interrupt
 *  0b0..Pin is disabled and does not contribute to the grouped interrupt
 *  0b1..Pin is enabled and contributes to the grouped interrupt
 */
#define GINT_PORT_ENA_ENA11(x)                   (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA11_SHIFT)) & GINT_PORT_ENA_ENA11_MASK)

#define GINT_PORT_ENA_ENA12_MASK                 (0x1000U)
#define GINT_PORT_ENA_ENA12_SHIFT                (12U)
/*! ENA12 - Enables port pin n to contribute to the group interrupt
 *  0b0..Pin is disabled and does not contribute to the grouped interrupt
 *  0b1..Pin is enabled and contributes to the grouped interrupt
 */
#define GINT_PORT_ENA_ENA12(x)                   (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA12_SHIFT)) & GINT_PORT_ENA_ENA12_MASK)

#define GINT_PORT_ENA_ENA13_MASK                 (0x2000U)
#define GINT_PORT_ENA_ENA13_SHIFT                (13U)
/*! ENA13 - Enables port pin n to contribute to the group interrupt
 *  0b0..Pin is disabled and does not contribute to the grouped interrupt
 *  0b1..Pin is enabled and contributes to the grouped interrupt
 */
#define GINT_PORT_ENA_ENA13(x)                   (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA13_SHIFT)) & GINT_PORT_ENA_ENA13_MASK)

#define GINT_PORT_ENA_ENA14_MASK                 (0x4000U)
#define GINT_PORT_ENA_ENA14_SHIFT                (14U)
/*! ENA14 - Enables port pin n to contribute to the group interrupt
 *  0b0..Pin is disabled and does not contribute to the grouped interrupt
 *  0b1..Pin is enabled and contributes to the grouped interrupt
 */
#define GINT_PORT_ENA_ENA14(x)                   (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA14_SHIFT)) & GINT_PORT_ENA_ENA14_MASK)

#define GINT_PORT_ENA_ENA15_MASK                 (0x8000U)
#define GINT_PORT_ENA_ENA15_SHIFT                (15U)
/*! ENA15 - Enables port pin n to contribute to the group interrupt
 *  0b0..Pin is disabled and does not contribute to the grouped interrupt
 *  0b1..Pin is enabled and contributes to the grouped interrupt
 */
#define GINT_PORT_ENA_ENA15(x)                   (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA15_SHIFT)) & GINT_PORT_ENA_ENA15_MASK)

#define GINT_PORT_ENA_ENA16_MASK                 (0x10000U)
#define GINT_PORT_ENA_ENA16_SHIFT                (16U)
/*! ENA16 - Enables port pin n to contribute to the group interrupt
 *  0b0..Pin is disabled and does not contribute to the grouped interrupt
 *  0b1..Pin is enabled and contributes to the grouped interrupt
 */
#define GINT_PORT_ENA_ENA16(x)                   (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA16_SHIFT)) & GINT_PORT_ENA_ENA16_MASK)

#define GINT_PORT_ENA_ENA17_MASK                 (0x20000U)
#define GINT_PORT_ENA_ENA17_SHIFT                (17U)
/*! ENA17 - Enables port pin n to contribute to the group interrupt
 *  0b0..Pin is disabled and does not contribute to the grouped interrupt
 *  0b1..Pin is enabled and contributes to the grouped interrupt
 */
#define GINT_PORT_ENA_ENA17(x)                   (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA17_SHIFT)) & GINT_PORT_ENA_ENA17_MASK)

#define GINT_PORT_ENA_ENA18_MASK                 (0x40000U)
#define GINT_PORT_ENA_ENA18_SHIFT                (18U)
/*! ENA18 - Enables port pin n to contribute to the group interrupt
 *  0b0..Pin is disabled and does not contribute to the grouped interrupt
 *  0b1..Pin is enabled and contributes to the grouped interrupt
 */
#define GINT_PORT_ENA_ENA18(x)                   (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA18_SHIFT)) & GINT_PORT_ENA_ENA18_MASK)

#define GINT_PORT_ENA_ENA19_MASK                 (0x80000U)
#define GINT_PORT_ENA_ENA19_SHIFT                (19U)
/*! ENA19 - Enables port pin n to contribute to the group interrupt
 *  0b0..Pin is disabled and does not contribute to the grouped interrupt
 *  0b1..Pin is enabled and contributes to the grouped interrupt
 */
#define GINT_PORT_ENA_ENA19(x)                   (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA19_SHIFT)) & GINT_PORT_ENA_ENA19_MASK)

#define GINT_PORT_ENA_ENA20_MASK                 (0x100000U)
#define GINT_PORT_ENA_ENA20_SHIFT                (20U)
/*! ENA20 - Enables port pin n to contribute to the group interrupt
 *  0b0..Pin is disabled and does not contribute to the grouped interrupt
 *  0b1..Pin is enabled and contributes to the grouped interrupt
 */
#define GINT_PORT_ENA_ENA20(x)                   (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA20_SHIFT)) & GINT_PORT_ENA_ENA20_MASK)

#define GINT_PORT_ENA_ENA21_MASK                 (0x200000U)
#define GINT_PORT_ENA_ENA21_SHIFT                (21U)
/*! ENA21 - Enables port pin n to contribute to the group interrupt
 *  0b0..Pin is disabled and does not contribute to the grouped interrupt
 *  0b1..Pin is enabled and contributes to the grouped interrupt
 */
#define GINT_PORT_ENA_ENA21(x)                   (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA21_SHIFT)) & GINT_PORT_ENA_ENA21_MASK)

#define GINT_PORT_ENA_ENA22_MASK                 (0x400000U)
#define GINT_PORT_ENA_ENA22_SHIFT                (22U)
/*! ENA22 - Enables port pin n to contribute to the group interrupt
 *  0b0..Pin is disabled and does not contribute to the grouped interrupt
 *  0b1..Pin is enabled and contributes to the grouped interrupt
 */
#define GINT_PORT_ENA_ENA22(x)                   (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA22_SHIFT)) & GINT_PORT_ENA_ENA22_MASK)

#define GINT_PORT_ENA_ENA23_MASK                 (0x800000U)
#define GINT_PORT_ENA_ENA23_SHIFT                (23U)
/*! ENA23 - Enables port pin n to contribute to the group interrupt
 *  0b0..Pin is disabled and does not contribute to the grouped interrupt
 *  0b1..Pin is enabled and contributes to the grouped interrupt
 */
#define GINT_PORT_ENA_ENA23(x)                   (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA23_SHIFT)) & GINT_PORT_ENA_ENA23_MASK)

#define GINT_PORT_ENA_ENA24_MASK                 (0x1000000U)
#define GINT_PORT_ENA_ENA24_SHIFT                (24U)
/*! ENA24 - Enables port pin n to contribute to the group interrupt
 *  0b0..Pin is disabled and does not contribute to the grouped interrupt
 *  0b1..Pin is enabled and contributes to the grouped interrupt
 */
#define GINT_PORT_ENA_ENA24(x)                   (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA24_SHIFT)) & GINT_PORT_ENA_ENA24_MASK)

#define GINT_PORT_ENA_ENA25_MASK                 (0x2000000U)
#define GINT_PORT_ENA_ENA25_SHIFT                (25U)
/*! ENA25 - Enables port pin n to contribute to the group interrupt
 *  0b0..Pin is disabled and does not contribute to the grouped interrupt
 *  0b1..Pin is enabled and contributes to the grouped interrupt
 */
#define GINT_PORT_ENA_ENA25(x)                   (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA25_SHIFT)) & GINT_PORT_ENA_ENA25_MASK)

#define GINT_PORT_ENA_ENA26_MASK                 (0x4000000U)
#define GINT_PORT_ENA_ENA26_SHIFT                (26U)
/*! ENA26 - Enables port pin n to contribute to the group interrupt
 *  0b0..Pin is disabled and does not contribute to the grouped interrupt
 *  0b1..Pin is enabled and contributes to the grouped interrupt
 */
#define GINT_PORT_ENA_ENA26(x)                   (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA26_SHIFT)) & GINT_PORT_ENA_ENA26_MASK)

#define GINT_PORT_ENA_ENA27_MASK                 (0x8000000U)
#define GINT_PORT_ENA_ENA27_SHIFT                (27U)
/*! ENA27 - Enables port pin n to contribute to the group interrupt
 *  0b0..Pin is disabled and does not contribute to the grouped interrupt
 *  0b1..Pin is enabled and contributes to the grouped interrupt
 */
#define GINT_PORT_ENA_ENA27(x)                   (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA27_SHIFT)) & GINT_PORT_ENA_ENA27_MASK)

#define GINT_PORT_ENA_ENA28_MASK                 (0x10000000U)
#define GINT_PORT_ENA_ENA28_SHIFT                (28U)
/*! ENA28 - Enables port pin n to contribute to the group interrupt
 *  0b0..Pin is disabled and does not contribute to the grouped interrupt
 *  0b1..Pin is enabled and contributes to the grouped interrupt
 */
#define GINT_PORT_ENA_ENA28(x)                   (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA28_SHIFT)) & GINT_PORT_ENA_ENA28_MASK)

#define GINT_PORT_ENA_ENA29_MASK                 (0x20000000U)
#define GINT_PORT_ENA_ENA29_SHIFT                (29U)
/*! ENA29 - Enables port pin n to contribute to the group interrupt
 *  0b0..Pin is disabled and does not contribute to the grouped interrupt
 *  0b1..Pin is enabled and contributes to the grouped interrupt
 */
#define GINT_PORT_ENA_ENA29(x)                   (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA29_SHIFT)) & GINT_PORT_ENA_ENA29_MASK)

#define GINT_PORT_ENA_ENA30_MASK                 (0x40000000U)
#define GINT_PORT_ENA_ENA30_SHIFT                (30U)
/*! ENA30 - Enables port pin n to contribute to the group interrupt
 *  0b0..Pin is disabled and does not contribute to the grouped interrupt
 *  0b1..Pin is enabled and contributes to the grouped interrupt
 */
#define GINT_PORT_ENA_ENA30(x)                   (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA30_SHIFT)) & GINT_PORT_ENA_ENA30_MASK)

#define GINT_PORT_ENA_ENA31_MASK                 (0x80000000U)
#define GINT_PORT_ENA_ENA31_SHIFT                (31U)
/*! ENA31 - Enables port pin n to contribute to the group interrupt
 *  0b0..Pin is disabled and does not contribute to the grouped interrupt
 *  0b1..Pin is enabled and contributes to the grouped interrupt
 */
#define GINT_PORT_ENA_ENA31(x)                   (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA31_SHIFT)) & GINT_PORT_ENA_ENA31_MASK)
/*! @} */

/* The count of GINT_PORT_ENA */
#define GINT_PORT_ENA_COUNT                      (2U)


/*!
 * @}
 */ /* end of group GINT_Register_Masks */


/* GINT - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral GINT0 base address */
  #define GINT0_BASE                               (0x50002000u)
  /** Peripheral GINT0 base address */
  #define GINT0_BASE_NS                            (0x40002000u)
  /** Peripheral GINT0 base pointer */
  #define GINT0                                    ((GINT_Type *)GINT0_BASE)
  /** Peripheral GINT0 base pointer */
  #define GINT0_NS                                 ((GINT_Type *)GINT0_BASE_NS)
  /** Peripheral GINT1 base address */
  #define GINT1_BASE                               (0x50003000u)
  /** Peripheral GINT1 base address */
  #define GINT1_BASE_NS                            (0x40003000u)
  /** Peripheral GINT1 base pointer */
  #define GINT1                                    ((GINT_Type *)GINT1_BASE)
  /** Peripheral GINT1 base pointer */
  #define GINT1_NS                                 ((GINT_Type *)GINT1_BASE_NS)
  /** Array initializer of GINT peripheral base addresses */
  #define GINT_BASE_ADDRS                          { GINT0_BASE, GINT1_BASE }
  /** Array initializer of GINT peripheral base pointers */
  #define GINT_BASE_PTRS                           { GINT0, GINT1 }
  /** Array initializer of GINT peripheral base addresses */
  #define GINT_BASE_ADDRS_NS                       { GINT0_BASE_NS, GINT1_BASE_NS }
  /** Array initializer of GINT peripheral base pointers */
  #define GINT_BASE_PTRS_NS                        { GINT0_NS, GINT1_NS }
#else
  /** Peripheral GINT0 base address */
  #define GINT0_BASE                               (0x40002000u)
  /** Peripheral GINT0 base pointer */
  #define GINT0                                    ((GINT_Type *)GINT0_BASE)
  /** Peripheral GINT1 base address */
  #define GINT1_BASE                               (0x40003000u)
  /** Peripheral GINT1 base pointer */
  #define GINT1                                    ((GINT_Type *)GINT1_BASE)
  /** Array initializer of GINT peripheral base addresses */
  #define GINT_BASE_ADDRS                          { GINT0_BASE, GINT1_BASE }
  /** Array initializer of GINT peripheral base pointers */
  #define GINT_BASE_PTRS                           { GINT0, GINT1 }
#endif
/** Interrupt vectors for the GINT peripheral type */
#define GINT_IRQS                                { GINT0_IRQn, GINT1_IRQn }

/*!
 * @}
 */ /* end of group GINT_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- GPIO Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
 * @{
 */

/** GPIO - Register Layout Typedef */
typedef struct {
  __IO uint8_t B[4][32];                           /**< Byte pin registers for all port GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */
       uint8_t RESERVED_0[3968];
  __IO uint32_t W[4][32];                          /**< Word pin registers for all port GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */
       uint8_t RESERVED_1[3584];
  __O  uint32_t DIR[4];                            /**< Port direction, array offset: 0x2000, array step: 0x4 */
       uint8_t RESERVED_2[112];
  __IO uint32_t MASK[4];                           /**< Port mask, array offset: 0x2080, array step: 0x4 */
       uint8_t RESERVED_3[112];
  __IO uint32_t PIN[4];                            /**< Port pin, array offset: 0x2100, array step: 0x4 */
       uint8_t RESERVED_4[112];
  __IO uint32_t MPIN[4];                           /**< Masked Port Pin, array offset: 0x2180, array step: 0x4 */
       uint8_t RESERVED_5[112];
  __IO uint32_t SET[4];                            /**< Port set, array offset: 0x2200, array step: 0x4 */
       uint8_t RESERVED_6[112];
  __IO uint32_t CLR[4];                            /**< Port clear, array offset: 0x2280, array step: 0x4 */
       uint8_t RESERVED_7[112];
  __O  uint32_t NOT[4];                            /**< Port toggle, array offset: 0x2300, array step: 0x4 */
       uint8_t RESERVED_8[112];
  __O  uint32_t DIRSET[4];                         /**< Port direction set, array offset: 0x2380, array step: 0x4 */
       uint8_t RESERVED_9[112];
  __IO uint32_t DIRCLR[4];                         /**< Port direction clear, array offset: 0x2400, array step: 0x4 */
       uint8_t RESERVED_10[112];
  __O  uint32_t DIRNOT[4];                         /**< Port direction toggle, array offset: 0x2480, array step: 0x4 */
       uint8_t RESERVED_11[112];
  __IO uint32_t INTENA[4];                         /**< Interrupt A enable control, array offset: 0x2500, array step: 0x4 */
       uint8_t RESERVED_12[112];
  __IO uint32_t INTENB[4];                         /**< Interrupt B enable control, array offset: 0x2580, array step: 0x4 */
       uint8_t RESERVED_13[112];
  __IO uint32_t INTPOL[4];                         /**< Interupt polarity control, array offset: 0x2600, array step: 0x4 */
       uint8_t RESERVED_14[112];
  __IO uint32_t INTEDG[4];                         /**< Interrupt edge select, array offset: 0x2680, array step: 0x4 */
       uint8_t RESERVED_15[112];
  __IO uint32_t INTSTATA[4];                       /**< Interrupt status for interrupt A, array offset: 0x2700, array step: 0x4 */
       uint8_t RESERVED_16[112];
  __IO uint32_t INTSTATB[4];                       /**< Interrupt status for interrupt B, array offset: 0x2780, array step: 0x4 */
} GPIO_Type;

/* ----------------------------------------------------------------------------
   -- GPIO Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup GPIO_Register_Masks GPIO Register Masks
 * @{
 */

/*! @name BYTE_PIN_BYTE_PIN_B - Byte pin registers for all port GPIO pins */
/*! @{ */

#define GPIO_BYTE_PIN_BYTE_PIN_B_PBYTE_MASK      (0x1U)
#define GPIO_BYTE_PIN_BYTE_PIN_B_PBYTE_SHIFT     (0U)
/*! PBYTE - Port Byte
 */
#define GPIO_BYTE_PIN_BYTE_PIN_B_PBYTE(x)        (((uint8_t)(((uint8_t)(x)) << GPIO_BYTE_PIN_BYTE_PIN_B_PBYTE_SHIFT)) & GPIO_BYTE_PIN_BYTE_PIN_B_PBYTE_MASK)
/*! @} */

/* The count of GPIO_BYTE_PIN_BYTE_PIN_B */
#define GPIO_BYTE_PIN_BYTE_PIN_B_COUNT           (4U)

/* The count of GPIO_BYTE_PIN_BYTE_PIN_B */
#define GPIO_BYTE_PIN_BYTE_PIN_B_COUNT2          (32U)

/*! @name WORD_PIN_WORD_PIN_W - Word pin registers for all port GPIO pins */
/*! @{ */

#define GPIO_WORD_PIN_WORD_PIN_W_PWORD_MASK      (0xFFFFFFFFU)
#define GPIO_WORD_PIN_WORD_PIN_W_PWORD_SHIFT     (0U)
/*! PWORD - PWORD
 */
#define GPIO_WORD_PIN_WORD_PIN_W_PWORD(x)        (((uint32_t)(((uint32_t)(x)) << GPIO_WORD_PIN_WORD_PIN_W_PWORD_SHIFT)) & GPIO_WORD_PIN_WORD_PIN_W_PWORD_MASK)
/*! @} */

/* The count of GPIO_WORD_PIN_WORD_PIN_W */
#define GPIO_WORD_PIN_WORD_PIN_W_COUNT           (4U)

/* The count of GPIO_WORD_PIN_WORD_PIN_W */
#define GPIO_WORD_PIN_WORD_PIN_W_COUNT2          (32U)

/*! @name DIR - Port direction */
/*! @{ */

#define GPIO_DIR_DIRP0_MASK                      (0x1U)
#define GPIO_DIR_DIRP0_SHIFT                     (0U)
/*! DIRP0 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP0(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP0_SHIFT)) & GPIO_DIR_DIRP0_MASK)

#define GPIO_DIR_DIRP1_MASK                      (0x2U)
#define GPIO_DIR_DIRP1_SHIFT                     (1U)
/*! DIRP1 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP1(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP1_SHIFT)) & GPIO_DIR_DIRP1_MASK)

#define GPIO_DIR_DIRP2_MASK                      (0x4U)
#define GPIO_DIR_DIRP2_SHIFT                     (2U)
/*! DIRP2 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP2(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP2_SHIFT)) & GPIO_DIR_DIRP2_MASK)

#define GPIO_DIR_DIRP3_MASK                      (0x8U)
#define GPIO_DIR_DIRP3_SHIFT                     (3U)
/*! DIRP3 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP3(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP3_SHIFT)) & GPIO_DIR_DIRP3_MASK)

#define GPIO_DIR_DIRP4_MASK                      (0x10U)
#define GPIO_DIR_DIRP4_SHIFT                     (4U)
/*! DIRP4 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP4(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP4_SHIFT)) & GPIO_DIR_DIRP4_MASK)

#define GPIO_DIR_DIRP5_MASK                      (0x20U)
#define GPIO_DIR_DIRP5_SHIFT                     (5U)
/*! DIRP5 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP5(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP5_SHIFT)) & GPIO_DIR_DIRP5_MASK)

#define GPIO_DIR_DIRP6_MASK                      (0x40U)
#define GPIO_DIR_DIRP6_SHIFT                     (6U)
/*! DIRP6 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP6(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP6_SHIFT)) & GPIO_DIR_DIRP6_MASK)

#define GPIO_DIR_DIRP7_MASK                      (0x80U)
#define GPIO_DIR_DIRP7_SHIFT                     (7U)
/*! DIRP7 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP7(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP7_SHIFT)) & GPIO_DIR_DIRP7_MASK)

#define GPIO_DIR_DIRP8_MASK                      (0x100U)
#define GPIO_DIR_DIRP8_SHIFT                     (8U)
/*! DIRP8 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP8(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP8_SHIFT)) & GPIO_DIR_DIRP8_MASK)

#define GPIO_DIR_DIRP9_MASK                      (0x200U)
#define GPIO_DIR_DIRP9_SHIFT                     (9U)
/*! DIRP9 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP9(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP9_SHIFT)) & GPIO_DIR_DIRP9_MASK)

#define GPIO_DIR_DIRP10_MASK                     (0x400U)
#define GPIO_DIR_DIRP10_SHIFT                    (10U)
/*! DIRP10 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP10(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP10_SHIFT)) & GPIO_DIR_DIRP10_MASK)

#define GPIO_DIR_DIRP11_MASK                     (0x800U)
#define GPIO_DIR_DIRP11_SHIFT                    (11U)
/*! DIRP11 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP11(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP11_SHIFT)) & GPIO_DIR_DIRP11_MASK)

#define GPIO_DIR_DIRP12_MASK                     (0x1000U)
#define GPIO_DIR_DIRP12_SHIFT                    (12U)
/*! DIRP12 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP12(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP12_SHIFT)) & GPIO_DIR_DIRP12_MASK)

#define GPIO_DIR_DIRP13_MASK                     (0x2000U)
#define GPIO_DIR_DIRP13_SHIFT                    (13U)
/*! DIRP13 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP13(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP13_SHIFT)) & GPIO_DIR_DIRP13_MASK)

#define GPIO_DIR_DIRP14_MASK                     (0x4000U)
#define GPIO_DIR_DIRP14_SHIFT                    (14U)
/*! DIRP14 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP14(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP14_SHIFT)) & GPIO_DIR_DIRP14_MASK)

#define GPIO_DIR_DIRP15_MASK                     (0x8000U)
#define GPIO_DIR_DIRP15_SHIFT                    (15U)
/*! DIRP15 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP15(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP15_SHIFT)) & GPIO_DIR_DIRP15_MASK)

#define GPIO_DIR_DIRP16_MASK                     (0x10000U)
#define GPIO_DIR_DIRP16_SHIFT                    (16U)
/*! DIRP16 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP16(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP16_SHIFT)) & GPIO_DIR_DIRP16_MASK)

#define GPIO_DIR_DIRP17_MASK                     (0x20000U)
#define GPIO_DIR_DIRP17_SHIFT                    (17U)
/*! DIRP17 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP17(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP17_SHIFT)) & GPIO_DIR_DIRP17_MASK)

#define GPIO_DIR_DIRP18_MASK                     (0x40000U)
#define GPIO_DIR_DIRP18_SHIFT                    (18U)
/*! DIRP18 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP18(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP18_SHIFT)) & GPIO_DIR_DIRP18_MASK)

#define GPIO_DIR_DIRP19_MASK                     (0x80000U)
#define GPIO_DIR_DIRP19_SHIFT                    (19U)
/*! DIRP19 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP19(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP19_SHIFT)) & GPIO_DIR_DIRP19_MASK)

#define GPIO_DIR_DIRP20_MASK                     (0x100000U)
#define GPIO_DIR_DIRP20_SHIFT                    (20U)
/*! DIRP20 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP20(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP20_SHIFT)) & GPIO_DIR_DIRP20_MASK)

#define GPIO_DIR_DIRP21_MASK                     (0x200000U)
#define GPIO_DIR_DIRP21_SHIFT                    (21U)
/*! DIRP21 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP21(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP21_SHIFT)) & GPIO_DIR_DIRP21_MASK)

#define GPIO_DIR_DIRP22_MASK                     (0x400000U)
#define GPIO_DIR_DIRP22_SHIFT                    (22U)
/*! DIRP22 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP22(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP22_SHIFT)) & GPIO_DIR_DIRP22_MASK)

#define GPIO_DIR_DIRP23_MASK                     (0x800000U)
#define GPIO_DIR_DIRP23_SHIFT                    (23U)
/*! DIRP23 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP23(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP23_SHIFT)) & GPIO_DIR_DIRP23_MASK)

#define GPIO_DIR_DIRP24_MASK                     (0x1000000U)
#define GPIO_DIR_DIRP24_SHIFT                    (24U)
/*! DIRP24 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP24(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP24_SHIFT)) & GPIO_DIR_DIRP24_MASK)

#define GPIO_DIR_DIRP25_MASK                     (0x2000000U)
#define GPIO_DIR_DIRP25_SHIFT                    (25U)
/*! DIRP25 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP25(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP25_SHIFT)) & GPIO_DIR_DIRP25_MASK)

#define GPIO_DIR_DIRP26_MASK                     (0x4000000U)
#define GPIO_DIR_DIRP26_SHIFT                    (26U)
/*! DIRP26 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP26(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP26_SHIFT)) & GPIO_DIR_DIRP26_MASK)

#define GPIO_DIR_DIRP27_MASK                     (0x8000000U)
#define GPIO_DIR_DIRP27_SHIFT                    (27U)
/*! DIRP27 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP27(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP27_SHIFT)) & GPIO_DIR_DIRP27_MASK)

#define GPIO_DIR_DIRP28_MASK                     (0x10000000U)
#define GPIO_DIR_DIRP28_SHIFT                    (28U)
/*! DIRP28 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP28(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP28_SHIFT)) & GPIO_DIR_DIRP28_MASK)

#define GPIO_DIR_DIRP29_MASK                     (0x20000000U)
#define GPIO_DIR_DIRP29_SHIFT                    (29U)
/*! DIRP29 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP29(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP29_SHIFT)) & GPIO_DIR_DIRP29_MASK)

#define GPIO_DIR_DIRP30_MASK                     (0x40000000U)
#define GPIO_DIR_DIRP30_SHIFT                    (30U)
/*! DIRP30 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP30(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP30_SHIFT)) & GPIO_DIR_DIRP30_MASK)

#define GPIO_DIR_DIRP31_MASK                     (0x80000000U)
#define GPIO_DIR_DIRP31_SHIFT                    (31U)
/*! DIRP31 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP31(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP31_SHIFT)) & GPIO_DIR_DIRP31_MASK)
/*! @} */

/* The count of GPIO_DIR */
#define GPIO_DIR_COUNT                           (4U)

/*! @name MASK - Port mask */
/*! @{ */

#define GPIO_MASK_MASKP0_MASK                    (0x1U)
#define GPIO_MASK_MASKP0_SHIFT                   (0U)
/*! MASKP0 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP0(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP0_SHIFT)) & GPIO_MASK_MASKP0_MASK)

#define GPIO_MASK_MASKP1_MASK                    (0x2U)
#define GPIO_MASK_MASKP1_SHIFT                   (1U)
/*! MASKP1 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP1(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP1_SHIFT)) & GPIO_MASK_MASKP1_MASK)

#define GPIO_MASK_MASKP2_MASK                    (0x4U)
#define GPIO_MASK_MASKP2_SHIFT                   (2U)
/*! MASKP2 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP2(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP2_SHIFT)) & GPIO_MASK_MASKP2_MASK)

#define GPIO_MASK_MASKP3_MASK                    (0x8U)
#define GPIO_MASK_MASKP3_SHIFT                   (3U)
/*! MASKP3 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP3(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP3_SHIFT)) & GPIO_MASK_MASKP3_MASK)

#define GPIO_MASK_MASKP4_MASK                    (0x10U)
#define GPIO_MASK_MASKP4_SHIFT                   (4U)
/*! MASKP4 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP4(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP4_SHIFT)) & GPIO_MASK_MASKP4_MASK)

#define GPIO_MASK_MASKP5_MASK                    (0x20U)
#define GPIO_MASK_MASKP5_SHIFT                   (5U)
/*! MASKP5 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP5(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP5_SHIFT)) & GPIO_MASK_MASKP5_MASK)

#define GPIO_MASK_MASKP6_MASK                    (0x40U)
#define GPIO_MASK_MASKP6_SHIFT                   (6U)
/*! MASKP6 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP6(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP6_SHIFT)) & GPIO_MASK_MASKP6_MASK)

#define GPIO_MASK_MASKP7_MASK                    (0x80U)
#define GPIO_MASK_MASKP7_SHIFT                   (7U)
/*! MASKP7 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP7(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP7_SHIFT)) & GPIO_MASK_MASKP7_MASK)

#define GPIO_MASK_MASKP8_MASK                    (0x100U)
#define GPIO_MASK_MASKP8_SHIFT                   (8U)
/*! MASKP8 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP8(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP8_SHIFT)) & GPIO_MASK_MASKP8_MASK)

#define GPIO_MASK_MASKP9_MASK                    (0x200U)
#define GPIO_MASK_MASKP9_SHIFT                   (9U)
/*! MASKP9 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP9(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP9_SHIFT)) & GPIO_MASK_MASKP9_MASK)

#define GPIO_MASK_MASKP10_MASK                   (0x400U)
#define GPIO_MASK_MASKP10_SHIFT                  (10U)
/*! MASKP10 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP10(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP10_SHIFT)) & GPIO_MASK_MASKP10_MASK)

#define GPIO_MASK_MASKP11_MASK                   (0x800U)
#define GPIO_MASK_MASKP11_SHIFT                  (11U)
/*! MASKP11 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP11(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP11_SHIFT)) & GPIO_MASK_MASKP11_MASK)

#define GPIO_MASK_MASKP12_MASK                   (0x1000U)
#define GPIO_MASK_MASKP12_SHIFT                  (12U)
/*! MASKP12 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP12(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP12_SHIFT)) & GPIO_MASK_MASKP12_MASK)

#define GPIO_MASK_MASKP13_MASK                   (0x2000U)
#define GPIO_MASK_MASKP13_SHIFT                  (13U)
/*! MASKP13 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP13(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP13_SHIFT)) & GPIO_MASK_MASKP13_MASK)

#define GPIO_MASK_MASKP14_MASK                   (0x4000U)
#define GPIO_MASK_MASKP14_SHIFT                  (14U)
/*! MASKP14 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP14(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP14_SHIFT)) & GPIO_MASK_MASKP14_MASK)

#define GPIO_MASK_MASKP15_MASK                   (0x8000U)
#define GPIO_MASK_MASKP15_SHIFT                  (15U)
/*! MASKP15 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP15(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP15_SHIFT)) & GPIO_MASK_MASKP15_MASK)

#define GPIO_MASK_MASKP16_MASK                   (0x10000U)
#define GPIO_MASK_MASKP16_SHIFT                  (16U)
/*! MASKP16 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP16(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP16_SHIFT)) & GPIO_MASK_MASKP16_MASK)

#define GPIO_MASK_MASKP17_MASK                   (0x20000U)
#define GPIO_MASK_MASKP17_SHIFT                  (17U)
/*! MASKP17 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP17(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP17_SHIFT)) & GPIO_MASK_MASKP17_MASK)

#define GPIO_MASK_MASKP18_MASK                   (0x40000U)
#define GPIO_MASK_MASKP18_SHIFT                  (18U)
/*! MASKP18 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP18(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP18_SHIFT)) & GPIO_MASK_MASKP18_MASK)

#define GPIO_MASK_MASKP19_MASK                   (0x80000U)
#define GPIO_MASK_MASKP19_SHIFT                  (19U)
/*! MASKP19 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP19(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP19_SHIFT)) & GPIO_MASK_MASKP19_MASK)

#define GPIO_MASK_MASKP20_MASK                   (0x100000U)
#define GPIO_MASK_MASKP20_SHIFT                  (20U)
/*! MASKP20 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP20(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP20_SHIFT)) & GPIO_MASK_MASKP20_MASK)

#define GPIO_MASK_MASKP21_MASK                   (0x200000U)
#define GPIO_MASK_MASKP21_SHIFT                  (21U)
/*! MASKP21 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP21(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP21_SHIFT)) & GPIO_MASK_MASKP21_MASK)

#define GPIO_MASK_MASKP22_MASK                   (0x400000U)
#define GPIO_MASK_MASKP22_SHIFT                  (22U)
/*! MASKP22 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP22(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP22_SHIFT)) & GPIO_MASK_MASKP22_MASK)

#define GPIO_MASK_MASKP23_MASK                   (0x800000U)
#define GPIO_MASK_MASKP23_SHIFT                  (23U)
/*! MASKP23 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP23(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP23_SHIFT)) & GPIO_MASK_MASKP23_MASK)

#define GPIO_MASK_MASKP24_MASK                   (0x1000000U)
#define GPIO_MASK_MASKP24_SHIFT                  (24U)
/*! MASKP24 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP24(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP24_SHIFT)) & GPIO_MASK_MASKP24_MASK)

#define GPIO_MASK_MASKP25_MASK                   (0x2000000U)
#define GPIO_MASK_MASKP25_SHIFT                  (25U)
/*! MASKP25 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP25(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP25_SHIFT)) & GPIO_MASK_MASKP25_MASK)

#define GPIO_MASK_MASKP26_MASK                   (0x4000000U)
#define GPIO_MASK_MASKP26_SHIFT                  (26U)
/*! MASKP26 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP26(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP26_SHIFT)) & GPIO_MASK_MASKP26_MASK)

#define GPIO_MASK_MASKP27_MASK                   (0x8000000U)
#define GPIO_MASK_MASKP27_SHIFT                  (27U)
/*! MASKP27 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP27(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP27_SHIFT)) & GPIO_MASK_MASKP27_MASK)

#define GPIO_MASK_MASKP28_MASK                   (0x10000000U)
#define GPIO_MASK_MASKP28_SHIFT                  (28U)
/*! MASKP28 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP28(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP28_SHIFT)) & GPIO_MASK_MASKP28_MASK)

#define GPIO_MASK_MASKP29_MASK                   (0x20000000U)
#define GPIO_MASK_MASKP29_SHIFT                  (29U)
/*! MASKP29 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP29(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP29_SHIFT)) & GPIO_MASK_MASKP29_MASK)

#define GPIO_MASK_MASKP30_MASK                   (0x40000000U)
#define GPIO_MASK_MASKP30_SHIFT                  (30U)
/*! MASKP30 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP30(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP30_SHIFT)) & GPIO_MASK_MASKP30_MASK)

#define GPIO_MASK_MASKP31_MASK                   (0x80000000U)
#define GPIO_MASK_MASKP31_SHIFT                  (31U)
/*! MASKP31 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP31(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP31_SHIFT)) & GPIO_MASK_MASKP31_MASK)
/*! @} */

/* The count of GPIO_MASK */
#define GPIO_MASK_COUNT                          (4U)

/*! @name PIN - Port pin */
/*! @{ */

#define GPIO_PIN_PORT0_MASK                      (0x1U)
#define GPIO_PIN_PORT0_SHIFT                     (0U)
/*! PORT0 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT0(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT0_SHIFT)) & GPIO_PIN_PORT0_MASK)

#define GPIO_PIN_PORT1_MASK                      (0x2U)
#define GPIO_PIN_PORT1_SHIFT                     (1U)
/*! PORT1 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT1(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT1_SHIFT)) & GPIO_PIN_PORT1_MASK)

#define GPIO_PIN_PORT2_MASK                      (0x4U)
#define GPIO_PIN_PORT2_SHIFT                     (2U)
/*! PORT2 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT2(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT2_SHIFT)) & GPIO_PIN_PORT2_MASK)

#define GPIO_PIN_PORT3_MASK                      (0x8U)
#define GPIO_PIN_PORT3_SHIFT                     (3U)
/*! PORT3 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT3(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT3_SHIFT)) & GPIO_PIN_PORT3_MASK)

#define GPIO_PIN_PORT4_MASK                      (0x10U)
#define GPIO_PIN_PORT4_SHIFT                     (4U)
/*! PORT4 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT4(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT4_SHIFT)) & GPIO_PIN_PORT4_MASK)

#define GPIO_PIN_PORT5_MASK                      (0x20U)
#define GPIO_PIN_PORT5_SHIFT                     (5U)
/*! PORT5 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT5(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT5_SHIFT)) & GPIO_PIN_PORT5_MASK)

#define GPIO_PIN_PORT6_MASK                      (0x40U)
#define GPIO_PIN_PORT6_SHIFT                     (6U)
/*! PORT6 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT6(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT6_SHIFT)) & GPIO_PIN_PORT6_MASK)

#define GPIO_PIN_PORT7_MASK                      (0x80U)
#define GPIO_PIN_PORT7_SHIFT                     (7U)
/*! PORT7 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT7(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT7_SHIFT)) & GPIO_PIN_PORT7_MASK)

#define GPIO_PIN_PORT8_MASK                      (0x100U)
#define GPIO_PIN_PORT8_SHIFT                     (8U)
/*! PORT8 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT8(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT8_SHIFT)) & GPIO_PIN_PORT8_MASK)

#define GPIO_PIN_PORT9_MASK                      (0x200U)
#define GPIO_PIN_PORT9_SHIFT                     (9U)
/*! PORT9 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT9(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT9_SHIFT)) & GPIO_PIN_PORT9_MASK)

#define GPIO_PIN_PORT10_MASK                     (0x400U)
#define GPIO_PIN_PORT10_SHIFT                    (10U)
/*! PORT10 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT10(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT10_SHIFT)) & GPIO_PIN_PORT10_MASK)

#define GPIO_PIN_PORT11_MASK                     (0x800U)
#define GPIO_PIN_PORT11_SHIFT                    (11U)
/*! PORT11 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT11(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT11_SHIFT)) & GPIO_PIN_PORT11_MASK)

#define GPIO_PIN_PORT12_MASK                     (0x1000U)
#define GPIO_PIN_PORT12_SHIFT                    (12U)
/*! PORT12 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT12(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT12_SHIFT)) & GPIO_PIN_PORT12_MASK)

#define GPIO_PIN_PORT13_MASK                     (0x2000U)
#define GPIO_PIN_PORT13_SHIFT                    (13U)
/*! PORT13 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT13(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT13_SHIFT)) & GPIO_PIN_PORT13_MASK)

#define GPIO_PIN_PORT14_MASK                     (0x4000U)
#define GPIO_PIN_PORT14_SHIFT                    (14U)
/*! PORT14 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT14(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT14_SHIFT)) & GPIO_PIN_PORT14_MASK)

#define GPIO_PIN_PORT15_MASK                     (0x8000U)
#define GPIO_PIN_PORT15_SHIFT                    (15U)
/*! PORT15 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT15(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT15_SHIFT)) & GPIO_PIN_PORT15_MASK)

#define GPIO_PIN_PORT16_MASK                     (0x10000U)
#define GPIO_PIN_PORT16_SHIFT                    (16U)
/*! PORT16 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT16(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT16_SHIFT)) & GPIO_PIN_PORT16_MASK)

#define GPIO_PIN_PORT17_MASK                     (0x20000U)
#define GPIO_PIN_PORT17_SHIFT                    (17U)
/*! PORT17 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT17(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT17_SHIFT)) & GPIO_PIN_PORT17_MASK)

#define GPIO_PIN_PORT18_MASK                     (0x40000U)
#define GPIO_PIN_PORT18_SHIFT                    (18U)
/*! PORT18 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT18(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT18_SHIFT)) & GPIO_PIN_PORT18_MASK)

#define GPIO_PIN_PORT19_MASK                     (0x80000U)
#define GPIO_PIN_PORT19_SHIFT                    (19U)
/*! PORT19 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT19(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT19_SHIFT)) & GPIO_PIN_PORT19_MASK)

#define GPIO_PIN_PORT20_MASK                     (0x100000U)
#define GPIO_PIN_PORT20_SHIFT                    (20U)
/*! PORT20 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT20(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT20_SHIFT)) & GPIO_PIN_PORT20_MASK)

#define GPIO_PIN_PORT21_MASK                     (0x200000U)
#define GPIO_PIN_PORT21_SHIFT                    (21U)
/*! PORT21 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT21(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT21_SHIFT)) & GPIO_PIN_PORT21_MASK)

#define GPIO_PIN_PORT22_MASK                     (0x400000U)
#define GPIO_PIN_PORT22_SHIFT                    (22U)
/*! PORT22 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT22(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT22_SHIFT)) & GPIO_PIN_PORT22_MASK)

#define GPIO_PIN_PORT23_MASK                     (0x800000U)
#define GPIO_PIN_PORT23_SHIFT                    (23U)
/*! PORT23 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT23(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT23_SHIFT)) & GPIO_PIN_PORT23_MASK)

#define GPIO_PIN_PORT24_MASK                     (0x1000000U)
#define GPIO_PIN_PORT24_SHIFT                    (24U)
/*! PORT24 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT24(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT24_SHIFT)) & GPIO_PIN_PORT24_MASK)

#define GPIO_PIN_PORT25_MASK                     (0x2000000U)
#define GPIO_PIN_PORT25_SHIFT                    (25U)
/*! PORT25 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT25(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT25_SHIFT)) & GPIO_PIN_PORT25_MASK)

#define GPIO_PIN_PORT26_MASK                     (0x4000000U)
#define GPIO_PIN_PORT26_SHIFT                    (26U)
/*! PORT26 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT26(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT26_SHIFT)) & GPIO_PIN_PORT26_MASK)

#define GPIO_PIN_PORT27_MASK                     (0x8000000U)
#define GPIO_PIN_PORT27_SHIFT                    (27U)
/*! PORT27 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT27(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT27_SHIFT)) & GPIO_PIN_PORT27_MASK)

#define GPIO_PIN_PORT28_MASK                     (0x10000000U)
#define GPIO_PIN_PORT28_SHIFT                    (28U)
/*! PORT28 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT28(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT28_SHIFT)) & GPIO_PIN_PORT28_MASK)

#define GPIO_PIN_PORT29_MASK                     (0x20000000U)
#define GPIO_PIN_PORT29_SHIFT                    (29U)
/*! PORT29 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT29(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT29_SHIFT)) & GPIO_PIN_PORT29_MASK)

#define GPIO_PIN_PORT30_MASK                     (0x40000000U)
#define GPIO_PIN_PORT30_SHIFT                    (30U)
/*! PORT30 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT30(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT30_SHIFT)) & GPIO_PIN_PORT30_MASK)

#define GPIO_PIN_PORT31_MASK                     (0x80000000U)
#define GPIO_PIN_PORT31_SHIFT                    (31U)
/*! PORT31 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT31(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT31_SHIFT)) & GPIO_PIN_PORT31_MASK)
/*! @} */

/* The count of GPIO_PIN */
#define GPIO_PIN_COUNT                           (4U)

/*! @name MPIN - Masked Port Pin */
/*! @{ */

#define GPIO_MPIN_MPORTP0_MASK                   (0x1U)
#define GPIO_MPIN_MPORTP0_SHIFT                  (0U)
/*! MPORTP0 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP0(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP0_SHIFT)) & GPIO_MPIN_MPORTP0_MASK)

#define GPIO_MPIN_MPORTP1_MASK                   (0x2U)
#define GPIO_MPIN_MPORTP1_SHIFT                  (1U)
/*! MPORTP1 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP1(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP1_SHIFT)) & GPIO_MPIN_MPORTP1_MASK)

#define GPIO_MPIN_MPORTP2_MASK                   (0x4U)
#define GPIO_MPIN_MPORTP2_SHIFT                  (2U)
/*! MPORTP2 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP2(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP2_SHIFT)) & GPIO_MPIN_MPORTP2_MASK)

#define GPIO_MPIN_MPORTP3_MASK                   (0x8U)
#define GPIO_MPIN_MPORTP3_SHIFT                  (3U)
/*! MPORTP3 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP3(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP3_SHIFT)) & GPIO_MPIN_MPORTP3_MASK)

#define GPIO_MPIN_MPORTP4_MASK                   (0x10U)
#define GPIO_MPIN_MPORTP4_SHIFT                  (4U)
/*! MPORTP4 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP4(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP4_SHIFT)) & GPIO_MPIN_MPORTP4_MASK)

#define GPIO_MPIN_MPORTP5_MASK                   (0x20U)
#define GPIO_MPIN_MPORTP5_SHIFT                  (5U)
/*! MPORTP5 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP5(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP5_SHIFT)) & GPIO_MPIN_MPORTP5_MASK)

#define GPIO_MPIN_MPORTP6_MASK                   (0x40U)
#define GPIO_MPIN_MPORTP6_SHIFT                  (6U)
/*! MPORTP6 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP6(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP6_SHIFT)) & GPIO_MPIN_MPORTP6_MASK)

#define GPIO_MPIN_MPORTP7_MASK                   (0x80U)
#define GPIO_MPIN_MPORTP7_SHIFT                  (7U)
/*! MPORTP7 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP7(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP7_SHIFT)) & GPIO_MPIN_MPORTP7_MASK)

#define GPIO_MPIN_MPORTP8_MASK                   (0x100U)
#define GPIO_MPIN_MPORTP8_SHIFT                  (8U)
/*! MPORTP8 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP8(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP8_SHIFT)) & GPIO_MPIN_MPORTP8_MASK)

#define GPIO_MPIN_MPORTP9_MASK                   (0x200U)
#define GPIO_MPIN_MPORTP9_SHIFT                  (9U)
/*! MPORTP9 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP9(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP9_SHIFT)) & GPIO_MPIN_MPORTP9_MASK)

#define GPIO_MPIN_MPORTP10_MASK                  (0x400U)
#define GPIO_MPIN_MPORTP10_SHIFT                 (10U)
/*! MPORTP10 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP10(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP10_SHIFT)) & GPIO_MPIN_MPORTP10_MASK)

#define GPIO_MPIN_MPORTP11_MASK                  (0x800U)
#define GPIO_MPIN_MPORTP11_SHIFT                 (11U)
/*! MPORTP11 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP11(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP11_SHIFT)) & GPIO_MPIN_MPORTP11_MASK)

#define GPIO_MPIN_MPORTP12_MASK                  (0x1000U)
#define GPIO_MPIN_MPORTP12_SHIFT                 (12U)
/*! MPORTP12 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP12(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP12_SHIFT)) & GPIO_MPIN_MPORTP12_MASK)

#define GPIO_MPIN_MPORTP13_MASK                  (0x2000U)
#define GPIO_MPIN_MPORTP13_SHIFT                 (13U)
/*! MPORTP13 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP13(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP13_SHIFT)) & GPIO_MPIN_MPORTP13_MASK)

#define GPIO_MPIN_MPORTP14_MASK                  (0x4000U)
#define GPIO_MPIN_MPORTP14_SHIFT                 (14U)
/*! MPORTP14 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP14(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP14_SHIFT)) & GPIO_MPIN_MPORTP14_MASK)

#define GPIO_MPIN_MPORTP15_MASK                  (0x8000U)
#define GPIO_MPIN_MPORTP15_SHIFT                 (15U)
/*! MPORTP15 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP15(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP15_SHIFT)) & GPIO_MPIN_MPORTP15_MASK)

#define GPIO_MPIN_MPORTP16_MASK                  (0x10000U)
#define GPIO_MPIN_MPORTP16_SHIFT                 (16U)
/*! MPORTP16 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP16(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP16_SHIFT)) & GPIO_MPIN_MPORTP16_MASK)

#define GPIO_MPIN_MPORTP17_MASK                  (0x20000U)
#define GPIO_MPIN_MPORTP17_SHIFT                 (17U)
/*! MPORTP17 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP17(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP17_SHIFT)) & GPIO_MPIN_MPORTP17_MASK)

#define GPIO_MPIN_MPORTP18_MASK                  (0x40000U)
#define GPIO_MPIN_MPORTP18_SHIFT                 (18U)
/*! MPORTP18 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP18(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP18_SHIFT)) & GPIO_MPIN_MPORTP18_MASK)

#define GPIO_MPIN_MPORTP19_MASK                  (0x80000U)
#define GPIO_MPIN_MPORTP19_SHIFT                 (19U)
/*! MPORTP19 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP19(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP19_SHIFT)) & GPIO_MPIN_MPORTP19_MASK)

#define GPIO_MPIN_MPORTP20_MASK                  (0x100000U)
#define GPIO_MPIN_MPORTP20_SHIFT                 (20U)
/*! MPORTP20 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP20(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP20_SHIFT)) & GPIO_MPIN_MPORTP20_MASK)

#define GPIO_MPIN_MPORTP21_MASK                  (0x200000U)
#define GPIO_MPIN_MPORTP21_SHIFT                 (21U)
/*! MPORTP21 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP21(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP21_SHIFT)) & GPIO_MPIN_MPORTP21_MASK)

#define GPIO_MPIN_MPORTP22_MASK                  (0x400000U)
#define GPIO_MPIN_MPORTP22_SHIFT                 (22U)
/*! MPORTP22 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP22(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP22_SHIFT)) & GPIO_MPIN_MPORTP22_MASK)

#define GPIO_MPIN_MPORTP23_MASK                  (0x800000U)
#define GPIO_MPIN_MPORTP23_SHIFT                 (23U)
/*! MPORTP23 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP23(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP23_SHIFT)) & GPIO_MPIN_MPORTP23_MASK)

#define GPIO_MPIN_MPORTP24_MASK                  (0x1000000U)
#define GPIO_MPIN_MPORTP24_SHIFT                 (24U)
/*! MPORTP24 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP24(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP24_SHIFT)) & GPIO_MPIN_MPORTP24_MASK)

#define GPIO_MPIN_MPORTP25_MASK                  (0x2000000U)
#define GPIO_MPIN_MPORTP25_SHIFT                 (25U)
/*! MPORTP25 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP25(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP25_SHIFT)) & GPIO_MPIN_MPORTP25_MASK)

#define GPIO_MPIN_MPORTP26_MASK                  (0x4000000U)
#define GPIO_MPIN_MPORTP26_SHIFT                 (26U)
/*! MPORTP26 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP26(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP26_SHIFT)) & GPIO_MPIN_MPORTP26_MASK)

#define GPIO_MPIN_MPORTP27_MASK                  (0x8000000U)
#define GPIO_MPIN_MPORTP27_SHIFT                 (27U)
/*! MPORTP27 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP27(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP27_SHIFT)) & GPIO_MPIN_MPORTP27_MASK)

#define GPIO_MPIN_MPORTP28_MASK                  (0x10000000U)
#define GPIO_MPIN_MPORTP28_SHIFT                 (28U)
/*! MPORTP28 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP28(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP28_SHIFT)) & GPIO_MPIN_MPORTP28_MASK)

#define GPIO_MPIN_MPORTP29_MASK                  (0x20000000U)
#define GPIO_MPIN_MPORTP29_SHIFT                 (29U)
/*! MPORTP29 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP29(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP29_SHIFT)) & GPIO_MPIN_MPORTP29_MASK)

#define GPIO_MPIN_MPORTP30_MASK                  (0x40000000U)
#define GPIO_MPIN_MPORTP30_SHIFT                 (30U)
/*! MPORTP30 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP30(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP30_SHIFT)) & GPIO_MPIN_MPORTP30_MASK)

#define GPIO_MPIN_MPORTP31_MASK                  (0x80000000U)
#define GPIO_MPIN_MPORTP31_SHIFT                 (31U)
/*! MPORTP31 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP31(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP31_SHIFT)) & GPIO_MPIN_MPORTP31_MASK)
/*! @} */

/* The count of GPIO_MPIN */
#define GPIO_MPIN_COUNT                          (4U)

/*! @name SET - Port set */
/*! @{ */

#define GPIO_SET_SETP_MASK                       (0xFFFFFFFFU)
#define GPIO_SET_SETP_SHIFT                      (0U)
/*! SETP - Read or set output bits
 *  0b00000000000000000000000000000000..Read- output bit; write- no operation
 *  0b00000000000000000000000000000001..Read- output bit; write- set output bit
 */
#define GPIO_SET_SETP(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK)
/*! @} */

/* The count of GPIO_SET */
#define GPIO_SET_COUNT                           (4U)

/*! @name CLR - Port clear */
/*! @{ */

#define GPIO_CLR_CLRP0_MASK                      (0x1U)
#define GPIO_CLR_CLRP0_SHIFT                     (0U)
/*! CLRP0 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP0(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP0_SHIFT)) & GPIO_CLR_CLRP0_MASK)

#define GPIO_CLR_CLRP1_MASK                      (0x2U)
#define GPIO_CLR_CLRP1_SHIFT                     (1U)
/*! CLRP1 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP1(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP1_SHIFT)) & GPIO_CLR_CLRP1_MASK)

#define GPIO_CLR_CLRP2_MASK                      (0x4U)
#define GPIO_CLR_CLRP2_SHIFT                     (2U)
/*! CLRP2 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP2(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP2_SHIFT)) & GPIO_CLR_CLRP2_MASK)

#define GPIO_CLR_CLRP3_MASK                      (0x8U)
#define GPIO_CLR_CLRP3_SHIFT                     (3U)
/*! CLRP3 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP3(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP3_SHIFT)) & GPIO_CLR_CLRP3_MASK)

#define GPIO_CLR_CLRP4_MASK                      (0x10U)
#define GPIO_CLR_CLRP4_SHIFT                     (4U)
/*! CLRP4 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP4(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP4_SHIFT)) & GPIO_CLR_CLRP4_MASK)

#define GPIO_CLR_CLRP5_MASK                      (0x20U)
#define GPIO_CLR_CLRP5_SHIFT                     (5U)
/*! CLRP5 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP5(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP5_SHIFT)) & GPIO_CLR_CLRP5_MASK)

#define GPIO_CLR_CLRP6_MASK                      (0x40U)
#define GPIO_CLR_CLRP6_SHIFT                     (6U)
/*! CLRP6 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP6(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP6_SHIFT)) & GPIO_CLR_CLRP6_MASK)

#define GPIO_CLR_CLRP7_MASK                      (0x80U)
#define GPIO_CLR_CLRP7_SHIFT                     (7U)
/*! CLRP7 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP7(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP7_SHIFT)) & GPIO_CLR_CLRP7_MASK)

#define GPIO_CLR_CLRP8_MASK                      (0x100U)
#define GPIO_CLR_CLRP8_SHIFT                     (8U)
/*! CLRP8 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP8(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP8_SHIFT)) & GPIO_CLR_CLRP8_MASK)

#define GPIO_CLR_CLRP9_MASK                      (0x200U)
#define GPIO_CLR_CLRP9_SHIFT                     (9U)
/*! CLRP9 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP9(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP9_SHIFT)) & GPIO_CLR_CLRP9_MASK)

#define GPIO_CLR_CLRP10_MASK                     (0x400U)
#define GPIO_CLR_CLRP10_SHIFT                    (10U)
/*! CLRP10 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP10(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP10_SHIFT)) & GPIO_CLR_CLRP10_MASK)

#define GPIO_CLR_CLRP11_MASK                     (0x800U)
#define GPIO_CLR_CLRP11_SHIFT                    (11U)
/*! CLRP11 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP11(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP11_SHIFT)) & GPIO_CLR_CLRP11_MASK)

#define GPIO_CLR_CLRP12_MASK                     (0x1000U)
#define GPIO_CLR_CLRP12_SHIFT                    (12U)
/*! CLRP12 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP12(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP12_SHIFT)) & GPIO_CLR_CLRP12_MASK)

#define GPIO_CLR_CLRP13_MASK                     (0x2000U)
#define GPIO_CLR_CLRP13_SHIFT                    (13U)
/*! CLRP13 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP13(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP13_SHIFT)) & GPIO_CLR_CLRP13_MASK)

#define GPIO_CLR_CLRP14_MASK                     (0x4000U)
#define GPIO_CLR_CLRP14_SHIFT                    (14U)
/*! CLRP14 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP14(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP14_SHIFT)) & GPIO_CLR_CLRP14_MASK)

#define GPIO_CLR_CLRP15_MASK                     (0x8000U)
#define GPIO_CLR_CLRP15_SHIFT                    (15U)
/*! CLRP15 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP15(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP15_SHIFT)) & GPIO_CLR_CLRP15_MASK)

#define GPIO_CLR_CLRP16_MASK                     (0x10000U)
#define GPIO_CLR_CLRP16_SHIFT                    (16U)
/*! CLRP16 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP16(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP16_SHIFT)) & GPIO_CLR_CLRP16_MASK)

#define GPIO_CLR_CLRP17_MASK                     (0x20000U)
#define GPIO_CLR_CLRP17_SHIFT                    (17U)
/*! CLRP17 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP17(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP17_SHIFT)) & GPIO_CLR_CLRP17_MASK)

#define GPIO_CLR_CLRP18_MASK                     (0x40000U)
#define GPIO_CLR_CLRP18_SHIFT                    (18U)
/*! CLRP18 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP18(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP18_SHIFT)) & GPIO_CLR_CLRP18_MASK)

#define GPIO_CLR_CLRP19_MASK                     (0x80000U)
#define GPIO_CLR_CLRP19_SHIFT                    (19U)
/*! CLRP19 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP19(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP19_SHIFT)) & GPIO_CLR_CLRP19_MASK)

#define GPIO_CLR_CLRP20_MASK                     (0x100000U)
#define GPIO_CLR_CLRP20_SHIFT                    (20U)
/*! CLRP20 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP20(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP20_SHIFT)) & GPIO_CLR_CLRP20_MASK)

#define GPIO_CLR_CLRP21_MASK                     (0x200000U)
#define GPIO_CLR_CLRP21_SHIFT                    (21U)
/*! CLRP21 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP21(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP21_SHIFT)) & GPIO_CLR_CLRP21_MASK)

#define GPIO_CLR_CLRP22_MASK                     (0x400000U)
#define GPIO_CLR_CLRP22_SHIFT                    (22U)
/*! CLRP22 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP22(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP22_SHIFT)) & GPIO_CLR_CLRP22_MASK)

#define GPIO_CLR_CLRP23_MASK                     (0x800000U)
#define GPIO_CLR_CLRP23_SHIFT                    (23U)
/*! CLRP23 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP23(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP23_SHIFT)) & GPIO_CLR_CLRP23_MASK)

#define GPIO_CLR_CLRP24_MASK                     (0x1000000U)
#define GPIO_CLR_CLRP24_SHIFT                    (24U)
/*! CLRP24 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP24(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP24_SHIFT)) & GPIO_CLR_CLRP24_MASK)

#define GPIO_CLR_CLRP25_MASK                     (0x2000000U)
#define GPIO_CLR_CLRP25_SHIFT                    (25U)
/*! CLRP25 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP25(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP25_SHIFT)) & GPIO_CLR_CLRP25_MASK)

#define GPIO_CLR_CLRP26_MASK                     (0x4000000U)
#define GPIO_CLR_CLRP26_SHIFT                    (26U)
/*! CLRP26 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP26(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP26_SHIFT)) & GPIO_CLR_CLRP26_MASK)

#define GPIO_CLR_CLRP27_MASK                     (0x8000000U)
#define GPIO_CLR_CLRP27_SHIFT                    (27U)
/*! CLRP27 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP27(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP27_SHIFT)) & GPIO_CLR_CLRP27_MASK)

#define GPIO_CLR_CLRP28_MASK                     (0x10000000U)
#define GPIO_CLR_CLRP28_SHIFT                    (28U)
/*! CLRP28 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP28(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP28_SHIFT)) & GPIO_CLR_CLRP28_MASK)

#define GPIO_CLR_CLRP29_MASK                     (0x20000000U)
#define GPIO_CLR_CLRP29_SHIFT                    (29U)
/*! CLRP29 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP29(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP29_SHIFT)) & GPIO_CLR_CLRP29_MASK)

#define GPIO_CLR_CLRP30_MASK                     (0x40000000U)
#define GPIO_CLR_CLRP30_SHIFT                    (30U)
/*! CLRP30 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP30(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP30_SHIFT)) & GPIO_CLR_CLRP30_MASK)

#define GPIO_CLR_CLRP31_MASK                     (0x80000000U)
#define GPIO_CLR_CLRP31_SHIFT                    (31U)
/*! CLRP31 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP31(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP31_SHIFT)) & GPIO_CLR_CLRP31_MASK)
/*! @} */

/* The count of GPIO_CLR */
#define GPIO_CLR_COUNT                           (4U)

/*! @name NOT - Port toggle */
/*! @{ */

#define GPIO_NOT_NOTP0_MASK                      (0x1U)
#define GPIO_NOT_NOTP0_SHIFT                     (0U)
/*! NOTP0 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP0(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP0_SHIFT)) & GPIO_NOT_NOTP0_MASK)

#define GPIO_NOT_NOTP1_MASK                      (0x2U)
#define GPIO_NOT_NOTP1_SHIFT                     (1U)
/*! NOTP1 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP1(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP1_SHIFT)) & GPIO_NOT_NOTP1_MASK)

#define GPIO_NOT_NOTP2_MASK                      (0x4U)
#define GPIO_NOT_NOTP2_SHIFT                     (2U)
/*! NOTP2 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP2(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP2_SHIFT)) & GPIO_NOT_NOTP2_MASK)

#define GPIO_NOT_NOTP3_MASK                      (0x8U)
#define GPIO_NOT_NOTP3_SHIFT                     (3U)
/*! NOTP3 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP3(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP3_SHIFT)) & GPIO_NOT_NOTP3_MASK)

#define GPIO_NOT_NOTP4_MASK                      (0x10U)
#define GPIO_NOT_NOTP4_SHIFT                     (4U)
/*! NOTP4 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP4(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP4_SHIFT)) & GPIO_NOT_NOTP4_MASK)

#define GPIO_NOT_NOTP5_MASK                      (0x20U)
#define GPIO_NOT_NOTP5_SHIFT                     (5U)
/*! NOTP5 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP5(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP5_SHIFT)) & GPIO_NOT_NOTP5_MASK)

#define GPIO_NOT_NOTP6_MASK                      (0x40U)
#define GPIO_NOT_NOTP6_SHIFT                     (6U)
/*! NOTP6 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP6(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP6_SHIFT)) & GPIO_NOT_NOTP6_MASK)

#define GPIO_NOT_NOTP7_MASK                      (0x80U)
#define GPIO_NOT_NOTP7_SHIFT                     (7U)
/*! NOTP7 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP7(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP7_SHIFT)) & GPIO_NOT_NOTP7_MASK)

#define GPIO_NOT_NOTP8_MASK                      (0x100U)
#define GPIO_NOT_NOTP8_SHIFT                     (8U)
/*! NOTP8 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP8(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP8_SHIFT)) & GPIO_NOT_NOTP8_MASK)

#define GPIO_NOT_NOTP9_MASK                      (0x200U)
#define GPIO_NOT_NOTP9_SHIFT                     (9U)
/*! NOTP9 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP9(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP9_SHIFT)) & GPIO_NOT_NOTP9_MASK)

#define GPIO_NOT_NOTP10_MASK                     (0x400U)
#define GPIO_NOT_NOTP10_SHIFT                    (10U)
/*! NOTP10 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP10(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP10_SHIFT)) & GPIO_NOT_NOTP10_MASK)

#define GPIO_NOT_NOTP11_MASK                     (0x800U)
#define GPIO_NOT_NOTP11_SHIFT                    (11U)
/*! NOTP11 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP11(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP11_SHIFT)) & GPIO_NOT_NOTP11_MASK)

#define GPIO_NOT_NOTP12_MASK                     (0x1000U)
#define GPIO_NOT_NOTP12_SHIFT                    (12U)
/*! NOTP12 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP12(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP12_SHIFT)) & GPIO_NOT_NOTP12_MASK)

#define GPIO_NOT_NOTP13_MASK                     (0x2000U)
#define GPIO_NOT_NOTP13_SHIFT                    (13U)
/*! NOTP13 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP13(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP13_SHIFT)) & GPIO_NOT_NOTP13_MASK)

#define GPIO_NOT_NOTP14_MASK                     (0x4000U)
#define GPIO_NOT_NOTP14_SHIFT                    (14U)
/*! NOTP14 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP14(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP14_SHIFT)) & GPIO_NOT_NOTP14_MASK)

#define GPIO_NOT_NOTP15_MASK                     (0x8000U)
#define GPIO_NOT_NOTP15_SHIFT                    (15U)
/*! NOTP15 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP15(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP15_SHIFT)) & GPIO_NOT_NOTP15_MASK)

#define GPIO_NOT_NOTP16_MASK                     (0x10000U)
#define GPIO_NOT_NOTP16_SHIFT                    (16U)
/*! NOTP16 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP16(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP16_SHIFT)) & GPIO_NOT_NOTP16_MASK)

#define GPIO_NOT_NOTP17_MASK                     (0x20000U)
#define GPIO_NOT_NOTP17_SHIFT                    (17U)
/*! NOTP17 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP17(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP17_SHIFT)) & GPIO_NOT_NOTP17_MASK)

#define GPIO_NOT_NOTP18_MASK                     (0x40000U)
#define GPIO_NOT_NOTP18_SHIFT                    (18U)
/*! NOTP18 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP18(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP18_SHIFT)) & GPIO_NOT_NOTP18_MASK)

#define GPIO_NOT_NOTP19_MASK                     (0x80000U)
#define GPIO_NOT_NOTP19_SHIFT                    (19U)
/*! NOTP19 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP19(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP19_SHIFT)) & GPIO_NOT_NOTP19_MASK)

#define GPIO_NOT_NOTP20_MASK                     (0x100000U)
#define GPIO_NOT_NOTP20_SHIFT                    (20U)
/*! NOTP20 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP20(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP20_SHIFT)) & GPIO_NOT_NOTP20_MASK)

#define GPIO_NOT_NOTP21_MASK                     (0x200000U)
#define GPIO_NOT_NOTP21_SHIFT                    (21U)
/*! NOTP21 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP21(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP21_SHIFT)) & GPIO_NOT_NOTP21_MASK)

#define GPIO_NOT_NOTP22_MASK                     (0x400000U)
#define GPIO_NOT_NOTP22_SHIFT                    (22U)
/*! NOTP22 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP22(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP22_SHIFT)) & GPIO_NOT_NOTP22_MASK)

#define GPIO_NOT_NOTP23_MASK                     (0x800000U)
#define GPIO_NOT_NOTP23_SHIFT                    (23U)
/*! NOTP23 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP23(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP23_SHIFT)) & GPIO_NOT_NOTP23_MASK)

#define GPIO_NOT_NOTP24_MASK                     (0x1000000U)
#define GPIO_NOT_NOTP24_SHIFT                    (24U)
/*! NOTP24 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP24(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP24_SHIFT)) & GPIO_NOT_NOTP24_MASK)

#define GPIO_NOT_NOTP25_MASK                     (0x2000000U)
#define GPIO_NOT_NOTP25_SHIFT                    (25U)
/*! NOTP25 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP25(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP25_SHIFT)) & GPIO_NOT_NOTP25_MASK)

#define GPIO_NOT_NOTP26_MASK                     (0x4000000U)
#define GPIO_NOT_NOTP26_SHIFT                    (26U)
/*! NOTP26 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP26(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP26_SHIFT)) & GPIO_NOT_NOTP26_MASK)

#define GPIO_NOT_NOTP27_MASK                     (0x8000000U)
#define GPIO_NOT_NOTP27_SHIFT                    (27U)
/*! NOTP27 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP27(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP27_SHIFT)) & GPIO_NOT_NOTP27_MASK)

#define GPIO_NOT_NOTP28_MASK                     (0x10000000U)
#define GPIO_NOT_NOTP28_SHIFT                    (28U)
/*! NOTP28 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP28(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP28_SHIFT)) & GPIO_NOT_NOTP28_MASK)

#define GPIO_NOT_NOTP29_MASK                     (0x20000000U)
#define GPIO_NOT_NOTP29_SHIFT                    (29U)
/*! NOTP29 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP29(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP29_SHIFT)) & GPIO_NOT_NOTP29_MASK)

#define GPIO_NOT_NOTP30_MASK                     (0x40000000U)
#define GPIO_NOT_NOTP30_SHIFT                    (30U)
/*! NOTP30 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP30(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP30_SHIFT)) & GPIO_NOT_NOTP30_MASK)

#define GPIO_NOT_NOTP31_MASK                     (0x80000000U)
#define GPIO_NOT_NOTP31_SHIFT                    (31U)
/*! NOTP31 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP31(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP31_SHIFT)) & GPIO_NOT_NOTP31_MASK)
/*! @} */

/* The count of GPIO_NOT */
#define GPIO_NOT_COUNT                           (4U)

/*! @name DIRSET - Port direction set */
/*! @{ */

#define GPIO_DIRSET_DIRSETP0_MASK                (0x1U)
#define GPIO_DIRSET_DIRSETP0_SHIFT               (0U)
/*! DIRSETP0 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP0(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP0_SHIFT)) & GPIO_DIRSET_DIRSETP0_MASK)

#define GPIO_DIRSET_DIRSETP1_MASK                (0x2U)
#define GPIO_DIRSET_DIRSETP1_SHIFT               (1U)
/*! DIRSETP1 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP1(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP1_SHIFT)) & GPIO_DIRSET_DIRSETP1_MASK)

#define GPIO_DIRSET_DIRSETP2_MASK                (0x4U)
#define GPIO_DIRSET_DIRSETP2_SHIFT               (2U)
/*! DIRSETP2 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP2(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP2_SHIFT)) & GPIO_DIRSET_DIRSETP2_MASK)

#define GPIO_DIRSET_DIRSETP3_MASK                (0x8U)
#define GPIO_DIRSET_DIRSETP3_SHIFT               (3U)
/*! DIRSETP3 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP3(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP3_SHIFT)) & GPIO_DIRSET_DIRSETP3_MASK)

#define GPIO_DIRSET_DIRSETP4_MASK                (0x10U)
#define GPIO_DIRSET_DIRSETP4_SHIFT               (4U)
/*! DIRSETP4 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP4(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP4_SHIFT)) & GPIO_DIRSET_DIRSETP4_MASK)

#define GPIO_DIRSET_DIRSETP5_MASK                (0x20U)
#define GPIO_DIRSET_DIRSETP5_SHIFT               (5U)
/*! DIRSETP5 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP5(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP5_SHIFT)) & GPIO_DIRSET_DIRSETP5_MASK)

#define GPIO_DIRSET_DIRSETP6_MASK                (0x40U)
#define GPIO_DIRSET_DIRSETP6_SHIFT               (6U)
/*! DIRSETP6 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP6(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP6_SHIFT)) & GPIO_DIRSET_DIRSETP6_MASK)

#define GPIO_DIRSET_DIRSETP7_MASK                (0x80U)
#define GPIO_DIRSET_DIRSETP7_SHIFT               (7U)
/*! DIRSETP7 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP7(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP7_SHIFT)) & GPIO_DIRSET_DIRSETP7_MASK)

#define GPIO_DIRSET_DIRSETP8_MASK                (0x100U)
#define GPIO_DIRSET_DIRSETP8_SHIFT               (8U)
/*! DIRSETP8 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP8(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP8_SHIFT)) & GPIO_DIRSET_DIRSETP8_MASK)

#define GPIO_DIRSET_DIRSETP9_MASK                (0x200U)
#define GPIO_DIRSET_DIRSETP9_SHIFT               (9U)
/*! DIRSETP9 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP9(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP9_SHIFT)) & GPIO_DIRSET_DIRSETP9_MASK)

#define GPIO_DIRSET_DIRSETP10_MASK               (0x400U)
#define GPIO_DIRSET_DIRSETP10_SHIFT              (10U)
/*! DIRSETP10 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP10(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP10_SHIFT)) & GPIO_DIRSET_DIRSETP10_MASK)

#define GPIO_DIRSET_DIRSETP11_MASK               (0x800U)
#define GPIO_DIRSET_DIRSETP11_SHIFT              (11U)
/*! DIRSETP11 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP11(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP11_SHIFT)) & GPIO_DIRSET_DIRSETP11_MASK)

#define GPIO_DIRSET_DIRSETP12_MASK               (0x1000U)
#define GPIO_DIRSET_DIRSETP12_SHIFT              (12U)
/*! DIRSETP12 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP12(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP12_SHIFT)) & GPIO_DIRSET_DIRSETP12_MASK)

#define GPIO_DIRSET_DIRSETP13_MASK               (0x2000U)
#define GPIO_DIRSET_DIRSETP13_SHIFT              (13U)
/*! DIRSETP13 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP13(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP13_SHIFT)) & GPIO_DIRSET_DIRSETP13_MASK)

#define GPIO_DIRSET_DIRSETP14_MASK               (0x4000U)
#define GPIO_DIRSET_DIRSETP14_SHIFT              (14U)
/*! DIRSETP14 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP14(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP14_SHIFT)) & GPIO_DIRSET_DIRSETP14_MASK)

#define GPIO_DIRSET_DIRSETP15_MASK               (0x8000U)
#define GPIO_DIRSET_DIRSETP15_SHIFT              (15U)
/*! DIRSETP15 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP15(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP15_SHIFT)) & GPIO_DIRSET_DIRSETP15_MASK)

#define GPIO_DIRSET_DIRSETP16_MASK               (0x10000U)
#define GPIO_DIRSET_DIRSETP16_SHIFT              (16U)
/*! DIRSETP16 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP16(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP16_SHIFT)) & GPIO_DIRSET_DIRSETP16_MASK)

#define GPIO_DIRSET_DIRSETP17_MASK               (0x20000U)
#define GPIO_DIRSET_DIRSETP17_SHIFT              (17U)
/*! DIRSETP17 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP17(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP17_SHIFT)) & GPIO_DIRSET_DIRSETP17_MASK)

#define GPIO_DIRSET_DIRSETP18_MASK               (0x40000U)
#define GPIO_DIRSET_DIRSETP18_SHIFT              (18U)
/*! DIRSETP18 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP18(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP18_SHIFT)) & GPIO_DIRSET_DIRSETP18_MASK)

#define GPIO_DIRSET_DIRSETP19_MASK               (0x80000U)
#define GPIO_DIRSET_DIRSETP19_SHIFT              (19U)
/*! DIRSETP19 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP19(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP19_SHIFT)) & GPIO_DIRSET_DIRSETP19_MASK)

#define GPIO_DIRSET_DIRSETP20_MASK               (0x100000U)
#define GPIO_DIRSET_DIRSETP20_SHIFT              (20U)
/*! DIRSETP20 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP20(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP20_SHIFT)) & GPIO_DIRSET_DIRSETP20_MASK)

#define GPIO_DIRSET_DIRSETP21_MASK               (0x200000U)
#define GPIO_DIRSET_DIRSETP21_SHIFT              (21U)
/*! DIRSETP21 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP21(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP21_SHIFT)) & GPIO_DIRSET_DIRSETP21_MASK)

#define GPIO_DIRSET_DIRSETP22_MASK               (0x400000U)
#define GPIO_DIRSET_DIRSETP22_SHIFT              (22U)
/*! DIRSETP22 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP22(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP22_SHIFT)) & GPIO_DIRSET_DIRSETP22_MASK)

#define GPIO_DIRSET_DIRSETP23_MASK               (0x800000U)
#define GPIO_DIRSET_DIRSETP23_SHIFT              (23U)
/*! DIRSETP23 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP23(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP23_SHIFT)) & GPIO_DIRSET_DIRSETP23_MASK)

#define GPIO_DIRSET_DIRSETP24_MASK               (0x1000000U)
#define GPIO_DIRSET_DIRSETP24_SHIFT              (24U)
/*! DIRSETP24 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP24(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP24_SHIFT)) & GPIO_DIRSET_DIRSETP24_MASK)

#define GPIO_DIRSET_DIRSETP25_MASK               (0x2000000U)
#define GPIO_DIRSET_DIRSETP25_SHIFT              (25U)
/*! DIRSETP25 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP25(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP25_SHIFT)) & GPIO_DIRSET_DIRSETP25_MASK)

#define GPIO_DIRSET_DIRSETP26_MASK               (0x4000000U)
#define GPIO_DIRSET_DIRSETP26_SHIFT              (26U)
/*! DIRSETP26 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP26(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP26_SHIFT)) & GPIO_DIRSET_DIRSETP26_MASK)

#define GPIO_DIRSET_DIRSETP27_MASK               (0x8000000U)
#define GPIO_DIRSET_DIRSETP27_SHIFT              (27U)
/*! DIRSETP27 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP27(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP27_SHIFT)) & GPIO_DIRSET_DIRSETP27_MASK)

#define GPIO_DIRSET_DIRSETP28_MASK               (0x10000000U)
#define GPIO_DIRSET_DIRSETP28_SHIFT              (28U)
/*! DIRSETP28 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP28(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP28_SHIFT)) & GPIO_DIRSET_DIRSETP28_MASK)

#define GPIO_DIRSET_DIRSETP29_MASK               (0x20000000U)
#define GPIO_DIRSET_DIRSETP29_SHIFT              (29U)
/*! DIRSETP29 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP29(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP29_SHIFT)) & GPIO_DIRSET_DIRSETP29_MASK)

#define GPIO_DIRSET_DIRSETP30_MASK               (0x40000000U)
#define GPIO_DIRSET_DIRSETP30_SHIFT              (30U)
/*! DIRSETP30 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP30(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP30_SHIFT)) & GPIO_DIRSET_DIRSETP30_MASK)

#define GPIO_DIRSET_DIRSETP31_MASK               (0x80000000U)
#define GPIO_DIRSET_DIRSETP31_SHIFT              (31U)
/*! DIRSETP31 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP31(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP31_SHIFT)) & GPIO_DIRSET_DIRSETP31_MASK)
/*! @} */

/* The count of GPIO_DIRSET */
#define GPIO_DIRSET_COUNT                        (4U)

/*! @name DIRCLR - Port direction clear */
/*! @{ */

#define GPIO_DIRCLR_DIRCLRP0_MASK                (0x1U)
#define GPIO_DIRCLR_DIRCLRP0_SHIFT               (0U)
/*! DIRCLRP0 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP0(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP0_SHIFT)) & GPIO_DIRCLR_DIRCLRP0_MASK)

#define GPIO_DIRCLR_DIRCLRP1_MASK                (0x2U)
#define GPIO_DIRCLR_DIRCLRP1_SHIFT               (1U)
/*! DIRCLRP1 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP1(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP1_SHIFT)) & GPIO_DIRCLR_DIRCLRP1_MASK)

#define GPIO_DIRCLR_DIRCLRP2_MASK                (0x4U)
#define GPIO_DIRCLR_DIRCLRP2_SHIFT               (2U)
/*! DIRCLRP2 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP2(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP2_SHIFT)) & GPIO_DIRCLR_DIRCLRP2_MASK)

#define GPIO_DIRCLR_DIRCLRP3_MASK                (0x8U)
#define GPIO_DIRCLR_DIRCLRP3_SHIFT               (3U)
/*! DIRCLRP3 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP3(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP3_SHIFT)) & GPIO_DIRCLR_DIRCLRP3_MASK)

#define GPIO_DIRCLR_DIRCLRP4_MASK                (0x10U)
#define GPIO_DIRCLR_DIRCLRP4_SHIFT               (4U)
/*! DIRCLRP4 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP4(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP4_SHIFT)) & GPIO_DIRCLR_DIRCLRP4_MASK)

#define GPIO_DIRCLR_DIRCLRP5_MASK                (0x20U)
#define GPIO_DIRCLR_DIRCLRP5_SHIFT               (5U)
/*! DIRCLRP5 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP5(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP5_SHIFT)) & GPIO_DIRCLR_DIRCLRP5_MASK)

#define GPIO_DIRCLR_DIRCLRP6_MASK                (0x40U)
#define GPIO_DIRCLR_DIRCLRP6_SHIFT               (6U)
/*! DIRCLRP6 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP6(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP6_SHIFT)) & GPIO_DIRCLR_DIRCLRP6_MASK)

#define GPIO_DIRCLR_DIRCLRP7_MASK                (0x80U)
#define GPIO_DIRCLR_DIRCLRP7_SHIFT               (7U)
/*! DIRCLRP7 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP7(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP7_SHIFT)) & GPIO_DIRCLR_DIRCLRP7_MASK)

#define GPIO_DIRCLR_DIRCLRP8_MASK                (0x100U)
#define GPIO_DIRCLR_DIRCLRP8_SHIFT               (8U)
/*! DIRCLRP8 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP8(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP8_SHIFT)) & GPIO_DIRCLR_DIRCLRP8_MASK)

#define GPIO_DIRCLR_DIRCLRP9_MASK                (0x200U)
#define GPIO_DIRCLR_DIRCLRP9_SHIFT               (9U)
/*! DIRCLRP9 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP9(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP9_SHIFT)) & GPIO_DIRCLR_DIRCLRP9_MASK)

#define GPIO_DIRCLR_DIRCLRP10_MASK               (0x400U)
#define GPIO_DIRCLR_DIRCLRP10_SHIFT              (10U)
/*! DIRCLRP10 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP10(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP10_SHIFT)) & GPIO_DIRCLR_DIRCLRP10_MASK)

#define GPIO_DIRCLR_DIRCLRP11_MASK               (0x800U)
#define GPIO_DIRCLR_DIRCLRP11_SHIFT              (11U)
/*! DIRCLRP11 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP11(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP11_SHIFT)) & GPIO_DIRCLR_DIRCLRP11_MASK)

#define GPIO_DIRCLR_DIRCLRP12_MASK               (0x1000U)
#define GPIO_DIRCLR_DIRCLRP12_SHIFT              (12U)
/*! DIRCLRP12 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP12(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP12_SHIFT)) & GPIO_DIRCLR_DIRCLRP12_MASK)

#define GPIO_DIRCLR_DIRCLRP13_MASK               (0x2000U)
#define GPIO_DIRCLR_DIRCLRP13_SHIFT              (13U)
/*! DIRCLRP13 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP13(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP13_SHIFT)) & GPIO_DIRCLR_DIRCLRP13_MASK)

#define GPIO_DIRCLR_DIRCLRP14_MASK               (0x4000U)
#define GPIO_DIRCLR_DIRCLRP14_SHIFT              (14U)
/*! DIRCLRP14 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP14(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP14_SHIFT)) & GPIO_DIRCLR_DIRCLRP14_MASK)

#define GPIO_DIRCLR_DIRCLRP15_MASK               (0x8000U)
#define GPIO_DIRCLR_DIRCLRP15_SHIFT              (15U)
/*! DIRCLRP15 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP15(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP15_SHIFT)) & GPIO_DIRCLR_DIRCLRP15_MASK)

#define GPIO_DIRCLR_DIRCLRP16_MASK               (0x10000U)
#define GPIO_DIRCLR_DIRCLRP16_SHIFT              (16U)
/*! DIRCLRP16 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP16(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP16_SHIFT)) & GPIO_DIRCLR_DIRCLRP16_MASK)

#define GPIO_DIRCLR_DIRCLRP17_MASK               (0x20000U)
#define GPIO_DIRCLR_DIRCLRP17_SHIFT              (17U)
/*! DIRCLRP17 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP17(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP17_SHIFT)) & GPIO_DIRCLR_DIRCLRP17_MASK)

#define GPIO_DIRCLR_DIRCLRP18_MASK               (0x40000U)
#define GPIO_DIRCLR_DIRCLRP18_SHIFT              (18U)
/*! DIRCLRP18 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP18(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP18_SHIFT)) & GPIO_DIRCLR_DIRCLRP18_MASK)

#define GPIO_DIRCLR_DIRCLRP19_MASK               (0x80000U)
#define GPIO_DIRCLR_DIRCLRP19_SHIFT              (19U)
/*! DIRCLRP19 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP19(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP19_SHIFT)) & GPIO_DIRCLR_DIRCLRP19_MASK)

#define GPIO_DIRCLR_DIRCLRP20_MASK               (0x100000U)
#define GPIO_DIRCLR_DIRCLRP20_SHIFT              (20U)
/*! DIRCLRP20 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP20(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP20_SHIFT)) & GPIO_DIRCLR_DIRCLRP20_MASK)

#define GPIO_DIRCLR_DIRCLRP21_MASK               (0x200000U)
#define GPIO_DIRCLR_DIRCLRP21_SHIFT              (21U)
/*! DIRCLRP21 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP21(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP21_SHIFT)) & GPIO_DIRCLR_DIRCLRP21_MASK)

#define GPIO_DIRCLR_DIRCLRP22_MASK               (0x400000U)
#define GPIO_DIRCLR_DIRCLRP22_SHIFT              (22U)
/*! DIRCLRP22 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP22(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP22_SHIFT)) & GPIO_DIRCLR_DIRCLRP22_MASK)

#define GPIO_DIRCLR_DIRCLRP23_MASK               (0x800000U)
#define GPIO_DIRCLR_DIRCLRP23_SHIFT              (23U)
/*! DIRCLRP23 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP23(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP23_SHIFT)) & GPIO_DIRCLR_DIRCLRP23_MASK)

#define GPIO_DIRCLR_DIRCLRP24_MASK               (0x1000000U)
#define GPIO_DIRCLR_DIRCLRP24_SHIFT              (24U)
/*! DIRCLRP24 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP24(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP24_SHIFT)) & GPIO_DIRCLR_DIRCLRP24_MASK)

#define GPIO_DIRCLR_DIRCLRP25_MASK               (0x2000000U)
#define GPIO_DIRCLR_DIRCLRP25_SHIFT              (25U)
/*! DIRCLRP25 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP25(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP25_SHIFT)) & GPIO_DIRCLR_DIRCLRP25_MASK)

#define GPIO_DIRCLR_DIRCLRP26_MASK               (0x4000000U)
#define GPIO_DIRCLR_DIRCLRP26_SHIFT              (26U)
/*! DIRCLRP26 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP26(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP26_SHIFT)) & GPIO_DIRCLR_DIRCLRP26_MASK)

#define GPIO_DIRCLR_DIRCLRP27_MASK               (0x8000000U)
#define GPIO_DIRCLR_DIRCLRP27_SHIFT              (27U)
/*! DIRCLRP27 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP27(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP27_SHIFT)) & GPIO_DIRCLR_DIRCLRP27_MASK)

#define GPIO_DIRCLR_DIRCLRP28_MASK               (0x10000000U)
#define GPIO_DIRCLR_DIRCLRP28_SHIFT              (28U)
/*! DIRCLRP28 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP28(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP28_SHIFT)) & GPIO_DIRCLR_DIRCLRP28_MASK)

#define GPIO_DIRCLR_DIRCLRP29_MASK               (0x20000000U)
#define GPIO_DIRCLR_DIRCLRP29_SHIFT              (29U)
/*! DIRCLRP29 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP29(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP29_SHIFT)) & GPIO_DIRCLR_DIRCLRP29_MASK)

#define GPIO_DIRCLR_DIRCLRP30_MASK               (0x40000000U)
#define GPIO_DIRCLR_DIRCLRP30_SHIFT              (30U)
/*! DIRCLRP30 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP30(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP30_SHIFT)) & GPIO_DIRCLR_DIRCLRP30_MASK)

#define GPIO_DIRCLR_DIRCLRP31_MASK               (0x80000000U)
#define GPIO_DIRCLR_DIRCLRP31_SHIFT              (31U)
/*! DIRCLRP31 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP31(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP31_SHIFT)) & GPIO_DIRCLR_DIRCLRP31_MASK)
/*! @} */

/* The count of GPIO_DIRCLR */
#define GPIO_DIRCLR_COUNT                        (4U)

/*! @name DIRNOT - Port direction toggle */
/*! @{ */

#define GPIO_DIRNOT_DIRNOTP_MASK                 (0x1FFFFFFFU)
#define GPIO_DIRNOT_DIRNOTP_SHIFT                (0U)
/*! DIRNOTP - Toggle direction bits.
 *  0b00000000000000000000000000000..No operation
 *  0b00000000000000000000000000001..Toggles direction bit
 */
#define GPIO_DIRNOT_DIRNOTP(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK)
/*! @} */

/* The count of GPIO_DIRNOT */
#define GPIO_DIRNOT_COUNT                        (4U)

/*! @name INTENA - Interrupt A enable control */
/*! @{ */

#define GPIO_INTENA_INT_EN0_MASK                 (0x1U)
#define GPIO_INTENA_INT_EN0_SHIFT                (0U)
/*! INT_EN0 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN0(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN0_SHIFT)) & GPIO_INTENA_INT_EN0_MASK)

#define GPIO_INTENA_INT_EN1_MASK                 (0x2U)
#define GPIO_INTENA_INT_EN1_SHIFT                (1U)
/*! INT_EN1 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN1(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN1_SHIFT)) & GPIO_INTENA_INT_EN1_MASK)

#define GPIO_INTENA_INT_EN2_MASK                 (0x4U)
#define GPIO_INTENA_INT_EN2_SHIFT                (2U)
/*! INT_EN2 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN2(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN2_SHIFT)) & GPIO_INTENA_INT_EN2_MASK)

#define GPIO_INTENA_INT_EN3_MASK                 (0x8U)
#define GPIO_INTENA_INT_EN3_SHIFT                (3U)
/*! INT_EN3 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN3(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN3_SHIFT)) & GPIO_INTENA_INT_EN3_MASK)

#define GPIO_INTENA_INT_EN4_MASK                 (0x10U)
#define GPIO_INTENA_INT_EN4_SHIFT                (4U)
/*! INT_EN4 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN4(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN4_SHIFT)) & GPIO_INTENA_INT_EN4_MASK)

#define GPIO_INTENA_INT_EN5_MASK                 (0x20U)
#define GPIO_INTENA_INT_EN5_SHIFT                (5U)
/*! INT_EN5 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN5(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN5_SHIFT)) & GPIO_INTENA_INT_EN5_MASK)

#define GPIO_INTENA_INT_EN6_MASK                 (0x40U)
#define GPIO_INTENA_INT_EN6_SHIFT                (6U)
/*! INT_EN6 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN6(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN6_SHIFT)) & GPIO_INTENA_INT_EN6_MASK)

#define GPIO_INTENA_INT_EN7_MASK                 (0x80U)
#define GPIO_INTENA_INT_EN7_SHIFT                (7U)
/*! INT_EN7 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN7(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN7_SHIFT)) & GPIO_INTENA_INT_EN7_MASK)

#define GPIO_INTENA_INT_EN8_MASK                 (0x100U)
#define GPIO_INTENA_INT_EN8_SHIFT                (8U)
/*! INT_EN8 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN8(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN8_SHIFT)) & GPIO_INTENA_INT_EN8_MASK)

#define GPIO_INTENA_INT_EN9_MASK                 (0x200U)
#define GPIO_INTENA_INT_EN9_SHIFT                (9U)
/*! INT_EN9 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN9(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN9_SHIFT)) & GPIO_INTENA_INT_EN9_MASK)

#define GPIO_INTENA_INT_EN10_MASK                (0x400U)
#define GPIO_INTENA_INT_EN10_SHIFT               (10U)
/*! INT_EN10 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN10(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN10_SHIFT)) & GPIO_INTENA_INT_EN10_MASK)

#define GPIO_INTENA_INT_EN11_MASK                (0x800U)
#define GPIO_INTENA_INT_EN11_SHIFT               (11U)
/*! INT_EN11 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN11(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN11_SHIFT)) & GPIO_INTENA_INT_EN11_MASK)

#define GPIO_INTENA_INT_EN12_MASK                (0x1000U)
#define GPIO_INTENA_INT_EN12_SHIFT               (12U)
/*! INT_EN12 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN12(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN12_SHIFT)) & GPIO_INTENA_INT_EN12_MASK)

#define GPIO_INTENA_INT_EN13_MASK                (0x2000U)
#define GPIO_INTENA_INT_EN13_SHIFT               (13U)
/*! INT_EN13 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN13(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN13_SHIFT)) & GPIO_INTENA_INT_EN13_MASK)

#define GPIO_INTENA_INT_EN14_MASK                (0x4000U)
#define GPIO_INTENA_INT_EN14_SHIFT               (14U)
/*! INT_EN14 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN14(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN14_SHIFT)) & GPIO_INTENA_INT_EN14_MASK)

#define GPIO_INTENA_INT_EN15_MASK                (0x8000U)
#define GPIO_INTENA_INT_EN15_SHIFT               (15U)
/*! INT_EN15 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN15(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN15_SHIFT)) & GPIO_INTENA_INT_EN15_MASK)

#define GPIO_INTENA_INT_EN16_MASK                (0x10000U)
#define GPIO_INTENA_INT_EN16_SHIFT               (16U)
/*! INT_EN16 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN16(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN16_SHIFT)) & GPIO_INTENA_INT_EN16_MASK)

#define GPIO_INTENA_INT_EN17_MASK                (0x20000U)
#define GPIO_INTENA_INT_EN17_SHIFT               (17U)
/*! INT_EN17 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN17(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN17_SHIFT)) & GPIO_INTENA_INT_EN17_MASK)

#define GPIO_INTENA_INT_EN18_MASK                (0x40000U)
#define GPIO_INTENA_INT_EN18_SHIFT               (18U)
/*! INT_EN18 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN18(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN18_SHIFT)) & GPIO_INTENA_INT_EN18_MASK)

#define GPIO_INTENA_INT_EN19_MASK                (0x80000U)
#define GPIO_INTENA_INT_EN19_SHIFT               (19U)
/*! INT_EN19 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN19(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN19_SHIFT)) & GPIO_INTENA_INT_EN19_MASK)

#define GPIO_INTENA_INT_EN20_MASK                (0x100000U)
#define GPIO_INTENA_INT_EN20_SHIFT               (20U)
/*! INT_EN20 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN20(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN20_SHIFT)) & GPIO_INTENA_INT_EN20_MASK)

#define GPIO_INTENA_INT_EN21_MASK                (0x200000U)
#define GPIO_INTENA_INT_EN21_SHIFT               (21U)
/*! INT_EN21 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN21(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN21_SHIFT)) & GPIO_INTENA_INT_EN21_MASK)

#define GPIO_INTENA_INT_EN22_MASK                (0x400000U)
#define GPIO_INTENA_INT_EN22_SHIFT               (22U)
/*! INT_EN22 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN22(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN22_SHIFT)) & GPIO_INTENA_INT_EN22_MASK)

#define GPIO_INTENA_INT_EN23_MASK                (0x800000U)
#define GPIO_INTENA_INT_EN23_SHIFT               (23U)
/*! INT_EN23 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN23(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN23_SHIFT)) & GPIO_INTENA_INT_EN23_MASK)

#define GPIO_INTENA_INT_EN24_MASK                (0x1000000U)
#define GPIO_INTENA_INT_EN24_SHIFT               (24U)
/*! INT_EN24 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN24(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN24_SHIFT)) & GPIO_INTENA_INT_EN24_MASK)

#define GPIO_INTENA_INT_EN25_MASK                (0x2000000U)
#define GPIO_INTENA_INT_EN25_SHIFT               (25U)
/*! INT_EN25 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN25(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN25_SHIFT)) & GPIO_INTENA_INT_EN25_MASK)

#define GPIO_INTENA_INT_EN26_MASK                (0x4000000U)
#define GPIO_INTENA_INT_EN26_SHIFT               (26U)
/*! INT_EN26 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN26(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN26_SHIFT)) & GPIO_INTENA_INT_EN26_MASK)

#define GPIO_INTENA_INT_EN27_MASK                (0x8000000U)
#define GPIO_INTENA_INT_EN27_SHIFT               (27U)
/*! INT_EN27 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN27(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN27_SHIFT)) & GPIO_INTENA_INT_EN27_MASK)

#define GPIO_INTENA_INT_EN28_MASK                (0x10000000U)
#define GPIO_INTENA_INT_EN28_SHIFT               (28U)
/*! INT_EN28 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN28(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN28_SHIFT)) & GPIO_INTENA_INT_EN28_MASK)

#define GPIO_INTENA_INT_EN29_MASK                (0x20000000U)
#define GPIO_INTENA_INT_EN29_SHIFT               (29U)
/*! INT_EN29 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN29(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN29_SHIFT)) & GPIO_INTENA_INT_EN29_MASK)

#define GPIO_INTENA_INT_EN30_MASK                (0x40000000U)
#define GPIO_INTENA_INT_EN30_SHIFT               (30U)
/*! INT_EN30 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN30(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN30_SHIFT)) & GPIO_INTENA_INT_EN30_MASK)

#define GPIO_INTENA_INT_EN31_MASK                (0x80000000U)
#define GPIO_INTENA_INT_EN31_SHIFT               (31U)
/*! INT_EN31 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN31(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN31_SHIFT)) & GPIO_INTENA_INT_EN31_MASK)
/*! @} */

/* The count of GPIO_INTENA */
#define GPIO_INTENA_COUNT                        (4U)

/*! @name INTENB - Interrupt B enable control */
/*! @{ */

#define GPIO_INTENB_INT_EN0_MASK                 (0x1U)
#define GPIO_INTENB_INT_EN0_SHIFT                (0U)
/*! INT_EN0 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN0(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN0_SHIFT)) & GPIO_INTENB_INT_EN0_MASK)

#define GPIO_INTENB_INT_EN1_MASK                 (0x2U)
#define GPIO_INTENB_INT_EN1_SHIFT                (1U)
/*! INT_EN1 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN1(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN1_SHIFT)) & GPIO_INTENB_INT_EN1_MASK)

#define GPIO_INTENB_INT_EN2_MASK                 (0x4U)
#define GPIO_INTENB_INT_EN2_SHIFT                (2U)
/*! INT_EN2 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN2(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN2_SHIFT)) & GPIO_INTENB_INT_EN2_MASK)

#define GPIO_INTENB_INT_EN3_MASK                 (0x8U)
#define GPIO_INTENB_INT_EN3_SHIFT                (3U)
/*! INT_EN3 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN3(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN3_SHIFT)) & GPIO_INTENB_INT_EN3_MASK)

#define GPIO_INTENB_INT_EN4_MASK                 (0x10U)
#define GPIO_INTENB_INT_EN4_SHIFT                (4U)
/*! INT_EN4 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN4(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN4_SHIFT)) & GPIO_INTENB_INT_EN4_MASK)

#define GPIO_INTENB_INT_EN5_MASK                 (0x20U)
#define GPIO_INTENB_INT_EN5_SHIFT                (5U)
/*! INT_EN5 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN5(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN5_SHIFT)) & GPIO_INTENB_INT_EN5_MASK)

#define GPIO_INTENB_INT_EN6_MASK                 (0x40U)
#define GPIO_INTENB_INT_EN6_SHIFT                (6U)
/*! INT_EN6 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN6(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN6_SHIFT)) & GPIO_INTENB_INT_EN6_MASK)

#define GPIO_INTENB_INT_EN7_MASK                 (0x80U)
#define GPIO_INTENB_INT_EN7_SHIFT                (7U)
/*! INT_EN7 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN7(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN7_SHIFT)) & GPIO_INTENB_INT_EN7_MASK)

#define GPIO_INTENB_INT_EN8_MASK                 (0x100U)
#define GPIO_INTENB_INT_EN8_SHIFT                (8U)
/*! INT_EN8 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN8(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN8_SHIFT)) & GPIO_INTENB_INT_EN8_MASK)

#define GPIO_INTENB_INT_EN9_MASK                 (0x200U)
#define GPIO_INTENB_INT_EN9_SHIFT                (9U)
/*! INT_EN9 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN9(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN9_SHIFT)) & GPIO_INTENB_INT_EN9_MASK)

#define GPIO_INTENB_INT_EN10_MASK                (0x400U)
#define GPIO_INTENB_INT_EN10_SHIFT               (10U)
/*! INT_EN10 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN10(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN10_SHIFT)) & GPIO_INTENB_INT_EN10_MASK)

#define GPIO_INTENB_INT_EN11_MASK                (0x800U)
#define GPIO_INTENB_INT_EN11_SHIFT               (11U)
/*! INT_EN11 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN11(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN11_SHIFT)) & GPIO_INTENB_INT_EN11_MASK)

#define GPIO_INTENB_INT_EN12_MASK                (0x1000U)
#define GPIO_INTENB_INT_EN12_SHIFT               (12U)
/*! INT_EN12 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN12(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN12_SHIFT)) & GPIO_INTENB_INT_EN12_MASK)

#define GPIO_INTENB_INT_EN13_MASK                (0x2000U)
#define GPIO_INTENB_INT_EN13_SHIFT               (13U)
/*! INT_EN13 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN13(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN13_SHIFT)) & GPIO_INTENB_INT_EN13_MASK)

#define GPIO_INTENB_INT_EN14_MASK                (0x4000U)
#define GPIO_INTENB_INT_EN14_SHIFT               (14U)
/*! INT_EN14 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN14(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN14_SHIFT)) & GPIO_INTENB_INT_EN14_MASK)

#define GPIO_INTENB_INT_EN15_MASK                (0x8000U)
#define GPIO_INTENB_INT_EN15_SHIFT               (15U)
/*! INT_EN15 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN15(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN15_SHIFT)) & GPIO_INTENB_INT_EN15_MASK)

#define GPIO_INTENB_INT_EN16_MASK                (0x10000U)
#define GPIO_INTENB_INT_EN16_SHIFT               (16U)
/*! INT_EN16 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN16(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN16_SHIFT)) & GPIO_INTENB_INT_EN16_MASK)

#define GPIO_INTENB_INT_EN17_MASK                (0x20000U)
#define GPIO_INTENB_INT_EN17_SHIFT               (17U)
/*! INT_EN17 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN17(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN17_SHIFT)) & GPIO_INTENB_INT_EN17_MASK)

#define GPIO_INTENB_INT_EN18_MASK                (0x40000U)
#define GPIO_INTENB_INT_EN18_SHIFT               (18U)
/*! INT_EN18 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN18(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN18_SHIFT)) & GPIO_INTENB_INT_EN18_MASK)

#define GPIO_INTENB_INT_EN19_MASK                (0x80000U)
#define GPIO_INTENB_INT_EN19_SHIFT               (19U)
/*! INT_EN19 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN19(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN19_SHIFT)) & GPIO_INTENB_INT_EN19_MASK)

#define GPIO_INTENB_INT_EN20_MASK                (0x100000U)
#define GPIO_INTENB_INT_EN20_SHIFT               (20U)
/*! INT_EN20 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN20(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN20_SHIFT)) & GPIO_INTENB_INT_EN20_MASK)

#define GPIO_INTENB_INT_EN21_MASK                (0x200000U)
#define GPIO_INTENB_INT_EN21_SHIFT               (21U)
/*! INT_EN21 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN21(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN21_SHIFT)) & GPIO_INTENB_INT_EN21_MASK)

#define GPIO_INTENB_INT_EN22_MASK                (0x400000U)
#define GPIO_INTENB_INT_EN22_SHIFT               (22U)
/*! INT_EN22 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN22(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN22_SHIFT)) & GPIO_INTENB_INT_EN22_MASK)

#define GPIO_INTENB_INT_EN23_MASK                (0x800000U)
#define GPIO_INTENB_INT_EN23_SHIFT               (23U)
/*! INT_EN23 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN23(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN23_SHIFT)) & GPIO_INTENB_INT_EN23_MASK)

#define GPIO_INTENB_INT_EN24_MASK                (0x1000000U)
#define GPIO_INTENB_INT_EN24_SHIFT               (24U)
/*! INT_EN24 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN24(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN24_SHIFT)) & GPIO_INTENB_INT_EN24_MASK)

#define GPIO_INTENB_INT_EN25_MASK                (0x2000000U)
#define GPIO_INTENB_INT_EN25_SHIFT               (25U)
/*! INT_EN25 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN25(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN25_SHIFT)) & GPIO_INTENB_INT_EN25_MASK)

#define GPIO_INTENB_INT_EN26_MASK                (0x4000000U)
#define GPIO_INTENB_INT_EN26_SHIFT               (26U)
/*! INT_EN26 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN26(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN26_SHIFT)) & GPIO_INTENB_INT_EN26_MASK)

#define GPIO_INTENB_INT_EN27_MASK                (0x8000000U)
#define GPIO_INTENB_INT_EN27_SHIFT               (27U)
/*! INT_EN27 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN27(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN27_SHIFT)) & GPIO_INTENB_INT_EN27_MASK)

#define GPIO_INTENB_INT_EN28_MASK                (0x10000000U)
#define GPIO_INTENB_INT_EN28_SHIFT               (28U)
/*! INT_EN28 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN28(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN28_SHIFT)) & GPIO_INTENB_INT_EN28_MASK)

#define GPIO_INTENB_INT_EN29_MASK                (0x20000000U)
#define GPIO_INTENB_INT_EN29_SHIFT               (29U)
/*! INT_EN29 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN29(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN29_SHIFT)) & GPIO_INTENB_INT_EN29_MASK)

#define GPIO_INTENB_INT_EN30_MASK                (0x40000000U)
#define GPIO_INTENB_INT_EN30_SHIFT               (30U)
/*! INT_EN30 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN30(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN30_SHIFT)) & GPIO_INTENB_INT_EN30_MASK)

#define GPIO_INTENB_INT_EN31_MASK                (0x80000000U)
#define GPIO_INTENB_INT_EN31_SHIFT               (31U)
/*! INT_EN31 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN31(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN31_SHIFT)) & GPIO_INTENB_INT_EN31_MASK)
/*! @} */

/* The count of GPIO_INTENB */
#define GPIO_INTENB_COUNT                        (4U)

/*! @name INTPOL - Interupt polarity control */
/*! @{ */

#define GPIO_INTPOL_POL_CTL0_MASK                (0x1U)
#define GPIO_INTPOL_POL_CTL0_SHIFT               (0U)
/*! POL_CTL0 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL0(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL0_SHIFT)) & GPIO_INTPOL_POL_CTL0_MASK)

#define GPIO_INTPOL_POL_CTL1_MASK                (0x2U)
#define GPIO_INTPOL_POL_CTL1_SHIFT               (1U)
/*! POL_CTL1 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL1(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL1_SHIFT)) & GPIO_INTPOL_POL_CTL1_MASK)

#define GPIO_INTPOL_POL_CTL2_MASK                (0x4U)
#define GPIO_INTPOL_POL_CTL2_SHIFT               (2U)
/*! POL_CTL2 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL2(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL2_SHIFT)) & GPIO_INTPOL_POL_CTL2_MASK)

#define GPIO_INTPOL_POL_CTL3_MASK                (0x8U)
#define GPIO_INTPOL_POL_CTL3_SHIFT               (3U)
/*! POL_CTL3 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL3(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL3_SHIFT)) & GPIO_INTPOL_POL_CTL3_MASK)

#define GPIO_INTPOL_POL_CTL4_MASK                (0x10U)
#define GPIO_INTPOL_POL_CTL4_SHIFT               (4U)
/*! POL_CTL4 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL4(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL4_SHIFT)) & GPIO_INTPOL_POL_CTL4_MASK)

#define GPIO_INTPOL_POL_CTL5_MASK                (0x20U)
#define GPIO_INTPOL_POL_CTL5_SHIFT               (5U)
/*! POL_CTL5 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL5(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL5_SHIFT)) & GPIO_INTPOL_POL_CTL5_MASK)

#define GPIO_INTPOL_POL_CTL6_MASK                (0x40U)
#define GPIO_INTPOL_POL_CTL6_SHIFT               (6U)
/*! POL_CTL6 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL6(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL6_SHIFT)) & GPIO_INTPOL_POL_CTL6_MASK)

#define GPIO_INTPOL_POL_CTL7_MASK                (0x80U)
#define GPIO_INTPOL_POL_CTL7_SHIFT               (7U)
/*! POL_CTL7 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL7(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL7_SHIFT)) & GPIO_INTPOL_POL_CTL7_MASK)

#define GPIO_INTPOL_POL_CTL8_MASK                (0x100U)
#define GPIO_INTPOL_POL_CTL8_SHIFT               (8U)
/*! POL_CTL8 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL8(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL8_SHIFT)) & GPIO_INTPOL_POL_CTL8_MASK)

#define GPIO_INTPOL_POL_CTL9_MASK                (0x200U)
#define GPIO_INTPOL_POL_CTL9_SHIFT               (9U)
/*! POL_CTL9 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL9(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL9_SHIFT)) & GPIO_INTPOL_POL_CTL9_MASK)

#define GPIO_INTPOL_POL_CTL10_MASK               (0x400U)
#define GPIO_INTPOL_POL_CTL10_SHIFT              (10U)
/*! POL_CTL10 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL10(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL10_SHIFT)) & GPIO_INTPOL_POL_CTL10_MASK)

#define GPIO_INTPOL_POL_CTL11_MASK               (0x800U)
#define GPIO_INTPOL_POL_CTL11_SHIFT              (11U)
/*! POL_CTL11 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL11(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL11_SHIFT)) & GPIO_INTPOL_POL_CTL11_MASK)

#define GPIO_INTPOL_POL_CTL12_MASK               (0x1000U)
#define GPIO_INTPOL_POL_CTL12_SHIFT              (12U)
/*! POL_CTL12 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL12(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL12_SHIFT)) & GPIO_INTPOL_POL_CTL12_MASK)

#define GPIO_INTPOL_POL_CTL13_MASK               (0x2000U)
#define GPIO_INTPOL_POL_CTL13_SHIFT              (13U)
/*! POL_CTL13 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL13(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL13_SHIFT)) & GPIO_INTPOL_POL_CTL13_MASK)

#define GPIO_INTPOL_POL_CTL14_MASK               (0x4000U)
#define GPIO_INTPOL_POL_CTL14_SHIFT              (14U)
/*! POL_CTL14 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL14(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL14_SHIFT)) & GPIO_INTPOL_POL_CTL14_MASK)

#define GPIO_INTPOL_POL_CTL15_MASK               (0x8000U)
#define GPIO_INTPOL_POL_CTL15_SHIFT              (15U)
/*! POL_CTL15 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL15(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL15_SHIFT)) & GPIO_INTPOL_POL_CTL15_MASK)

#define GPIO_INTPOL_POL_CTL16_MASK               (0x10000U)
#define GPIO_INTPOL_POL_CTL16_SHIFT              (16U)
/*! POL_CTL16 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL16(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL16_SHIFT)) & GPIO_INTPOL_POL_CTL16_MASK)

#define GPIO_INTPOL_POL_CTL17_MASK               (0x20000U)
#define GPIO_INTPOL_POL_CTL17_SHIFT              (17U)
/*! POL_CTL17 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL17(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL17_SHIFT)) & GPIO_INTPOL_POL_CTL17_MASK)

#define GPIO_INTPOL_POL_CTL18_MASK               (0x40000U)
#define GPIO_INTPOL_POL_CTL18_SHIFT              (18U)
/*! POL_CTL18 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL18(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL18_SHIFT)) & GPIO_INTPOL_POL_CTL18_MASK)

#define GPIO_INTPOL_POL_CTL19_MASK               (0x80000U)
#define GPIO_INTPOL_POL_CTL19_SHIFT              (19U)
/*! POL_CTL19 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL19(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL19_SHIFT)) & GPIO_INTPOL_POL_CTL19_MASK)

#define GPIO_INTPOL_POL_CTL20_MASK               (0x100000U)
#define GPIO_INTPOL_POL_CTL20_SHIFT              (20U)
/*! POL_CTL20 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL20(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL20_SHIFT)) & GPIO_INTPOL_POL_CTL20_MASK)

#define GPIO_INTPOL_POL_CTL21_MASK               (0x200000U)
#define GPIO_INTPOL_POL_CTL21_SHIFT              (21U)
/*! POL_CTL21 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL21(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL21_SHIFT)) & GPIO_INTPOL_POL_CTL21_MASK)

#define GPIO_INTPOL_POL_CTL22_MASK               (0x400000U)
#define GPIO_INTPOL_POL_CTL22_SHIFT              (22U)
/*! POL_CTL22 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL22(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL22_SHIFT)) & GPIO_INTPOL_POL_CTL22_MASK)

#define GPIO_INTPOL_POL_CTL23_MASK               (0x800000U)
#define GPIO_INTPOL_POL_CTL23_SHIFT              (23U)
/*! POL_CTL23 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL23(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL23_SHIFT)) & GPIO_INTPOL_POL_CTL23_MASK)

#define GPIO_INTPOL_POL_CTL24_MASK               (0x1000000U)
#define GPIO_INTPOL_POL_CTL24_SHIFT              (24U)
/*! POL_CTL24 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL24(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL24_SHIFT)) & GPIO_INTPOL_POL_CTL24_MASK)

#define GPIO_INTPOL_POL_CTL25_MASK               (0x2000000U)
#define GPIO_INTPOL_POL_CTL25_SHIFT              (25U)
/*! POL_CTL25 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL25(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL25_SHIFT)) & GPIO_INTPOL_POL_CTL25_MASK)

#define GPIO_INTPOL_POL_CTL26_MASK               (0x4000000U)
#define GPIO_INTPOL_POL_CTL26_SHIFT              (26U)
/*! POL_CTL26 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL26(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL26_SHIFT)) & GPIO_INTPOL_POL_CTL26_MASK)

#define GPIO_INTPOL_POL_CTL27_MASK               (0x8000000U)
#define GPIO_INTPOL_POL_CTL27_SHIFT              (27U)
/*! POL_CTL27 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL27(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL27_SHIFT)) & GPIO_INTPOL_POL_CTL27_MASK)

#define GPIO_INTPOL_POL_CTL28_MASK               (0x10000000U)
#define GPIO_INTPOL_POL_CTL28_SHIFT              (28U)
/*! POL_CTL28 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL28(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL28_SHIFT)) & GPIO_INTPOL_POL_CTL28_MASK)

#define GPIO_INTPOL_POL_CTL29_MASK               (0x20000000U)
#define GPIO_INTPOL_POL_CTL29_SHIFT              (29U)
/*! POL_CTL29 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL29(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL29_SHIFT)) & GPIO_INTPOL_POL_CTL29_MASK)

#define GPIO_INTPOL_POL_CTL30_MASK               (0x40000000U)
#define GPIO_INTPOL_POL_CTL30_SHIFT              (30U)
/*! POL_CTL30 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL30(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL30_SHIFT)) & GPIO_INTPOL_POL_CTL30_MASK)

#define GPIO_INTPOL_POL_CTL31_MASK               (0x80000000U)
#define GPIO_INTPOL_POL_CTL31_SHIFT              (31U)
/*! POL_CTL31 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL31(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL31_SHIFT)) & GPIO_INTPOL_POL_CTL31_MASK)
/*! @} */

/* The count of GPIO_INTPOL */
#define GPIO_INTPOL_COUNT                        (4U)

/*! @name INTEDG - Interrupt edge select */
/*! @{ */

#define GPIO_INTEDG_EDGE0_MASK                   (0x1U)
#define GPIO_INTEDG_EDGE0_SHIFT                  (0U)
/*! EDGE0 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE0(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE0_SHIFT)) & GPIO_INTEDG_EDGE0_MASK)

#define GPIO_INTEDG_EDGE1_MASK                   (0x2U)
#define GPIO_INTEDG_EDGE1_SHIFT                  (1U)
/*! EDGE1 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE1(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE1_SHIFT)) & GPIO_INTEDG_EDGE1_MASK)

#define GPIO_INTEDG_EDGE2_MASK                   (0x4U)
#define GPIO_INTEDG_EDGE2_SHIFT                  (2U)
/*! EDGE2 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE2(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE2_SHIFT)) & GPIO_INTEDG_EDGE2_MASK)

#define GPIO_INTEDG_EDGE3_MASK                   (0x8U)
#define GPIO_INTEDG_EDGE3_SHIFT                  (3U)
/*! EDGE3 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE3(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE3_SHIFT)) & GPIO_INTEDG_EDGE3_MASK)

#define GPIO_INTEDG_EDGE4_MASK                   (0x10U)
#define GPIO_INTEDG_EDGE4_SHIFT                  (4U)
/*! EDGE4 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE4(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE4_SHIFT)) & GPIO_INTEDG_EDGE4_MASK)

#define GPIO_INTEDG_EDGE5_MASK                   (0x20U)
#define GPIO_INTEDG_EDGE5_SHIFT                  (5U)
/*! EDGE5 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE5(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE5_SHIFT)) & GPIO_INTEDG_EDGE5_MASK)

#define GPIO_INTEDG_EDGE6_MASK                   (0x40U)
#define GPIO_INTEDG_EDGE6_SHIFT                  (6U)
/*! EDGE6 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE6(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE6_SHIFT)) & GPIO_INTEDG_EDGE6_MASK)

#define GPIO_INTEDG_EDGE7_MASK                   (0x80U)
#define GPIO_INTEDG_EDGE7_SHIFT                  (7U)
/*! EDGE7 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE7(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE7_SHIFT)) & GPIO_INTEDG_EDGE7_MASK)

#define GPIO_INTEDG_EDGE8_MASK                   (0x100U)
#define GPIO_INTEDG_EDGE8_SHIFT                  (8U)
/*! EDGE8 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE8(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE8_SHIFT)) & GPIO_INTEDG_EDGE8_MASK)

#define GPIO_INTEDG_EDGE9_MASK                   (0x200U)
#define GPIO_INTEDG_EDGE9_SHIFT                  (9U)
/*! EDGE9 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE9(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE9_SHIFT)) & GPIO_INTEDG_EDGE9_MASK)

#define GPIO_INTEDG_EDGE10_MASK                  (0x400U)
#define GPIO_INTEDG_EDGE10_SHIFT                 (10U)
/*! EDGE10 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE10(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE10_SHIFT)) & GPIO_INTEDG_EDGE10_MASK)

#define GPIO_INTEDG_EDGE11_MASK                  (0x800U)
#define GPIO_INTEDG_EDGE11_SHIFT                 (11U)
/*! EDGE11 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE11(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE11_SHIFT)) & GPIO_INTEDG_EDGE11_MASK)

#define GPIO_INTEDG_EDGE12_MASK                  (0x1000U)
#define GPIO_INTEDG_EDGE12_SHIFT                 (12U)
/*! EDGE12 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE12(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE12_SHIFT)) & GPIO_INTEDG_EDGE12_MASK)

#define GPIO_INTEDG_EDGE13_MASK                  (0x2000U)
#define GPIO_INTEDG_EDGE13_SHIFT                 (13U)
/*! EDGE13 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE13(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE13_SHIFT)) & GPIO_INTEDG_EDGE13_MASK)

#define GPIO_INTEDG_EDGE14_MASK                  (0x4000U)
#define GPIO_INTEDG_EDGE14_SHIFT                 (14U)
/*! EDGE14 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE14(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE14_SHIFT)) & GPIO_INTEDG_EDGE14_MASK)

#define GPIO_INTEDG_EDGE15_MASK                  (0x8000U)
#define GPIO_INTEDG_EDGE15_SHIFT                 (15U)
/*! EDGE15 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE15(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE15_SHIFT)) & GPIO_INTEDG_EDGE15_MASK)

#define GPIO_INTEDG_EDGE16_MASK                  (0x10000U)
#define GPIO_INTEDG_EDGE16_SHIFT                 (16U)
/*! EDGE16 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE16(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE16_SHIFT)) & GPIO_INTEDG_EDGE16_MASK)

#define GPIO_INTEDG_EDGE17_MASK                  (0x20000U)
#define GPIO_INTEDG_EDGE17_SHIFT                 (17U)
/*! EDGE17 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE17(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE17_SHIFT)) & GPIO_INTEDG_EDGE17_MASK)

#define GPIO_INTEDG_EDGE18_MASK                  (0x40000U)
#define GPIO_INTEDG_EDGE18_SHIFT                 (18U)
/*! EDGE18 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE18(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE18_SHIFT)) & GPIO_INTEDG_EDGE18_MASK)

#define GPIO_INTEDG_EDGE19_MASK                  (0x80000U)
#define GPIO_INTEDG_EDGE19_SHIFT                 (19U)
/*! EDGE19 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE19(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE19_SHIFT)) & GPIO_INTEDG_EDGE19_MASK)

#define GPIO_INTEDG_EDGE20_MASK                  (0x100000U)
#define GPIO_INTEDG_EDGE20_SHIFT                 (20U)
/*! EDGE20 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE20(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE20_SHIFT)) & GPIO_INTEDG_EDGE20_MASK)

#define GPIO_INTEDG_EDGE21_MASK                  (0x200000U)
#define GPIO_INTEDG_EDGE21_SHIFT                 (21U)
/*! EDGE21 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE21(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE21_SHIFT)) & GPIO_INTEDG_EDGE21_MASK)

#define GPIO_INTEDG_EDGE22_MASK                  (0x400000U)
#define GPIO_INTEDG_EDGE22_SHIFT                 (22U)
/*! EDGE22 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE22(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE22_SHIFT)) & GPIO_INTEDG_EDGE22_MASK)

#define GPIO_INTEDG_EDGE23_MASK                  (0x800000U)
#define GPIO_INTEDG_EDGE23_SHIFT                 (23U)
/*! EDGE23 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE23(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE23_SHIFT)) & GPIO_INTEDG_EDGE23_MASK)

#define GPIO_INTEDG_EDGE24_MASK                  (0x1000000U)
#define GPIO_INTEDG_EDGE24_SHIFT                 (24U)
/*! EDGE24 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE24(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE24_SHIFT)) & GPIO_INTEDG_EDGE24_MASK)

#define GPIO_INTEDG_EDGE25_MASK                  (0x2000000U)
#define GPIO_INTEDG_EDGE25_SHIFT                 (25U)
/*! EDGE25 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE25(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE25_SHIFT)) & GPIO_INTEDG_EDGE25_MASK)

#define GPIO_INTEDG_EDGE26_MASK                  (0x4000000U)
#define GPIO_INTEDG_EDGE26_SHIFT                 (26U)
/*! EDGE26 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE26(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE26_SHIFT)) & GPIO_INTEDG_EDGE26_MASK)

#define GPIO_INTEDG_EDGE27_MASK                  (0x8000000U)
#define GPIO_INTEDG_EDGE27_SHIFT                 (27U)
/*! EDGE27 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE27(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE27_SHIFT)) & GPIO_INTEDG_EDGE27_MASK)

#define GPIO_INTEDG_EDGE28_MASK                  (0x10000000U)
#define GPIO_INTEDG_EDGE28_SHIFT                 (28U)
/*! EDGE28 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE28(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE28_SHIFT)) & GPIO_INTEDG_EDGE28_MASK)

#define GPIO_INTEDG_EDGE29_MASK                  (0x20000000U)
#define GPIO_INTEDG_EDGE29_SHIFT                 (29U)
/*! EDGE29 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE29(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE29_SHIFT)) & GPIO_INTEDG_EDGE29_MASK)

#define GPIO_INTEDG_EDGE30_MASK                  (0x40000000U)
#define GPIO_INTEDG_EDGE30_SHIFT                 (30U)
/*! EDGE30 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE30(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE30_SHIFT)) & GPIO_INTEDG_EDGE30_MASK)

#define GPIO_INTEDG_EDGE31_MASK                  (0x80000000U)
#define GPIO_INTEDG_EDGE31_SHIFT                 (31U)
/*! EDGE31 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE31(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE31_SHIFT)) & GPIO_INTEDG_EDGE31_MASK)
/*! @} */

/* The count of GPIO_INTEDG */
#define GPIO_INTEDG_COUNT                        (4U)

/*! @name INTSTATA - Interrupt status for interrupt A */
/*! @{ */

#define GPIO_INTSTATA_STATUS_MASK                (0xFFFFFFFFU)
#define GPIO_INTSTATA_STATUS_SHIFT               (0U)
/*! STATUS - Interrupt status.
 */
#define GPIO_INTSTATA_STATUS(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTSTATA_STATUS_SHIFT)) & GPIO_INTSTATA_STATUS_MASK)
/*! @} */

/* The count of GPIO_INTSTATA */
#define GPIO_INTSTATA_COUNT                      (4U)

/*! @name INTSTATB - Interrupt status for interrupt B */
/*! @{ */

#define GPIO_INTSTATB_STATUS_MASK                (0xFFFFFFFFU)
#define GPIO_INTSTATB_STATUS_SHIFT               (0U)
/*! STATUS - Interrupt status
 */
#define GPIO_INTSTATB_STATUS(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTSTATB_STATUS_SHIFT)) & GPIO_INTSTATB_STATUS_MASK)
/*! @} */

/* The count of GPIO_INTSTATB */
#define GPIO_INTSTATB_COUNT                      (4U)


/*!
 * @}
 */ /* end of group GPIO_Register_Masks */


/* GPIO - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral GPIO base address */
  #define GPIO_BASE                                (0x5008C000u)
  /** Peripheral GPIO base address */
  #define GPIO_BASE_NS                             (0x4008C000u)
  /** Peripheral GPIO base pointer */
  #define GPIO                                     ((GPIO_Type *)GPIO_BASE)
  /** Peripheral GPIO base pointer */
  #define GPIO_NS                                  ((GPIO_Type *)GPIO_BASE_NS)
  /** Peripheral SECGPIO base address */
  #define SECGPIO_BASE                             (0x500A8000u)
  /** Peripheral SECGPIO base address */
  #define SECGPIO_BASE_NS                          (0x400A8000u)
  /** Peripheral SECGPIO base pointer */
  #define SECGPIO                                  ((GPIO_Type *)SECGPIO_BASE)
  /** Peripheral SECGPIO base pointer */
  #define SECGPIO_NS                               ((GPIO_Type *)SECGPIO_BASE_NS)
  /** Array initializer of GPIO peripheral base addresses */
  #define GPIO_BASE_ADDRS                          { GPIO_BASE, SECGPIO_BASE }
  /** Array initializer of GPIO peripheral base pointers */
  #define GPIO_BASE_PTRS                           { GPIO, SECGPIO }
  /** Array initializer of GPIO peripheral base addresses */
  #define GPIO_BASE_ADDRS_NS                       { GPIO_BASE_NS, SECGPIO_BASE_NS }
  /** Array initializer of GPIO peripheral base pointers */
  #define GPIO_BASE_PTRS_NS                        { GPIO_NS, SECGPIO_NS }
#else
  /** Peripheral GPIO base address */
  #define GPIO_BASE                                (0x4008C000u)
  /** Peripheral GPIO base pointer */
  #define GPIO                                     ((GPIO_Type *)GPIO_BASE)
  /** Peripheral SECGPIO base address */
  #define SECGPIO_BASE                             (0x400A8000u)
  /** Peripheral SECGPIO base pointer */
  #define SECGPIO                                  ((GPIO_Type *)SECGPIO_BASE)
  /** Array initializer of GPIO peripheral base addresses */
  #define GPIO_BASE_ADDRS                          { GPIO_BASE, SECGPIO_BASE }
  /** Array initializer of GPIO peripheral base pointers */
  #define GPIO_BASE_PTRS                           { GPIO, SECGPIO }
#endif

/*!
 * @}
 */ /* end of group GPIO_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- HSCMP Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup HSCMP_Peripheral_Access_Layer HSCMP Peripheral Access Layer
 * @{
 */

/** HSCMP - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
  __IO uint32_t CCR0;                              /**< Comparator Control Register 0, offset: 0x8 */
  __IO uint32_t CCR1;                              /**< Comparator Control Register 1, offset: 0xC */
  __IO uint32_t CCR2;                              /**< Comparator Control Register 2, offset: 0x10 */
       uint8_t RESERVED_0[4];
  __IO uint32_t DCR;                               /**< DAC Control Register, offset: 0x18 */
  __IO uint32_t IER;                               /**< Interrupt Enable Register, offset: 0x1C */
  __IO uint32_t CSR;                               /**< Comparator Status Register, offset: 0x20 */
  __IO uint32_t RRCR0;                             /**< Round Robin Control Register 0, offset: 0x24 */
  __IO uint32_t RRCR1;                             /**< Round Robin Control Register 1, offset: 0x28 */
  __IO uint32_t RRCSR;                             /**< Round Robin Control and Status Register, offset: 0x2C */
  __IO uint32_t RRSR;                              /**< Round Robin Status Register, offset: 0x30 */
       uint8_t RESERVED_1[4];
  __IO uint32_t RRCR2;                             /**< Round Robin Control Register 2, offset: 0x38 */
} HSCMP_Type;

/* ----------------------------------------------------------------------------
   -- HSCMP Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup HSCMP_Register_Masks HSCMP Register Masks
 * @{
 */

/*! @name VERID - Version ID Register */
/*! @{ */

#define HSCMP_VERID_FEATURE_MASK                 (0xFFFFU)
#define HSCMP_VERID_FEATURE_SHIFT                (0U)
/*! FEATURE - Feature Specification Number
 *  0b0000000000000001..Round robin feature
 */
#define HSCMP_VERID_FEATURE(x)                   (((uint32_t)(((uint32_t)(x)) << HSCMP_VERID_FEATURE_SHIFT)) & HSCMP_VERID_FEATURE_MASK)

#define HSCMP_VERID_MINOR_MASK                   (0xFF0000U)
#define HSCMP_VERID_MINOR_SHIFT                  (16U)
/*! MINOR - Minor Version Number
 */
#define HSCMP_VERID_MINOR(x)                     (((uint32_t)(((uint32_t)(x)) << HSCMP_VERID_MINOR_SHIFT)) & HSCMP_VERID_MINOR_MASK)

#define HSCMP_VERID_MAJOR_MASK                   (0xFF000000U)
#define HSCMP_VERID_MAJOR_SHIFT                  (24U)
/*! MAJOR - Major Version Number
 */
#define HSCMP_VERID_MAJOR(x)                     (((uint32_t)(((uint32_t)(x)) << HSCMP_VERID_MAJOR_SHIFT)) & HSCMP_VERID_MAJOR_MASK)
/*! @} */

/*! @name PARAM - Parameter Register */
/*! @{ */

#define HSCMP_PARAM_DAC_RES_MASK                 (0xFU)
#define HSCMP_PARAM_DAC_RES_SHIFT                (0U)
/*! DAC_RES - DAC Resolution
 *  0b0000..4 bit DAC
 *  0b0001..6 bit DAC
 *  0b0010..8 bit DAC
 *  0b0011..10 bit DAC
 *  0b0100..12 bit DAC
 *  0b0101..14 bit DAC
 *  0b0110..16 bit DAC
 */
#define HSCMP_PARAM_DAC_RES(x)                   (((uint32_t)(((uint32_t)(x)) << HSCMP_PARAM_DAC_RES_SHIFT)) & HSCMP_PARAM_DAC_RES_MASK)
/*! @} */

/*! @name CCR0 - Comparator Control Register 0 */
/*! @{ */

#define HSCMP_CCR0_CMP_EN_MASK                   (0x1U)
#define HSCMP_CCR0_CMP_EN_SHIFT                  (0U)
/*! CMP_EN - Comparator Enable
 *  0b0..Disable (The analog logic remains off and consumes no power.)
 *  0b1..Enable
 */
#define HSCMP_CCR0_CMP_EN(x)                     (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR0_CMP_EN_SHIFT)) & HSCMP_CCR0_CMP_EN_MASK)

#define HSCMP_CCR0_CMP_STOP_EN_MASK              (0x2U)
#define HSCMP_CCR0_CMP_STOP_EN_SHIFT             (1U)
/*! CMP_STOP_EN - Comparator STOP Mode Enable
 *  0b0..Disable the analog comparator regardless of CMP_EN.
 *  0b1..Allow the analog comparator to be enabled by CMP_EN.
 */
#define HSCMP_CCR0_CMP_STOP_EN(x)                (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR0_CMP_STOP_EN_SHIFT)) & HSCMP_CCR0_CMP_STOP_EN_MASK)

#define HSCMP_CCR0_LINKEN_MASK                   (0x4U)
#define HSCMP_CCR0_LINKEN_SHIFT                  (2U)
/*! LINKEN - CMP-to-DAC Link Enable
 *  0b0..Disable the CMP-to-DAC link: enabling or disabling the DAC is independent from enabling or disabling the CMP.
 *  0b1..Enable the CMP-to-DAC link: the DAC enable/disable is controlled by the CMP_EN bit instead of DCR[DAC_EN].
 */
#define HSCMP_CCR0_LINKEN(x)                     (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR0_LINKEN_SHIFT)) & HSCMP_CCR0_LINKEN_MASK)
/*! @} */

/*! @name CCR1 - Comparator Control Register 1 */
/*! @{ */

#define HSCMP_CCR1_WINDOW_EN_MASK                (0x1U)
#define HSCMP_CCR1_WINDOW_EN_SHIFT               (0U)
/*! WINDOW_EN - Windowing Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define HSCMP_CCR1_WINDOW_EN(x)                  (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR1_WINDOW_EN_SHIFT)) & HSCMP_CCR1_WINDOW_EN_MASK)

#define HSCMP_CCR1_SAMPLE_EN_MASK                (0x2U)
#define HSCMP_CCR1_SAMPLE_EN_SHIFT               (1U)
/*! SAMPLE_EN - Sampling Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define HSCMP_CCR1_SAMPLE_EN(x)                  (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR1_SAMPLE_EN_SHIFT)) & HSCMP_CCR1_SAMPLE_EN_MASK)

#define HSCMP_CCR1_DMA_EN_MASK                   (0x4U)
#define HSCMP_CCR1_DMA_EN_SHIFT                  (2U)
/*! DMA_EN - DMA Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define HSCMP_CCR1_DMA_EN(x)                     (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR1_DMA_EN_SHIFT)) & HSCMP_CCR1_DMA_EN_MASK)

#define HSCMP_CCR1_COUT_INV_MASK                 (0x8U)
#define HSCMP_CCR1_COUT_INV_SHIFT                (3U)
/*! COUT_INV - Comparator Invert
 *  0b0..Do not invert
 *  0b1..Invert
 */
#define HSCMP_CCR1_COUT_INV(x)                   (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR1_COUT_INV_SHIFT)) & HSCMP_CCR1_COUT_INV_MASK)

#define HSCMP_CCR1_COUT_SEL_MASK                 (0x10U)
#define HSCMP_CCR1_COUT_SEL_SHIFT                (4U)
/*! COUT_SEL - Comparator Output Select
 *  0b0..Use COUT (filtered)
 *  0b1..Use COUTA (unfiltered)
 */
#define HSCMP_CCR1_COUT_SEL(x)                   (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR1_COUT_SEL_SHIFT)) & HSCMP_CCR1_COUT_SEL_MASK)

#define HSCMP_CCR1_COUT_PEN_MASK                 (0x20U)
#define HSCMP_CCR1_COUT_PEN_SHIFT                (5U)
/*! COUT_PEN - Comparator Output Pin Enable
 *  0b0..Not available
 *  0b1..Available
 */
#define HSCMP_CCR1_COUT_PEN(x)                   (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR1_COUT_PEN_SHIFT)) & HSCMP_CCR1_COUT_PEN_MASK)

#define HSCMP_CCR1_COUTA_OWEN_MASK               (0x40U)
#define HSCMP_CCR1_COUTA_OWEN_SHIFT              (6U)
/*! COUTA_OWEN - COUTA_OW Enable
 *  0b0..COUTA holds the last sampled value
 *  0b1..COUTA is defined by the COUTA_OW bit
 */
#define HSCMP_CCR1_COUTA_OWEN(x)                 (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR1_COUTA_OWEN_SHIFT)) & HSCMP_CCR1_COUTA_OWEN_MASK)

#define HSCMP_CCR1_COUTA_OW_MASK                 (0x80U)
#define HSCMP_CCR1_COUTA_OW_SHIFT                (7U)
/*! COUTA_OW - COUTA Output Level for Closed Window
 *  0b0..COUTA is 0
 *  0b1..COUTA is 1
 */
#define HSCMP_CCR1_COUTA_OW(x)                   (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR1_COUTA_OW_SHIFT)) & HSCMP_CCR1_COUTA_OW_MASK)

#define HSCMP_CCR1_WINDOW_INV_MASK               (0x100U)
#define HSCMP_CCR1_WINDOW_INV_SHIFT              (8U)
/*! WINDOW_INV - WINDOW/SAMPLE Signal Invert
 *  0b0..Do not invert
 *  0b1..Invert
 */
#define HSCMP_CCR1_WINDOW_INV(x)                 (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR1_WINDOW_INV_SHIFT)) & HSCMP_CCR1_WINDOW_INV_MASK)

#define HSCMP_CCR1_WINDOW_CLS_MASK               (0x200U)
#define HSCMP_CCR1_WINDOW_CLS_SHIFT              (9U)
/*! WINDOW_CLS - COUT Event Window Close
 *  0b0..COUT event cannot close the window
 *  0b1..COUT event can close the window
 */
#define HSCMP_CCR1_WINDOW_CLS(x)                 (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR1_WINDOW_CLS_SHIFT)) & HSCMP_CCR1_WINDOW_CLS_MASK)

#define HSCMP_CCR1_EVT_SEL_MASK                  (0xC00U)
#define HSCMP_CCR1_EVT_SEL_SHIFT                 (10U)
/*! EVT_SEL - COUT Event Select
 *  0b00..Rising edge
 *  0b01..Falling edge
 *  0b1x..Both edges
 */
#define HSCMP_CCR1_EVT_SEL(x)                    (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR1_EVT_SEL_SHIFT)) & HSCMP_CCR1_EVT_SEL_MASK)

#define HSCMP_CCR1_FILT_CNT_MASK                 (0x70000U)
#define HSCMP_CCR1_FILT_CNT_SHIFT                (16U)
/*! FILT_CNT - Filter Sample Count
 *  0b000..Filter is bypassed: COUT = COUTA
 *  0b001..1 consecutive sample (Comparator output is simply sampled.)
 *  0b010..2 consecutive samples
 *  0b011..3 consecutive samples
 *  0b100..4 consecutive samples
 *  0b101..5 consecutive samples
 *  0b110..6 consecutive samples
 *  0b111..7 consecutive samples
 */
#define HSCMP_CCR1_FILT_CNT(x)                   (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR1_FILT_CNT_SHIFT)) & HSCMP_CCR1_FILT_CNT_MASK)

#define HSCMP_CCR1_FILT_PER_MASK                 (0xFF000000U)
#define HSCMP_CCR1_FILT_PER_SHIFT                (24U)
/*! FILT_PER - Filter Sample Period
 */
#define HSCMP_CCR1_FILT_PER(x)                   (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR1_FILT_PER_SHIFT)) & HSCMP_CCR1_FILT_PER_MASK)
/*! @} */

/*! @name CCR2 - Comparator Control Register 2 */
/*! @{ */

#define HSCMP_CCR2_CMP_HPMD_MASK                 (0x1U)
#define HSCMP_CCR2_CMP_HPMD_SHIFT                (0U)
/*! CMP_HPMD - CMP High Power Mode Select
 *  0b0..Low power(speed) comparison mode
 *  0b1..High power(speed) comparison mode
 */
#define HSCMP_CCR2_CMP_HPMD(x)                   (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR2_CMP_HPMD_SHIFT)) & HSCMP_CCR2_CMP_HPMD_MASK)

#define HSCMP_CCR2_CMP_NPMD_MASK                 (0x2U)
#define HSCMP_CCR2_CMP_NPMD_SHIFT                (1U)
/*! CMP_NPMD - CMP Nano Power Mode Select
 *  0b0..Disable (Mode is determined by CMP_HPMD.)
 *  0b1..Enable
 */
#define HSCMP_CCR2_CMP_NPMD(x)                   (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR2_CMP_NPMD_SHIFT)) & HSCMP_CCR2_CMP_NPMD_MASK)

#define HSCMP_CCR2_OFFSET_MASK                   (0x4U)
#define HSCMP_CCR2_OFFSET_SHIFT                  (2U)
/*! OFFSET - Comparator Offset Control
 *  0b0..Level 0: The hysteresis selected by HYSTCTR is valid for both directions (rising and falling).
 *  0b1..Level 1: Hysteresis does not apply when INP (input-plus) crosses INM (input-minus) in the rising
 *       direction or when INM crosses INP in the falling direction. Hysteresis still applies for INP crossing INM in the
 *       falling direction.
 */
#define HSCMP_CCR2_OFFSET(x)                     (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR2_OFFSET_SHIFT)) & HSCMP_CCR2_OFFSET_MASK)

#define HSCMP_CCR2_HYSTCTR_MASK                  (0x30U)
#define HSCMP_CCR2_HYSTCTR_SHIFT                 (4U)
/*! HYSTCTR - Comparator Hysteresis Control
 *  0b00..Level 0
 *  0b01..Level 1
 *  0b10..Level 2
 *  0b11..Level 3
 */
#define HSCMP_CCR2_HYSTCTR(x)                    (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR2_HYSTCTR_SHIFT)) & HSCMP_CCR2_HYSTCTR_MASK)

#define HSCMP_CCR2_PSEL_MASK                     (0x70000U)
#define HSCMP_CCR2_PSEL_SHIFT                    (16U)
/*! PSEL - Plus Input MUX Select
 *  0b000..Input 0p
 *  0b001..Input 1p
 *  0b010..Input 2p
 *  0b011..Input 3p
 *  0b100..Input 4p
 *  0b101..Input 5p
 *  0b110..Reserved
 *  0b111..Internal DAC output
 */
#define HSCMP_CCR2_PSEL(x)                       (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR2_PSEL_SHIFT)) & HSCMP_CCR2_PSEL_MASK)

#define HSCMP_CCR2_MSEL_MASK                     (0x700000U)
#define HSCMP_CCR2_MSEL_SHIFT                    (20U)
/*! MSEL - Minus Input MUX Select
 *  0b000..Input 0m
 *  0b001..Input 1m
 *  0b010..Input 2m
 *  0b011..Input 3m
 *  0b100..Input 4m
 *  0b101..Input 5m
 *  0b110..Reserved
 *  0b111..Internal DAC output
 */
#define HSCMP_CCR2_MSEL(x)                       (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR2_MSEL_SHIFT)) & HSCMP_CCR2_MSEL_MASK)

#define HSCMP_CCR2_INPSEL_MASK                   (0x3000000U)
#define HSCMP_CCR2_INPSEL_SHIFT                  (24U)
/*! INPSEL - Input Plus Select
 *  0b00..IN0: from the 8-bit DAC output
 *  0b01..IN1: from the analog 8-1 mux
 *  0b10..Reserved
 *  0b11..Reserved
 */
#define HSCMP_CCR2_INPSEL(x)                     (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR2_INPSEL_SHIFT)) & HSCMP_CCR2_INPSEL_MASK)

#define HSCMP_CCR2_INMSEL_MASK                   (0x30000000U)
#define HSCMP_CCR2_INMSEL_SHIFT                  (28U)
/*! INMSEL - Input Minus Select
 *  0b00..IN0: from the 8-bit DAC output
 *  0b01..IN1: from the analog 8-1 mux
 *  0b10..Reserved
 *  0b11..Reserved
 */
#define HSCMP_CCR2_INMSEL(x)                     (((uint32_t)(((uint32_t)(x)) << HSCMP_CCR2_INMSEL_SHIFT)) & HSCMP_CCR2_INMSEL_MASK)
/*! @} */

/*! @name DCR - DAC Control Register */
/*! @{ */

#define HSCMP_DCR_DAC_EN_MASK                    (0x1U)
#define HSCMP_DCR_DAC_EN_SHIFT                   (0U)
/*! DAC_EN - DAC Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define HSCMP_DCR_DAC_EN(x)                      (((uint32_t)(((uint32_t)(x)) << HSCMP_DCR_DAC_EN_SHIFT)) & HSCMP_DCR_DAC_EN_MASK)

#define HSCMP_DCR_DAC_HPMD_MASK                  (0x2U)
#define HSCMP_DCR_DAC_HPMD_SHIFT                 (1U)
/*! DAC_HPMD - DAC High Power Mode Select
 *  0b0..Disable
 *  0b1..Enable
 */
#define HSCMP_DCR_DAC_HPMD(x)                    (((uint32_t)(((uint32_t)(x)) << HSCMP_DCR_DAC_HPMD_SHIFT)) & HSCMP_DCR_DAC_HPMD_MASK)

#define HSCMP_DCR_VRSEL_MASK                     (0x100U)
#define HSCMP_DCR_VRSEL_SHIFT                    (8U)
/*! VRSEL - DAC Reference High Voltage Source Select
 *  0b0..vrefh0
 *  0b1..vrefh1
 */
#define HSCMP_DCR_VRSEL(x)                       (((uint32_t)(((uint32_t)(x)) << HSCMP_DCR_VRSEL_SHIFT)) & HSCMP_DCR_VRSEL_MASK)

#define HSCMP_DCR_DACOE_MASK                     (0x8000U)
#define HSCMP_DCR_DACOE_SHIFT                    (15U)
/*! DACOE - DAC Output Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define HSCMP_DCR_DACOE(x)                       (((uint32_t)(((uint32_t)(x)) << HSCMP_DCR_DACOE_SHIFT)) & HSCMP_DCR_DACOE_MASK)

#define HSCMP_DCR_DAC_DATA_MASK                  (0xFF0000U)
#define HSCMP_DCR_DAC_DATA_SHIFT                 (16U)
/*! DAC_DATA - DAC Output Voltage Select
 */
#define HSCMP_DCR_DAC_DATA(x)                    (((uint32_t)(((uint32_t)(x)) << HSCMP_DCR_DAC_DATA_SHIFT)) & HSCMP_DCR_DAC_DATA_MASK)
/*! @} */

/*! @name IER - Interrupt Enable Register */
/*! @{ */

#define HSCMP_IER_CFR_IE_MASK                    (0x1U)
#define HSCMP_IER_CFR_IE_SHIFT                   (0U)
/*! CFR_IE - Comparator Flag Rising Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable: Assert an interrupt when CFR is set.
 */
#define HSCMP_IER_CFR_IE(x)                      (((uint32_t)(((uint32_t)(x)) << HSCMP_IER_CFR_IE_SHIFT)) & HSCMP_IER_CFR_IE_MASK)

#define HSCMP_IER_CFF_IE_MASK                    (0x2U)
#define HSCMP_IER_CFF_IE_SHIFT                   (1U)
/*! CFF_IE - Comparator Flag Falling Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable: Assert an interrupt when CFF is set.
 */
#define HSCMP_IER_CFF_IE(x)                      (((uint32_t)(((uint32_t)(x)) << HSCMP_IER_CFF_IE_SHIFT)) & HSCMP_IER_CFF_IE_MASK)

#define HSCMP_IER_RRF_IE_MASK                    (0x4U)
#define HSCMP_IER_RRF_IE_SHIFT                   (2U)
/*! RRF_IE - Round-Robin Flag Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable: Assert an interrupt when the comparison result changes for a given channel.
 */
#define HSCMP_IER_RRF_IE(x)                      (((uint32_t)(((uint32_t)(x)) << HSCMP_IER_RRF_IE_SHIFT)) & HSCMP_IER_RRF_IE_MASK)
/*! @} */

/*! @name CSR - Comparator Status Register */
/*! @{ */

#define HSCMP_CSR_CFR_MASK                       (0x1U)
#define HSCMP_CSR_CFR_SHIFT                      (0U)
/*! CFR - Analog Comparator Flag Rising
 *  0b0..Not detected
 *  0b1..Detected
 */
#define HSCMP_CSR_CFR(x)                         (((uint32_t)(((uint32_t)(x)) << HSCMP_CSR_CFR_SHIFT)) & HSCMP_CSR_CFR_MASK)

#define HSCMP_CSR_CFF_MASK                       (0x2U)
#define HSCMP_CSR_CFF_SHIFT                      (1U)
/*! CFF - Analog Comparator Flag Falling
 *  0b0..Not detected
 *  0b1..Detected
 */
#define HSCMP_CSR_CFF(x)                         (((uint32_t)(((uint32_t)(x)) << HSCMP_CSR_CFF_SHIFT)) & HSCMP_CSR_CFF_MASK)

#define HSCMP_CSR_RRF_MASK                       (0x4U)
#define HSCMP_CSR_RRF_SHIFT                      (2U)
/*! RRF - Round-Robin Flag
 *  0b0..Not detected
 *  0b1..Detected
 */
#define HSCMP_CSR_RRF(x)                         (((uint32_t)(((uint32_t)(x)) << HSCMP_CSR_RRF_SHIFT)) & HSCMP_CSR_RRF_MASK)

#define HSCMP_CSR_COUT_MASK                      (0x100U)
#define HSCMP_CSR_COUT_SHIFT                     (8U)
/*! COUT - Analog Comparator Output
 */
#define HSCMP_CSR_COUT(x)                        (((uint32_t)(((uint32_t)(x)) << HSCMP_CSR_COUT_SHIFT)) & HSCMP_CSR_COUT_MASK)
/*! @} */

/*! @name RRCR0 - Round Robin Control Register 0 */
/*! @{ */

#define HSCMP_RRCR0_RR_EN_MASK                   (0x1U)
#define HSCMP_RRCR0_RR_EN_SHIFT                  (0U)
/*! RR_EN - Round-Robin Enable
 *  0b1..Enable
 *  0b0..Disable
 */
#define HSCMP_RRCR0_RR_EN(x)                     (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCR0_RR_EN_SHIFT)) & HSCMP_RRCR0_RR_EN_MASK)

#define HSCMP_RRCR0_RR_NSAM_MASK                 (0x300U)
#define HSCMP_RRCR0_RR_NSAM_SHIFT                (8U)
/*! RR_NSAM - Number of Sample Clocks
 *  0b00..0 clocks
 *  0b01..1 clocks
 *  0b10..2 clocks
 *  0b11..3 clocks
 */
#define HSCMP_RRCR0_RR_NSAM(x)                   (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCR0_RR_NSAM_SHIFT)) & HSCMP_RRCR0_RR_NSAM_MASK)

#define HSCMP_RRCR0_RR_INITMOD_MASK              (0x3F0000U)
#define HSCMP_RRCR0_RR_INITMOD_SHIFT             (16U)
/*! RR_INITMOD - Initialization Delay Modulus
 *  0b000000..63 cycles (same as 111111b)
 *  0b000001-0b111111..1 to 63 cycles
 */
#define HSCMP_RRCR0_RR_INITMOD(x)                (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCR0_RR_INITMOD_SHIFT)) & HSCMP_RRCR0_RR_INITMOD_MASK)
/*! @} */

/*! @name RRCR1 - Round Robin Control Register 1 */
/*! @{ */

#define HSCMP_RRCR1_RR_CH0EN_MASK                (0x1U)
#define HSCMP_RRCR1_RR_CH0EN_SHIFT               (0U)
/*! RR_CH0EN - Channel 0 Input Enable in Trigger Mode
 *  0b1..Enable
 *  0b0..Disable
 */
#define HSCMP_RRCR1_RR_CH0EN(x)                  (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCR1_RR_CH0EN_SHIFT)) & HSCMP_RRCR1_RR_CH0EN_MASK)

#define HSCMP_RRCR1_RR_CH1EN_MASK                (0x2U)
#define HSCMP_RRCR1_RR_CH1EN_SHIFT               (1U)
/*! RR_CH1EN - Channel 1 Input Enable in Trigger Mode
 *  0b1..Enable
 *  0b0..Disable
 */
#define HSCMP_RRCR1_RR_CH1EN(x)                  (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCR1_RR_CH1EN_SHIFT)) & HSCMP_RRCR1_RR_CH1EN_MASK)

#define HSCMP_RRCR1_RR_CH2EN_MASK                (0x4U)
#define HSCMP_RRCR1_RR_CH2EN_SHIFT               (2U)
/*! RR_CH2EN - Channel 2 Input Enable in Trigger Mode
 *  0b1..Enable
 *  0b0..Disable
 */
#define HSCMP_RRCR1_RR_CH2EN(x)                  (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCR1_RR_CH2EN_SHIFT)) & HSCMP_RRCR1_RR_CH2EN_MASK)

#define HSCMP_RRCR1_RR_CH3EN_MASK                (0x8U)
#define HSCMP_RRCR1_RR_CH3EN_SHIFT               (3U)
/*! RR_CH3EN - Channel 3 Input Enable in Trigger Mode
 *  0b1..Enable
 *  0b0..Disable
 */
#define HSCMP_RRCR1_RR_CH3EN(x)                  (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCR1_RR_CH3EN_SHIFT)) & HSCMP_RRCR1_RR_CH3EN_MASK)

#define HSCMP_RRCR1_RR_CH4EN_MASK                (0x10U)
#define HSCMP_RRCR1_RR_CH4EN_SHIFT               (4U)
/*! RR_CH4EN - Channel 4 Input Enable in Trigger Mode
 *  0b1..Enable
 *  0b0..Disable
 */
#define HSCMP_RRCR1_RR_CH4EN(x)                  (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCR1_RR_CH4EN_SHIFT)) & HSCMP_RRCR1_RR_CH4EN_MASK)

#define HSCMP_RRCR1_RR_CH5EN_MASK                (0x20U)
#define HSCMP_RRCR1_RR_CH5EN_SHIFT               (5U)
/*! RR_CH5EN - Channel 5 Input Enable in Trigger Mode
 *  0b1..Enable
 *  0b0..Disable
 */
#define HSCMP_RRCR1_RR_CH5EN(x)                  (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCR1_RR_CH5EN_SHIFT)) & HSCMP_RRCR1_RR_CH5EN_MASK)

#define HSCMP_RRCR1_RR_CH6EN_MASK                (0x40U)
#define HSCMP_RRCR1_RR_CH6EN_SHIFT               (6U)
/*! RR_CH6EN - Channel 6 Input Enable in Trigger Mode
 *  0b1..Enable
 *  0b0..Disable
 */
#define HSCMP_RRCR1_RR_CH6EN(x)                  (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCR1_RR_CH6EN_SHIFT)) & HSCMP_RRCR1_RR_CH6EN_MASK)

#define HSCMP_RRCR1_RR_CH7EN_MASK                (0x80U)
#define HSCMP_RRCR1_RR_CH7EN_SHIFT               (7U)
/*! RR_CH7EN - Channel 7 Input Enable in Trigger Mode
 *  0b1..Enable
 *  0b0..Disable
 */
#define HSCMP_RRCR1_RR_CH7EN(x)                  (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCR1_RR_CH7EN_SHIFT)) & HSCMP_RRCR1_RR_CH7EN_MASK)

#define HSCMP_RRCR1_FIXP_MASK                    (0x10000U)
#define HSCMP_RRCR1_FIXP_SHIFT                   (16U)
/*! FIXP - Fixed Port
 *  0b0..Fix the Plus port. Sweep only the inputs to the Minus port.
 *  0b1..Fix the Minus port. Sweep only the inputs to the Plus port.
 */
#define HSCMP_RRCR1_FIXP(x)                      (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCR1_FIXP_SHIFT)) & HSCMP_RRCR1_FIXP_MASK)

#define HSCMP_RRCR1_FIXCH_MASK                   (0x700000U)
#define HSCMP_RRCR1_FIXCH_SHIFT                  (20U)
/*! FIXCH - Fixed Channel Select
 *  0b000..Channel 0
 *  0b001..Channel 1
 *  0b010..Channel 2
 *  0b011..Channel 3
 *  0b100..Channel 4
 *  0b101..Channel 5
 *  0b110..Channel 6
 *  0b111..Channel 7
 */
#define HSCMP_RRCR1_FIXCH(x)                     (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCR1_FIXCH_SHIFT)) & HSCMP_RRCR1_FIXCH_MASK)
/*! @} */

/*! @name RRCSR - Round Robin Control and Status Register */
/*! @{ */

#define HSCMP_RRCSR_RR_CH0OUT_MASK               (0x1U)
#define HSCMP_RRCSR_RR_CH0OUT_SHIFT              (0U)
/*! RR_CH0OUT - Comparison Result for Channel 0
 */
#define HSCMP_RRCSR_RR_CH0OUT(x)                 (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCSR_RR_CH0OUT_SHIFT)) & HSCMP_RRCSR_RR_CH0OUT_MASK)

#define HSCMP_RRCSR_RR_CH1OUT_MASK               (0x2U)
#define HSCMP_RRCSR_RR_CH1OUT_SHIFT              (1U)
/*! RR_CH1OUT - Comparison Result for Channel 1
 */
#define HSCMP_RRCSR_RR_CH1OUT(x)                 (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCSR_RR_CH1OUT_SHIFT)) & HSCMP_RRCSR_RR_CH1OUT_MASK)

#define HSCMP_RRCSR_RR_CH2OUT_MASK               (0x4U)
#define HSCMP_RRCSR_RR_CH2OUT_SHIFT              (2U)
/*! RR_CH2OUT - Comparison Result for Channel 2
 */
#define HSCMP_RRCSR_RR_CH2OUT(x)                 (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCSR_RR_CH2OUT_SHIFT)) & HSCMP_RRCSR_RR_CH2OUT_MASK)

#define HSCMP_RRCSR_RR_CH3OUT_MASK               (0x8U)
#define HSCMP_RRCSR_RR_CH3OUT_SHIFT              (3U)
/*! RR_CH3OUT - Comparison Result for Channel 3
 */
#define HSCMP_RRCSR_RR_CH3OUT(x)                 (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCSR_RR_CH3OUT_SHIFT)) & HSCMP_RRCSR_RR_CH3OUT_MASK)

#define HSCMP_RRCSR_RR_CH4OUT_MASK               (0x10U)
#define HSCMP_RRCSR_RR_CH4OUT_SHIFT              (4U)
/*! RR_CH4OUT - Comparison Result for Channel 4
 */
#define HSCMP_RRCSR_RR_CH4OUT(x)                 (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCSR_RR_CH4OUT_SHIFT)) & HSCMP_RRCSR_RR_CH4OUT_MASK)

#define HSCMP_RRCSR_RR_CH5OUT_MASK               (0x20U)
#define HSCMP_RRCSR_RR_CH5OUT_SHIFT              (5U)
/*! RR_CH5OUT - Comparison Result for Channel 5
 */
#define HSCMP_RRCSR_RR_CH5OUT(x)                 (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCSR_RR_CH5OUT_SHIFT)) & HSCMP_RRCSR_RR_CH5OUT_MASK)

#define HSCMP_RRCSR_RR_CH6OUT_MASK               (0x40U)
#define HSCMP_RRCSR_RR_CH6OUT_SHIFT              (6U)
/*! RR_CH6OUT - Comparison Result for Channel 6
 */
#define HSCMP_RRCSR_RR_CH6OUT(x)                 (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCSR_RR_CH6OUT_SHIFT)) & HSCMP_RRCSR_RR_CH6OUT_MASK)

#define HSCMP_RRCSR_RR_CH7OUT_MASK               (0x80U)
#define HSCMP_RRCSR_RR_CH7OUT_SHIFT              (7U)
/*! RR_CH7OUT - Comparison Result for Channel 7
 */
#define HSCMP_RRCSR_RR_CH7OUT(x)                 (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCSR_RR_CH7OUT_SHIFT)) & HSCMP_RRCSR_RR_CH7OUT_MASK)
/*! @} */

/*! @name RRSR - Round Robin Status Register */
/*! @{ */

#define HSCMP_RRSR_RR_CH0F_MASK                  (0x1U)
#define HSCMP_RRSR_RR_CH0F_SHIFT                 (0U)
/*! RR_CH0F - Channel 0 Input Changed Flag
 *  0b0..Not different
 *  0b1..Different
 */
#define HSCMP_RRSR_RR_CH0F(x)                    (((uint32_t)(((uint32_t)(x)) << HSCMP_RRSR_RR_CH0F_SHIFT)) & HSCMP_RRSR_RR_CH0F_MASK)

#define HSCMP_RRSR_RR_CH1F_MASK                  (0x2U)
#define HSCMP_RRSR_RR_CH1F_SHIFT                 (1U)
/*! RR_CH1F - Channel 1 Input Changed Flag
 *  0b0..Not different
 *  0b1..Different
 */
#define HSCMP_RRSR_RR_CH1F(x)                    (((uint32_t)(((uint32_t)(x)) << HSCMP_RRSR_RR_CH1F_SHIFT)) & HSCMP_RRSR_RR_CH1F_MASK)

#define HSCMP_RRSR_RR_CH2F_MASK                  (0x4U)
#define HSCMP_RRSR_RR_CH2F_SHIFT                 (2U)
/*! RR_CH2F - Channel 2 Input Changed Flag
 *  0b0..Not different
 *  0b1..Different
 */
#define HSCMP_RRSR_RR_CH2F(x)                    (((uint32_t)(((uint32_t)(x)) << HSCMP_RRSR_RR_CH2F_SHIFT)) & HSCMP_RRSR_RR_CH2F_MASK)

#define HSCMP_RRSR_RR_CH3F_MASK                  (0x8U)
#define HSCMP_RRSR_RR_CH3F_SHIFT                 (3U)
/*! RR_CH3F - Channel 3 Input Changed Flag
 *  0b0..Not different
 *  0b1..Different
 */
#define HSCMP_RRSR_RR_CH3F(x)                    (((uint32_t)(((uint32_t)(x)) << HSCMP_RRSR_RR_CH3F_SHIFT)) & HSCMP_RRSR_RR_CH3F_MASK)

#define HSCMP_RRSR_RR_CH4F_MASK                  (0x10U)
#define HSCMP_RRSR_RR_CH4F_SHIFT                 (4U)
/*! RR_CH4F - Channel 4 Input Changed Flag
 *  0b0..Not different
 *  0b1..Different
 */
#define HSCMP_RRSR_RR_CH4F(x)                    (((uint32_t)(((uint32_t)(x)) << HSCMP_RRSR_RR_CH4F_SHIFT)) & HSCMP_RRSR_RR_CH4F_MASK)

#define HSCMP_RRSR_RR_CH5F_MASK                  (0x20U)
#define HSCMP_RRSR_RR_CH5F_SHIFT                 (5U)
/*! RR_CH5F - Channel 5 Input Changed Flag
 *  0b0..Not different
 *  0b1..Different
 */
#define HSCMP_RRSR_RR_CH5F(x)                    (((uint32_t)(((uint32_t)(x)) << HSCMP_RRSR_RR_CH5F_SHIFT)) & HSCMP_RRSR_RR_CH5F_MASK)

#define HSCMP_RRSR_RR_CH6F_MASK                  (0x40U)
#define HSCMP_RRSR_RR_CH6F_SHIFT                 (6U)
/*! RR_CH6F - Channel 6 Input Changed Flag
 *  0b0..Not different
 *  0b1..Different
 */
#define HSCMP_RRSR_RR_CH6F(x)                    (((uint32_t)(((uint32_t)(x)) << HSCMP_RRSR_RR_CH6F_SHIFT)) & HSCMP_RRSR_RR_CH6F_MASK)

#define HSCMP_RRSR_RR_CH7F_MASK                  (0x80U)
#define HSCMP_RRSR_RR_CH7F_SHIFT                 (7U)
/*! RR_CH7F - Channel 7 Input Changed Flag
 *  0b0..Not different
 *  0b1..Different
 */
#define HSCMP_RRSR_RR_CH7F(x)                    (((uint32_t)(((uint32_t)(x)) << HSCMP_RRSR_RR_CH7F_SHIFT)) & HSCMP_RRSR_RR_CH7F_MASK)
/*! @} */

/*! @name RRCR2 - Round Robin Control Register 2 */
/*! @{ */

#define HSCMP_RRCR2_RR_TIMER_RELOAD_MASK         (0xFFFFFFFU)
#define HSCMP_RRCR2_RR_TIMER_RELOAD_SHIFT        (0U)
/*! RR_TIMER_RELOAD - Number of sample clocks
 */
#define HSCMP_RRCR2_RR_TIMER_RELOAD(x)           (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCR2_RR_TIMER_RELOAD_SHIFT)) & HSCMP_RRCR2_RR_TIMER_RELOAD_MASK)

#define HSCMP_RRCR2_RR_TIMER_EN_MASK             (0x80000000U)
#define HSCMP_RRCR2_RR_TIMER_EN_SHIFT            (31U)
/*! RR_TIMER_EN - Round-Robin internal timer enable.
 *  0b0..Round-Robin internal timer is disabled.
 *  0b1..Round-Robin internal timer is enabled.
 */
#define HSCMP_RRCR2_RR_TIMER_EN(x)               (((uint32_t)(((uint32_t)(x)) << HSCMP_RRCR2_RR_TIMER_EN_SHIFT)) & HSCMP_RRCR2_RR_TIMER_EN_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group HSCMP_Register_Masks */


/* HSCMP - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral HSCMP0 base address */
  #define HSCMP0_BASE                              (0x500B3000u)
  /** Peripheral HSCMP0 base address */
  #define HSCMP0_BASE_NS                           (0x400B3000u)
  /** Peripheral HSCMP0 base pointer */
  #define HSCMP0                                   ((HSCMP_Type *)HSCMP0_BASE)
  /** Peripheral HSCMP0 base pointer */
  #define HSCMP0_NS                                ((HSCMP_Type *)HSCMP0_BASE_NS)
  /** Peripheral HSCMP1 base address */
  #define HSCMP1_BASE                              (0x500B7000u)
  /** Peripheral HSCMP1 base address */
  #define HSCMP1_BASE_NS                           (0x400B7000u)
  /** Peripheral HSCMP1 base pointer */
  #define HSCMP1                                   ((HSCMP_Type *)HSCMP1_BASE)
  /** Peripheral HSCMP1 base pointer */
  #define HSCMP1_NS                                ((HSCMP_Type *)HSCMP1_BASE_NS)
  /** Peripheral HSCMP2 base address */
  #define HSCMP2_BASE                              (0x500BA000u)
  /** Peripheral HSCMP2 base address */
  #define HSCMP2_BASE_NS                           (0x400BA000u)
  /** Peripheral HSCMP2 base pointer */
  #define HSCMP2                                   ((HSCMP_Type *)HSCMP2_BASE)
  /** Peripheral HSCMP2 base pointer */
  #define HSCMP2_NS                                ((HSCMP_Type *)HSCMP2_BASE_NS)
  /** Array initializer of HSCMP peripheral base addresses */
  #define HSCMP_BASE_ADDRS                         { HSCMP0_BASE, HSCMP1_BASE, HSCMP2_BASE }
  /** Array initializer of HSCMP peripheral base pointers */
  #define HSCMP_BASE_PTRS                          { HSCMP0, HSCMP1, HSCMP2 }
  /** Array initializer of HSCMP peripheral base addresses */
  #define HSCMP_BASE_ADDRS_NS                      { HSCMP0_BASE_NS, HSCMP1_BASE_NS, HSCMP2_BASE_NS }
  /** Array initializer of HSCMP peripheral base pointers */
  #define HSCMP_BASE_PTRS_NS                       { HSCMP0_NS, HSCMP1_NS, HSCMP2_NS }
#else
  /** Peripheral HSCMP0 base address */
  #define HSCMP0_BASE                              (0x400B3000u)
  /** Peripheral HSCMP0 base pointer */
  #define HSCMP0                                   ((HSCMP_Type *)HSCMP0_BASE)
  /** Peripheral HSCMP1 base address */
  #define HSCMP1_BASE                              (0x400B7000u)
  /** Peripheral HSCMP1 base pointer */
  #define HSCMP1                                   ((HSCMP_Type *)HSCMP1_BASE)
  /** Peripheral HSCMP2 base address */
  #define HSCMP2_BASE                              (0x400BA000u)
  /** Peripheral HSCMP2 base pointer */
  #define HSCMP2                                   ((HSCMP_Type *)HSCMP2_BASE)
  /** Array initializer of HSCMP peripheral base addresses */
  #define HSCMP_BASE_ADDRS                         { HSCMP0_BASE, HSCMP1_BASE, HSCMP2_BASE }
  /** Array initializer of HSCMP peripheral base pointers */
  #define HSCMP_BASE_PTRS                          { HSCMP0, HSCMP1, HSCMP2 }
#endif
/** Interrupt vectors for the HSCMP peripheral type */
#define HSCMP_IRQS                               { HSCMP0_IRQn, HSCMP1_IRQn, HSCMP2_IRQn }

/*!
 * @}
 */ /* end of group HSCMP_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- I2C Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
 * @{
 */

/** I2C - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[2048];
  __IO uint32_t CFG;                               /**< Configuration Register, offset: 0x800 */
  __IO uint32_t STAT;                              /**< Status Register, offset: 0x804 */
  __IO uint32_t INTENSET;                          /**< Interrupt Enable Set Register, offset: 0x808 */
  __O  uint32_t INTENCLR;                          /**< Interrupt Enable Clear Register, offset: 0x80C */
  __IO uint32_t TIMEOUT;                           /**< Time-out Register, offset: 0x810 */
  __IO uint32_t CLKDIV;                            /**< Clock Divider Register, offset: 0x814 */
  __I  uint32_t INTSTAT;                           /**< Interrupt Status Register, offset: 0x818 */
       uint8_t RESERVED_1[4];
  __IO uint32_t MSTCTL;                            /**< Master Control Register, offset: 0x820 */
  __IO uint32_t MSTTIME;                           /**< Master Timing Register, offset: 0x824 */
  __IO uint32_t MSTDAT;                            /**< Master Data Register, offset: 0x828 */
       uint8_t RESERVED_2[20];
  __IO uint32_t SLVCTL;                            /**< Slave Control Register, offset: 0x840 */
  __IO uint32_t SLVDAT;                            /**< Slave Data Register, offset: 0x844 */
  __IO uint32_t SLVADR[4];                         /**< Slave Address Register, array offset: 0x848, array step: 0x4 */
  __IO uint32_t SLVQUAL0;                          /**< Slave Qualification for Address 0 Register, offset: 0x858 */
       uint8_t RESERVED_3[36];
  __I  uint32_t MONRXDAT;                          /**< Monitor Receiver Data Register, offset: 0x880 */
       uint8_t RESERVED_4[1912];
  __I  uint32_t ID;                                /**< Peripheral Identification Register, offset: 0xFFC */
} I2C_Type;

/* ----------------------------------------------------------------------------
   -- I2C Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup I2C_Register_Masks I2C Register Masks
 * @{
 */

/*! @name CFG - Configuration Register */
/*! @{ */

#define I2C_CFG_MSTEN_MASK                       (0x1U)
#define I2C_CFG_MSTEN_SHIFT                      (0U)
/*! MSTEN - Master Enable
 *  0b0..Disabled. The I2C Master function is disabled. When disabled, the Master configuration settings are not
 *       changed, but the Master function is internally reset.
 *  0b1..Enabled. The I2C Master function is enabled.
 */
#define I2C_CFG_MSTEN(x)                         (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK)

#define I2C_CFG_SLVEN_MASK                       (0x2U)
#define I2C_CFG_SLVEN_SHIFT                      (1U)
/*! SLVEN - Slave Enable
 *  0b0..Disabled. The I2C slave function is disabled. When disabled, the Slave configuration settings are not
 *       changed, but the Slave function is internally reset.
 *  0b1..Enabled. The I2C slave function is enabled.
 */
#define I2C_CFG_SLVEN(x)                         (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK)

#define I2C_CFG_MONEN_MASK                       (0x4U)
#define I2C_CFG_MONEN_SHIFT                      (2U)
/*! MONEN - Monitor Enable
 *  0b0..Disabled. The I2C Monitor function is disabled. When disabled, the Monitor function configuration
 *       settings are not changed, but the Monitor function is internally reset.
 *  0b1..Enabled. The I2C Monitor function is enabled.
 */
#define I2C_CFG_MONEN(x)                         (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK)

#define I2C_CFG_TIMEOUTEN_MASK                   (0x8U)
#define I2C_CFG_TIMEOUTEN_SHIFT                  (3U)
/*! TIMEOUTEN - I2C bus Time-out Enable
 *  0b0..Disabled. The time-out function is disabled. When disabled, the time-out function is internally reset.
 *  0b1..Enabled. The time-out function is enabled. Both types of time-out flags will be generated and will cause
 *       interrupts if those flags are enabled. Typically, only one time-out flag will be used in a system.
 */
#define I2C_CFG_TIMEOUTEN(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK)

#define I2C_CFG_MONCLKSTR_MASK                   (0x10U)
#define I2C_CFG_MONCLKSTR_SHIFT                  (4U)
/*! MONCLKSTR - Monitor function Clock Stretching
 *  0b0..Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able
 *       to read data provided by the Monitor function before it (the data) is overwritten. This mode can be used
 *       when non-invasive monitoring is critical.
 *  0b1..Enabled. The Monitor function will perform clock stretching, to ensure that the software or DMA can read
 *       all incoming data supplied by the Monitor function.
 */
#define I2C_CFG_MONCLKSTR(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK)

#define I2C_CFG_HSCAPABLE_MASK                   (0x20U)
#define I2C_CFG_HSCAPABLE_SHIFT                  (5U)
/*! HSCAPABLE - High Speed mode Capable enable
 *  0b0..Fast mode Plus enable
 *  0b1..High Speed mode enable
 */
#define I2C_CFG_HSCAPABLE(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_CFG_HSCAPABLE_SHIFT)) & I2C_CFG_HSCAPABLE_MASK)
/*! @} */

/*! @name STAT - Status Register */
/*! @{ */

#define I2C_STAT_MSTPENDING_MASK                 (0x1U)
#define I2C_STAT_MSTPENDING_SHIFT                (0U)
/*! MSTPENDING - Master Pending
 *  0b0..In progress. Communication is in progress and the Master function is busy and cannot currently accept a command.
 *  0b1..Pending. The Master function needs software service or is in the idle state. If the master is not in the
 *       idle state, then the master is waiting to receive or transmit data, or is waiting for the NACK bit.
 */
#define I2C_STAT_MSTPENDING(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK)

#define I2C_STAT_MSTSTATE_MASK                   (0xEU)
#define I2C_STAT_MSTSTATE_SHIFT                  (1U)
/*! MSTSTATE - Master State code
 *  0b000..Idle. The Master function is available to be used for a new transaction.
 *  0b001..Receive ready. Received data is available (in Master Receiver mode). Address plus Read was previously sent and Acknowledged by a slave.
 *  0b010..Transmit ready. Data can be transmitted (in Master Transmitter mode). Address plus Write was previously sent and Acknowledged by a slave.
 *  0b011..NACK Address. Slave NACKed address.
 *  0b100..NACK Data. Slave NACKed transmitted data.
 */
#define I2C_STAT_MSTSTATE(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK)

#define I2C_STAT_MSTARBLOSS_MASK                 (0x10U)
#define I2C_STAT_MSTARBLOSS_SHIFT                (4U)
/*! MSTARBLOSS - Master Arbitration Loss flag
 *  0b0..No Arbitration Loss has occurred
 *  0b1..Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master
 *       function has already stopped driving the bus and has gone into an idle state. Software can respond by doing
 *       nothing, or by sending a Start (to attempt to gain control of the bus when the bus next becomes idle).
 */
#define I2C_STAT_MSTARBLOSS(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK)

#define I2C_STAT_MSTSTSTPERR_MASK                (0x40U)
#define I2C_STAT_MSTSTSTPERR_SHIFT               (6U)
/*! MSTSTSTPERR - Master Start/Stop Error flag
 *  0b0..No Start/Stop Error has occurred.
 *  0b1..The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when Start
 *       or Stop is not allowed by the I2C specification. The Master interface has stopped driving the bus and
 *       gone into an idle state; no action is required. A request for a Start could be made, or software could
 *       attempt to make sure that the bus has not stalled.
 */
#define I2C_STAT_MSTSTSTPERR(x)                  (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK)

#define I2C_STAT_SLVPENDING_MASK                 (0x100U)
#define I2C_STAT_SLVPENDING_SHIFT                (8U)
/*! SLVPENDING - Slave Pending
 *  0b0..In progress. The Slave function does not currently need software service.
 *  0b1..Pending. The Slave function needs software service. Information about what is needed is in the Slave state field (SLVSTATE).
 */
#define I2C_STAT_SLVPENDING(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK)

#define I2C_STAT_SLVSTATE_MASK                   (0x600U)
#define I2C_STAT_SLVSTATE_SHIFT                  (9U)
/*! SLVSTATE - Slave State
 *  0b00..Slave address. Address plus R/W received. At least one of the 4 slave addresses has been matched by hardware.
 *  0b01..Slave receive. Received data is available (in Slave Receiver mode).
 *  0b10..Slave transmit. Data can be transmitted (in Slave Transmitter mode).
 *  0b11..Reserved
 */
#define I2C_STAT_SLVSTATE(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK)

#define I2C_STAT_SLVNOTSTR_MASK                  (0x800U)
#define I2C_STAT_SLVNOTSTR_SHIFT                 (11U)
/*! SLVNOTSTR - Slave Not Stretching
 *  0b0..Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleepmode cannot be entered at this time.
 *  0b1..Not stretching. The slave function is not currently stretching the I2C bus clock. Deep-sleep mode can be entered at this time.
 */
#define I2C_STAT_SLVNOTSTR(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK)

#define I2C_STAT_SLVIDX_MASK                     (0x3000U)
#define I2C_STAT_SLVIDX_SHIFT                    (12U)
/*! SLVIDX - Slave address match Index T
 *  0b00..Address 0. Slave address 0 was matched.
 *  0b01..Address 1. Slave address 1 was matched.
 *  0b10..Address 2. Slave address 2 was matched.
 *  0b11..Address 3. Slave address 3 was matched.
 */
#define I2C_STAT_SLVIDX(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK)

#define I2C_STAT_SLVSEL_MASK                     (0x4000U)
#define I2C_STAT_SLVSEL_SHIFT                    (14U)
/*! SLVSEL - Slave selected flag
 *  0b0..Not selected. The Slave function is not currently selected.
 *  0b1..Selected. The Slave function is currently selected.
 */
#define I2C_STAT_SLVSEL(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK)

#define I2C_STAT_SLVDESEL_MASK                   (0x8000U)
#define I2C_STAT_SLVDESEL_SHIFT                  (15U)
/*! SLVDESEL - Slave Deselected flag
 *  0b0..Not deselected. The Slave function has not become deselected. This does not mean that the Slave is
 *       currently selected. That information is in the SLVSEL flag.
 *  0b1..Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag
 *       changing from 1 to 0. See SLVSEL for details about when that event occurs.
 */
#define I2C_STAT_SLVDESEL(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK)

#define I2C_STAT_MONRDY_MASK                     (0x10000U)
#define I2C_STAT_MONRDY_SHIFT                    (16U)
/*! MONRDY - Monitor Ready
 *  0b0..No data. The Monitor function does not currently have data available.
 *  0b1..Data waiting. The Monitor function has data waiting to be read.
 */
#define I2C_STAT_MONRDY(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK)

#define I2C_STAT_MONOV_MASK                      (0x20000U)
#define I2C_STAT_MONOV_SHIFT                     (17U)
/*! MONOV - Monitor Overflow flag
 *  0b0..No overrun. Monitor data has not overrun.
 *  0b1..Overrun. A Monitor data overrun has occurred. An overrun can only happen when Monitor clock stretching
 *       not enabled via the CFG[MONCLKSTR] bit. Writing 1 to MONOV bit clears the MONOV flag.
 */
#define I2C_STAT_MONOV(x)                        (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK)

#define I2C_STAT_MONACTIVE_MASK                  (0x40000U)
#define I2C_STAT_MONACTIVE_SHIFT                 (18U)
/*! MONACTIVE - Monitor Active flag
 *  0b0..Inactive. The Monitor function considers the I2C bus to be inactive.
 *  0b1..Active. The Monitor function considers the I2C bus to be active.
 */
#define I2C_STAT_MONACTIVE(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK)

#define I2C_STAT_MONIDLE_MASK                    (0x80000U)
#define I2C_STAT_MONIDLE_SHIFT                   (19U)
/*! MONIDLE - Monitor Idle flag
 *  0b0..Not idle. The I2C bus is not idle, or MONIDLE flag has been cleared by software.
 *  0b1..Idle. The I2C bus has gone idle at least once, since the last time MONIDLE flag was cleared by software.
 */
#define I2C_STAT_MONIDLE(x)                      (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK)

#define I2C_STAT_EVENTTIMEOUT_MASK               (0x1000000U)
#define I2C_STAT_EVENTTIMEOUT_SHIFT              (24U)
/*! EVENTTIMEOUT - Event Time-out Interrupt flag
 *  0b0..No time-out. I2C bus events have not caused a time-out.
 *  0b1..Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register.
 */
#define I2C_STAT_EVENTTIMEOUT(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK)

#define I2C_STAT_SCLTIMEOUT_MASK                 (0x2000000U)
#define I2C_STAT_SCLTIMEOUT_SHIFT                (25U)
/*! SCLTIMEOUT - SCL Time-out Interrupt flag
 *  0b0..No time-out. SCL low time has not caused a time-out.
 *  0b1..Time-out. SCL low time has caused a time-out.
 */
#define I2C_STAT_SCLTIMEOUT(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK)
/*! @} */

/*! @name INTENSET - Interrupt Enable Set Register */
/*! @{ */

#define I2C_INTENSET_MSTPENDINGEN_MASK           (0x1U)
#define I2C_INTENSET_MSTPENDINGEN_SHIFT          (0U)
/*! MSTPENDINGEN - Master Pending interrupt Enable
 *  0b0..Disabled. The MstPending interrupt is disabled.
 *  0b1..Enabled. The MstPending interrupt is enabled.
 */
#define I2C_INTENSET_MSTPENDINGEN(x)             (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK)

#define I2C_INTENSET_MSTARBLOSSEN_MASK           (0x10U)
#define I2C_INTENSET_MSTARBLOSSEN_SHIFT          (4U)
/*! MSTARBLOSSEN - Master Arbitration Loss interrupt Enable
 *  0b0..Disabled. The MstArbLoss interrupt is disabled.
 *  0b1..Enabled. The MstArbLoss interrupt is enabled.
 */
#define I2C_INTENSET_MSTARBLOSSEN(x)             (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK)

#define I2C_INTENSET_MSTSTSTPERREN_MASK          (0x40U)
#define I2C_INTENSET_MSTSTSTPERREN_SHIFT         (6U)
/*! MSTSTSTPERREN - Master Start/Stop Error interrupt Enable
 *  0b0..Disabled. The MstStStpErr interrupt is disabled.
 *  0b1..Enabled. The MstStStpErr interrupt is enabled.
 */
#define I2C_INTENSET_MSTSTSTPERREN(x)            (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK)

#define I2C_INTENSET_SLVPENDINGEN_MASK           (0x100U)
#define I2C_INTENSET_SLVPENDINGEN_SHIFT          (8U)
/*! SLVPENDINGEN - Slave Pending interrupt Enable
 *  0b0..Disabled. The SlvPending interrupt is disabled.
 *  0b1..Enabled. The SlvPending interrupt is enabled.
 */
#define I2C_INTENSET_SLVPENDINGEN(x)             (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK)

#define I2C_INTENSET_SLVNOTSTREN_MASK            (0x800U)
#define I2C_INTENSET_SLVNOTSTREN_SHIFT           (11U)
/*! SLVNOTSTREN - Slave Not Stretching interrupt Enable
 *  0b0..Disabled. The SlvNotStr interrupt is disabled.
 *  0b1..Enabled. The SlvNotStr interrupt is enabled.
 */
#define I2C_INTENSET_SLVNOTSTREN(x)              (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK)

#define I2C_INTENSET_SLVDESELEN_MASK             (0x8000U)
#define I2C_INTENSET_SLVDESELEN_SHIFT            (15U)
/*! SLVDESELEN - Slave Deselect interrupt Enable
 *  0b0..Disabled. The SlvDeSel interrupt is disabled.
 *  0b1..Enabled. The SlvDeSel interrupt is enabled.
 */
#define I2C_INTENSET_SLVDESELEN(x)               (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK)

#define I2C_INTENSET_MONRDYEN_MASK               (0x10000U)
#define I2C_INTENSET_MONRDYEN_SHIFT              (16U)
/*! MONRDYEN - Monitor data Ready interrupt Enable
 *  0b0..Disabled. The MonRdy interrupt is disabled.
 *  0b1..Enabled. The MonRdy interrupt is enabled.
 */
#define I2C_INTENSET_MONRDYEN(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK)

#define I2C_INTENSET_MONOVEN_MASK                (0x20000U)
#define I2C_INTENSET_MONOVEN_SHIFT               (17U)
/*! MONOVEN - Monitor Overrun interrupt Enable
 *  0b0..Disabled. The MonOv interrupt is disabled.
 *  0b1..Enabled. The MonOv interrupt is enabled.
 */
#define I2C_INTENSET_MONOVEN(x)                  (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK)

#define I2C_INTENSET_MONIDLEEN_MASK              (0x80000U)
#define I2C_INTENSET_MONIDLEEN_SHIFT             (19U)
/*! MONIDLEEN - Monitor Idle interrupt Enable
 *  0b0..Disabled. The MonIdle interrupt is disabled.
 *  0b1..Enabled. The MonIdle interrupt is enabled.
 */
#define I2C_INTENSET_MONIDLEEN(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK)

#define I2C_INTENSET_EVENTTIMEOUTEN_MASK         (0x1000000U)
#define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT        (24U)
/*! EVENTTIMEOUTEN - Event Time-out interrupt Enable
 *  0b0..Disabled. The Event time-out interrupt is disabled.
 *  0b1..Enabled. The Event time-out interrupt is enabled.
 */
#define I2C_INTENSET_EVENTTIMEOUTEN(x)           (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK)

#define I2C_INTENSET_SCLTIMEOUTEN_MASK           (0x2000000U)
#define I2C_INTENSET_SCLTIMEOUTEN_SHIFT          (25U)
/*! SCLTIMEOUTEN - SCL Time-out interrupt Enable
 *  0b0..Disabled. The SCL time-out interrupt is disabled.
 *  0b1..Enabled. The SCL time-out interrupt is enabled.
 */
#define I2C_INTENSET_SCLTIMEOUTEN(x)             (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK)
/*! @} */

/*! @name INTENCLR - Interrupt Enable Clear Register */
/*! @{ */

#define I2C_INTENCLR_MSTPENDINGCLR_MASK          (0x1U)
#define I2C_INTENCLR_MSTPENDINGCLR_SHIFT         (0U)
/*! MSTPENDINGCLR - Master Pending interrupt clear
 *  0b0..No effect on interrupt
 *  0b1..Clears the interrupt bit in INTENSET register
 */
#define I2C_INTENCLR_MSTPENDINGCLR(x)            (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK)

#define I2C_INTENCLR_MSTARBLOSSCLR_MASK          (0x10U)
#define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT         (4U)
/*! MSTARBLOSSCLR - Master Arbitration Loss interrupt clear
 *  0b0..No effect on interrupt
 *  0b1..Clears the interrupt bit in INTENSET register
 */
#define I2C_INTENCLR_MSTARBLOSSCLR(x)            (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK)

#define I2C_INTENCLR_MSTSTSTPERRCLR_MASK         (0x40U)
#define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT        (6U)
/*! MSTSTSTPERRCLR - Master Start/Stop Error interrupt clear
 *  0b0..No effect on interrupt
 *  0b1..Clears the interrupt bit in INTENSET register
 */
#define I2C_INTENCLR_MSTSTSTPERRCLR(x)           (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK)

#define I2C_INTENCLR_SLVPENDINGCLR_MASK          (0x100U)
#define I2C_INTENCLR_SLVPENDINGCLR_SHIFT         (8U)
/*! SLVPENDINGCLR - Slave Pending interrupt clear
 *  0b0..No effect on interrupt
 *  0b1..Clears the interrupt bit in INTENSET register
 */
#define I2C_INTENCLR_SLVPENDINGCLR(x)            (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK)

#define I2C_INTENCLR_SLVNOTSTRCLR_MASK           (0x800U)
#define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT          (11U)
/*! SLVNOTSTRCLR - Slave Not Stretching interrupt clear
 *  0b0..No effect on interrupt
 *  0b1..Clears the interrupt bit in INTENSET register
 */
#define I2C_INTENCLR_SLVNOTSTRCLR(x)             (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK)

#define I2C_INTENCLR_SLVDESELCLR_MASK            (0x8000U)
#define I2C_INTENCLR_SLVDESELCLR_SHIFT           (15U)
/*! SLVDESELCLR - Slave Deselect interrupt clear
 *  0b0..No effect on interrupt
 *  0b1..Clears the interrupt bit in INTENSET register
 */
#define I2C_INTENCLR_SLVDESELCLR(x)              (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK)

#define I2C_INTENCLR_MONRDYCLR_MASK              (0x10000U)
#define I2C_INTENCLR_MONRDYCLR_SHIFT             (16U)
/*! MONRDYCLR - Monitor data Ready interrupt clear
 *  0b0..No effect on interrupt
 *  0b1..Clears the interrupt bit in INTENSET register
 */
#define I2C_INTENCLR_MONRDYCLR(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK)

#define I2C_INTENCLR_MONOVCLR_MASK               (0x20000U)
#define I2C_INTENCLR_MONOVCLR_SHIFT              (17U)
/*! MONOVCLR - Monitor Overrun interrupt clear
 *  0b0..No effect on interrupt
 *  0b1..Clears the interrupt bit in INTENSET register
 */
#define I2C_INTENCLR_MONOVCLR(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK)

#define I2C_INTENCLR_MONIDLECLR_MASK             (0x80000U)
#define I2C_INTENCLR_MONIDLECLR_SHIFT            (19U)
/*! MONIDLECLR - Monitor Idle interrupt clear
 *  0b0..No effect on interrupt
 *  0b1..Clears the interrupt bit in INTENSET register
 */
#define I2C_INTENCLR_MONIDLECLR(x)               (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK)

#define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK        (0x1000000U)
#define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT       (24U)
/*! EVENTTIMEOUTCLR - Event time-out interrupt clear
 *  0b0..No effect on interrupt
 *  0b1..Clears the interrupt bit in INTENSET register
 */
#define I2C_INTENCLR_EVENTTIMEOUTCLR(x)          (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK)

#define I2C_INTENCLR_SCLTIMEOUTCLR_MASK          (0x2000000U)
#define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT         (25U)
/*! SCLTIMEOUTCLR - SCL time-out interrupt clear
 *  0b0..No effect on interrupt
 *  0b1..Clears the interrupt bit in INTENSET register
 */
#define I2C_INTENCLR_SCLTIMEOUTCLR(x)            (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK)
/*! @} */

/*! @name TIMEOUT - Time-out Register */
/*! @{ */

#define I2C_TIMEOUT_TOMIN_MASK                   (0xFU)
#define I2C_TIMEOUT_TOMIN_SHIFT                  (0U)
/*! TOMIN - Time-out time value, the bottom 4 bits
 */
#define I2C_TIMEOUT_TOMIN(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK)

#define I2C_TIMEOUT_TO_MASK                      (0xFFF0U)
#define I2C_TIMEOUT_TO_SHIFT                     (4U)
/*! TO - Time-out time value
 *  0b000000000000..A time-out will occur after 16 counts of the I2C function clock.
 *  0b000000000001..A time-out will occur after 32 counts of the I2C function clock.
 *  0b111111111111..A time-out will occur after 65,536 counts of the I2C function clock.
 */
#define I2C_TIMEOUT_TO(x)                        (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK)
/*! @} */

/*! @name CLKDIV - Clock Divider Register */
/*! @{ */

#define I2C_CLKDIV_DIVVAL_MASK                   (0xFFFFU)
#define I2C_CLKDIV_DIVVAL_SHIFT                  (0U)
/*! DIVVAL - Divider Value
 *  0b0000000000000000..FCLK is used directly by the I2C.
 *  0b0000000000000001..FCLK is divided by 2 before being used by the I2C.
 *  0b0000000000000010..FCLK is divided by 3 before being used by the I2C.
 *  0b1111111111111111..FCLK is divided by 65,536 before being used by the I2C.
 */
#define I2C_CLKDIV_DIVVAL(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK)
/*! @} */

/*! @name INTSTAT - Interrupt Status Register */
/*! @{ */

#define I2C_INTSTAT_MSTPENDING_MASK              (0x1U)
#define I2C_INTSTAT_MSTPENDING_SHIFT             (0U)
/*! MSTPENDING - Master Pending
 *  0b0..Not active
 *  0b1..Active
 */
#define I2C_INTSTAT_MSTPENDING(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK)

#define I2C_INTSTAT_MSTARBLOSS_MASK              (0x10U)
#define I2C_INTSTAT_MSTARBLOSS_SHIFT             (4U)
/*! MSTARBLOSS - Master Arbitration Loss flag
 *  0b0..Not active
 *  0b1..Active
 */
#define I2C_INTSTAT_MSTARBLOSS(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK)

#define I2C_INTSTAT_MSTSTSTPERR_MASK             (0x40U)
#define I2C_INTSTAT_MSTSTSTPERR_SHIFT            (6U)
/*! MSTSTSTPERR - Master Start/Stop Error flag
 *  0b0..Not active
 *  0b1..Active
 */
#define I2C_INTSTAT_MSTSTSTPERR(x)               (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK)

#define I2C_INTSTAT_SLVPENDING_MASK              (0x100U)
#define I2C_INTSTAT_SLVPENDING_SHIFT             (8U)
/*! SLVPENDING - Slave Pending
 *  0b0..Not active
 *  0b1..Active
 */
#define I2C_INTSTAT_SLVPENDING(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK)

#define I2C_INTSTAT_SLVNOTSTR_MASK               (0x800U)
#define I2C_INTSTAT_SLVNOTSTR_SHIFT              (11U)
/*! SLVNOTSTR - Slave Not Stretching status
 *  0b0..Not active
 *  0b1..Active
 */
#define I2C_INTSTAT_SLVNOTSTR(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK)

#define I2C_INTSTAT_SLVDESEL_MASK                (0x8000U)
#define I2C_INTSTAT_SLVDESEL_SHIFT               (15U)
/*! SLVDESEL - Slave Deselected flag
 *  0b0..Not active
 *  0b1..Active
 */
#define I2C_INTSTAT_SLVDESEL(x)                  (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK)

#define I2C_INTSTAT_MONRDY_MASK                  (0x10000U)
#define I2C_INTSTAT_MONRDY_SHIFT                 (16U)
/*! MONRDY - Monitor Ready
 *  0b0..Not active
 *  0b1..Active
 */
#define I2C_INTSTAT_MONRDY(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK)

#define I2C_INTSTAT_MONOV_MASK                   (0x20000U)
#define I2C_INTSTAT_MONOV_SHIFT                  (17U)
/*! MONOV - Monitor Overflow flag
 *  0b0..Not active
 *  0b1..Active
 */
#define I2C_INTSTAT_MONOV(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK)

#define I2C_INTSTAT_MONIDLE_MASK                 (0x80000U)
#define I2C_INTSTAT_MONIDLE_SHIFT                (19U)
/*! MONIDLE - Monitor Idle flag
 *  0b0..Not active
 *  0b1..Active
 */
#define I2C_INTSTAT_MONIDLE(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK)

#define I2C_INTSTAT_EVENTTIMEOUT_MASK            (0x1000000U)
#define I2C_INTSTAT_EVENTTIMEOUT_SHIFT           (24U)
/*! EVENTTIMEOUT - Event Time-out Interrupt flag
 *  0b0..Not active
 *  0b1..Active
 */
#define I2C_INTSTAT_EVENTTIMEOUT(x)              (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK)

#define I2C_INTSTAT_SCLTIMEOUT_MASK              (0x2000000U)
#define I2C_INTSTAT_SCLTIMEOUT_SHIFT             (25U)
/*! SCLTIMEOUT - SCL Time-out Interrupt flag
 *  0b0..Not active
 *  0b1..Active
 */
#define I2C_INTSTAT_SCLTIMEOUT(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK)
/*! @} */

/*! @name MSTCTL - Master Control Register */
/*! @{ */

#define I2C_MSTCTL_MSTCONTINUE_MASK              (0x1U)
#define I2C_MSTCTL_MSTCONTINUE_SHIFT             (0U)
/*! MSTCONTINUE - Master Continue(write-only)
 *  0b0..No effect
 *  0b1..Continue. Informs the Master function to continue to the next operation. This action must done after
 *       writing transmit data, reading received data, or any other housekeeping related to the next bus operation.
 */
#define I2C_MSTCTL_MSTCONTINUE(x)                (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK)

#define I2C_MSTCTL_MSTSTART_MASK                 (0x2U)
#define I2C_MSTCTL_MSTSTART_SHIFT                (1U)
/*! MSTSTART - Master Start control(write-only)
 *  0b0..No effect
 *  0b1..Start. A Start will be generated on the I2C bus at the next allowed time.
 */
#define I2C_MSTCTL_MSTSTART(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK)

#define I2C_MSTCTL_MSTSTOP_MASK                  (0x4U)
#define I2C_MSTCTL_MSTSTOP_SHIFT                 (2U)
/*! MSTSTOP - Master Stop control(write-only)
 *  0b0..No effect
 *  0b1..Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave
 *       if the master is receiving data from the slave (in Master Receiver mode).
 */
#define I2C_MSTCTL_MSTSTOP(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK)

#define I2C_MSTCTL_MSTDMA_MASK                   (0x8U)
#define I2C_MSTCTL_MSTDMA_SHIFT                  (3U)
/*! MSTDMA - Master DMA enable
 *  0b0..Disable. No DMA requests are generated for master operation.
 *  0b1..Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating
 *       Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically.
 */
#define I2C_MSTCTL_MSTDMA(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK)
/*! @} */

/*! @name MSTTIME - Master Timing Register */
/*! @{ */

#define I2C_MSTTIME_MSTSCLLOW_MASK               (0x7U)
#define I2C_MSTTIME_MSTSCLLOW_SHIFT              (0U)
/*! MSTSCLLOW - Master SCL Low time
 *  0b000..2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider.
 *  0b001..3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider.
 *  0b010..4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider.
 *  0b011..5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider.
 *  0b100..6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider.
 *  0b101..7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider.
 *  0b110..8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider.
 *  0b111..9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider.
 */
#define I2C_MSTTIME_MSTSCLLOW(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK)

#define I2C_MSTTIME_MSTSCLHIGH_MASK              (0x70U)
#define I2C_MSTTIME_MSTSCLHIGH_SHIFT             (4U)
/*! MSTSCLHIGH - Master SCL High time
 *  0b000..2 clocks. Minimum SCL high time is 2 clocks of the I2C clock pre-divider.
 *  0b001..3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider .
 *  0b010..4 clocks. Minimum SCL high time is 4 clocks of the I2C clock pre-divider.
 *  0b011..5 clocks. Minimum SCL high time is 5 clocks of the I2C clock pre-divider.
 *  0b100..6 clocks. Minimum SCL high time is 6 clocks of the I2C clock pre-divider.
 *  0b101..7 clocks. Minimum SCL high time is 7 clocks of the I2C clock pre-divider.
 *  0b110..8 clocks. Minimum SCL high time is 8 clocks of the I2C clock pre-divider.
 *  0b111..9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider.
 */
#define I2C_MSTTIME_MSTSCLHIGH(x)                (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK)
/*! @} */

/*! @name MSTDAT - Master Data Register */
/*! @{ */

#define I2C_MSTDAT_DATA_MASK                     (0xFFU)
#define I2C_MSTDAT_DATA_SHIFT                    (0U)
/*! DATA - Master function data register
 */
#define I2C_MSTDAT_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK)
/*! @} */

/*! @name SLVCTL - Slave Control Register */
/*! @{ */

#define I2C_SLVCTL_SLVCONTINUE_MASK              (0x1U)
#define I2C_SLVCTL_SLVCONTINUE_SHIFT             (0U)
/*! SLVCONTINUE - Slave Continue
 *  0b0..No effect
 *  0b1..Continue. Informs the Slave function to continue to the next operation, by clearing the STAT[SLVPENDING]
 *       flag. This must be done after writing transmit data, reading received data, or any other housekeeping
 *       related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE should not be
 *       set unless SLVPENDING = 1.
 */
#define I2C_SLVCTL_SLVCONTINUE(x)                (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK)

#define I2C_SLVCTL_SLVNACK_MASK                  (0x2U)
#define I2C_SLVCTL_SLVNACK_SHIFT                 (1U)
/*! SLVNACK - Slave NACK
 *  0b0..No effect
 *  0b1..NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (in Slave Receiver mode).
 */
#define I2C_SLVCTL_SLVNACK(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK)

#define I2C_SLVCTL_SLVDMA_MASK                   (0x8U)
#define I2C_SLVCTL_SLVDMA_SHIFT                  (3U)
/*! SLVDMA - Slave DMA enable
 *  0b0..Disabled. No DMA requests are issued for Slave mode operation.
 *  0b1..Enabled. DMA requests are issued for I2C slave data transmission and reception.
 */
#define I2C_SLVCTL_SLVDMA(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK)

#define I2C_SLVCTL_AUTOACK_MASK                  (0x100U)
#define I2C_SLVCTL_AUTOACK_SHIFT                 (8U)
/*! AUTOACK - Automatic Acknowledge
 *  0b0..Normal, non-automatic operation. If AUTONACK = 0, then a SlvPending interrupt is generated when a
 *       matching address is received. If AUTONACK = 1, then received addresses are NACKed (ignored).
 *  0b1..A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately,
 *       allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does
 *       not match AUTOMATCHREAD, then the behavior will depend on the SLVADR0[AUTONACK] bit: if AUTONACK is set,
 *       then it will be Nacked; if AUTONACK is clear, then a SlvPending interrupt is generated.
 */
#define I2C_SLVCTL_AUTOACK(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOACK_SHIFT)) & I2C_SLVCTL_AUTOACK_MASK)

#define I2C_SLVCTL_AUTOMATCHREAD_MASK            (0x200U)
#define I2C_SLVCTL_AUTOMATCHREAD_SHIFT           (9U)
/*! AUTOMATCHREAD - Automatic Match Read
 *  0b0..In Automatic Mode, the expected next operation is an I2C write.
 *  0b1..In Automatic Mode, the expected next operation is an I2C read.
 */
#define I2C_SLVCTL_AUTOMATCHREAD(x)              (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOMATCHREAD_SHIFT)) & I2C_SLVCTL_AUTOMATCHREAD_MASK)
/*! @} */

/*! @name SLVDAT - Slave Data Register */
/*! @{ */

#define I2C_SLVDAT_DATA_MASK                     (0xFFU)
#define I2C_SLVDAT_DATA_SHIFT                    (0U)
/*! DATA - Slave function data register
 */
#define I2C_SLVDAT_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK)
/*! @} */

/*! @name SLVADR - Slave Address Register */
/*! @{ */

#define I2C_SLVADR_SADISABLE_MASK                (0x1U)
#define I2C_SLVADR_SADISABLE_SHIFT               (0U)
/*! SADISABLE - Slave Address n Disable
 *  0b0..Enabled. Slave Address n is enabled.
 *  0b1..Ignored. Slave Address n is ignored.
 */
#define I2C_SLVADR_SADISABLE(x)                  (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK)

#define I2C_SLVADR_SLVADR_MASK                   (0xFEU)
#define I2C_SLVADR_SLVADR_SHIFT                  (1U)
/*! SLVADR - Slave Address.
 */
#define I2C_SLVADR_SLVADR(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK)

#define I2C_SLVADR_AUTONACK_MASK                 (0x8000U)
#define I2C_SLVADR_AUTONACK_SHIFT                (15U)
/*! AUTONACK - Automatic NACK operation
 *  0b0..Normal operation, matching I2C addresses are not ignored.
 *  0b1..Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, and the address
 *       matches SLVADRn, and AUTOMATCHREAD matches the direction.
 */
#define I2C_SLVADR_AUTONACK(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_AUTONACK_SHIFT)) & I2C_SLVADR_AUTONACK_MASK)
/*! @} */

/* The count of I2C_SLVADR */
#define I2C_SLVADR_COUNT                         (4U)

/*! @name SLVQUAL0 - Slave Qualification for Address 0 Register */
/*! @{ */

#define I2C_SLVQUAL0_QUALMODE0_MASK              (0x1U)
#define I2C_SLVQUAL0_QUALMODE0_SHIFT             (0U)
/*! QUALMODE0 - Qualify mode for slave address 0
 *  0b0..Mask. The SLVQUAL0 field is used as a logical mask for matching address 0.
 *  0b1..Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses.
 */
#define I2C_SLVQUAL0_QUALMODE0(x)                (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK)

#define I2C_SLVQUAL0_SLVQUAL0_MASK               (0xFEU)
#define I2C_SLVQUAL0_SLVQUAL0_SHIFT              (1U)
/*! SLVQUAL0 - Slave address Qualifier for address 0
 */
#define I2C_SLVQUAL0_SLVQUAL0(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK)
/*! @} */

/*! @name MONRXDAT - Monitor Receiver Data Register */
/*! @{ */

#define I2C_MONRXDAT_MONRXDAT_MASK               (0xFFU)
#define I2C_MONRXDAT_MONRXDAT_SHIFT              (0U)
/*! MONRXDAT - Monitor function Receiver Data
 */
#define I2C_MONRXDAT_MONRXDAT(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK)

#define I2C_MONRXDAT_MONSTART_MASK               (0x100U)
#define I2C_MONRXDAT_MONSTART_SHIFT              (8U)
/*! MONSTART - Monitor Received Start
 *  0b0..No start detected. The Monitor function has not detected a Start event on the I2C bus.
 *  0b1..Start detected. The Monitor function has detected a Start event on the I2C bus.
 */
#define I2C_MONRXDAT_MONSTART(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK)

#define I2C_MONRXDAT_MONRESTART_MASK             (0x200U)
#define I2C_MONRXDAT_MONRESTART_SHIFT            (9U)
/*! MONRESTART - Monitor Received Repeated Start
 *  0b0..No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus.
 *  0b1..Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus.
 */
#define I2C_MONRXDAT_MONRESTART(x)               (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK)

#define I2C_MONRXDAT_MONNACK_MASK                (0x400U)
#define I2C_MONRXDAT_MONNACK_SHIFT               (10U)
/*! MONNACK - Monitor Received NACK
 *  0b0..Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver.
 *  0b1..Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver.
 */
#define I2C_MONRXDAT_MONNACK(x)                  (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK)
/*! @} */

/*! @name ID - Peripheral Identification Register */
/*! @{ */

#define I2C_ID_APERTURE_MASK                     (0xFFU)
#define I2C_ID_APERTURE_SHIFT                    (0U)
/*! APERTURE - Aperture
 */
#define I2C_ID_APERTURE(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_ID_APERTURE_SHIFT)) & I2C_ID_APERTURE_MASK)

#define I2C_ID_MINOR_REV_MASK                    (0xF00U)
#define I2C_ID_MINOR_REV_SHIFT                   (8U)
/*! MINOR_REV - Minor revision of module implementation
 */
#define I2C_ID_MINOR_REV(x)                      (((uint32_t)(((uint32_t)(x)) << I2C_ID_MINOR_REV_SHIFT)) & I2C_ID_MINOR_REV_MASK)

#define I2C_ID_MAJOR_REV_MASK                    (0xF000U)
#define I2C_ID_MAJOR_REV_SHIFT                   (12U)
/*! MAJOR_REV - Major revision of module implementation
 */
#define I2C_ID_MAJOR_REV(x)                      (((uint32_t)(((uint32_t)(x)) << I2C_ID_MAJOR_REV_SHIFT)) & I2C_ID_MAJOR_REV_MASK)

#define I2C_ID_ID_MASK                           (0xFFFF0000U)
#define I2C_ID_ID_SHIFT                          (16U)
/*! ID - Module identifier for the selected function
 */
#define I2C_ID_ID(x)                             (((uint32_t)(((uint32_t)(x)) << I2C_ID_ID_SHIFT)) & I2C_ID_ID_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group I2C_Register_Masks */


/* I2C - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral I2C0 base address */
  #define I2C0_BASE                                (0x50086000u)
  /** Peripheral I2C0 base address */
  #define I2C0_BASE_NS                             (0x40086000u)
  /** Peripheral I2C0 base pointer */
  #define I2C0                                     ((I2C_Type *)I2C0_BASE)
  /** Peripheral I2C0 base pointer */
  #define I2C0_NS                                  ((I2C_Type *)I2C0_BASE_NS)
  /** Peripheral I2C1 base address */
  #define I2C1_BASE                                (0x50087000u)
  /** Peripheral I2C1 base address */
  #define I2C1_BASE_NS                             (0x40087000u)
  /** Peripheral I2C1 base pointer */
  #define I2C1                                     ((I2C_Type *)I2C1_BASE)
  /** Peripheral I2C1 base pointer */
  #define I2C1_NS                                  ((I2C_Type *)I2C1_BASE_NS)
  /** Peripheral I2C2 base address */
  #define I2C2_BASE                                (0x50088000u)
  /** Peripheral I2C2 base address */
  #define I2C2_BASE_NS                             (0x40088000u)
  /** Peripheral I2C2 base pointer */
  #define I2C2                                     ((I2C_Type *)I2C2_BASE)
  /** Peripheral I2C2 base pointer */
  #define I2C2_NS                                  ((I2C_Type *)I2C2_BASE_NS)
  /** Peripheral I2C3 base address */
  #define I2C3_BASE                                (0x50089000u)
  /** Peripheral I2C3 base address */
  #define I2C3_BASE_NS                             (0x40089000u)
  /** Peripheral I2C3 base pointer */
  #define I2C3                                     ((I2C_Type *)I2C3_BASE)
  /** Peripheral I2C3 base pointer */
  #define I2C3_NS                                  ((I2C_Type *)I2C3_BASE_NS)
  /** Peripheral I2C4 base address */
  #define I2C4_BASE                                (0x5008A000u)
  /** Peripheral I2C4 base address */
  #define I2C4_BASE_NS                             (0x4008A000u)
  /** Peripheral I2C4 base pointer */
  #define I2C4                                     ((I2C_Type *)I2C4_BASE)
  /** Peripheral I2C4 base pointer */
  #define I2C4_NS                                  ((I2C_Type *)I2C4_BASE_NS)
  /** Peripheral I2C5 base address */
  #define I2C5_BASE                                (0x50096000u)
  /** Peripheral I2C5 base address */
  #define I2C5_BASE_NS                             (0x40096000u)
  /** Peripheral I2C5 base pointer */
  #define I2C5                                     ((I2C_Type *)I2C5_BASE)
  /** Peripheral I2C5 base pointer */
  #define I2C5_NS                                  ((I2C_Type *)I2C5_BASE_NS)
  /** Peripheral I2C6 base address */
  #define I2C6_BASE                                (0x50097000u)
  /** Peripheral I2C6 base address */
  #define I2C6_BASE_NS                             (0x40097000u)
  /** Peripheral I2C6 base pointer */
  #define I2C6                                     ((I2C_Type *)I2C6_BASE)
  /** Peripheral I2C6 base pointer */
  #define I2C6_NS                                  ((I2C_Type *)I2C6_BASE_NS)
  /** Peripheral I2C7 base address */
  #define I2C7_BASE                                (0x50098000u)
  /** Peripheral I2C7 base address */
  #define I2C7_BASE_NS                             (0x40098000u)
  /** Peripheral I2C7 base pointer */
  #define I2C7                                     ((I2C_Type *)I2C7_BASE)
  /** Peripheral I2C7 base pointer */
  #define I2C7_NS                                  ((I2C_Type *)I2C7_BASE_NS)
  /** Array initializer of I2C peripheral base addresses */
  #define I2C_BASE_ADDRS                           { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE }
  /** Array initializer of I2C peripheral base pointers */
  #define I2C_BASE_PTRS                            { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 }
  /** Array initializer of I2C peripheral base addresses */
  #define I2C_BASE_ADDRS_NS                        { I2C0_BASE_NS, I2C1_BASE_NS, I2C2_BASE_NS, I2C3_BASE_NS, I2C4_BASE_NS, I2C5_BASE_NS, I2C6_BASE_NS, I2C7_BASE_NS }
  /** Array initializer of I2C peripheral base pointers */
  #define I2C_BASE_PTRS_NS                         { I2C0_NS, I2C1_NS, I2C2_NS, I2C3_NS, I2C4_NS, I2C5_NS, I2C6_NS, I2C7_NS }
#else
  /** Peripheral I2C0 base address */
  #define I2C0_BASE                                (0x40086000u)
  /** Peripheral I2C0 base pointer */
  #define I2C0                                     ((I2C_Type *)I2C0_BASE)
  /** Peripheral I2C1 base address */
  #define I2C1_BASE                                (0x40087000u)
  /** Peripheral I2C1 base pointer */
  #define I2C1                                     ((I2C_Type *)I2C1_BASE)
  /** Peripheral I2C2 base address */
  #define I2C2_BASE                                (0x40088000u)
  /** Peripheral I2C2 base pointer */
  #define I2C2                                     ((I2C_Type *)I2C2_BASE)
  /** Peripheral I2C3 base address */
  #define I2C3_BASE                                (0x40089000u)
  /** Peripheral I2C3 base pointer */
  #define I2C3                                     ((I2C_Type *)I2C3_BASE)
  /** Peripheral I2C4 base address */
  #define I2C4_BASE                                (0x4008A000u)
  /** Peripheral I2C4 base pointer */
  #define I2C4                                     ((I2C_Type *)I2C4_BASE)
  /** Peripheral I2C5 base address */
  #define I2C5_BASE                                (0x40096000u)
  /** Peripheral I2C5 base pointer */
  #define I2C5                                     ((I2C_Type *)I2C5_BASE)
  /** Peripheral I2C6 base address */
  #define I2C6_BASE                                (0x40097000u)
  /** Peripheral I2C6 base pointer */
  #define I2C6                                     ((I2C_Type *)I2C6_BASE)
  /** Peripheral I2C7 base address */
  #define I2C7_BASE                                (0x40098000u)
  /** Peripheral I2C7 base pointer */
  #define I2C7                                     ((I2C_Type *)I2C7_BASE)
  /** Array initializer of I2C peripheral base addresses */
  #define I2C_BASE_ADDRS                           { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE }
  /** Array initializer of I2C peripheral base pointers */
  #define I2C_BASE_PTRS                            { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 }
#endif
/** Interrupt vectors for the I2C peripheral type */
#define I2C_IRQS                                 { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn }

/*!
 * @}
 */ /* end of group I2C_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- I2S Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
 * @{
 */

/** I2S - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[3072];
  __IO uint32_t CFG1;                              /**< Configuration Register 1 for the Primary Channel Pair, offset: 0xC00 */
  __IO uint32_t CFG2;                              /**< Configuration Register 2 for the Primary Channel Pair, offset: 0xC04 */
  __IO uint32_t STAT;                              /**< Status Register for the Primary Channel Pair, offset: 0xC08 */
       uint8_t RESERVED_1[16];
  __IO uint32_t DIV;                               /**< Clock Divider, offset: 0xC1C */
  struct {                                         /* offset: 0xC20, array step: 0x20 */
    __IO uint32_t PCFG1;                             /**< Configuration Register 1 for Channel Pair 1..Configuration Register 1 for Channel Pair 3, array offset: 0xC20, array step: 0x20 */
    __IO uint32_t PCFG2;                             /**< Configuration Register 2 for Channel Pair 1..Configuration Register 2 for Channel Pair 3, array offset: 0xC24, array step: 0x20 */
    __I  uint32_t PSTAT;                             /**< Status Register for Channel Pair 1..Status Register for Channel Pair 3, array offset: 0xC28, array step: 0x20 */
         uint8_t RESERVED_0[20];
  } SECCHANNEL[3];
       uint8_t RESERVED_2[384];
  __IO uint32_t FIFOCFG;                           /**< FIFO Configuration and Enable, offset: 0xE00 */
  __IO uint32_t FIFOSTAT;                          /**< FIFO Status, offset: 0xE04 */
  __IO uint32_t FIFOTRIG;                          /**< FIFO Trigger Settings, offset: 0xE08 */
       uint8_t RESERVED_3[4];
  __IO uint32_t FIFOINTENSET;                      /**< FIFO Interrupt Enable Set and Read, offset: 0xE10 */
  __IO uint32_t FIFOINTENCLR;                      /**< FIFO Interrupt Enable Clear and Read, offset: 0xE14 */
  __I  uint32_t FIFOINTSTAT;                       /**< FIFO Interrupt Status, offset: 0xE18 */
       uint8_t RESERVED_4[4];
  __O  uint32_t FIFOWR;                            /**< FIFO Write Data, offset: 0xE20 */
  __O  uint32_t FIFOWR48H;                         /**< FIFO Write Data for Upper Data Bits, offset: 0xE24 */
       uint8_t RESERVED_5[8];
  __I  uint32_t FIFORD;                            /**< FIFO Read Data, offset: 0xE30 */
  __I  uint32_t FIFORD48H;                         /**< FIFO Read Data for Upper Data Bits, offset: 0xE34 */
       uint8_t RESERVED_6[8];
  __I  uint32_t FIFORDNOPOP;                       /**< FIFO Data Read with No FIFO Pop, offset: 0xE40 */
  __I  uint32_t FIFORD48HNOPOP;                    /**< FIFO Data Read for Upper Data Bits with No FIFO Pop, offset: 0xE44 */
  __I  uint32_t FIFOSIZE;                          /**< FIFO Size Register, offset: 0xE48 */
  __IO uint32_t FIFORXTIMEOUTCFG;                  /**< FIFO Receive Timeout Configuration, offset: 0xE4C */
  __I  uint32_t FIFORXTIMEOUTCNT;                  /**< FIFO Receive Timeout Counter, offset: 0xE50 */
       uint8_t RESERVED_7[424];
  __I  uint32_t ID;                                /**< I2S Module Identification, offset: 0xFFC */
} I2S_Type;

/* ----------------------------------------------------------------------------
   -- I2S Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup I2S_Register_Masks I2S Register Masks
 * @{
 */

/*! @name CFG1 - Configuration Register 1 for the Primary Channel Pair */
/*! @{ */

#define I2S_CFG1_MAINENABLE_MASK                 (0x1U)
#define I2S_CFG1_MAINENABLE_SHIFT                (0U)
/*! MAINENABLE - Main Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define I2S_CFG1_MAINENABLE(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MAINENABLE_SHIFT)) & I2S_CFG1_MAINENABLE_MASK)

#define I2S_CFG1_DATAPAUSE_MASK                  (0x2U)
#define I2S_CFG1_DATAPAUSE_SHIFT                 (1U)
/*! DATAPAUSE - Data Flow Pause
 *  0b0..Normal operation
 *  0b1..Pause
 */
#define I2S_CFG1_DATAPAUSE(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATAPAUSE_SHIFT)) & I2S_CFG1_DATAPAUSE_MASK)

#define I2S_CFG1_PAIRCOUNT_MASK                  (0xCU)
#define I2S_CFG1_PAIRCOUNT_SHIFT                 (2U)
/*! PAIRCOUNT - Pair Count
 *  0b00..One Pair
 *  0b01..Two Pairs
 *  0b10..Three Pairs
 *  0b11..Four Pairs
 */
#define I2S_CFG1_PAIRCOUNT(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PAIRCOUNT_SHIFT)) & I2S_CFG1_PAIRCOUNT_MASK)

#define I2S_CFG1_MSTSLVCFG_MASK                  (0x30U)
#define I2S_CFG1_MSTSLVCFG_SHIFT                 (4U)
/*! MSTSLVCFG - Master/Slave Configuration Selection
 *  0b00..Normal Slave Mode
 *  0b01..WS Synchronized Master Mode
 *  0b10..Master Using an Existing SCK Mode
 *  0b11..Normal Master Mode
 */
#define I2S_CFG1_MSTSLVCFG(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MSTSLVCFG_SHIFT)) & I2S_CFG1_MSTSLVCFG_MASK)

#define I2S_CFG1_MODE_MASK                       (0xC0U)
#define I2S_CFG1_MODE_SHIFT                      (6U)
/*! MODE - Mode
 *  0b00..Classic Mode
 *  0b01..DSP mode WS 50% duty cycle
 *  0b10..DSP mode WS 1 clock
 *  0b11..DSP mode WS 1 data
 */
#define I2S_CFG1_MODE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MODE_SHIFT)) & I2S_CFG1_MODE_MASK)

#define I2S_CFG1_RIGHTLOW_MASK                   (0x100U)
#define I2S_CFG1_RIGHTLOW_SHIFT                  (8U)
/*! RIGHTLOW - Right Channel Low
 *  0b0..Right high
 *  0b1..Right low
 */
#define I2S_CFG1_RIGHTLOW(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_RIGHTLOW_SHIFT)) & I2S_CFG1_RIGHTLOW_MASK)

#define I2S_CFG1_LEFTJUST_MASK                   (0x200U)
#define I2S_CFG1_LEFTJUST_SHIFT                  (9U)
/*! LEFTJUST - Left-Justify Data
 *  0b0..Right-justified
 *  0b1..Left-justified
 */
#define I2S_CFG1_LEFTJUST(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_LEFTJUST_SHIFT)) & I2S_CFG1_LEFTJUST_MASK)

#define I2S_CFG1_ONECHANNEL_MASK                 (0x400U)
#define I2S_CFG1_ONECHANNEL_SHIFT                (10U)
/*! ONECHANNEL - Single Channel Mode
 *  0b0..Dual channel
 *  0b1..Single channel
 */
#define I2S_CFG1_ONECHANNEL(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK)

#define I2S_CFG1_PDMDATA_MASK                    (0x800U)
#define I2S_CFG1_PDMDATA_SHIFT                   (11U)
/*! PDMDATA - PDM Data Selection
 *  0b0..Normal Operation
 *  0b1..DMIC subsystem
 */
#define I2S_CFG1_PDMDATA(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PDMDATA_SHIFT)) & I2S_CFG1_PDMDATA_MASK)

#define I2S_CFG1_SCK_POL_MASK                    (0x1000U)
#define I2S_CFG1_SCK_POL_SHIFT                   (12U)
/*! SCK_POL - SCK Polarity
 *  0b0..Falling edge
 *  0b1..Rising edge
 */
#define I2S_CFG1_SCK_POL(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_SCK_POL_SHIFT)) & I2S_CFG1_SCK_POL_MASK)

#define I2S_CFG1_WS_POL_MASK                     (0x2000U)
#define I2S_CFG1_WS_POL_SHIFT                    (13U)
/*! WS_POL - WS Polarity
 *  0b0..Not inverted
 *  0b1..Inverted
 */
#define I2S_CFG1_WS_POL(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_WS_POL_SHIFT)) & I2S_CFG1_WS_POL_MASK)

#define I2S_CFG1_DATALEN_MASK                    (0x1F0000U)
#define I2S_CFG1_DATALEN_SHIFT                   (16U)
/*! DATALEN - Data Length
 *  0b00011..Data is 4 bits in length.
 *  0b00100..Data is 5 bits in length.
 *  0b00111..Data is 8 bits in length.
 *  0b11110..Data is 31 bits in length.
 *  0b11111..Data is 32 bits in length.
 */
#define I2S_CFG1_DATALEN(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATALEN_SHIFT)) & I2S_CFG1_DATALEN_MASK)
/*! @} */

/*! @name CFG2 - Configuration Register 2 for the Primary Channel Pair */
/*! @{ */

#define I2S_CFG2_FRAMELEN_MASK                   (0x7FFU)
#define I2S_CFG2_FRAMELEN_SHIFT                  (0U)
/*! FRAMELEN - Frame Length
 *  0b00000000011..Frame is 4 bits in total length
 *  0b00000000100..Frame is 5 bits in total length
 *  0b00111111111..Frame is 512 bits in total length
 *  0b11111111111..Frame is 2048 bits in total length
 */
#define I2S_CFG2_FRAMELEN(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_FRAMELEN_SHIFT)) & I2S_CFG2_FRAMELEN_MASK)

#define I2S_CFG2_POSITION_MASK                   (0x7FF0000U)
#define I2S_CFG2_POSITION_SHIFT                  (16U)
/*! POSITION - Data Position
 *  0b00000000000..Data begins at bit position 0 (the first bit position) within the frame or WS phase
 *  0b00000000001..Data begins at bit position 1 within the frame or WS phase
 *  0b00000000010..Data begins at bit position 2 within the frame or WS phase
 */
#define I2S_CFG2_POSITION(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_POSITION_SHIFT)) & I2S_CFG2_POSITION_MASK)
/*! @} */

/*! @name STAT - Status Register for the Primary Channel Pair */
/*! @{ */

#define I2S_STAT_BUSY_MASK                       (0x1U)
#define I2S_STAT_BUSY_SHIFT                      (0U)
/*! BUSY - Busy Status
 *  0b0..Idle
 *  0b1..Busy
 */
#define I2S_STAT_BUSY(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_STAT_BUSY_SHIFT)) & I2S_STAT_BUSY_MASK)

#define I2S_STAT_SLVFRMERR_MASK                  (0x2U)
#define I2S_STAT_SLVFRMERR_SHIFT                 (1U)
/*! SLVFRMERR - Slave Frame Error
 *  0b0..No error
 *  0b1..Error
 */
#define I2S_STAT_SLVFRMERR(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_STAT_SLVFRMERR_SHIFT)) & I2S_STAT_SLVFRMERR_MASK)

#define I2S_STAT_LR_MASK                         (0x4U)
#define I2S_STAT_LR_SHIFT                        (2U)
/*! LR - Left/Right Indication
 *  0b0..Left channel
 *  0b1..Right channel
 */
#define I2S_STAT_LR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_STAT_LR_SHIFT)) & I2S_STAT_LR_MASK)

#define I2S_STAT_DATAPAUSED_MASK                 (0x8U)
#define I2S_STAT_DATAPAUSED_SHIFT                (3U)
/*! DATAPAUSED - Data Paused
 *  0b0..Not Paused
 *  0b1..Paused
 */
#define I2S_STAT_DATAPAUSED(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_STAT_DATAPAUSED_SHIFT)) & I2S_STAT_DATAPAUSED_MASK)
/*! @} */

/*! @name DIV - Clock Divider */
/*! @{ */

#define I2S_DIV_DIV_MASK                         (0xFFFU)
#define I2S_DIV_DIV_SHIFT                        (0U)
/*! DIV - Divider
 *  0b000000000000..FCLK is used directly.
 *  0b000000000001..FCLK is divided by 2.
 *  0b000000000010..FCLK is divided by 3.
 *  0b111111111111..FCLK is divided by 4,096.
 */
#define I2S_DIV_DIV(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_DIV_DIV_SHIFT)) & I2S_DIV_DIV_MASK)
/*! @} */

/*! @name SECCHANNEL_PCFG1 - Configuration Register 1 for Channel Pair 1..Configuration Register 1 for Channel Pair 3 */
/*! @{ */

#define I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK     (0x1U)
#define I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT    (0U)
/*! PAIRENABLE - Pair Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define I2S_SECCHANNEL_PCFG1_PAIRENABLE(x)       (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT)) & I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK)

#define I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK     (0x400U)
#define I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT    (10U)
/*! ONECHANNEL - Single Channel Mode
 *  0b0..Dual Channel
 *  0b1..Single Channel
 */
#define I2S_SECCHANNEL_PCFG1_ONECHANNEL(x)       (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT)) & I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK)
/*! @} */

/* The count of I2S_SECCHANNEL_PCFG1 */
#define I2S_SECCHANNEL_PCFG1_COUNT               (3U)

/*! @name SECCHANNEL_PCFG2 - Configuration Register 2 for Channel Pair 1..Configuration Register 2 for Channel Pair 3 */
/*! @{ */

#define I2S_SECCHANNEL_PCFG2_POSITION_MASK       (0x1FF0000U)
#define I2S_SECCHANNEL_PCFG2_POSITION_SHIFT      (16U)
/*! POSITION - Data Position
 */
#define I2S_SECCHANNEL_PCFG2_POSITION(x)         (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG2_POSITION_SHIFT)) & I2S_SECCHANNEL_PCFG2_POSITION_MASK)
/*! @} */

/* The count of I2S_SECCHANNEL_PCFG2 */
#define I2S_SECCHANNEL_PCFG2_COUNT               (3U)

/*! @name SECCHANNEL_PSTAT - Status Register for Channel Pair 1..Status Register for Channel Pair 3 */
/*! @{ */

#define I2S_SECCHANNEL_PSTAT_BUSY_MASK           (0x1U)
#define I2S_SECCHANNEL_PSTAT_BUSY_SHIFT          (0U)
/*! BUSY - Busy Status for Channel Pair
 *  0b0..Idle. The transmitter/receiver for this channel pair is currently idle.
 *  0b1..Busy. The transmitter/receiver for this channel pair is currently processing data.
 */
#define I2S_SECCHANNEL_PSTAT_BUSY(x)             (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_BUSY_SHIFT)) & I2S_SECCHANNEL_PSTAT_BUSY_MASK)

#define I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK      (0x2U)
#define I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT     (1U)
/*! SLVFRMERR - Save Frame Error Flag
 *  0b0..No Error
 *  0b1..Error
 */
#define I2S_SECCHANNEL_PSTAT_SLVFRMERR(x)        (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT)) & I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK)

#define I2S_SECCHANNEL_PSTAT_LR_MASK             (0x4U)
#define I2S_SECCHANNEL_PSTAT_LR_SHIFT            (2U)
/*! LR - Left/Right Indication
 *  0b0..Left channel
 *  0b1..Right channel
 */
#define I2S_SECCHANNEL_PSTAT_LR(x)               (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_LR_SHIFT)) & I2S_SECCHANNEL_PSTAT_LR_MASK)

#define I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK     (0x8U)
#define I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT    (3U)
/*! DATAPAUSED - Data Paused Status Flag
 *  0b0..Data Not Paused. Data is not currently paused. A data pause may have been requested but is not yet in
 *       force, waiting for an allowed pause point. Refer to the description in CFG1[DATAPAUSE].
 *  0b1..Data Paused. A data pause has been requested and is now in force.
 */
#define I2S_SECCHANNEL_PSTAT_DATAPAUSED(x)       (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT)) & I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK)
/*! @} */

/* The count of I2S_SECCHANNEL_PSTAT */
#define I2S_SECCHANNEL_PSTAT_COUNT               (3U)

/*! @name FIFOCFG - FIFO Configuration and Enable */
/*! @{ */

#define I2S_FIFOCFG_ENABLETX_MASK                (0x1U)
#define I2S_FIFOCFG_ENABLETX_SHIFT               (0U)
/*! ENABLETX - Enable Transmit FIFO
 *  0b0..Disabled Transmit. The transmit FIFO is not enabled.
 *  0b1..Enabled transmit. The transmit FIFO is enabled.
 */
#define I2S_FIFOCFG_ENABLETX(x)                  (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLETX_SHIFT)) & I2S_FIFOCFG_ENABLETX_MASK)

#define I2S_FIFOCFG_ENABLERX_MASK                (0x2U)
#define I2S_FIFOCFG_ENABLERX_SHIFT               (1U)
/*! ENABLERX - Enable Receive FIFO
 *  0b0..Disabled. The receive FIFO is not enabled.
 *  0b1..Enabled. The receive FIFO is enabled.
 */
#define I2S_FIFOCFG_ENABLERX(x)                  (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLERX_SHIFT)) & I2S_FIFOCFG_ENABLERX_MASK)

#define I2S_FIFOCFG_TXI2SE0_MASK                 (0x4U)
#define I2S_FIFOCFG_TXI2SE0_SHIFT                (2U)
/*! TXI2SE0 - Transmit I2S Empty 0
 *  0b0..Last value
 *  0b1..Zero
 */
#define I2S_FIFOCFG_TXI2SE0(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK)

#define I2S_FIFOCFG_PACK48_MASK                  (0x8U)
#define I2S_FIFOCFG_PACK48_SHIFT                 (3U)
/*! PACK48 - Packing Format 48-bit data
 *  0b0..Bits_24
 *  0b1..Bits_32_16
 */
#define I2S_FIFOCFG_PACK48(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK)

#define I2S_FIFOCFG_SIZE_MASK                    (0x30U)
#define I2S_FIFOCFG_SIZE_SHIFT                   (4U)
/*! SIZE - FIFO Size Configuration
 *  0b10..Size 32 Bits
 *  0b11..Size 48 Bits
 */
#define I2S_FIFOCFG_SIZE(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_SIZE_SHIFT)) & I2S_FIFOCFG_SIZE_MASK)

#define I2S_FIFOCFG_DMATX_MASK                   (0x1000U)
#define I2S_FIFOCFG_DMATX_SHIFT                  (12U)
/*! DMATX - DMA Transmit
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define I2S_FIFOCFG_DMATX(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMATX_SHIFT)) & I2S_FIFOCFG_DMATX_MASK)

#define I2S_FIFOCFG_DMARX_MASK                   (0x2000U)
#define I2S_FIFOCFG_DMARX_SHIFT                  (13U)
/*! DMARX - DMA Receive
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define I2S_FIFOCFG_DMARX(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMARX_SHIFT)) & I2S_FIFOCFG_DMARX_MASK)

#define I2S_FIFOCFG_WAKETX_MASK                  (0x4000U)
#define I2S_FIFOCFG_WAKETX_SHIFT                 (14U)
/*! WAKETX - Wake-up for Transmit FIFO Level
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define I2S_FIFOCFG_WAKETX(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKETX_SHIFT)) & I2S_FIFOCFG_WAKETX_MASK)

#define I2S_FIFOCFG_WAKERX_MASK                  (0x8000U)
#define I2S_FIFOCFG_WAKERX_SHIFT                 (15U)
/*! WAKERX - Wake-up for Receive FIFO Level
 *  0b0..Only enabled interrupts wake up the device from reduced power modes.
 *  0b1..A device wake-up for DMA occurs if the receive FIFO level reaches the value specified by FIFOTRIG[RXLVL],
 *       even when the RXLVL interrupt is not enabled.
 */
#define I2S_FIFOCFG_WAKERX(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKERX_SHIFT)) & I2S_FIFOCFG_WAKERX_MASK)

#define I2S_FIFOCFG_EMPTYTX_MASK                 (0x10000U)
#define I2S_FIFOCFG_EMPTYTX_SHIFT                (16U)
/*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied.
 */
#define I2S_FIFOCFG_EMPTYTX(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYTX_SHIFT)) & I2S_FIFOCFG_EMPTYTX_MASK)

#define I2S_FIFOCFG_EMPTYRX_MASK                 (0x20000U)
#define I2S_FIFOCFG_EMPTYRX_SHIFT                (17U)
/*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied.
 */
#define I2S_FIFOCFG_EMPTYRX(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYRX_SHIFT)) & I2S_FIFOCFG_EMPTYRX_MASK)

#define I2S_FIFOCFG_POPDBG_MASK                  (0x40000U)
#define I2S_FIFOCFG_POPDBG_SHIFT                 (18U)
/*! POPDBG - Pop FIFO for Debug Reads
 *  0b0..Debug reads of the FIFO do not pop the FIFO.
 *  0b1..A debug read causes the FIFO to pop.
 */
#define I2S_FIFOCFG_POPDBG(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_POPDBG_SHIFT)) & I2S_FIFOCFG_POPDBG_MASK)
/*! @} */

/*! @name FIFOSTAT - FIFO Status */
/*! @{ */

#define I2S_FIFOSTAT_TXERR_MASK                  (0x1U)
#define I2S_FIFOSTAT_TXERR_SHIFT                 (0U)
/*! TXERR - TX FIFO Error
 *  0b0..No transmit FIFO error occured
 *  0b1..Transmit FIFO error occured
 */
#define I2S_FIFOSTAT_TXERR(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXERR_SHIFT)) & I2S_FIFOSTAT_TXERR_MASK)

#define I2S_FIFOSTAT_RXERR_MASK                  (0x2U)
#define I2S_FIFOSTAT_RXERR_SHIFT                 (1U)
/*! RXERR - RX FIFO Error
 *  0b0..No receive FIFO error occured
 *  0b1..Receive FIFO error occured
 */
#define I2S_FIFOSTAT_RXERR(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXERR_SHIFT)) & I2S_FIFOSTAT_RXERR_MASK)

#define I2S_FIFOSTAT_PERINT_MASK                 (0x8U)
#define I2S_FIFOSTAT_PERINT_SHIFT                (3U)
/*! PERINT - Peripheral Interrupt
 *  0b0..No interrupt
 *  0b1..Interrupt
 */
#define I2S_FIFOSTAT_PERINT(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_PERINT_SHIFT)) & I2S_FIFOSTAT_PERINT_MASK)

#define I2S_FIFOSTAT_TXEMPTY_MASK                (0x10U)
#define I2S_FIFOSTAT_TXEMPTY_SHIFT               (4U)
/*! TXEMPTY - Transmit FIFO Empty
 *  0b0..Transmit FIFO is not empty
 *  0b1..Transmit FIFO is empty; however, the peripheral may still be processing the last piece of data.
 */
#define I2S_FIFOSTAT_TXEMPTY(x)                  (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXEMPTY_SHIFT)) & I2S_FIFOSTAT_TXEMPTY_MASK)

#define I2S_FIFOSTAT_TXNOTFULL_MASK              (0x20U)
#define I2S_FIFOSTAT_TXNOTFULL_SHIFT             (5U)
/*! TXNOTFULL - Transmit FIFO Not Full
 *  0b0..Transmit FIFO is full, and another write would cause an overflow
 *  0b1..Transmit FIFO is not full, so more data can be written
 */
#define I2S_FIFOSTAT_TXNOTFULL(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXNOTFULL_SHIFT)) & I2S_FIFOSTAT_TXNOTFULL_MASK)

#define I2S_FIFOSTAT_RXNOTEMPTY_MASK             (0x40U)
#define I2S_FIFOSTAT_RXNOTEMPTY_SHIFT            (6U)
/*! RXNOTEMPTY - Receive FIFO Not Empty
 *  0b0..Receive FIFO is empty
 *  0b1..Receive FIFO is not empty, so data can be read.
 */
#define I2S_FIFOSTAT_RXNOTEMPTY(x)               (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXNOTEMPTY_SHIFT)) & I2S_FIFOSTAT_RXNOTEMPTY_MASK)

#define I2S_FIFOSTAT_RXFULL_MASK                 (0x80U)
#define I2S_FIFOSTAT_RXFULL_SHIFT                (7U)
/*! RXFULL - Receive FIFO Full
 *  0b0..Receive FIFO is not full
 *  0b1..Receive FIFO is full
 */
#define I2S_FIFOSTAT_RXFULL(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXFULL_SHIFT)) & I2S_FIFOSTAT_RXFULL_MASK)

#define I2S_FIFOSTAT_TXLVL_MASK                  (0x1F00U)
#define I2S_FIFOSTAT_TXLVL_SHIFT                 (8U)
/*! TXLVL - Transmit FIFO Current Level
 *  0b00000..TX FIFO is empty
 */
#define I2S_FIFOSTAT_TXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXLVL_SHIFT)) & I2S_FIFOSTAT_TXLVL_MASK)

#define I2S_FIFOSTAT_RXLVL_MASK                  (0x1F0000U)
#define I2S_FIFOSTAT_RXLVL_SHIFT                 (16U)
/*! RXLVL - Receive FIFO Current Level
 *  0b00000..RX FIFO is empty
 */
#define I2S_FIFOSTAT_RXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXLVL_SHIFT)) & I2S_FIFOSTAT_RXLVL_MASK)

#define I2S_FIFOSTAT_RXTIMEOUT_MASK              (0x1000000U)
#define I2S_FIFOSTAT_RXTIMEOUT_SHIFT             (24U)
/*! RXTIMEOUT - Receive FIFO Timeout
 *  0b0..RX FIFO on
 *  0b1..RX FIFO has timed out, based on the timeout configuration in the FIFORXTIMEOUTCFG register.
 */
#define I2S_FIFOSTAT_RXTIMEOUT(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXTIMEOUT_SHIFT)) & I2S_FIFOSTAT_RXTIMEOUT_MASK)
/*! @} */

/*! @name FIFOTRIG - FIFO Trigger Settings */
/*! @{ */

#define I2S_FIFOTRIG_TXLVLENA_MASK               (0x1U)
#define I2S_FIFOTRIG_TXLVLENA_SHIFT              (0U)
/*! TXLVLENA - Transmit FIFO Level Trigger Enable
 *  0b0..Transmit FIFO level does not generate a FIFO level trigger.
 *  0b1..An trigger generates if the transmit FIFO level reaches the value specified by the TXLVL field in this register.
 */
#define I2S_FIFOTRIG_TXLVLENA(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVLENA_SHIFT)) & I2S_FIFOTRIG_TXLVLENA_MASK)

#define I2S_FIFOTRIG_RXLVLENA_MASK               (0x2U)
#define I2S_FIFOTRIG_RXLVLENA_SHIFT              (1U)
/*! RXLVLENA - Receive FIFO Level Trigger Enable
 *  0b0..Receive FIFO level does not generate a FIFO level trigger.
 *  0b1..An trigger generates if the receive FIFO level reaches the value specified by the RXLVL.
 */
#define I2S_FIFOTRIG_RXLVLENA(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVLENA_SHIFT)) & I2S_FIFOTRIG_RXLVLENA_MASK)

#define I2S_FIFOTRIG_TXLVL_MASK                  (0xF00U)
#define I2S_FIFOTRIG_TXLVL_SHIFT                 (8U)
/*! TXLVL - Transmit FIFO Level Trigger Point
 *  0b0000..Trigger when the TX FIFO becomes empty.
 *  0b0001..Trigger when the TX FIFO level decreases to one entry.
 *  0b1111..Trigger when the TX FIFO level decreases to 15 entries (is no longer full).
 */
#define I2S_FIFOTRIG_TXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVL_SHIFT)) & I2S_FIFOTRIG_TXLVL_MASK)

#define I2S_FIFOTRIG_RXLVL_MASK                  (0xF0000U)
#define I2S_FIFOTRIG_RXLVL_SHIFT                 (16U)
/*! RXLVL - Receive FIFO Level Trigger Point
 *  0b0000..Trigger when the RX FIFO has received 1 entry (the FIFO is no longer empty).
 *  0b0001..Trigger when the RX FIFO has received 2 entries.
 *  0b1111..Trigger when the RX FIFO has received 16 entries (the FIFO has become full).
 */
#define I2S_FIFOTRIG_RXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVL_SHIFT)) & I2S_FIFOTRIG_RXLVL_MASK)
/*! @} */

/*! @name FIFOINTENSET - FIFO Interrupt Enable Set and Read */
/*! @{ */

#define I2S_FIFOINTENSET_TXERR_MASK              (0x1U)
#define I2S_FIFOINTENSET_TXERR_SHIFT             (0U)
/*! TXERR - Transmit Error Interrupt
 *  0b0..Disabled. No interrupt generates for a transmit error.
 *  0b1..Enabled. An interrupt generates when a transmit error occurs.
 */
#define I2S_FIFOINTENSET_TXERR(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXERR_SHIFT)) & I2S_FIFOINTENSET_TXERR_MASK)

#define I2S_FIFOINTENSET_RXERR_MASK              (0x2U)
#define I2S_FIFOINTENSET_RXERR_SHIFT             (1U)
/*! RXERR - Receive Error Interrupt
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define I2S_FIFOINTENSET_RXERR(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXERR_SHIFT)) & I2S_FIFOINTENSET_RXERR_MASK)

#define I2S_FIFOINTENSET_TXLVL_MASK              (0x4U)
#define I2S_FIFOINTENSET_TXLVL_SHIFT             (2U)
/*! TXLVL - Transmit Level Interrupt
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define I2S_FIFOINTENSET_TXLVL(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXLVL_SHIFT)) & I2S_FIFOINTENSET_TXLVL_MASK)

#define I2S_FIFOINTENSET_RXLVL_MASK              (0x8U)
#define I2S_FIFOINTENSET_RXLVL_SHIFT             (3U)
/*! RXLVL - Receive Level Interrupt
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define I2S_FIFOINTENSET_RXLVL(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXLVL_SHIFT)) & I2S_FIFOINTENSET_RXLVL_MASK)

#define I2S_FIFOINTENSET_RXTIMEOUT_MASK          (0x1000000U)
#define I2S_FIFOINTENSET_RXTIMEOUT_SHIFT         (24U)
/*! RXTIMEOUT - Receive Timeout
 *  0b0..No RX interrupt will be generated.
 *  0b1..Asserts RX interrupt if RX FIFO Timeout event occurs.
 */
#define I2S_FIFOINTENSET_RXTIMEOUT(x)            (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXTIMEOUT_SHIFT)) & I2S_FIFOINTENSET_RXTIMEOUT_MASK)
/*! @} */

/*! @name FIFOINTENCLR - FIFO Interrupt Enable Clear and Read */
/*! @{ */

#define I2S_FIFOINTENCLR_TXERR_MASK              (0x1U)
#define I2S_FIFOINTENCLR_TXERR_SHIFT             (0U)
/*! TXERR - Transmit Error Interrupt Clear
 *  0b0..Interrupt is not cleared.
 *  0b1..Interrupt is cleared.
 */
#define I2S_FIFOINTENCLR_TXERR(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXERR_SHIFT)) & I2S_FIFOINTENCLR_TXERR_MASK)

#define I2S_FIFOINTENCLR_RXERR_MASK              (0x2U)
#define I2S_FIFOINTENCLR_RXERR_SHIFT             (1U)
/*! RXERR - Receive Error Interrupt Clear
 *  0b0..Interrupt is not cleared.
 *  0b1..Interrupt is cleared.
 */
#define I2S_FIFOINTENCLR_RXERR(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXERR_SHIFT)) & I2S_FIFOINTENCLR_RXERR_MASK)

#define I2S_FIFOINTENCLR_TXLVL_MASK              (0x4U)
#define I2S_FIFOINTENCLR_TXLVL_SHIFT             (2U)
/*! TXLVL - Transmit Level Interrupt Clear
 *  0b0..Interrupt is not cleared.
 *  0b1..Interrupt is cleared.
 */
#define I2S_FIFOINTENCLR_TXLVL(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXLVL_SHIFT)) & I2S_FIFOINTENCLR_TXLVL_MASK)

#define I2S_FIFOINTENCLR_RXLVL_MASK              (0x8U)
#define I2S_FIFOINTENCLR_RXLVL_SHIFT             (3U)
/*! RXLVL - Receive Level Interrupt Clear
 *  0b0..Interrupt is not cleared.
 *  0b1..Interrupt is cleared.
 */
#define I2S_FIFOINTENCLR_RXLVL(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXLVL_SHIFT)) & I2S_FIFOINTENCLR_RXLVL_MASK)

#define I2S_FIFOINTENCLR_RXTIMEOUT_MASK          (0x1000000U)
#define I2S_FIFOINTENCLR_RXTIMEOUT_SHIFT         (24U)
/*! RXTIMEOUT - Receive Timeout
 *  0b0..No effect
 *  0b1..Clear the interrupt
 */
#define I2S_FIFOINTENCLR_RXTIMEOUT(x)            (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXTIMEOUT_SHIFT)) & I2S_FIFOINTENCLR_RXTIMEOUT_MASK)
/*! @} */

/*! @name FIFOINTSTAT - FIFO Interrupt Status */
/*! @{ */

#define I2S_FIFOINTSTAT_TXERR_MASK               (0x1U)
#define I2S_FIFOINTSTAT_TXERR_SHIFT              (0U)
/*! TXERR - TX FIFO Error Interrupt Status
 *  0b0..Not pending
 *  0b1..Pending
 */
#define I2S_FIFOINTSTAT_TXERR(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXERR_SHIFT)) & I2S_FIFOINTSTAT_TXERR_MASK)

#define I2S_FIFOINTSTAT_RXERR_MASK               (0x2U)
#define I2S_FIFOINTSTAT_RXERR_SHIFT              (1U)
/*! RXERR - RX FIFO Error Interrupt Status
 *  0b0..Not pending
 *  0b1..Pending
 */
#define I2S_FIFOINTSTAT_RXERR(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXERR_SHIFT)) & I2S_FIFOINTSTAT_RXERR_MASK)

#define I2S_FIFOINTSTAT_TXLVL_MASK               (0x4U)
#define I2S_FIFOINTSTAT_TXLVL_SHIFT              (2U)
/*! TXLVL - Transmit FIFO Level Interrupt Status
 *  0b0..Not pending
 *  0b1..Pending
 */
#define I2S_FIFOINTSTAT_TXLVL(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXLVL_SHIFT)) & I2S_FIFOINTSTAT_TXLVL_MASK)

#define I2S_FIFOINTSTAT_RXLVL_MASK               (0x8U)
#define I2S_FIFOINTSTAT_RXLVL_SHIFT              (3U)
/*! RXLVL - Receive FIFO Level Interrupt Status
 *  0b0..Not pending
 *  0b1..Pending
 */
#define I2S_FIFOINTSTAT_RXLVL(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXLVL_SHIFT)) & I2S_FIFOINTSTAT_RXLVL_MASK)

#define I2S_FIFOINTSTAT_PERINT_MASK              (0x10U)
#define I2S_FIFOINTSTAT_PERINT_SHIFT             (4U)
/*! PERINT - Peripheral Interrupt Status
 *  0b0..Not pending
 *  0b1..Pending
 */
#define I2S_FIFOINTSTAT_PERINT(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_PERINT_SHIFT)) & I2S_FIFOINTSTAT_PERINT_MASK)

#define I2S_FIFOINTSTAT_RXTIMEOUT_MASK           (0x1000000U)
#define I2S_FIFOINTSTAT_RXTIMEOUT_SHIFT          (24U)
/*! RXTIMEOUT - Receive Timeout Status
 *  0b0..Not pending
 *  0b1..Pending
 */
#define I2S_FIFOINTSTAT_RXTIMEOUT(x)             (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXTIMEOUT_SHIFT)) & I2S_FIFOINTSTAT_RXTIMEOUT_MASK)
/*! @} */

/*! @name FIFOWR - FIFO Write Data */
/*! @{ */

#define I2S_FIFOWR_TXDATA_MASK                   (0xFFFFFFFFU)
#define I2S_FIFOWR_TXDATA_SHIFT                  (0U)
/*! TXDATA - Transmit Data to the FIFO
 */
#define I2S_FIFOWR_TXDATA(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR_TXDATA_SHIFT)) & I2S_FIFOWR_TXDATA_MASK)
/*! @} */

/*! @name FIFOWR48H - FIFO Write Data for Upper Data Bits */
/*! @{ */

#define I2S_FIFOWR48H_TXDATA_MASK                (0xFFFFFFU)
#define I2S_FIFOWR48H_TXDATA_SHIFT               (0U)
/*! TXDATA - Transmit Data to the FIFO
 */
#define I2S_FIFOWR48H_TXDATA(x)                  (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR48H_TXDATA_SHIFT)) & I2S_FIFOWR48H_TXDATA_MASK)
/*! @} */

/*! @name FIFORD - FIFO Read Data */
/*! @{ */

#define I2S_FIFORD_RXDATA_MASK                   (0xFFFFFFFFU)
#define I2S_FIFORD_RXDATA_SHIFT                  (0U)
/*! RXDATA - Received Data from the FIFO
 */
#define I2S_FIFORD_RXDATA(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD_RXDATA_SHIFT)) & I2S_FIFORD_RXDATA_MASK)
/*! @} */

/*! @name FIFORD48H - FIFO Read Data for Upper Data Bits */
/*! @{ */

#define I2S_FIFORD48H_RXDATA_MASK                (0xFFFFFFU)
#define I2S_FIFORD48H_RXDATA_SHIFT               (0U)
/*! RXDATA - Received Data from the FIFO
 */
#define I2S_FIFORD48H_RXDATA(x)                  (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48H_RXDATA_SHIFT)) & I2S_FIFORD48H_RXDATA_MASK)
/*! @} */

/*! @name FIFORDNOPOP - FIFO Data Read with No FIFO Pop */
/*! @{ */

#define I2S_FIFORDNOPOP_RXDATA_MASK              (0xFFFFFFFFU)
#define I2S_FIFORDNOPOP_RXDATA_SHIFT             (0U)
/*! RXDATA - Received Data from the FIFO
 */
#define I2S_FIFORDNOPOP_RXDATA(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFORDNOPOP_RXDATA_SHIFT)) & I2S_FIFORDNOPOP_RXDATA_MASK)
/*! @} */

/*! @name FIFORD48HNOPOP - FIFO Data Read for Upper Data Bits with No FIFO Pop */
/*! @{ */

#define I2S_FIFORD48HNOPOP_RXDATA_MASK           (0xFFFFFFU)
#define I2S_FIFORD48HNOPOP_RXDATA_SHIFT          (0U)
/*! RXDATA - Received Data from the FIFO
 */
#define I2S_FIFORD48HNOPOP_RXDATA(x)             (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK)
/*! @} */

/*! @name FIFOSIZE - FIFO Size Register */
/*! @{ */

#define I2S_FIFOSIZE_FIFOSIZE_MASK               (0x1FU)
#define I2S_FIFOSIZE_FIFOSIZE_SHIFT              (0U)
/*! FIFOSIZE - FIFO Size
 */
#define I2S_FIFOSIZE_FIFOSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSIZE_FIFOSIZE_SHIFT)) & I2S_FIFOSIZE_FIFOSIZE_MASK)
/*! @} */

/*! @name FIFORXTIMEOUTCFG - FIFO Receive Timeout Configuration */
/*! @{ */

#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER_MASK (0xFFU)
#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER_SHIFT (0U)
/*! RXTIMEOUT_PRESCALER - Receive Timeout Counter Clock Prescaler
 */
#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER_SHIFT)) & I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER_MASK)

#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE_MASK (0xFFFF00U)
#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE_SHIFT (8U)
/*! RXTIMEOUT_VALUE - Receive Timeout Value
 */
#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE(x)  (((uint32_t)(((uint32_t)(x)) << I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE_SHIFT)) & I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE_MASK)

#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_EN_MASK   (0x1000000U)
#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_EN_SHIFT  (24U)
/*! RXTIMEOUT_EN - Receive Timeout Enable
 *  0b0..Disable RX FIFO timeout
 *  0b1..Enable RX FIFO timeout
 */
#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_EN(x)     (((uint32_t)(((uint32_t)(x)) << I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_EN_SHIFT)) & I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_EN_MASK)

#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_COW_MASK  (0x2000000U)
#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_COW_SHIFT (25U)
/*! RXTIMEOUT_COW - Receive Timeout Continue On Write
 *  0b0..RX FIFO timeout counter is reset every time data is transferred from the peripheral into the RX FIFO.
 *  0b1..RX FIFO timeout counter is not reset every time data is transferred from the peripheral into the RX FIFO.
 */
#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_COW(x)    (((uint32_t)(((uint32_t)(x)) << I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_COW_SHIFT)) & I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_COW_MASK)

#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_COE_MASK  (0x4000000U)
#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_COE_SHIFT (26U)
/*! RXTIMEOUT_COE - Receive Timeout Continue On Empty
 *  0b0..RX FIFO timeout counter is reset when the RX FIFO becomes empty.
 *  0b1..RX FIFO timeout counter is not reset when the RX FIFO becomes empty.
 */
#define I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_COE(x)    (((uint32_t)(((uint32_t)(x)) << I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_COE_SHIFT)) & I2S_FIFORXTIMEOUTCFG_RXTIMEOUT_COE_MASK)
/*! @} */

/*! @name FIFORXTIMEOUTCNT - FIFO Receive Timeout Counter */
/*! @{ */

#define I2S_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT_MASK  (0xFFFFU)
#define I2S_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT_SHIFT (0U)
/*! RXTIMEOUT_CNT - Current RX FIFO timeout counter value
 */
#define I2S_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT(x)    (((uint32_t)(((uint32_t)(x)) << I2S_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT_SHIFT)) & I2S_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT_MASK)
/*! @} */

/*! @name ID - I2S Module Identification */
/*! @{ */

#define I2S_ID_APERTURE_MASK                     (0xFFU)
#define I2S_ID_APERTURE_SHIFT                    (0U)
/*! APERTURE - Aperture
 */
#define I2S_ID_APERTURE(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_ID_APERTURE_SHIFT)) & I2S_ID_APERTURE_MASK)

#define I2S_ID_MINOR_REV_MASK                    (0xF00U)
#define I2S_ID_MINOR_REV_SHIFT                   (8U)
/*! MINOR_REV - Minor Revision
 */
#define I2S_ID_MINOR_REV(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_ID_MINOR_REV_SHIFT)) & I2S_ID_MINOR_REV_MASK)

#define I2S_ID_MAJOR_REV_MASK                    (0xF000U)
#define I2S_ID_MAJOR_REV_SHIFT                   (12U)
/*! MAJOR_REV - Major Revision
 */
#define I2S_ID_MAJOR_REV(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_ID_MAJOR_REV_SHIFT)) & I2S_ID_MAJOR_REV_MASK)

#define I2S_ID_ID_MASK                           (0xFFFF0000U)
#define I2S_ID_ID_SHIFT                          (16U)
/*! ID - Module Identifier
 */
#define I2S_ID_ID(x)                             (((uint32_t)(((uint32_t)(x)) << I2S_ID_ID_SHIFT)) & I2S_ID_ID_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group I2S_Register_Masks */


/* I2S - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral I2S0 base address */
  #define I2S0_BASE                                (0x50086000u)
  /** Peripheral I2S0 base address */
  #define I2S0_BASE_NS                             (0x40086000u)
  /** Peripheral I2S0 base pointer */
  #define I2S0                                     ((I2S_Type *)I2S0_BASE)
  /** Peripheral I2S0 base pointer */
  #define I2S0_NS                                  ((I2S_Type *)I2S0_BASE_NS)
  /** Peripheral I2S1 base address */
  #define I2S1_BASE                                (0x50087000u)
  /** Peripheral I2S1 base address */
  #define I2S1_BASE_NS                             (0x40087000u)
  /** Peripheral I2S1 base pointer */
  #define I2S1                                     ((I2S_Type *)I2S1_BASE)
  /** Peripheral I2S1 base pointer */
  #define I2S1_NS                                  ((I2S_Type *)I2S1_BASE_NS)
  /** Peripheral I2S2 base address */
  #define I2S2_BASE                                (0x50088000u)
  /** Peripheral I2S2 base address */
  #define I2S2_BASE_NS                             (0x40088000u)
  /** Peripheral I2S2 base pointer */
  #define I2S2                                     ((I2S_Type *)I2S2_BASE)
  /** Peripheral I2S2 base pointer */
  #define I2S2_NS                                  ((I2S_Type *)I2S2_BASE_NS)
  /** Peripheral I2S3 base address */
  #define I2S3_BASE                                (0x50089000u)
  /** Peripheral I2S3 base address */
  #define I2S3_BASE_NS                             (0x40089000u)
  /** Peripheral I2S3 base pointer */
  #define I2S3                                     ((I2S_Type *)I2S3_BASE)
  /** Peripheral I2S3 base pointer */
  #define I2S3_NS                                  ((I2S_Type *)I2S3_BASE_NS)
  /** Peripheral I2S4 base address */
  #define I2S4_BASE                                (0x5008A000u)
  /** Peripheral I2S4 base address */
  #define I2S4_BASE_NS                             (0x4008A000u)
  /** Peripheral I2S4 base pointer */
  #define I2S4                                     ((I2S_Type *)I2S4_BASE)
  /** Peripheral I2S4 base pointer */
  #define I2S4_NS                                  ((I2S_Type *)I2S4_BASE_NS)
  /** Peripheral I2S5 base address */
  #define I2S5_BASE                                (0x50096000u)
  /** Peripheral I2S5 base address */
  #define I2S5_BASE_NS                             (0x40096000u)
  /** Peripheral I2S5 base pointer */
  #define I2S5                                     ((I2S_Type *)I2S5_BASE)
  /** Peripheral I2S5 base pointer */
  #define I2S5_NS                                  ((I2S_Type *)I2S5_BASE_NS)
  /** Peripheral I2S6 base address */
  #define I2S6_BASE                                (0x50097000u)
  /** Peripheral I2S6 base address */
  #define I2S6_BASE_NS                             (0x40097000u)
  /** Peripheral I2S6 base pointer */
  #define I2S6                                     ((I2S_Type *)I2S6_BASE)
  /** Peripheral I2S6 base pointer */
  #define I2S6_NS                                  ((I2S_Type *)I2S6_BASE_NS)
  /** Peripheral I2S7 base address */
  #define I2S7_BASE                                (0x50098000u)
  /** Peripheral I2S7 base address */
  #define I2S7_BASE_NS                             (0x40098000u)
  /** Peripheral I2S7 base pointer */
  #define I2S7                                     ((I2S_Type *)I2S7_BASE)
  /** Peripheral I2S7 base pointer */
  #define I2S7_NS                                  ((I2S_Type *)I2S7_BASE_NS)
  /** Array initializer of I2S peripheral base addresses */
  #define I2S_BASE_ADDRS                           { I2S0_BASE, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S4_BASE, I2S5_BASE, I2S6_BASE, I2S7_BASE }
  /** Array initializer of I2S peripheral base pointers */
  #define I2S_BASE_PTRS                            { I2S0, I2S1, I2S2, I2S3, I2S4, I2S5, I2S6, I2S7 }
  /** Array initializer of I2S peripheral base addresses */
  #define I2S_BASE_ADDRS_NS                        { I2S0_BASE_NS, I2S1_BASE_NS, I2S2_BASE_NS, I2S3_BASE_NS, I2S4_BASE_NS, I2S5_BASE_NS, I2S6_BASE_NS, I2S7_BASE_NS }
  /** Array initializer of I2S peripheral base pointers */
  #define I2S_BASE_PTRS_NS                         { I2S0_NS, I2S1_NS, I2S2_NS, I2S3_NS, I2S4_NS, I2S5_NS, I2S6_NS, I2S7_NS }
#else
  /** Peripheral I2S0 base address */
  #define I2S0_BASE                                (0x40086000u)
  /** Peripheral I2S0 base pointer */
  #define I2S0                                     ((I2S_Type *)I2S0_BASE)
  /** Peripheral I2S1 base address */
  #define I2S1_BASE                                (0x40087000u)
  /** Peripheral I2S1 base pointer */
  #define I2S1                                     ((I2S_Type *)I2S1_BASE)
  /** Peripheral I2S2 base address */
  #define I2S2_BASE                                (0x40088000u)
  /** Peripheral I2S2 base pointer */
  #define I2S2                                     ((I2S_Type *)I2S2_BASE)
  /** Peripheral I2S3 base address */
  #define I2S3_BASE                                (0x40089000u)
  /** Peripheral I2S3 base pointer */
  #define I2S3                                     ((I2S_Type *)I2S3_BASE)
  /** Peripheral I2S4 base address */
  #define I2S4_BASE                                (0x4008A000u)
  /** Peripheral I2S4 base pointer */
  #define I2S4                                     ((I2S_Type *)I2S4_BASE)
  /** Peripheral I2S5 base address */
  #define I2S5_BASE                                (0x40096000u)
  /** Peripheral I2S5 base pointer */
  #define I2S5                                     ((I2S_Type *)I2S5_BASE)
  /** Peripheral I2S6 base address */
  #define I2S6_BASE                                (0x40097000u)
  /** Peripheral I2S6 base pointer */
  #define I2S6                                     ((I2S_Type *)I2S6_BASE)
  /** Peripheral I2S7 base address */
  #define I2S7_BASE                                (0x40098000u)
  /** Peripheral I2S7 base pointer */
  #define I2S7                                     ((I2S_Type *)I2S7_BASE)
  /** Array initializer of I2S peripheral base addresses */
  #define I2S_BASE_ADDRS                           { I2S0_BASE, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S4_BASE, I2S5_BASE, I2S6_BASE, I2S7_BASE }
  /** Array initializer of I2S peripheral base pointers */
  #define I2S_BASE_PTRS                            { I2S0, I2S1, I2S2, I2S3, I2S4, I2S5, I2S6, I2S7 }
#endif
/** Interrupt vectors for the I2S peripheral type */
#define I2S_IRQS                                 { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn }

/*!
 * @}
 */ /* end of group I2S_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- I3C Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup I3C_Peripheral_Access_Layer I3C Peripheral Access Layer
 * @{
 */

/** I3C - Register Layout Typedef */
typedef struct {
  __IO uint32_t MCONFIG;                           /**< Master Configuration, offset: 0x0 */
  __IO uint32_t SCONFIG;                           /**< Slave Configuration, offset: 0x4 */
  __IO uint32_t SSTATUS;                           /**< Slave Status, offset: 0x8 */
  __IO uint32_t SCTRL;                             /**< Slave Control, offset: 0xC */
  __IO uint32_t SINTSET;                           /**< Slave Interrupt Set, offset: 0x10 */
  __IO uint32_t SINTCLR;                           /**< Slave Interrupt Clear, offset: 0x14 */
  __I  uint32_t SINTMASKED;                        /**< Slave Interrupt Mask, offset: 0x18 */
  __IO uint32_t SERRWARN;                          /**< Slave Errors and Warnings, offset: 0x1C */
  __IO uint32_t SDMACTRL;                          /**< Slave DMA Control, offset: 0x20 */
       uint8_t RESERVED_0[8];
  __IO uint32_t SDATACTRL;                         /**< Slave Data Control, offset: 0x2C */
  __O  uint32_t SWDATAB;                           /**< Slave Write Data Byte, offset: 0x30 */
  __O  uint32_t SWDATABE;                          /**< Slave Write Data Byte End, offset: 0x34 */
  __O  uint32_t SWDATAH;                           /**< Slave Write Data Half-word, offset: 0x38 */
  __O  uint32_t SWDATAHE;                          /**< Slave Write Data Half-word End, offset: 0x3C */
  __I  uint32_t SRDATAB;                           /**< Slave Read Data Byte, offset: 0x40 */
       uint8_t RESERVED_1[4];
  __I  uint32_t SRDATAH;                           /**< Slave Read Data Half-word, offset: 0x48 */
       uint8_t RESERVED_2[16];
  __I  uint32_t SCAPABILITIES2;                    /**< Slave Capabilities 2, offset: 0x5C */
  __I  uint32_t SCAPABILITIES;                     /**< Slave Capabilities, offset: 0x60 */
  __IO uint32_t SDYNADDR;                          /**< Slave Dynamic Address, offset: 0x64 */
  __IO uint32_t SMAXLIMITS;                        /**< Slave Maximum Limits, offset: 0x68 */
  __IO uint32_t SIDPARTNO;                         /**< Slave ID Part Number, offset: 0x6C */
  __IO uint32_t SIDEXT;                            /**< Slave ID Extension, offset: 0x70 */
  __IO uint32_t SVENDORID;                         /**< Slave Vendor ID, offset: 0x74 */
  __IO uint32_t STCCLOCK;                          /**< Slave Time Control Clock, offset: 0x78 */
  __I  uint32_t SMSGMAPADDR;                       /**< Slave Message Map Address, offset: 0x7C */
       uint8_t RESERVED_3[4];
  __IO uint32_t MCTRL;                             /**< Master Main Control, offset: 0x84 */
  __IO uint32_t MSTATUS;                           /**< Master Status, offset: 0x88 */
  __IO uint32_t MIBIRULES;                         /**< Master In-band Interrupt Registry and Rules, offset: 0x8C */
  __IO uint32_t MINTSET;                           /**< Master Interrupt Set, offset: 0x90 */
  __IO uint32_t MINTCLR;                           /**< Master Interrupt Clear, offset: 0x94 */
  __I  uint32_t MINTMASKED;                        /**< Master Interrupt Mask, offset: 0x98 */
  __IO uint32_t MERRWARN;                          /**< Master Errors and Warnings, offset: 0x9C */
  __IO uint32_t MDMACTRL;                          /**< Master DMA Control, offset: 0xA0 */
       uint8_t RESERVED_4[8];
  __IO uint32_t MDATACTRL;                         /**< Master Data Control, offset: 0xAC */
  __O  uint32_t MWDATAB;                           /**< Master Write Data Byte, offset: 0xB0 */
  __O  uint32_t MWDATABE;                          /**< Master Write Data Byte End, offset: 0xB4 */
  __O  uint32_t MWDATAH;                           /**< Master Write Data Half-word, offset: 0xB8 */
  __O  uint32_t MWDATAHE;                          /**< Master Write Data Byte End, offset: 0xBC */
  __I  uint32_t MRDATAB;                           /**< Master Read Data Byte, offset: 0xC0 */
       uint8_t RESERVED_5[4];
  __I  uint32_t MRDATAH;                           /**< Master Read Data Half-word, offset: 0xC8 */
  __O  uint32_t MWDATAB1;                          /**< Byte-only Write Byte Data (to bus), offset: 0xCC */
  union {                                          /* offset: 0xD0 */
    __O  uint32_t MWMSG_SDR_CONTROL;                 /**< Master Write Message in SDR mode, offset: 0xD0 */
    __O  uint32_t MWMSG_SDR_DATA;                    /**< Master Write Message Data in SDR mode, offset: 0xD0 */
  };
  __I  uint32_t MRMSG_SDR;                         /**< Master Read Message in SDR mode, offset: 0xD4 */
  union {                                          /* offset: 0xD8 */
    __O  uint32_t MWMSG_DDR_CONTROL;                 /**< Master Write Message in DDR mode, offset: 0xD8 */
    __O  uint32_t MWMSG_DDR_DATA;                    /**< Master Write Message Data in DDR mode, offset: 0xD8 */
  };
  __I  uint32_t MRMSG_DDR;                         /**< Master Read Message in DDR mode, offset: 0xDC */
       uint8_t RESERVED_6[4];
  __IO uint32_t MDYNADDR;                          /**< Master Dynamic Address, offset: 0xE4 */
       uint8_t RESERVED_7[52];
  __I  uint32_t SMAPCTRL0;                         /**< Map Feature Control 0, offset: 0x11C */
       uint8_t RESERVED_8[32];
  __IO uint32_t IBIEXT1;                           /**< Extended IBI Data 1, offset: 0x140 */
  __IO uint32_t IBIEXT2;                           /**< Extended IBI Data 2, offset: 0x144 */
       uint8_t RESERVED_9[3764];
  __I  uint32_t SID;                               /**< Slave Module ID, offset: 0xFFC */
} I3C_Type;

/* ----------------------------------------------------------------------------
   -- I3C Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup I3C_Register_Masks I3C Register Masks
 * @{
 */

/*! @name MCONFIG - Master Configuration */
/*! @{ */

#define I3C_MCONFIG_MSTENA_MASK                  (0x3U)
#define I3C_MCONFIG_MSTENA_SHIFT                 (0U)
/*! MSTENA - Master enable
 *  0b00..MASTER_OFF
 *  0b01..MASTER_ON
 *  0b10..MASTER_CAPABLE
 *  0b11..I2C_MASTER_MODE
 */
#define I3C_MCONFIG_MSTENA(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_MSTENA_SHIFT)) & I3C_MCONFIG_MSTENA_MASK)

#define I3C_MCONFIG_DISTO_MASK                   (0x8U)
#define I3C_MCONFIG_DISTO_SHIFT                  (3U)
/*! DISTO - Disable Timeout
 */
#define I3C_MCONFIG_DISTO(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_DISTO_SHIFT)) & I3C_MCONFIG_DISTO_MASK)

#define I3C_MCONFIG_HKEEP_MASK                   (0x30U)
#define I3C_MCONFIG_HKEEP_SHIFT                  (4U)
/*! HKEEP - High-Keeper
 *  0b00..NONE
 *  0b01..WIRED_IN
 *  0b10..PASSIVE_SDA
 *  0b11..PASSIVE_ON_SDA_SCL
 */
#define I3C_MCONFIG_HKEEP(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_HKEEP_SHIFT)) & I3C_MCONFIG_HKEEP_MASK)

#define I3C_MCONFIG_ODSTOP_MASK                  (0x40U)
#define I3C_MCONFIG_ODSTOP_SHIFT                 (6U)
/*! ODSTOP - Open drain stop
 */
#define I3C_MCONFIG_ODSTOP(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODSTOP_SHIFT)) & I3C_MCONFIG_ODSTOP_MASK)

#define I3C_MCONFIG_PPBAUD_MASK                  (0xF00U)
#define I3C_MCONFIG_PPBAUD_SHIFT                 (8U)
/*! PPBAUD - Push-pull baud rate
 */
#define I3C_MCONFIG_PPBAUD(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPBAUD_SHIFT)) & I3C_MCONFIG_PPBAUD_MASK)

#define I3C_MCONFIG_PPLOW_MASK                   (0xF000U)
#define I3C_MCONFIG_PPLOW_SHIFT                  (12U)
/*! PPLOW - Push-Pull low
 */
#define I3C_MCONFIG_PPLOW(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPLOW_SHIFT)) & I3C_MCONFIG_PPLOW_MASK)

#define I3C_MCONFIG_ODBAUD_MASK                  (0xFF0000U)
#define I3C_MCONFIG_ODBAUD_SHIFT                 (16U)
/*! ODBAUD - Open drain baud rate
 */
#define I3C_MCONFIG_ODBAUD(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODBAUD_SHIFT)) & I3C_MCONFIG_ODBAUD_MASK)

#define I3C_MCONFIG_ODHPP_MASK                   (0x1000000U)
#define I3C_MCONFIG_ODHPP_SHIFT                  (24U)
/*! ODHPP - Open Drain High Push-Pull
 */
#define I3C_MCONFIG_ODHPP(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODHPP_SHIFT)) & I3C_MCONFIG_ODHPP_MASK)

#define I3C_MCONFIG_SKEW_MASK                    (0xE000000U)
#define I3C_MCONFIG_SKEW_SHIFT                   (25U)
/*! SKEW - Skew
 */
#define I3C_MCONFIG_SKEW(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_SKEW_SHIFT)) & I3C_MCONFIG_SKEW_MASK)

#define I3C_MCONFIG_I2CBAUD_MASK                 (0xF0000000U)
#define I3C_MCONFIG_I2CBAUD_SHIFT                (28U)
/*! I2CBAUD - I2C baud rate
 */
#define I3C_MCONFIG_I2CBAUD(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_I2CBAUD_SHIFT)) & I3C_MCONFIG_I2CBAUD_MASK)
/*! @} */

/*! @name SCONFIG - Slave Configuration */
/*! @{ */

#define I3C_SCONFIG_SLVENA_MASK                  (0x1U)
#define I3C_SCONFIG_SLVENA_SHIFT                 (0U)
/*! SLVENA - Slave enable
 */
#define I3C_SCONFIG_SLVENA(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SLVENA_SHIFT)) & I3C_SCONFIG_SLVENA_MASK)

#define I3C_SCONFIG_NACK_MASK                    (0x2U)
#define I3C_SCONFIG_NACK_SHIFT                   (1U)
/*! NACK - Not acknowledge
 */
#define I3C_SCONFIG_NACK(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_NACK_SHIFT)) & I3C_SCONFIG_NACK_MASK)

#define I3C_SCONFIG_MATCHSS_MASK                 (0x4U)
#define I3C_SCONFIG_MATCHSS_SHIFT                (2U)
/*! MATCHSS - Match START or STOP
 */
#define I3C_SCONFIG_MATCHSS(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_MATCHSS_SHIFT)) & I3C_SCONFIG_MATCHSS_MASK)

#define I3C_SCONFIG_S0IGNORE_MASK                (0x8U)
#define I3C_SCONFIG_S0IGNORE_SHIFT               (3U)
/*! S0IGNORE - S0/S1 errors ignore
 */
#define I3C_SCONFIG_S0IGNORE(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_S0IGNORE_SHIFT)) & I3C_SCONFIG_S0IGNORE_MASK)

#define I3C_SCONFIG_DDROK_MASK                   (0x10U)
#define I3C_SCONFIG_DDROK_SHIFT                  (4U)
/*! DDROK - DDR OK
 */
#define I3C_SCONFIG_DDROK(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_DDROK_SHIFT)) & I3C_SCONFIG_DDROK_MASK)

#define I3C_SCONFIG_IDRAND_MASK                  (0x100U)
#define I3C_SCONFIG_IDRAND_SHIFT                 (8U)
/*! IDRAND - ID random
 */
#define I3C_SCONFIG_IDRAND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_IDRAND_SHIFT)) & I3C_SCONFIG_IDRAND_MASK)

#define I3C_SCONFIG_OFFLINE_MASK                 (0x200U)
#define I3C_SCONFIG_OFFLINE_SHIFT                (9U)
/*! OFFLINE - Offline
 */
#define I3C_SCONFIG_OFFLINE(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_OFFLINE_SHIFT)) & I3C_SCONFIG_OFFLINE_MASK)

#define I3C_SCONFIG_BAMATCH_MASK                 (0xFF0000U)
#define I3C_SCONFIG_BAMATCH_SHIFT                (16U)
/*! BAMATCH - Bus available match
 */
#define I3C_SCONFIG_BAMATCH(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_BAMATCH_SHIFT)) & I3C_SCONFIG_BAMATCH_MASK)

#define I3C_SCONFIG_SADDR_MASK                   (0xFE000000U)
#define I3C_SCONFIG_SADDR_SHIFT                  (25U)
/*! SADDR - Static address
 */
#define I3C_SCONFIG_SADDR(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SADDR_SHIFT)) & I3C_SCONFIG_SADDR_MASK)
/*! @} */

/*! @name SSTATUS - Slave Status */
/*! @{ */

#define I3C_SSTATUS_STNOTSTOP_MASK               (0x1U)
#define I3C_SSTATUS_STNOTSTOP_SHIFT              (0U)
/*! STNOTSTOP - Status not stop
 */
#define I3C_SSTATUS_STNOTSTOP(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STNOTSTOP_SHIFT)) & I3C_SSTATUS_STNOTSTOP_MASK)

#define I3C_SSTATUS_STMSG_MASK                   (0x2U)
#define I3C_SSTATUS_STMSG_SHIFT                  (1U)
/*! STMSG - Status message
 */
#define I3C_SSTATUS_STMSG(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STMSG_SHIFT)) & I3C_SSTATUS_STMSG_MASK)

#define I3C_SSTATUS_STCCCH_MASK                  (0x4U)
#define I3C_SSTATUS_STCCCH_SHIFT                 (2U)
/*! STCCCH - Status Common Command Code Handler
 */
#define I3C_SSTATUS_STCCCH(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STCCCH_SHIFT)) & I3C_SSTATUS_STCCCH_MASK)

#define I3C_SSTATUS_STREQRD_MASK                 (0x8U)
#define I3C_SSTATUS_STREQRD_SHIFT                (3U)
/*! STREQRD - Status request read
 */
#define I3C_SSTATUS_STREQRD(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STREQRD_SHIFT)) & I3C_SSTATUS_STREQRD_MASK)

#define I3C_SSTATUS_STREQWR_MASK                 (0x10U)
#define I3C_SSTATUS_STREQWR_SHIFT                (4U)
/*! STREQWR - Status request write
 */
#define I3C_SSTATUS_STREQWR(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STREQWR_SHIFT)) & I3C_SSTATUS_STREQWR_MASK)

#define I3C_SSTATUS_STDAA_MASK                   (0x20U)
#define I3C_SSTATUS_STDAA_SHIFT                  (5U)
/*! STDAA - Status Dynamic Address Assignment
 */
#define I3C_SSTATUS_STDAA(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STDAA_SHIFT)) & I3C_SSTATUS_STDAA_MASK)

#define I3C_SSTATUS_STHDR_MASK                   (0x40U)
#define I3C_SSTATUS_STHDR_SHIFT                  (6U)
/*! STHDR - Status High Data Rate
 */
#define I3C_SSTATUS_STHDR(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STHDR_SHIFT)) & I3C_SSTATUS_STHDR_MASK)

#define I3C_SSTATUS_START_MASK                   (0x100U)
#define I3C_SSTATUS_START_SHIFT                  (8U)
/*! START - Start
 */
#define I3C_SSTATUS_START(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_START_SHIFT)) & I3C_SSTATUS_START_MASK)

#define I3C_SSTATUS_MATCHED_MASK                 (0x200U)
#define I3C_SSTATUS_MATCHED_SHIFT                (9U)
/*! MATCHED - Matched
 */
#define I3C_SSTATUS_MATCHED(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_MATCHED_SHIFT)) & I3C_SSTATUS_MATCHED_MASK)

#define I3C_SSTATUS_STOP_MASK                    (0x400U)
#define I3C_SSTATUS_STOP_SHIFT                   (10U)
/*! STOP - Stop
 */
#define I3C_SSTATUS_STOP(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STOP_SHIFT)) & I3C_SSTATUS_STOP_MASK)

#define I3C_SSTATUS_RX_PEND_MASK                 (0x800U)
#define I3C_SSTATUS_RX_PEND_SHIFT                (11U)
/*! RX_PEND - Received message pending
 */
#define I3C_SSTATUS_RX_PEND(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_RX_PEND_SHIFT)) & I3C_SSTATUS_RX_PEND_MASK)

#define I3C_SSTATUS_TXNOTFULL_MASK               (0x1000U)
#define I3C_SSTATUS_TXNOTFULL_SHIFT              (12U)
/*! TXNOTFULL - Transmit buffer is not full
 */
#define I3C_SSTATUS_TXNOTFULL(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_TXNOTFULL_SHIFT)) & I3C_SSTATUS_TXNOTFULL_MASK)

#define I3C_SSTATUS_DACHG_MASK                   (0x2000U)
#define I3C_SSTATUS_DACHG_SHIFT                  (13U)
/*! DACHG - DACHG
 */
#define I3C_SSTATUS_DACHG(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_DACHG_SHIFT)) & I3C_SSTATUS_DACHG_MASK)

#define I3C_SSTATUS_CCC_MASK                     (0x4000U)
#define I3C_SSTATUS_CCC_SHIFT                    (14U)
/*! CCC - Common Command Code
 */
#define I3C_SSTATUS_CCC(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_CCC_SHIFT)) & I3C_SSTATUS_CCC_MASK)

#define I3C_SSTATUS_ERRWARN_MASK                 (0x8000U)
#define I3C_SSTATUS_ERRWARN_SHIFT                (15U)
/*! ERRWARN - Error warning
 */
#define I3C_SSTATUS_ERRWARN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_ERRWARN_SHIFT)) & I3C_SSTATUS_ERRWARN_MASK)

#define I3C_SSTATUS_HDRMATCH_MASK                (0x10000U)
#define I3C_SSTATUS_HDRMATCH_SHIFT               (16U)
/*! HDRMATCH - High Data Rate command match
 */
#define I3C_SSTATUS_HDRMATCH(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_HDRMATCH_SHIFT)) & I3C_SSTATUS_HDRMATCH_MASK)

#define I3C_SSTATUS_CHANDLED_MASK                (0x20000U)
#define I3C_SSTATUS_CHANDLED_SHIFT               (17U)
/*! CHANDLED - Common Command Code handled
 */
#define I3C_SSTATUS_CHANDLED(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_CHANDLED_SHIFT)) & I3C_SSTATUS_CHANDLED_MASK)

#define I3C_SSTATUS_EVENT_MASK                   (0x40000U)
#define I3C_SSTATUS_EVENT_SHIFT                  (18U)
/*! EVENT - Event
 */
#define I3C_SSTATUS_EVENT(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_EVENT_SHIFT)) & I3C_SSTATUS_EVENT_MASK)

#define I3C_SSTATUS_EVDET_MASK                   (0x300000U)
#define I3C_SSTATUS_EVDET_SHIFT                  (20U)
/*! EVDET - Event details
 *  0b00..NONE
 *  0b01..NO_REQUEST
 *  0b10..NACKED
 *  0b11..ACKED
 */
#define I3C_SSTATUS_EVDET(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_EVDET_SHIFT)) & I3C_SSTATUS_EVDET_MASK)

#define I3C_SSTATUS_IBIDIS_MASK                  (0x1000000U)
#define I3C_SSTATUS_IBIDIS_SHIFT                 (24U)
/*! IBIDIS - In-Band Interrupts are disabled
 */
#define I3C_SSTATUS_IBIDIS(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_IBIDIS_SHIFT)) & I3C_SSTATUS_IBIDIS_MASK)

#define I3C_SSTATUS_MRDIS_MASK                   (0x2000000U)
#define I3C_SSTATUS_MRDIS_SHIFT                  (25U)
/*! MRDIS - Master requests are disabled
 */
#define I3C_SSTATUS_MRDIS(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_MRDIS_SHIFT)) & I3C_SSTATUS_MRDIS_MASK)

#define I3C_SSTATUS_HJDIS_MASK                   (0x8000000U)
#define I3C_SSTATUS_HJDIS_SHIFT                  (27U)
/*! HJDIS - Hot-Join is disabled
 */
#define I3C_SSTATUS_HJDIS(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_HJDIS_SHIFT)) & I3C_SSTATUS_HJDIS_MASK)

#define I3C_SSTATUS_ACTSTATE_MASK                (0x30000000U)
#define I3C_SSTATUS_ACTSTATE_SHIFT               (28U)
/*! ACTSTATE - Activity state from Common Command Codes (CCC)
 *  0b00..NO_LATENCY
 *  0b01..LATENCY_1MS
 *  0b10..LATENCY_100MS
 *  0b11..LATENCY_10S
 */
#define I3C_SSTATUS_ACTSTATE(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_ACTSTATE_SHIFT)) & I3C_SSTATUS_ACTSTATE_MASK)

#define I3C_SSTATUS_TIMECTRL_MASK                (0xC0000000U)
#define I3C_SSTATUS_TIMECTRL_SHIFT               (30U)
/*! TIMECTRL - Time control
 *  0b00..NO_TIME_CONTROL
 *  0b01..
 *  0b10..ASYNC_MODE
 *  0b11..
 */
#define I3C_SSTATUS_TIMECTRL(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_TIMECTRL_SHIFT)) & I3C_SSTATUS_TIMECTRL_MASK)
/*! @} */

/*! @name SCTRL - Slave Control */
/*! @{ */

#define I3C_SCTRL_EVENT_MASK                     (0x3U)
#define I3C_SCTRL_EVENT_SHIFT                    (0U)
/*! EVENT - EVENT
 *  0b00..NORMAL_MODE
 *  0b01..IBI
 *  0b10..MASTER_REQUEST
 *  0b11..HOT_JOIN_REQUEST
 */
#define I3C_SCTRL_EVENT(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_EVENT_SHIFT)) & I3C_SCTRL_EVENT_MASK)

#define I3C_SCTRL_EXTDATA_MASK                   (0x8U)
#define I3C_SCTRL_EXTDATA_SHIFT                  (3U)
/*! EXTDATA - Extended Data
 */
#define I3C_SCTRL_EXTDATA(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_EXTDATA_SHIFT)) & I3C_SCTRL_EXTDATA_MASK)

#define I3C_SCTRL_IBIDATA_MASK                   (0xFF00U)
#define I3C_SCTRL_IBIDATA_SHIFT                  (8U)
/*! IBIDATA - In-Band Interrupt data
 */
#define I3C_SCTRL_IBIDATA(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_IBIDATA_SHIFT)) & I3C_SCTRL_IBIDATA_MASK)

#define I3C_SCTRL_PENDINT_MASK                   (0xF0000U)
#define I3C_SCTRL_PENDINT_SHIFT                  (16U)
/*! PENDINT - Pending interrupt
 */
#define I3C_SCTRL_PENDINT(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_PENDINT_SHIFT)) & I3C_SCTRL_PENDINT_MASK)

#define I3C_SCTRL_ACTSTATE_MASK                  (0x300000U)
#define I3C_SCTRL_ACTSTATE_SHIFT                 (20U)
/*! ACTSTATE - Activity state (of slave)
 */
#define I3C_SCTRL_ACTSTATE(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_ACTSTATE_SHIFT)) & I3C_SCTRL_ACTSTATE_MASK)

#define I3C_SCTRL_VENDINFO_MASK                  (0xFF000000U)
#define I3C_SCTRL_VENDINFO_SHIFT                 (24U)
/*! VENDINFO - Vendor information
 */
#define I3C_SCTRL_VENDINFO(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_VENDINFO_SHIFT)) & I3C_SCTRL_VENDINFO_MASK)
/*! @} */

/*! @name SINTSET - Slave Interrupt Set */
/*! @{ */

#define I3C_SINTSET_START_MASK                   (0x100U)
#define I3C_SINTSET_START_SHIFT                  (8U)
/*! START - Start interrupt enable
 */
#define I3C_SINTSET_START(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_START_SHIFT)) & I3C_SINTSET_START_MASK)

#define I3C_SINTSET_MATCHED_MASK                 (0x200U)
#define I3C_SINTSET_MATCHED_SHIFT                (9U)
/*! MATCHED - Match interrupt enable
 */
#define I3C_SINTSET_MATCHED(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_MATCHED_SHIFT)) & I3C_SINTSET_MATCHED_MASK)

#define I3C_SINTSET_STOP_MASK                    (0x400U)
#define I3C_SINTSET_STOP_SHIFT                   (10U)
/*! STOP - Stop interrupt enable
 */
#define I3C_SINTSET_STOP(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_STOP_SHIFT)) & I3C_SINTSET_STOP_MASK)

#define I3C_SINTSET_RXPEND_MASK                  (0x800U)
#define I3C_SINTSET_RXPEND_SHIFT                 (11U)
/*! RXPEND - Receive interrupt enable
 */
#define I3C_SINTSET_RXPEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_RXPEND_SHIFT)) & I3C_SINTSET_RXPEND_MASK)

#define I3C_SINTSET_TXSEND_MASK                  (0x1000U)
#define I3C_SINTSET_TXSEND_SHIFT                 (12U)
/*! TXSEND - Transmit interrupt enable
 */
#define I3C_SINTSET_TXSEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_TXSEND_SHIFT)) & I3C_SINTSET_TXSEND_MASK)

#define I3C_SINTSET_DACHG_MASK                   (0x2000U)
#define I3C_SINTSET_DACHG_SHIFT                  (13U)
/*! DACHG - Dynamic address change interrupt enable
 */
#define I3C_SINTSET_DACHG(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_DACHG_SHIFT)) & I3C_SINTSET_DACHG_MASK)

#define I3C_SINTSET_CCC_MASK                     (0x4000U)
#define I3C_SINTSET_CCC_SHIFT                    (14U)
/*! CCC - Common Command Code (CCC) (that was not handled by I3C module) interrupt enable
 */
#define I3C_SINTSET_CCC(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_CCC_SHIFT)) & I3C_SINTSET_CCC_MASK)

#define I3C_SINTSET_ERRWARN_MASK                 (0x8000U)
#define I3C_SINTSET_ERRWARN_SHIFT                (15U)
/*! ERRWARN - Error/warning interrupt enable
 */
#define I3C_SINTSET_ERRWARN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_ERRWARN_SHIFT)) & I3C_SINTSET_ERRWARN_MASK)

#define I3C_SINTSET_DDRMATCHED_MASK              (0x10000U)
#define I3C_SINTSET_DDRMATCHED_SHIFT             (16U)
/*! DDRMATCHED - Double Data Rate (DDR) interrupt enable
 */
#define I3C_SINTSET_DDRMATCHED(x)                (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_DDRMATCHED_SHIFT)) & I3C_SINTSET_DDRMATCHED_MASK)

#define I3C_SINTSET_CHANDLED_MASK                (0x20000U)
#define I3C_SINTSET_CHANDLED_SHIFT               (17U)
/*! CHANDLED - Common Command Code (CCC) (that was handled by I3C module) interrupt enable
 */
#define I3C_SINTSET_CHANDLED(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_CHANDLED_SHIFT)) & I3C_SINTSET_CHANDLED_MASK)

#define I3C_SINTSET_EVENT_MASK                   (0x40000U)
#define I3C_SINTSET_EVENT_SHIFT                  (18U)
/*! EVENT - Event interrupt enable
 */
#define I3C_SINTSET_EVENT(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_EVENT_SHIFT)) & I3C_SINTSET_EVENT_MASK)
/*! @} */

/*! @name SINTCLR - Slave Interrupt Clear */
/*! @{ */

#define I3C_SINTCLR_START_MASK                   (0x100U)
#define I3C_SINTCLR_START_SHIFT                  (8U)
/*! START - START interrupt enable clear
 */
#define I3C_SINTCLR_START(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_START_SHIFT)) & I3C_SINTCLR_START_MASK)

#define I3C_SINTCLR_MATCHED_MASK                 (0x200U)
#define I3C_SINTCLR_MATCHED_SHIFT                (9U)
/*! MATCHED - MATCHED interrupt enable clear
 */
#define I3C_SINTCLR_MATCHED(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_MATCHED_SHIFT)) & I3C_SINTCLR_MATCHED_MASK)

#define I3C_SINTCLR_STOP_MASK                    (0x400U)
#define I3C_SINTCLR_STOP_SHIFT                   (10U)
/*! STOP - STOP interrupt enable clear
 */
#define I3C_SINTCLR_STOP(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_STOP_SHIFT)) & I3C_SINTCLR_STOP_MASK)

#define I3C_SINTCLR_RXPEND_MASK                  (0x800U)
#define I3C_SINTCLR_RXPEND_SHIFT                 (11U)
/*! RXPEND - RXPEND interrupt enable clear
 */
#define I3C_SINTCLR_RXPEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_RXPEND_SHIFT)) & I3C_SINTCLR_RXPEND_MASK)

#define I3C_SINTCLR_TXSEND_MASK                  (0x1000U)
#define I3C_SINTCLR_TXSEND_SHIFT                 (12U)
/*! TXSEND - TXSEND interrupt enable clear
 */
#define I3C_SINTCLR_TXSEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_TXSEND_SHIFT)) & I3C_SINTCLR_TXSEND_MASK)

#define I3C_SINTCLR_DACHG_MASK                   (0x2000U)
#define I3C_SINTCLR_DACHG_SHIFT                  (13U)
/*! DACHG - DACHG interrupt enable clear
 */
#define I3C_SINTCLR_DACHG(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_DACHG_SHIFT)) & I3C_SINTCLR_DACHG_MASK)

#define I3C_SINTCLR_CCC_MASK                     (0x4000U)
#define I3C_SINTCLR_CCC_SHIFT                    (14U)
/*! CCC - CCC interrupt enable clear
 */
#define I3C_SINTCLR_CCC(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_CCC_SHIFT)) & I3C_SINTCLR_CCC_MASK)

#define I3C_SINTCLR_ERRWARN_MASK                 (0x8000U)
#define I3C_SINTCLR_ERRWARN_SHIFT                (15U)
/*! ERRWARN - ERRWARN interrupt enable clear
 */
#define I3C_SINTCLR_ERRWARN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_ERRWARN_SHIFT)) & I3C_SINTCLR_ERRWARN_MASK)

#define I3C_SINTCLR_DDRMATCHED_MASK              (0x10000U)
#define I3C_SINTCLR_DDRMATCHED_SHIFT             (16U)
/*! DDRMATCHED - DDRMATCHED interrupt enable clear
 */
#define I3C_SINTCLR_DDRMATCHED(x)                (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_DDRMATCHED_SHIFT)) & I3C_SINTCLR_DDRMATCHED_MASK)

#define I3C_SINTCLR_CHANDLED_MASK                (0x20000U)
#define I3C_SINTCLR_CHANDLED_SHIFT               (17U)
/*! CHANDLED - CHANDLED interrupt enable clear
 */
#define I3C_SINTCLR_CHANDLED(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_CHANDLED_SHIFT)) & I3C_SINTCLR_CHANDLED_MASK)

#define I3C_SINTCLR_EVENT_MASK                   (0x40000U)
#define I3C_SINTCLR_EVENT_SHIFT                  (18U)
/*! EVENT - EVENT interrupt enable clear
 */
#define I3C_SINTCLR_EVENT(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_EVENT_SHIFT)) & I3C_SINTCLR_EVENT_MASK)
/*! @} */

/*! @name SINTMASKED - Slave Interrupt Mask */
/*! @{ */

#define I3C_SINTMASKED_START_MASK                (0x100U)
#define I3C_SINTMASKED_START_SHIFT               (8U)
/*! START - START interrupt mask
 */
#define I3C_SINTMASKED_START(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_START_SHIFT)) & I3C_SINTMASKED_START_MASK)

#define I3C_SINTMASKED_MATCHED_MASK              (0x200U)
#define I3C_SINTMASKED_MATCHED_SHIFT             (9U)
/*! MATCHED - MATCHED interrupt mask
 */
#define I3C_SINTMASKED_MATCHED(x)                (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_MATCHED_SHIFT)) & I3C_SINTMASKED_MATCHED_MASK)

#define I3C_SINTMASKED_STOP_MASK                 (0x400U)
#define I3C_SINTMASKED_STOP_SHIFT                (10U)
/*! STOP - STOP interrupt mask
 */
#define I3C_SINTMASKED_STOP(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_STOP_SHIFT)) & I3C_SINTMASKED_STOP_MASK)

#define I3C_SINTMASKED_RXPEND_MASK               (0x800U)
#define I3C_SINTMASKED_RXPEND_SHIFT              (11U)
/*! RXPEND - RXPEND interrupt mask
 */
#define I3C_SINTMASKED_RXPEND(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_RXPEND_SHIFT)) & I3C_SINTMASKED_RXPEND_MASK)

#define I3C_SINTMASKED_TXSEND_MASK               (0x1000U)
#define I3C_SINTMASKED_TXSEND_SHIFT              (12U)
/*! TXSEND - TXSEND interrupt mask
 */
#define I3C_SINTMASKED_TXSEND(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_TXSEND_SHIFT)) & I3C_SINTMASKED_TXSEND_MASK)

#define I3C_SINTMASKED_DACHG_MASK                (0x2000U)
#define I3C_SINTMASKED_DACHG_SHIFT               (13U)
/*! DACHG - DACHG interrupt mask
 */
#define I3C_SINTMASKED_DACHG(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_DACHG_SHIFT)) & I3C_SINTMASKED_DACHG_MASK)

#define I3C_SINTMASKED_CCC_MASK                  (0x4000U)
#define I3C_SINTMASKED_CCC_SHIFT                 (14U)
/*! CCC - CCC interrupt mask
 */
#define I3C_SINTMASKED_CCC(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_CCC_SHIFT)) & I3C_SINTMASKED_CCC_MASK)

#define I3C_SINTMASKED_ERRWARN_MASK              (0x8000U)
#define I3C_SINTMASKED_ERRWARN_SHIFT             (15U)
/*! ERRWARN - ERRWARN interrupt mask
 */
#define I3C_SINTMASKED_ERRWARN(x)                (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_ERRWARN_SHIFT)) & I3C_SINTMASKED_ERRWARN_MASK)

#define I3C_SINTMASKED_DDRMATCHED_MASK           (0x10000U)
#define I3C_SINTMASKED_DDRMATCHED_SHIFT          (16U)
/*! DDRMATCHED - DDRMATCHED interrupt mask
 */
#define I3C_SINTMASKED_DDRMATCHED(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_DDRMATCHED_SHIFT)) & I3C_SINTMASKED_DDRMATCHED_MASK)

#define I3C_SINTMASKED_CHANDLED_MASK             (0x20000U)
#define I3C_SINTMASKED_CHANDLED_SHIFT            (17U)
/*! CHANDLED - CHANDLED interrupt mask
 */
#define I3C_SINTMASKED_CHANDLED(x)               (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_CHANDLED_SHIFT)) & I3C_SINTMASKED_CHANDLED_MASK)

#define I3C_SINTMASKED_EVENT_MASK                (0x40000U)
#define I3C_SINTMASKED_EVENT_SHIFT               (18U)
/*! EVENT - EVENT interrupt mask
 */
#define I3C_SINTMASKED_EVENT(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_EVENT_SHIFT)) & I3C_SINTMASKED_EVENT_MASK)
/*! @} */

/*! @name SERRWARN - Slave Errors and Warnings */
/*! @{ */

#define I3C_SERRWARN_ORUN_MASK                   (0x1U)
#define I3C_SERRWARN_ORUN_SHIFT                  (0U)
/*! ORUN - Overrun error
 */
#define I3C_SERRWARN_ORUN(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_ORUN_SHIFT)) & I3C_SERRWARN_ORUN_MASK)

#define I3C_SERRWARN_URUN_MASK                   (0x2U)
#define I3C_SERRWARN_URUN_SHIFT                  (1U)
/*! URUN - Underrun error
 */
#define I3C_SERRWARN_URUN(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUN_SHIFT)) & I3C_SERRWARN_URUN_MASK)

#define I3C_SERRWARN_URUNNACK_MASK               (0x4U)
#define I3C_SERRWARN_URUNNACK_SHIFT              (2U)
/*! URUNNACK - Underrun and Not Acknowledged (NACKed) error
 */
#define I3C_SERRWARN_URUNNACK(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUNNACK_SHIFT)) & I3C_SERRWARN_URUNNACK_MASK)

#define I3C_SERRWARN_TERM_MASK                   (0x8U)
#define I3C_SERRWARN_TERM_SHIFT                  (3U)
/*! TERM - Terminated error
 */
#define I3C_SERRWARN_TERM(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_TERM_SHIFT)) & I3C_SERRWARN_TERM_MASK)

#define I3C_SERRWARN_INVSTART_MASK               (0x10U)
#define I3C_SERRWARN_INVSTART_SHIFT              (4U)
/*! INVSTART - Invalid start error
 */
#define I3C_SERRWARN_INVSTART(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_INVSTART_SHIFT)) & I3C_SERRWARN_INVSTART_MASK)

#define I3C_SERRWARN_SPAR_MASK                   (0x100U)
#define I3C_SERRWARN_SPAR_SHIFT                  (8U)
/*! SPAR - SDR parity error
 */
#define I3C_SERRWARN_SPAR(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_SPAR_SHIFT)) & I3C_SERRWARN_SPAR_MASK)

#define I3C_SERRWARN_HPAR_MASK                   (0x200U)
#define I3C_SERRWARN_HPAR_SHIFT                  (9U)
/*! HPAR - HDR parity error
 */
#define I3C_SERRWARN_HPAR(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_HPAR_SHIFT)) & I3C_SERRWARN_HPAR_MASK)

#define I3C_SERRWARN_HCRC_MASK                   (0x400U)
#define I3C_SERRWARN_HCRC_SHIFT                  (10U)
/*! HCRC - HDR-DDR CRC error
 */
#define I3C_SERRWARN_HCRC(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_HCRC_SHIFT)) & I3C_SERRWARN_HCRC_MASK)

#define I3C_SERRWARN_S0S1_MASK                   (0x800U)
#define I3C_SERRWARN_S0S1_SHIFT                  (11U)
/*! S0S1 - S0 or S1 error
 */
#define I3C_SERRWARN_S0S1(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_S0S1_SHIFT)) & I3C_SERRWARN_S0S1_MASK)

#define I3C_SERRWARN_OREAD_MASK                  (0x10000U)
#define I3C_SERRWARN_OREAD_SHIFT                 (16U)
/*! OREAD - Over-read error
 */
#define I3C_SERRWARN_OREAD(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OREAD_SHIFT)) & I3C_SERRWARN_OREAD_MASK)

#define I3C_SERRWARN_OWRITE_MASK                 (0x20000U)
#define I3C_SERRWARN_OWRITE_SHIFT                (17U)
/*! OWRITE - Over-write error
 */
#define I3C_SERRWARN_OWRITE(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OWRITE_SHIFT)) & I3C_SERRWARN_OWRITE_MASK)
/*! @} */

/*! @name SDMACTRL - Slave DMA Control */
/*! @{ */

#define I3C_SDMACTRL_DMAFB_MASK                  (0x3U)
#define I3C_SDMACTRL_DMAFB_SHIFT                 (0U)
/*! DMAFB - DMA Read (From-bus) trigger
 *  0b00..DMA not used
 *  0b01..DMA is enabled for 1 frame
 *  0b10..DMA enable
 *  0b11..
 */
#define I3C_SDMACTRL_DMAFB(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMAFB_SHIFT)) & I3C_SDMACTRL_DMAFB_MASK)

#define I3C_SDMACTRL_DMATB_MASK                  (0xCU)
#define I3C_SDMACTRL_DMATB_SHIFT                 (2U)
/*! DMATB - DMA Write (To-bus) trigger
 *  0b00..NOT_USED
 *  0b01..ENABLE_ONE_FRAME
 *  0b10..ENABLE
 *  0b11..
 */
#define I3C_SDMACTRL_DMATB(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMATB_SHIFT)) & I3C_SDMACTRL_DMATB_MASK)

#define I3C_SDMACTRL_DMAWIDTH_MASK               (0x30U)
#define I3C_SDMACTRL_DMAWIDTH_SHIFT              (4U)
/*! DMAWIDTH - Width of DMA operations
 *  0b00, 0b01..BYTE, Default = 1
 *  0b10..HALF_WORD
 *  0b11..
 */
#define I3C_SDMACTRL_DMAWIDTH(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMAWIDTH_SHIFT)) & I3C_SDMACTRL_DMAWIDTH_MASK)
/*! @} */

/*! @name SDATACTRL - Slave Data Control */
/*! @{ */

#define I3C_SDATACTRL_FLUSHTB_MASK               (0x1U)
#define I3C_SDATACTRL_FLUSHTB_SHIFT              (0U)
/*! FLUSHTB - Flush the to-bus buffer/FIFO
 */
#define I3C_SDATACTRL_FLUSHTB(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_FLUSHTB_SHIFT)) & I3C_SDATACTRL_FLUSHTB_MASK)

#define I3C_SDATACTRL_FLUSHFB_MASK               (0x2U)
#define I3C_SDATACTRL_FLUSHFB_SHIFT              (1U)
/*! FLUSHFB - Flushes the from-bus buffer/FIFO
 */
#define I3C_SDATACTRL_FLUSHFB(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_FLUSHFB_SHIFT)) & I3C_SDATACTRL_FLUSHFB_MASK)

#define I3C_SDATACTRL_UNLOCK_MASK                (0x8U)
#define I3C_SDATACTRL_UNLOCK_SHIFT               (3U)
/*! UNLOCK - Unlock
 */
#define I3C_SDATACTRL_UNLOCK(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_UNLOCK_SHIFT)) & I3C_SDATACTRL_UNLOCK_MASK)

#define I3C_SDATACTRL_TXTRIG_MASK                (0x30U)
#define I3C_SDATACTRL_TXTRIG_SHIFT               (4U)
/*! TXTRIG - Trigger level for TX FIFO emptiness
 *  0b00..Trigger on empty
 *  0b01..Trigger on ¼ full or less
 *  0b10..Trigger on .5 full or less
 *  0b11..Trigger on 1 less than full or less (Default)
 */
#define I3C_SDATACTRL_TXTRIG(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXTRIG_SHIFT)) & I3C_SDATACTRL_TXTRIG_MASK)

#define I3C_SDATACTRL_RXTRIG_MASK                (0xC0U)
#define I3C_SDATACTRL_RXTRIG_SHIFT               (6U)
/*! RXTRIG - Trigger level for RX FIFO fullness
 *  0b00..Trigger on not empty
 *  0b01..Trigger on ¼ or more full
 *  0b10..Trigger on .5 or more full
 *  0b11..Trigger on 3/4 or more full
 */
#define I3C_SDATACTRL_RXTRIG(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXTRIG_SHIFT)) & I3C_SDATACTRL_RXTRIG_MASK)

#define I3C_SDATACTRL_TXCOUNT_MASK               (0x1F0000U)
#define I3C_SDATACTRL_TXCOUNT_SHIFT              (16U)
/*! TXCOUNT - Count of bytes in TX
 */
#define I3C_SDATACTRL_TXCOUNT(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXCOUNT_SHIFT)) & I3C_SDATACTRL_TXCOUNT_MASK)

#define I3C_SDATACTRL_RXCOUNT_MASK               (0x1F000000U)
#define I3C_SDATACTRL_RXCOUNT_SHIFT              (24U)
/*! RXCOUNT - Count of bytes in RX
 */
#define I3C_SDATACTRL_RXCOUNT(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXCOUNT_SHIFT)) & I3C_SDATACTRL_RXCOUNT_MASK)

#define I3C_SDATACTRL_TXFULL_MASK                (0x40000000U)
#define I3C_SDATACTRL_TXFULL_SHIFT               (30U)
/*! TXFULL - TX is full
 *  0b1..TX is full
 *  0b0..TX is not full
 */
#define I3C_SDATACTRL_TXFULL(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXFULL_SHIFT)) & I3C_SDATACTRL_TXFULL_MASK)

#define I3C_SDATACTRL_RXEMPTY_MASK               (0x80000000U)
#define I3C_SDATACTRL_RXEMPTY_SHIFT              (31U)
/*! RXEMPTY - RX is empty
 *  0b1..RX is empty
 *  0b0..RX is not empty
 */
#define I3C_SDATACTRL_RXEMPTY(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXEMPTY_SHIFT)) & I3C_SDATACTRL_RXEMPTY_MASK)
/*! @} */

/*! @name SWDATAB - Slave Write Data Byte */
/*! @{ */

#define I3C_SWDATAB_DATA_MASK                    (0xFFU)
#define I3C_SWDATAB_DATA_SHIFT                   (0U)
/*! DATA - The data byte to send to the master
 */
#define I3C_SWDATAB_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_DATA_SHIFT)) & I3C_SWDATAB_DATA_MASK)

#define I3C_SWDATAB_END_MASK                     (0x100U)
#define I3C_SWDATAB_END_SHIFT                    (8U)
/*! END - End
 */
#define I3C_SWDATAB_END(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_END_SHIFT)) & I3C_SWDATAB_END_MASK)

#define I3C_SWDATAB_END_ALSO_MASK                (0x10000U)
#define I3C_SWDATAB_END_ALSO_SHIFT               (16U)
/*! END_ALSO - End also
 */
#define I3C_SWDATAB_END_ALSO(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_END_ALSO_SHIFT)) & I3C_SWDATAB_END_ALSO_MASK)
/*! @} */

/*! @name SWDATABE - Slave Write Data Byte End */
/*! @{ */

#define I3C_SWDATABE_DATA_MASK                   (0xFFU)
#define I3C_SWDATABE_DATA_SHIFT                  (0U)
/*! DATA - The data byte to send to the master
 */
#define I3C_SWDATABE_DATA(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SWDATABE_DATA_SHIFT)) & I3C_SWDATABE_DATA_MASK)
/*! @} */

/*! @name SWDATAH - Slave Write Data Half-word */
/*! @{ */

#define I3C_SWDATAH_DATA0_MASK                   (0xFFU)
#define I3C_SWDATAH_DATA0_SHIFT                  (0U)
/*! DATA0 - The 1st byte to send to the master
 */
#define I3C_SWDATAH_DATA0(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_DATA0_SHIFT)) & I3C_SWDATAH_DATA0_MASK)

#define I3C_SWDATAH_DATA1_MASK                   (0xFF00U)
#define I3C_SWDATAH_DATA1_SHIFT                  (8U)
/*! DATA1 - The 2nd byte to send to the master
 */
#define I3C_SWDATAH_DATA1(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_DATA1_SHIFT)) & I3C_SWDATAH_DATA1_MASK)

#define I3C_SWDATAH_END_MASK                     (0x10000U)
#define I3C_SWDATAH_END_SHIFT                    (16U)
/*! END - End of message
 */
#define I3C_SWDATAH_END(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_END_SHIFT)) & I3C_SWDATAH_END_MASK)
/*! @} */

/*! @name SWDATAHE - Slave Write Data Half-word End */
/*! @{ */

#define I3C_SWDATAHE_DATA0_MASK                  (0xFFU)
#define I3C_SWDATAHE_DATA0_SHIFT                 (0U)
/*! DATA0 - The 1st byte to send to the master
 */
#define I3C_SWDATAHE_DATA0(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAHE_DATA0_SHIFT)) & I3C_SWDATAHE_DATA0_MASK)

#define I3C_SWDATAHE_DATA1_MASK                  (0xFF00U)
#define I3C_SWDATAHE_DATA1_SHIFT                 (8U)
/*! DATA1 - The 2nd byte to send to the master
 */
#define I3C_SWDATAHE_DATA1(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAHE_DATA1_SHIFT)) & I3C_SWDATAHE_DATA1_MASK)
/*! @} */

/*! @name SRDATAB - Slave Read Data Byte */
/*! @{ */

#define I3C_SRDATAB_DATA0_MASK                   (0xFFU)
#define I3C_SRDATAB_DATA0_SHIFT                  (0U)
/*! DATA0 - Byte read from the master
 */
#define I3C_SRDATAB_DATA0(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAB_DATA0_SHIFT)) & I3C_SRDATAB_DATA0_MASK)
/*! @} */

/*! @name SRDATAH - Slave Read Data Half-word */
/*! @{ */

#define I3C_SRDATAH_LSB_MASK                     (0xFFU)
#define I3C_SRDATAH_LSB_SHIFT                    (0U)
/*! LSB - The 1st byte read from the slave
 */
#define I3C_SRDATAH_LSB(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAH_LSB_SHIFT)) & I3C_SRDATAH_LSB_MASK)

#define I3C_SRDATAH_MSB_MASK                     (0xFF00U)
#define I3C_SRDATAH_MSB_SHIFT                    (8U)
/*! MSB - The 2nd byte read from the slave
 */
#define I3C_SRDATAH_MSB(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAH_MSB_SHIFT)) & I3C_SRDATAH_MSB_MASK)
/*! @} */

/*! @name SCAPABILITIES2 - Slave Capabilities 2 */
/*! @{ */

#define I3C_SCAPABILITIES2_MAPCNT_MASK           (0xFU)
#define I3C_SCAPABILITIES2_MAPCNT_SHIFT          (0U)
/*! MAPCNT - Map Count
 */
#define I3C_SCAPABILITIES2_MAPCNT(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_MAPCNT_SHIFT)) & I3C_SCAPABILITIES2_MAPCNT_MASK)

#define I3C_SCAPABILITIES2_I2C10B_MASK           (0x10U)
#define I3C_SCAPABILITIES2_I2C10B_SHIFT          (4U)
/*! I2C10B - I2C 10-bit Address
 *  0b0..Does not support I2C10B
 *  0b1..Supports I2C10B
 */
#define I3C_SCAPABILITIES2_I2C10B(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2C10B_SHIFT)) & I3C_SCAPABILITIES2_I2C10B_MASK)

#define I3C_SCAPABILITIES2_I2CRST_MASK           (0x20U)
#define I3C_SCAPABILITIES2_I2CRST_SHIFT          (5U)
/*! I2CRST - I2C SW Reset
 *  0b0..Does not support I2CRST
 *  0b1..Supports I2CRST
 */
#define I3C_SCAPABILITIES2_I2CRST(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2CRST_SHIFT)) & I3C_SCAPABILITIES2_I2CRST_MASK)

#define I3C_SCAPABILITIES2_I2CDEVID_MASK         (0x40U)
#define I3C_SCAPABILITIES2_I2CDEVID_SHIFT        (6U)
/*! I2CDEVID - I2C Device ID
 *  0b0..Does not support I2CDEVID
 *  0b1..Supports I2CDEVID
 */
#define I3C_SCAPABILITIES2_I2CDEVID(x)           (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2CDEVID_SHIFT)) & I3C_SCAPABILITIES2_I2CDEVID_MASK)

#define I3C_SCAPABILITIES2_IBIEXT_MASK           (0x100U)
#define I3C_SCAPABILITIES2_IBIEXT_SHIFT          (8U)
/*! IBIEXT - In-Band Interrupt EXTDATA
 *  0b0..Does not support IBIEXT
 *  0b1..Supports IBIEXT
 */
#define I3C_SCAPABILITIES2_IBIEXT(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_IBIEXT_SHIFT)) & I3C_SCAPABILITIES2_IBIEXT_MASK)

#define I3C_SCAPABILITIES2_IBIXREG_MASK          (0x200U)
#define I3C_SCAPABILITIES2_IBIXREG_SHIFT         (9U)
/*! IBIXREG - In-Band Interrupt Extended Register
 *  0b0..Does not support IBIXREG
 *  0b1..Supports IBIXREG
 */
#define I3C_SCAPABILITIES2_IBIXREG(x)            (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_IBIXREG_SHIFT)) & I3C_SCAPABILITIES2_IBIXREG_MASK)

#define I3C_SCAPABILITIES2_SLVRST_MASK           (0x20000U)
#define I3C_SCAPABILITIES2_SLVRST_SHIFT          (17U)
/*! SLVRST - Slave Reset
 *  0b0..Does not support Slave Reset
 *  0b1..Supports Slave Reset
 */
#define I3C_SCAPABILITIES2_SLVRST(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_SLVRST_SHIFT)) & I3C_SCAPABILITIES2_SLVRST_MASK)

#define I3C_SCAPABILITIES2_GROUP_MASK            (0xC0000U)
#define I3C_SCAPABILITIES2_GROUP_SHIFT           (18U)
/*! GROUP - GROUP
 *  0b00..Does not supports v1.1 Group addressing
 *  0b01..Supports one group
 *  0b10..Supports two groups
 *  0b11..Supports three groups
 */
#define I3C_SCAPABILITIES2_GROUP(x)              (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_GROUP_SHIFT)) & I3C_SCAPABILITIES2_GROUP_MASK)

#define I3C_SCAPABILITIES2_AASA_MASK             (0x200000U)
#define I3C_SCAPABILITIES2_AASA_SHIFT            (21U)
/*! AASA - Supports SETAASA
 */
#define I3C_SCAPABILITIES2_AASA(x)               (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_AASA_SHIFT)) & I3C_SCAPABILITIES2_AASA_MASK)

#define I3C_SCAPABILITIES2_SSTSUB_MASK           (0x400000U)
#define I3C_SCAPABILITIES2_SSTSUB_SHIFT          (22U)
/*! SSTSUB - Slave-Slave(s)-Tunnel subscriber capable
 */
#define I3C_SCAPABILITIES2_SSTSUB(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_SSTSUB_SHIFT)) & I3C_SCAPABILITIES2_SSTSUB_MASK)

#define I3C_SCAPABILITIES2_SSTWR_MASK            (0x800000U)
#define I3C_SCAPABILITIES2_SSTWR_SHIFT           (23U)
/*! SSTWR - Slave-Slave(s)-Tunnel write capable
 */
#define I3C_SCAPABILITIES2_SSTWR(x)              (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_SSTWR_SHIFT)) & I3C_SCAPABILITIES2_SSTWR_MASK)
/*! @} */

/*! @name SCAPABILITIES - Slave Capabilities */
/*! @{ */

#define I3C_SCAPABILITIES_IDENA_MASK             (0x3U)
#define I3C_SCAPABILITIES_IDENA_SHIFT            (0U)
/*! IDENA - ID 48b handler
 *  0b00..APPLICATION
 *  0b01..HW
 *  0b10..HW_BUT
 *  0b11..PARTNO
 */
#define I3C_SCAPABILITIES_IDENA(x)               (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IDENA_SHIFT)) & I3C_SCAPABILITIES_IDENA_MASK)

#define I3C_SCAPABILITIES_IDREG_MASK             (0x3CU)
#define I3C_SCAPABILITIES_IDREG_SHIFT            (2U)
/*! IDREG - ID register
 */
#define I3C_SCAPABILITIES_IDREG(x)               (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IDREG_SHIFT)) & I3C_SCAPABILITIES_IDREG_MASK)

#define I3C_SCAPABILITIES_HDRSUPP_MASK           (0xC0U)
#define I3C_SCAPABILITIES_HDRSUPP_SHIFT          (6U)
/*! HDRSUPP - HDR support
 */
#define I3C_SCAPABILITIES_HDRSUPP(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_HDRSUPP_SHIFT)) & I3C_SCAPABILITIES_HDRSUPP_MASK)

#define I3C_SCAPABILITIES_MASTER_MASK            (0x200U)
#define I3C_SCAPABILITIES_MASTER_SHIFT           (9U)
/*! MASTER - Master
 *  0b0..MASTERNOTSUPPORTED
 *  0b1..MASTERSUPPORTED
 */
#define I3C_SCAPABILITIES_MASTER(x)              (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_MASTER_SHIFT)) & I3C_SCAPABILITIES_MASTER_MASK)

#define I3C_SCAPABILITIES_SADDR_MASK             (0xC00U)
#define I3C_SCAPABILITIES_SADDR_SHIFT            (10U)
/*! SADDR - Static address
 *  0b00..NO_STATIC
 *  0b01..STATIC
 *  0b10..HW_CONTROL
 *  0b11..CONFIG
 */
#define I3C_SCAPABILITIES_SADDR(x)               (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_SADDR_SHIFT)) & I3C_SCAPABILITIES_SADDR_MASK)

#define I3C_SCAPABILITIES_CCCHANDLE_MASK         (0xF000U)
#define I3C_SCAPABILITIES_CCCHANDLE_SHIFT        (12U)
/*! CCCHANDLE - Common Command Codes (CCC) handling
 */
#define I3C_SCAPABILITIES_CCCHANDLE(x)           (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_CCCHANDLE_SHIFT)) & I3C_SCAPABILITIES_CCCHANDLE_MASK)

#define I3C_SCAPABILITIES_IBI_MR_HJ_MASK         (0x1F0000U)
#define I3C_SCAPABILITIES_IBI_MR_HJ_SHIFT        (16U)
/*! IBI_MR_HJ - In-Band Interrupts, Master Requests, Hot Join events
 */
#define I3C_SCAPABILITIES_IBI_MR_HJ(x)           (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IBI_MR_HJ_SHIFT)) & I3C_SCAPABILITIES_IBI_MR_HJ_MASK)

#define I3C_SCAPABILITIES_TIMECTRL_MASK          (0x200000U)
#define I3C_SCAPABILITIES_TIMECTRL_SHIFT         (21U)
/*! TIMECTRL - Time control
 *  0b0..NO_TIME_CONTROL_TYPE
 *  0b1..ATLEAST1_TIME_CONTROL
 */
#define I3C_SCAPABILITIES_TIMECTRL(x)            (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_TIMECTRL_SHIFT)) & I3C_SCAPABILITIES_TIMECTRL_MASK)

#define I3C_SCAPABILITIES_EXTFIFO_MASK           (0x3800000U)
#define I3C_SCAPABILITIES_EXTFIFO_SHIFT          (23U)
/*! EXTFIFO - External FIFO
 *  0b000..NO_EXT_FIFO
 *  0b001..STD_EXT_FIFO
 *  0b010..REQUEST_EXT_FIFO
 *  0b011..
 */
#define I3C_SCAPABILITIES_EXTFIFO(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_EXTFIFO_SHIFT)) & I3C_SCAPABILITIES_EXTFIFO_MASK)

#define I3C_SCAPABILITIES_FIFOTX_MASK            (0xC000000U)
#define I3C_SCAPABILITIES_FIFOTX_SHIFT           (26U)
/*! FIFOTX - FIFO transmit
 *  0b00..FIFO_2BYTE
 *  0b01..FIFO_4BYTE: 4-byte TX FIFO
 *  0b10..FIFO_8BYTE: 8-byte TX FIFO
 *  0b11..FIFO_16BYTE: 16-byte TX FIFO or larger
 */
#define I3C_SCAPABILITIES_FIFOTX(x)              (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_FIFOTX_SHIFT)) & I3C_SCAPABILITIES_FIFOTX_MASK)

#define I3C_SCAPABILITIES_FIFORX_MASK            (0x30000000U)
#define I3C_SCAPABILITIES_FIFORX_SHIFT           (28U)
/*! FIFORX - FIFO receive
 *  0b00..FIFO_2BYTE
 *  0b01..FIFO_4BYTE
 *  0b10..FIFO_8BYTE
 *  0b11..FIFO_16BYTE
 */
#define I3C_SCAPABILITIES_FIFORX(x)              (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_FIFORX_SHIFT)) & I3C_SCAPABILITIES_FIFORX_MASK)

#define I3C_SCAPABILITIES_INT_MASK               (0x40000000U)
#define I3C_SCAPABILITIES_INT_SHIFT              (30U)
/*! INT - INT
 *  0b1..Interrupts are supported
 *  0b0..Interrupts are not supported
 */
#define I3C_SCAPABILITIES_INT(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_INT_SHIFT)) & I3C_SCAPABILITIES_INT_MASK)

#define I3C_SCAPABILITIES_DMA_MASK               (0x80000000U)
#define I3C_SCAPABILITIES_DMA_SHIFT              (31U)
/*! DMA - DMA
 *  0b1..DMA is supported
 *  0b0..DMA is not supported
 */
#define I3C_SCAPABILITIES_DMA(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_DMA_SHIFT)) & I3C_SCAPABILITIES_DMA_MASK)
/*! @} */

/*! @name SDYNADDR - Slave Dynamic Address */
/*! @{ */

#define I3C_SDYNADDR_DAVALID_MASK                (0x1U)
#define I3C_SDYNADDR_DAVALID_SHIFT               (0U)
/*! DAVALID - DAVALID
 *  0b0..DANOTASSIGNED: a Dynamic Address is not assigned
 *  0b1..DAASSIGNED: a Dynamic Address is assigned
 */
#define I3C_SDYNADDR_DAVALID(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_DAVALID_SHIFT)) & I3C_SDYNADDR_DAVALID_MASK)

#define I3C_SDYNADDR_DADDR_MASK                  (0xFEU)
#define I3C_SDYNADDR_DADDR_SHIFT                 (1U)
/*! DADDR - Dynamic address
 */
#define I3C_SDYNADDR_DADDR(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_DADDR_SHIFT)) & I3C_SDYNADDR_DADDR_MASK)

#define I3C_SDYNADDR_MAPSA_MASK                  (0x1000U)
#define I3C_SDYNADDR_MAPSA_SHIFT                 (12U)
/*! MAPSA - Map a Static Address
 */
#define I3C_SDYNADDR_MAPSA(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_MAPSA_SHIFT)) & I3C_SDYNADDR_MAPSA_MASK)

#define I3C_SDYNADDR_SA10B_MASK                  (0xE000U)
#define I3C_SDYNADDR_SA10B_SHIFT                 (13U)
/*! SA10B - 10bit Static Address
 */
#define I3C_SDYNADDR_SA10B(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_SA10B_SHIFT)) & I3C_SDYNADDR_SA10B_MASK)

#define I3C_SDYNADDR_KEY_MASK                    (0xFFFF0000U)
#define I3C_SDYNADDR_KEY_SHIFT                   (16U)
/*! KEY - Key
 */
#define I3C_SDYNADDR_KEY(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_KEY_SHIFT)) & I3C_SDYNADDR_KEY_MASK)
/*! @} */

/*! @name SMAXLIMITS - Slave Maximum Limits */
/*! @{ */

#define I3C_SMAXLIMITS_MAXRD_MASK                (0xFFFU)
#define I3C_SMAXLIMITS_MAXRD_SHIFT               (0U)
/*! MAXRD - Maximum read length
 */
#define I3C_SMAXLIMITS_MAXRD(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SMAXLIMITS_MAXRD_SHIFT)) & I3C_SMAXLIMITS_MAXRD_MASK)

#define I3C_SMAXLIMITS_MAXWR_MASK                (0xFFF0000U)
#define I3C_SMAXLIMITS_MAXWR_SHIFT               (16U)
/*! MAXWR - Maximum write length
 */
#define I3C_SMAXLIMITS_MAXWR(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SMAXLIMITS_MAXWR_SHIFT)) & I3C_SMAXLIMITS_MAXWR_MASK)
/*! @} */

/*! @name SIDPARTNO - Slave ID Part Number */
/*! @{ */

#define I3C_SIDPARTNO_PARTNO_MASK                (0xFFFFFFFFU)
#define I3C_SIDPARTNO_PARTNO_SHIFT               (0U)
/*! PARTNO - Part number
 */
#define I3C_SIDPARTNO_PARTNO(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SIDPARTNO_PARTNO_SHIFT)) & I3C_SIDPARTNO_PARTNO_MASK)
/*! @} */

/*! @name SIDEXT - Slave ID Extension */
/*! @{ */

#define I3C_SIDEXT_DCR_MASK                      (0xFF00U)
#define I3C_SIDEXT_DCR_SHIFT                     (8U)
/*! DCR - Device Characteristic Register
 */
#define I3C_SIDEXT_DCR(x)                        (((uint32_t)(((uint32_t)(x)) << I3C_SIDEXT_DCR_SHIFT)) & I3C_SIDEXT_DCR_MASK)

#define I3C_SIDEXT_BCR_MASK                      (0xFF0000U)
#define I3C_SIDEXT_BCR_SHIFT                     (16U)
/*! BCR - Bus Characteristics Register
 */
#define I3C_SIDEXT_BCR(x)                        (((uint32_t)(((uint32_t)(x)) << I3C_SIDEXT_BCR_SHIFT)) & I3C_SIDEXT_BCR_MASK)
/*! @} */

/*! @name SVENDORID - Slave Vendor ID */
/*! @{ */

#define I3C_SVENDORID_VID_MASK                   (0x7FFFU)
#define I3C_SVENDORID_VID_SHIFT                  (0U)
/*! VID - Vendor ID
 */
#define I3C_SVENDORID_VID(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SVENDORID_VID_SHIFT)) & I3C_SVENDORID_VID_MASK)
/*! @} */

/*! @name STCCLOCK - Slave Time Control Clock */
/*! @{ */

#define I3C_STCCLOCK_ACCURACY_MASK               (0xFFU)
#define I3C_STCCLOCK_ACCURACY_SHIFT              (0U)
/*! ACCURACY - Clock accuracy
 */
#define I3C_STCCLOCK_ACCURACY(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_STCCLOCK_ACCURACY_SHIFT)) & I3C_STCCLOCK_ACCURACY_MASK)

#define I3C_STCCLOCK_FREQ_MASK                   (0xFF00U)
#define I3C_STCCLOCK_FREQ_SHIFT                  (8U)
/*! FREQ - Clock frequency
 */
#define I3C_STCCLOCK_FREQ(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_STCCLOCK_FREQ_SHIFT)) & I3C_STCCLOCK_FREQ_MASK)
/*! @} */

/*! @name SMSGMAPADDR - Slave Message Map Address */
/*! @{ */

#define I3C_SMSGMAPADDR_MAPLAST_MASK             (0xFU)
#define I3C_SMSGMAPADDR_MAPLAST_SHIFT            (0U)
/*! MAPLAST - Matched Address Index
 */
#define I3C_SMSGMAPADDR_MAPLAST(x)               (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLAST_SHIFT)) & I3C_SMSGMAPADDR_MAPLAST_MASK)

#define I3C_SMSGMAPADDR_LASTSTATIC_MASK          (0x10U)
#define I3C_SMSGMAPADDR_LASTSTATIC_SHIFT         (4U)
/*! LASTSTATIC - Last Static Address Matched
 */
#define I3C_SMSGMAPADDR_LASTSTATIC(x)            (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_LASTSTATIC_SHIFT)) & I3C_SMSGMAPADDR_LASTSTATIC_MASK)

#define I3C_SMSGMAPADDR_MAPLASTM1_MASK           (0xF00U)
#define I3C_SMSGMAPADDR_MAPLASTM1_SHIFT          (8U)
/*! MAPLASTM1 - Matched Previous Address Index 1
 */
#define I3C_SMSGMAPADDR_MAPLASTM1(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLASTM1_SHIFT)) & I3C_SMSGMAPADDR_MAPLASTM1_MASK)

#define I3C_SMSGMAPADDR_MAPLASTM2_MASK           (0xF0000U)
#define I3C_SMSGMAPADDR_MAPLASTM2_SHIFT          (16U)
/*! MAPLASTM2 - Matched Previous Index 2
 */
#define I3C_SMSGMAPADDR_MAPLASTM2(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLASTM2_SHIFT)) & I3C_SMSGMAPADDR_MAPLASTM2_MASK)
/*! @} */

/*! @name MCTRL - Master Main Control */
/*! @{ */

#define I3C_MCTRL_REQUEST_MASK                   (0x7U)
#define I3C_MCTRL_REQUEST_SHIFT                  (0U)
/*! REQUEST - Request
 *  0b000..NONE
 *  0b001..EMITSTARTADDR
 *  0b010..EMITSTOP
 *  0b011..IBIACKNACK
 *  0b100..PROCESSDAA
 *  0b101..
 *  0b110..FORCEEXIT and SLAVERESET
 *  0b111..AUTOIBI
 */
#define I3C_MCTRL_REQUEST(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_REQUEST_SHIFT)) & I3C_MCTRL_REQUEST_MASK)

#define I3C_MCTRL_TYPE_MASK                      (0x30U)
#define I3C_MCTRL_TYPE_SHIFT                     (4U)
/*! TYPE - Bus type with EmitStartAddr
 *  0b00..I3C
 *  0b01..I2C
 *  0b10..DDR
 *  0b11..
 */
#define I3C_MCTRL_TYPE(x)                        (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_TYPE_SHIFT)) & I3C_MCTRL_TYPE_MASK)

#define I3C_MCTRL_IBIRESP_MASK                   (0xC0U)
#define I3C_MCTRL_IBIRESP_SHIFT                  (6U)
/*! IBIRESP - In-Band Interrupt (IBI) response
 *  0b00..ACK
 *  0b01..NACK
 *  0b10..ACK_WITH_MANDATORY
 *  0b11..MANUAL
 */
#define I3C_MCTRL_IBIRESP(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_IBIRESP_SHIFT)) & I3C_MCTRL_IBIRESP_MASK)

#define I3C_MCTRL_DIR_MASK                       (0x100U)
#define I3C_MCTRL_DIR_SHIFT                      (8U)
/*! DIR - DIR
 *  0b0..DIRWRITE: Write
 *  0b1..DIRREAD: Read
 */
#define I3C_MCTRL_DIR(x)                         (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_DIR_SHIFT)) & I3C_MCTRL_DIR_MASK)

#define I3C_MCTRL_ADDR_MASK                      (0xFE00U)
#define I3C_MCTRL_ADDR_SHIFT                     (9U)
/*! ADDR - Address
 */
#define I3C_MCTRL_ADDR(x)                        (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_ADDR_SHIFT)) & I3C_MCTRL_ADDR_MASK)

#define I3C_MCTRL_RDTERM_MASK                    (0xFF0000U)
#define I3C_MCTRL_RDTERM_SHIFT                   (16U)
/*! RDTERM - Read terminate
 */
#define I3C_MCTRL_RDTERM(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_RDTERM_SHIFT)) & I3C_MCTRL_RDTERM_MASK)
/*! @} */

/*! @name MSTATUS - Master Status */
/*! @{ */

#define I3C_MSTATUS_STATE_MASK                   (0x7U)
#define I3C_MSTATUS_STATE_SHIFT                  (0U)
/*! STATE - State of the master
 *  0b000..IDLE: the bus has STOPped.
 *  0b001..SLVREQ
 *  0b010..MSGSDR
 *  0b011..NORMACT
 *  0b100..MSGDDR
 *  0b101..DAA
 *  0b110..IBIACK
 *  0b111..IBIRCV
 */
#define I3C_MSTATUS_STATE(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_STATE_SHIFT)) & I3C_MSTATUS_STATE_MASK)

#define I3C_MSTATUS_BETWEEN_MASK                 (0x10U)
#define I3C_MSTATUS_BETWEEN_SHIFT                (4U)
/*! BETWEEN - Between
 *  0b0..Inactive
 *  0b1..Active
 */
#define I3C_MSTATUS_BETWEEN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_BETWEEN_SHIFT)) & I3C_MSTATUS_BETWEEN_MASK)

#define I3C_MSTATUS_NACKED_MASK                  (0x20U)
#define I3C_MSTATUS_NACKED_SHIFT                 (5U)
/*! NACKED - Not acknowledged
 */
#define I3C_MSTATUS_NACKED(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_NACKED_SHIFT)) & I3C_MSTATUS_NACKED_MASK)

#define I3C_MSTATUS_IBITYPE_MASK                 (0xC0U)
#define I3C_MSTATUS_IBITYPE_SHIFT                (6U)
/*! IBITYPE - In-Band Interrupt (IBI) type
 *  0b00..NONE
 *  0b01..IBI
 *  0b10..MR
 *  0b11..HJ
 */
#define I3C_MSTATUS_IBITYPE(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBITYPE_SHIFT)) & I3C_MSTATUS_IBITYPE_MASK)

#define I3C_MSTATUS_SLVSTART_MASK                (0x100U)
#define I3C_MSTATUS_SLVSTART_SHIFT               (8U)
/*! SLVSTART - Slave start
 */
#define I3C_MSTATUS_SLVSTART(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_SLVSTART_SHIFT)) & I3C_MSTATUS_SLVSTART_MASK)

#define I3C_MSTATUS_MCTRLDONE_MASK               (0x200U)
#define I3C_MSTATUS_MCTRLDONE_SHIFT              (9U)
/*! MCTRLDONE - Master control done
 */
#define I3C_MSTATUS_MCTRLDONE(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_MCTRLDONE_SHIFT)) & I3C_MSTATUS_MCTRLDONE_MASK)

#define I3C_MSTATUS_COMPLETE_MASK                (0x400U)
#define I3C_MSTATUS_COMPLETE_SHIFT               (10U)
/*! COMPLETE - COMPLETE
 */
#define I3C_MSTATUS_COMPLETE(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_COMPLETE_SHIFT)) & I3C_MSTATUS_COMPLETE_MASK)

#define I3C_MSTATUS_RXPEND_MASK                  (0x800U)
#define I3C_MSTATUS_RXPEND_SHIFT                 (11U)
/*! RXPEND - RXPEND
 */
#define I3C_MSTATUS_RXPEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_RXPEND_SHIFT)) & I3C_MSTATUS_RXPEND_MASK)

#define I3C_MSTATUS_TXNOTFULL_MASK               (0x1000U)
#define I3C_MSTATUS_TXNOTFULL_SHIFT              (12U)
/*! TXNOTFULL - TX buffer/FIFO not yet full
 */
#define I3C_MSTATUS_TXNOTFULL(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_TXNOTFULL_SHIFT)) & I3C_MSTATUS_TXNOTFULL_MASK)

#define I3C_MSTATUS_IBIWON_MASK                  (0x2000U)
#define I3C_MSTATUS_IBIWON_SHIFT                 (13U)
/*! IBIWON - In-Band Interrupt (IBI) won
 */
#define I3C_MSTATUS_IBIWON(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBIWON_SHIFT)) & I3C_MSTATUS_IBIWON_MASK)

#define I3C_MSTATUS_ERRWARN_MASK                 (0x8000U)
#define I3C_MSTATUS_ERRWARN_SHIFT                (15U)
/*! ERRWARN - Error or warning
 */
#define I3C_MSTATUS_ERRWARN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_ERRWARN_SHIFT)) & I3C_MSTATUS_ERRWARN_MASK)

#define I3C_MSTATUS_NOWMASTER_MASK               (0x80000U)
#define I3C_MSTATUS_NOWMASTER_SHIFT              (19U)
/*! NOWMASTER - Now master (now this module is a master)
 */
#define I3C_MSTATUS_NOWMASTER(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_NOWMASTER_SHIFT)) & I3C_MSTATUS_NOWMASTER_MASK)

#define I3C_MSTATUS_IBIADDR_MASK                 (0x7F000000U)
#define I3C_MSTATUS_IBIADDR_SHIFT                (24U)
/*! IBIADDR - IBI address
 */
#define I3C_MSTATUS_IBIADDR(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBIADDR_SHIFT)) & I3C_MSTATUS_IBIADDR_MASK)
/*! @} */

/*! @name MIBIRULES - Master In-band Interrupt Registry and Rules */
/*! @{ */

#define I3C_MIBIRULES_ADDR0_MASK                 (0x3FU)
#define I3C_MIBIRULES_ADDR0_SHIFT                (0U)
/*! ADDR0 - ADDR0
 */
#define I3C_MIBIRULES_ADDR0(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR0_SHIFT)) & I3C_MIBIRULES_ADDR0_MASK)

#define I3C_MIBIRULES_ADDR1_MASK                 (0xFC0U)
#define I3C_MIBIRULES_ADDR1_SHIFT                (6U)
/*! ADDR1 - ADDR1
 */
#define I3C_MIBIRULES_ADDR1(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR1_SHIFT)) & I3C_MIBIRULES_ADDR1_MASK)

#define I3C_MIBIRULES_ADDR2_MASK                 (0x3F000U)
#define I3C_MIBIRULES_ADDR2_SHIFT                (12U)
/*! ADDR2 - ADDR2
 */
#define I3C_MIBIRULES_ADDR2(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR2_SHIFT)) & I3C_MIBIRULES_ADDR2_MASK)

#define I3C_MIBIRULES_ADDR3_MASK                 (0xFC0000U)
#define I3C_MIBIRULES_ADDR3_SHIFT                (18U)
/*! ADDR3 - ADDR3
 */
#define I3C_MIBIRULES_ADDR3(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR3_SHIFT)) & I3C_MIBIRULES_ADDR3_MASK)

#define I3C_MIBIRULES_ADDR4_MASK                 (0x3F000000U)
#define I3C_MIBIRULES_ADDR4_SHIFT                (24U)
/*! ADDR4 - ADDR4
 */
#define I3C_MIBIRULES_ADDR4(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR4_SHIFT)) & I3C_MIBIRULES_ADDR4_MASK)

#define I3C_MIBIRULES_MSB0_MASK                  (0x40000000U)
#define I3C_MIBIRULES_MSB0_SHIFT                 (30U)
/*! MSB0 - Set Most Significant address Bit to 0
 */
#define I3C_MIBIRULES_MSB0(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_MSB0_SHIFT)) & I3C_MIBIRULES_MSB0_MASK)

#define I3C_MIBIRULES_NOBYTE_MASK                (0x80000000U)
#define I3C_MIBIRULES_NOBYTE_SHIFT               (31U)
/*! NOBYTE - No IBI byte
 */
#define I3C_MIBIRULES_NOBYTE(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_NOBYTE_SHIFT)) & I3C_MIBIRULES_NOBYTE_MASK)
/*! @} */

/*! @name MINTSET - Master Interrupt Set */
/*! @{ */

#define I3C_MINTSET_SLVSTART_MASK                (0x100U)
#define I3C_MINTSET_SLVSTART_SHIFT               (8U)
/*! SLVSTART - Slave start interrupt enable
 */
#define I3C_MINTSET_SLVSTART(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_SLVSTART_SHIFT)) & I3C_MINTSET_SLVSTART_MASK)

#define I3C_MINTSET_MCTRLDONE_MASK               (0x200U)
#define I3C_MINTSET_MCTRLDONE_SHIFT              (9U)
/*! MCTRLDONE - Master control done interrupt enable
 */
#define I3C_MINTSET_MCTRLDONE(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_MCTRLDONE_SHIFT)) & I3C_MINTSET_MCTRLDONE_MASK)

#define I3C_MINTSET_COMPLETE_MASK                (0x400U)
#define I3C_MINTSET_COMPLETE_SHIFT               (10U)
/*! COMPLETE - Completed message interrupt enable
 */
#define I3C_MINTSET_COMPLETE(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_COMPLETE_SHIFT)) & I3C_MINTSET_COMPLETE_MASK)

#define I3C_MINTSET_RXPEND_MASK                  (0x800U)
#define I3C_MINTSET_RXPEND_SHIFT                 (11U)
/*! RXPEND - RX pending interrupt enable
 */
#define I3C_MINTSET_RXPEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_RXPEND_SHIFT)) & I3C_MINTSET_RXPEND_MASK)

#define I3C_MINTSET_TXNOTFULL_MASK               (0x1000U)
#define I3C_MINTSET_TXNOTFULL_SHIFT              (12U)
/*! TXNOTFULL - TX buffer/FIFO is not full interrupt enable
 */
#define I3C_MINTSET_TXNOTFULL(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_TXNOTFULL_SHIFT)) & I3C_MINTSET_TXNOTFULL_MASK)

#define I3C_MINTSET_IBIWON_MASK                  (0x2000U)
#define I3C_MINTSET_IBIWON_SHIFT                 (13U)
/*! IBIWON - In-Band Interrupt (IBI) won interrupt enable
 */
#define I3C_MINTSET_IBIWON(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_IBIWON_SHIFT)) & I3C_MINTSET_IBIWON_MASK)

#define I3C_MINTSET_ERRWARN_MASK                 (0x8000U)
#define I3C_MINTSET_ERRWARN_SHIFT                (15U)
/*! ERRWARN - Error or warning (ERRWARN) interrupt enable
 */
#define I3C_MINTSET_ERRWARN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_ERRWARN_SHIFT)) & I3C_MINTSET_ERRWARN_MASK)

#define I3C_MINTSET_NOWMASTER_MASK               (0x80000U)
#define I3C_MINTSET_NOWMASTER_SHIFT              (19U)
/*! NOWMASTER - Now master (now this I3C module is a master) interrupt enable
 */
#define I3C_MINTSET_NOWMASTER(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_NOWMASTER_SHIFT)) & I3C_MINTSET_NOWMASTER_MASK)
/*! @} */

/*! @name MINTCLR - Master Interrupt Clear */
/*! @{ */

#define I3C_MINTCLR_SLVSTART_MASK                (0x100U)
#define I3C_MINTCLR_SLVSTART_SHIFT               (8U)
/*! SLVSTART - SLVSTART interrupt enable clear
 */
#define I3C_MINTCLR_SLVSTART(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_SLVSTART_SHIFT)) & I3C_MINTCLR_SLVSTART_MASK)

#define I3C_MINTCLR_MCTRLDONE_MASK               (0x200U)
#define I3C_MINTCLR_MCTRLDONE_SHIFT              (9U)
/*! MCTRLDONE - MCTRLDONE interrupt enable clear
 */
#define I3C_MINTCLR_MCTRLDONE(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_MCTRLDONE_SHIFT)) & I3C_MINTCLR_MCTRLDONE_MASK)

#define I3C_MINTCLR_COMPLETE_MASK                (0x400U)
#define I3C_MINTCLR_COMPLETE_SHIFT               (10U)
/*! COMPLETE - COMPLETE interrupt enable clear
 */
#define I3C_MINTCLR_COMPLETE(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_COMPLETE_SHIFT)) & I3C_MINTCLR_COMPLETE_MASK)

#define I3C_MINTCLR_RXPEND_MASK                  (0x800U)
#define I3C_MINTCLR_RXPEND_SHIFT                 (11U)
/*! RXPEND - RXPEND interrupt enable clear
 */
#define I3C_MINTCLR_RXPEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_RXPEND_SHIFT)) & I3C_MINTCLR_RXPEND_MASK)

#define I3C_MINTCLR_TXNOTFULL_MASK               (0x1000U)
#define I3C_MINTCLR_TXNOTFULL_SHIFT              (12U)
/*! TXNOTFULL - TXNOTFULL interrupt enable clear
 */
#define I3C_MINTCLR_TXNOTFULL(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_TXNOTFULL_SHIFT)) & I3C_MINTCLR_TXNOTFULL_MASK)

#define I3C_MINTCLR_IBIWON_MASK                  (0x2000U)
#define I3C_MINTCLR_IBIWON_SHIFT                 (13U)
/*! IBIWON - IBIWON interrupt enable clear
 */
#define I3C_MINTCLR_IBIWON(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_IBIWON_SHIFT)) & I3C_MINTCLR_IBIWON_MASK)

#define I3C_MINTCLR_ERRWARN_MASK                 (0x8000U)
#define I3C_MINTCLR_ERRWARN_SHIFT                (15U)
/*! ERRWARN - ERRWARN interrupt enable clear
 */
#define I3C_MINTCLR_ERRWARN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_ERRWARN_SHIFT)) & I3C_MINTCLR_ERRWARN_MASK)

#define I3C_MINTCLR_NOWMASTER_MASK               (0x80000U)
#define I3C_MINTCLR_NOWMASTER_SHIFT              (19U)
/*! NOWMASTER - NOWMASTER interrupt enable clear
 */
#define I3C_MINTCLR_NOWMASTER(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_NOWMASTER_SHIFT)) & I3C_MINTCLR_NOWMASTER_MASK)
/*! @} */

/*! @name MINTMASKED - Master Interrupt Mask */
/*! @{ */

#define I3C_MINTMASKED_SLVSTART_MASK             (0x100U)
#define I3C_MINTMASKED_SLVSTART_SHIFT            (8U)
/*! SLVSTART - SLVSTART interrupt mask
 */
#define I3C_MINTMASKED_SLVSTART(x)               (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_SLVSTART_SHIFT)) & I3C_MINTMASKED_SLVSTART_MASK)

#define I3C_MINTMASKED_MCTRLDONE_MASK            (0x200U)
#define I3C_MINTMASKED_MCTRLDONE_SHIFT           (9U)
/*! MCTRLDONE - MCTRLDONE interrupt mask
 */
#define I3C_MINTMASKED_MCTRLDONE(x)              (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_MCTRLDONE_SHIFT)) & I3C_MINTMASKED_MCTRLDONE_MASK)

#define I3C_MINTMASKED_COMPLETE_MASK             (0x400U)
#define I3C_MINTMASKED_COMPLETE_SHIFT            (10U)
/*! COMPLETE - COMPLETE interrupt mask
 */
#define I3C_MINTMASKED_COMPLETE(x)               (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_COMPLETE_SHIFT)) & I3C_MINTMASKED_COMPLETE_MASK)

#define I3C_MINTMASKED_RXPEND_MASK               (0x800U)
#define I3C_MINTMASKED_RXPEND_SHIFT              (11U)
/*! RXPEND - RXPEND interrupt mask
 */
#define I3C_MINTMASKED_RXPEND(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_RXPEND_SHIFT)) & I3C_MINTMASKED_RXPEND_MASK)

#define I3C_MINTMASKED_TXNOTFULL_MASK            (0x1000U)
#define I3C_MINTMASKED_TXNOTFULL_SHIFT           (12U)
/*! TXNOTFULL - TXNOTFULL interrupt mask
 */
#define I3C_MINTMASKED_TXNOTFULL(x)              (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_TXNOTFULL_SHIFT)) & I3C_MINTMASKED_TXNOTFULL_MASK)

#define I3C_MINTMASKED_IBIWON_MASK               (0x2000U)
#define I3C_MINTMASKED_IBIWON_SHIFT              (13U)
/*! IBIWON - IBIWON interrupt mask
 */
#define I3C_MINTMASKED_IBIWON(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_IBIWON_SHIFT)) & I3C_MINTMASKED_IBIWON_MASK)

#define I3C_MINTMASKED_ERRWARN_MASK              (0x8000U)
#define I3C_MINTMASKED_ERRWARN_SHIFT             (15U)
/*! ERRWARN - ERRWARN interrupt mask
 */
#define I3C_MINTMASKED_ERRWARN(x)                (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_ERRWARN_SHIFT)) & I3C_MINTMASKED_ERRWARN_MASK)

#define I3C_MINTMASKED_NOWMASTER_MASK            (0x80000U)
#define I3C_MINTMASKED_NOWMASTER_SHIFT           (19U)
/*! NOWMASTER - NOWMASTER interrupt mask
 */
#define I3C_MINTMASKED_NOWMASTER(x)              (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_NOWMASTER_SHIFT)) & I3C_MINTMASKED_NOWMASTER_MASK)
/*! @} */

/*! @name MERRWARN - Master Errors and Warnings */
/*! @{ */

#define I3C_MERRWARN_NACK_MASK                   (0x4U)
#define I3C_MERRWARN_NACK_SHIFT                  (2U)
/*! NACK - Not acknowledge (NACK) error
 */
#define I3C_MERRWARN_NACK(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_NACK_SHIFT)) & I3C_MERRWARN_NACK_MASK)

#define I3C_MERRWARN_WRABT_MASK                  (0x8U)
#define I3C_MERRWARN_WRABT_SHIFT                 (3U)
/*! WRABT - WRABT (Write abort) error
 */
#define I3C_MERRWARN_WRABT(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_WRABT_SHIFT)) & I3C_MERRWARN_WRABT_MASK)

#define I3C_MERRWARN_HPAR_MASK                   (0x200U)
#define I3C_MERRWARN_HPAR_SHIFT                  (9U)
/*! HPAR - High data rate parity
 */
#define I3C_MERRWARN_HPAR(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_HPAR_SHIFT)) & I3C_MERRWARN_HPAR_MASK)

#define I3C_MERRWARN_HCRC_MASK                   (0x400U)
#define I3C_MERRWARN_HCRC_SHIFT                  (10U)
/*! HCRC - High data rate CRC error
 */
#define I3C_MERRWARN_HCRC(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_HCRC_SHIFT)) & I3C_MERRWARN_HCRC_MASK)

#define I3C_MERRWARN_OREAD_MASK                  (0x10000U)
#define I3C_MERRWARN_OREAD_SHIFT                 (16U)
/*! OREAD - Over-read error
 */
#define I3C_MERRWARN_OREAD(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OREAD_SHIFT)) & I3C_MERRWARN_OREAD_MASK)

#define I3C_MERRWARN_OWRITE_MASK                 (0x20000U)
#define I3C_MERRWARN_OWRITE_SHIFT                (17U)
/*! OWRITE - Over-write error
 */
#define I3C_MERRWARN_OWRITE(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OWRITE_SHIFT)) & I3C_MERRWARN_OWRITE_MASK)

#define I3C_MERRWARN_MSGERR_MASK                 (0x40000U)
#define I3C_MERRWARN_MSGERR_SHIFT                (18U)
/*! MSGERR - Message error
 */
#define I3C_MERRWARN_MSGERR(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_MSGERR_SHIFT)) & I3C_MERRWARN_MSGERR_MASK)

#define I3C_MERRWARN_INVREQ_MASK                 (0x80000U)
#define I3C_MERRWARN_INVREQ_SHIFT                (19U)
/*! INVREQ - Invalid request error
 */
#define I3C_MERRWARN_INVREQ(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_INVREQ_SHIFT)) & I3C_MERRWARN_INVREQ_MASK)

#define I3C_MERRWARN_TIMEOUT_MASK                (0x100000U)
#define I3C_MERRWARN_TIMEOUT_SHIFT               (20U)
/*! TIMEOUT - TIMEOUT error
 */
#define I3C_MERRWARN_TIMEOUT(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_TIMEOUT_SHIFT)) & I3C_MERRWARN_TIMEOUT_MASK)
/*! @} */

/*! @name MDMACTRL - Master DMA Control */
/*! @{ */

#define I3C_MDMACTRL_DMAFB_MASK                  (0x3U)
#define I3C_MDMACTRL_DMAFB_SHIFT                 (0U)
/*! DMAFB - DMA from bus
 *  0b00..NOT_USED
 *  0b01..ENABLE_ONE_FRAME
 *  0b10..ENABLE
 *  0b11..
 */
#define I3C_MDMACTRL_DMAFB(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMAFB_SHIFT)) & I3C_MDMACTRL_DMAFB_MASK)

#define I3C_MDMACTRL_DMATB_MASK                  (0xCU)
#define I3C_MDMACTRL_DMATB_SHIFT                 (2U)
/*! DMATB - DMA to bus
 *  0b00..NOT_USED
 *  0b01..ENABLE_ONE_FRAME
 *  0b10..ENABLE
 *  0b11..
 */
#define I3C_MDMACTRL_DMATB(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMATB_SHIFT)) & I3C_MDMACTRL_DMATB_MASK)

#define I3C_MDMACTRL_DMAWIDTH_MASK               (0x30U)
#define I3C_MDMACTRL_DMAWIDTH_SHIFT              (4U)
/*! DMAWIDTH - DMA width
 *  0b00, 0b01..BYTE
 *  0b10..HALF_WORD
 *  0b11..
 */
#define I3C_MDMACTRL_DMAWIDTH(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMAWIDTH_SHIFT)) & I3C_MDMACTRL_DMAWIDTH_MASK)
/*! @} */

/*! @name MDATACTRL - Master Data Control */
/*! @{ */

#define I3C_MDATACTRL_FLUSHTB_MASK               (0x1U)
#define I3C_MDATACTRL_FLUSHTB_SHIFT              (0U)
/*! FLUSHTB - Flush to-bus buffer/FIFO
 */
#define I3C_MDATACTRL_FLUSHTB(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_FLUSHTB_SHIFT)) & I3C_MDATACTRL_FLUSHTB_MASK)

#define I3C_MDATACTRL_FLUSHFB_MASK               (0x2U)
#define I3C_MDATACTRL_FLUSHFB_SHIFT              (1U)
/*! FLUSHFB - Flush from-bus buffer/FIFO
 */
#define I3C_MDATACTRL_FLUSHFB(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_FLUSHFB_SHIFT)) & I3C_MDATACTRL_FLUSHFB_MASK)

#define I3C_MDATACTRL_UNLOCK_MASK                (0x8U)
#define I3C_MDATACTRL_UNLOCK_SHIFT               (3U)
/*! UNLOCK - Unlock
 */
#define I3C_MDATACTRL_UNLOCK(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_UNLOCK_SHIFT)) & I3C_MDATACTRL_UNLOCK_MASK)

#define I3C_MDATACTRL_TXTRIG_MASK                (0x30U)
#define I3C_MDATACTRL_TXTRIG_SHIFT               (4U)
/*! TXTRIG - TX trigger level
 *  0b00..Trigger on empty
 *  0b01..Trigger on 1/4 full or less
 *  0b10..Trigger on 1/2 full or less
 *  0b11..Default. Trigger on 1 less than full or less
 */
#define I3C_MDATACTRL_TXTRIG(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXTRIG_SHIFT)) & I3C_MDATACTRL_TXTRIG_MASK)

#define I3C_MDATACTRL_RXTRIG_MASK                (0xC0U)
#define I3C_MDATACTRL_RXTRIG_SHIFT               (6U)
/*! RXTRIG - RX trigger level
 *  0b00..Trigger on not empty
 *  0b01..Trigger on 1/4 full or more
 *  0b10..Trigger on 1/2 full or more
 *  0b11..Trigger on 3/4 full or more
 */
#define I3C_MDATACTRL_RXTRIG(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXTRIG_SHIFT)) & I3C_MDATACTRL_RXTRIG_MASK)

#define I3C_MDATACTRL_TXCOUNT_MASK               (0x1F0000U)
#define I3C_MDATACTRL_TXCOUNT_SHIFT              (16U)
/*! TXCOUNT - TX byte count
 */
#define I3C_MDATACTRL_TXCOUNT(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXCOUNT_SHIFT)) & I3C_MDATACTRL_TXCOUNT_MASK)

#define I3C_MDATACTRL_RXCOUNT_MASK               (0x1F000000U)
#define I3C_MDATACTRL_RXCOUNT_SHIFT              (24U)
/*! RXCOUNT - RX byte count
 */
#define I3C_MDATACTRL_RXCOUNT(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXCOUNT_SHIFT)) & I3C_MDATACTRL_RXCOUNT_MASK)

#define I3C_MDATACTRL_TXFULL_MASK                (0x40000000U)
#define I3C_MDATACTRL_TXFULL_SHIFT               (30U)
/*! TXFULL - TX is full.
 *  0b0..TX is not yet full.
 *  0b1..TX is full.
 */
#define I3C_MDATACTRL_TXFULL(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXFULL_SHIFT)) & I3C_MDATACTRL_TXFULL_MASK)

#define I3C_MDATACTRL_RXEMPTY_MASK               (0x80000000U)
#define I3C_MDATACTRL_RXEMPTY_SHIFT              (31U)
/*! RXEMPTY - RX is empty.
 *  0b0..RX is not yet empty.
 *  0b1..RX is empty.
 */
#define I3C_MDATACTRL_RXEMPTY(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXEMPTY_SHIFT)) & I3C_MDATACTRL_RXEMPTY_MASK)
/*! @} */

/*! @name MWDATAB - Master Write Data Byte */
/*! @{ */

#define I3C_MWDATAB_VALUE_MASK                   (0xFFU)
#define I3C_MWDATAB_VALUE_SHIFT                  (0U)
/*! VALUE - Data byte
 */
#define I3C_MWDATAB_VALUE(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_VALUE_SHIFT)) & I3C_MWDATAB_VALUE_MASK)

#define I3C_MWDATAB_END_MASK                     (0x100U)
#define I3C_MWDATAB_END_SHIFT                    (8U)
/*! END - End of message
 */
#define I3C_MWDATAB_END(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_END_SHIFT)) & I3C_MWDATAB_END_MASK)

#define I3C_MWDATAB_END_ALSO_MASK                (0x10000U)
#define I3C_MWDATAB_END_ALSO_SHIFT               (16U)
/*! END_ALSO - End of message also
 */
#define I3C_MWDATAB_END_ALSO(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_END_ALSO_SHIFT)) & I3C_MWDATAB_END_ALSO_MASK)
/*! @} */

/*! @name MWDATABE - Master Write Data Byte End */
/*! @{ */

#define I3C_MWDATABE_VALUE_MASK                  (0xFFU)
#define I3C_MWDATABE_VALUE_SHIFT                 (0U)
/*! VALUE - Data
 */
#define I3C_MWDATABE_VALUE(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MWDATABE_VALUE_SHIFT)) & I3C_MWDATABE_VALUE_MASK)
/*! @} */

/*! @name MWDATAH - Master Write Data Half-word */
/*! @{ */

#define I3C_MWDATAH_DATA0_MASK                   (0xFFU)
#define I3C_MWDATAH_DATA0_SHIFT                  (0U)
/*! DATA0 - Data byte 0
 */
#define I3C_MWDATAH_DATA0(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_DATA0_SHIFT)) & I3C_MWDATAH_DATA0_MASK)

#define I3C_MWDATAH_DATA1_MASK                   (0xFF00U)
#define I3C_MWDATAH_DATA1_SHIFT                  (8U)
/*! DATA1 - Data byte 1
 */
#define I3C_MWDATAH_DATA1(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_DATA1_SHIFT)) & I3C_MWDATAH_DATA1_MASK)

#define I3C_MWDATAH_END_MASK                     (0x10000U)
#define I3C_MWDATAH_END_SHIFT                    (16U)
/*! END - End of message
 */
#define I3C_MWDATAH_END(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_END_SHIFT)) & I3C_MWDATAH_END_MASK)
/*! @} */

/*! @name MWDATAHE - Master Write Data Byte End */
/*! @{ */

#define I3C_MWDATAHE_DATA0_MASK                  (0xFFU)
#define I3C_MWDATAHE_DATA0_SHIFT                 (0U)
/*! DATA0 - DATA 0
 */
#define I3C_MWDATAHE_DATA0(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAHE_DATA0_SHIFT)) & I3C_MWDATAHE_DATA0_MASK)

#define I3C_MWDATAHE_DATA1_MASK                  (0xFF00U)
#define I3C_MWDATAHE_DATA1_SHIFT                 (8U)
/*! DATA1 - DATA 1
 */
#define I3C_MWDATAHE_DATA1(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAHE_DATA1_SHIFT)) & I3C_MWDATAHE_DATA1_MASK)
/*! @} */

/*! @name MRDATAB - Master Read Data Byte */
/*! @{ */

#define I3C_MRDATAB_VALUE_MASK                   (0xFFU)
#define I3C_MRDATAB_VALUE_SHIFT                  (0U)
/*! VALUE - VALUE
 */
#define I3C_MRDATAB_VALUE(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAB_VALUE_SHIFT)) & I3C_MRDATAB_VALUE_MASK)
/*! @} */

/*! @name MRDATAH - Master Read Data Half-word */
/*! @{ */

#define I3C_MRDATAH_LSB_MASK                     (0xFFU)
#define I3C_MRDATAH_LSB_SHIFT                    (0U)
/*! LSB - LSB
 */
#define I3C_MRDATAH_LSB(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAH_LSB_SHIFT)) & I3C_MRDATAH_LSB_MASK)

#define I3C_MRDATAH_MSB_MASK                     (0xFF00U)
#define I3C_MRDATAH_MSB_SHIFT                    (8U)
/*! MSB - MSB
 */
#define I3C_MRDATAH_MSB(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAH_MSB_SHIFT)) & I3C_MRDATAH_MSB_MASK)
/*! @} */

/*! @name MWDATAB1 - Byte-only Write Byte Data (to bus) */
/*! @{ */

#define I3C_MWDATAB1_VALUE_MASK                  (0xFFU)
#define I3C_MWDATAB1_VALUE_SHIFT                 (0U)
/*! VALUE - Value
 */
#define I3C_MWDATAB1_VALUE(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB1_VALUE_SHIFT)) & I3C_MWDATAB1_VALUE_MASK)
/*! @} */

/*! @name MWMSG_SDR_CONTROL - Master Write Message in SDR mode */
/*! @{ */

#define I3C_MWMSG_SDR_CONTROL_DIR_MASK           (0x1U)
#define I3C_MWMSG_SDR_CONTROL_DIR_SHIFT          (0U)
/*! DIR - Direction
 *  0b0..Write
 *  0b1..Read
 */
#define I3C_MWMSG_SDR_CONTROL_DIR(x)             (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_DIR_SHIFT)) & I3C_MWMSG_SDR_CONTROL_DIR_MASK)

#define I3C_MWMSG_SDR_CONTROL_ADDR_MASK          (0xFEU)
#define I3C_MWMSG_SDR_CONTROL_ADDR_SHIFT         (1U)
/*! ADDR - Address to be written to
 */
#define I3C_MWMSG_SDR_CONTROL_ADDR(x)            (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_ADDR_SHIFT)) & I3C_MWMSG_SDR_CONTROL_ADDR_MASK)

#define I3C_MWMSG_SDR_CONTROL_END_MASK           (0x100U)
#define I3C_MWMSG_SDR_CONTROL_END_SHIFT          (8U)
/*! END - End of SDR message
 */
#define I3C_MWMSG_SDR_CONTROL_END(x)             (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_END_SHIFT)) & I3C_MWMSG_SDR_CONTROL_END_MASK)

#define I3C_MWMSG_SDR_CONTROL_I2C_MASK           (0x400U)
#define I3C_MWMSG_SDR_CONTROL_I2C_SHIFT          (10U)
/*! I2C - I2C
 *  0b0..I3C message
 *  0b1..I2C message
 */
#define I3C_MWMSG_SDR_CONTROL_I2C(x)             (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_I2C_SHIFT)) & I3C_MWMSG_SDR_CONTROL_I2C_MASK)

#define I3C_MWMSG_SDR_CONTROL_LEN_MASK           (0xF800U)
#define I3C_MWMSG_SDR_CONTROL_LEN_SHIFT          (11U)
/*! LEN - Length
 */
#define I3C_MWMSG_SDR_CONTROL_LEN(x)             (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_LEN_SHIFT)) & I3C_MWMSG_SDR_CONTROL_LEN_MASK)
/*! @} */

/*! @name MWMSG_SDR_DATA - Master Write Message Data in SDR mode */
/*! @{ */

#define I3C_MWMSG_SDR_DATA_DATA16B_MASK          (0xFFFFU)
#define I3C_MWMSG_SDR_DATA_DATA16B_SHIFT         (0U)
/*! DATA16B - Data
 */
#define I3C_MWMSG_SDR_DATA_DATA16B(x)            (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_DATA_DATA16B_SHIFT)) & I3C_MWMSG_SDR_DATA_DATA16B_MASK)
/*! @} */

/*! @name MRMSG_SDR - Master Read Message in SDR mode */
/*! @{ */

#define I3C_MRMSG_SDR_DATA_MASK                  (0xFFFFU)
#define I3C_MRMSG_SDR_DATA_SHIFT                 (0U)
/*! DATA - Data
 */
#define I3C_MRMSG_SDR_DATA(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MRMSG_SDR_DATA_SHIFT)) & I3C_MRMSG_SDR_DATA_MASK)
/*! @} */

/*! @name MWMSG_DDR_CONTROL - Master Write Message in DDR mode */
/*! @{ */

#define I3C_MWMSG_DDR_CONTROL_LEN_MASK           (0x3FFU)
#define I3C_MWMSG_DDR_CONTROL_LEN_SHIFT          (0U)
/*! LEN - Length of message
 */
#define I3C_MWMSG_DDR_CONTROL_LEN(x)             (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL_LEN_SHIFT)) & I3C_MWMSG_DDR_CONTROL_LEN_MASK)

#define I3C_MWMSG_DDR_CONTROL_END_MASK           (0x4000U)
#define I3C_MWMSG_DDR_CONTROL_END_SHIFT          (14U)
/*! END - End of message
 */
#define I3C_MWMSG_DDR_CONTROL_END(x)             (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL_END_SHIFT)) & I3C_MWMSG_DDR_CONTROL_END_MASK)
/*! @} */

/*! @name MWMSG_DDR_DATA - Master Write Message Data in DDR mode */
/*! @{ */

#define I3C_MWMSG_DDR_DATA_DATA16B_MASK          (0xFFFFU)
#define I3C_MWMSG_DDR_DATA_DATA16B_SHIFT         (0U)
/*! DATA16B - Data
 */
#define I3C_MWMSG_DDR_DATA_DATA16B(x)            (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_DATA_DATA16B_SHIFT)) & I3C_MWMSG_DDR_DATA_DATA16B_MASK)
/*! @} */

/*! @name MRMSG_DDR - Master Read Message in DDR mode */
/*! @{ */

#define I3C_MRMSG_DDR_DATA_MASK                  (0xFFFFU)
#define I3C_MRMSG_DDR_DATA_SHIFT                 (0U)
/*! DATA - Data
 */
#define I3C_MRMSG_DDR_DATA(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MRMSG_DDR_DATA_SHIFT)) & I3C_MRMSG_DDR_DATA_MASK)
/*! @} */

/*! @name MDYNADDR - Master Dynamic Address */
/*! @{ */

#define I3C_MDYNADDR_DAVALID_MASK                (0x1U)
#define I3C_MDYNADDR_DAVALID_SHIFT               (0U)
/*! DAVALID - Dynamic address valid
 */
#define I3C_MDYNADDR_DAVALID(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MDYNADDR_DAVALID_SHIFT)) & I3C_MDYNADDR_DAVALID_MASK)

#define I3C_MDYNADDR_DADDR_MASK                  (0xFEU)
#define I3C_MDYNADDR_DADDR_SHIFT                 (1U)
/*! DADDR - Dynamic address
 */
#define I3C_MDYNADDR_DADDR(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MDYNADDR_DADDR_SHIFT)) & I3C_MDYNADDR_DADDR_MASK)
/*! @} */

/*! @name SMAPCTRL0 - Map Feature Control 0 */
/*! @{ */

#define I3C_SMAPCTRL0_ENA_MASK                   (0x1U)
#define I3C_SMAPCTRL0_ENA_SHIFT                  (0U)
/*! ENA - Enable
 */
#define I3C_SMAPCTRL0_ENA(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_ENA_SHIFT)) & I3C_SMAPCTRL0_ENA_MASK)

#define I3C_SMAPCTRL0_DA_MASK                    (0xFEU)
#define I3C_SMAPCTRL0_DA_SHIFT                   (1U)
/*! DA - Dynamic Address
 */
#define I3C_SMAPCTRL0_DA(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_DA_SHIFT)) & I3C_SMAPCTRL0_DA_MASK)

#define I3C_SMAPCTRL0_CAUSE_MASK                 (0x700U)
#define I3C_SMAPCTRL0_CAUSE_SHIFT                (8U)
/*! CAUSE - Cause
 */
#define I3C_SMAPCTRL0_CAUSE(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_CAUSE_SHIFT)) & I3C_SMAPCTRL0_CAUSE_MASK)
/*! @} */

/*! @name IBIEXT1 - Extended IBI Data 1 */
/*! @{ */

#define I3C_IBIEXT1_CNT_MASK                     (0x7U)
#define I3C_IBIEXT1_CNT_SHIFT                    (0U)
/*! CNT - Count
 */
#define I3C_IBIEXT1_CNT(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_CNT_SHIFT)) & I3C_IBIEXT1_CNT_MASK)

#define I3C_IBIEXT1_MAX_MASK                     (0x70U)
#define I3C_IBIEXT1_MAX_SHIFT                    (4U)
/*! MAX - Maximum
 */
#define I3C_IBIEXT1_MAX(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_MAX_SHIFT)) & I3C_IBIEXT1_MAX_MASK)

#define I3C_IBIEXT1_EXT1_MASK                    (0xFF00U)
#define I3C_IBIEXT1_EXT1_SHIFT                   (8U)
/*! EXT1 - Extra byte 1
 */
#define I3C_IBIEXT1_EXT1(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT1_SHIFT)) & I3C_IBIEXT1_EXT1_MASK)

#define I3C_IBIEXT1_EXT2_MASK                    (0xFF0000U)
#define I3C_IBIEXT1_EXT2_SHIFT                   (16U)
/*! EXT2 - Extra byte 2
 */
#define I3C_IBIEXT1_EXT2(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT2_SHIFT)) & I3C_IBIEXT1_EXT2_MASK)

#define I3C_IBIEXT1_EXT3_MASK                    (0xFF000000U)
#define I3C_IBIEXT1_EXT3_SHIFT                   (24U)
/*! EXT3 - Extra byte 3
 */
#define I3C_IBIEXT1_EXT3(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT3_SHIFT)) & I3C_IBIEXT1_EXT3_MASK)
/*! @} */

/*! @name IBIEXT2 - Extended IBI Data 2 */
/*! @{ */

#define I3C_IBIEXT2_EXT4_MASK                    (0xFFU)
#define I3C_IBIEXT2_EXT4_SHIFT                   (0U)
/*! EXT4 - Extra byte 4
 */
#define I3C_IBIEXT2_EXT4(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT4_SHIFT)) & I3C_IBIEXT2_EXT4_MASK)

#define I3C_IBIEXT2_EXT5_MASK                    (0xFF00U)
#define I3C_IBIEXT2_EXT5_SHIFT                   (8U)
/*! EXT5 - Extra byte 5
 */
#define I3C_IBIEXT2_EXT5(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT5_SHIFT)) & I3C_IBIEXT2_EXT5_MASK)

#define I3C_IBIEXT2_EXT6_MASK                    (0xFF0000U)
#define I3C_IBIEXT2_EXT6_SHIFT                   (16U)
/*! EXT6 - Extra byte 6
 */
#define I3C_IBIEXT2_EXT6(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT6_SHIFT)) & I3C_IBIEXT2_EXT6_MASK)

#define I3C_IBIEXT2_EXT7_MASK                    (0xFF000000U)
#define I3C_IBIEXT2_EXT7_SHIFT                   (24U)
/*! EXT7 - Extra byte 7
 */
#define I3C_IBIEXT2_EXT7(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT7_SHIFT)) & I3C_IBIEXT2_EXT7_MASK)
/*! @} */

/*! @name SID - Slave Module ID */
/*! @{ */

#define I3C_SID_ID_MASK                          (0xFFFFFFFFU)
#define I3C_SID_ID_SHIFT                         (0U)
/*! ID - ID
 */
#define I3C_SID_ID(x)                            (((uint32_t)(((uint32_t)(x)) << I3C_SID_ID_SHIFT)) & I3C_SID_ID_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group I3C_Register_Masks */


/* I3C - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral I3C0 base address */
  #define I3C0_BASE                                (0x50016000u)
  /** Peripheral I3C0 base address */
  #define I3C0_BASE_NS                             (0x40016000u)
  /** Peripheral I3C0 base pointer */
  #define I3C0                                     ((I3C_Type *)I3C0_BASE)
  /** Peripheral I3C0 base pointer */
  #define I3C0_NS                                  ((I3C_Type *)I3C0_BASE_NS)
  /** Array initializer of I3C peripheral base addresses */
  #define I3C_BASE_ADDRS                           { I3C0_BASE }
  /** Array initializer of I3C peripheral base pointers */
  #define I3C_BASE_PTRS                            { I3C0 }
  /** Array initializer of I3C peripheral base addresses */
  #define I3C_BASE_ADDRS_NS                        { I3C0_BASE_NS }
  /** Array initializer of I3C peripheral base pointers */
  #define I3C_BASE_PTRS_NS                         { I3C0_NS }
#else
  /** Peripheral I3C0 base address */
  #define I3C0_BASE                                (0x40016000u)
  /** Peripheral I3C0 base pointer */
  #define I3C0                                     ((I3C_Type *)I3C0_BASE)
  /** Array initializer of I3C peripheral base addresses */
  #define I3C_BASE_ADDRS                           { I3C0_BASE }
  /** Array initializer of I3C peripheral base pointers */
  #define I3C_BASE_PTRS                            { I3C0 }
#endif
/** Interrupt vectors for the I3C peripheral type */
#define I3C_IRQS                                 { I3C0_IRQn }

/*!
 * @}
 */ /* end of group I3C_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- INPUTMUX Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer
 * @{
 */

/** INPUTMUX - Register Layout Typedef */
typedef struct {
  __IO uint32_t SCT0_INMUX[7];                     /**< Inputmux register for SCT0 input, array offset: 0x0, array step: 0x4 */
       uint8_t RESERVED_0[4];
  __IO uint32_t TIMER0CAP[4];                      /**< Capture select register for TIMER0 inputs, array offset: 0x20, array step: 0x4 */
  __IO uint32_t TIMER0TRIG;                        /**< Trigger register for TIMER0, offset: 0x30 */
       uint8_t RESERVED_1[12];
  __IO uint32_t TIMER1CAP[4];                      /**< Capture select register for TIMER1 inputs, array offset: 0x40, array step: 0x4 */
  __IO uint32_t TIMER1TRIG;                        /**< Trigger register for TIMER1, offset: 0x50 */
       uint8_t RESERVED_2[12];
  __IO uint32_t TIMER2CAP[4];                      /**< Capture select register for TIMER2 inputs, array offset: 0x60, array step: 0x4 */
  __IO uint32_t TIMER2TRIG;                        /**< Trigger register for TIMER2, offset: 0x70 */
       uint8_t RESERVED_3[44];
  __IO uint32_t EZHARCHB_INMUX[8];                 /**< Inputmux register for EZH arch B inputs, array offset: 0xA0, array step: 0x4 */
  __IO uint32_t PINTSEL[8];                        /**< Pin interrupt select, array offset: 0xC0, array step: 0x4 */
  __IO uint32_t DMA0_ITRIG_INMUX[32];              /**< Trigger select for DMA0 channel, array offset: 0xE0, array step: 0x4 */
  __IO uint32_t DMA0_OTRIG_INMUX[7];               /**< DMA0 output trigger selection for DMA0 input trigger, array offset: 0x160, array step: 0x4 */
       uint8_t RESERVED_4[4];
  __IO uint32_t FREQMEAS_REF;                      /**< Selection for frequency measurement reference clock, offset: 0x180 */
  __IO uint32_t FREQMEAS_TAR;                      /**< Selection for frequency measurement target clock, offset: 0x184 */
       uint8_t RESERVED_5[24];
  __IO uint32_t TIMER3CAP[4];                      /**< Capture select register for TIMER3 inputs, array offset: 0x1A0, array step: 0x4 */
  __IO uint32_t TIMER3TRIG;                        /**< Trigger register for TIMER3, offset: 0x1B0 */
       uint8_t RESERVED_6[12];
  __IO uint32_t TIMER4CAP[4];                      /**< Capture select register for TIMER4 inputs, array offset: 0x1C0, array step: 0x4 */
  __IO uint32_t TIMER4TRIG;                        /**< Trigger register for TIMER4, offset: 0x1D0 */
       uint8_t RESERVED_7[12];
  __IO uint32_t PINTSECSEL[2];                     /**< Pin interrupt secure select, array offset: 0x1E0, array step: 0x4 */
       uint8_t RESERVED_8[24];
  __IO uint32_t DMA1_ITRIG_INMUX[16];              /**< Trigger select for DMA1 channel, array offset: 0x200, array step: 0x4 */
  __IO uint32_t DMA1_OTRIG_INMUX[4];               /**< DMA1 output trigger selection for DMA1 input trigger, array offset: 0x240, array step: 0x4 */
       uint8_t RESERVED_9[16];
  __IO uint32_t HSCMP0_TRIG;                       /**< Input connections for HSCMP0, offset: 0x260 */
       uint8_t RESERVED_10[28];
  __IO uint32_t ADC0_TRIG[4];                      /**< ADC0 Trigger input connections, array offset: 0x280, array step: 0x4 */
       uint8_t RESERVED_11[48];
  __IO uint32_t ADC1_TRIG[4];                      /**< ADC1 Trigger input connections, array offset: 0x2C0, array step: 0x4 */
       uint8_t RESERVED_12[48];
  __IO uint32_t DAC0_TRIG;                         /**< DAC0 Trigger Inputs, offset: 0x300 */
       uint8_t RESERVED_13[28];
  __IO uint32_t DAC1_TRIG;                         /**< DAC1 Trigger Inputs, offset: 0x320 */
       uint8_t RESERVED_14[28];
  __IO uint32_t DAC2_TRIG;                         /**< DAC2 Trigger Inputs, offset: 0x340 */
       uint8_t RESERVED_15[28];
  __IO uint32_t ENC0_TRIG;                         /**< ENC0 Trigger Input Connections, offset: 0x360 */
  __IO uint32_t ENC0_HOME;                         /**< ENC0 Input Connections, offset: 0x364 */
  __IO uint32_t ENC0_INDEX;                        /**< ENC0 Input Connections, offset: 0x368 */
  __IO uint32_t ENC0_PHASEB;                       /**< ENC0 Input Connections, offset: 0x36C */
  __IO uint32_t ENC0_PHASEA;                       /**< ENC0 Input Connections, offset: 0x370 */
       uint8_t RESERVED_16[12];
  __IO uint32_t ENC1_TRIG;                         /**< ENC1 Trigger Input Connections, offset: 0x380 */
  __IO uint32_t ENC1_HOME;                         /**< ENC1 Input Connections, offset: 0x384 */
  __IO uint32_t ENC1_INDEX;                        /**< ENC1 Input Connections, offset: 0x388 */
  __IO uint32_t ENC1_PHASEB;                       /**< ENC1 Input Connections, offset: 0x38C */
  __IO uint32_t ENC1_PHASEA;                       /**< ENC1 Input Connections, offset: 0x390 */
       uint8_t RESERVED_17[12];
  __IO uint32_t PWM0_EXTSYNC[4];                   /**< PWM0 external synchronization, array offset: 0x3A0, array step: 0x4 */
  __IO uint32_t PWM0_EXTA[4];                      /**< PWM0 input trigger connections, array offset: 0x3B0, array step: 0x4 */
  __IO uint32_t PWM0_EXTFORCE;                     /**< PWM0 external force trigger connections, offset: 0x3C0 */
  __IO uint32_t PWM0_FAULT[4];                     /**< PWM0 fault input trigger connections, array offset: 0x3C4, array step: 0x4 */
       uint8_t RESERVED_18[12];
  __IO uint32_t PWM1_EXTSYNC[4];                   /**< PWM1 external synchronization, array offset: 0x3E0, array step: 0x4 */
  __IO uint32_t PWM1_EXTA[4];                      /**< PWM1 input trigger connections, array offset: 0x3F0, array step: 0x4 */
  __IO uint32_t PWM1_EXTFORCE;                     /**< PWM1 external force trigger connections, offset: 0x400 */
  __IO uint32_t PWM1_FAULT[4];                     /**< PWM1 fault input trigger connections, array offset: 0x404, array step: 0x4 */
       uint8_t RESERVED_19[12];
  __IO uint32_t PWM0_EXTCLK;                       /**< PWM0 external clock trigger connections, offset: 0x420 */
  __IO uint32_t PWM1_EXTCLK;                       /**< PWM1 external clock trigger connections, offset: 0x424 */
       uint8_t RESERVED_20[24];
  __IO uint32_t AOI0_IN[16];                       /**< AOI0 trigger inputs, array offset: 0x440, array step: 0x4 */
  __IO uint32_t AOI1_IN[16];                       /**< AOI1 trigger inputs, array offset: 0x480, array step: 0x4 */
  __IO uint32_t AOI_EXT_TRIG[8];                   /**< AOI External Trigger Inputs, array offset: 0x4C0, array step: 0x4 */
  __IO uint32_t HSCMP1_TRIG;                       /**< Input connections for HSCMP1, offset: 0x4E0 */
       uint8_t RESERVED_21[28];
  __IO uint32_t HSCMP2_TRIG;                       /**< Input connections for HSCMP2, offset: 0x500 */
       uint8_t RESERVED_22[28];
  __IO uint32_t DMA0_ITRIG_INMUX32[20];            /**< Trigger select for DMA0 channel, array offset: 0x520, array step: 0x4 */
       uint8_t RESERVED_23[464];
  __IO uint32_t DMA0_REQEN0;                       /**< Enable DMA0 requests, offset: 0x740 */
  __IO uint32_t DMA0_REQEN1;                       /**< Enable DMA0 requests, offset: 0x744 */
  __O  uint32_t DMA0_REQEN0_SET;                   /**< Set bits in DMA0_REQEN0 register, offset: 0x748 */
  __O  uint32_t DMA0_REQEN1_SET;                   /**< Set bits in DMA0_REQEN1 register, offset: 0x74C */
  __O  uint32_t DMA0_REQEN0_CLR;                   /**< Clear bits in DMA0_REQEN0 register, offset: 0x750 */
  __O  uint32_t DMA0_REQEN1_CLR;                   /**< Clear bits in DMA0_REQEN1 register, offset: 0x754 */
       uint8_t RESERVED_24[8];
  __IO uint32_t DMA1_REQEN;                        /**< Enable DMA1 requests, offset: 0x760 */
       uint8_t RESERVED_25[4];
  __O  uint32_t DMA1_REQEN_SET;                    /**< Set bits in DMA1_REQEN register, offset: 0x768 */
       uint8_t RESERVED_26[4];
  __O  uint32_t DMA1_REQEN_CLR;                    /**< Clear bits in DMA1_REQEN register, offset: 0x770 */
       uint8_t RESERVED_27[12];
  __IO uint32_t DMA0_ITRIGEN0;                     /**< Enable DMA0 triggers, offset: 0x780 */
  __IO uint32_t DMA0_ITRIGEN1;                     /**< Enable DMA0 triggers, offset: 0x784 */
  __O  uint32_t DMA0_ITRIGEN0_SET;                 /**< Set bits in DMA0_ITRIGEN0 register, offset: 0x788 */
  __O  uint32_t DMA0_ITRIGEN1_SET;                 /**< Set bits in DMA0_ITRIGEN1 register, offset: 0x78C */
  __O  uint32_t DMA0_ITRIGEN0_CLR;                 /**< Clear bits in DMA0_ITRIGEN0 register, offset: 0x790 */
  __O  uint32_t DMA0_ITRIGEN1_CLR;                 /**< Clear bits in DMA0_ITRIGEN1 register, offset: 0x794 */
       uint8_t RESERVED_28[8];
  __IO uint32_t DMA1_ITRIGEN;                      /**< Enable DMA1 triggers, offset: 0x7A0 */
       uint8_t RESERVED_29[4];
  __O  uint32_t DMA1_ITRIGEN_SET;                  /**< Set bits in DMA1_ITRIGEN register, offset: 0x7A8 */
       uint8_t RESERVED_30[4];
  __O  uint32_t DMA1_ITRIGEN_CLR;                  /**< Clear bits in DMA1_ITRIGEN register, offset: 0x7B0 */
} INPUTMUX_Type;

/* ----------------------------------------------------------------------------
   -- INPUTMUX Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks
 * @{
 */

/*! @name SCT0_INMUX - Inputmux register for SCT0 input */
/*! @{ */

#define INPUTMUX_SCT0_INMUX_INP_N_MASK           (0x3FU)
#define INPUTMUX_SCT0_INMUX_INP_N_SHIFT          (0U)
/*! INP_N - Input number to SCT0 inputs 0 to 6.
 *  0b000000..SCT_GPIO_IN_A function selected from IOCON register
 *  0b000001..SCT_GPIO_IN_B function selected from IOCON register
 *  0b000010..SCT_GPIO_IN_C function selected from IOCON register
 *  0b000011..SCT_GPIO_IN_D function selected from IOCON register
 *  0b000100..SCT_GPIO_IN_E function selected from IOCON register
 *  0b000101..SCT_GPIO_IN_F function selected from IOCON register
 *  0b000110..SCT_GPIO_IN_G function selected from IOCON register
 *  0b000111..SCT_GPIO_IN_H function selected from IOCON register
 *  0b001000..T0_MAT0 ctimer 0 match[0] output
 *  0b001001..T1_MAT0 ctimer 1 match[0] output
 *  0b001010..T2_MAT0 ctimer 2 match[0] output
 *  0b001011..T3_MAT0 ctimer 3 match[0] output
 *  0b001100..T4_MAT0 ctimer 4 match[0] output
 *  0b001101..ADC0_IRQ interrupt request from ADC0
 *  0b001110..GPIOINT_BMATCH
 *  0b001111..USB0_FRAME_TOGGLE
 *  0b010000..Reserved
 *  0b010001..ACMP0_OUT from analog comparator
 *  0b010010..SHARED_I2S_SCLK0 output from I2S pin sharing
 *  0b010011..SHARED_I2S_SCLK1 output from I2S pin sharing
 *  0b010100..SHARED_I2S_WS0 output from I2S pin sharing
 *  0b010101..SHARED_I2S_WS1 output from I2S pin sharing
 *  0b010110..ARM_TXEV interrupt event from CPU0
 *  0b010111..DEBUG_HALTED from CPU0
 *  0b011000..ADC1_IRQ interrupt request from ADC1
 *  0b011001..ADC0_tcomp[0]
 *  0b011010..ADC0_tcomp[1]
 *  0b011011..ADC0_tcomp[2]
 *  0b011100..ADC0_tcomp[3]
 *  0b011101..ADC1_tcomp[0]
 *  0b011110..ADC1_tcomp[1]
 *  0b011111..ADC1_tcomp[2]
 *  0b100000..ADC1_tcomp[3]
 *  0b100001..HSCMP0_OUT
 *  0b100010..HSCMP1_OUT
 *  0b100011..HSCMP2_OUT
 *  0b100100..PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1
 *  0b100101..PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1
 *  0b100110..PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1
 *  0b100111..PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1
 *  0b101000..PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1
 *  0b101001..PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1
 *  0b101010..PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1
 *  0b101011..PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1
 *  0b101100..ENC0_CMP/POS_MATCH
 *  0b101101..ENC1_CMP/POS_MATCH
 *  0b101110..AOI0_OUT0
 *  0b101111..AOI0_OUT1
 *  0b110000..AOI0_OUT2
 *  0b110001..AOI0_OUT3
 *  0b110010..AOI1_OUT0
 *  0b110011..AOI1_OUT1
 *  0b110100..AOI1_OUT2
 *  0b110101..AOI1_OUT3
 *  0b110110..FC3_SCK
 *  0b110111..FC3_RXD_SDA_MOSI_DATA
 *  0b111000..FC3_TXD_SCL_MISO_WS
 *  0b111001..FC3_CTS_DSA_SSEL0
 *  0b111010..TMPR_OUT
 *  0b111011-0b111111..None
 */
#define INPUTMUX_SCT0_INMUX_INP_N(x)             (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SCT0_INMUX_INP_N_SHIFT)) & INPUTMUX_SCT0_INMUX_INP_N_MASK)
/*! @} */

/* The count of INPUTMUX_SCT0_INMUX */
#define INPUTMUX_SCT0_INMUX_COUNT                (7U)

/*! @name TIMER0CAP - Capture select register for TIMER0 inputs */
/*! @{ */

#define INPUTMUX_TIMER0CAP_CAPTSEL_MASK          (0x3FU)
#define INPUTMUX_TIMER0CAP_CAPTSEL_SHIFT         (0U)
/*! CAPTSEL - Input number to TIMER0 capture inputs 0 to 5
 *  0b000000..CTIMER_INP0 function selected from IOCON register
 *  0b000001..CTIMER_INP1 function selected from IOCON register
 *  0b000010..CTIMER_INP2 function selected from IOCON register
 *  0b000011..CTIMER_INP3 function selected from IOCON register
 *  0b000100..CTIMER_INP4 function selected from IOCON register
 *  0b000101..CTIMER_INP5 function selected from IOCON register
 *  0b000110..CTIMER_INP6 function selected from IOCON register
 *  0b000111..CTIMER_INP7 function selected from IOCON register
 *  0b001000..CTIMER_INP8 function selected from IOCON register
 *  0b001001..CTIMER_INP9 function selected from IOCON register
 *  0b001010..CTIMER_INP10 function selected from IOCON register
 *  0b001011..CTIMER_INP11 function selected from IOCON register
 *  0b001100..CTIMER_INP12 function selected from IOCON register
 *  0b001101..CTIMER_INP13 function selected from IOCON register
 *  0b001110..CTIMER_INP14 function selected from IOCON register
 *  0b001111..CTIMER_INP15 function selected from IOCON register
 *  0b010000..CTIMER_INP16 function selected from IOCON register
 *  0b010001..CTIMER_INP17 function selected from IOCON register
 *  0b010010..CTIMER_INP18 function selected from IOCON register
 *  0b010011..CTIMER_INP19 function selected from IOCON register
 *  0b010100..USB0_FRAME_TOGGLE
 *  0b010101..Reserved
 *  0b010110..ACMP0_OUT from analog comparator
 *  0b010111..SHARED_I2S_WS0 output from I2S pin sharing
 *  0b011000..SHARED_I2S_WS1 output from I2S pin sharing
 *  0b011001..ADC0_IRQ
 *  0b011010..ADC1_IRQ
 *  0b011011..HSCMP0_OUT
 *  0b011100..HSCMP1_OUT
 *  0b011101..HSCMP2_OUT
 *  0b011110..PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1
 *  0b011111..PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1
 *  0b100000..PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1
 *  0b100001..PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1
 *  0b100010..PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1
 *  0b100011..PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1
 *  0b100100..PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1
 *  0b100101..PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1
 *  0b100110..ENC0_CMP/POS_MATCH
 *  0b100111..ENC1_CMP/POS_MATCH
 *  0b101000..AOI0_OUT0
 *  0b101001..AOI0_OUT1
 *  0b101010..AOI0_OUT2
 *  0b101011..AOI0_OUT3
 *  0b101100..AOI1_OUT0
 *  0b101101..AOI1_OUT1
 *  0b101110..AOI1_OUT2
 *  0b101111..AOI1_OUT3
 *  0b110000..TMPR_OUT
 *  0b110001-0b111111..None
 */
#define INPUTMUX_TIMER0CAP_CAPTSEL(x)            (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER0CAP_CAPTSEL_SHIFT)) & INPUTMUX_TIMER0CAP_CAPTSEL_MASK)
/*! @} */

/* The count of INPUTMUX_TIMER0CAP */
#define INPUTMUX_TIMER0CAP_COUNT                 (4U)

/*! @name TIMER0TRIG - Trigger register for TIMER0 */
/*! @{ */

#define INPUTMUX_TIMER0TRIG_TRIGIN_MASK          (0x3FU)
#define INPUTMUX_TIMER0TRIG_TRIGIN_SHIFT         (0U)
/*! TRIGIN - Input number to TIMER0 trigger inputs
 *  0b000000..CTIMER_INP0 function selected from IOCON register
 *  0b000001..CTIMER_INP1 function selected from IOCON register
 *  0b000010..CTIMER_INP2 function selected from IOCON register
 *  0b000011..CTIMER_INP3 function selected from IOCON register
 *  0b000100..CTIMER_INP4 function selected from IOCON register
 *  0b000101..CTIMER_INP5 function selected from IOCON register
 *  0b000110..CTIMER_INP6 function selected from IOCON register
 *  0b000111..CTIMER_INP7 function selected from IOCON register
 *  0b001000..CTIMER_INP8 function selected from IOCON register
 *  0b001001..CTIMER_INP9 function selected from IOCON register
 *  0b001010..CTIMER_INP10 function selected from IOCON register
 *  0b001011..CTIMER_INP11 function selected from IOCON register
 *  0b001100..CTIMER_INP12 function selected from IOCON register
 *  0b001101..CTIMER_INP13 function selected from IOCON register
 *  0b001110..CTIMER_INP14 function selected from IOCON register
 *  0b001111..CTIMER_INP15 function selected from IOCON register
 *  0b010000..CTIMER_INP16 function selected from IOCON register
 *  0b010001..CTIMER_INP17 function selected from IOCON register
 *  0b010010..CTIMER_INP18 function selected from IOCON register
 *  0b010011..CTIMER_INP19 function selected from IOCON register
 *  0b010100..USB0_FRAME_TOGGLE
 *  0b010101..Reserved
 *  0b010110..ACMP0_OUT from analog comparator
 *  0b010111..SHARED_I2S_WS0 output from I2S pin sharing
 *  0b011000..SHARED_I2S_WS1 output from I2S pin sharing
 *  0b011001..ADC0_IRQ
 *  0b011010..ADC1_IRQ
 *  0b011011..HSCMP0_OUT
 *  0b011100..HSCMP1_OUT
 *  0b011101..HSCMP2_OUT
 *  0b011110..PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1
 *  0b011111..PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1
 *  0b100000..PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1
 *  0b100001..PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1
 *  0b100010..PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1
 *  0b100011..PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1
 *  0b100100..PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1
 *  0b100101..PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1
 *  0b100110..ENC0_CMP/POS_MATCH
 *  0b100111..ENC1_CMP/POS_MATCH
 *  0b101000..AOI0_OUT0
 *  0b101001..AOI0_OUT1
 *  0b101010..AOI0_OUT2
 *  0b101011..AOI0_OUT3
 *  0b101100..AOI1_OUT0
 *  0b101101..AOI1_OUT1
 *  0b101110..AOI1_OUT2
 *  0b101111..AOI1_OUT3
 *  0b110000..TMPR_OUT
 *  0b110001-0b111111..None
 */
#define INPUTMUX_TIMER0TRIG_TRIGIN(x)            (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER0TRIG_TRIGIN_SHIFT)) & INPUTMUX_TIMER0TRIG_TRIGIN_MASK)
/*! @} */

/*! @name TIMER1CAP - Capture select register for TIMER1 inputs */
/*! @{ */

#define INPUTMUX_TIMER1CAP_CAPTSEL_MASK          (0x3FU)
#define INPUTMUX_TIMER1CAP_CAPTSEL_SHIFT         (0U)
/*! CAPTSEL - Input number to TIMER1 capture inputs 0 to 5
 *  0b000000..CTIMER_INP0 function selected from IOCON register
 *  0b000001..CTIMER_INP1 function selected from IOCON register
 *  0b000010..CTIMER_INP2 function selected from IOCON register
 *  0b000011..CTIMER_INP3 function selected from IOCON register
 *  0b000100..CTIMER_INP4 function selected from IOCON register
 *  0b000101..CTIMER_INP5 function selected from IOCON register
 *  0b000110..CTIMER_INP6 function selected from IOCON register
 *  0b000111..CTIMER_INP7 function selected from IOCON register
 *  0b001000..CTIMER_INP8 function selected from IOCON register
 *  0b001001..CTIMER_INP9 function selected from IOCON register
 *  0b001010..CTIMER_INP10 function selected from IOCON register
 *  0b001011..CTIMER_INP11 function selected from IOCON register
 *  0b001100..CTIMER_INP12 function selected from IOCON register
 *  0b001101..CTIMER_INP13 function selected from IOCON register
 *  0b001110..CTIMER_INP14 function selected from IOCON register
 *  0b001111..CTIMER_INP15 function selected from IOCON register
 *  0b010000..CTIMER_INP16 function selected from IOCON register
 *  0b010001..CTIMER_INP17 function selected from IOCON register
 *  0b010010..CTIMER_INP18 function selected from IOCON register
 *  0b010011..CTIMER_INP19 function selected from IOCON register
 *  0b010100..USB0_FRAME_TOGGLE
 *  0b010101..Reserved
 *  0b010110..ACMP0_OUT from analog comparator
 *  0b010111..SHARED_I2S_WS0 output from I2S pin sharing
 *  0b011000..SHARED_I2S_WS1 output from I2S pin sharing
 *  0b011001..ADC0_IRQ
 *  0b011010..ADC1_IRQ
 *  0b011011..HSCMP0_OUT
 *  0b011100..HSCMP1_OUT
 *  0b011101..HSCMP2_OUT
 *  0b011110..PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1
 *  0b011111..PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1
 *  0b100000..PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1
 *  0b100001..PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1
 *  0b100010..PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1
 *  0b100011..PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1
 *  0b100100..PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1
 *  0b100101..PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1
 *  0b100110..ENC0_CMP/POS_MATCH
 *  0b100111..ENC1_CMP/POS_MATCH
 *  0b101000..AOI0_OUT0
 *  0b101001..AOI0_OUT1
 *  0b101010..AOI0_OUT2
 *  0b101011..AOI0_OUT3
 *  0b101100..AOI1_OUT0
 *  0b101101..AOI1_OUT1
 *  0b101110..AOI1_OUT2
 *  0b101111..AOI1_OUT3
 *  0b110000..TMPR_OUT
 *  0b110001-0b111111..None
 */
#define INPUTMUX_TIMER1CAP_CAPTSEL(x)            (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER1CAP_CAPTSEL_SHIFT)) & INPUTMUX_TIMER1CAP_CAPTSEL_MASK)
/*! @} */

/* The count of INPUTMUX_TIMER1CAP */
#define INPUTMUX_TIMER1CAP_COUNT                 (4U)

/*! @name TIMER1TRIG - Trigger register for TIMER1 */
/*! @{ */

#define INPUTMUX_TIMER1TRIG_TRIGIN_MASK          (0x3FU)
#define INPUTMUX_TIMER1TRIG_TRIGIN_SHIFT         (0U)
/*! TRIGIN - Input number to TIMER1 trigger inputs
 *  0b000000..CTIMER_INP0 function selected from IOCON register
 *  0b000001..CTIMER_INP1 function selected from IOCON register
 *  0b000010..CTIMER_INP2 function selected from IOCON register
 *  0b000011..CTIMER_INP3 function selected from IOCON register
 *  0b000100..CTIMER_INP4 function selected from IOCON register
 *  0b000101..CTIMER_INP5 function selected from IOCON register
 *  0b000110..CTIMER_INP6 function selected from IOCON register
 *  0b000111..CTIMER_INP7 function selected from IOCON register
 *  0b001000..CTIMER_INP8 function selected from IOCON register
 *  0b001001..CTIMER_INP9 function selected from IOCON register
 *  0b001010..CTIMER_INP10 function selected from IOCON register
 *  0b001011..CTIMER_INP11 function selected from IOCON register
 *  0b001100..CTIMER_INP12 function selected from IOCON register
 *  0b001101..CTIMER_INP13 function selected from IOCON register
 *  0b001110..CTIMER_INP14 function selected from IOCON register
 *  0b001111..CTIMER_INP15 function selected from IOCON register
 *  0b010000..CTIMER_INP16 function selected from IOCON register
 *  0b010001..CTIMER_INP17 function selected from IOCON register
 *  0b010010..CTIMER_INP18 function selected from IOCON register
 *  0b010011..CTIMER_INP19 function selected from IOCON register
 *  0b010100..USB0_FRAME_TOGGLE
 *  0b010101..Reserved
 *  0b010110..ACMP0_OUT from analog comparator
 *  0b010111..SHARED_I2S_WS0 output from I2S pin sharing
 *  0b011000..SHARED_I2S_WS1 output from I2S pin sharing
 *  0b011001..ADC0_IRQ
 *  0b011010..ADC1_IRQ
 *  0b011011..HSCMP0_OUT
 *  0b011100..HSCMP1_OUT
 *  0b011101..HSCMP2_OUT
 *  0b011110..PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1
 *  0b011111..PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1
 *  0b100000..PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1
 *  0b100001..PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1
 *  0b100010..PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1
 *  0b100011..PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1
 *  0b100100..PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1
 *  0b100101..PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1
 *  0b100110..ENC0_CMP/POS_MATCH
 *  0b100111..ENC1_CMP/POS_MATCH
 *  0b101000..AOI0_OUT0
 *  0b101001..AOI0_OUT1
 *  0b101010..AOI0_OUT2
 *  0b101011..AOI0_OUT3
 *  0b101100..AOI1_OUT0
 *  0b101101..AOI1_OUT1
 *  0b101110..AOI1_OUT2
 *  0b101111..AOI1_OUT3
 *  0b110000..TMPR_OUT
 *  0b110001-0b111111..None
 */
#define INPUTMUX_TIMER1TRIG_TRIGIN(x)            (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER1TRIG_TRIGIN_SHIFT)) & INPUTMUX_TIMER1TRIG_TRIGIN_MASK)
/*! @} */

/*! @name TIMER2CAP - Capture select register for TIMER2 inputs */
/*! @{ */

#define INPUTMUX_TIMER2CAP_CAPTSEL_MASK          (0x3FU)
#define INPUTMUX_TIMER2CAP_CAPTSEL_SHIFT         (0U)
/*! CAPTSEL - Input number to TIMER2 capture inputs 0 to 5
 *  0b000000..CTIMER_INP0 function selected from IOCON register
 *  0b000001..CTIMER_INP1 function selected from IOCON register
 *  0b000010..CTIMER_INP2 function selected from IOCON register
 *  0b000011..CTIMER_INP3 function selected from IOCON register
 *  0b000100..CTIMER_INP4 function selected from IOCON register
 *  0b000101..CTIMER_INP5 function selected from IOCON register
 *  0b000110..CTIMER_INP6 function selected from IOCON register
 *  0b000111..CTIMER_INP7 function selected from IOCON register
 *  0b001000..CTIMER_INP8 function selected from IOCON register
 *  0b001001..CTIMER_INP9 function selected from IOCON register
 *  0b001010..CTIMER_INP10 function selected from IOCON register
 *  0b001011..CTIMER_INP11 function selected from IOCON register
 *  0b001100..CTIMER_INP12 function selected from IOCON register
 *  0b001101..CTIMER_INP13 function selected from IOCON register
 *  0b001110..CTIMER_INP14 function selected from IOCON register
 *  0b001111..CTIMER_INP15 function selected from IOCON register
 *  0b010000..CTIMER_INP16 function selected from IOCON register
 *  0b010001..CTIMER_INP17 function selected from IOCON register
 *  0b010010..CTIMER_INP18 function selected from IOCON register
 *  0b010011..CTIMER_INP19 function selected from IOCON register
 *  0b010100..USB0_FRAME_TOGGLE
 *  0b010101..Reserved
 *  0b010110..ACMP0_OUT from analog comparator
 *  0b010111..SHARED_I2S_WS0 output from I2S pin sharing
 *  0b011000..SHARED_I2S_WS1 output from I2S pin sharing
 *  0b011001..ADC0_IRQ
 *  0b011010..ADC1_IRQ
 *  0b011011..HSCMP0_OUT
 *  0b011100..HSCMP1_OUT
 *  0b011101..HSCMP2_OUT
 *  0b011110..PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1
 *  0b011111..PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1
 *  0b100000..PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1
 *  0b100001..PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1
 *  0b100010..PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1
 *  0b100011..PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1
 *  0b100100..PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1
 *  0b100101..PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1
 *  0b100110..ENC0_CMP/POS_MATCH
 *  0b100111..ENC1_CMP/POS_MATCH
 *  0b101000..AOI0_OUT0
 *  0b101001..AOI0_OUT1
 *  0b101010..AOI0_OUT2
 *  0b101011..AOI0_OUT3
 *  0b101100..AOI1_OUT0
 *  0b101101..AOI1_OUT1
 *  0b101110..AOI1_OUT2
 *  0b101111..AOI1_OUT3
 *  0b110000..TMPR_OUT
 *  0b110001-0b111111..None
 */
#define INPUTMUX_TIMER2CAP_CAPTSEL(x)            (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER2CAP_CAPTSEL_SHIFT)) & INPUTMUX_TIMER2CAP_CAPTSEL_MASK)
/*! @} */

/* The count of INPUTMUX_TIMER2CAP */
#define INPUTMUX_TIMER2CAP_COUNT                 (4U)

/*! @name TIMER2TRIG - Trigger register for TIMER2 */
/*! @{ */

#define INPUTMUX_TIMER2TRIG_TRIGIN_MASK          (0x3FU)
#define INPUTMUX_TIMER2TRIG_TRIGIN_SHIFT         (0U)
/*! TRIGIN - Input number to TIMER2 trigger inputs
 *  0b000000..CTIMER_INP0 function selected from IOCON register
 *  0b000001..CTIMER_INP1 function selected from IOCON register
 *  0b000010..CTIMER_INP2 function selected from IOCON register
 *  0b000011..CTIMER_INP3 function selected from IOCON register
 *  0b000100..CTIMER_INP4 function selected from IOCON register
 *  0b000101..CTIMER_INP5 function selected from IOCON register
 *  0b000110..CTIMER_INP6 function selected from IOCON register
 *  0b000111..CTIMER_INP7 function selected from IOCON register
 *  0b001000..CTIMER_INP8 function selected from IOCON register
 *  0b001001..CTIMER_INP9 function selected from IOCON register
 *  0b001010..CTIMER_INP10 function selected from IOCON register
 *  0b001011..CTIMER_INP11 function selected from IOCON register
 *  0b001100..CTIMER_INP12 function selected from IOCON register
 *  0b001101..CTIMER_INP13 function selected from IOCON register
 *  0b001110..CTIMER_INP14 function selected from IOCON register
 *  0b001111..CTIMER_INP15 function selected from IOCON register
 *  0b010000..CTIMER_INP16 function selected from IOCON register
 *  0b010001..CTIMER_INP17 function selected from IOCON register
 *  0b010010..CTIMER_INP18 function selected from IOCON register
 *  0b010011..CTIMER_INP19 function selected from IOCON register
 *  0b010100..USB0_FRAME_TOGGLE
 *  0b010101..Reserved
 *  0b010110..ACMP0_OUT from analog comparator
 *  0b010111..SHARED_I2S_WS0 output from I2S pin sharing
 *  0b011000..SHARED_I2S_WS1 output from I2S pin sharing
 *  0b011001..ADC0_IRQ
 *  0b011010..ADC1_IRQ
 *  0b011011..HSCMP0_OUT
 *  0b011100..HSCMP1_OUT
 *  0b011101..HSCMP2_OUT
 *  0b011110..PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1
 *  0b011111..PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1
 *  0b100000..PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1
 *  0b100001..PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1
 *  0b100010..PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1
 *  0b100011..PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1
 *  0b100100..PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1
 *  0b100101..PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1
 *  0b100110..ENC0_CMP/POS_MATCH
 *  0b100111..ENC1_CMP/POS_MATCH
 *  0b101000..AOI0_OUT0
 *  0b101001..AOI0_OUT1
 *  0b101010..AOI0_OUT2
 *  0b101011..AOI0_OUT3
 *  0b101100..AOI1_OUT0
 *  0b101101..AOI1_OUT1
 *  0b101110..AOI1_OUT2
 *  0b101111..AOI1_OUT3
 *  0b110000..TMPR_OUT
 *  0b110001-0b111111..None
 */
#define INPUTMUX_TIMER2TRIG_TRIGIN(x)            (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER2TRIG_TRIGIN_SHIFT)) & INPUTMUX_TIMER2TRIG_TRIGIN_MASK)
/*! @} */

/*! @name EZHARCHB_INMUX - Inputmux register for EZH arch B inputs */
/*! @{ */

#define INPUTMUX_EZHARCHB_INMUX_INP_MASK         (0x7FU)
#define INPUTMUX_EZHARCHB_INMUX_INP_SHIFT        (0U)
/*! INP - Input number select to EZHARCHB input
 *  0b0000000-0b0001111..GPI00_0 to GPIO0_15 functions synced to system clock, selected from IOCON register
 *  0b0010000..SCT_OUT8 output from SCTimer, synced to system clock
 *  0b0010001..SCT_OUT9 output from SCTimer, synced to system clock
 *  0b0010010..Reserved
 *  0b0010011..Reserved
 *  0b0010100..MRT_IRQ0 Multi-rate timer interrupt request 0
 *  0b0010101..MRT_IRQ1 Multi-rate timer interrupt request 1
 *  0b0010110..T4_MAT3 ctimer 4 match[3] output
 *  0b0010111..T4_MAT2 ctimer 4 match[2] output
 *  0b0011000..T3_MAT3 ctimer 3 match[3] output
 *  0b0011001..T3_MAT2 ctimer 3 match[2] output
 *  0b0011010..T1_MAT3 ctimer 1 match[3] output
 *  0b0011011..T1_MAT2 ctimer 1 match[2] output
 *  0b0011100..UTICK0_IRQ Micro-tick timer interrupt, synced to system clock
 *  0b0011101..WDT_IRQ Watchdog Timer interrupt request, synced to system clock
 *  0b0011110..ADC0_IRQ interrupt request from ADC
 *  0b0011111..ACMP0_IRQ Combined Analog comparator interrupt request
 *  0b0100000..LSPI_HS_IRQ High speed Serial Peripheral interface interrupt request
 *  0b0100001..FLEXCOMM7_IRQ Flexcomm7 interrupt synced to system clock
 *  0b0100010..FLEXCOMM6_IRQ Flexcomm6 interrupt synced to system clock
 *  0b0100011..FLEXCOMM5_IRQ Flexcomm5 interrupt synced to system clock
 *  0b0100100..FLEXCOMM4_IRQ Flexcomm4 interrupt synced to system clock
 *  0b0100101..FLEXCOMM3_IRQ Flexcomm3 interrupt synced to system clock
 *  0b0100110..FLEXCOMM2_IRQ Flexcomm2 interrupt synced to system clock
 *  0b0100111..FLEXCOMM1_IRQ Flexcomm1 interrupt synced to system clock
 *  0b0101000..FLEXCOMM0_IRQ Flexcomm0 interrupt synced to system clock
 *  0b0101001..DMA0_IRQ DMA0 interrupt request
 *  0b0101010..DMA1_IRQ DMA1 interrupt request
 *  0b0101011..SYS_IRQ combined WDT_INT Watchdog Timer interrupt request | FLASH_IRQ Flash interrupt request | BOD_IRQ BrownOut Detection interrupt request
 *  0b0101100..RTC_COMBO_IRQ Real Time Clock Combined Alarm | Wake-up interrupt request
 *  0b0101101..ARM_TXEV interrupt event from CPU0
 *  0b0101110..GPIOINT_BMATCH GPIO_INT boolean pattern match output
 *  0b0101111..Reserved
 *  0b0110000..Reserved
 *  0b0110001..ACMP_OUT output from analog comparator
 *  0b0110010..USB0_FRAME_TOGGLE
 *  0b0110011..Reserved
 *  0b0110100..OSTIMER_IRQ OS Timer interrupt request
 *  0b0110101..ADC1 interrupt
 *  0b0110110..HSCOMP0_IRQ/HSCOMP1_IRQ/HSCOMP2_IRQ
 *  0b0110111..DAC0 interrupt
 *  0b0111000..DAC1/2 interrupt
 *  0b0111001..FlexPWM0 interrupt
 *  0b0111010..FlexPWM1 interrupt
 *  0b0111011..ENC0 interrupt
 *  0b0111100..ENC1 interrupt
 *  0b0111101..AOI0_OUT0
 *  0b0111110..AOI1_OUT0
 *  0b0111111..TMPR_OUT
 *  0b1000000-0b1111110..Reserved
 */
#define INPUTMUX_EZHARCHB_INMUX_INP(x)           (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EZHARCHB_INMUX_INP_SHIFT)) & INPUTMUX_EZHARCHB_INMUX_INP_MASK)
/*! @} */

/* The count of INPUTMUX_EZHARCHB_INMUX */
#define INPUTMUX_EZHARCHB_INMUX_COUNT            (8U)

/*! @name PINTSEL - Pin interrupt select */
/*! @{ */

#define INPUTMUX_PINTSEL_INTPIN_MASK             (0x7FU)
#define INPUTMUX_PINTSEL_INTPIN_SHIFT            (0U)
/*! INTPIN - Pin number select for pin interrupt or pattern match engine input. For PIOx_y: INTPIN =
 *    (x * 32) + y. PIO0_0 to PIO1_31 correspond to numbers 0 to 63.
 */
#define INPUTMUX_PINTSEL_INTPIN(x)               (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSEL_INTPIN_MASK)
/*! @} */

/* The count of INPUTMUX_PINTSEL */
#define INPUTMUX_PINTSEL_COUNT                   (8U)

/*! @name DMA0_ITRIG_INMUX - Trigger select for DMA0 channel */
/*! @{ */

#define INPUTMUX_DMA0_ITRIG_INMUX_INP_MASK       (0x3FU)
#define INPUTMUX_DMA0_ITRIG_INMUX_INP_SHIFT      (0U)
/*! INP - Trigger input number (binary value) for DMA channel n (n = 0 to 31).
 *  0b000000..FlexSPI_RX
 *  0b000001..FlexSPI_TX
 *  0b000010..GPIO_INT0
 *  0b000011..GPIO_INT1
 *  0b000100..GPIO_INT2
 *  0b000101..GPIO_INT3
 *  0b000110..T0_DMAREQ_M0
 *  0b000111..T0_DMAREQ_M1
 *  0b001000..T1_DMAREQ_M0
 *  0b001001..T1_DMAREQ_M1
 *  0b001010..T2_DMAREQ_M0
 *  0b001011..T2_DMAREQ_M1
 *  0b001100..T3_DMAREQ_M0
 *  0b001101..T3_DMAREQ_M1
 *  0b001110..T4_DMAREQ_M0
 *  0b001111..T4_DMAREQ_M1
 *  0b010000..ACMP0_OUT
 *  0b010001..SDMA0_TRIGOUT_A
 *  0b010010..SDMA0_TRIGOUT_B
 *  0b010011..SDMA0_TRIGOUT_C
 *  0b010100..SDMA0_TRIGOUT_D
 *  0b010101..SCT_DMA0
 *  0b010110..SCT_DMA1
 *  0b010111..ADC0_tcomp[0]
 *  0b011000..ADC1_tcomp[0]
 *  0b011001..HSCMP0
 *  0b011010..HSCMP1
 *  0b011011..HSCMP2
 *  0b011100..AOI0_OUT0
 *  0b011101..AOI0_OUT1
 *  0b011110..AOI0_OUT2
 *  0b011111..AOI0_OUT3
 *  0b100000..AOI1_OUT0
 *  0b100001..AOI1_OUT1
 *  0b100010..AOI1_OUT2
 *  0b100011..AOI1_OUT3
 *  0b100100..FlexPWM0_req_capt0
 *  0b100101..FlexPWM0_req_capt1
 *  0b100110..FlexPWM0_req_capt2
 *  0b100111..FlexPWM0_req_capt3
 *  0b101000..FlexPWM0_req_val0
 *  0b101001..FlexPWM0_req_val1
 *  0b101010..FlexPWM0_req_val2
 *  0b101011..FlexPWM0_req_val3
 *  0b101100..FlexPWM1_req_capt0
 *  0b101101..FlexPWM1_req_capt1
 *  0b101110..FlexPWM1_req_capt2
 *  0b101111..FlexPWM1_req_capt3
 *  0b110000..FlexPWM1_req_val0
 *  0b110001..FlexPWM1_req_val1
 *  0b110010..FlexPWM1_req_val2
 *  0b110011..FlexPWM1_req_val3
 *  0b110100..TMPR_OUT
 *  0b110110-0b111111..Reserved
 */
#define INPUTMUX_DMA0_ITRIG_INMUX_INP(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA0_ITRIG_INMUX_INP_MASK)
/*! @} */

/* The count of INPUTMUX_DMA0_ITRIG_INMUX */
#define INPUTMUX_DMA0_ITRIG_INMUX_COUNT          (32U)

/*! @name DMA0_OTRIG_INMUX - DMA0 output trigger selection for DMA0 input trigger */
/*! @{ */

#define INPUTMUX_DMA0_OTRIG_INMUX_INP_MASK       (0x3FU)
#define INPUTMUX_DMA0_OTRIG_INMUX_INP_SHIFT      (0U)
/*! INP - DMA trigger output number (binary value) for DMA channel n (n = 0 to 52).
 */
#define INPUTMUX_DMA0_OTRIG_INMUX_INP(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA0_OTRIG_INMUX_INP_MASK)
/*! @} */

/* The count of INPUTMUX_DMA0_OTRIG_INMUX */
#define INPUTMUX_DMA0_OTRIG_INMUX_COUNT          (7U)

/*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */
/*! @{ */

#define INPUTMUX_FREQMEAS_REF_CLKIN_MASK         (0x1FU)
#define INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT        (0U)
/*! CLKIN - Clock source number (binary value) for frequency measure function target clock.
 *  0b00000..XTAL32MHz
 *  0b00001..FRO_OSC_12M
 *  0b00010..FRO_OSC_96M
 *  0b00011..WDOSC (FRO1M)
 *  0b00100..32KHZ_OSC
 *  0b00101..MAIN_SYS_CLOCK
 *  0b00110..FREQME_GPIO_CLK_A
 *  0b00111..FREQME_GPIO_CLK_B
 *  0b01000..AOI0_OUT2
 *  0b01001..AOI1_OUT2
 */
#define INPUTMUX_FREQMEAS_REF_CLKIN(x)           (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_REF_CLKIN_MASK)
/*! @} */

/*! @name FREQMEAS_TAR - Selection for frequency measurement target clock */
/*! @{ */

#define INPUTMUX_FREQMEAS_TAR_CLKIN_MASK         (0x1FU)
#define INPUTMUX_FREQMEAS_TAR_CLKIN_SHIFT        (0U)
/*! CLKIN - Clock source number (binary value) for frequency measure function target clock
 *  0b00000..XTAL32MHz
 *  0b00001..FRO_OSC_12M
 *  0b00010..FRO_OSC_96M
 *  0b00011..WDOSC (FRO1M)
 *  0b00100..32KHZ_OSC
 *  0b00101..MAIN_SYS_CLOCK
 *  0b00110..FREQME_GPIO_CLK_A
 *  0b00111..FREQME_GPIO_CLK_B
 *  0b01000..AOI0_OUT2
 *  0b01001..AOI1_OUT2
 */
#define INPUTMUX_FREQMEAS_TAR_CLKIN(x)           (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TAR_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_TAR_CLKIN_MASK)
/*! @} */

/*! @name TIMER3CAP - Capture select register for TIMER3 inputs */
/*! @{ */

#define INPUTMUX_TIMER3CAP_CAPTSEL_MASK          (0x3FU)
#define INPUTMUX_TIMER3CAP_CAPTSEL_SHIFT         (0U)
/*! CAPTSEL - Input number to TIMER3 capture inputs 0 to 5
 *  0b000000..CTIMER_INP0 function selected from IOCON register
 *  0b000001..CTIMER_INP1 function selected from IOCON register
 *  0b000010..CTIMER_INP2 function selected from IOCON register
 *  0b000011..CTIMER_INP3 function selected from IOCON register
 *  0b000100..CTIMER_INP4 function selected from IOCON register
 *  0b000101..CTIMER_INP5 function selected from IOCON register
 *  0b000110..CTIMER_INP6 function selected from IOCON register
 *  0b000111..CTIMER_INP7 function selected from IOCON register
 *  0b001000..CTIMER_INP8 function selected from IOCON register
 *  0b001001..CTIMER_INP9 function selected from IOCON register
 *  0b001010..CTIMER_INP10 function selected from IOCON register
 *  0b001011..CTIMER_INP11 function selected from IOCON register
 *  0b001100..CTIMER_INP12 function selected from IOCON register
 *  0b001101..CTIMER_INP13 function selected from IOCON register
 *  0b001110..CTIMER_INP14 function selected from IOCON register
 *  0b001111..CTIMER_INP15 function selected from IOCON register
 *  0b010000..CTIMER_INP16 function selected from IOCON register
 *  0b010001..CTIMER_INP17 function selected from IOCON register
 *  0b010010..CTIMER_INP18 function selected from IOCON register
 *  0b010011..CTIMER_INP19 function selected from IOCON register
 *  0b010100..USB0_FRAME_TOGGLE
 *  0b010101..Reserved
 *  0b010110..ACMP0_OUT from analog comparator
 *  0b010111..SHARED_I2S_WS0 output from I2S pin sharing
 *  0b011000..SHARED_I2S_WS1 output from I2S pin sharing
 *  0b011001..ADC0_IRQ
 *  0b011010..ADC1_IRQ
 *  0b011011..HSCMP0_OUT
 *  0b011100..HSCMP1_OUT
 *  0b011101..HSCMP2_OUT
 *  0b011110..PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1
 *  0b011111..PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1
 *  0b100000..PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1
 *  0b100001..PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1
 *  0b100010..PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1
 *  0b100011..PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1
 *  0b100100..PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1
 *  0b100101..PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1
 *  0b100110..ENC0_CMP/POS_MATCH
 *  0b100111..ENC1_CMP/POS_MATCH
 *  0b101000..AOI0_OUT0
 *  0b101001..AOI0_OUT1
 *  0b101010..AOI0_OUT2
 *  0b101011..AOI0_OUT3
 *  0b101100..AOI1_OUT0
 *  0b101101..AOI1_OUT1
 *  0b101110..AOI1_OUT2
 *  0b101111..AOI1_OUT3
 *  0b110000..TMPR_OUT
 *  0b110001-0b111111..None
 */
#define INPUTMUX_TIMER3CAP_CAPTSEL(x)            (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER3CAP_CAPTSEL_SHIFT)) & INPUTMUX_TIMER3CAP_CAPTSEL_MASK)
/*! @} */

/* The count of INPUTMUX_TIMER3CAP */
#define INPUTMUX_TIMER3CAP_COUNT                 (4U)

/*! @name TIMER3TRIG - Trigger register for TIMER3 */
/*! @{ */

#define INPUTMUX_TIMER3TRIG_TRIGIN_MASK          (0x3FU)
#define INPUTMUX_TIMER3TRIG_TRIGIN_SHIFT         (0U)
/*! TRIGIN - Input number to TIMER3 trigger inputs
 *  0b000000..CTIMER_INP0 function selected from IOCON register
 *  0b000001..CTIMER_INP1 function selected from IOCON register
 *  0b000010..CTIMER_INP2 function selected from IOCON register
 *  0b000011..CTIMER_INP3 function selected from IOCON register
 *  0b000100..CTIMER_INP4 function selected from IOCON register
 *  0b000101..CTIMER_INP5 function selected from IOCON register
 *  0b000110..CTIMER_INP6 function selected from IOCON register
 *  0b000111..CTIMER_INP7 function selected from IOCON register
 *  0b001000..CTIMER_INP8 function selected from IOCON register
 *  0b001001..CTIMER_INP9 function selected from IOCON register
 *  0b001010..CTIMER_INP10 function selected from IOCON register
 *  0b001011..CTIMER_INP11 function selected from IOCON register
 *  0b001100..CTIMER_INP12 function selected from IOCON register
 *  0b001101..CTIMER_INP13 function selected from IOCON register
 *  0b001110..CTIMER_INP14 function selected from IOCON register
 *  0b001111..CTIMER_INP15 function selected from IOCON register
 *  0b010000..CTIMER_INP16 function selected from IOCON register
 *  0b010001..CTIMER_INP17 function selected from IOCON register
 *  0b010010..CTIMER_INP18 function selected from IOCON register
 *  0b010011..CTIMER_INP19 function selected from IOCON register
 *  0b010100..USB0_FRAME_TOGGLE
 *  0b010101..Reserved
 *  0b010110..ACMP0_OUT from analog comparator
 *  0b010111..SHARED_I2S_WS0 output from I2S pin sharing
 *  0b011000..SHARED_I2S_WS1 output from I2S pin sharing
 *  0b011001..ADC0_IRQ
 *  0b011010..ADC1_IRQ
 *  0b011011..HSCMP0_OUT
 *  0b011100..HSCMP1_OUT
 *  0b011101..HSCMP2_OUT
 *  0b011110..PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1
 *  0b011111..PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1
 *  0b100000..PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1
 *  0b100001..PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1
 *  0b100010..PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1
 *  0b100011..PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1
 *  0b100100..PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1
 *  0b100101..PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1
 *  0b100110..ENC0_CMP/POS_MATCH
 *  0b100111..ENC1_CMP/POS_MATCH
 *  0b101000..AOI0_OUT0
 *  0b101001..AOI0_OUT1
 *  0b101010..AOI0_OUT2
 *  0b101011..AOI0_OUT3
 *  0b101100..AOI1_OUT0
 *  0b101101..AOI1_OUT1
 *  0b101110..AOI1_OUT2
 *  0b101111..AOI1_OUT3
 *  0b110000..TMPR_OUT
 *  0b110001-0b111111..None
 */
#define INPUTMUX_TIMER3TRIG_TRIGIN(x)            (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER3TRIG_TRIGIN_SHIFT)) & INPUTMUX_TIMER3TRIG_TRIGIN_MASK)
/*! @} */

/*! @name TIMER4CAP - Capture select register for TIMER4 inputs */
/*! @{ */

#define INPUTMUX_TIMER4CAP_CAPTSEL_MASK          (0x3FU)
#define INPUTMUX_TIMER4CAP_CAPTSEL_SHIFT         (0U)
/*! CAPTSEL - Input number to TIMER4 capture inputs 0 to 5
 *  0b000000..CTIMER_INP0 function selected from IOCON register
 *  0b000001..CTIMER_INP1 function selected from IOCON register
 *  0b000010..CTIMER_INP2 function selected from IOCON register
 *  0b000011..CTIMER_INP3 function selected from IOCON register
 *  0b000100..CTIMER_INP4 function selected from IOCON register
 *  0b000101..CTIMER_INP5 function selected from IOCON register
 *  0b000110..CTIMER_INP6 function selected from IOCON register
 *  0b000111..CTIMER_INP7 function selected from IOCON register
 *  0b001000..CTIMER_INP8 function selected from IOCON register
 *  0b001001..CTIMER_INP9 function selected from IOCON register
 *  0b001010..CTIMER_INP10 function selected from IOCON register
 *  0b001011..CTIMER_INP11 function selected from IOCON register
 *  0b001100..CTIMER_INP12 function selected from IOCON register
 *  0b001101..CTIMER_INP13 function selected from IOCON register
 *  0b001110..CTIMER_INP14 function selected from IOCON register
 *  0b001111..CTIMER_INP15 function selected from IOCON register
 *  0b010000..CTIMER_INP16 function selected from IOCON register
 *  0b010001..CTIMER_INP17 function selected from IOCON register
 *  0b010010..CTIMER_INP18 function selected from IOCON register
 *  0b010011..CTIMER_INP19 function selected from IOCON register
 *  0b010100..USB0_FRAME_TOGGLE
 *  0b010101..Reserved
 *  0b010110..ACMP0_OUT from analog comparator
 *  0b010111..SHARED_I2S_WS0 output from I2S pin sharing
 *  0b011000..SHARED_I2S_WS1 output from I2S pin sharing
 *  0b011001..ADC0_IRQ
 *  0b011010..ADC1_IRQ
 *  0b011011..HSCMP0_OUT
 *  0b011100..HSCMP1_OUT
 *  0b011101..HSCMP2_OUT
 *  0b011110..PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1
 *  0b011111..PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1
 *  0b100000..PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1
 *  0b100001..PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1
 *  0b100010..PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1
 *  0b100011..PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1
 *  0b100100..PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1
 *  0b100101..PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1
 *  0b100110..ENC0_CMP/POS_MATCH
 *  0b100111..ENC1_CMP/POS_MATCH
 *  0b101000..AOI0_OUT0
 *  0b101001..AOI0_OUT1
 *  0b101010..AOI0_OUT2
 *  0b101011..AOI0_OUT3
 *  0b101100..AOI1_OUT0
 *  0b101101..AOI1_OUT1
 *  0b101110..AOI1_OUT2
 *  0b101111..AOI1_OUT3
 *  0b110000..TMPR_OUT
 *  0b110001-0b111111..None
 */
#define INPUTMUX_TIMER4CAP_CAPTSEL(x)            (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER4CAP_CAPTSEL_SHIFT)) & INPUTMUX_TIMER4CAP_CAPTSEL_MASK)
/*! @} */

/* The count of INPUTMUX_TIMER4CAP */
#define INPUTMUX_TIMER4CAP_COUNT                 (4U)

/*! @name TIMER4TRIG - Trigger register for TIMER4 */
/*! @{ */

#define INPUTMUX_TIMER4TRIG_TRIGIN_MASK          (0x3FU)
#define INPUTMUX_TIMER4TRIG_TRIGIN_SHIFT         (0U)
/*! TRIGIN - Input number to TIMER4 trigger inputs
 *  0b000000..CTIMER_INP0 function selected from IOCON register
 *  0b000001..CTIMER_INP1 function selected from IOCON register
 *  0b000010..CTIMER_INP2 function selected from IOCON register
 *  0b000011..CTIMER_INP3 function selected from IOCON register
 *  0b000100..CTIMER_INP4 function selected from IOCON register
 *  0b000101..CTIMER_INP5 function selected from IOCON register
 *  0b000110..CTIMER_INP6 function selected from IOCON register
 *  0b000111..CTIMER_INP7 function selected from IOCON register
 *  0b001000..CTIMER_INP8 function selected from IOCON register
 *  0b001001..CTIMER_INP9 function selected from IOCON register
 *  0b001010..CTIMER_INP10 function selected from IOCON register
 *  0b001011..CTIMER_INP11 function selected from IOCON register
 *  0b001100..CTIMER_INP12 function selected from IOCON register
 *  0b001101..CTIMER_INP13 function selected from IOCON register
 *  0b001110..CTIMER_INP14 function selected from IOCON register
 *  0b001111..CTIMER_INP15 function selected from IOCON register
 *  0b010000..CTIMER_INP16 function selected from IOCON register
 *  0b010001..CTIMER_INP17 function selected from IOCON register
 *  0b010010..CTIMER_INP18 function selected from IOCON register
 *  0b010011..CTIMER_INP19 function selected from IOCON register
 *  0b010100..USB0_FRAME_TOGGLE
 *  0b010101..Reserved
 *  0b010110..ACMP0_OUT from analog comparator
 *  0b010111..SHARED_I2S_WS0 output from I2S pin sharing
 *  0b011000..SHARED_I2S_WS1 output from I2S pin sharing
 *  0b011001..ADC0_IRQ
 *  0b011010..ADC1_IRQ
 *  0b011011..HSCMP0_OUT
 *  0b011100..HSCMP1_OUT
 *  0b011101..HSCMP2_OUT
 *  0b011110..PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1
 *  0b011111..PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1
 *  0b100000..PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1
 *  0b100001..PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1
 *  0b100010..PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1
 *  0b100011..PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1
 *  0b100100..PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1
 *  0b100101..PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1
 *  0b100110..ENC0_CMP/POS_MATCH
 *  0b100111..ENC1_CMP/POS_MATCH
 *  0b101000..AOI0_OUT0
 *  0b101001..AOI0_OUT1
 *  0b101010..AOI0_OUT2
 *  0b101011..AOI0_OUT3
 *  0b101100..AOI1_OUT0
 *  0b101101..AOI1_OUT1
 *  0b101110..AOI1_OUT2
 *  0b101111..AOI1_OUT3
 *  0b110000..TMPR_OUT
 *  0b110001-0b111111..None
 */
#define INPUTMUX_TIMER4TRIG_TRIGIN(x)            (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER4TRIG_TRIGIN_SHIFT)) & INPUTMUX_TIMER4TRIG_TRIGIN_MASK)
/*! @} */

/*! @name PINTSECSEL - Pin interrupt secure select */
/*! @{ */

#define INPUTMUX_PINTSECSEL_INTPIN_MASK          (0x3FU)
#define INPUTMUX_PINTSECSEL_INTPIN_SHIFT         (0U)
/*! INTPIN - Pin number select for pin interrupt secure or pattern match engine input. For PIO0_x:
 *    INTPIN = x. PIO0_0 to PIO0_31 correspond to numbers 0 to 31.
 */
#define INPUTMUX_PINTSECSEL_INTPIN(x)            (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSECSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSECSEL_INTPIN_MASK)
/*! @} */

/* The count of INPUTMUX_PINTSECSEL */
#define INPUTMUX_PINTSECSEL_COUNT                (2U)

/*! @name DMA1_ITRIG_INMUX - Trigger select for DMA1 channel */
/*! @{ */

#define INPUTMUX_DMA1_ITRIG_INMUX_INP_MASK       (0x1FU)
#define INPUTMUX_DMA1_ITRIG_INMUX_INP_SHIFT      (0U)
/*! INP - Trigger input number (binary value) for DMA channel n (n = 0 to 14).
 *  0b00000..Pin interrupt 0 (GPIO_INT0)
 *  0b00001..Pin interrupt 1 (GPIO_INT1)
 *  0b00010..Pin interrupt 2 (GPIO_INT2)
 *  0b00011..Pin interrupt 3 (GPIO_INT3)
 *  0b00100..Timer CTIMER0 Match 0 (T0_DMAREQ_M0)
 *  0b00101..Timer CTIMER0 Match 1 (T0_DMAREQ_M1)
 *  0b00110..Timer CTIMER2 Match 0 (T2_DMAREQ_M0)
 *  0b00111..Timer CTIMER4 Match 0 (T4_DMAREQ_M0)
 *  0b01000..SDMA1_TRIGOUT_A
 *  0b01001..SDMA1_TRIGOUT_B
 *  0b01010..SDMA1_TRIGOUT_C
 *  0b01011..SDMA1_TRIGOUT_D
 *  0b01100..SCT_DMA_REQ0
 *  0b01101..SCT_DMA_REQ1
 *  0b01110..FlexSPI_RX
 *  0b01111..FlexSPI_TX
 *  0b10000..AOI0_OUT0
 *  0b10001..AOI0_OUT1
 *  0b10010..AOI0_OUT2
 *  0b10011..AOI0_OUT3
 *  0b10100..AOI1_OUT0
 *  0b10101..AOI1_OUT1
 *  0b10110..AOI1_OUT2
 *  0b10111..AOI1_OUT3
 *  0b11000..TMPR_OUT
 *  0b11001-0b11111..Reserved
 */
#define INPUTMUX_DMA1_ITRIG_INMUX_INP(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA1_ITRIG_INMUX_INP_MASK)
/*! @} */

/* The count of INPUTMUX_DMA1_ITRIG_INMUX */
#define INPUTMUX_DMA1_ITRIG_INMUX_COUNT          (16U)

/*! @name DMA1_OTRIG_INMUX - DMA1 output trigger selection for DMA1 input trigger */
/*! @{ */

#define INPUTMUX_DMA1_OTRIG_INMUX_SDMA1_CH_TRIGOUT_MASK (0xFU)
#define INPUTMUX_DMA1_OTRIG_INMUX_SDMA1_CH_TRIGOUT_SHIFT (0U)
/*! SDMA1_CH_TRIGOUT - DMA trigger output number (binary value) for DMA channel n (n = 0 to 15).
 *  0b0000..SDMA1_CH0_TRIGOUT
 *  0b0001..SDMA1_CH1_TRIGOUT
 *  0b0010..SDMA1_CH2_TRIGOUT
 *  0b0011..SDMA1_CH3_TRIGOUT
 *  0b0100..SDMA1_CH4_TRIGOUT
 *  0b0101..SDMA1_CH5_TRIGOUT
 *  0b0110..SDMA1_CH6_TRIGOUT
 *  0b0111..SDMA1_CH7_TRIGOUT
 *  0b1000..SDMA1_CH8_TRIGOUT
 *  0b1001..SDMA1_CH9_TRIGOUT
 *  0b1010..SDMA1_CH10_TRIGOUT
 *  0b1011..SDMA1_CH11_TRIGOUT
 *  0b1100..SDMA1_CH12_TRIGOUT
 *  0b1101..SDMA1_CH13_TRIGOUT
 *  0b1110-0b1111..Reserved
 */
#define INPUTMUX_DMA1_OTRIG_INMUX_SDMA1_CH_TRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_OTRIG_INMUX_SDMA1_CH_TRIGOUT_SHIFT)) & INPUTMUX_DMA1_OTRIG_INMUX_SDMA1_CH_TRIGOUT_MASK)
/*! @} */

/* The count of INPUTMUX_DMA1_OTRIG_INMUX */
#define INPUTMUX_DMA1_OTRIG_INMUX_COUNT          (4U)

/*! @name HSCMP0_TRIG - Input connections for HSCMP0 */
/*! @{ */

#define INPUTMUX_HSCMP0_TRIG_TRIGIN_MASK         (0x3FU)
#define INPUTMUX_HSCMP0_TRIG_TRIGIN_SHIFT        (0U)
/*! TRIGIN - CMP0 input trigger
 *  0b000000..PIN_INT0
 *  0b000001..PIN_INT6
 *  0b000010..SCT_OUT4
 *  0b000011..SCT_OUT5
 *  0b000100..SCT_OUT6
 *  0b000101..T0_MAT3
 *  0b000110..T1_MAT3
 *  0b000111..T2_MAT3
 *  0b001000..T0_MAT0
 *  0b001001..T4_MAT0
 *  0b001010..Reserved
 *  0b001011..ARM_TXEV
 *  0b001100..GPIOINT_BMATCH
 *  0b001101..ADC0_tcomp[0]
 *  0b001110..ADC1_tcomp[0]
 *  0b001111..Reserved
 *  0b010000..Reserved
 *  0b010001..PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1
 *  0b010010..PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1
 *  0b010011..PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1
 *  0b010100..PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1
 *  0b010101..PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1
 *  0b010110..PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1
 *  0b010111..PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1
 *  0b011000..PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1
 *  0b011001..ENC0_CMP/POS_MATCH
 *  0b011010..ENC1_CMP/POS_MATCH
 *  0b011011..AOI0_OUT0
 *  0b011100..AOI0_OUT1
 *  0b011101..AOI0_OUT2
 *  0b011110..AOI0_OUT3
 *  0b011111..AOI1_OUT0
 *  0b100000..AOI1_OUT1
 *  0b100001..AOI1_OUT2
 *  0b100010..AOI1_OUT3
 *  0b100011..DMA0_TRIGOUT0
 *  0b100100..DMA0_TRIGOUT1
 *  0b100101..DMA0_TRIGOUT2
 */
#define INPUTMUX_HSCMP0_TRIG_TRIGIN(x)           (((uint32_t)(((uint32_t)(x)) << INPUTMUX_HSCMP0_TRIG_TRIGIN_SHIFT)) & INPUTMUX_HSCMP0_TRIG_TRIGIN_MASK)
/*! @} */

/*! @name ADC0_TRIGN_ADC0_TRIG - ADC0 Trigger input connections */
/*! @{ */

#define INPUTMUX_ADC0_TRIGN_ADC0_TRIG_TRIGIN_MASK (0x3FU)
#define INPUTMUX_ADC0_TRIGN_ADC0_TRIG_TRIGIN_SHIFT (0U)
/*! TRIGIN - ADC0 trigger inputs
 *  0b000000..PIN_INT0
 *  0b000001..PIN_INT1
 *  0b000010..SCT_OUT4
 *  0b000011..SCT_OUT5
 *  0b000100..SCT_OUT9
 *  0b000101..T0_MAT3
 *  0b000110..T1_MAT3
 *  0b000111..T2_MAT3
 *  0b001000..T3_MAT3
 *  0b001001..T4_MAT3
 *  0b001010..ACMP0_OUT
 *  0b001011..ARM_TXEV
 *  0b001100..GPIOINT_BMATCH
 *  0b001101..ADC0_tcomp[0]
 *  0b001110..ADC0_tcomp[1]
 *  0b001111..ADC0_tcomp[2]
 *  0b010000..ADC0_tcomp[3]
 *  0b010001..ADC1_tcomp[0]
 *  0b010010..ADC1_tcomp[1]
 *  0b010011..ADC1_tcomp[2]
 *  0b010100..ADC1_tcomp[3]
 *  0b010101..HSCMP0_OUT
 *  0b010110..HSCMP1_OUT
 *  0b010111..HSCMP2_OUT
 *  0b011000..PWM0_SM0_MUX_TRIG0
 *  0b011001..PWM0_SM0_MUX_TRIG1
 *  0b011010..PWM0_SM1_MUX_TRIG0
 *  0b011011..PWM0_SM1_MUX_TRIG1
 *  0b011100..PWM0_SM2_MUX_TRIG0
 *  0b011101..PWM0_SM2_MUX_TRIG1
 *  0b011110..PWM0_SM3_MUX_TRIG0
 *  0b011111..PWM0_SM3_MUX_TRIG1
 *  0b100000..PWM1_SM0_MUX_TRIG0
 *  0b100001..PWM1_SM0_MUX_TRIG1
 *  0b100010..PWM1_SM1_MUX_TRIG0
 *  0b100011..PWM1_SM1_MUX_TRIG1
 *  0b100100..PWM1_SM2_MUX_TRIG0
 *  0b100101..PWM1_SM2_MUX_TRIG1
 *  0b100110..PWM1_SM3_MUX_TRIG0
 *  0b100111..PWM1_SM3_MUX_TRIG1
 *  0b101000..ENC0_CMP/POS_MATCH
 *  0b101001..ENC1_CMP/POS_MATCH
 *  0b101010..AOI0_OUT0
 *  0b101011..AOI0_OUT1
 *  0b101100..AOI0_OUT2
 *  0b101101..AOI0_OUT3
 *  0b101110..AOI1_OUT0
 *  0b101111..AOI1_OUT1
 *  0b110000..AOI1_OUT2
 *  0b110001..AOI1_OUT3
 *  0b110010..DMA0_TRIGOUT0
 *  0b110011..DMA0_TRIGOUT1
 *  0b110100..DMA0_TRIGOUT2
 *  0b110101-0b111111..None
 */
#define INPUTMUX_ADC0_TRIGN_ADC0_TRIG_TRIGIN(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ADC0_TRIGN_ADC0_TRIG_TRIGIN_SHIFT)) & INPUTMUX_ADC0_TRIGN_ADC0_TRIG_TRIGIN_MASK)
/*! @} */

/* The count of INPUTMUX_ADC0_TRIGN_ADC0_TRIG */
#define INPUTMUX_ADC0_TRIGN_ADC0_TRIG_COUNT      (4U)

/*! @name ADC1_TRIGN_ADC1_TRIG - ADC1 Trigger input connections */
/*! @{ */

#define INPUTMUX_ADC1_TRIGN_ADC1_TRIG_TRIGIN_MASK (0x3FU)
#define INPUTMUX_ADC1_TRIGN_ADC1_TRIG_TRIGIN_SHIFT (0U)
/*! TRIGIN - ADC1 trigger inputs
 *  0b000000..PIN_INT0
 *  0b000001..PIN_INT2
 *  0b000010..SCT_OUT4
 *  0b000011..SCT_OUT5
 *  0b000100..SCT_OUT3
 *  0b000101..T0_MAT3
 *  0b000110..T1_MAT3
 *  0b000111..T2_MAT3
 *  0b001000..T3_MAT2
 *  0b001001..T4_MAT1
 *  0b001010..ACMP0_OUT
 *  0b001011..ARM_TXEV
 *  0b001100..GPIOINT_BMATCH
 *  0b001101..ADC0_tcomp[0]
 *  0b001110..ADC0_tcomp[1]
 *  0b001111..ADC0_tcomp[2]
 *  0b010000..ADC0_tcomp[3]
 *  0b010001..ADC1_tcomp[0]
 *  0b010010..ADC1_tcomp[1]
 *  0b010011..ADC1_tcomp[2]
 *  0b010100..ADC1_tcomp[3]
 *  0b010101..HSCMP0_OUT
 *  0b010110..HSCMP1_OUT
 *  0b010111..HSCMP2_OUT
 *  0b011000..PWM0_SM0_MUX_TRIG0
 *  0b011001..PWM0_SM0_MUX_TRIG1
 *  0b011010..PWM0_SM1_MUX_TRIG0
 *  0b011011..PWM0_SM1_MUX_TRIG1
 *  0b011100..PWM0_SM2_MUX_TRIG0
 *  0b011101..PWM0_SM2_MUX_TRIG1
 *  0b011110..PWM0_SM3_MUX_TRIG0
 *  0b011111..PWM0_SM3_MUX_TRIG1
 *  0b100000..PWM1_SM0_MUX_TRIG0
 *  0b100001..PWM1_SM0_MUX_TRIG1
 *  0b100010..PWM1_SM1_MUX_TRIG0
 *  0b100011..PWM1_SM1_MUX_TRIG1
 *  0b100100..PWM1_SM2_MUX_TRIG0
 *  0b100101..PWM1_SM2_MUX_TRIG1
 *  0b100110..PWM1_SM3_MUX_TRIG0
 *  0b100111..PWM1_SM3_MUX_TRIG1
 *  0b101000..ENC0_CMP/POS_MATCH
 *  0b101001..ENC1_CMP/POS_MATCH
 *  0b101010..AOI0_OUT0
 *  0b101011..AOI0_OUT1
 *  0b101100..AOI0_OUT2
 *  0b101101..AOI0_OUT3
 *  0b101110..AOI1_OUT0
 *  0b101111..AOI1_OUT1
 *  0b110000..AOI1_OUT2
 *  0b110001..AOI1_OUT3
 *  0b110010..DMA0_TRIGOUT0
 *  0b110011..DMA0_TRIGOUT1
 *  0b110100..DMA0_TRIGOUT2
 *  0b110101-0b111111..None
 */
#define INPUTMUX_ADC1_TRIGN_ADC1_TRIG_TRIGIN(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ADC1_TRIGN_ADC1_TRIG_TRIGIN_SHIFT)) & INPUTMUX_ADC1_TRIGN_ADC1_TRIG_TRIGIN_MASK)
/*! @} */

/* The count of INPUTMUX_ADC1_TRIGN_ADC1_TRIG */
#define INPUTMUX_ADC1_TRIGN_ADC1_TRIG_COUNT      (4U)

/*! @name DAC0_TRIG - DAC0 Trigger Inputs */
/*! @{ */

#define INPUTMUX_DAC0_TRIG_TRIGIN_MASK           (0x1FU)
#define INPUTMUX_DAC0_TRIG_TRIGIN_SHIFT          (0U)
/*! TRIGIN - DAC0 trigger input
 *  0b00000..PIN_INT0
 *  0b00001..PIN_INT3
 *  0b00010..SCT_OUT4
 *  0b00011..SCT_OUT5
 *  0b00100..SCT_OUT0
 *  0b00101..T0_MAT3
 *  0b00110..T1_MAT3
 *  0b00111..T2_MAT3
 *  0b01000..T2_MAT0
 *  0b01001..T3_MAT0
 *  0b01010..ACMP0_OUT
 *  0b01011..ARM_TXEV
 *  0b01100..GPIOINT_BMATCH
 *  0b01101..ADC0_tcomp[0]
 *  0b01110..ADC1_tcomp[0]
 *  0b01111..HSCMP0_OUT
 *  0b10000..HSCMP1_OUT
 *  0b10001..HSCMP2_OUT
 *  0b10010..AOI0_OUT0
 *  0b10011..AOI0_OUT1
 *  0b10100..AOI0_OUT2
 *  0b10101..AOI0_OUT3
 *  0b10110..AOI1_OUT0
 *  0b10111..AOI1_OUT1
 *  0b11000..AOI1_OUT2
 *  0b11001..AOI1_OUT3
 *  0b11010..DMA0_TRIGOUT0
 *  0b11011..DMA0_TRIGOUT1
 *  0b11100..DMA0_TRIGOUT2
 */
#define INPUTMUX_DAC0_TRIG_TRIGIN(x)             (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DAC0_TRIG_TRIGIN_SHIFT)) & INPUTMUX_DAC0_TRIG_TRIGIN_MASK)
/*! @} */

/*! @name DAC1_TRIG - DAC1 Trigger Inputs */
/*! @{ */

#define INPUTMUX_DAC1_TRIG_TRIGIN_MASK           (0x1FU)
#define INPUTMUX_DAC1_TRIG_TRIGIN_SHIFT          (0U)
/*! TRIGIN - DAC1 trigger input
 *  0b00000..PIN_INT0
 *  0b00001..PIN_INT4
 *  0b00010..SCT_OUT4
 *  0b00011..SCT_OUT5
 *  0b00100..SCT_OUT1
 *  0b00101..T0_MAT3
 *  0b00110..T1_MAT3
 *  0b00111..T2_MAT3
 *  0b01000..T2_MAT1
 *  0b01001..T3_MAT1
 *  0b01010..ACMP0_OUT
 *  0b01011..ARM_TXEV
 *  0b01100..GPIOINT_BMATCH
 *  0b01101..ADC0_tcomp[1]
 *  0b01110..ADC1_tcomp[1]
 *  0b01111..HSCMP0_OUT
 *  0b10000..HSCMP1_OUT
 *  0b10001..HSCMP2_OUT
 *  0b10010..AOI0_OUT0
 *  0b10011..AOI0_OUT1
 *  0b10100..AOI0_OUT2
 *  0b10101..AOI0_OUT3
 *  0b10110..AOI1_OUT0
 *  0b10111..AOI1_OUT1
 *  0b11000..AOI1_OUT2
 *  0b11001..AOI1_OUT3
 *  0b11010..DMA0_TRIGOUT0
 *  0b11011..DMA0_TRIGOUT1
 *  0b11100..DMA0_TRIGOUT2
 */
#define INPUTMUX_DAC1_TRIG_TRIGIN(x)             (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DAC1_TRIG_TRIGIN_SHIFT)) & INPUTMUX_DAC1_TRIG_TRIGIN_MASK)
/*! @} */

/*! @name DAC2_TRIG - DAC2 Trigger Inputs */
/*! @{ */

#define INPUTMUX_DAC2_TRIG_TRIGIN_MASK           (0x1FU)
#define INPUTMUX_DAC2_TRIG_TRIGIN_SHIFT          (0U)
/*! TRIGIN - DAC2 trigger input
 *  0b00000..PIN_INT0
 *  0b00001..PIN_INT5
 *  0b00010..SCT_OUT4
 *  0b00011..SCT_OUT5
 *  0b00100..SCT_OUT2
 *  0b00101..T0_MAT3
 *  0b00110..T1_MAT3
 *  0b00111..T2_MAT3
 *  0b01000..T2_MAT2
 *  0b01001..T3_MAT2
 *  0b01010..ACMP0_OUT
 *  0b01011..ARM_TXEV
 *  0b01100..GPIOINT_BMATCH
 *  0b01101..ADC0_tcomp[2]
 *  0b01110..ADC1_tcomp[2]
 *  0b01111..HSCMP0_OUT
 *  0b10000..HSCMP1_OUT
 *  0b10001..HSCMP2_OUT
 *  0b10010..AOI0_OUT0
 *  0b10011..AOI0_OUT1
 *  0b10100..AOI0_OUT2
 *  0b10101..AOI0_OUT3
 *  0b10110..AOI1_OUT0
 *  0b10111..AOI1_OUT1
 *  0b11000..AOI1_OUT2
 *  0b11001..AOI1_OUT3
 *  0b11010..DMA0_TRIGOUT0
 *  0b11011..DMA0_TRIGOUT1
 *  0b11100..DMA0_TRIGOUT2
 */
#define INPUTMUX_DAC2_TRIG_TRIGIN(x)             (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DAC2_TRIG_TRIGIN_SHIFT)) & INPUTMUX_DAC2_TRIG_TRIGIN_MASK)
/*! @} */

/*! @name ENC0_TRIG - ENC0 Trigger Input Connections */
/*! @{ */

#define INPUTMUX_ENC0_TRIG_TRIGIN_MASK           (0x3FU)
#define INPUTMUX_ENC0_TRIG_TRIGIN_SHIFT          (0U)
/*! TRIGIN - ENC0 input trigger
 *  0b000000..PIN_INT0
 *  0b000001..PIN_INT4
 *  0b000010..SCT_OUT4
 *  0b000011..SCT_OUT5
 *  0b000100..SCT_OUT1
 *  0b000101..T0_MAT3
 *  0b000110..T1_MAT3
 *  0b000111..T2_MAT3
 *  0b001000..T1_MAT0
 *  0b001001..T3_MAT0
 *  0b001010..ACMP0_OUT
 *  0b001011..ARM_TXEV
 *  0b001100..GPIOINT_BMATCH
 *  0b001101..ADC0_tcomp[0]
 *  0b001110..ADC0_tcomp[1]
 *  0b001111..ADC0_tcomp[2]
 *  0b010000..ADC0_tcomp[3]
 *  0b010001..ADC1_tcomp[0]
 *  0b010010..ADC1_tcomp[1]
 *  0b010011..ADC1_tcomp[2]
 *  0b010100..ADC1_tcomp[3]
 *  0b010101..HSCMP0_OUT
 *  0b010110..HSCMP1_OUT
 *  0b010111..HSCMP2_OUT
 *  0b011000..PWM1_SM0_MUX_TRIG0
 *  0b011001..PWM1_SM0_MUX_TRIG1
 *  0b011010..PWM1_SM1_MUX_TRIG0
 *  0b011011..PWM1_SM1_MUX_TRIG1
 *  0b011100..PWM1_SM2_MUX_TRIG0
 *  0b011101..PWM1_SM2_MUX_TRIG1
 *  0b011110..PWM1_SM3_MUX_TRIG0
 *  0b011111..PWM1_SM3_MUX_TRIG1
 *  0b100000..ENC0_CMP/POS_MATCH
 *  0b100001..ENC1_CMP/POS_MATCH
 *  0b100010..AOI0_OUT0
 *  0b100011..AOI0_OUT1
 *  0b100100..AOI0_OUT2
 *  0b100101..AOI0_OUT3
 *  0b100110..AOI1_OUT0
 *  0b100111..AOI1_OUT1
 *  0b101000..AOI1_OUT2
 *  0b101001..AOI1_OUT3
 *  0b101010..EXTTRIG_IN0
 *  0b101011..EXTTRIG_IN1
 *  0b101100..EXTTRIG_IN2
 *  0b101101..EXTTRIG_IN3
 *  0b101110..EXTTRIG_IN4
 *  0b101111..EXTTRIG_IN5
 *  0b110000..EXTTRIG_IN6
 *  0b110001..EXTTRIG_IN7
 *  0b110010..EXTTRIG_IN8
 *  0b110011..EXTTRIG_IN9
 *  0b110100..DMA0_TRIGOUT0
 *  0b110101..DMA0_TRIGOUT1
 *  0b110110..DMA0_TRIGOUT2
 */
#define INPUTMUX_ENC0_TRIG_TRIGIN(x)             (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ENC0_TRIG_TRIGIN_SHIFT)) & INPUTMUX_ENC0_TRIG_TRIGIN_MASK)
/*! @} */

/*! @name ENC0_HOME - ENC0 Input Connections */
/*! @{ */

#define INPUTMUX_ENC0_HOME_ENC0_HOME_MASK        (0x3FU)
#define INPUTMUX_ENC0_HOME_ENC0_HOME_SHIFT       (0U)
/*! ENC0_HOME - ENC0 Input Connections
 *  0b000000..PIN_INT0
 *  0b000001..PIN_INT4
 *  0b000010..SCT_OUT4
 *  0b000011..SCT_OUT5
 *  0b000100..SCT_OUT1
 *  0b000101..T0_MAT3
 *  0b000110..T1_MAT3
 *  0b000111..T2_MAT3
 *  0b001000..T1_MAT0
 *  0b001001..T3_MAT0
 *  0b001010..ACMP0_OUT
 *  0b001011..ARM_TXEV
 *  0b001100..GPIOINT_BMATCH
 *  0b001101..ADC0_tcomp[0]
 *  0b001110..ADC0_tcomp[1]
 *  0b001111..ADC0_tcomp[2]
 *  0b010000..ADC0_tcomp[3]
 *  0b010001..ADC1_tcomp[0]
 *  0b010010..ADC1_tcomp[1]
 *  0b010011..ADC1_tcomp[2]
 *  0b010100..ADC1_tcomp[3]
 *  0b010101..HSCMP0_OUT
 *  0b010110..HSCMP1_OUT
 *  0b010111..HSCMP2_OUT
 *  0b011000..PWM1_SM0_MUX_TRIG0
 *  0b011001..PWM1_SM0_MUX_TRIG1
 *  0b011010..PWM1_SM0_MUX_TRIG0
 *  0b011011..PWM1_SM1_MUX_TRIG1
 *  0b011100..PWM1_SM2_MUX_TRIG0
 *  0b011101..PWM1_SM2_MUX_TRIG1
 *  0b011110..PWM1_SM3_MUX_TRIG0
 *  0b011111..PWM1_SM3_MUX_TRIG1
 *  0b100000..ENC0_CMP/POS_MATCH
 *  0b100001..ENC1_CMP/POS_MATCH
 *  0b100010..AOI0_OUT0
 *  0b100011..AOI0_OUT1
 *  0b100100..AOI0_OUT2
 *  0b100101..AOI0_OUT3
 *  0b100110..AOI1_OUT0
 *  0b100111..AOI1_OUT1
 *  0b101000..AOI1_OUT2
 *  0b101001..AOI1_OUT3
 *  0b101010..EXTTRIG_IN0
 *  0b101011..EXTTRIG_IN1
 *  0b101100..EXTTRIG_IN2
 *  0b101101..EXTTRIG_IN3
 *  0b101110..EXTTRIG_IN4
 *  0b101111..EXTTRIG_IN5
 *  0b110000..EXTTRIG_IN6
 *  0b110001..EXTTRIG_IN7
 *  0b110010..EXTTRIG_IN8
 *  0b110011..EXTTRIG_IN9
 *  0b110100..DMA0_TRIGOUT0
 *  0b110101..DMA0_TRIGOUT1
 *  0b110110..DMA0_TRIGOUT2
 */
#define INPUTMUX_ENC0_HOME_ENC0_HOME(x)          (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ENC0_HOME_ENC0_HOME_SHIFT)) & INPUTMUX_ENC0_HOME_ENC0_HOME_MASK)
/*! @} */

/*! @name ENC0_INDEX - ENC0 Input Connections */
/*! @{ */

#define INPUTMUX_ENC0_INDEX_ENC0_INDEX_MASK      (0x3FU)
#define INPUTMUX_ENC0_INDEX_ENC0_INDEX_SHIFT     (0U)
/*! ENC0_INDEX - ENC0 Input Connections
 *  0b000000..PIN_INT0
 *  0b000001..PIN_INT4
 *  0b000010..SCT_OUT4
 *  0b000011..SCT_OUT5
 *  0b000100..SCT_OUT1
 *  0b000101..T0_MAT3
 *  0b000110..T1_MAT3
 *  0b000111..T2_MAT3
 *  0b001000..T1_MAT0
 *  0b001001..T3_MAT0
 *  0b001010..ACMP0_OUT
 *  0b001011..ARM_TXEV
 *  0b001100..GPIOINT_BMATCH
 *  0b001101..ADC0_tcomp[0]
 *  0b001110..ADC0_tcomp[1]
 *  0b001111..ADC0_tcomp[2]
 *  0b010000..ADC0_tcomp[3]
 *  0b010001..ADC1_tcomp[0]
 *  0b010010..ADC1_tcomp[1]
 *  0b010011..ADC1_tcomp[2]
 *  0b010100..ADC1_tcomp[3]
 *  0b010101..HSCMP0_OUT
 *  0b010110..HSCMP1_OUT
 *  0b010111..HSCMP2_OUT
 *  0b011000..PWM1_SM0_MUX_TRIG0
 *  0b011001..PWM1_SM0_MUX_TRIG1
 *  0b011010..PWM1_SM1_MUX_TRIG0
 *  0b011011..PWM1_SM1_MUX_TRIG1
 *  0b011100..PWM1_SM2_MUX_TRIG0
 *  0b011101..PWM1_SM2_MUX_TRIG1
 *  0b011110..PWM1_SM3_MUX_TRIG0
 *  0b011111..PWM1_SM3_MUX_TRIG1
 *  0b100000..ENC0_CMP/POS_MATCH
 *  0b100001..ENC1_CMP/POS_MATCH
 *  0b100010..AOI0_OUT0
 *  0b100011..AOI0_OUT1
 *  0b100100..AOI0_OUT2
 *  0b100101..AOI0_OUT3
 *  0b100110..AOI1_OUT0
 *  0b100111..AOI1_OUT1
 *  0b101000..AOI1_OUT2
 *  0b101001..AOI1_OUT3
 *  0b101010..EXTTRIG_IN0
 *  0b101011..EXTTRIG_IN1
 *  0b101100..EXTTRIG_IN2
 *  0b101101..EXTTRIG_IN3
 *  0b101110..EXTTRIG_IN4
 *  0b101111..EXTTRIG_IN5
 *  0b110000..EXTTRIG_IN6
 *  0b110001..EXTTRIG_IN7
 *  0b110010..EXTTRIG_IN8
 *  0b110011..EXTTRIG_IN9
 *  0b110100..DMA0_TRIGOUT0
 *  0b110101..DMA0_TRIGOUT1
 *  0b110110..DMA0_TRIGOUT2
 */
#define INPUTMUX_ENC0_INDEX_ENC0_INDEX(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ENC0_INDEX_ENC0_INDEX_SHIFT)) & INPUTMUX_ENC0_INDEX_ENC0_INDEX_MASK)
/*! @} */

/*! @name ENC0_PHASEB - ENC0 Input Connections */
/*! @{ */

#define INPUTMUX_ENC0_PHASEB_ENC0_PHASEB_MASK    (0x3FU)
#define INPUTMUX_ENC0_PHASEB_ENC0_PHASEB_SHIFT   (0U)
/*! ENC0_PHASEB - ENC0 Input Connections
 *  0b000000..PIN_INT0
 *  0b000001..PIN_INT4
 *  0b000010..SCT_OUT4
 *  0b000011..SCT_OUT5
 *  0b000100..SCT_OUT1
 *  0b000101..T0_MAT3
 *  0b000110..T1_MAT3
 *  0b000111..T2_MAT3
 *  0b001000..T1_MAT0
 *  0b001001..T3_MAT0
 *  0b001010..ACMP0_OUT
 *  0b001011..ARM_TXEV
 *  0b001100..GPIOINT_BMATCH
 *  0b001101..ADC0_tcomp[0]
 *  0b001110..ADC0_tcomp[1]
 *  0b001111..ADC0_tcomp[2]
 *  0b010000..ADC0_tcomp[3]
 *  0b010001..ADC1_tcomp[0]
 *  0b010010..ADC1_tcomp[1]
 *  0b010011..ADC1_tcomp[2]
 *  0b010100..ADC1_tcomp[3]
 *  0b010101..HSCMP0_OUT
 *  0b010110..HSCMP1_OUT
 *  0b010111..HSCMP2_OUT
 *  0b011000..PWM1_SM0_MUX_TRIG0
 *  0b011001..PWM1_SM0_MUX_TRIG1
 *  0b011010..PWM1_SM1_MUX_TRIG0
 *  0b011011..PWM1_SM1_MUX_TRIG1
 *  0b011100..PWM1_SM2_MUX_TRIG0
 *  0b011101..PWM1_SM2_MUX_TRIG1
 *  0b011110..PWM1_SM3_MUX_TRIG0
 *  0b011111..PWM1_SM3_MUX_TRIG1
 *  0b100000..ENC0_CMP/POS_MATCH
 *  0b100001..ENC1_CMP/POS_MATCH
 *  0b100010..AOI0_OUT0
 *  0b100011..AOI0_OUT1
 *  0b100100..AOI0_OUT2
 *  0b100101..AOI0_OUT3
 *  0b100110..AOI1_OUT0
 *  0b100111..AOI1_OUT1
 *  0b101000..AOI1_OUT2
 *  0b101001..AOI1_OUT3
 *  0b101010..EXTTRIG_IN0
 *  0b101011..EXTTRIG_IN1
 *  0b101100..EXTTRIG_IN2
 *  0b101101..EXTTRIG_IN3
 *  0b101110..EXTTRIG_IN4
 *  0b101111..EXTTRIG_IN5
 *  0b110000..EXTTRIG_IN6
 *  0b110001..EXTTRIG_IN7
 *  0b110010..EXTTRIG_IN8
 *  0b110011..EXTTRIG_IN9
 *  0b110100..DMA0_TRIGOUT0
 *  0b110101..DMA0_TRIGOUT1
 *  0b110110..DMA0_TRIGOUT2
 */
#define INPUTMUX_ENC0_PHASEB_ENC0_PHASEB(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ENC0_PHASEB_ENC0_PHASEB_SHIFT)) & INPUTMUX_ENC0_PHASEB_ENC0_PHASEB_MASK)
/*! @} */

/*! @name ENC0_PHASEA - ENC0 Input Connections */
/*! @{ */

#define INPUTMUX_ENC0_PHASEA_ENC0_PHASEA_MASK    (0x3FU)
#define INPUTMUX_ENC0_PHASEA_ENC0_PHASEA_SHIFT   (0U)
/*! ENC0_PHASEA - ENC0 Input Connections
 *  0b000000..PIN_INT0
 *  0b000001..PIN_INT4
 *  0b000010..SCT_OUT4
 *  0b000011..SCT_OUT5
 *  0b000100..SCT_OUT1
 *  0b000101..T0_MAT3
 *  0b000110..T1_MAT3
 *  0b000111..T2_MAT3
 *  0b001000..T1_MAT0
 *  0b001001..T3_MAT0
 *  0b001010..ACMP0_OUT
 *  0b001011..ARM_TXEV
 *  0b001100..GPIOINT_BMATCH
 *  0b001101..ADC0_tcomp[0]
 *  0b001110..ADC0_tcomp[1]
 *  0b001111..ADC0_tcomp[2]
 *  0b010000..ADC0_tcomp[3]
 *  0b010001..ADC1_tcomp[0]
 *  0b010010..ADC1_tcomp[1]
 *  0b010011..ADC1_tcomp[2]
 *  0b010100..ADC1_tcomp[3]
 *  0b010101..HSCMP0_OUT
 *  0b010110..HSCMP1_OUT
 *  0b010111..HSCMP2_OUT
 *  0b011000..PWM1_SM0_MUX_TRIG0
 *  0b011001..PWM1_SM0_MUX_TRIG1
 *  0b011010..PWM1_SM1_MUX_TRIG0
 *  0b011011..PWM1_SM1_MUX_TRIG1
 *  0b011100..PWM1_SM2_MUX_TRIG0
 *  0b011101..PWM1_SM2_MUX_TRIG1
 *  0b011110..PWM1_SM3_MUX_TRIG0
 *  0b011111..PWM1_SM3_MUX_TRIG1
 *  0b100000..ENC0_CMP/POS_MATCH
 *  0b100001..ENC1_CMP/POS_MATCH
 *  0b100010..AOI0_OUT0
 *  0b100011..AOI0_OUT1
 *  0b100100..AOI0_OUT2
 *  0b100101..AOI0_OUT3
 *  0b100110..AOI1_OUT0
 *  0b100111..AOI1_OUT1
 *  0b101000..AOI1_OUT2
 *  0b101001..AOI1_OUT3
 *  0b101010..EXTTRIG_IN0
 *  0b101011..EXTTRIG_IN1
 *  0b101100..EXTTRIG_IN2
 *  0b101101..EXTTRIG_IN3
 *  0b101110..EXTTRIG_IN4
 *  0b101111..EXTTRIG_IN5
 *  0b110000..EXTTRIG_IN6
 *  0b110001..EXTTRIG_IN7
 *  0b110010..EXTTRIG_IN8
 *  0b110011..EXTTRIG_IN9
 *  0b110100..DMA0_TRIGOUT0
 *  0b110101..DMA0_TRIGOUT1
 *  0b110110..DMA0_TRIGOUT2
 */
#define INPUTMUX_ENC0_PHASEA_ENC0_PHASEA(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ENC0_PHASEA_ENC0_PHASEA_SHIFT)) & INPUTMUX_ENC0_PHASEA_ENC0_PHASEA_MASK)
/*! @} */

/*! @name ENC1_TRIG - ENC1 Trigger Input Connections */
/*! @{ */

#define INPUTMUX_ENC1_TRIG_TRIGIN_MASK           (0x3FU)
#define INPUTMUX_ENC1_TRIG_TRIGIN_SHIFT          (0U)
/*! TRIGIN - ENC1 input trigger
 *  0b000000..PIN_INT0
 *  0b000001..PIN_INT5
 *  0b000010..SCT_OUT4
 *  0b000011..SCT_OUT5
 *  0b000100..SCT_OUT7
 *  0b000101..T0_MAT3
 *  0b000110..T1_MAT3
 *  0b000111..T2_MAT3
 *  0b001000..T1_MAT1
 *  0b001001..T3_MAT1
 *  0b001010..ACMP0_OUT
 *  0b001011..ARM_TXEV
 *  0b001100..GPIOINT_BMATCH
 *  0b001101..ADC0_tcomp[0]
 *  0b001110..ADC0_tcomp[1]
 *  0b001111..ADC0_tcomp[2]
 *  0b010000..ADC0_tcomp[3]
 *  0b010001..ADC1_tcomp[0]
 *  0b010010..ADC1_tcomp[1]
 *  0b010011..ADC1_tcomp[2]
 *  0b010100..ADC1_tcomp[3]
 *  0b010101..HSCMP0_OUT
 *  0b010110..HSCMP1_OUT
 *  0b010111..HSCMP2_OUT
 *  0b011000..PWM1_SM0_MUX_TRIG0
 *  0b011001..PWM1_SM0_MUX_TRIG1
 *  0b011010..PWM1_SM1_MUX_TRIG0
 *  0b011011..PWM1_SM1_MUX_TRIG1
 *  0b011100..PWM1_SM2_MUX_TRIG0
 *  0b011101..PWM1_SM2_MUX_TRIG1
 *  0b011110..PWM1_SM3_MUX_TRIG0
 *  0b011111..PWM1_SM3_MUX_TRIG1
 *  0b100000..ENC0_CMP/POS_MATCH
 *  0b100001..ENC1_CMP/POS_MATCH
 *  0b100010..AOI0_OUT0
 *  0b100011..AOI0_OUT1
 *  0b100100..AOI0_OUT2
 *  0b100101..AOI0_OUT3
 *  0b100110..AOI1_OUT0
 *  0b100111..AOI1_OUT1
 *  0b101000..AOI1_OUT2
 *  0b101001..AOI1_OUT3
 *  0b101010..EXTTRIG_IN0
 *  0b101011..EXTTRIG_IN1
 *  0b101100..EXTTRIG_IN2
 *  0b101101..EXTTRIG_IN3
 *  0b101110..EXTTRIG_IN4
 *  0b101111..EXTTRIG_IN5
 *  0b110000..EXTTRIG_IN6
 *  0b110001..EXTTRIG_IN7
 *  0b110010..EXTTRIG_IN8
 *  0b110011..EXTTRIG_IN9
 *  0b110100..DMA0_TRIGOUT0
 *  0b110101..DMA0_TRIGOUT1
 *  0b110110..DMA0_TRIGOUT2
 */
#define INPUTMUX_ENC1_TRIG_TRIGIN(x)             (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ENC1_TRIG_TRIGIN_SHIFT)) & INPUTMUX_ENC1_TRIG_TRIGIN_MASK)
/*! @} */

/*! @name ENC1_HOME - ENC1 Input Connections */
/*! @{ */

#define INPUTMUX_ENC1_HOME_ENC1_HOME_MASK        (0x3FU)
#define INPUTMUX_ENC1_HOME_ENC1_HOME_SHIFT       (0U)
/*! ENC1_HOME - ENC1 input trigger
 *  0b000000..PIN_INT0
 *  0b000001..PIN_INT5
 *  0b000010..SCT_OUT4
 *  0b000011..SCT_OUT5
 *  0b000100..SCT_OUT7
 *  0b000101..T0_MAT3
 *  0b000110..T1_MAT3
 *  0b000111..T2_MAT3
 *  0b001000..T1_MAT1
 *  0b001001..T3_MAT1
 *  0b001010..ACMP0_OUT
 *  0b001011..ARM_TXEV
 *  0b001100..GPIOINT_BMATCH
 *  0b001101..ADC0_tcomp[0]
 *  0b001110..ADC0_tcomp[1]
 *  0b001111..ADC0_tcomp[2]
 *  0b010000..ADC0_tcomp[3]
 *  0b010001..ADC1_tcomp[0]
 *  0b010010..ADC1_tcomp[1]
 *  0b010011..ADC1_tcomp[2]
 *  0b010100..ADC1_tcomp[3]
 *  0b010101..HSCMP0_OUT
 *  0b010110..HSCMP1_OUT
 *  0b010111..HSCMP2_OUT
 *  0b011000..PWM1_SM0_MUX_TRIG0
 *  0b011001..PWM1_SM0_MUX_TRIG1
 *  0b011010..PWM1_SM1_MUX_TRIG0
 *  0b011011..PWM1_SM1_MUX_TRIG1
 *  0b011100..PWM1_SM2_MUX_TRIG0
 *  0b011101..PWM1_SM2_MUX_TRIG1
 *  0b011110..PWM1_SM3_MUX_TRIG0
 *  0b011111..PWM1_SM3_MUX_TRIG1
 *  0b100000..ENC0_CMP/POS_MATCH
 *  0b100001..ENC1_CMP/POS_MATCH
 *  0b100010..AOI0_OUT0
 *  0b100011..AOI0_OUT1
 *  0b100100..AOI0_OUT2
 *  0b100101..AOI0_OUT3
 *  0b100110..AOI1_OUT0
 *  0b100111..AOI1_OUT1
 *  0b101000..AOI1_OUT2
 *  0b101001..AOI1_OUT3
 *  0b101010..EXTTRIG_IN0
 *  0b101011..EXTTRIG_IN1
 *  0b101100..EXTTRIG_IN2
 *  0b101101..EXTTRIG_IN3
 *  0b101110..EXTTRIG_IN4
 *  0b101111..EXTTRIG_IN5
 *  0b110000..EXTTRIG_IN6
 *  0b110001..EXTTRIG_IN7
 *  0b110010..EXTTRIG_IN8
 *  0b110011..EXTTRIG_IN9
 *  0b110100..DMA0_TRIGOUT0
 *  0b110101..DMA0_TRIGOUT1
 *  0b110110..DMA0_TRIGOUT2
 */
#define INPUTMUX_ENC1_HOME_ENC1_HOME(x)          (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ENC1_HOME_ENC1_HOME_SHIFT)) & INPUTMUX_ENC1_HOME_ENC1_HOME_MASK)
/*! @} */

/*! @name ENC1_INDEX - ENC1 Input Connections */
/*! @{ */

#define INPUTMUX_ENC1_INDEX_ENC1_INDEX_MASK      (0x3FU)
#define INPUTMUX_ENC1_INDEX_ENC1_INDEX_SHIFT     (0U)
/*! ENC1_INDEX - ENC1 input trigger
 *  0b000000..PIN_INT0
 *  0b000001..PIN_INT5
 *  0b000010..SCT_OUT4
 *  0b000011..SCT_OUT5
 *  0b000100..SCT_OUT7
 *  0b000101..T0_MAT3
 *  0b000110..T1_MAT3
 *  0b000111..T2_MAT3
 *  0b001000..T1_MAT1
 *  0b001001..T3_MAT1
 *  0b001010..ACMP0_OUT
 *  0b001011..ARM_TXEV
 *  0b001100..GPIOINT_BMATCH
 *  0b001101..ADC0_tcomp[0]
 *  0b001110..ADC0_tcomp[1]
 *  0b001111..ADC0_tcomp[2]
 *  0b010000..ADC0_tcomp[3]
 *  0b010001..ADC1_tcomp[0]
 *  0b010010..ADC1_tcomp[1]
 *  0b010011..ADC1_tcomp[2]
 *  0b010100..ADC1_tcomp[3]
 *  0b010101..HSCMP0_OUT
 *  0b010110..HSCMP1_OUT
 *  0b010111..HSCMP2_OUT
 *  0b011000..PWM1_SM0_MUX_TRIG0
 *  0b011001..PWM1_SM0_MUX_TRIG1
 *  0b011010..PWM1_SM1_MUX_TRIG0
 *  0b011011..PWM1_SM1_MUX_TRIG1
 *  0b011100..PWM1_SM2_MUX_TRIG0
 *  0b011101..PWM1_SM2_MUX_TRIG1
 *  0b011110..PWM1_SM3_MUX_TRIG0
 *  0b011111..PWM1_SM3_MUX_TRIG1
 *  0b100000..ENC0_CMP/POS_MATCH
 *  0b100001..ENC1_CMP/POS_MATCH
 *  0b100010..AOI0_OUT0
 *  0b100011..AOI0_OUT1
 *  0b100100..AOI0_OUT2
 *  0b100101..AOI0_OUT3
 *  0b100110..AOI1_OUT0
 *  0b100111..AOI1_OUT1
 *  0b101000..AOI1_OUT2
 *  0b101001..AOI1_OUT3
 *  0b101010..EXTTRIG_IN0
 *  0b101011..EXTTRIG_IN1
 *  0b101100..EXTTRIG_IN2
 *  0b101101..EXTTRIG_IN3
 *  0b101110..EXTTRIG_IN4
 *  0b101111..EXTTRIG_IN5
 *  0b110000..EXTTRIG_IN6
 *  0b110001..EXTTRIG_IN7
 *  0b110010..EXTTRIG_IN8
 *  0b110011..EXTTRIG_IN9
 *  0b110100..DMA0_TRIGOUT0
 *  0b110101..DMA0_TRIGOUT1
 *  0b110110..DMA0_TRIGOUT2
 */
#define INPUTMUX_ENC1_INDEX_ENC1_INDEX(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ENC1_INDEX_ENC1_INDEX_SHIFT)) & INPUTMUX_ENC1_INDEX_ENC1_INDEX_MASK)
/*! @} */

/*! @name ENC1_PHASEB - ENC1 Input Connections */
/*! @{ */

#define INPUTMUX_ENC1_PHASEB_ENC1_PHASEB_MASK    (0x3FU)
#define INPUTMUX_ENC1_PHASEB_ENC1_PHASEB_SHIFT   (0U)
/*! ENC1_PHASEB - ENC1 input trigger
 *  0b000000..PIN_INT0
 *  0b000001..PIN_INT5
 *  0b000010..SCT_OUT4
 *  0b000011..SCT_OUT5
 *  0b000100..SCT_OUT7
 *  0b000101..T0_MAT3
 *  0b000110..T1_MAT3
 *  0b000111..T2_MAT3
 *  0b001000..T1_MAT1
 *  0b001001..T3_MAT1
 *  0b001010..ACMP0_OUT
 *  0b001011..ARM_TXEV
 *  0b001100..GPIOINT_BMATCH
 *  0b001101..ADC0_tcomp[0]
 *  0b001110..ADC0_tcomp[1]
 *  0b001111..ADC0_tcomp[2]
 *  0b010000..ADC0_tcomp[3]
 *  0b010001..ADC1_tcomp[0]
 *  0b010010..ADC1_tcomp[1]
 *  0b010011..ADC1_tcomp[2]
 *  0b010100..ADC1_tcomp[3]
 *  0b010101..HSCMP0_OUT
 *  0b010110..HSCMP1_OUT
 *  0b010111..HSCMP2_OUT
 *  0b011000..PWM1_SM0_MUX_TRIG0
 *  0b011001..PWM1_SM0_MUX_TRIG1
 *  0b011010..PWM1_SM1_MUX_TRIG0
 *  0b011011..PWM1_SM1_MUX_TRIG1
 *  0b011100..PWM1_SM2_MUX_TRIG0
 *  0b011101..PWM1_SM2_MUX_TRIG1
 *  0b011110..PWM1_SM3_MUX_TRIG0
 *  0b011111..PWM1_SM3_MUX_TRIG1
 *  0b100000..ENC0_CMP/POS_MATCH
 *  0b100001..ENC1_CMP/POS_MATCH
 *  0b100010..AOI0_OUT0
 *  0b100011..AOI0_OUT1
 *  0b100100..AOI0_OUT2
 *  0b100101..AOI0_OUT3
 *  0b100110..AOI1_OUT0
 *  0b100111..AOI1_OUT1
 *  0b101000..AOI1_OUT2
 *  0b101001..AOI1_OUT3
 *  0b101010..EXTTRIG_IN0
 *  0b101011..EXTTRIG_IN1
 *  0b101100..EXTTRIG_IN2
 *  0b101101..EXTTRIG_IN3
 *  0b101110..EXTTRIG_IN4
 *  0b101111..EXTTRIG_IN5
 *  0b110000..EXTTRIG_IN6
 *  0b110001..EXTTRIG_IN7
 *  0b110010..EXTTRIG_IN8
 *  0b110011..EXTTRIG_IN9
 *  0b110100..DMA0_TRIGOUT0
 *  0b110101..DMA0_TRIGOUT1
 *  0b110110..DMA0_TRIGOUT2
 */
#define INPUTMUX_ENC1_PHASEB_ENC1_PHASEB(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ENC1_PHASEB_ENC1_PHASEB_SHIFT)) & INPUTMUX_ENC1_PHASEB_ENC1_PHASEB_MASK)
/*! @} */

/*! @name ENC1_PHASEA - ENC1 Input Connections */
/*! @{ */

#define INPUTMUX_ENC1_PHASEA_ENC1_PHASEA_MASK    (0x3FU)
#define INPUTMUX_ENC1_PHASEA_ENC1_PHASEA_SHIFT   (0U)
/*! ENC1_PHASEA - ENC1 input trigger
 *  0b000000..PIN_INT0
 *  0b000001..PIN_INT5
 *  0b000010..SCT_OUT4
 *  0b000011..SCT_OUT5
 *  0b000100..SCT_OUT7
 *  0b000101..T0_MAT3
 *  0b000110..T1_MAT3
 *  0b000111..T2_MAT3
 *  0b001000..T1_MAT1
 *  0b001001..T3_MAT1
 *  0b001010..ACMP0_OUT
 *  0b001011..ARM_TXEV
 *  0b001100..GPIOINT_BMATCH
 *  0b001101..ADC0_tcomp[0]
 *  0b001110..ADC0_tcomp[1]
 *  0b001111..ADC0_tcomp[2]
 *  0b010000..ADC0_tcomp[3]
 *  0b010001..ADC1_tcomp[0]
 *  0b010010..ADC1_tcomp[1]
 *  0b010011..ADC1_tcomp[2]
 *  0b010100..ADC1_tcomp[3]
 *  0b010101..HSCMP0_OUT
 *  0b010110..HSCMP1_OUT
 *  0b010111..HSCMP2_OUT
 *  0b011000..PWM1_SM0_MUX_TRIG0
 *  0b011001..PWM1_SM0_MUX_TRIG1
 *  0b011010..PWM1_SM1_MUX_TRIG0
 *  0b011011..PWM1_SM1_MUX_TRIG1
 *  0b011100..PWM1_SM2_MUX_TRIG0
 *  0b011101..PWM1_SM2_MUX_TRIG1
 *  0b011110..PWM1_SM3_MUX_TRIG0
 *  0b011111..PWM1_SM3_MUX_TRIG1
 *  0b100000..ENC0_CMP/POS_MATCH
 *  0b100001..ENC1_CMP/POS_MATCH
 *  0b100010..AOI0_OUT0
 *  0b100011..AOI0_OUT1
 *  0b100100..AOI0_OUT2
 *  0b100101..AOI0_OUT3
 *  0b100110..AOI1_OUT0
 *  0b100111..AOI1_OUT1
 *  0b101000..AOI1_OUT2
 *  0b101001..AOI1_OUT3
 *  0b101010..EXTTRIG_IN0
 *  0b101011..EXTTRIG_IN1
 *  0b101100..EXTTRIG_IN2
 *  0b101101..EXTTRIG_IN3
 *  0b101110..EXTTRIG_IN4
 *  0b101111..EXTTRIG_IN5
 *  0b110000..EXTTRIG_IN6
 *  0b110001..EXTTRIG_IN7
 *  0b110010..EXTTRIG_IN8
 *  0b110011..EXTTRIG_IN9
 *  0b110100..DMA0_TRIGOUT0
 *  0b110101..DMA0_TRIGOUT1
 *  0b110110..DMA0_TRIGOUT2
 */
#define INPUTMUX_ENC1_PHASEA_ENC1_PHASEA(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ENC1_PHASEA_ENC1_PHASEA_SHIFT)) & INPUTMUX_ENC1_PHASEA_ENC1_PHASEA_MASK)
/*! @} */

/*! @name PWM0_EXTSYNCN_PWM0_EXTSYNC - PWM0 external synchronization */
/*! @{ */

#define INPUTMUX_PWM0_EXTSYNCN_PWM0_EXTSYNC_TRIGIN_MASK (0x3FU)
#define INPUTMUX_PWM0_EXTSYNCN_PWM0_EXTSYNC_TRIGIN_SHIFT (0U)
/*! TRIGIN - Trigger input connections for PWM0
 *  0b000000..PIN_INT0
 *  0b000001..PIN_INT5
 *  0b000010..SCT_OUT4
 *  0b000011..SCT_OUT5
 *  0b000100..SCT_OUT2
 *  0b000101..T0_MAT3
 *  0b000110..T1_MAT3
 *  0b000111..T2_MAT3
 *  0b001000..T2_MAT0
 *  0b001001..T4_MAT0
 *  0b001010..ACMP0_OUT
 *  0b001011..ARM_TXEV
 *  0b001100..GPIOINT_BMATCH
 *  0b001101..ADC0_tcomp[0]
 *  0b001110..ADC0_tcomp[1]
 *  0b001111..ADC0_tcomp[2]
 *  0b010000..ADC0_tcomp[3]
 *  0b010001..ADC1_tcomp[0]
 *  0b010010..ADC1_tcomp[1]
 *  0b010011..ADC1_tcomp[2]
 *  0b010100..ADC1_tcomp[3]
 *  0b010101..HSCMP0_OUT
 *  0b010110..HSCMP1_OUT
 *  0b010111..HSCMP2_OUT
 *  0b011000..PWM1_SM0_MUX_TRIG0
 *  0b011001..PWM1_SM0_MUX_TRIG1
 *  0b011010..PWM1_SM1_MUX_TRIG0
 *  0b011011..PWM1_SM1_MUX_TRIG1
 *  0b011100..PWM1_SM2_MUX_TRIG0
 *  0b011101..PWM1_SM2_MUX_TRIG1
 *  0b011110..PWM1_SM3_MUX_TRIG0
 *  0b011111..PWM1_SM3_MUX_TRIG1
 *  0b100000..ENC0_CMP/POS_MATCH
 *  0b100001..ENC1_CMP/POS_MATCH
 *  0b100010..AOI0_OUT0
 *  0b100011..AOI0_OUT1
 *  0b100100..AOI0_OUT2
 *  0b100101..AOI0_OUT3
 *  0b100110..AOI1_OUT0
 *  0b100111..AOI1_OUT1
 *  0b101000..AOI1_OUT2
 *  0b101001..AOI1_OUT3
 *  0b101010..EXTTRIG_IN0
 *  0b101011..EXTTRIG_IN1
 *  0b101100..EXTTRIG_IN2
 *  0b101101..EXTTRIG_IN3
 *  0b101110..EXTTRIG_IN4
 *  0b101111..EXTTRIG_IN5
 *  0b110000..EXTTRIG_IN6
 *  0b110001..EXTTRIG_IN7
 *  0b110010..EXTTRIG_IN8
 *  0b110011..EXTTRIG_IN9
 *  0b110100..DMA0_TRIGOUT0
 *  0b110101..DMA0_TRIGOUT1
 *  0b110110..DMA0_TRIGOUT2
 */
#define INPUTMUX_PWM0_EXTSYNCN_PWM0_EXTSYNC_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PWM0_EXTSYNCN_PWM0_EXTSYNC_TRIGIN_SHIFT)) & INPUTMUX_PWM0_EXTSYNCN_PWM0_EXTSYNC_TRIGIN_MASK)
/*! @} */

/* The count of INPUTMUX_PWM0_EXTSYNCN_PWM0_EXTSYNC */
#define INPUTMUX_PWM0_EXTSYNCN_PWM0_EXTSYNC_COUNT (4U)

/*! @name PWM0_EXTAN_PWM0_EXTA - PWM0 input trigger connections */
/*! @{ */

#define INPUTMUX_PWM0_EXTAN_PWM0_EXTA_TRIGIN_MASK (0x3FU)
#define INPUTMUX_PWM0_EXTAN_PWM0_EXTA_TRIGIN_SHIFT (0U)
/*! TRIGIN - Trigger input connections for PWM0
 *  0b000000..PIN_INT0
 *  0b000001..PIN_INT5
 *  0b000010..SCT_OUT4
 *  0b000011..SCT_OUT5
 *  0b000100..SCT_OUT2
 *  0b000101..T0_MAT3
 *  0b000110..T1_MAT3
 *  0b000111..T2_MAT3
 *  0b001000..T2_MAT0
 *  0b001001..T4_MAT0
 *  0b001010..ACMP0_OUT
 *  0b001011..ARM_TXEV
 *  0b001100..GPIOINT_BMATCH
 *  0b001101..ADC0_tcomp[0]
 *  0b001110..ADC0_tcomp[1]
 *  0b001111..ADC0_tcomp[2]
 *  0b010000..ADC0_tcomp[3]
 *  0b010001..ADC1_tcomp[0]
 *  0b010010..ADC1_tcomp[1]
 *  0b010011..ADC1_tcomp[2]
 *  0b010100..ADC1_tcomp[3]
 *  0b010101..HSCMP0_OUT
 *  0b010110..HSCMP1_OUT
 *  0b010111..HSCMP2_OUT
 *  0b011000..PWM1_SM0_MUX_TRIG0
 *  0b011001..PWM1_SM0_MUX_TRIG1
 *  0b011010..PWM1_SM1_MUX_TRIG0
 *  0b011011..PWM1_SM1_MUX_TRIG1
 *  0b011100..PWM1_SM2_MUX_TRIG0
 *  0b011101..PWM1_SM2_MUX_TRIG1
 *  0b011110..PWM1_SM3_MUX_TRIG0
 *  0b011111..PWM1_SM3_MUX_TRIG1
 *  0b100000..ENC0_CMP/POS_MATCH
 *  0b100001..ENC1_CMP/POS_MATCH
 *  0b100010..AOI0_OUT0
 *  0b100011..AOI0_OUT1
 *  0b100100..AOI0_OUT2
 *  0b100101..AOI0_OUT3
 *  0b100110..AOI1_OUT0
 *  0b100111..AOI1_OUT1
 *  0b101000..AOI1_OUT2
 *  0b101001..AOI1_OUT3
 *  0b101010..EXTTRIG_IN0
 *  0b101011..EXTTRIG_IN1
 *  0b101100..EXTTRIG_IN2
 *  0b101101..EXTTRIG_IN3
 *  0b101110..EXTTRIG_IN4
 *  0b101111..EXTTRIG_IN5
 *  0b110000..EXTTRIG_IN6
 *  0b110001..EXTTRIG_IN7
 *  0b110010..EXTTRIG_IN8
 *  0b110011..EXTTRIG_IN9
 *  0b110100..DMA0_TRIGOUT0
 *  0b110101..DMA0_TRIGOUT1
 *  0b110110..DMA0_TRIGOUT2
 */
#define INPUTMUX_PWM0_EXTAN_PWM0_EXTA_TRIGIN(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PWM0_EXTAN_PWM0_EXTA_TRIGIN_SHIFT)) & INPUTMUX_PWM0_EXTAN_PWM0_EXTA_TRIGIN_MASK)
/*! @} */

/* The count of INPUTMUX_PWM0_EXTAN_PWM0_EXTA */
#define INPUTMUX_PWM0_EXTAN_PWM0_EXTA_COUNT      (4U)

/*! @name PWM0_EXTFORCE - PWM0 external force trigger connections */
/*! @{ */

#define INPUTMUX_PWM0_EXTFORCE_TRIGIN_MASK       (0x3FU)
#define INPUTMUX_PWM0_EXTFORCE_TRIGIN_SHIFT      (0U)
/*! TRIGIN - Trigger input connections for PWM0
 *  0b000000..PIN_INT0
 *  0b000001..PIN_INT5
 *  0b000010..SCT_OUT4
 *  0b000011..SCT_OUT5
 *  0b000100..SCT_OUT2
 *  0b000101..T0_MAT3
 *  0b000110..T1_MAT3
 *  0b000111..T2_MAT3
 *  0b001000..T2_MAT0
 *  0b001001..T4_MAT0
 *  0b001010..ACMP0_OUT
 *  0b001011..ARM_TXEV
 *  0b001100..GPIOINT_BMATCH
 *  0b001101..ADC0_tcomp[0]
 *  0b001110..ADC0_tcomp[1]
 *  0b001111..ADC0_tcomp[2]
 *  0b010000..ADC0_tcomp[3]
 *  0b010001..ADC1_tcomp[0]
 *  0b010010..ADC1_tcomp[1]
 *  0b010011..ADC1_tcomp[2]
 *  0b010100..ADC1_tcomp[3]
 *  0b010101..HSCMP0_OUT
 *  0b010110..HSCMP1_OUT
 *  0b010111..HSCMP2_OUT
 *  0b011000..PWM1_SM0_MUX_TRIG0
 *  0b011001..PWM1_SM0_MUX_TRIG1
 *  0b011010..PWM1_SM1_MUX_TRIG0
 *  0b011011..PWM1_SM1_MUX_TRIG1
 *  0b011100..PWM1_SM2_MUX_TRIG0
 *  0b011101..PWM1_SM2_MUX_TRIG1
 *  0b011110..PWM1_SM3_MUX_TRIG0
 *  0b011111..PWM1_SM3_MUX_TRIG1
 *  0b100000..ENC0_CMP/POS_MATCH
 *  0b100001..ENC1_CMP/POS_MATCH
 *  0b100010..AOI0_OUT0
 *  0b100011..AOI0_OUT1
 *  0b100100..AOI0_OUT2
 *  0b100101..AOI0_OUT3
 *  0b100110..AOI1_OUT0
 *  0b100111..AOI1_OUT1
 *  0b101000..AOI1_OUT2
 *  0b101001..AOI1_OUT3
 *  0b101010..EXTTRIG_IN0
 *  0b101011..EXTTRIG_IN1
 *  0b101100..EXTTRIG_IN2
 *  0b101101..EXTTRIG_IN3
 *  0b101110..EXTTRIG_IN4
 *  0b101111..EXTTRIG_IN5
 *  0b110000..EXTTRIG_IN6
 *  0b110001..EXTTRIG_IN7
 *  0b110010..EXTTRIG_IN8
 *  0b110011..EXTTRIG_IN9
 *  0b110100..DMA0_TRIGOUT0
 *  0b110101..DMA0_TRIGOUT1
 *  0b110110..DMA0_TRIGOUT2
 */
#define INPUTMUX_PWM0_EXTFORCE_TRIGIN(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PWM0_EXTFORCE_TRIGIN_SHIFT)) & INPUTMUX_PWM0_EXTFORCE_TRIGIN_MASK)
/*! @} */

/*! @name PWM0_FAULTN_PWM0_FAULT - PWM0 fault input trigger connections */
/*! @{ */

#define INPUTMUX_PWM0_FAULTN_PWM0_FAULT_TRIGIN_MASK (0x3FU)
#define INPUTMUX_PWM0_FAULTN_PWM0_FAULT_TRIGIN_SHIFT (0U)
/*! TRIGIN - Trigger input connections for PWM0
 *  0b000000..PIN_INT0
 *  0b000001..PIN_INT5
 *  0b000010..SCT_OUT4
 *  0b000011..SCT_OUT5
 *  0b000100..SCT_OUT2
 *  0b000101..T0_MAT3
 *  0b000110..T1_MAT3
 *  0b000111..T2_MAT3
 *  0b001000..T2_MAT0
 *  0b001001..T4_MAT0
 *  0b001010..ACMP0_OUT
 *  0b001011..ARM_TXEV
 *  0b001100..GPIOINT_BMATCH
 *  0b001101..ADC0_tcomp[0]
 *  0b001110..ADC0_tcomp[1]
 *  0b001111..ADC0_tcomp[2]
 *  0b010000..ADC0_tcomp[3]
 *  0b010001..ADC1_tcomp[0]
 *  0b010010..ADC1_tcomp[1]
 *  0b010011..ADC1_tcomp[2]
 *  0b010100..ADC1_tcomp[3]
 *  0b010101..HSCMP0_OUT
 *  0b010110..HSCMP1_OUT
 *  0b010111..HSCMP2_OUT
 *  0b011000..PWM1_SM0_MUX_TRIG0
 *  0b011001..PWM1_SM0_MUX_TRIG1
 *  0b011010..PWM1_SM1_MUX_TRIG0
 *  0b011011..PWM1_SM1_MUX_TRIG1
 *  0b011100..PWM1_SM2_MUX_TRIG0
 *  0b011101..PWM1_SM2_MUX_TRIG1
 *  0b011110..PWM1_SM3_MUX_TRIG0
 *  0b011111..PWM1_SM3_MUX_TRIG1
 *  0b100000..ENC0_CMP/POS_MATCH
 *  0b100001..ENC1_CMP/POS_MATCH
 *  0b100010..AOI0_OUT0
 *  0b100011..AOI0_OUT1
 *  0b100100..AOI0_OUT2
 *  0b100101..AOI0_OUT3
 *  0b100110..AOI1_OUT0
 *  0b100111..AOI1_OUT1
 *  0b101000..AOI1_OUT2
 *  0b101001..AOI1_OUT3
 *  0b101010..EXTTRIG_IN0
 *  0b101011..EXTTRIG_IN1
 *  0b101100..EXTTRIG_IN2
 *  0b101101..EXTTRIG_IN3
 *  0b101110..EXTTRIG_IN4
 *  0b101111..EXTTRIG_IN5
 *  0b110000..EXTTRIG_IN6
 *  0b110001..EXTTRIG_IN7
 *  0b110010..EXTTRIG_IN8
 *  0b110011..EXTTRIG_IN9
 *  0b110100..DMA0_TRIGOUT0
 *  0b110101..DMA0_TRIGOUT1
 *  0b110110..DMA0_TRIGOUT2
 */
#define INPUTMUX_PWM0_FAULTN_PWM0_FAULT_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PWM0_FAULTN_PWM0_FAULT_TRIGIN_SHIFT)) & INPUTMUX_PWM0_FAULTN_PWM0_FAULT_TRIGIN_MASK)
/*! @} */

/* The count of INPUTMUX_PWM0_FAULTN_PWM0_FAULT */
#define INPUTMUX_PWM0_FAULTN_PWM0_FAULT_COUNT    (4U)

/*! @name PWM1_EXTSYNCN_PWM1_EXTSYNC - PWM1 external synchronization */
/*! @{ */

#define INPUTMUX_PWM1_EXTSYNCN_PWM1_EXTSYNC_TRIGIN_MASK (0x3FU)
#define INPUTMUX_PWM1_EXTSYNCN_PWM1_EXTSYNC_TRIGIN_SHIFT (0U)
/*! TRIGIN - Trigger input connections for PWM1
 *  0b000000..PIN_INT0
 *  0b000001..PIN_INT2
 *  0b000010..SCT_OUT4
 *  0b000011..SCT_OUT5
 *  0b000100..SCT_OUT3
 *  0b000101..T0_MAT3
 *  0b000110..T1_MAT3
 *  0b000111..T2_MAT3
 *  0b001000..T2_MAT1
 *  0b001001..T4_MAT1
 *  0b001010..ACMP0_OUT
 *  0b001011..ARM_TXEV
 *  0b001100..GPIOINT_BMATCH
 *  0b001101..ADC0_tcomp[0]
 *  0b001110..ADC0_tcomp[1]
 *  0b001111..ADC0_tcomp[2]
 *  0b010000..ADC0_tcomp[3]
 *  0b010001..ADC1_tcomp[0]
 *  0b010010..ADC1_tcomp[1]
 *  0b010011..ADC1_tcomp[2]
 *  0b010100..ADC1_tcomp[3]
 *  0b010101..HSCMP0_OUT
 *  0b010110..HSCMP1_OUT
 *  0b010111..HSCMP2_OUT
 *  0b011000..PWM0_SM0_MUX_TRIG0
 *  0b011001..PWM0_SM0_MUX_TRIG1
 *  0b011010..PWM0_SM1_MUX_TRIG0
 *  0b011011..PWM0_SM1_MUX_TRIG1
 *  0b011100..PWM0_SM2_MUX_TRIG0
 *  0b011101..PWM0_SM2_MUX_TRIG1
 *  0b011110..PWM0_SM3_MUX_TRIG0
 *  0b011111..PWM0_SM3_MUX_TRIG1
 *  0b100000..ENC0_CMP/POS_MATCH
 *  0b100001..ENC1_CMP/POS_MATCH
 *  0b100010..AOI0_OUT0
 *  0b100011..AOI0_OUT1
 *  0b100100..AOI0_OUT2
 *  0b100101..AOI0_OUT3
 *  0b100110..AOI1_OUT0
 *  0b100111..AOI1_OUT1
 *  0b101000..AOI1_OUT2
 *  0b101001..AOI1_OUT3
 *  0b101010..EXTTRIG_IN0
 *  0b101011..EXTTRIG_IN1
 *  0b101100..EXTTRIG_IN2
 *  0b101101..EXTTRIG_IN3
 *  0b101110..EXTTRIG_IN4
 *  0b101111..EXTTRIG_IN5
 *  0b110000..EXTTRIG_IN6
 *  0b110001..EXTTRIG_IN7
 *  0b110010..EXTTRIG_IN8
 *  0b110011..EXTTRIG_IN9
 *  0b110100..DMA0_TRIGOUT0
 *  0b110101..DMA0_TRIGOUT1
 *  0b110110..DMA0_TRIGOUT2
 */
#define INPUTMUX_PWM1_EXTSYNCN_PWM1_EXTSYNC_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PWM1_EXTSYNCN_PWM1_EXTSYNC_TRIGIN_SHIFT)) & INPUTMUX_PWM1_EXTSYNCN_PWM1_EXTSYNC_TRIGIN_MASK)
/*! @} */

/* The count of INPUTMUX_PWM1_EXTSYNCN_PWM1_EXTSYNC */
#define INPUTMUX_PWM1_EXTSYNCN_PWM1_EXTSYNC_COUNT (4U)

/*! @name PWM1_EXTAN_PWM1_EXTA - PWM1 input trigger connections */
/*! @{ */

#define INPUTMUX_PWM1_EXTAN_PWM1_EXTA_TRIGIN_MASK (0x3FU)
#define INPUTMUX_PWM1_EXTAN_PWM1_EXTA_TRIGIN_SHIFT (0U)
/*! TRIGIN - Trigger input connections for PWM1
 *  0b000000..PIN_INT0
 *  0b000001..PIN_INT2
 *  0b000010..SCT_OUT4
 *  0b000011..SCT_OUT5
 *  0b000100..SCT_OUT3
 *  0b000101..T0_MAT3
 *  0b000110..T1_MAT3
 *  0b000111..T2_MAT3
 *  0b001000..T2_MAT1
 *  0b001001..T4_MAT1
 *  0b001010..ACMP0_OUT
 *  0b001011..ARM_TXEV
 *  0b001100..GPIOINT_BMATCH
 *  0b001101..ADC0_tcomp[0]
 *  0b001110..ADC0_tcomp[1]
 *  0b001111..ADC0_tcomp[2]
 *  0b010000..ADC0_tcomp[3]
 *  0b010001..ADC1_tcomp[0]
 *  0b010010..ADC1_tcomp[1]
 *  0b010011..ADC1_tcomp[2]
 *  0b010100..ADC1_tcomp[3]
 *  0b010101..HSCMP0_OUT
 *  0b010110..HSCMP1_OUT
 *  0b010111..HSCMP2_OUT
 *  0b011000..PWM0_SM0_MUX_TRIG0
 *  0b011001..PWM0_SM0_MUX_TRIG1
 *  0b011010..PWM0_SM1_MUX_TRIG0
 *  0b011011..PWM0_SM1_MUX_TRIG1
 *  0b011100..PWM0_SM2_MUX_TRIG0
 *  0b011101..PWM0_SM2_MUX_TRIG1
 *  0b011110..PWM0_SM3_MUX_TRIG0
 *  0b011111..PWM0_SM3_MUX_TRIG1
 *  0b100000..ENC0_CMP/POS_MATCH
 *  0b100001..ENC1_CMP/POS_MATCH
 *  0b100010..AOI0_OUT0
 *  0b100011..AOI0_OUT1
 *  0b100100..AOI0_OUT2
 *  0b100101..AOI0_OUT3
 *  0b100110..AOI1_OUT0
 *  0b100111..AOI1_OUT1
 *  0b101000..AOI1_OUT2
 *  0b101001..AOI1_OUT3
 *  0b101010..EXTTRIG_IN0
 *  0b101011..EXTTRIG_IN1
 *  0b101100..EXTTRIG_IN2
 *  0b101101..EXTTRIG_IN3
 *  0b101110..EXTTRIG_IN4
 *  0b101111..EXTTRIG_IN5
 *  0b110000..EXTTRIG_IN6
 *  0b110001..EXTTRIG_IN7
 *  0b110010..EXTTRIG_IN8
 *  0b110011..EXTTRIG_IN9
 *  0b110100..DMA0_TRIGOUT0
 *  0b110101..DMA0_TRIGOUT1
 *  0b110110..DMA0_TRIGOUT2
 */
#define INPUTMUX_PWM1_EXTAN_PWM1_EXTA_TRIGIN(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PWM1_EXTAN_PWM1_EXTA_TRIGIN_SHIFT)) & INPUTMUX_PWM1_EXTAN_PWM1_EXTA_TRIGIN_MASK)
/*! @} */

/* The count of INPUTMUX_PWM1_EXTAN_PWM1_EXTA */
#define INPUTMUX_PWM1_EXTAN_PWM1_EXTA_COUNT      (4U)

/*! @name PWM1_EXTFORCE - PWM1 external force trigger connections */
/*! @{ */

#define INPUTMUX_PWM1_EXTFORCE_TRIGIN_MASK       (0x3FU)
#define INPUTMUX_PWM1_EXTFORCE_TRIGIN_SHIFT      (0U)
/*! TRIGIN - Trigger input connections for PWM1
 *  0b000000..PIN_INT0
 *  0b000001..PIN_INT2
 *  0b000010..SCT_OUT4
 *  0b000011..SCT_OUT5
 *  0b000100..SCT_OUT3
 *  0b000101..T0_MAT3
 *  0b000110..T1_MAT3
 *  0b000111..T2_MAT3
 *  0b001000..T2_MAT1
 *  0b001001..T4_MAT1
 *  0b001010..ACMP0_OUT
 *  0b001011..ARM_TXEV
 *  0b001100..GPIOINT_BMATCH
 *  0b001101..ADC0_tcomp[0]
 *  0b001110..ADC0_tcomp[1]
 *  0b001111..ADC0_tcomp[2]
 *  0b010000..ADC0_tcomp[3]
 *  0b010001..ADC1_tcomp[0]
 *  0b010010..ADC1_tcomp[1]
 *  0b010011..ADC1_tcomp[2]
 *  0b010100..ADC1_tcomp[3]
 *  0b010101..HSCMP0_OUT
 *  0b010110..HSCMP1_OUT
 *  0b010111..HSCMP2_OUT
 *  0b011000..PWM0_SM0_MUX_TRIG0
 *  0b011001..PWM0_SM0_MUX_TRIG1
 *  0b011010..PWM0_SM1_MUX_TRIG0
 *  0b011011..PWM0_SM1_MUX_TRIG1
 *  0b011100..PWM0_SM2_MUX_TRIG0
 *  0b011101..PWM0_SM2_MUX_TRIG1
 *  0b011110..PWM0_SM3_MUX_TRIG0
 *  0b011111..PWM0_SM3_MUX_TRIG1
 *  0b100000..ENC0_CMP/POS_MATCH
 *  0b100001..ENC1_CMP/POS_MATCH
 *  0b100010..AOI0_OUT0
 *  0b100011..AOI0_OUT1
 *  0b100100..AOI0_OUT2
 *  0b100101..AOI0_OUT3
 *  0b100110..AOI1_OUT0
 *  0b100111..AOI1_OUT1
 *  0b101000..AOI1_OUT2
 *  0b101001..AOI1_OUT3
 *  0b101010..EXTTRIG_IN0
 *  0b101011..EXTTRIG_IN1
 *  0b101100..EXTTRIG_IN2
 *  0b101101..EXTTRIG_IN3
 *  0b101110..EXTTRIG_IN4
 *  0b101111..EXTTRIG_IN5
 *  0b110000..EXTTRIG_IN6
 *  0b110001..EXTTRIG_IN7
 *  0b110010..EXTTRIG_IN8
 *  0b110011..EXTTRIG_IN9
 *  0b110100..DMA0_TRIGOUT0
 *  0b110101..DMA0_TRIGOUT1
 *  0b110110..DMA0_TRIGOUT2
 */
#define INPUTMUX_PWM1_EXTFORCE_TRIGIN(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PWM1_EXTFORCE_TRIGIN_SHIFT)) & INPUTMUX_PWM1_EXTFORCE_TRIGIN_MASK)
/*! @} */

/*! @name PWM1_FAULTN_PWM1_FAULT - PWM1 fault input trigger connections */
/*! @{ */

#define INPUTMUX_PWM1_FAULTN_PWM1_FAULT_TRIGIN_MASK (0x3FU)
#define INPUTMUX_PWM1_FAULTN_PWM1_FAULT_TRIGIN_SHIFT (0U)
/*! TRIGIN - Trigger input connections for PWM1
 *  0b000000..PIN_INT0
 *  0b000001..PIN_INT2
 *  0b000010..SCT_OUT4
 *  0b000011..SCT_OUT5
 *  0b000100..SCT_OUT3
 *  0b000101..T0_MAT3
 *  0b000110..T1_MAT3
 *  0b000111..T2_MAT3
 *  0b001000..T2_MAT1
 *  0b001001..T4_MAT1
 *  0b001010..ACMP0_OUT
 *  0b001011..ARM_TXEV
 *  0b001100..GPIOINT_BMATCH
 *  0b001101..ADC0_tcomp[0]
 *  0b001110..ADC0_tcomp[1]
 *  0b001111..ADC0_tcomp[2]
 *  0b010000..ADC0_tcomp[3]
 *  0b010001..ADC1_tcomp[0]
 *  0b010010..ADC1_tcomp[1]
 *  0b010011..ADC1_tcomp[2]
 *  0b010100..ADC1_tcomp[3]
 *  0b010101..HSCMP0_OUT
 *  0b010110..HSCMP1_OUT
 *  0b010111..HSCMP2_OUT
 *  0b011000..PWM0_SM0_MUX_TRIG0
 *  0b011001..PWM0_SM0_MUX_TRIG1
 *  0b011010..PWM0_SM1_MUX_TRIG0
 *  0b011011..PWM0_SM1_MUX_TRIG1
 *  0b011100..PWM0_SM2_MUX_TRIG0
 *  0b011101..PWM0_SM2_MUX_TRIG1
 *  0b011110..PWM0_SM3_MUX_TRIG0
 *  0b011111..PWM0_SM3_MUX_TRIG1
 *  0b100000..ENC0_CMP/POS_MATCH
 *  0b100001..ENC1_CMP/POS_MATCH
 *  0b100010..AOI0_OUT0
 *  0b100011..AOI0_OUT1
 *  0b100100..AOI0_OUT2
 *  0b100101..AOI0_OUT3
 *  0b100110..AOI1_OUT0
 *  0b100111..AOI1_OUT1
 *  0b101000..AOI1_OUT2
 *  0b101001..AOI1_OUT3
 *  0b101010..EXTTRIG_IN0
 *  0b101011..EXTTRIG_IN1
 *  0b101100..EXTTRIG_IN2
 *  0b101101..EXTTRIG_IN3
 *  0b101110..EXTTRIG_IN4
 *  0b101111..EXTTRIG_IN5
 *  0b110000..EXTTRIG_IN6
 *  0b110001..EXTTRIG_IN7
 *  0b110010..EXTTRIG_IN8
 *  0b110011..EXTTRIG_IN9
 *  0b110100..DMA0_TRIGOUT0
 *  0b110101..DMA0_TRIGOUT1
 *  0b110110..DMA0_TRIGOUT2
 */
#define INPUTMUX_PWM1_FAULTN_PWM1_FAULT_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PWM1_FAULTN_PWM1_FAULT_TRIGIN_SHIFT)) & INPUTMUX_PWM1_FAULTN_PWM1_FAULT_TRIGIN_MASK)
/*! @} */

/* The count of INPUTMUX_PWM1_FAULTN_PWM1_FAULT */
#define INPUTMUX_PWM1_FAULTN_PWM1_FAULT_COUNT    (4U)

/*! @name PWM0_EXTCLK - PWM0 external clock trigger connections */
/*! @{ */

#define INPUTMUX_PWM0_EXTCLK_TRIGIN_MASK         (0x3FU)
#define INPUTMUX_PWM0_EXTCLK_TRIGIN_SHIFT        (0U)
/*! TRIGIN - Trigger input connections for PWM0
 *  0b000000..PIN_INT0
 *  0b000001..PIN_INT5
 *  0b000010..SCT_OUT4
 *  0b000011..SCT_OUT5
 *  0b000100..SCT_OUT2
 *  0b000101..T0_MAT3
 *  0b000110..T1_MAT3
 *  0b000111..T2_MAT3
 *  0b001000..T2_MAT0
 *  0b001001..T4_MAT0
 *  0b001010..ACMP0_OUT
 *  0b001011..ARM_TXEV
 *  0b001100..GPIOINT_BMATCH
 *  0b001101..ADC0_tcomp[0]
 *  0b001110..ADC0_tcomp[1]
 *  0b001111..ADC0_tcomp[2]
 *  0b010000..ADC0_tcomp[3]
 *  0b010001..ADC1_tcomp[0]
 *  0b010010..ADC1_tcomp[1]
 *  0b010011..ADC1_tcomp[2]
 *  0b010100..ADC1_tcomp[3]
 *  0b010101..HSCMP0_OUT
 *  0b010110..HSCMP1_OUT
 *  0b010111..HSCMP2_OUT
 *  0b011000..PWM1_SM0_MUX_TRIG0
 *  0b011001..PWM1_SM0_MUX_TRIG1
 *  0b011010..PWM1_SM1_MUX_TRIG0
 *  0b011011..PWM1_SM1_MUX_TRIG1
 *  0b011100..PWM1_SM2_MUX_TRIG0
 *  0b011101..PWM1_SM2_MUX_TRIG1
 *  0b011110..PWM1_SM3_MUX_TRIG0
 *  0b011111..PWM1_SM3_MUX_TRIG1
 *  0b100000..ENC0_CMP/POS_MATCH
 *  0b100001..ENC1_CMP/POS_MATCH
 *  0b100010..AOI0_OUT0
 *  0b100011..AOI0_OUT1
 *  0b100100..AOI0_OUT2
 *  0b100101..AOI0_OUT3
 *  0b100110..AOI1_OUT0
 *  0b100111..AOI1_OUT1
 *  0b101000..AOI1_OUT2
 *  0b101001..AOI1_OUT3
 *  0b101010..EXTTRIG_IN0
 *  0b101011..EXTTRIG_IN1
 *  0b101100..EXTTRIG_IN2
 *  0b101101..EXTTRIG_IN3
 *  0b101110..EXTTRIG_IN4
 *  0b101111..EXTTRIG_IN5
 *  0b110000..EXTTRIG_IN6
 *  0b110001..EXTTRIG_IN7
 *  0b110010..EXTTRIG_IN8
 *  0b110011..EXTTRIG_IN9
 *  0b110100..DMA0_TRIGOUT0
 *  0b110101..DMA0_TRIGOUT1
 *  0b110110..DMA0_TRIGOUT2
 */
#define INPUTMUX_PWM0_EXTCLK_TRIGIN(x)           (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PWM0_EXTCLK_TRIGIN_SHIFT)) & INPUTMUX_PWM0_EXTCLK_TRIGIN_MASK)
/*! @} */

/*! @name PWM1_EXTCLK - PWM1 external clock trigger connections */
/*! @{ */

#define INPUTMUX_PWM1_EXTCLK_TRIGIN_MASK         (0x3FU)
#define INPUTMUX_PWM1_EXTCLK_TRIGIN_SHIFT        (0U)
/*! TRIGIN - Trigger input connections for PWM1
 *  0b000000..PIN_INT0
 *  0b000001..PIN_INT2
 *  0b000010..SCT_OUT4
 *  0b000011..SCT_OUT5
 *  0b000100..SCT_OUT3
 *  0b000101..T0_MAT3
 *  0b000110..T1_MAT3
 *  0b000111..T2_MAT3
 *  0b001000..T2_MAT1
 *  0b001001..T4_MAT1
 *  0b001010..ACMP0_OUT
 *  0b001011..ARM_TXEV
 *  0b001100..GPIOINT_BMATCH
 *  0b001101..ADC0_tcomp[0]
 *  0b001110..ADC0_tcomp[1]
 *  0b001111..ADC0_tcomp[2]
 *  0b010000..ADC0_tcomp[3]
 *  0b010001..ADC1_tcomp[0]
 *  0b010010..ADC1_tcomp[1]
 *  0b010011..ADC1_tcomp[2]
 *  0b010100..ADC1_tcomp[3]
 *  0b010101..HSCMP0_OUT
 *  0b010110..HSCMP1_OUT
 *  0b010111..HSCMP2_OUT
 *  0b011000..PWM0_SM0_MUX_TRIG0
 *  0b011001..PWM0_SM0_MUX_TRIG1
 *  0b011010..PWM0_SM1_MUX_TRIG0
 *  0b011011..PWM0_SM1_MUX_TRIG1
 *  0b011100..PWM0_SM2_MUX_TRIG0
 *  0b011101..PWM0_SM2_MUX_TRIG1
 *  0b011110..PWM0_SM3_MUX_TRIG0
 *  0b011111..PWM0_SM3_MUX_TRIG1
 *  0b100000..ENC0_CMP/POS_MATCH
 *  0b100001..ENC1_CMP/POS_MATCH
 *  0b100010..AOI0_OUT0
 *  0b100011..AOI0_OUT1
 *  0b100100..AOI0_OUT2
 *  0b100101..AOI0_OUT3
 *  0b100110..AOI1_OUT0
 *  0b100111..AOI1_OUT1
 *  0b101000..AOI1_OUT2
 *  0b101001..AOI1_OUT3
 *  0b101010..EXTTRIG_IN0
 *  0b101011..EXTTRIG_IN1
 *  0b101100..EXTTRIG_IN2
 *  0b101101..EXTTRIG_IN3
 *  0b101110..EXTTRIG_IN4
 *  0b101111..EXTTRIG_IN5
 *  0b110000..EXTTRIG_IN6
 *  0b110001..EXTTRIG_IN7
 *  0b110010..EXTTRIG_IN8
 *  0b110011..EXTTRIG_IN9
 *  0b110100..DMA0_TRIGOUT0
 *  0b110101..DMA0_TRIGOUT1
 *  0b110110..DMA0_TRIGOUT2
 */
#define INPUTMUX_PWM1_EXTCLK_TRIGIN(x)           (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PWM1_EXTCLK_TRIGIN_SHIFT)) & INPUTMUX_PWM1_EXTCLK_TRIGIN_MASK)
/*! @} */

/*! @name AOI0_IN - AOI0 trigger inputs */
/*! @{ */

#define INPUTMUX_AOI0_IN_IN_MASK                 (0x3FU)
#define INPUTMUX_AOI0_IN_IN_SHIFT                (0U)
/*! IN - Input trigger assignments
 *  0b000000..PIN_INT0
 *  0b000001..PIN_INT1
 *  0b000010..SCT_OUT0
 *  0b000011..SCT_OUT1
 *  0b000100..SCT_OUT2
 *  0b000101..SCT_OUT3
 *  0b000110..T0_MAT3
 *  0b000111..T1_MAT3
 *  0b001000..T2_MAT3
 *  0b001001..T2_MAT2
 *  0b001010..T3_MAT2
 *  0b001011..T4_MAT2
 *  0b001100..ACMP0_OUT
 *  0b001101..GPIOINT_BMATCH
 *  0b001110..ADC0_IRQ
 *  0b001111..ADC1_IRQ
 *  0b010000..ADC0_tcomp[0]
 *  0b010001..ADC0_tcomp[1]
 *  0b010010..ADC0_tcomp[2]
 *  0b010011..ADC0_tcomp[3]
 *  0b010100..ADC1_tcomp[0]
 *  0b010101..ADC1_tcomp[1]
 *  0b010110..ADC1_tcomp[2]
 *  0b010111..ADC1_tcomp[3]
 *  0b011000..HSCMP0_OUT
 *  0b011001..HSCMP1_OUT
 *  0b011010..HSCMP2_OUT
 *  0b011011..PWM0_SM0_MUX_TRIG0
 *  0b011100..PWM0_SM0_MUX_TRIG1
 *  0b011101..PWM0_SM1_MUX_TRIG0
 *  0b011110..PWM0_SM1_MUX_TRIG1
 *  0b011111..PWM0_SM2_MUX_TRIG0
 *  0b100000..PWM0_SM2_MUX_TRIG1
 *  0b100001..PWM0_SM3_MUX_TRIG0
 *  0b100010..PWM0_SM3_MUX_TRIG1
 *  0b100011..PWM1_SM0_MUX_TRIG0
 *  0b100100..PWM1_SM0_MUX_TRIG1
 *  0b100101..PWM1_SM1_MUX_TRIG0
 *  0b100110..PWM1_SM1_MUX_TRIG1
 *  0b100111..PWM1_SM2_MUX_TRIG0
 *  0b101000..PWM1_SM2_MUX_TRIG1
 *  0b101001..PWM1_SM3_MUX_TRIG0
 *  0b101010..PWM1_SM3_MUX_TRIG1
 *  0b101011..ENC0_CMP/POS_MATCH
 *  0b101100..ENC1_CMP/POS_MATCH
 *  0b101101..EXTTRIG_IN0
 *  0b101110..EXTTRIG_IN1
 *  0b101111..EXTTRIG_IN2
 *  0b110000..EXTTRIG_IN3
 *  0b110001..Reserved
 *  0b110010..Reserved
 *  0b110011..DMA0_TRIGOUT0
 *  0b110100..DMA0_TRIGOUT1
 *  0b110101..DMA0_TRIGOUT2
 *  0b110110..DMA0_TRIGOUT3
 *  0b110111..DMA0_TRIGOUT4
 *  0b111000..DMA0_TRIGOUT5
 *  0b111001..DMA0_TRIGOUT6
 *  0b111010..DMA1_TRIGOUT0
 *  0b111011..DMA1_TRIGOUT1
 *  0b111100..DMA1_TRIGOUT2
 */
#define INPUTMUX_AOI0_IN_IN(x)                   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_AOI0_IN_IN_SHIFT)) & INPUTMUX_AOI0_IN_IN_MASK)
/*! @} */

/* The count of INPUTMUX_AOI0_IN */
#define INPUTMUX_AOI0_INPUTTRIGGER0              (16U)

/*! @name AOI1_IN - AOI1 trigger inputs */
/*! @{ */

#define INPUTMUX_AOI1_IN_IN_MASK                 (0x3FU)
#define INPUTMUX_AOI1_IN_IN_SHIFT                (0U)
/*! IN - Input trigger assignments
 *  0b000000..PIN_INT0
 *  0b000001..PIN_INT1
 *  0b000010..SCT_OUT0
 *  0b000011..SCT_OUT1
 *  0b000100..SCT_OUT2
 *  0b000101..SCT_OUT3
 *  0b000110..T0_MAT3
 *  0b000111..T1_MAT3
 *  0b001000..T2_MAT3
 *  0b001001..T2_MAT2
 *  0b001010..T3_MAT2
 *  0b001011..T4_MAT2
 *  0b001100..ACMP0_OUT
 *  0b001101..GPIOINT_BMATCH
 *  0b001110..ADC0_IRQ
 *  0b001111..ADC1_IRQ
 *  0b010000..ADC0_tcomp[0]
 *  0b010001..ADC0_tcomp[1]
 *  0b010010..ADC0_tcomp[2]
 *  0b010011..ADC0_tcomp[3]
 *  0b010100..ADC1_tcomp[0]
 *  0b010101..ADC1_tcomp[1]
 *  0b010110..ADC1_tcomp[2]
 *  0b010111..ADC1_tcomp[3]
 *  0b011000..HSCMP0_OUT
 *  0b011001..HSCMP1_OUT
 *  0b011010..HSCMP2_OUT
 *  0b011011..PWM0_SM0_MUX_TRIG0
 *  0b011100..PWM0_SM0_MUX_TRIG1
 *  0b011101..PWM0_SM1_MUX_TRIG0
 *  0b011110..PWM0_SM1_MUX_TRIG1
 *  0b011111..PWM0_SM2_MUX_TRIG0
 *  0b100000..PWM0_SM2_MUX_TRIG1
 *  0b100001..PWM0_SM3_MUX_TRIG0
 *  0b100010..PWM0_SM3_MUX_TRIG1
 *  0b100011..PWM1_SM0_MUX_TRIG0
 *  0b100100..PWM1_SM0_MUX_TRIG1
 *  0b100101..PWM1_SM1_MUX_TRIG0
 *  0b100110..PWM1_SM1_MUX_TRIG1
 *  0b100111..PWM1_SM2_MUX_TRIG0
 *  0b101000..PWM1_SM2_MUX_TRIG1
 *  0b101001..PWM1_SM3_MUX_TRIG0
 *  0b101010..PWM1_SM3_MUX_TRIG1
 *  0b101011..ENC0_CMP/POS_MATCH
 *  0b101100..ENC1_CMP/POS_MATCH
 *  0b101101..EXTTRIG_IN0
 *  0b101110..EXTTRIG_IN1
 *  0b101111..EXTTRIG_IN2
 *  0b110000..EXTTRIG_IN3
 *  0b110001..Reserved
 *  0b110010..Reserved
 *  0b110011..DMA0_TRIGOUT0
 *  0b110100..DMA0_TRIGOUT1
 *  0b110101..DMA0_TRIGOUT2
 *  0b110110..DMA0_TRIGOUT3
 *  0b110111..DMA0_TRIGOUT4
 *  0b111000..DMA0_TRIGOUT5
 *  0b111001..DMA0_TRIGOUT6
 *  0b111010..DMA1_TRIGOUT0
 *  0b111011..DMA1_TRIGOUT1
 *  0b111100..DMA1_TRIGOUT2
 */
#define INPUTMUX_AOI1_IN_IN(x)                   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_AOI1_IN_IN_SHIFT)) & INPUTMUX_AOI1_IN_IN_MASK)
/*! @} */

/* The count of INPUTMUX_AOI1_IN */
#define INPUTMUX_AOI1_INPUTTRIGGER0              (16U)

/*! @name AOIX_EXT_TRIGN_AOI_EXT_TRIG - AOI External Trigger Inputs */
/*! @{ */

#define INPUTMUX_AOIX_EXT_TRIGN_AOI_EXT_TRIG_TRIGIN_MASK (0x1FU)
#define INPUTMUX_AOIX_EXT_TRIGN_AOI_EXT_TRIG_TRIGIN_SHIFT (0U)
/*! TRIGIN - AOI external trigger inputs from 0 to 4.
 *  0b00000..PIN_INT0
 *  0b00001..PIN_INT1
 *  0b00010..ADC0_IRQ
 *  0b00011..ADC1_IRQ
 *  0b00100..ADC0_tcomp[0]
 *  0b00101..ADC1_tcomp[0]
 *  0b00110..PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1
 *  0b00111..PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1
 *  0b01000..PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1
 *  0b01001..PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1
 *  0b01010..PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1
 *  0b01011..PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1
 *  0b01100..PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1
 *  0b01101..PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1
 *  0b01110..ENC0_CMP/POS_MATCH
 *  0b01111..ENC1_CMP/POS_MATCH
 *  0b10000..AOI0_OUT0
 *  0b10001..AOI0_OUT1
 *  0b10010..AOI0_OUT2
 *  0b10011..AOI0_OUT3
 *  0b10100..AOI1_OUT0
 *  0b10101..AOI1_OUT1
 *  0b10110..AOI1_OUT2
 *  0b10111..AOI1_OUT3
 *  0b11000..TMPR_OUT
 *  0b11001-0b11111..None
 */
#define INPUTMUX_AOIX_EXT_TRIGN_AOI_EXT_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_AOIX_EXT_TRIGN_AOI_EXT_TRIG_TRIGIN_SHIFT)) & INPUTMUX_AOIX_EXT_TRIGN_AOI_EXT_TRIG_TRIGIN_MASK)
/*! @} */

/* The count of INPUTMUX_AOIX_EXT_TRIGN_AOI_EXT_TRIG */
#define INPUTMUX_AOIX_EXT_TRIGN_AOI_EXT_TRIG_COUNT (8U)

/*! @name HSCMP1_TRIG - Input connections for HSCMP1 */
/*! @{ */

#define INPUTMUX_HSCMP1_TRIG_TRIGIN_MASK         (0x3FU)
#define INPUTMUX_HSCMP1_TRIG_TRIGIN_SHIFT        (0U)
/*! TRIGIN - CMP1 input trigger
 *  0b000000..PIN_INT0
 *  0b000001..PIN_INT7
 *  0b000010..SCT_OUT4
 *  0b000011..SCT_OUT5
 *  0b000100..SCT_OUT7
 *  0b000101..T0_MAT3
 *  0b000110..T1_MAT3
 *  0b000111..T2_MAT3
 *  0b001000..T0_MAT1
 *  0b001001..T4_MAT1
 *  0b001010..Reserved
 *  0b001011..ARM_TXEV
 *  0b001100..GPIOINT_BMATCH
 *  0b001101..ADC0_tcomp[1]
 *  0b001110..ADC1_tcomp[1]
 *  0b001111..Reserved
 *  0b010000..Reserved
 *  0b010001..PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1
 *  0b010010..PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1
 *  0b010011..PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1
 *  0b010100..PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1
 *  0b010101..PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1
 *  0b010110..PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1
 *  0b010111..PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1
 *  0b011000..PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1
 *  0b011001..ENC0_CMP/POS_MATCH
 *  0b011010..ENC1_CMP/POS_MATCH
 *  0b011011..AOI0_OUT0
 *  0b011100..AOI0_OUT1
 *  0b011101..AOI0_OUT2
 *  0b011110..AOI0_OUT3
 *  0b011111..AOI1_OUT0
 *  0b100000..AOI1_OUT1
 *  0b100001..AOI1_OUT2
 *  0b100010..AOI1_OUT3
 *  0b100011..DMA0_TRIGOUT0
 *  0b100100..DMA0_TRIGOUT1
 *  0b100101..DMA0_TRIGOUT2
 */
#define INPUTMUX_HSCMP1_TRIG_TRIGIN(x)           (((uint32_t)(((uint32_t)(x)) << INPUTMUX_HSCMP1_TRIG_TRIGIN_SHIFT)) & INPUTMUX_HSCMP1_TRIG_TRIGIN_MASK)
/*! @} */

/*! @name HSCMP2_TRIG - Input connections for HSCMP2 */
/*! @{ */

#define INPUTMUX_HSCMP2_TRIG_TRIGIN_MASK         (0x3FU)
#define INPUTMUX_HSCMP2_TRIG_TRIGIN_SHIFT        (0U)
/*! TRIGIN - CMP2 input trigger
 *  0b000000..PIN_INT0
 *  0b000001..PIN_INT4
 *  0b000010..SCT_OUT4
 *  0b000011..SCT_OUT5
 *  0b000100..SCT_OUT8
 *  0b000101..T0_MAT3
 *  0b000110..T1_MAT3
 *  0b000111..T2_MAT3
 *  0b001000..T0_MAT2
 *  0b001001..T4_MAT2
 *  0b001010..Reserved
 *  0b001011..ARM_TXEV
 *  0b001100..GPIOINT_BMATCH
 *  0b001101..ADC0_tcomp[2]
 *  0b001110..ADC1_tcomp[2]
 *  0b001111..Reserved
 *  0b010000..Reserved
 *  0b010001..PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1
 *  0b010010..PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1
 *  0b010011..PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1
 *  0b010100..PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1
 *  0b010101..PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1
 *  0b010110..PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1
 *  0b010111..PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1
 *  0b011000..PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1
 *  0b011001..ENC0_CMP/POS_MATCH
 *  0b011010..ENC1_CMP/POS_MATCH
 *  0b011011..AOI0_OUT0
 *  0b011100..AOI0_OUT1
 *  0b011101..AOI0_OUT2
 *  0b011110..AOI0_OUT3
 *  0b011111..AOI1_OUT0
 *  0b100000..AOI1_OUT1
 *  0b100001..AOI1_OUT2
 *  0b100010..AOI1_OUT3
 *  0b100011..DMA0_TRIGOUT0
 *  0b100100..DMA0_TRIGOUT1
 *  0b100101..DMA0_TRIGOUT2
 */
#define INPUTMUX_HSCMP2_TRIG_TRIGIN(x)           (((uint32_t)(((uint32_t)(x)) << INPUTMUX_HSCMP2_TRIG_TRIGIN_SHIFT)) & INPUTMUX_HSCMP2_TRIG_TRIGIN_MASK)
/*! @} */

/*! @name DMA0_ITRIG_INMUX32 - Trigger select for DMA0 channel */
/*! @{ */

#define INPUTMUX_DMA0_ITRIG_INMUX32_INP_MASK     (0x3FU)
#define INPUTMUX_DMA0_ITRIG_INMUX32_INP_SHIFT    (0U)
/*! INP - Trigger input number (binary value) for DMA channel n (n = 32 to 51).
 *  0b000000..FlexSPI_RX
 *  0b000001..FlexSPI_TX
 *  0b000010..GPIO_INT0
 *  0b000011..GPIO_INT1
 *  0b000100..GPIO_INT2
 *  0b000101..GPIO_INT3
 *  0b000110..T0_DMAREQ_M0
 *  0b000111..T0_DMAREQ_M1
 *  0b001000..T1_DMAREQ_M0
 *  0b001001..T1_DMAREQ_M1
 *  0b001010..T2_DMAREQ_M0
 *  0b001011..T2_DMAREQ_M1
 *  0b001100..T3_DMAREQ_M0
 *  0b001101..T3_DMAREQ_M1
 *  0b001110..T4_DMAREQ_M0
 *  0b001111..T4_DMAREQ_M1
 *  0b010000..ACMP0_OUT
 *  0b010001..SDMA0_TRIGOUT_A
 *  0b010010..SDMA0_TRIGOUT_B
 *  0b010011..SDMA0_TRIGOUT_C
 *  0b010100..SDMA0_TRIGOUT_D
 *  0b010101..SCT_DMA0
 *  0b010110..SCT_DMA1
 *  0b010111..ADC0_tcomp[0]
 *  0b011000..ADC1_tcomp[0]
 *  0b011001..HSCMP0
 *  0b011010..HSCMP1
 *  0b011011..HSCMP2
 *  0b011100..AOI0_OUT0
 *  0b011101..AOI0_OUT1
 *  0b011110..AOI0_OUT2
 *  0b011111..AOI0_OUT3
 *  0b100000..AOI1_OUT0
 *  0b100001..AOI1_OUT1
 *  0b100010..AOI1_OUT2
 *  0b100011..AOI1_OUT3
 *  0b100100..FlexPWM0_req_capt0
 *  0b100101..FlexPWM0_req_capt1
 *  0b100110..FlexPWM0_req_capt2
 *  0b100111..FlexPWM0_req_capt3
 *  0b101000..FlexPWM0_req_val0
 *  0b101001..FlexPWM0_req_val1
 *  0b101010..FlexPWM0_req_val2
 *  0b101011..FlexPWM0_req_val3
 *  0b101100..FlexPWM1_req_capt0
 *  0b101101..FlexPWM1_req_capt1
 *  0b101110..FlexPWM1_req_capt2
 *  0b101111..FlexPWM1_req_capt3
 *  0b110000..FlexPWM1_req_val0
 *  0b110001..FlexPWM1_req_val1
 *  0b110010..FlexPWM1_req_val2
 *  0b110011..FlexPWM1_req_val3
 *  0b110100..TMPR_OUT
 *  0b110110-0b111111..Reserved
 */
#define INPUTMUX_DMA0_ITRIG_INMUX32_INP(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_INMUX32_INP_SHIFT)) & INPUTMUX_DMA0_ITRIG_INMUX32_INP_MASK)
/*! @} */

/* The count of INPUTMUX_DMA0_ITRIG_INMUX32 */
#define INPUTMUX_DMA0_ITRIG_INMUX32_COUNT        (20U)

/*! @name DMA0_REQEN0 - Enable DMA0 requests */
/*! @{ */

#define INPUTMUX_DMA0_REQEN0_REQ_ENA0_MASK       (0x1U)
#define INPUTMUX_DMA0_REQEN0_REQ_ENA0_SHIFT      (0U)
/*! REQ_ENA0 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled.
 */
#define INPUTMUX_DMA0_REQEN0_REQ_ENA0(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA0_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA0_MASK)

#define INPUTMUX_DMA0_REQEN0_REQ_ENA1_MASK       (0x2U)
#define INPUTMUX_DMA0_REQEN0_REQ_ENA1_SHIFT      (1U)
/*! REQ_ENA1 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled.
 */
#define INPUTMUX_DMA0_REQEN0_REQ_ENA1(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA1_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA1_MASK)

#define INPUTMUX_DMA0_REQEN0_REQ_ENA2_MASK       (0x4U)
#define INPUTMUX_DMA0_REQEN0_REQ_ENA2_SHIFT      (2U)
/*! REQ_ENA2 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled.
 */
#define INPUTMUX_DMA0_REQEN0_REQ_ENA2(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA2_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA2_MASK)

#define INPUTMUX_DMA0_REQEN0_REQ_ENA3_MASK       (0x8U)
#define INPUTMUX_DMA0_REQEN0_REQ_ENA3_SHIFT      (3U)
/*! REQ_ENA3 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled.
 */
#define INPUTMUX_DMA0_REQEN0_REQ_ENA3(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA3_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA3_MASK)

#define INPUTMUX_DMA0_REQEN0_REQ_ENA4_MASK       (0x10U)
#define INPUTMUX_DMA0_REQEN0_REQ_ENA4_SHIFT      (4U)
/*! REQ_ENA4 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled.
 */
#define INPUTMUX_DMA0_REQEN0_REQ_ENA4(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA4_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA4_MASK)

#define INPUTMUX_DMA0_REQEN0_REQ_ENA5_MASK       (0x20U)
#define INPUTMUX_DMA0_REQEN0_REQ_ENA5_SHIFT      (5U)
/*! REQ_ENA5 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled.
 */
#define INPUTMUX_DMA0_REQEN0_REQ_ENA5(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA5_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA5_MASK)

#define INPUTMUX_DMA0_REQEN0_REQ_ENA6_MASK       (0x40U)
#define INPUTMUX_DMA0_REQEN0_REQ_ENA6_SHIFT      (6U)
/*! REQ_ENA6 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled.
 */
#define INPUTMUX_DMA0_REQEN0_REQ_ENA6(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA6_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA6_MASK)

#define INPUTMUX_DMA0_REQEN0_REQ_ENA7_MASK       (0x80U)
#define INPUTMUX_DMA0_REQEN0_REQ_ENA7_SHIFT      (7U)
/*! REQ_ENA7 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled.
 */
#define INPUTMUX_DMA0_REQEN0_REQ_ENA7(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA7_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA7_MASK)

#define INPUTMUX_DMA0_REQEN0_REQ_ENA8_MASK       (0x100U)
#define INPUTMUX_DMA0_REQEN0_REQ_ENA8_SHIFT      (8U)
/*! REQ_ENA8 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled.
 */
#define INPUTMUX_DMA0_REQEN0_REQ_ENA8(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA8_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA8_MASK)

#define INPUTMUX_DMA0_REQEN0_REQ_ENA9_MASK       (0x200U)
#define INPUTMUX_DMA0_REQEN0_REQ_ENA9_SHIFT      (9U)
/*! REQ_ENA9 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled.
 */
#define INPUTMUX_DMA0_REQEN0_REQ_ENA9(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA9_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA9_MASK)

#define INPUTMUX_DMA0_REQEN0_REQ_ENA10_MASK      (0x400U)
#define INPUTMUX_DMA0_REQEN0_REQ_ENA10_SHIFT     (10U)
/*! REQ_ENA10 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled.
 */
#define INPUTMUX_DMA0_REQEN0_REQ_ENA10(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA10_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA10_MASK)

#define INPUTMUX_DMA0_REQEN0_REQ_ENA11_MASK      (0x800U)
#define INPUTMUX_DMA0_REQEN0_REQ_ENA11_SHIFT     (11U)
/*! REQ_ENA11 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled.
 */
#define INPUTMUX_DMA0_REQEN0_REQ_ENA11(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA11_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA11_MASK)

#define INPUTMUX_DMA0_REQEN0_REQ_ENA12_MASK      (0x1000U)
#define INPUTMUX_DMA0_REQEN0_REQ_ENA12_SHIFT     (12U)
/*! REQ_ENA12 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled.
 */
#define INPUTMUX_DMA0_REQEN0_REQ_ENA12(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA12_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA12_MASK)

#define INPUTMUX_DMA0_REQEN0_REQ_ENA13_MASK      (0x2000U)
#define INPUTMUX_DMA0_REQEN0_REQ_ENA13_SHIFT     (13U)
/*! REQ_ENA13 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled.
 */
#define INPUTMUX_DMA0_REQEN0_REQ_ENA13(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA13_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA13_MASK)

#define INPUTMUX_DMA0_REQEN0_REQ_ENA14_MASK      (0x4000U)
#define INPUTMUX_DMA0_REQEN0_REQ_ENA14_SHIFT     (14U)
/*! REQ_ENA14 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled.
 */
#define INPUTMUX_DMA0_REQEN0_REQ_ENA14(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA14_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA14_MASK)

#define INPUTMUX_DMA0_REQEN0_REQ_ENA15_MASK      (0x8000U)
#define INPUTMUX_DMA0_REQEN0_REQ_ENA15_SHIFT     (15U)
/*! REQ_ENA15 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled.
 */
#define INPUTMUX_DMA0_REQEN0_REQ_ENA15(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA15_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA15_MASK)

#define INPUTMUX_DMA0_REQEN0_REQ_ENA16_MASK      (0x10000U)
#define INPUTMUX_DMA0_REQEN0_REQ_ENA16_SHIFT     (16U)
/*! REQ_ENA16 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled.
 */
#define INPUTMUX_DMA0_REQEN0_REQ_ENA16(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA16_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA16_MASK)

#define INPUTMUX_DMA0_REQEN0_REQ_ENA17_MASK      (0x20000U)
#define INPUTMUX_DMA0_REQEN0_REQ_ENA17_SHIFT     (17U)
/*! REQ_ENA17 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled.
 */
#define INPUTMUX_DMA0_REQEN0_REQ_ENA17(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA17_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA17_MASK)

#define INPUTMUX_DMA0_REQEN0_REQ_ENA18_MASK      (0x40000U)
#define INPUTMUX_DMA0_REQEN0_REQ_ENA18_SHIFT     (18U)
/*! REQ_ENA18 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled.
 */
#define INPUTMUX_DMA0_REQEN0_REQ_ENA18(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA18_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA18_MASK)

#define INPUTMUX_DMA0_REQEN0_REQ_ENA19_MASK      (0x80000U)
#define INPUTMUX_DMA0_REQEN0_REQ_ENA19_SHIFT     (19U)
/*! REQ_ENA19 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled.
 */
#define INPUTMUX_DMA0_REQEN0_REQ_ENA19(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA19_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA19_MASK)

#define INPUTMUX_DMA0_REQEN0_REQ_ENA20_MASK      (0x100000U)
#define INPUTMUX_DMA0_REQEN0_REQ_ENA20_SHIFT     (20U)
/*! REQ_ENA20 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled.
 */
#define INPUTMUX_DMA0_REQEN0_REQ_ENA20(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA20_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA20_MASK)

#define INPUTMUX_DMA0_REQEN0_REQ_ENA21_MASK      (0x200000U)
#define INPUTMUX_DMA0_REQEN0_REQ_ENA21_SHIFT     (21U)
/*! REQ_ENA21 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled.
 */
#define INPUTMUX_DMA0_REQEN0_REQ_ENA21(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA21_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA21_MASK)

#define INPUTMUX_DMA0_REQEN0_REQ_ENA22_MASK      (0x400000U)
#define INPUTMUX_DMA0_REQEN0_REQ_ENA22_SHIFT     (22U)
/*! REQ_ENA22 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled.
 */
#define INPUTMUX_DMA0_REQEN0_REQ_ENA22(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA22_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA22_MASK)

#define INPUTMUX_DMA0_REQEN0_REQ_ENA23_MASK      (0x800000U)
#define INPUTMUX_DMA0_REQEN0_REQ_ENA23_SHIFT     (23U)
/*! REQ_ENA23 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled.
 */
#define INPUTMUX_DMA0_REQEN0_REQ_ENA23(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA23_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA23_MASK)

#define INPUTMUX_DMA0_REQEN0_REQ_ENA24_MASK      (0x1000000U)
#define INPUTMUX_DMA0_REQEN0_REQ_ENA24_SHIFT     (24U)
/*! REQ_ENA24 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled.
 */
#define INPUTMUX_DMA0_REQEN0_REQ_ENA24(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA24_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA24_MASK)

#define INPUTMUX_DMA0_REQEN0_REQ_ENA25_MASK      (0x2000000U)
#define INPUTMUX_DMA0_REQEN0_REQ_ENA25_SHIFT     (25U)
/*! REQ_ENA25 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled.
 */
#define INPUTMUX_DMA0_REQEN0_REQ_ENA25(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA25_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA25_MASK)

#define INPUTMUX_DMA0_REQEN0_REQ_ENA26_MASK      (0x4000000U)
#define INPUTMUX_DMA0_REQEN0_REQ_ENA26_SHIFT     (26U)
/*! REQ_ENA26 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled.
 */
#define INPUTMUX_DMA0_REQEN0_REQ_ENA26(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA26_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA26_MASK)

#define INPUTMUX_DMA0_REQEN0_REQ_ENA27_MASK      (0x8000000U)
#define INPUTMUX_DMA0_REQEN0_REQ_ENA27_SHIFT     (27U)
/*! REQ_ENA27 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled.
 */
#define INPUTMUX_DMA0_REQEN0_REQ_ENA27(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA27_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA27_MASK)

#define INPUTMUX_DMA0_REQEN0_REQ_ENA28_MASK      (0x10000000U)
#define INPUTMUX_DMA0_REQEN0_REQ_ENA28_SHIFT     (28U)
/*! REQ_ENA28 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled.
 */
#define INPUTMUX_DMA0_REQEN0_REQ_ENA28(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA28_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA28_MASK)

#define INPUTMUX_DMA0_REQEN0_REQ_ENA29_MASK      (0x20000000U)
#define INPUTMUX_DMA0_REQEN0_REQ_ENA29_SHIFT     (29U)
/*! REQ_ENA29 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled.
 */
#define INPUTMUX_DMA0_REQEN0_REQ_ENA29(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA29_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA29_MASK)

#define INPUTMUX_DMA0_REQEN0_REQ_ENA30_MASK      (0x40000000U)
#define INPUTMUX_DMA0_REQEN0_REQ_ENA30_SHIFT     (30U)
/*! REQ_ENA30 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled.
 */
#define INPUTMUX_DMA0_REQEN0_REQ_ENA30(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA30_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA30_MASK)

#define INPUTMUX_DMA0_REQEN0_REQ_ENA31_MASK      (0x80000000U)
#define INPUTMUX_DMA0_REQEN0_REQ_ENA31_SHIFT     (31U)
/*! REQ_ENA31 - Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled.
 */
#define INPUTMUX_DMA0_REQEN0_REQ_ENA31(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_REQ_ENA31_SHIFT)) & INPUTMUX_DMA0_REQEN0_REQ_ENA31_MASK)
/*! @} */

/*! @name DMA0_REQEN1 - Enable DMA0 requests */
/*! @{ */

#define INPUTMUX_DMA0_REQEN1_REQ_ENA0_MASK       (0x1U)
#define INPUTMUX_DMA0_REQEN1_REQ_ENA0_SHIFT      (0U)
/*! REQ_ENA0 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled.
 */
#define INPUTMUX_DMA0_REQEN1_REQ_ENA0(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA0_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA0_MASK)

#define INPUTMUX_DMA0_REQEN1_REQ_ENA1_MASK       (0x2U)
#define INPUTMUX_DMA0_REQEN1_REQ_ENA1_SHIFT      (1U)
/*! REQ_ENA1 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled.
 */
#define INPUTMUX_DMA0_REQEN1_REQ_ENA1(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA1_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA1_MASK)

#define INPUTMUX_DMA0_REQEN1_REQ_ENA2_MASK       (0x4U)
#define INPUTMUX_DMA0_REQEN1_REQ_ENA2_SHIFT      (2U)
/*! REQ_ENA2 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled.
 */
#define INPUTMUX_DMA0_REQEN1_REQ_ENA2(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA2_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA2_MASK)

#define INPUTMUX_DMA0_REQEN1_REQ_ENA3_MASK       (0x8U)
#define INPUTMUX_DMA0_REQEN1_REQ_ENA3_SHIFT      (3U)
/*! REQ_ENA3 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled.
 */
#define INPUTMUX_DMA0_REQEN1_REQ_ENA3(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA3_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA3_MASK)

#define INPUTMUX_DMA0_REQEN1_REQ_ENA4_MASK       (0x10U)
#define INPUTMUX_DMA0_REQEN1_REQ_ENA4_SHIFT      (4U)
/*! REQ_ENA4 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled.
 */
#define INPUTMUX_DMA0_REQEN1_REQ_ENA4(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA4_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA4_MASK)

#define INPUTMUX_DMA0_REQEN1_REQ_ENA5_MASK       (0x20U)
#define INPUTMUX_DMA0_REQEN1_REQ_ENA5_SHIFT      (5U)
/*! REQ_ENA5 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled.
 */
#define INPUTMUX_DMA0_REQEN1_REQ_ENA5(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA5_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA5_MASK)

#define INPUTMUX_DMA0_REQEN1_REQ_ENA6_MASK       (0x40U)
#define INPUTMUX_DMA0_REQEN1_REQ_ENA6_SHIFT      (6U)
/*! REQ_ENA6 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled.
 */
#define INPUTMUX_DMA0_REQEN1_REQ_ENA6(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA6_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA6_MASK)

#define INPUTMUX_DMA0_REQEN1_REQ_ENA7_MASK       (0x80U)
#define INPUTMUX_DMA0_REQEN1_REQ_ENA7_SHIFT      (7U)
/*! REQ_ENA7 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled.
 */
#define INPUTMUX_DMA0_REQEN1_REQ_ENA7(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA7_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA7_MASK)

#define INPUTMUX_DMA0_REQEN1_REQ_ENA8_MASK       (0x100U)
#define INPUTMUX_DMA0_REQEN1_REQ_ENA8_SHIFT      (8U)
/*! REQ_ENA8 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled.
 */
#define INPUTMUX_DMA0_REQEN1_REQ_ENA8(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA8_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA8_MASK)

#define INPUTMUX_DMA0_REQEN1_REQ_ENA9_MASK       (0x200U)
#define INPUTMUX_DMA0_REQEN1_REQ_ENA9_SHIFT      (9U)
/*! REQ_ENA9 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled.
 */
#define INPUTMUX_DMA0_REQEN1_REQ_ENA9(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA9_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA9_MASK)

#define INPUTMUX_DMA0_REQEN1_REQ_ENA10_MASK      (0x400U)
#define INPUTMUX_DMA0_REQEN1_REQ_ENA10_SHIFT     (10U)
/*! REQ_ENA10 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled.
 */
#define INPUTMUX_DMA0_REQEN1_REQ_ENA10(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA10_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA10_MASK)

#define INPUTMUX_DMA0_REQEN1_REQ_ENA11_MASK      (0x800U)
#define INPUTMUX_DMA0_REQEN1_REQ_ENA11_SHIFT     (11U)
/*! REQ_ENA11 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled.
 */
#define INPUTMUX_DMA0_REQEN1_REQ_ENA11(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA11_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA11_MASK)

#define INPUTMUX_DMA0_REQEN1_REQ_ENA12_MASK      (0x1000U)
#define INPUTMUX_DMA0_REQEN1_REQ_ENA12_SHIFT     (12U)
/*! REQ_ENA12 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled.
 */
#define INPUTMUX_DMA0_REQEN1_REQ_ENA12(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA12_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA12_MASK)

#define INPUTMUX_DMA0_REQEN1_REQ_ENA13_MASK      (0x2000U)
#define INPUTMUX_DMA0_REQEN1_REQ_ENA13_SHIFT     (13U)
/*! REQ_ENA13 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled.
 */
#define INPUTMUX_DMA0_REQEN1_REQ_ENA13(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA13_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA13_MASK)

#define INPUTMUX_DMA0_REQEN1_REQ_ENA14_MASK      (0x4000U)
#define INPUTMUX_DMA0_REQEN1_REQ_ENA14_SHIFT     (14U)
/*! REQ_ENA14 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled.
 */
#define INPUTMUX_DMA0_REQEN1_REQ_ENA14(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA14_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA14_MASK)

#define INPUTMUX_DMA0_REQEN1_REQ_ENA15_MASK      (0x8000U)
#define INPUTMUX_DMA0_REQEN1_REQ_ENA15_SHIFT     (15U)
/*! REQ_ENA15 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled.
 */
#define INPUTMUX_DMA0_REQEN1_REQ_ENA15(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA15_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA15_MASK)

#define INPUTMUX_DMA0_REQEN1_REQ_ENA16_MASK      (0x10000U)
#define INPUTMUX_DMA0_REQEN1_REQ_ENA16_SHIFT     (16U)
/*! REQ_ENA16 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled.
 */
#define INPUTMUX_DMA0_REQEN1_REQ_ENA16(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA16_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA16_MASK)

#define INPUTMUX_DMA0_REQEN1_REQ_ENA17_MASK      (0x20000U)
#define INPUTMUX_DMA0_REQEN1_REQ_ENA17_SHIFT     (17U)
/*! REQ_ENA17 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled.
 */
#define INPUTMUX_DMA0_REQEN1_REQ_ENA17(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA17_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA17_MASK)

#define INPUTMUX_DMA0_REQEN1_REQ_ENA18_MASK      (0x40000U)
#define INPUTMUX_DMA0_REQEN1_REQ_ENA18_SHIFT     (18U)
/*! REQ_ENA18 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled.
 */
#define INPUTMUX_DMA0_REQEN1_REQ_ENA18(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA18_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA18_MASK)

#define INPUTMUX_DMA0_REQEN1_REQ_ENA19_MASK      (0x80000U)
#define INPUTMUX_DMA0_REQEN1_REQ_ENA19_SHIFT     (19U)
/*! REQ_ENA19 - Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request input #(i+32) is enabled.
 */
#define INPUTMUX_DMA0_REQEN1_REQ_ENA19(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_REQ_ENA19_SHIFT)) & INPUTMUX_DMA0_REQEN1_REQ_ENA19_MASK)
/*! @} */

/*! @name DMA0_REQEN0_SET - Set bits in DMA0_REQEN0 register */
/*! @{ */

#define INPUTMUX_DMA0_REQEN0_SET_SET0_MASK       (0x1U)
#define INPUTMUX_DMA0_REQEN0_SET_SET0_SHIFT      (0U)
/*! SET0 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_SET_SET0(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET0_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET0_MASK)

#define INPUTMUX_DMA0_REQEN0_SET_SET1_MASK       (0x2U)
#define INPUTMUX_DMA0_REQEN0_SET_SET1_SHIFT      (1U)
/*! SET1 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_SET_SET1(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET1_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET1_MASK)

#define INPUTMUX_DMA0_REQEN0_SET_SET2_MASK       (0x4U)
#define INPUTMUX_DMA0_REQEN0_SET_SET2_SHIFT      (2U)
/*! SET2 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_SET_SET2(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET2_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET2_MASK)

#define INPUTMUX_DMA0_REQEN0_SET_SET3_MASK       (0x8U)
#define INPUTMUX_DMA0_REQEN0_SET_SET3_SHIFT      (3U)
/*! SET3 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_SET_SET3(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET3_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET3_MASK)

#define INPUTMUX_DMA0_REQEN0_SET_SET4_MASK       (0x10U)
#define INPUTMUX_DMA0_REQEN0_SET_SET4_SHIFT      (4U)
/*! SET4 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_SET_SET4(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET4_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET4_MASK)

#define INPUTMUX_DMA0_REQEN0_SET_SET5_MASK       (0x20U)
#define INPUTMUX_DMA0_REQEN0_SET_SET5_SHIFT      (5U)
/*! SET5 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_SET_SET5(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET5_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET5_MASK)

#define INPUTMUX_DMA0_REQEN0_SET_SET6_MASK       (0x40U)
#define INPUTMUX_DMA0_REQEN0_SET_SET6_SHIFT      (6U)
/*! SET6 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_SET_SET6(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET6_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET6_MASK)

#define INPUTMUX_DMA0_REQEN0_SET_SET7_MASK       (0x80U)
#define INPUTMUX_DMA0_REQEN0_SET_SET7_SHIFT      (7U)
/*! SET7 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_SET_SET7(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET7_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET7_MASK)

#define INPUTMUX_DMA0_REQEN0_SET_SET8_MASK       (0x100U)
#define INPUTMUX_DMA0_REQEN0_SET_SET8_SHIFT      (8U)
/*! SET8 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_SET_SET8(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET8_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET8_MASK)

#define INPUTMUX_DMA0_REQEN0_SET_SET9_MASK       (0x200U)
#define INPUTMUX_DMA0_REQEN0_SET_SET9_SHIFT      (9U)
/*! SET9 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_SET_SET9(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET9_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET9_MASK)

#define INPUTMUX_DMA0_REQEN0_SET_SET10_MASK      (0x400U)
#define INPUTMUX_DMA0_REQEN0_SET_SET10_SHIFT     (10U)
/*! SET10 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_SET_SET10(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET10_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET10_MASK)

#define INPUTMUX_DMA0_REQEN0_SET_SET11_MASK      (0x800U)
#define INPUTMUX_DMA0_REQEN0_SET_SET11_SHIFT     (11U)
/*! SET11 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_SET_SET11(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET11_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET11_MASK)

#define INPUTMUX_DMA0_REQEN0_SET_SET12_MASK      (0x1000U)
#define INPUTMUX_DMA0_REQEN0_SET_SET12_SHIFT     (12U)
/*! SET12 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_SET_SET12(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET12_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET12_MASK)

#define INPUTMUX_DMA0_REQEN0_SET_SET13_MASK      (0x2000U)
#define INPUTMUX_DMA0_REQEN0_SET_SET13_SHIFT     (13U)
/*! SET13 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_SET_SET13(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET13_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET13_MASK)

#define INPUTMUX_DMA0_REQEN0_SET_SET14_MASK      (0x4000U)
#define INPUTMUX_DMA0_REQEN0_SET_SET14_SHIFT     (14U)
/*! SET14 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_SET_SET14(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET14_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET14_MASK)

#define INPUTMUX_DMA0_REQEN0_SET_SET15_MASK      (0x8000U)
#define INPUTMUX_DMA0_REQEN0_SET_SET15_SHIFT     (15U)
/*! SET15 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_SET_SET15(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET15_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET15_MASK)

#define INPUTMUX_DMA0_REQEN0_SET_SET16_MASK      (0x10000U)
#define INPUTMUX_DMA0_REQEN0_SET_SET16_SHIFT     (16U)
/*! SET16 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_SET_SET16(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET16_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET16_MASK)

#define INPUTMUX_DMA0_REQEN0_SET_SET17_MASK      (0x20000U)
#define INPUTMUX_DMA0_REQEN0_SET_SET17_SHIFT     (17U)
/*! SET17 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_SET_SET17(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET17_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET17_MASK)

#define INPUTMUX_DMA0_REQEN0_SET_SET18_MASK      (0x40000U)
#define INPUTMUX_DMA0_REQEN0_SET_SET18_SHIFT     (18U)
/*! SET18 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_SET_SET18(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET18_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET18_MASK)

#define INPUTMUX_DMA0_REQEN0_SET_SET19_MASK      (0x80000U)
#define INPUTMUX_DMA0_REQEN0_SET_SET19_SHIFT     (19U)
/*! SET19 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_SET_SET19(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET19_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET19_MASK)

#define INPUTMUX_DMA0_REQEN0_SET_SET20_MASK      (0x100000U)
#define INPUTMUX_DMA0_REQEN0_SET_SET20_SHIFT     (20U)
/*! SET20 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_SET_SET20(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET20_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET20_MASK)

#define INPUTMUX_DMA0_REQEN0_SET_SET21_MASK      (0x200000U)
#define INPUTMUX_DMA0_REQEN0_SET_SET21_SHIFT     (21U)
/*! SET21 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_SET_SET21(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET21_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET21_MASK)

#define INPUTMUX_DMA0_REQEN0_SET_SET22_MASK      (0x400000U)
#define INPUTMUX_DMA0_REQEN0_SET_SET22_SHIFT     (22U)
/*! SET22 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_SET_SET22(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET22_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET22_MASK)

#define INPUTMUX_DMA0_REQEN0_SET_SET23_MASK      (0x800000U)
#define INPUTMUX_DMA0_REQEN0_SET_SET23_SHIFT     (23U)
/*! SET23 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_SET_SET23(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET23_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET23_MASK)

#define INPUTMUX_DMA0_REQEN0_SET_SET24_MASK      (0x1000000U)
#define INPUTMUX_DMA0_REQEN0_SET_SET24_SHIFT     (24U)
/*! SET24 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_SET_SET24(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET24_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET24_MASK)

#define INPUTMUX_DMA0_REQEN0_SET_SET25_MASK      (0x2000000U)
#define INPUTMUX_DMA0_REQEN0_SET_SET25_SHIFT     (25U)
/*! SET25 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_SET_SET25(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET25_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET25_MASK)

#define INPUTMUX_DMA0_REQEN0_SET_SET26_MASK      (0x4000000U)
#define INPUTMUX_DMA0_REQEN0_SET_SET26_SHIFT     (26U)
/*! SET26 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_SET_SET26(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET26_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET26_MASK)

#define INPUTMUX_DMA0_REQEN0_SET_SET27_MASK      (0x8000000U)
#define INPUTMUX_DMA0_REQEN0_SET_SET27_SHIFT     (27U)
/*! SET27 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_SET_SET27(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET27_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET27_MASK)

#define INPUTMUX_DMA0_REQEN0_SET_SET28_MASK      (0x10000000U)
#define INPUTMUX_DMA0_REQEN0_SET_SET28_SHIFT     (28U)
/*! SET28 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_SET_SET28(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET28_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET28_MASK)

#define INPUTMUX_DMA0_REQEN0_SET_SET29_MASK      (0x20000000U)
#define INPUTMUX_DMA0_REQEN0_SET_SET29_SHIFT     (29U)
/*! SET29 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_SET_SET29(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET29_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET29_MASK)

#define INPUTMUX_DMA0_REQEN0_SET_SET30_MASK      (0x40000000U)
#define INPUTMUX_DMA0_REQEN0_SET_SET30_SHIFT     (30U)
/*! SET30 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_SET_SET30(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET30_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET30_MASK)

#define INPUTMUX_DMA0_REQEN0_SET_SET31_MASK      (0x80000000U)
#define INPUTMUX_DMA0_REQEN0_SET_SET31_SHIFT     (31U)
/*! SET31 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_SET_SET31(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_SET_SET31_SHIFT)) & INPUTMUX_DMA0_REQEN0_SET_SET31_MASK)
/*! @} */

/*! @name DMA0_REQEN1_SET - Set bits in DMA0_REQEN1 register */
/*! @{ */

#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA0_MASK   (0x1U)
#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA0_SHIFT  (0U)
/*! REQ_ENA0 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register.
 */
#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA0(x)     (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA0_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA0_MASK)

#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA1_MASK   (0x2U)
#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA1_SHIFT  (1U)
/*! REQ_ENA1 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register.
 */
#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA1(x)     (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA1_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA1_MASK)

#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA2_MASK   (0x4U)
#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA2_SHIFT  (2U)
/*! REQ_ENA2 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register.
 */
#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA2(x)     (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA2_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA2_MASK)

#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA3_MASK   (0x8U)
#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA3_SHIFT  (3U)
/*! REQ_ENA3 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register.
 */
#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA3(x)     (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA3_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA3_MASK)

#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA4_MASK   (0x10U)
#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA4_SHIFT  (4U)
/*! REQ_ENA4 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register.
 */
#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA4(x)     (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA4_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA4_MASK)

#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA5_MASK   (0x20U)
#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA5_SHIFT  (5U)
/*! REQ_ENA5 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register.
 */
#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA5(x)     (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA5_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA5_MASK)

#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA6_MASK   (0x40U)
#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA6_SHIFT  (6U)
/*! REQ_ENA6 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register.
 */
#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA6(x)     (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA6_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA6_MASK)

#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA7_MASK   (0x80U)
#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA7_SHIFT  (7U)
/*! REQ_ENA7 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register.
 */
#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA7(x)     (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA7_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA7_MASK)

#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA8_MASK   (0x100U)
#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA8_SHIFT  (8U)
/*! REQ_ENA8 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register.
 */
#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA8(x)     (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA8_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA8_MASK)

#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA9_MASK   (0x200U)
#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA9_SHIFT  (9U)
/*! REQ_ENA9 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register.
 */
#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA9(x)     (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA9_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA9_MASK)

#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA10_MASK  (0x400U)
#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA10_SHIFT (10U)
/*! REQ_ENA10 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register.
 */
#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA10(x)    (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA10_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA10_MASK)

#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA11_MASK  (0x800U)
#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA11_SHIFT (11U)
/*! REQ_ENA11 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register.
 */
#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA11(x)    (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA11_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA11_MASK)

#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA12_MASK  (0x1000U)
#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA12_SHIFT (12U)
/*! REQ_ENA12 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register.
 */
#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA12(x)    (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA12_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA12_MASK)

#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA13_MASK  (0x2000U)
#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA13_SHIFT (13U)
/*! REQ_ENA13 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register.
 */
#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA13(x)    (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA13_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA13_MASK)

#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA14_MASK  (0x4000U)
#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA14_SHIFT (14U)
/*! REQ_ENA14 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register.
 */
#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA14(x)    (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA14_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA14_MASK)

#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA15_MASK  (0x8000U)
#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA15_SHIFT (15U)
/*! REQ_ENA15 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register.
 */
#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA15(x)    (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA15_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA15_MASK)

#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA16_MASK  (0x10000U)
#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA16_SHIFT (16U)
/*! REQ_ENA16 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register.
 */
#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA16(x)    (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA16_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA16_MASK)

#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA17_MASK  (0x20000U)
#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA17_SHIFT (17U)
/*! REQ_ENA17 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register.
 */
#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA17(x)    (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA17_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA17_MASK)

#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA18_MASK  (0x40000U)
#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA18_SHIFT (18U)
/*! REQ_ENA18 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register.
 */
#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA18(x)    (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA18_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA18_MASK)

#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA19_MASK  (0x80000U)
#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA19_SHIFT (19U)
/*! REQ_ENA19 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no change in DMA0_REQEN1 register.
 */
#define INPUTMUX_DMA0_REQEN1_SET_REQ_ENA19(x)    (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_SET_REQ_ENA19_SHIFT)) & INPUTMUX_DMA0_REQEN1_SET_REQ_ENA19_MASK)
/*! @} */

/*! @name DMA0_REQEN0_CLR - Clear bits in DMA0_REQEN0 register */
/*! @{ */

#define INPUTMUX_DMA0_REQEN0_CLR_CLR0_MASK       (0x1U)
#define INPUTMUX_DMA0_REQEN0_CLR_CLR0_SHIFT      (0U)
/*! CLR0 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_CLR_CLR0(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR0_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR0_MASK)

#define INPUTMUX_DMA0_REQEN0_CLR_CLR1_MASK       (0x2U)
#define INPUTMUX_DMA0_REQEN0_CLR_CLR1_SHIFT      (1U)
/*! CLR1 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_CLR_CLR1(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR1_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR1_MASK)

#define INPUTMUX_DMA0_REQEN0_CLR_CLR2_MASK       (0x4U)
#define INPUTMUX_DMA0_REQEN0_CLR_CLR2_SHIFT      (2U)
/*! CLR2 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_CLR_CLR2(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR2_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR2_MASK)

#define INPUTMUX_DMA0_REQEN0_CLR_CLR3_MASK       (0x8U)
#define INPUTMUX_DMA0_REQEN0_CLR_CLR3_SHIFT      (3U)
/*! CLR3 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_CLR_CLR3(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR3_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR3_MASK)

#define INPUTMUX_DMA0_REQEN0_CLR_CLR4_MASK       (0x10U)
#define INPUTMUX_DMA0_REQEN0_CLR_CLR4_SHIFT      (4U)
/*! CLR4 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_CLR_CLR4(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR4_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR4_MASK)

#define INPUTMUX_DMA0_REQEN0_CLR_CLR5_MASK       (0x20U)
#define INPUTMUX_DMA0_REQEN0_CLR_CLR5_SHIFT      (5U)
/*! CLR5 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_CLR_CLR5(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR5_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR5_MASK)

#define INPUTMUX_DMA0_REQEN0_CLR_CLR6_MASK       (0x40U)
#define INPUTMUX_DMA0_REQEN0_CLR_CLR6_SHIFT      (6U)
/*! CLR6 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_CLR_CLR6(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR6_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR6_MASK)

#define INPUTMUX_DMA0_REQEN0_CLR_CLR7_MASK       (0x80U)
#define INPUTMUX_DMA0_REQEN0_CLR_CLR7_SHIFT      (7U)
/*! CLR7 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_CLR_CLR7(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR7_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR7_MASK)

#define INPUTMUX_DMA0_REQEN0_CLR_CLR8_MASK       (0x100U)
#define INPUTMUX_DMA0_REQEN0_CLR_CLR8_SHIFT      (8U)
/*! CLR8 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_CLR_CLR8(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR8_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR8_MASK)

#define INPUTMUX_DMA0_REQEN0_CLR_CLR9_MASK       (0x200U)
#define INPUTMUX_DMA0_REQEN0_CLR_CLR9_SHIFT      (9U)
/*! CLR9 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_CLR_CLR9(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR9_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR9_MASK)

#define INPUTMUX_DMA0_REQEN0_CLR_CLR10_MASK      (0x400U)
#define INPUTMUX_DMA0_REQEN0_CLR_CLR10_SHIFT     (10U)
/*! CLR10 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_CLR_CLR10(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR10_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR10_MASK)

#define INPUTMUX_DMA0_REQEN0_CLR_CLR11_MASK      (0x800U)
#define INPUTMUX_DMA0_REQEN0_CLR_CLR11_SHIFT     (11U)
/*! CLR11 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_CLR_CLR11(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR11_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR11_MASK)

#define INPUTMUX_DMA0_REQEN0_CLR_CLR12_MASK      (0x1000U)
#define INPUTMUX_DMA0_REQEN0_CLR_CLR12_SHIFT     (12U)
/*! CLR12 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_CLR_CLR12(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR12_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR12_MASK)

#define INPUTMUX_DMA0_REQEN0_CLR_CLR13_MASK      (0x2000U)
#define INPUTMUX_DMA0_REQEN0_CLR_CLR13_SHIFT     (13U)
/*! CLR13 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_CLR_CLR13(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR13_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR13_MASK)

#define INPUTMUX_DMA0_REQEN0_CLR_CLR14_MASK      (0x4000U)
#define INPUTMUX_DMA0_REQEN0_CLR_CLR14_SHIFT     (14U)
/*! CLR14 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_CLR_CLR14(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR14_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR14_MASK)

#define INPUTMUX_DMA0_REQEN0_CLR_CLR15_MASK      (0x8000U)
#define INPUTMUX_DMA0_REQEN0_CLR_CLR15_SHIFT     (15U)
/*! CLR15 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_CLR_CLR15(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR15_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR15_MASK)

#define INPUTMUX_DMA0_REQEN0_CLR_CLR16_MASK      (0x10000U)
#define INPUTMUX_DMA0_REQEN0_CLR_CLR16_SHIFT     (16U)
/*! CLR16 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_CLR_CLR16(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR16_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR16_MASK)

#define INPUTMUX_DMA0_REQEN0_CLR_CLR17_MASK      (0x20000U)
#define INPUTMUX_DMA0_REQEN0_CLR_CLR17_SHIFT     (17U)
/*! CLR17 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_CLR_CLR17(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR17_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR17_MASK)

#define INPUTMUX_DMA0_REQEN0_CLR_CLR18_MASK      (0x40000U)
#define INPUTMUX_DMA0_REQEN0_CLR_CLR18_SHIFT     (18U)
/*! CLR18 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_CLR_CLR18(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR18_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR18_MASK)

#define INPUTMUX_DMA0_REQEN0_CLR_CLR19_MASK      (0x80000U)
#define INPUTMUX_DMA0_REQEN0_CLR_CLR19_SHIFT     (19U)
/*! CLR19 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_CLR_CLR19(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR19_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR19_MASK)

#define INPUTMUX_DMA0_REQEN0_CLR_CLR20_MASK      (0x100000U)
#define INPUTMUX_DMA0_REQEN0_CLR_CLR20_SHIFT     (20U)
/*! CLR20 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_CLR_CLR20(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR20_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR20_MASK)

#define INPUTMUX_DMA0_REQEN0_CLR_CLR21_MASK      (0x200000U)
#define INPUTMUX_DMA0_REQEN0_CLR_CLR21_SHIFT     (21U)
/*! CLR21 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_CLR_CLR21(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR21_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR21_MASK)

#define INPUTMUX_DMA0_REQEN0_CLR_CLR22_MASK      (0x400000U)
#define INPUTMUX_DMA0_REQEN0_CLR_CLR22_SHIFT     (22U)
/*! CLR22 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_CLR_CLR22(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR22_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR22_MASK)

#define INPUTMUX_DMA0_REQEN0_CLR_CLR23_MASK      (0x800000U)
#define INPUTMUX_DMA0_REQEN0_CLR_CLR23_SHIFT     (23U)
/*! CLR23 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_CLR_CLR23(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR23_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR23_MASK)

#define INPUTMUX_DMA0_REQEN0_CLR_CLR24_MASK      (0x1000000U)
#define INPUTMUX_DMA0_REQEN0_CLR_CLR24_SHIFT     (24U)
/*! CLR24 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_CLR_CLR24(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR24_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR24_MASK)

#define INPUTMUX_DMA0_REQEN0_CLR_CLR25_MASK      (0x2000000U)
#define INPUTMUX_DMA0_REQEN0_CLR_CLR25_SHIFT     (25U)
/*! CLR25 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_CLR_CLR25(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR25_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR25_MASK)

#define INPUTMUX_DMA0_REQEN0_CLR_CLR26_MASK      (0x4000000U)
#define INPUTMUX_DMA0_REQEN0_CLR_CLR26_SHIFT     (26U)
/*! CLR26 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_CLR_CLR26(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR26_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR26_MASK)

#define INPUTMUX_DMA0_REQEN0_CLR_CLR27_MASK      (0x8000000U)
#define INPUTMUX_DMA0_REQEN0_CLR_CLR27_SHIFT     (27U)
/*! CLR27 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_CLR_CLR27(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR27_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR27_MASK)

#define INPUTMUX_DMA0_REQEN0_CLR_CLR28_MASK      (0x10000000U)
#define INPUTMUX_DMA0_REQEN0_CLR_CLR28_SHIFT     (28U)
/*! CLR28 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_CLR_CLR28(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR28_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR28_MASK)

#define INPUTMUX_DMA0_REQEN0_CLR_CLR29_MASK      (0x20000000U)
#define INPUTMUX_DMA0_REQEN0_CLR_CLR29_SHIFT     (29U)
/*! CLR29 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_CLR_CLR29(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR29_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR29_MASK)

#define INPUTMUX_DMA0_REQEN0_CLR_CLR30_MASK      (0x40000000U)
#define INPUTMUX_DMA0_REQEN0_CLR_CLR30_SHIFT     (30U)
/*! CLR30 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_CLR_CLR30(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR30_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR30_MASK)

#define INPUTMUX_DMA0_REQEN0_CLR_CLR31_MASK      (0x80000000U)
#define INPUTMUX_DMA0_REQEN0_CLR_CLR31_SHIFT     (31U)
/*! CLR31 - Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN0 register.
 */
#define INPUTMUX_DMA0_REQEN0_CLR_CLR31(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN0_CLR_CLR31_SHIFT)) & INPUTMUX_DMA0_REQEN0_CLR_CLR31_MASK)
/*! @} */

/*! @name DMA0_REQEN1_CLR - Clear bits in DMA0_REQEN1 register */
/*! @{ */

#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA0_MASK   (0x1U)
#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA0_SHIFT  (0U)
/*! REQ_ENA0 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register.
 */
#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA0(x)     (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA0_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA0_MASK)

#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA1_MASK   (0x2U)
#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA1_SHIFT  (1U)
/*! REQ_ENA1 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register.
 */
#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA1(x)     (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA1_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA1_MASK)

#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA2_MASK   (0x4U)
#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA2_SHIFT  (2U)
/*! REQ_ENA2 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register.
 */
#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA2(x)     (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA2_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA2_MASK)

#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA3_MASK   (0x8U)
#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA3_SHIFT  (3U)
/*! REQ_ENA3 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register.
 */
#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA3(x)     (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA3_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA3_MASK)

#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA4_MASK   (0x10U)
#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA4_SHIFT  (4U)
/*! REQ_ENA4 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register.
 */
#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA4(x)     (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA4_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA4_MASK)

#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA5_MASK   (0x20U)
#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA5_SHIFT  (5U)
/*! REQ_ENA5 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register.
 */
#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA5(x)     (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA5_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA5_MASK)

#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA6_MASK   (0x40U)
#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA6_SHIFT  (6U)
/*! REQ_ENA6 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register.
 */
#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA6(x)     (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA6_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA6_MASK)

#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA7_MASK   (0x80U)
#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA7_SHIFT  (7U)
/*! REQ_ENA7 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register.
 */
#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA7(x)     (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA7_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA7_MASK)

#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA8_MASK   (0x100U)
#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA8_SHIFT  (8U)
/*! REQ_ENA8 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register.
 */
#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA8(x)     (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA8_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA8_MASK)

#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA9_MASK   (0x200U)
#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA9_SHIFT  (9U)
/*! REQ_ENA9 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register.
 */
#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA9(x)     (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA9_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA9_MASK)

#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA10_MASK  (0x400U)
#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA10_SHIFT (10U)
/*! REQ_ENA10 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register.
 */
#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA10(x)    (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA10_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA10_MASK)

#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA11_MASK  (0x800U)
#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA11_SHIFT (11U)
/*! REQ_ENA11 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register.
 */
#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA11(x)    (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA11_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA11_MASK)

#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA12_MASK  (0x1000U)
#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA12_SHIFT (12U)
/*! REQ_ENA12 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register.
 */
#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA12(x)    (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA12_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA12_MASK)

#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA13_MASK  (0x2000U)
#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA13_SHIFT (13U)
/*! REQ_ENA13 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register.
 */
#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA13(x)    (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA13_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA13_MASK)

#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA14_MASK  (0x4000U)
#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA14_SHIFT (14U)
/*! REQ_ENA14 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register.
 */
#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA14(x)    (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA14_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA14_MASK)

#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA15_MASK  (0x8000U)
#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA15_SHIFT (15U)
/*! REQ_ENA15 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register.
 */
#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA15(x)    (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA15_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA15_MASK)

#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA16_MASK  (0x10000U)
#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA16_SHIFT (16U)
/*! REQ_ENA16 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register.
 */
#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA16(x)    (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA16_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA16_MASK)

#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA17_MASK  (0x20000U)
#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA17_SHIFT (17U)
/*! REQ_ENA17 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register.
 */
#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA17(x)    (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA17_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA17_MASK)

#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA18_MASK  (0x40000U)
#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA18_SHIFT (18U)
/*! REQ_ENA18 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register.
 */
#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA18(x)    (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA18_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA18_MASK)

#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA19_MASK  (0x80000U)
#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA19_SHIFT (19U)
/*! REQ_ENA19 - Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , no change in DMA0_REQEN1 register.
 */
#define INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA19(x)    (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA19_SHIFT)) & INPUTMUX_DMA0_REQEN1_CLR_REQ_ENA19_MASK)
/*! @} */

/*! @name DMA1_REQEN - Enable DMA1 requests */
/*! @{ */

#define INPUTMUX_DMA1_REQEN_REQ_ENA0_MASK        (0x1U)
#define INPUTMUX_DMA1_REQEN_REQ_ENA0_SHIFT       (0U)
/*! REQ_ENA0 - Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled.
 */
#define INPUTMUX_DMA1_REQEN_REQ_ENA0(x)          (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_REQ_ENA0_SHIFT)) & INPUTMUX_DMA1_REQEN_REQ_ENA0_MASK)

#define INPUTMUX_DMA1_REQEN_REQ_ENA1_MASK        (0x2U)
#define INPUTMUX_DMA1_REQEN_REQ_ENA1_SHIFT       (1U)
/*! REQ_ENA1 - Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled.
 */
#define INPUTMUX_DMA1_REQEN_REQ_ENA1(x)          (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_REQ_ENA1_SHIFT)) & INPUTMUX_DMA1_REQEN_REQ_ENA1_MASK)

#define INPUTMUX_DMA1_REQEN_REQ_ENA2_MASK        (0x4U)
#define INPUTMUX_DMA1_REQEN_REQ_ENA2_SHIFT       (2U)
/*! REQ_ENA2 - Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled.
 */
#define INPUTMUX_DMA1_REQEN_REQ_ENA2(x)          (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_REQ_ENA2_SHIFT)) & INPUTMUX_DMA1_REQEN_REQ_ENA2_MASK)

#define INPUTMUX_DMA1_REQEN_REQ_ENA3_MASK        (0x8U)
#define INPUTMUX_DMA1_REQEN_REQ_ENA3_SHIFT       (3U)
/*! REQ_ENA3 - Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled.
 */
#define INPUTMUX_DMA1_REQEN_REQ_ENA3(x)          (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_REQ_ENA3_SHIFT)) & INPUTMUX_DMA1_REQEN_REQ_ENA3_MASK)

#define INPUTMUX_DMA1_REQEN_REQ_ENA4_MASK        (0x10U)
#define INPUTMUX_DMA1_REQEN_REQ_ENA4_SHIFT       (4U)
/*! REQ_ENA4 - Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled.
 */
#define INPUTMUX_DMA1_REQEN_REQ_ENA4(x)          (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_REQ_ENA4_SHIFT)) & INPUTMUX_DMA1_REQEN_REQ_ENA4_MASK)

#define INPUTMUX_DMA1_REQEN_REQ_ENA5_MASK        (0x20U)
#define INPUTMUX_DMA1_REQEN_REQ_ENA5_SHIFT       (5U)
/*! REQ_ENA5 - Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled.
 */
#define INPUTMUX_DMA1_REQEN_REQ_ENA5(x)          (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_REQ_ENA5_SHIFT)) & INPUTMUX_DMA1_REQEN_REQ_ENA5_MASK)

#define INPUTMUX_DMA1_REQEN_REQ_ENA6_MASK        (0x40U)
#define INPUTMUX_DMA1_REQEN_REQ_ENA6_SHIFT       (6U)
/*! REQ_ENA6 - Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled.
 */
#define INPUTMUX_DMA1_REQEN_REQ_ENA6(x)          (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_REQ_ENA6_SHIFT)) & INPUTMUX_DMA1_REQEN_REQ_ENA6_MASK)

#define INPUTMUX_DMA1_REQEN_REQ_ENA7_MASK        (0x80U)
#define INPUTMUX_DMA1_REQEN_REQ_ENA7_SHIFT       (7U)
/*! REQ_ENA7 - Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled.
 */
#define INPUTMUX_DMA1_REQEN_REQ_ENA7(x)          (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_REQ_ENA7_SHIFT)) & INPUTMUX_DMA1_REQEN_REQ_ENA7_MASK)

#define INPUTMUX_DMA1_REQEN_REQ_ENA8_MASK        (0x100U)
#define INPUTMUX_DMA1_REQEN_REQ_ENA8_SHIFT       (8U)
/*! REQ_ENA8 - Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled.
 */
#define INPUTMUX_DMA1_REQEN_REQ_ENA8(x)          (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_REQ_ENA8_SHIFT)) & INPUTMUX_DMA1_REQEN_REQ_ENA8_MASK)

#define INPUTMUX_DMA1_REQEN_REQ_ENA9_MASK        (0x200U)
#define INPUTMUX_DMA1_REQEN_REQ_ENA9_SHIFT       (9U)
/*! REQ_ENA9 - Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled.
 */
#define INPUTMUX_DMA1_REQEN_REQ_ENA9(x)          (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_REQ_ENA9_SHIFT)) & INPUTMUX_DMA1_REQEN_REQ_ENA9_MASK)

#define INPUTMUX_DMA1_REQEN_REQ_ENA10_MASK       (0x400U)
#define INPUTMUX_DMA1_REQEN_REQ_ENA10_SHIFT      (10U)
/*! REQ_ENA10 - Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled.
 */
#define INPUTMUX_DMA1_REQEN_REQ_ENA10(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_REQ_ENA10_SHIFT)) & INPUTMUX_DMA1_REQEN_REQ_ENA10_MASK)

#define INPUTMUX_DMA1_REQEN_REQ_ENA11_MASK       (0x800U)
#define INPUTMUX_DMA1_REQEN_REQ_ENA11_SHIFT      (11U)
/*! REQ_ENA11 - Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled.
 */
#define INPUTMUX_DMA1_REQEN_REQ_ENA11(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_REQ_ENA11_SHIFT)) & INPUTMUX_DMA1_REQEN_REQ_ENA11_MASK)

#define INPUTMUX_DMA1_REQEN_REQ_ENA12_MASK       (0x1000U)
#define INPUTMUX_DMA1_REQEN_REQ_ENA12_SHIFT      (12U)
/*! REQ_ENA12 - Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled.
 */
#define INPUTMUX_DMA1_REQEN_REQ_ENA12(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_REQ_ENA12_SHIFT)) & INPUTMUX_DMA1_REQEN_REQ_ENA12_MASK)

#define INPUTMUX_DMA1_REQEN_REQ_ENA13_MASK       (0x2000U)
#define INPUTMUX_DMA1_REQEN_REQ_ENA13_SHIFT      (13U)
/*! REQ_ENA13 - Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled.
 */
#define INPUTMUX_DMA1_REQEN_REQ_ENA13(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_REQ_ENA13_SHIFT)) & INPUTMUX_DMA1_REQEN_REQ_ENA13_MASK)

#define INPUTMUX_DMA1_REQEN_REQ_ENA14_MASK       (0x4000U)
#define INPUTMUX_DMA1_REQEN_REQ_ENA14_SHIFT      (14U)
/*! REQ_ENA14 - Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled.
 */
#define INPUTMUX_DMA1_REQEN_REQ_ENA14(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_REQ_ENA14_SHIFT)) & INPUTMUX_DMA1_REQEN_REQ_ENA14_MASK)

#define INPUTMUX_DMA1_REQEN_REQ_ENA15_MASK       (0x8000U)
#define INPUTMUX_DMA1_REQEN_REQ_ENA15_SHIFT      (15U)
/*! REQ_ENA15 - Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled.
 */
#define INPUTMUX_DMA1_REQEN_REQ_ENA15(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_REQ_ENA15_SHIFT)) & INPUTMUX_DMA1_REQEN_REQ_ENA15_MASK)
/*! @} */

/*! @name DMA1_REQEN_SET - Set bits in DMA1_REQEN register */
/*! @{ */

#define INPUTMUX_DMA1_REQEN_SET_SET0_MASK        (0x1U)
#define INPUTMUX_DMA1_REQEN_SET_SET0_SHIFT       (0U)
/*! SET0 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no change in DMA1_REQEN register
 */
#define INPUTMUX_DMA1_REQEN_SET_SET0(x)          (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_SET_SET0_SHIFT)) & INPUTMUX_DMA1_REQEN_SET_SET0_MASK)

#define INPUTMUX_DMA1_REQEN_SET_SET1_MASK        (0x2U)
#define INPUTMUX_DMA1_REQEN_SET_SET1_SHIFT       (1U)
/*! SET1 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no change in DMA1_REQEN register
 */
#define INPUTMUX_DMA1_REQEN_SET_SET1(x)          (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_SET_SET1_SHIFT)) & INPUTMUX_DMA1_REQEN_SET_SET1_MASK)

#define INPUTMUX_DMA1_REQEN_SET_SET2_MASK        (0x4U)
#define INPUTMUX_DMA1_REQEN_SET_SET2_SHIFT       (2U)
/*! SET2 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no change in DMA1_REQEN register
 */
#define INPUTMUX_DMA1_REQEN_SET_SET2(x)          (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_SET_SET2_SHIFT)) & INPUTMUX_DMA1_REQEN_SET_SET2_MASK)

#define INPUTMUX_DMA1_REQEN_SET_SET3_MASK        (0x8U)
#define INPUTMUX_DMA1_REQEN_SET_SET3_SHIFT       (3U)
/*! SET3 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no change in DMA1_REQEN register
 */
#define INPUTMUX_DMA1_REQEN_SET_SET3(x)          (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_SET_SET3_SHIFT)) & INPUTMUX_DMA1_REQEN_SET_SET3_MASK)

#define INPUTMUX_DMA1_REQEN_SET_SET4_MASK        (0x10U)
#define INPUTMUX_DMA1_REQEN_SET_SET4_SHIFT       (4U)
/*! SET4 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no change in DMA1_REQEN register
 */
#define INPUTMUX_DMA1_REQEN_SET_SET4(x)          (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_SET_SET4_SHIFT)) & INPUTMUX_DMA1_REQEN_SET_SET4_MASK)

#define INPUTMUX_DMA1_REQEN_SET_SET5_MASK        (0x20U)
#define INPUTMUX_DMA1_REQEN_SET_SET5_SHIFT       (5U)
/*! SET5 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no change in DMA1_REQEN register
 */
#define INPUTMUX_DMA1_REQEN_SET_SET5(x)          (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_SET_SET5_SHIFT)) & INPUTMUX_DMA1_REQEN_SET_SET5_MASK)

#define INPUTMUX_DMA1_REQEN_SET_SET6_MASK        (0x40U)
#define INPUTMUX_DMA1_REQEN_SET_SET6_SHIFT       (6U)
/*! SET6 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no change in DMA1_REQEN register
 */
#define INPUTMUX_DMA1_REQEN_SET_SET6(x)          (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_SET_SET6_SHIFT)) & INPUTMUX_DMA1_REQEN_SET_SET6_MASK)

#define INPUTMUX_DMA1_REQEN_SET_SET7_MASK        (0x80U)
#define INPUTMUX_DMA1_REQEN_SET_SET7_SHIFT       (7U)
/*! SET7 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no change in DMA1_REQEN register
 */
#define INPUTMUX_DMA1_REQEN_SET_SET7(x)          (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_SET_SET7_SHIFT)) & INPUTMUX_DMA1_REQEN_SET_SET7_MASK)

#define INPUTMUX_DMA1_REQEN_SET_SET8_MASK        (0x100U)
#define INPUTMUX_DMA1_REQEN_SET_SET8_SHIFT       (8U)
/*! SET8 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no change in DMA1_REQEN register
 */
#define INPUTMUX_DMA1_REQEN_SET_SET8(x)          (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_SET_SET8_SHIFT)) & INPUTMUX_DMA1_REQEN_SET_SET8_MASK)

#define INPUTMUX_DMA1_REQEN_SET_SET9_MASK        (0x200U)
#define INPUTMUX_DMA1_REQEN_SET_SET9_SHIFT       (9U)
/*! SET9 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no change in DMA1_REQEN register
 */
#define INPUTMUX_DMA1_REQEN_SET_SET9(x)          (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_SET_SET9_SHIFT)) & INPUTMUX_DMA1_REQEN_SET_SET9_MASK)

#define INPUTMUX_DMA1_REQEN_SET_SET10_MASK       (0x400U)
#define INPUTMUX_DMA1_REQEN_SET_SET10_SHIFT      (10U)
/*! SET10 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no change in DMA1_REQEN register
 */
#define INPUTMUX_DMA1_REQEN_SET_SET10(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_SET_SET10_SHIFT)) & INPUTMUX_DMA1_REQEN_SET_SET10_MASK)

#define INPUTMUX_DMA1_REQEN_SET_SET11_MASK       (0x800U)
#define INPUTMUX_DMA1_REQEN_SET_SET11_SHIFT      (11U)
/*! SET11 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no change in DMA1_REQEN register
 */
#define INPUTMUX_DMA1_REQEN_SET_SET11(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_SET_SET11_SHIFT)) & INPUTMUX_DMA1_REQEN_SET_SET11_MASK)

#define INPUTMUX_DMA1_REQEN_SET_SET12_MASK       (0x1000U)
#define INPUTMUX_DMA1_REQEN_SET_SET12_SHIFT      (12U)
/*! SET12 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no change in DMA1_REQEN register
 */
#define INPUTMUX_DMA1_REQEN_SET_SET12(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_SET_SET12_SHIFT)) & INPUTMUX_DMA1_REQEN_SET_SET12_MASK)

#define INPUTMUX_DMA1_REQEN_SET_SET13_MASK       (0x2000U)
#define INPUTMUX_DMA1_REQEN_SET_SET13_SHIFT      (13U)
/*! SET13 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no change in DMA1_REQEN register
 */
#define INPUTMUX_DMA1_REQEN_SET_SET13(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_SET_SET13_SHIFT)) & INPUTMUX_DMA1_REQEN_SET_SET13_MASK)

#define INPUTMUX_DMA1_REQEN_SET_SET14_MASK       (0x4000U)
#define INPUTMUX_DMA1_REQEN_SET_SET14_SHIFT      (14U)
/*! SET14 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no change in DMA1_REQEN register
 */
#define INPUTMUX_DMA1_REQEN_SET_SET14(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_SET_SET14_SHIFT)) & INPUTMUX_DMA1_REQEN_SET_SET14_MASK)

#define INPUTMUX_DMA1_REQEN_SET_SET15_MASK       (0x8000U)
#define INPUTMUX_DMA1_REQEN_SET_SET15_SHIFT      (15U)
/*! SET15 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no change in DMA1_REQEN register
 */
#define INPUTMUX_DMA1_REQEN_SET_SET15(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_SET_SET15_SHIFT)) & INPUTMUX_DMA1_REQEN_SET_SET15_MASK)
/*! @} */

/*! @name DMA1_REQEN_CLR - Clear bits in DMA1_REQEN register */
/*! @{ */

#define INPUTMUX_DMA1_REQEN_CLR_CLR0_MASK        (0x1U)
#define INPUTMUX_DMA1_REQEN_CLR_CLR0_SHIFT       (0U)
/*! CLR0 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , no change in DMA1_REQEN register
 */
#define INPUTMUX_DMA1_REQEN_CLR_CLR0(x)          (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_CLR_CLR0_SHIFT)) & INPUTMUX_DMA1_REQEN_CLR_CLR0_MASK)

#define INPUTMUX_DMA1_REQEN_CLR_CLR1_MASK        (0x2U)
#define INPUTMUX_DMA1_REQEN_CLR_CLR1_SHIFT       (1U)
/*! CLR1 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , no change in DMA1_REQEN register
 */
#define INPUTMUX_DMA1_REQEN_CLR_CLR1(x)          (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_CLR_CLR1_SHIFT)) & INPUTMUX_DMA1_REQEN_CLR_CLR1_MASK)

#define INPUTMUX_DMA1_REQEN_CLR_CLR2_MASK        (0x4U)
#define INPUTMUX_DMA1_REQEN_CLR_CLR2_SHIFT       (2U)
/*! CLR2 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , no change in DMA1_REQEN register
 */
#define INPUTMUX_DMA1_REQEN_CLR_CLR2(x)          (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_CLR_CLR2_SHIFT)) & INPUTMUX_DMA1_REQEN_CLR_CLR2_MASK)

#define INPUTMUX_DMA1_REQEN_CLR_CLR3_MASK        (0x8U)
#define INPUTMUX_DMA1_REQEN_CLR_CLR3_SHIFT       (3U)
/*! CLR3 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , no change in DMA1_REQEN register
 */
#define INPUTMUX_DMA1_REQEN_CLR_CLR3(x)          (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_CLR_CLR3_SHIFT)) & INPUTMUX_DMA1_REQEN_CLR_CLR3_MASK)

#define INPUTMUX_DMA1_REQEN_CLR_CLR4_MASK        (0x10U)
#define INPUTMUX_DMA1_REQEN_CLR_CLR4_SHIFT       (4U)
/*! CLR4 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , no change in DMA1_REQEN register
 */
#define INPUTMUX_DMA1_REQEN_CLR_CLR4(x)          (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_CLR_CLR4_SHIFT)) & INPUTMUX_DMA1_REQEN_CLR_CLR4_MASK)

#define INPUTMUX_DMA1_REQEN_CLR_CLR5_MASK        (0x20U)
#define INPUTMUX_DMA1_REQEN_CLR_CLR5_SHIFT       (5U)
/*! CLR5 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , no change in DMA1_REQEN register
 */
#define INPUTMUX_DMA1_REQEN_CLR_CLR5(x)          (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_CLR_CLR5_SHIFT)) & INPUTMUX_DMA1_REQEN_CLR_CLR5_MASK)

#define INPUTMUX_DMA1_REQEN_CLR_CLR6_MASK        (0x40U)
#define INPUTMUX_DMA1_REQEN_CLR_CLR6_SHIFT       (6U)
/*! CLR6 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , no change in DMA1_REQEN register
 */
#define INPUTMUX_DMA1_REQEN_CLR_CLR6(x)          (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_CLR_CLR6_SHIFT)) & INPUTMUX_DMA1_REQEN_CLR_CLR6_MASK)

#define INPUTMUX_DMA1_REQEN_CLR_CLR7_MASK        (0x80U)
#define INPUTMUX_DMA1_REQEN_CLR_CLR7_SHIFT       (7U)
/*! CLR7 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , no change in DMA1_REQEN register
 */
#define INPUTMUX_DMA1_REQEN_CLR_CLR7(x)          (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_CLR_CLR7_SHIFT)) & INPUTMUX_DMA1_REQEN_CLR_CLR7_MASK)

#define INPUTMUX_DMA1_REQEN_CLR_CLR8_MASK        (0x100U)
#define INPUTMUX_DMA1_REQEN_CLR_CLR8_SHIFT       (8U)
/*! CLR8 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , no change in DMA1_REQEN register
 */
#define INPUTMUX_DMA1_REQEN_CLR_CLR8(x)          (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_CLR_CLR8_SHIFT)) & INPUTMUX_DMA1_REQEN_CLR_CLR8_MASK)

#define INPUTMUX_DMA1_REQEN_CLR_CLR9_MASK        (0x200U)
#define INPUTMUX_DMA1_REQEN_CLR_CLR9_SHIFT       (9U)
/*! CLR9 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , no change in DMA1_REQEN register
 */
#define INPUTMUX_DMA1_REQEN_CLR_CLR9(x)          (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_CLR_CLR9_SHIFT)) & INPUTMUX_DMA1_REQEN_CLR_CLR9_MASK)

#define INPUTMUX_DMA1_REQEN_CLR_CLR10_MASK       (0x400U)
#define INPUTMUX_DMA1_REQEN_CLR_CLR10_SHIFT      (10U)
/*! CLR10 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , no change in DMA1_REQEN register
 */
#define INPUTMUX_DMA1_REQEN_CLR_CLR10(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_CLR_CLR10_SHIFT)) & INPUTMUX_DMA1_REQEN_CLR_CLR10_MASK)

#define INPUTMUX_DMA1_REQEN_CLR_CLR11_MASK       (0x800U)
#define INPUTMUX_DMA1_REQEN_CLR_CLR11_SHIFT      (11U)
/*! CLR11 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , no change in DMA1_REQEN register
 */
#define INPUTMUX_DMA1_REQEN_CLR_CLR11(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_CLR_CLR11_SHIFT)) & INPUTMUX_DMA1_REQEN_CLR_CLR11_MASK)

#define INPUTMUX_DMA1_REQEN_CLR_CLR12_MASK       (0x1000U)
#define INPUTMUX_DMA1_REQEN_CLR_CLR12_SHIFT      (12U)
/*! CLR12 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , no change in DMA1_REQEN register
 */
#define INPUTMUX_DMA1_REQEN_CLR_CLR12(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_CLR_CLR12_SHIFT)) & INPUTMUX_DMA1_REQEN_CLR_CLR12_MASK)

#define INPUTMUX_DMA1_REQEN_CLR_CLR13_MASK       (0x2000U)
#define INPUTMUX_DMA1_REQEN_CLR_CLR13_SHIFT      (13U)
/*! CLR13 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , no change in DMA1_REQEN register
 */
#define INPUTMUX_DMA1_REQEN_CLR_CLR13(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_CLR_CLR13_SHIFT)) & INPUTMUX_DMA1_REQEN_CLR_CLR13_MASK)

#define INPUTMUX_DMA1_REQEN_CLR_CLR14_MASK       (0x4000U)
#define INPUTMUX_DMA1_REQEN_CLR_CLR14_SHIFT      (14U)
/*! CLR14 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , no change in DMA1_REQEN register
 */
#define INPUTMUX_DMA1_REQEN_CLR_CLR14(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_CLR_CLR14_SHIFT)) & INPUTMUX_DMA1_REQEN_CLR_CLR14_MASK)

#define INPUTMUX_DMA1_REQEN_CLR_CLR15_MASK       (0x8000U)
#define INPUTMUX_DMA1_REQEN_CLR_CLR15_SHIFT      (15U)
/*! CLR15 - Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , no change in DMA1_REQEN register
 */
#define INPUTMUX_DMA1_REQEN_CLR_CLR15(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQEN_CLR_CLR15_SHIFT)) & INPUTMUX_DMA1_REQEN_CLR_CLR15_MASK)
/*! @} */

/*! @name DMA0_ITRIGEN0 - Enable DMA0 triggers */
/*! @{ */

#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN0_MASK     (0x1U)
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN0_SHIFT    (0U)
/*! ITRIGEN0 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled.
 */
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN0(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN0_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN0_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN1_MASK     (0x2U)
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN1_SHIFT    (1U)
/*! ITRIGEN1 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled.
 */
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN1(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN1_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN1_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN2_MASK     (0x4U)
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN2_SHIFT    (2U)
/*! ITRIGEN2 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled.
 */
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN2(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN2_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN2_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN3_MASK     (0x8U)
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN3_SHIFT    (3U)
/*! ITRIGEN3 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled.
 */
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN3(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN3_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN3_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN4_MASK     (0x10U)
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN4_SHIFT    (4U)
/*! ITRIGEN4 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled.
 */
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN4(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN4_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN4_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN5_MASK     (0x20U)
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN5_SHIFT    (5U)
/*! ITRIGEN5 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled.
 */
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN5(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN5_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN5_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN6_MASK     (0x40U)
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN6_SHIFT    (6U)
/*! ITRIGEN6 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled.
 */
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN6(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN6_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN6_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN7_MASK     (0x80U)
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN7_SHIFT    (7U)
/*! ITRIGEN7 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled.
 */
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN7(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN7_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN7_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN8_MASK     (0x100U)
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN8_SHIFT    (8U)
/*! ITRIGEN8 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled.
 */
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN8(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN8_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN8_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN9_MASK     (0x200U)
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN9_SHIFT    (9U)
/*! ITRIGEN9 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled.
 */
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN9(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN9_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN9_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN10_MASK    (0x400U)
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN10_SHIFT   (10U)
/*! ITRIGEN10 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled.
 */
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN10(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN10_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN10_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN11_MASK    (0x800U)
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN11_SHIFT   (11U)
/*! ITRIGEN11 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled.
 */
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN11(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN11_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN11_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN12_MASK    (0x1000U)
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN12_SHIFT   (12U)
/*! ITRIGEN12 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled.
 */
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN12(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN12_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN12_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN13_MASK    (0x2000U)
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN13_SHIFT   (13U)
/*! ITRIGEN13 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled.
 */
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN13(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN13_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN13_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN14_MASK    (0x4000U)
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN14_SHIFT   (14U)
/*! ITRIGEN14 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled.
 */
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN14(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN14_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN14_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN15_MASK    (0x8000U)
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN15_SHIFT   (15U)
/*! ITRIGEN15 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled.
 */
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN15(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN15_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN15_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN16_MASK    (0x10000U)
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN16_SHIFT   (16U)
/*! ITRIGEN16 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled.
 */
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN16(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN16_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN16_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN17_MASK    (0x20000U)
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN17_SHIFT   (17U)
/*! ITRIGEN17 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled.
 */
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN17(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN17_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN17_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN18_MASK    (0x40000U)
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN18_SHIFT   (18U)
/*! ITRIGEN18 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled.
 */
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN18(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN18_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN18_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN19_MASK    (0x80000U)
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN19_SHIFT   (19U)
/*! ITRIGEN19 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled.
 */
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN19(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN19_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN19_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN20_MASK    (0x100000U)
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN20_SHIFT   (20U)
/*! ITRIGEN20 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled.
 */
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN20(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN20_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN20_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN21_MASK    (0x200000U)
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN21_SHIFT   (21U)
/*! ITRIGEN21 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled.
 */
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN21(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN21_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN21_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN22_MASK    (0x400000U)
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN22_SHIFT   (22U)
/*! ITRIGEN22 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled.
 */
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN22(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN22_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN22_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN23_MASK    (0x800000U)
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN23_SHIFT   (23U)
/*! ITRIGEN23 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled.
 */
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN23(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN23_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN23_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN24_MASK    (0x1000000U)
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN24_SHIFT   (24U)
/*! ITRIGEN24 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled.
 */
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN24(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN24_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN24_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN25_MASK    (0x2000000U)
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN25_SHIFT   (25U)
/*! ITRIGEN25 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled.
 */
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN25(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN25_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN25_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN26_MASK    (0x4000000U)
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN26_SHIFT   (26U)
/*! ITRIGEN26 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled.
 */
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN26(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN26_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN26_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN27_MASK    (0x8000000U)
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN27_SHIFT   (27U)
/*! ITRIGEN27 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled.
 */
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN27(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN27_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN27_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN28_MASK    (0x10000000U)
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN28_SHIFT   (28U)
/*! ITRIGEN28 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled.
 */
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN28(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN28_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN28_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN29_MASK    (0x20000000U)
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN29_SHIFT   (29U)
/*! ITRIGEN29 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled.
 */
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN29(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN29_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN29_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN30_MASK    (0x40000000U)
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN30_SHIFT   (30U)
/*! ITRIGEN30 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled.
 */
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN30(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN30_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN30_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN31_MASK    (0x80000000U)
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN31_SHIFT   (31U)
/*! ITRIGEN31 - Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled.
 */
#define INPUTMUX_DMA0_ITRIGEN0_ITRIGEN31(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_ITRIGEN31_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_ITRIGEN31_MASK)
/*! @} */

/*! @name DMA0_ITRIGEN1 - Enable DMA0 triggers */
/*! @{ */

#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN0_MASK     (0x1U)
#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN0_SHIFT    (0U)
/*! ITRIGEN0 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled.
 */
#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN0(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN0_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN0_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN1_MASK     (0x2U)
#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN1_SHIFT    (1U)
/*! ITRIGEN1 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled.
 */
#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN1(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN1_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN1_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN2_MASK     (0x4U)
#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN2_SHIFT    (2U)
/*! ITRIGEN2 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled.
 */
#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN2(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN2_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN2_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN3_MASK     (0x8U)
#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN3_SHIFT    (3U)
/*! ITRIGEN3 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled.
 */
#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN3(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN3_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN3_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN4_MASK     (0x10U)
#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN4_SHIFT    (4U)
/*! ITRIGEN4 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled.
 */
#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN4(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN4_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN4_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN5_MASK     (0x20U)
#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN5_SHIFT    (5U)
/*! ITRIGEN5 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled.
 */
#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN5(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN5_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN5_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN6_MASK     (0x40U)
#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN6_SHIFT    (6U)
/*! ITRIGEN6 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled.
 */
#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN6(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN6_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN6_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN7_MASK     (0x80U)
#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN7_SHIFT    (7U)
/*! ITRIGEN7 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled.
 */
#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN7(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN7_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN7_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN8_MASK     (0x100U)
#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN8_SHIFT    (8U)
/*! ITRIGEN8 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled.
 */
#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN8(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN8_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN8_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN9_MASK     (0x200U)
#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN9_SHIFT    (9U)
/*! ITRIGEN9 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled.
 */
#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN9(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN9_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN9_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN10_MASK    (0x400U)
#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN10_SHIFT   (10U)
/*! ITRIGEN10 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled.
 */
#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN10(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN10_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN10_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN11_MASK    (0x800U)
#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN11_SHIFT   (11U)
/*! ITRIGEN11 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled.
 */
#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN11(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN11_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN11_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN12_MASK    (0x1000U)
#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN12_SHIFT   (12U)
/*! ITRIGEN12 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled.
 */
#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN12(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN12_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN12_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN13_MASK    (0x2000U)
#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN13_SHIFT   (13U)
/*! ITRIGEN13 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled.
 */
#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN13(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN13_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN13_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN14_MASK    (0x4000U)
#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN14_SHIFT   (14U)
/*! ITRIGEN14 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled.
 */
#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN14(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN14_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN14_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN15_MASK    (0x8000U)
#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN15_SHIFT   (15U)
/*! ITRIGEN15 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled.
 */
#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN15(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN15_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN15_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN16_MASK    (0x10000U)
#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN16_SHIFT   (16U)
/*! ITRIGEN16 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled.
 */
#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN16(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN16_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN16_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN17_MASK    (0x20000U)
#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN17_SHIFT   (17U)
/*! ITRIGEN17 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled.
 */
#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN17(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN17_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN17_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN18_MASK    (0x40000U)
#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN18_SHIFT   (18U)
/*! ITRIGEN18 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled.
 */
#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN18(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN18_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN18_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN19_MASK    (0x80000U)
#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN19_SHIFT   (19U)
/*! ITRIGEN19 - Controls the remaining 20 trigger inputs of DMA0. If bit n is '1' the DMA trigger input #(n+32) is enabled.
 */
#define INPUTMUX_DMA0_ITRIGEN1_ITRIGEN19(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_ITRIGEN19_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_ITRIGEN19_MASK)
/*! @} */

/*! @name DMA0_ITRIGEN0_SET - Set bits in DMA0_ITRIGEN0 register */
/*! @{ */

#define INPUTMUX_DMA0_ITRIGEN0_SET_SET0_MASK     (0x1U)
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET0_SHIFT    (0U)
/*! SET0 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET0(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET0_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET0_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_SET_SET1_MASK     (0x2U)
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET1_SHIFT    (1U)
/*! SET1 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET1(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET1_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET1_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_SET_SET2_MASK     (0x4U)
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET2_SHIFT    (2U)
/*! SET2 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET2(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET2_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET2_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_SET_SET3_MASK     (0x8U)
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET3_SHIFT    (3U)
/*! SET3 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET3(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET3_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET3_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_SET_SET4_MASK     (0x10U)
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET4_SHIFT    (4U)
/*! SET4 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET4(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET4_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET4_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_SET_SET5_MASK     (0x20U)
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET5_SHIFT    (5U)
/*! SET5 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET5(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET5_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET5_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_SET_SET6_MASK     (0x40U)
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET6_SHIFT    (6U)
/*! SET6 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET6(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET6_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET6_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_SET_SET7_MASK     (0x80U)
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET7_SHIFT    (7U)
/*! SET7 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET7(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET7_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET7_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_SET_SET8_MASK     (0x100U)
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET8_SHIFT    (8U)
/*! SET8 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET8(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET8_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET8_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_SET_SET9_MASK     (0x200U)
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET9_SHIFT    (9U)
/*! SET9 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET9(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET9_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET9_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_SET_SET10_MASK    (0x400U)
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET10_SHIFT   (10U)
/*! SET10 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET10(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET10_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET10_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_SET_SET11_MASK    (0x800U)
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET11_SHIFT   (11U)
/*! SET11 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET11(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET11_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET11_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_SET_SET12_MASK    (0x1000U)
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET12_SHIFT   (12U)
/*! SET12 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET12(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET12_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET12_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_SET_SET13_MASK    (0x2000U)
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET13_SHIFT   (13U)
/*! SET13 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET13(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET13_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET13_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_SET_SET14_MASK    (0x4000U)
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET14_SHIFT   (14U)
/*! SET14 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET14(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET14_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET14_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_SET_SET15_MASK    (0x8000U)
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET15_SHIFT   (15U)
/*! SET15 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET15(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET15_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET15_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_SET_SET16_MASK    (0x10000U)
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET16_SHIFT   (16U)
/*! SET16 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET16(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET16_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET16_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_SET_SET17_MASK    (0x20000U)
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET17_SHIFT   (17U)
/*! SET17 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET17(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET17_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET17_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_SET_SET18_MASK    (0x40000U)
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET18_SHIFT   (18U)
/*! SET18 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET18(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET18_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET18_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_SET_SET19_MASK    (0x80000U)
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET19_SHIFT   (19U)
/*! SET19 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET19(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET19_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET19_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_SET_SET20_MASK    (0x100000U)
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET20_SHIFT   (20U)
/*! SET20 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET20(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET20_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET20_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_SET_SET21_MASK    (0x200000U)
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET21_SHIFT   (21U)
/*! SET21 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET21(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET21_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET21_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_SET_SET22_MASK    (0x400000U)
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET22_SHIFT   (22U)
/*! SET22 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET22(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET22_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET22_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_SET_SET23_MASK    (0x800000U)
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET23_SHIFT   (23U)
/*! SET23 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET23(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET23_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET23_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_SET_SET24_MASK    (0x1000000U)
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET24_SHIFT   (24U)
/*! SET24 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET24(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET24_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET24_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_SET_SET25_MASK    (0x2000000U)
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET25_SHIFT   (25U)
/*! SET25 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET25(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET25_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET25_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_SET_SET26_MASK    (0x4000000U)
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET26_SHIFT   (26U)
/*! SET26 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET26(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET26_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET26_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_SET_SET27_MASK    (0x8000000U)
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET27_SHIFT   (27U)
/*! SET27 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET27(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET27_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET27_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_SET_SET28_MASK    (0x10000000U)
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET28_SHIFT   (28U)
/*! SET28 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET28(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET28_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET28_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_SET_SET29_MASK    (0x20000000U)
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET29_SHIFT   (29U)
/*! SET29 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET29(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET29_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET29_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_SET_SET30_MASK    (0x40000000U)
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET30_SHIFT   (30U)
/*! SET30 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET30(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET30_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET30_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_SET_SET31_MASK    (0x80000000U)
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET31_SHIFT   (31U)
/*! SET31 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_SET_SET31(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_SET_SET31_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_SET_SET31_MASK)
/*! @} */

/*! @name DMA0_ITRIGEN1_SET - Set bits in DMA0_ITRIGEN1 register */
/*! @{ */

#define INPUTMUX_DMA0_ITRIGEN1_SET_SET0_MASK     (0x1U)
#define INPUTMUX_DMA0_ITRIGEN1_SET_SET0_SHIFT    (0U)
/*! SET0 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN1 register.
 */
#define INPUTMUX_DMA0_ITRIGEN1_SET_SET0(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET0_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET0_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_SET_SET1_MASK     (0x2U)
#define INPUTMUX_DMA0_ITRIGEN1_SET_SET1_SHIFT    (1U)
/*! SET1 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN1 register.
 */
#define INPUTMUX_DMA0_ITRIGEN1_SET_SET1(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET1_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET1_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_SET_SET2_MASK     (0x4U)
#define INPUTMUX_DMA0_ITRIGEN1_SET_SET2_SHIFT    (2U)
/*! SET2 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN1 register.
 */
#define INPUTMUX_DMA0_ITRIGEN1_SET_SET2(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET2_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET2_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_SET_SET3_MASK     (0x8U)
#define INPUTMUX_DMA0_ITRIGEN1_SET_SET3_SHIFT    (3U)
/*! SET3 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN1 register.
 */
#define INPUTMUX_DMA0_ITRIGEN1_SET_SET3(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET3_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET3_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_SET_SET4_MASK     (0x10U)
#define INPUTMUX_DMA0_ITRIGEN1_SET_SET4_SHIFT    (4U)
/*! SET4 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN1 register.
 */
#define INPUTMUX_DMA0_ITRIGEN1_SET_SET4(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET4_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET4_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_SET_SET5_MASK     (0x20U)
#define INPUTMUX_DMA0_ITRIGEN1_SET_SET5_SHIFT    (5U)
/*! SET5 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN1 register.
 */
#define INPUTMUX_DMA0_ITRIGEN1_SET_SET5(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET5_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET5_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_SET_SET6_MASK     (0x40U)
#define INPUTMUX_DMA0_ITRIGEN1_SET_SET6_SHIFT    (6U)
/*! SET6 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN1 register.
 */
#define INPUTMUX_DMA0_ITRIGEN1_SET_SET6(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET6_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET6_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_SET_SET7_MASK     (0x80U)
#define INPUTMUX_DMA0_ITRIGEN1_SET_SET7_SHIFT    (7U)
/*! SET7 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN1 register.
 */
#define INPUTMUX_DMA0_ITRIGEN1_SET_SET7(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET7_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET7_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_SET_SET8_MASK     (0x100U)
#define INPUTMUX_DMA0_ITRIGEN1_SET_SET8_SHIFT    (8U)
/*! SET8 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN1 register.
 */
#define INPUTMUX_DMA0_ITRIGEN1_SET_SET8(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET8_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET8_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_SET_SET9_MASK     (0x200U)
#define INPUTMUX_DMA0_ITRIGEN1_SET_SET9_SHIFT    (9U)
/*! SET9 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN1 register.
 */
#define INPUTMUX_DMA0_ITRIGEN1_SET_SET9(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET9_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET9_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_SET_SET10_MASK    (0x400U)
#define INPUTMUX_DMA0_ITRIGEN1_SET_SET10_SHIFT   (10U)
/*! SET10 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN1 register.
 */
#define INPUTMUX_DMA0_ITRIGEN1_SET_SET10(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET10_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET10_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_SET_SET11_MASK    (0x800U)
#define INPUTMUX_DMA0_ITRIGEN1_SET_SET11_SHIFT   (11U)
/*! SET11 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN1 register.
 */
#define INPUTMUX_DMA0_ITRIGEN1_SET_SET11(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET11_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET11_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_SET_SET12_MASK    (0x1000U)
#define INPUTMUX_DMA0_ITRIGEN1_SET_SET12_SHIFT   (12U)
/*! SET12 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN1 register.
 */
#define INPUTMUX_DMA0_ITRIGEN1_SET_SET12(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET12_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET12_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_SET_SET13_MASK    (0x2000U)
#define INPUTMUX_DMA0_ITRIGEN1_SET_SET13_SHIFT   (13U)
/*! SET13 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN1 register.
 */
#define INPUTMUX_DMA0_ITRIGEN1_SET_SET13(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET13_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET13_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_SET_SET14_MASK    (0x4000U)
#define INPUTMUX_DMA0_ITRIGEN1_SET_SET14_SHIFT   (14U)
/*! SET14 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN1 register.
 */
#define INPUTMUX_DMA0_ITRIGEN1_SET_SET14(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET14_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET14_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_SET_SET15_MASK    (0x8000U)
#define INPUTMUX_DMA0_ITRIGEN1_SET_SET15_SHIFT   (15U)
/*! SET15 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN1 register.
 */
#define INPUTMUX_DMA0_ITRIGEN1_SET_SET15(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET15_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET15_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_SET_SET16_MASK    (0x10000U)
#define INPUTMUX_DMA0_ITRIGEN1_SET_SET16_SHIFT   (16U)
/*! SET16 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN1 register.
 */
#define INPUTMUX_DMA0_ITRIGEN1_SET_SET16(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET16_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET16_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_SET_SET17_MASK    (0x20000U)
#define INPUTMUX_DMA0_ITRIGEN1_SET_SET17_SHIFT   (17U)
/*! SET17 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN1 register.
 */
#define INPUTMUX_DMA0_ITRIGEN1_SET_SET17(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET17_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET17_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_SET_SET18_MASK    (0x40000U)
#define INPUTMUX_DMA0_ITRIGEN1_SET_SET18_SHIFT   (18U)
/*! SET18 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN1 register.
 */
#define INPUTMUX_DMA0_ITRIGEN1_SET_SET18(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET18_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET18_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_SET_SET19_MASK    (0x80000U)
#define INPUTMUX_DMA0_ITRIGEN1_SET_SET19_SHIFT   (19U)
/*! SET19 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN1 register.
 */
#define INPUTMUX_DMA0_ITRIGEN1_SET_SET19(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_SET_SET19_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_SET_SET19_MASK)
/*! @} */

/*! @name DMA0_ITRIGEN0_CLR - Clear bits in DMA0_ITRIGEN0 register */
/*! @{ */

#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR0_MASK     (0x1U)
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR0_SHIFT    (0U)
/*! CLR0 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR0(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR0_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR0_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR1_MASK     (0x2U)
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR1_SHIFT    (1U)
/*! CLR1 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR1(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR1_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR1_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR2_MASK     (0x4U)
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR2_SHIFT    (2U)
/*! CLR2 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR2(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR2_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR2_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR3_MASK     (0x8U)
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR3_SHIFT    (3U)
/*! CLR3 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR3(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR3_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR3_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR4_MASK     (0x10U)
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR4_SHIFT    (4U)
/*! CLR4 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR4(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR4_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR4_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR5_MASK     (0x20U)
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR5_SHIFT    (5U)
/*! CLR5 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR5(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR5_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR5_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR6_MASK     (0x40U)
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR6_SHIFT    (6U)
/*! CLR6 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR6(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR6_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR6_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR7_MASK     (0x80U)
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR7_SHIFT    (7U)
/*! CLR7 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR7(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR7_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR7_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR8_MASK     (0x100U)
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR8_SHIFT    (8U)
/*! CLR8 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR8(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR8_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR8_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR9_MASK     (0x200U)
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR9_SHIFT    (9U)
/*! CLR9 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR9(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR9_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR9_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR10_MASK    (0x400U)
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR10_SHIFT   (10U)
/*! CLR10 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 ,
 *    no change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR10(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR10_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR10_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR11_MASK    (0x800U)
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR11_SHIFT   (11U)
/*! CLR11 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 ,
 *    no change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR11(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR11_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR11_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR12_MASK    (0x1000U)
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR12_SHIFT   (12U)
/*! CLR12 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 ,
 *    no change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR12(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR12_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR12_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR13_MASK    (0x2000U)
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR13_SHIFT   (13U)
/*! CLR13 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 ,
 *    no change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR13(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR13_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR13_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR14_MASK    (0x4000U)
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR14_SHIFT   (14U)
/*! CLR14 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 ,
 *    no change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR14(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR14_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR14_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR15_MASK    (0x8000U)
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR15_SHIFT   (15U)
/*! CLR15 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 ,
 *    no change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR15(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR15_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR15_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR16_MASK    (0x10000U)
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR16_SHIFT   (16U)
/*! CLR16 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 ,
 *    no change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR16(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR16_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR16_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR17_MASK    (0x20000U)
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR17_SHIFT   (17U)
/*! CLR17 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 ,
 *    no change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR17(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR17_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR17_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR18_MASK    (0x40000U)
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR18_SHIFT   (18U)
/*! CLR18 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 ,
 *    no change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR18(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR18_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR18_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR19_MASK    (0x80000U)
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR19_SHIFT   (19U)
/*! CLR19 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 ,
 *    no change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR19(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR19_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR19_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR20_MASK    (0x100000U)
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR20_SHIFT   (20U)
/*! CLR20 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 ,
 *    no change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR20(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR20_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR20_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR21_MASK    (0x200000U)
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR21_SHIFT   (21U)
/*! CLR21 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 ,
 *    no change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR21(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR21_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR21_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR22_MASK    (0x400000U)
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR22_SHIFT   (22U)
/*! CLR22 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 ,
 *    no change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR22(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR22_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR22_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR23_MASK    (0x800000U)
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR23_SHIFT   (23U)
/*! CLR23 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 ,
 *    no change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR23(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR23_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR23_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR24_MASK    (0x1000000U)
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR24_SHIFT   (24U)
/*! CLR24 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 ,
 *    no change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR24(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR24_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR24_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR25_MASK    (0x2000000U)
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR25_SHIFT   (25U)
/*! CLR25 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 ,
 *    no change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR25(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR25_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR25_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR26_MASK    (0x4000000U)
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR26_SHIFT   (26U)
/*! CLR26 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 ,
 *    no change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR26(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR26_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR26_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR27_MASK    (0x8000000U)
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR27_SHIFT   (27U)
/*! CLR27 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 ,
 *    no change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR27(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR27_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR27_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR28_MASK    (0x10000000U)
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR28_SHIFT   (28U)
/*! CLR28 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 ,
 *    no change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR28(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR28_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR28_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR29_MASK    (0x20000000U)
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR29_SHIFT   (29U)
/*! CLR29 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 ,
 *    no change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR29(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR29_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR29_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR30_MASK    (0x40000000U)
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR30_SHIFT   (30U)
/*! CLR30 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 ,
 *    no change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR30(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR30_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR30_MASK)

#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR31_MASK    (0x80000000U)
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR31_SHIFT   (31U)
/*! CLR31 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 ,
 *    no change in DMA0_ITRIGEN0 register.
 */
#define INPUTMUX_DMA0_ITRIGEN0_CLR_CLR31(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN0_CLR_CLR31_SHIFT)) & INPUTMUX_DMA0_ITRIGEN0_CLR_CLR31_MASK)
/*! @} */

/*! @name DMA0_ITRIGEN1_CLR - Clear bits in DMA0_ITRIGEN1 register */
/*! @{ */

#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR0_MASK     (0x1U)
#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR0_SHIFT    (0U)
/*! CLR0 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN1 register.
 */
#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR0(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR0_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR0_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR1_MASK     (0x2U)
#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR1_SHIFT    (1U)
/*! CLR1 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN1 register.
 */
#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR1(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR1_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR1_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR2_MASK     (0x4U)
#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR2_SHIFT    (2U)
/*! CLR2 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN1 register.
 */
#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR2(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR2_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR2_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR3_MASK     (0x8U)
#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR3_SHIFT    (3U)
/*! CLR3 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN1 register.
 */
#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR3(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR3_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR3_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR4_MASK     (0x10U)
#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR4_SHIFT    (4U)
/*! CLR4 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN1 register.
 */
#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR4(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR4_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR4_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR5_MASK     (0x20U)
#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR5_SHIFT    (5U)
/*! CLR5 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN1 register.
 */
#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR5(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR5_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR5_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR6_MASK     (0x40U)
#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR6_SHIFT    (6U)
/*! CLR6 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN1 register.
 */
#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR6(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR6_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR6_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR7_MASK     (0x80U)
#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR7_SHIFT    (7U)
/*! CLR7 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN1 register.
 */
#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR7(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR7_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR7_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR8_MASK     (0x100U)
#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR8_SHIFT    (8U)
/*! CLR8 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN1 register.
 */
#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR8(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR8_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR8_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR9_MASK     (0x200U)
#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR9_SHIFT    (9U)
/*! CLR9 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 , no
 *    change in DMA0_ITRIGEN1 register.
 */
#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR9(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR9_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR9_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR10_MASK    (0x400U)
#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR10_SHIFT   (10U)
/*! CLR10 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 ,
 *    no change in DMA0_ITRIGEN1 register.
 */
#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR10(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR10_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR10_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR11_MASK    (0x800U)
#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR11_SHIFT   (11U)
/*! CLR11 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 ,
 *    no change in DMA0_ITRIGEN1 register.
 */
#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR11(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR11_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR11_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR12_MASK    (0x1000U)
#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR12_SHIFT   (12U)
/*! CLR12 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 ,
 *    no change in DMA0_ITRIGEN1 register.
 */
#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR12(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR12_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR12_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR13_MASK    (0x2000U)
#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR13_SHIFT   (13U)
/*! CLR13 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 ,
 *    no change in DMA0_ITRIGEN1 register.
 */
#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR13(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR13_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR13_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR14_MASK    (0x4000U)
#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR14_SHIFT   (14U)
/*! CLR14 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 ,
 *    no change in DMA0_ITRIGEN1 register.
 */
#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR14(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR14_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR14_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR15_MASK    (0x8000U)
#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR15_SHIFT   (15U)
/*! CLR15 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 ,
 *    no change in DMA0_ITRIGEN1 register.
 */
#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR15(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR15_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR15_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR16_MASK    (0x10000U)
#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR16_SHIFT   (16U)
/*! CLR16 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 ,
 *    no change in DMA0_ITRIGEN1 register.
 */
#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR16(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR16_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR16_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR17_MASK    (0x20000U)
#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR17_SHIFT   (17U)
/*! CLR17 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 ,
 *    no change in DMA0_ITRIGEN1 register.
 */
#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR17(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR17_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR17_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR18_MASK    (0x40000U)
#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR18_SHIFT   (18U)
/*! CLR18 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 ,
 *    no change in DMA0_ITRIGEN1 register.
 */
#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR18(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR18_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR18_MASK)

#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR19_MASK    (0x80000U)
#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR19_SHIFT   (19U)
/*! CLR19 - Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 ,
 *    no change in DMA0_ITRIGEN1 register.
 */
#define INPUTMUX_DMA0_ITRIGEN1_CLR_CLR19(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIGEN1_CLR_CLR19_SHIFT)) & INPUTMUX_DMA0_ITRIGEN1_CLR_CLR19_MASK)
/*! @} */

/*! @name DMA1_ITRIGEN - Enable DMA1 triggers */
/*! @{ */

#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN0_MASK      (0x1U)
#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN0_SHIFT     (0U)
/*! ITRIGEN0 - Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled.
 */
#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN0(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_ITRIGEN0_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_ITRIGEN0_MASK)

#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN1_MASK      (0x2U)
#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN1_SHIFT     (1U)
/*! ITRIGEN1 - Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled.
 */
#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN1(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_ITRIGEN1_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_ITRIGEN1_MASK)

#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN2_MASK      (0x4U)
#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN2_SHIFT     (2U)
/*! ITRIGEN2 - Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled.
 */
#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN2(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_ITRIGEN2_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_ITRIGEN2_MASK)

#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN3_MASK      (0x8U)
#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN3_SHIFT     (3U)
/*! ITRIGEN3 - Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled.
 */
#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN3(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_ITRIGEN3_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_ITRIGEN3_MASK)

#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN4_MASK      (0x10U)
#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN4_SHIFT     (4U)
/*! ITRIGEN4 - Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled.
 */
#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN4(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_ITRIGEN4_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_ITRIGEN4_MASK)

#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN5_MASK      (0x20U)
#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN5_SHIFT     (5U)
/*! ITRIGEN5 - Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled.
 */
#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN5(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_ITRIGEN5_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_ITRIGEN5_MASK)

#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN6_MASK      (0x40U)
#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN6_SHIFT     (6U)
/*! ITRIGEN6 - Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled.
 */
#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN6(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_ITRIGEN6_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_ITRIGEN6_MASK)

#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN7_MASK      (0x80U)
#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN7_SHIFT     (7U)
/*! ITRIGEN7 - Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled.
 */
#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN7(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_ITRIGEN7_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_ITRIGEN7_MASK)

#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN8_MASK      (0x100U)
#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN8_SHIFT     (8U)
/*! ITRIGEN8 - Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled.
 */
#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN8(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_ITRIGEN8_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_ITRIGEN8_MASK)

#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN9_MASK      (0x200U)
#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN9_SHIFT     (9U)
/*! ITRIGEN9 - Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled.
 */
#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN9(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_ITRIGEN9_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_ITRIGEN9_MASK)

#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN10_MASK     (0x400U)
#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN10_SHIFT    (10U)
/*! ITRIGEN10 - Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled.
 */
#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN10(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_ITRIGEN10_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_ITRIGEN10_MASK)

#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN11_MASK     (0x800U)
#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN11_SHIFT    (11U)
/*! ITRIGEN11 - Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled.
 */
#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN11(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_ITRIGEN11_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_ITRIGEN11_MASK)

#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN12_MASK     (0x1000U)
#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN12_SHIFT    (12U)
/*! ITRIGEN12 - Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled.
 */
#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN12(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_ITRIGEN12_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_ITRIGEN12_MASK)

#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN13_MASK     (0x2000U)
#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN13_SHIFT    (13U)
/*! ITRIGEN13 - Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled.
 */
#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN13(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_ITRIGEN13_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_ITRIGEN13_MASK)

#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN14_MASK     (0x4000U)
#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN14_SHIFT    (14U)
/*! ITRIGEN14 - Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled.
 */
#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN14(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_ITRIGEN14_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_ITRIGEN14_MASK)

#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN15_MASK     (0x8000U)
#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN15_SHIFT    (15U)
/*! ITRIGEN15 - Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled.
 */
#define INPUTMUX_DMA1_ITRIGEN_ITRIGEN15(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_ITRIGEN15_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_ITRIGEN15_MASK)
/*! @} */

/*! @name DMA1_ITRIGEN_SET - Set bits in DMA1_ITRIGEN register */
/*! @{ */

#define INPUTMUX_DMA1_ITRIGEN_SET_SET0_MASK      (0x1U)
#define INPUTMUX_DMA1_ITRIGEN_SET_SET0_SHIFT     (0U)
/*! SET0 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , no change in DMA1_ITRIGEN register
 */
#define INPUTMUX_DMA1_ITRIGEN_SET_SET0(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_SET_SET0_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_SET_SET0_MASK)

#define INPUTMUX_DMA1_ITRIGEN_SET_SET1_MASK      (0x2U)
#define INPUTMUX_DMA1_ITRIGEN_SET_SET1_SHIFT     (1U)
/*! SET1 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , no change in DMA1_ITRIGEN register
 */
#define INPUTMUX_DMA1_ITRIGEN_SET_SET1(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_SET_SET1_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_SET_SET1_MASK)

#define INPUTMUX_DMA1_ITRIGEN_SET_SET2_MASK      (0x4U)
#define INPUTMUX_DMA1_ITRIGEN_SET_SET2_SHIFT     (2U)
/*! SET2 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , no change in DMA1_ITRIGEN register
 */
#define INPUTMUX_DMA1_ITRIGEN_SET_SET2(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_SET_SET2_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_SET_SET2_MASK)

#define INPUTMUX_DMA1_ITRIGEN_SET_SET3_MASK      (0x8U)
#define INPUTMUX_DMA1_ITRIGEN_SET_SET3_SHIFT     (3U)
/*! SET3 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , no change in DMA1_ITRIGEN register
 */
#define INPUTMUX_DMA1_ITRIGEN_SET_SET3(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_SET_SET3_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_SET_SET3_MASK)

#define INPUTMUX_DMA1_ITRIGEN_SET_SET4_MASK      (0x10U)
#define INPUTMUX_DMA1_ITRIGEN_SET_SET4_SHIFT     (4U)
/*! SET4 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , no change in DMA1_ITRIGEN register
 */
#define INPUTMUX_DMA1_ITRIGEN_SET_SET4(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_SET_SET4_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_SET_SET4_MASK)

#define INPUTMUX_DMA1_ITRIGEN_SET_SET5_MASK      (0x20U)
#define INPUTMUX_DMA1_ITRIGEN_SET_SET5_SHIFT     (5U)
/*! SET5 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , no change in DMA1_ITRIGEN register
 */
#define INPUTMUX_DMA1_ITRIGEN_SET_SET5(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_SET_SET5_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_SET_SET5_MASK)

#define INPUTMUX_DMA1_ITRIGEN_SET_SET6_MASK      (0x40U)
#define INPUTMUX_DMA1_ITRIGEN_SET_SET6_SHIFT     (6U)
/*! SET6 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , no change in DMA1_ITRIGEN register
 */
#define INPUTMUX_DMA1_ITRIGEN_SET_SET6(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_SET_SET6_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_SET_SET6_MASK)

#define INPUTMUX_DMA1_ITRIGEN_SET_SET7_MASK      (0x80U)
#define INPUTMUX_DMA1_ITRIGEN_SET_SET7_SHIFT     (7U)
/*! SET7 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , no change in DMA1_ITRIGEN register
 */
#define INPUTMUX_DMA1_ITRIGEN_SET_SET7(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_SET_SET7_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_SET_SET7_MASK)

#define INPUTMUX_DMA1_ITRIGEN_SET_SET8_MASK      (0x100U)
#define INPUTMUX_DMA1_ITRIGEN_SET_SET8_SHIFT     (8U)
/*! SET8 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , no change in DMA1_ITRIGEN register
 */
#define INPUTMUX_DMA1_ITRIGEN_SET_SET8(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_SET_SET8_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_SET_SET8_MASK)

#define INPUTMUX_DMA1_ITRIGEN_SET_SET9_MASK      (0x200U)
#define INPUTMUX_DMA1_ITRIGEN_SET_SET9_SHIFT     (9U)
/*! SET9 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , no change in DMA1_ITRIGEN register
 */
#define INPUTMUX_DMA1_ITRIGEN_SET_SET9(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_SET_SET9_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_SET_SET9_MASK)

#define INPUTMUX_DMA1_ITRIGEN_SET_SET10_MASK     (0x400U)
#define INPUTMUX_DMA1_ITRIGEN_SET_SET10_SHIFT    (10U)
/*! SET10 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , no change in DMA1_ITRIGEN register
 */
#define INPUTMUX_DMA1_ITRIGEN_SET_SET10(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_SET_SET10_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_SET_SET10_MASK)

#define INPUTMUX_DMA1_ITRIGEN_SET_SET11_MASK     (0x800U)
#define INPUTMUX_DMA1_ITRIGEN_SET_SET11_SHIFT    (11U)
/*! SET11 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , no change in DMA1_ITRIGEN register
 */
#define INPUTMUX_DMA1_ITRIGEN_SET_SET11(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_SET_SET11_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_SET_SET11_MASK)

#define INPUTMUX_DMA1_ITRIGEN_SET_SET12_MASK     (0x1000U)
#define INPUTMUX_DMA1_ITRIGEN_SET_SET12_SHIFT    (12U)
/*! SET12 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , no change in DMA1_ITRIGEN register
 */
#define INPUTMUX_DMA1_ITRIGEN_SET_SET12(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_SET_SET12_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_SET_SET12_MASK)

#define INPUTMUX_DMA1_ITRIGEN_SET_SET13_MASK     (0x2000U)
#define INPUTMUX_DMA1_ITRIGEN_SET_SET13_SHIFT    (13U)
/*! SET13 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , no change in DMA1_ITRIGEN register
 */
#define INPUTMUX_DMA1_ITRIGEN_SET_SET13(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_SET_SET13_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_SET_SET13_MASK)

#define INPUTMUX_DMA1_ITRIGEN_SET_SET14_MASK     (0x4000U)
#define INPUTMUX_DMA1_ITRIGEN_SET_SET14_SHIFT    (14U)
/*! SET14 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , no change in DMA1_ITRIGEN register
 */
#define INPUTMUX_DMA1_ITRIGEN_SET_SET14(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_SET_SET14_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_SET_SET14_MASK)

#define INPUTMUX_DMA1_ITRIGEN_SET_SET15_MASK     (0x8000U)
#define INPUTMUX_DMA1_ITRIGEN_SET_SET15_SHIFT    (15U)
/*! SET15 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , no change in DMA1_ITRIGEN register
 */
#define INPUTMUX_DMA1_ITRIGEN_SET_SET15(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_SET_SET15_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_SET_SET15_MASK)
/*! @} */

/*! @name DMA1_ITRIGEN_CLR - Clear bits in DMA1_ITRIGEN register */
/*! @{ */

#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR0_MASK      (0x1U)
#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR0_SHIFT     (0U)
/*! CLR0 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIGEN register
 */
#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR0(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_CLR_CLR0_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_CLR_CLR0_MASK)

#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR1_MASK      (0x2U)
#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR1_SHIFT     (1U)
/*! CLR1 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIGEN register
 */
#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR1(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_CLR_CLR1_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_CLR_CLR1_MASK)

#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR2_MASK      (0x4U)
#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR2_SHIFT     (2U)
/*! CLR2 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIGEN register
 */
#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR2(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_CLR_CLR2_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_CLR_CLR2_MASK)

#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR3_MASK      (0x8U)
#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR3_SHIFT     (3U)
/*! CLR3 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIGEN register
 */
#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR3(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_CLR_CLR3_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_CLR_CLR3_MASK)

#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR4_MASK      (0x10U)
#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR4_SHIFT     (4U)
/*! CLR4 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIGEN register
 */
#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR4(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_CLR_CLR4_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_CLR_CLR4_MASK)

#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR5_MASK      (0x20U)
#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR5_SHIFT     (5U)
/*! CLR5 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIGEN register
 */
#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR5(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_CLR_CLR5_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_CLR_CLR5_MASK)

#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR6_MASK      (0x40U)
#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR6_SHIFT     (6U)
/*! CLR6 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIGEN register
 */
#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR6(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_CLR_CLR6_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_CLR_CLR6_MASK)

#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR7_MASK      (0x80U)
#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR7_SHIFT     (7U)
/*! CLR7 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIGEN register
 */
#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR7(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_CLR_CLR7_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_CLR_CLR7_MASK)

#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR8_MASK      (0x100U)
#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR8_SHIFT     (8U)
/*! CLR8 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIGEN register
 */
#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR8(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_CLR_CLR8_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_CLR_CLR8_MASK)

#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR9_MASK      (0x200U)
#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR9_SHIFT     (9U)
/*! CLR9 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIGEN register
 */
#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR9(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_CLR_CLR9_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_CLR_CLR9_MASK)

#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR10_MASK     (0x400U)
#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR10_SHIFT    (10U)
/*! CLR10 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIGEN register
 */
#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR10(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_CLR_CLR10_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_CLR_CLR10_MASK)

#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR11_MASK     (0x800U)
#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR11_SHIFT    (11U)
/*! CLR11 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIGEN register
 */
#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR11(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_CLR_CLR11_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_CLR_CLR11_MASK)

#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR12_MASK     (0x1000U)
#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR12_SHIFT    (12U)
/*! CLR12 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIGEN register
 */
#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR12(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_CLR_CLR12_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_CLR_CLR12_MASK)

#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR13_MASK     (0x2000U)
#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR13_SHIFT    (13U)
/*! CLR13 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIGEN register
 */
#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR13(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_CLR_CLR13_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_CLR_CLR13_MASK)

#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR14_MASK     (0x4000U)
#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR14_SHIFT    (14U)
/*! CLR14 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIGEN register
 */
#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR14(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_CLR_CLR14_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_CLR_CLR14_MASK)

#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR15_MASK     (0x8000U)
#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR15_SHIFT    (15U)
/*! CLR15 - Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIGEN register
 */
#define INPUTMUX_DMA1_ITRIGEN_CLR_CLR15(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIGEN_CLR_CLR15_SHIFT)) & INPUTMUX_DMA1_ITRIGEN_CLR_CLR15_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group INPUTMUX_Register_Masks */


/* INPUTMUX - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral INPUTMUX base address */
  #define INPUTMUX_BASE                            (0x50006000u)
  /** Peripheral INPUTMUX base address */
  #define INPUTMUX_BASE_NS                         (0x40006000u)
  /** Peripheral INPUTMUX base pointer */
  #define INPUTMUX                                 ((INPUTMUX_Type *)INPUTMUX_BASE)
  /** Peripheral INPUTMUX base pointer */
  #define INPUTMUX_NS                              ((INPUTMUX_Type *)INPUTMUX_BASE_NS)
  /** Array initializer of INPUTMUX peripheral base addresses */
  #define INPUTMUX_BASE_ADDRS                      { INPUTMUX_BASE }
  /** Array initializer of INPUTMUX peripheral base pointers */
  #define INPUTMUX_BASE_PTRS                       { INPUTMUX }
  /** Array initializer of INPUTMUX peripheral base addresses */
  #define INPUTMUX_BASE_ADDRS_NS                   { INPUTMUX_BASE_NS }
  /** Array initializer of INPUTMUX peripheral base pointers */
  #define INPUTMUX_BASE_PTRS_NS                    { INPUTMUX_NS }
#else
  /** Peripheral INPUTMUX base address */
  #define INPUTMUX_BASE                            (0x40006000u)
  /** Peripheral INPUTMUX base pointer */
  #define INPUTMUX                                 ((INPUTMUX_Type *)INPUTMUX_BASE)
  /** Array initializer of INPUTMUX peripheral base addresses */
  #define INPUTMUX_BASE_ADDRS                      { INPUTMUX_BASE }
  /** Array initializer of INPUTMUX peripheral base pointers */
  #define INPUTMUX_BASE_PTRS                       { INPUTMUX }
#endif

/*!
 * @}
 */ /* end of group INPUTMUX_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- IOCON Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup IOCON_Peripheral_Access_Layer IOCON Peripheral Access Layer
 * @{
 */

/** IOCON - Register Layout Typedef */
typedef struct {
  __IO uint32_t PIO[4][32];                        /**< Analog/Digital I/O control for port..Digital I/O control for port, array offset: 0x0, array step: index*0x80, index2*0x4 */
} IOCON_Type;

/* ----------------------------------------------------------------------------
   -- IOCON Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup IOCON_Register_Masks IOCON Register Masks
 * @{
 */

/*! @name PIO - Analog/Digital I/O control for port..Digital I/O control for port */
/*! @{ */

#define IOCON_PIO_FUNC_MASK                      (0xFU)
#define IOCON_PIO_FUNC_SHIFT                     (0U)
/*! FUNC - Signal(function) select
 */
#define IOCON_PIO_FUNC(x)                        (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FUNC_SHIFT)) & IOCON_PIO_FUNC_MASK)

#define IOCON_PIO_MODE_MASK                      (0x30U)
#define IOCON_PIO_MODE_SHIFT                     (4U)
/*! MODE - Mode select (on-chip pull-up/pull-down resistor control)
 *  0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled).
 *  0b01..Pull-down. Pull-down resistor enabled.
 *  0b10..Pull-up. Pull-up resistor enabled.
 *  0b11..Repeater. Repeater mode.
 */
#define IOCON_PIO_MODE(x)                        (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK)

#define IOCON_PIO_SLEW_MASK                      (0x40U)
#define IOCON_PIO_SLEW_SHIFT                     (6U)
/*! SLEW - Driver slew rate
 *  0b0..Standard-mode, output slew rate is slower. More outputs can be switched simultaneously.
 *  0b1..Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details.
 */
#define IOCON_PIO_SLEW(x)                        (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SLEW_SHIFT)) & IOCON_PIO_SLEW_MASK)

#define IOCON_PIO_INVERT_MASK                    (0x80U)
#define IOCON_PIO_INVERT_SHIFT                   (7U)
/*! INVERT - Invert polarity of input signal
 *  0b0..Don't invert the signal.
 *  0b1..Invert the signal.
 */
#define IOCON_PIO_INVERT(x)                      (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INVERT_SHIFT)) & IOCON_PIO_INVERT_MASK)

#define IOCON_PIO_DIGIMODE_MASK                  (0x100U)
#define IOCON_PIO_DIGIMODE_SHIFT                 (8U)
/*! DIGIMODE - Select Digital mode
 *  0b0..Disable digital mode. Digital input set to 0.
 *  0b1..Enable Digital mode. Digital input is enabled.
 */
#define IOCON_PIO_DIGIMODE(x)                    (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DIGIMODE_SHIFT)) & IOCON_PIO_DIGIMODE_MASK)

#define IOCON_PIO_OD_MASK                        (0x200U)
#define IOCON_PIO_OD_SHIFT                       (9U)
/*! OD - Controls open-drain mode
 *  0b0..Normal. Normal push-pull output
 *  0b1..Open-drain. Simulated open-drain output (high drive disabled).
 */
#define IOCON_PIO_OD(x)                          (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK)

#define IOCON_PIO_ASW0_MASK                      (0x400U)
#define IOCON_PIO_ASW0_SHIFT                     (10U)
/*! ASW0 - Analog switch input control
 *  0b0..Analog switch is open. (disable)
 *  0b1..Analog switch is closed. (enable)
 */
#define IOCON_PIO_ASW0(x)                        (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ASW0_SHIFT)) & IOCON_PIO_ASW0_MASK)

#define IOCON_PIO_ASW1_MASK                      (0x800U)
#define IOCON_PIO_ASW1_SHIFT                     (11U)
/*! ASW1 - Analog switch input control
 *  0b0..Analog switch is open. (disable)
 *  0b1..Analog switch is closed. (enable)
 */
#define IOCON_PIO_ASW1(x)                        (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ASW1_SHIFT)) & IOCON_PIO_ASW1_MASK)

#define IOCON_PIO_SSEL_MASK                      (0x800U)
#define IOCON_PIO_SSEL_SHIFT                     (11U)
/*! SSEL - Supply Selection bit.
 *  0b0..3V3 Signaling in I2C Mode.
 *  0b1..1V8 Signaling in I2C Mode.
 */
#define IOCON_PIO_SSEL(x)                        (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SSEL_SHIFT)) & IOCON_PIO_SSEL_MASK)

#define IOCON_PIO_FILTEROFF_MASK                 (0x1000U)
#define IOCON_PIO_FILTEROFF_SHIFT                (12U)
/*! FILTEROFF - Controls input glitch filter
 *  0b0..Filter enabled.
 *  0b1..Filter disabled.
 */
#define IOCON_PIO_FILTEROFF(x)                   (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FILTEROFF_SHIFT)) & IOCON_PIO_FILTEROFF_MASK)

#define IOCON_PIO_ECS_MASK                       (0x2000U)
#define IOCON_PIO_ECS_SHIFT                      (13U)
/*! ECS - Pull-up current source enable in I2C mode
 *  0b1..Enabled. Pull resistor is conencted.
 *  0b0..Disabled. IO is in open drain cell.
 */
#define IOCON_PIO_ECS(x)                         (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ECS_SHIFT)) & IOCON_PIO_ECS_MASK)

#define IOCON_PIO_EGP_MASK                       (0x4000U)
#define IOCON_PIO_EGP_SHIFT                      (14U)
/*! EGP - Switch between GPIO mode and I2C mode
 *  0b0..I2C mode
 *  0b1..GPIO mode.
 */
#define IOCON_PIO_EGP(x)                         (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_EGP_SHIFT)) & IOCON_PIO_EGP_MASK)

#define IOCON_PIO_I2CFILTER_MASK                 (0x8000U)
#define IOCON_PIO_I2CFILTER_SHIFT                (15U)
/*! I2CFILTER - Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation and High-Speed mode operation.
 *  0b0..I2C 50 ns glitch filter enabled. Typically used for Standard-mode, Fast-mode and Fast-mode Plus I2C.
 *  0b1..I2C 10 ns glitch filter enabled. Typically used for High-speed mode I2C.
 */
#define IOCON_PIO_I2CFILTER(x)                   (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CFILTER_SHIFT)) & IOCON_PIO_I2CFILTER_MASK)
/*! @} */

/* The count of IOCON_PIO */
#define IOCON_PIO_COUNT                          (4U)

/* The count of IOCON_PIO */
#define IOCON_PIO_COUNT2                         (32U)


/*!
 * @}
 */ /* end of group IOCON_Register_Masks */


/* IOCON - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral IOCON base address */
  #define IOCON_BASE                               (0x50001000u)
  /** Peripheral IOCON base address */
  #define IOCON_BASE_NS                            (0x40001000u)
  /** Peripheral IOCON base pointer */
  #define IOCON                                    ((IOCON_Type *)IOCON_BASE)
  /** Peripheral IOCON base pointer */
  #define IOCON_NS                                 ((IOCON_Type *)IOCON_BASE_NS)
  /** Array initializer of IOCON peripheral base addresses */
  #define IOCON_BASE_ADDRS                         { IOCON_BASE }
  /** Array initializer of IOCON peripheral base pointers */
  #define IOCON_BASE_PTRS                          { IOCON }
  /** Array initializer of IOCON peripheral base addresses */
  #define IOCON_BASE_ADDRS_NS                      { IOCON_BASE_NS }
  /** Array initializer of IOCON peripheral base pointers */
  #define IOCON_BASE_PTRS_NS                       { IOCON_NS }
#else
  /** Peripheral IOCON base address */
  #define IOCON_BASE                               (0x40001000u)
  /** Peripheral IOCON base pointer */
  #define IOCON                                    ((IOCON_Type *)IOCON_BASE)
  /** Array initializer of IOCON peripheral base addresses */
  #define IOCON_BASE_ADDRS                         { IOCON_BASE }
  /** Array initializer of IOCON peripheral base pointers */
  #define IOCON_BASE_PTRS                          { IOCON }
#endif

/*!
 * @}
 */ /* end of group IOCON_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- ITRC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup ITRC_Peripheral_Access_Layer ITRC Peripheral Access Layer
 * @{
 */

/** ITRC - Register Layout Typedef */
typedef struct {
  __IO uint32_t STATUS;                            /**< ITRC outputs and IN0 to IN15 Status, offset: 0x0 */
       uint8_t RESERVED_0[4];
  __IO uint32_t OUT0_SEL0;                         /**< ITRC_IRQ trigger Source IN0 to IN15 selector 0, offset: 0x8 */
  __IO uint32_t OUT0_SEL1;                         /**< ITRC_IRQ Trigger source IN0 to IN15 selector 1, offset: 0xC */
  __IO uint32_t OUT1_SEL0;                         /**< CSS_RESET Trigger source IN0 to IN15 selector 0, offset: 0x10 */
  __IO uint32_t OUT1_SEL1;                         /**< CSS_RESET Trigger source IN0 to IN15 selector 1, offset: 0x14 */
  __IO uint32_t OUT2_SEL0;                         /**< PUF_ZEROIZE Trigger source IN0 to IN15 selector 0, offset: 0x18 */
  __IO uint32_t OUT2_SEL1;                         /**< PUF_ZEROIZE Trigger source IN0 to IN15 selector 1, offset: 0x1C */
  __IO uint32_t OUT3_SEL0;                         /**< RAM_ZEROIZE Trigger source IN0 to IN15 selector 0, offset: 0x20 */
  __IO uint32_t OUT3_SEL1;                         /**< RAM_ZEROIZE Trigger source IN0 to IN15 selector 1, offset: 0x24 */
  __IO uint32_t OUT4_SEL0;                         /**< CHIP_RESET Trigger source IN0 to IN15 selector 0, offset: 0x28 */
  __IO uint32_t OUT4_SEL1;                         /**< CHIP_RESET Trigger source IN0 to IN15 selector 1, offset: 0x2C */
  __IO uint32_t OUT5_SEL0;                         /**< TMPR_OUT0 IN0 to IN15 selector 0, offset: 0x30 */
  __IO uint32_t OUT5_SEL1;                         /**< TMPR_OUT0 IN0 to IN15 selector 1, offset: 0x34 */
  __IO uint32_t OUT6_SEL0;                         /**< TMPR_OUT1 IN0 to IN15 selector 0, offset: 0x38 */
  __IO uint32_t OUT6_SEL1;                         /**< TMPR_OUT1 IN0 to IN15 selector 1, offset: 0x3C */
       uint8_t RESERVED_1[176];
  __O  uint32_t SW_EVENT0;                         /**< Software event 0, offset: 0xF0 */
  __O  uint32_t SW_EVENT1;                         /**< Software event 1, offset: 0xF4 */
} ITRC_Type;

/* ----------------------------------------------------------------------------
   -- ITRC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup ITRC_Register_Masks ITRC Register Masks
 * @{
 */

/*! @name STATUS - ITRC outputs and IN0 to IN15 Status */
/*! @{ */

#define ITRC_STATUS_IN0_STATUS_MASK              (0x1U)
#define ITRC_STATUS_IN0_STATUS_SHIFT             (0U)
/*! IN0_STATUS - Digital glitch detector event occurred.
 */
#define ITRC_STATUS_IN0_STATUS(x)                (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN0_STATUS_SHIFT)) & ITRC_STATUS_IN0_STATUS_MASK)

#define ITRC_STATUS_IN1_STATUS_MASK              (0x2U)
#define ITRC_STATUS_IN1_STATUS_SHIFT             (1U)
/*! IN1_STATUS - Tamper pins logic detected an event.
 */
#define ITRC_STATUS_IN1_STATUS(x)                (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN1_STATUS_SHIFT)) & ITRC_STATUS_IN1_STATUS_MASK)

#define ITRC_STATUS_IN2_STATUS_MASK              (0x4U)
#define ITRC_STATUS_IN2_STATUS_SHIFT             (2U)
/*! IN2_STATUS - Code watchdog detected an code execution anomaly.
 */
#define ITRC_STATUS_IN2_STATUS(x)                (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN2_STATUS_SHIFT)) & ITRC_STATUS_IN2_STATUS_MASK)

#define ITRC_STATUS_IN3_STATUS_MASK              (0x8U)
#define ITRC_STATUS_IN3_STATUS_SHIFT             (3U)
/*! IN3_STATUS - Low voltage event (BoD) detected on VDD_MAIN rail.
 */
#define ITRC_STATUS_IN3_STATUS(x)                (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN3_STATUS_SHIFT)) & ITRC_STATUS_IN3_STATUS_MASK)

#define ITRC_STATUS_IN4_STATUS_MASK              (0x10U)
#define ITRC_STATUS_IN4_STATUS_SHIFT             (4U)
/*! IN4_STATUS - Low voltage event (BoD) detected on VDD_CORE rail.
 */
#define ITRC_STATUS_IN4_STATUS(x)                (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN4_STATUS_SHIFT)) & ITRC_STATUS_IN4_STATUS_MASK)

#define ITRC_STATUS_IN5_STATUS_MASK              (0x20U)
#define ITRC_STATUS_IN5_STATUS_SHIFT             (5U)
/*! IN5_STATUS - Watch Dog timer event occurred.
 */
#define ITRC_STATUS_IN5_STATUS(x)                (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN5_STATUS_SHIFT)) & ITRC_STATUS_IN5_STATUS_MASK)

#define ITRC_STATUS_IN6_STATUS_MASK              (0x40U)
#define ITRC_STATUS_IN6_STATUS_SHIFT             (6U)
/*! IN6_STATUS - Flash ECC mismatch event occurred.
 */
#define ITRC_STATUS_IN6_STATUS(x)                (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN6_STATUS_SHIFT)) & ITRC_STATUS_IN6_STATUS_MASK)

#define ITRC_STATUS_IN7_STATUS_MASK              (0x80U)
#define ITRC_STATUS_IN7_STATUS_SHIFT             (7U)
/*! IN7_STATUS - AHB secure bus checkers detected illegal access.
 */
#define ITRC_STATUS_IN7_STATUS(x)                (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN7_STATUS_SHIFT)) & ITRC_STATUS_IN7_STATUS_MASK)

#define ITRC_STATUS_IN8_STATUS_MASK              (0x100U)
#define ITRC_STATUS_IN8_STATUS_SHIFT             (8U)
/*! IN8_STATUS - CSS error event occurred.
 */
#define ITRC_STATUS_IN8_STATUS(x)                (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN8_STATUS_SHIFT)) & ITRC_STATUS_IN8_STATUS_MASK)

#define ITRC_STATUS_IN10_STATUS_MASK             (0x400U)
#define ITRC_STATUS_IN10_STATUS_SHIFT            (10U)
/*! IN10_STATUS - PKC module detected an error event.
 */
#define ITRC_STATUS_IN10_STATUS(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN10_STATUS_SHIFT)) & ITRC_STATUS_IN10_STATUS_MASK)

#define ITRC_STATUS_IN14_STATUS_MASK             (0x4000U)
#define ITRC_STATUS_IN14_STATUS_SHIFT            (14U)
/*! IN14_STATUS - Software event 0 occurred.
 */
#define ITRC_STATUS_IN14_STATUS(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN14_STATUS_SHIFT)) & ITRC_STATUS_IN14_STATUS_MASK)

#define ITRC_STATUS_IN15_STATUS_MASK             (0x8000U)
#define ITRC_STATUS_IN15_STATUS_SHIFT            (15U)
/*! IN15_STATUS - Software event 1 occurred.
 */
#define ITRC_STATUS_IN15_STATUS(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN15_STATUS_SHIFT)) & ITRC_STATUS_IN15_STATUS_MASK)

#define ITRC_STATUS_OUT0_STATUS_MASK             (0x10000U)
#define ITRC_STATUS_OUT0_STATUS_SHIFT            (16U)
/*! OUT0_STATUS - ITRC triggered ITRC_IRQ output.
 */
#define ITRC_STATUS_OUT0_STATUS(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT0_STATUS_SHIFT)) & ITRC_STATUS_OUT0_STATUS_MASK)

#define ITRC_STATUS_OUT1_STATUS_MASK             (0x20000U)
#define ITRC_STATUS_OUT1_STATUS_SHIFT            (17U)
/*! OUT1_STATUS - ITRC triggered CSS_RESET to clear CSS key store.
 */
#define ITRC_STATUS_OUT1_STATUS(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT1_STATUS_SHIFT)) & ITRC_STATUS_OUT1_STATUS_MASK)

#define ITRC_STATUS_OUT2_STATUS_MASK             (0x40000U)
#define ITRC_STATUS_OUT2_STATUS_SHIFT            (18U)
/*! OUT2_STATUS - ITRC triggered PUF_ZEROIZE to clear PUF key store and RAM.
 */
#define ITRC_STATUS_OUT2_STATUS(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT2_STATUS_SHIFT)) & ITRC_STATUS_OUT2_STATUS_MASK)

#define ITRC_STATUS_OUT3_STATUS_MASK             (0x80000U)
#define ITRC_STATUS_OUT3_STATUS_SHIFT            (19U)
/*! OUT3_STATUS - ITRC triggered RAM_ZEROIZE to clear retention and PKC RAM contents.
 */
#define ITRC_STATUS_OUT3_STATUS(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT3_STATUS_SHIFT)) & ITRC_STATUS_OUT3_STATUS_MASK)

#define ITRC_STATUS_OUT4_STATUS_MASK             (0x100000U)
#define ITRC_STATUS_OUT4_STATUS_SHIFT            (20U)
/*! OUT4_STATUS - ITRC triggered CHIP_RESET to reset the chip after all other response process finished.
 */
#define ITRC_STATUS_OUT4_STATUS(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT4_STATUS_SHIFT)) & ITRC_STATUS_OUT4_STATUS_MASK)

#define ITRC_STATUS_OUT5_STATUS_MASK             (0x200000U)
#define ITRC_STATUS_OUT5_STATUS_SHIFT            (21U)
/*! OUT5_STATUS - ITRC triggered TMPR_OUT internal signal connected to various on-chip multiplexers.
 */
#define ITRC_STATUS_OUT5_STATUS(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT5_STATUS_SHIFT)) & ITRC_STATUS_OUT5_STATUS_MASK)
/*! @} */

/*! @name OUT0_SEL0 - ITRC_IRQ trigger Source IN0 to IN15 selector 0 */
/*! @{ */

#define ITRC_OUT0_SEL0_IN0_SEL0_MASK             (0x3U)
#define ITRC_OUT0_SEL0_IN0_SEL0_SHIFT            (0U)
/*! IN0_SEL0 - Selects digital glitch detector as a trigger source.
 */
#define ITRC_OUT0_SEL0_IN0_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_IN0_SEL0_SHIFT)) & ITRC_OUT0_SEL0_IN0_SEL0_MASK)

#define ITRC_OUT0_SEL0_IN1_SEL0_MASK             (0xCU)
#define ITRC_OUT0_SEL0_IN1_SEL0_SHIFT            (2U)
/*! IN1_SEL0 - Selects tamper pin event as a trigger source.
 */
#define ITRC_OUT0_SEL0_IN1_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_IN1_SEL0_SHIFT)) & ITRC_OUT0_SEL0_IN1_SEL0_MASK)

#define ITRC_OUT0_SEL0_IN2_SEL0_MASK             (0x30U)
#define ITRC_OUT0_SEL0_IN2_SEL0_SHIFT            (4U)
/*! IN2_SEL0 - Selects Code Watch Dog event as a trigger source.
 */
#define ITRC_OUT0_SEL0_IN2_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_IN2_SEL0_SHIFT)) & ITRC_OUT0_SEL0_IN2_SEL0_MASK)

#define ITRC_OUT0_SEL0_IN3_SEL0_MASK             (0xC0U)
#define ITRC_OUT0_SEL0_IN3_SEL0_SHIFT            (6U)
/*! IN3_SEL0 - Selects low-voltage event on VDD_MAIN rail as a trigger source.
 */
#define ITRC_OUT0_SEL0_IN3_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_IN3_SEL0_SHIFT)) & ITRC_OUT0_SEL0_IN3_SEL0_MASK)

#define ITRC_OUT0_SEL0_IN4_SEL0_MASK             (0x300U)
#define ITRC_OUT0_SEL0_IN4_SEL0_SHIFT            (8U)
/*! IN4_SEL0 - Selects low-voltage event on VDD_CORE rail as a trigger source.
 */
#define ITRC_OUT0_SEL0_IN4_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_IN4_SEL0_SHIFT)) & ITRC_OUT0_SEL0_IN4_SEL0_MASK)

#define ITRC_OUT0_SEL0_IN5_SEL0_MASK             (0xC00U)
#define ITRC_OUT0_SEL0_IN5_SEL0_SHIFT            (10U)
/*! IN5_SEL0 - Selects Watch Dog timer event as a trigger source.
 */
#define ITRC_OUT0_SEL0_IN5_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_IN5_SEL0_SHIFT)) & ITRC_OUT0_SEL0_IN5_SEL0_MASK)

#define ITRC_OUT0_SEL0_IN6_SEL0_MASK             (0x3000U)
#define ITRC_OUT0_SEL0_IN6_SEL0_SHIFT            (12U)
/*! IN6_SEL0 - Selects Flash ECC mismatch event as a trigger source.
 */
#define ITRC_OUT0_SEL0_IN6_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_IN6_SEL0_SHIFT)) & ITRC_OUT0_SEL0_IN6_SEL0_MASK)

#define ITRC_OUT0_SEL0_IN7_SEL0_MASK             (0xC000U)
#define ITRC_OUT0_SEL0_IN7_SEL0_SHIFT            (14U)
/*! IN7_SEL0 - Selects AHB secure bus illegal access event as a trigger source.
 */
#define ITRC_OUT0_SEL0_IN7_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_IN7_SEL0_SHIFT)) & ITRC_OUT0_SEL0_IN7_SEL0_MASK)

#define ITRC_OUT0_SEL0_IN8_SEL0_MASK             (0x30000U)
#define ITRC_OUT0_SEL0_IN8_SEL0_SHIFT            (16U)
/*! IN8_SEL0 - Selects CSS error event as a trigger source.
 */
#define ITRC_OUT0_SEL0_IN8_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_IN8_SEL0_SHIFT)) & ITRC_OUT0_SEL0_IN8_SEL0_MASK)

#define ITRC_OUT0_SEL0_IN10_SEL0_MASK            (0x300000U)
#define ITRC_OUT0_SEL0_IN10_SEL0_SHIFT           (20U)
/*! IN10_SEL0 - Selects PKC error event as a trigger source.
 */
#define ITRC_OUT0_SEL0_IN10_SEL0(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_IN10_SEL0_SHIFT)) & ITRC_OUT0_SEL0_IN10_SEL0_MASK)

#define ITRC_OUT0_SEL0_IN14_SEL0_MASK            (0x30000000U)
#define ITRC_OUT0_SEL0_IN14_SEL0_SHIFT           (28U)
/*! IN14_SEL0 - Selects software event 0 as a trigger source.
 */
#define ITRC_OUT0_SEL0_IN14_SEL0(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_IN14_SEL0_SHIFT)) & ITRC_OUT0_SEL0_IN14_SEL0_MASK)

#define ITRC_OUT0_SEL0_IN15_SEL0_MASK            (0xC0000000U)
#define ITRC_OUT0_SEL0_IN15_SEL0_SHIFT           (30U)
/*! IN15_SEL0 - Selects software event 1 as a trigger source.
 */
#define ITRC_OUT0_SEL0_IN15_SEL0(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL0_IN15_SEL0_SHIFT)) & ITRC_OUT0_SEL0_IN15_SEL0_MASK)
/*! @} */

/*! @name OUT0_SEL1 - ITRC_IRQ Trigger source IN0 to IN15 selector 1 */
/*! @{ */

#define ITRC_OUT0_SEL1_IN0_SEL1_MASK             (0x3U)
#define ITRC_OUT0_SEL1_IN0_SEL1_SHIFT            (0U)
/*! IN0_SEL1 - Selects digital glitch detector as a trigger source.
 */
#define ITRC_OUT0_SEL1_IN0_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_IN0_SEL1_SHIFT)) & ITRC_OUT0_SEL1_IN0_SEL1_MASK)

#define ITRC_OUT0_SEL1_IN1_SEL1_MASK             (0xCU)
#define ITRC_OUT0_SEL1_IN1_SEL1_SHIFT            (2U)
/*! IN1_SEL1 - Selects tamper pin event as a trigger source.
 */
#define ITRC_OUT0_SEL1_IN1_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_IN1_SEL1_SHIFT)) & ITRC_OUT0_SEL1_IN1_SEL1_MASK)

#define ITRC_OUT0_SEL1_IN2_SEL1_MASK             (0x30U)
#define ITRC_OUT0_SEL1_IN2_SEL1_SHIFT            (4U)
/*! IN2_SEL1 - Selects Code Watch Dog event as a trigger source.
 */
#define ITRC_OUT0_SEL1_IN2_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_IN2_SEL1_SHIFT)) & ITRC_OUT0_SEL1_IN2_SEL1_MASK)

#define ITRC_OUT0_SEL1_IN3_SEL1_MASK             (0xC0U)
#define ITRC_OUT0_SEL1_IN3_SEL1_SHIFT            (6U)
/*! IN3_SEL1 - Selects low-voltage event on VDD_MAIN rail as a trigger source.
 */
#define ITRC_OUT0_SEL1_IN3_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_IN3_SEL1_SHIFT)) & ITRC_OUT0_SEL1_IN3_SEL1_MASK)

#define ITRC_OUT0_SEL1_IN4_SEL1_MASK             (0x300U)
#define ITRC_OUT0_SEL1_IN4_SEL1_SHIFT            (8U)
/*! IN4_SEL1 - Selects low-voltage event on VDD_CORE rail as a trigger source.
 */
#define ITRC_OUT0_SEL1_IN4_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_IN4_SEL1_SHIFT)) & ITRC_OUT0_SEL1_IN4_SEL1_MASK)

#define ITRC_OUT0_SEL1_IN5_SEL1_MASK             (0xC00U)
#define ITRC_OUT0_SEL1_IN5_SEL1_SHIFT            (10U)
/*! IN5_SEL1 - Selects Watch Dog timer event as a trigger source.
 */
#define ITRC_OUT0_SEL1_IN5_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_IN5_SEL1_SHIFT)) & ITRC_OUT0_SEL1_IN5_SEL1_MASK)

#define ITRC_OUT0_SEL1_IN6_SEL1_MASK             (0x3000U)
#define ITRC_OUT0_SEL1_IN6_SEL1_SHIFT            (12U)
/*! IN6_SEL1 - Selects Flash ECC mismatch event as a trigger source.
 */
#define ITRC_OUT0_SEL1_IN6_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_IN6_SEL1_SHIFT)) & ITRC_OUT0_SEL1_IN6_SEL1_MASK)

#define ITRC_OUT0_SEL1_IN7_SEL1_MASK             (0xC000U)
#define ITRC_OUT0_SEL1_IN7_SEL1_SHIFT            (14U)
/*! IN7_SEL1 - Selects AHB secure bus illegal access event as a trigger source.
 */
#define ITRC_OUT0_SEL1_IN7_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_IN7_SEL1_SHIFT)) & ITRC_OUT0_SEL1_IN7_SEL1_MASK)

#define ITRC_OUT0_SEL1_IN8_SEL1_MASK             (0x30000U)
#define ITRC_OUT0_SEL1_IN8_SEL1_SHIFT            (16U)
/*! IN8_SEL1 - Selects CSS error event as a trigger source.
 */
#define ITRC_OUT0_SEL1_IN8_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_IN8_SEL1_SHIFT)) & ITRC_OUT0_SEL1_IN8_SEL1_MASK)

#define ITRC_OUT0_SEL1_IN10_SEL1_MASK            (0x300000U)
#define ITRC_OUT0_SEL1_IN10_SEL1_SHIFT           (20U)
/*! IN10_SEL1 - Selects PKC error event as a trigger source.
 */
#define ITRC_OUT0_SEL1_IN10_SEL1(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_IN10_SEL1_SHIFT)) & ITRC_OUT0_SEL1_IN10_SEL1_MASK)

#define ITRC_OUT0_SEL1_IN14_SEL1_MASK            (0x30000000U)
#define ITRC_OUT0_SEL1_IN14_SEL1_SHIFT           (28U)
/*! IN14_SEL1 - Selects software event 0 as a trigger source.
 */
#define ITRC_OUT0_SEL1_IN14_SEL1(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_IN14_SEL1_SHIFT)) & ITRC_OUT0_SEL1_IN14_SEL1_MASK)

#define ITRC_OUT0_SEL1_IN15_SEL1_MASK            (0xC0000000U)
#define ITRC_OUT0_SEL1_IN15_SEL1_SHIFT           (30U)
/*! IN15_SEL1 - Selects software event 1 as a trigger source.
 */
#define ITRC_OUT0_SEL1_IN15_SEL1(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT0_SEL1_IN15_SEL1_SHIFT)) & ITRC_OUT0_SEL1_IN15_SEL1_MASK)
/*! @} */

/*! @name OUT1_SEL0 - CSS_RESET Trigger source IN0 to IN15 selector 0 */
/*! @{ */

#define ITRC_OUT1_SEL0_IN0_SEL0_MASK             (0x3U)
#define ITRC_OUT1_SEL0_IN0_SEL0_SHIFT            (0U)
/*! IN0_SEL0 - CSS_RESET Trigger source selector 0 register.
 */
#define ITRC_OUT1_SEL0_IN0_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_IN0_SEL0_SHIFT)) & ITRC_OUT1_SEL0_IN0_SEL0_MASK)

#define ITRC_OUT1_SEL0_IN1_SEL0_MASK             (0xCU)
#define ITRC_OUT1_SEL0_IN1_SEL0_SHIFT            (2U)
/*! IN1_SEL0 - Selects tamper pin event as a trigger source.
 */
#define ITRC_OUT1_SEL0_IN1_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_IN1_SEL0_SHIFT)) & ITRC_OUT1_SEL0_IN1_SEL0_MASK)

#define ITRC_OUT1_SEL0_IN2_SEL0_MASK             (0x30U)
#define ITRC_OUT1_SEL0_IN2_SEL0_SHIFT            (4U)
/*! IN2_SEL0 - Selects Code Watch Dog event as a trigger source.
 */
#define ITRC_OUT1_SEL0_IN2_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_IN2_SEL0_SHIFT)) & ITRC_OUT1_SEL0_IN2_SEL0_MASK)

#define ITRC_OUT1_SEL0_IN3_SEL0_MASK             (0xC0U)
#define ITRC_OUT1_SEL0_IN3_SEL0_SHIFT            (6U)
/*! IN3_SEL0 - Selects low-voltage event on VDD_MAIN rail as a trigger source.
 */
#define ITRC_OUT1_SEL0_IN3_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_IN3_SEL0_SHIFT)) & ITRC_OUT1_SEL0_IN3_SEL0_MASK)

#define ITRC_OUT1_SEL0_IN4_SEL0_MASK             (0x300U)
#define ITRC_OUT1_SEL0_IN4_SEL0_SHIFT            (8U)
/*! IN4_SEL0 - Selects low-voltage event on VDD_CORE rail as a trigger source.
 */
#define ITRC_OUT1_SEL0_IN4_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_IN4_SEL0_SHIFT)) & ITRC_OUT1_SEL0_IN4_SEL0_MASK)

#define ITRC_OUT1_SEL0_IN5_SEL0_MASK             (0xC00U)
#define ITRC_OUT1_SEL0_IN5_SEL0_SHIFT            (10U)
/*! IN5_SEL0 - Selects Watch Dog timer event as a trigger source.
 */
#define ITRC_OUT1_SEL0_IN5_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_IN5_SEL0_SHIFT)) & ITRC_OUT1_SEL0_IN5_SEL0_MASK)

#define ITRC_OUT1_SEL0_IN6_SEL0_MASK             (0x3000U)
#define ITRC_OUT1_SEL0_IN6_SEL0_SHIFT            (12U)
/*! IN6_SEL0 - Selects Flash ECC mismatch event as a trigger source.
 */
#define ITRC_OUT1_SEL0_IN6_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_IN6_SEL0_SHIFT)) & ITRC_OUT1_SEL0_IN6_SEL0_MASK)

#define ITRC_OUT1_SEL0_IN7_SEL0_MASK             (0xC000U)
#define ITRC_OUT1_SEL0_IN7_SEL0_SHIFT            (14U)
/*! IN7_SEL0 - Selects AHB secure bus illegal access event as a trigger source.
 */
#define ITRC_OUT1_SEL0_IN7_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_IN7_SEL0_SHIFT)) & ITRC_OUT1_SEL0_IN7_SEL0_MASK)

#define ITRC_OUT1_SEL0_IN8_SEL0_MASK             (0x30000U)
#define ITRC_OUT1_SEL0_IN8_SEL0_SHIFT            (16U)
/*! IN8_SEL0 - Selects CSS error event as a trigger source.
 */
#define ITRC_OUT1_SEL0_IN8_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_IN8_SEL0_SHIFT)) & ITRC_OUT1_SEL0_IN8_SEL0_MASK)

#define ITRC_OUT1_SEL0_IN10_SEL0_MASK            (0x300000U)
#define ITRC_OUT1_SEL0_IN10_SEL0_SHIFT           (20U)
/*! IN10_SEL0 - Selects PKC error event as a trigger source.
 */
#define ITRC_OUT1_SEL0_IN10_SEL0(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_IN10_SEL0_SHIFT)) & ITRC_OUT1_SEL0_IN10_SEL0_MASK)

#define ITRC_OUT1_SEL0_IN14_SEL0_MASK            (0x30000000U)
#define ITRC_OUT1_SEL0_IN14_SEL0_SHIFT           (28U)
/*! IN14_SEL0 - Selects software event 0 as a trigger source.
 */
#define ITRC_OUT1_SEL0_IN14_SEL0(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_IN14_SEL0_SHIFT)) & ITRC_OUT1_SEL0_IN14_SEL0_MASK)

#define ITRC_OUT1_SEL0_IN15_SEL0_MASK            (0xC0000000U)
#define ITRC_OUT1_SEL0_IN15_SEL0_SHIFT           (30U)
/*! IN15_SEL0 - Selects software event 1 as a trigger source.
 */
#define ITRC_OUT1_SEL0_IN15_SEL0(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL0_IN15_SEL0_SHIFT)) & ITRC_OUT1_SEL0_IN15_SEL0_MASK)
/*! @} */

/*! @name OUT1_SEL1 - CSS_RESET Trigger source IN0 to IN15 selector 1 */
/*! @{ */

#define ITRC_OUT1_SEL1_IN0_SEL1_MASK             (0x3U)
#define ITRC_OUT1_SEL1_IN0_SEL1_SHIFT            (0U)
/*! IN0_SEL1 - Selects digital glitch detector as a trigger source.
 */
#define ITRC_OUT1_SEL1_IN0_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_IN0_SEL1_SHIFT)) & ITRC_OUT1_SEL1_IN0_SEL1_MASK)

#define ITRC_OUT1_SEL1_IN1_SEL1_MASK             (0xCU)
#define ITRC_OUT1_SEL1_IN1_SEL1_SHIFT            (2U)
/*! IN1_SEL1 - Selects tamper pin event as a trigger source.
 */
#define ITRC_OUT1_SEL1_IN1_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_IN1_SEL1_SHIFT)) & ITRC_OUT1_SEL1_IN1_SEL1_MASK)

#define ITRC_OUT1_SEL1_IN2_SEL1_MASK             (0x30U)
#define ITRC_OUT1_SEL1_IN2_SEL1_SHIFT            (4U)
/*! IN2_SEL1 - Selects Code Watch Dog event as a trigger source.
 */
#define ITRC_OUT1_SEL1_IN2_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_IN2_SEL1_SHIFT)) & ITRC_OUT1_SEL1_IN2_SEL1_MASK)

#define ITRC_OUT1_SEL1_IN3_SEL1_MASK             (0xC0U)
#define ITRC_OUT1_SEL1_IN3_SEL1_SHIFT            (6U)
/*! IN3_SEL1 - Selects low-voltage event on VDD_MAIN rail as a trigger source.
 */
#define ITRC_OUT1_SEL1_IN3_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_IN3_SEL1_SHIFT)) & ITRC_OUT1_SEL1_IN3_SEL1_MASK)

#define ITRC_OUT1_SEL1_IN4_SEL1_MASK             (0x300U)
#define ITRC_OUT1_SEL1_IN4_SEL1_SHIFT            (8U)
/*! IN4_SEL1 - Selects low-voltage event on VDD_CORE rail as a trigger source.
 */
#define ITRC_OUT1_SEL1_IN4_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_IN4_SEL1_SHIFT)) & ITRC_OUT1_SEL1_IN4_SEL1_MASK)

#define ITRC_OUT1_SEL1_IN5_SEL1_MASK             (0xC00U)
#define ITRC_OUT1_SEL1_IN5_SEL1_SHIFT            (10U)
/*! IN5_SEL1 - Selects Watch Dog timer event as a trigger source.
 */
#define ITRC_OUT1_SEL1_IN5_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_IN5_SEL1_SHIFT)) & ITRC_OUT1_SEL1_IN5_SEL1_MASK)

#define ITRC_OUT1_SEL1_IN6_SEL1_MASK             (0x3000U)
#define ITRC_OUT1_SEL1_IN6_SEL1_SHIFT            (12U)
/*! IN6_SEL1 - Selects Flash ECC mismatch event as a trigger source.
 */
#define ITRC_OUT1_SEL1_IN6_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_IN6_SEL1_SHIFT)) & ITRC_OUT1_SEL1_IN6_SEL1_MASK)

#define ITRC_OUT1_SEL1_IN7_SEL1_MASK             (0xC000U)
#define ITRC_OUT1_SEL1_IN7_SEL1_SHIFT            (14U)
/*! IN7_SEL1 - Selects AHB secure bus illegal access event as a trigger source.
 */
#define ITRC_OUT1_SEL1_IN7_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_IN7_SEL1_SHIFT)) & ITRC_OUT1_SEL1_IN7_SEL1_MASK)

#define ITRC_OUT1_SEL1_IN8_SEL1_MASK             (0x30000U)
#define ITRC_OUT1_SEL1_IN8_SEL1_SHIFT            (16U)
/*! IN8_SEL1 - Selects CSS error event as a trigger source.
 */
#define ITRC_OUT1_SEL1_IN8_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_IN8_SEL1_SHIFT)) & ITRC_OUT1_SEL1_IN8_SEL1_MASK)

#define ITRC_OUT1_SEL1_IN10_SEL1_MASK            (0x300000U)
#define ITRC_OUT1_SEL1_IN10_SEL1_SHIFT           (20U)
/*! IN10_SEL1 - Selects PKC error event as a trigger source.
 */
#define ITRC_OUT1_SEL1_IN10_SEL1(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_IN10_SEL1_SHIFT)) & ITRC_OUT1_SEL1_IN10_SEL1_MASK)

#define ITRC_OUT1_SEL1_IN14_SEL1_MASK            (0x30000000U)
#define ITRC_OUT1_SEL1_IN14_SEL1_SHIFT           (28U)
/*! IN14_SEL1 - Selects software event 0 as a trigger source.
 */
#define ITRC_OUT1_SEL1_IN14_SEL1(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_IN14_SEL1_SHIFT)) & ITRC_OUT1_SEL1_IN14_SEL1_MASK)

#define ITRC_OUT1_SEL1_IN15_SEL1_MASK            (0xC0000000U)
#define ITRC_OUT1_SEL1_IN15_SEL1_SHIFT           (30U)
/*! IN15_SEL1 - Selects software event 1 as a trigger source.
 */
#define ITRC_OUT1_SEL1_IN15_SEL1(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT1_SEL1_IN15_SEL1_SHIFT)) & ITRC_OUT1_SEL1_IN15_SEL1_MASK)
/*! @} */

/*! @name OUT2_SEL0 - PUF_ZEROIZE Trigger source IN0 to IN15 selector 0 */
/*! @{ */

#define ITRC_OUT2_SEL0_IN0_SEL0_MASK             (0x3U)
#define ITRC_OUT2_SEL0_IN0_SEL0_SHIFT            (0U)
/*! IN0_SEL0 - CSS_RESET Trigger source selector 0 register.
 */
#define ITRC_OUT2_SEL0_IN0_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL0_IN0_SEL0_SHIFT)) & ITRC_OUT2_SEL0_IN0_SEL0_MASK)

#define ITRC_OUT2_SEL0_IN1_SEL0_MASK             (0xCU)
#define ITRC_OUT2_SEL0_IN1_SEL0_SHIFT            (2U)
/*! IN1_SEL0 - Selects tamper pin event as a trigger source.
 */
#define ITRC_OUT2_SEL0_IN1_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL0_IN1_SEL0_SHIFT)) & ITRC_OUT2_SEL0_IN1_SEL0_MASK)

#define ITRC_OUT2_SEL0_IN2_SEL0_MASK             (0x30U)
#define ITRC_OUT2_SEL0_IN2_SEL0_SHIFT            (4U)
/*! IN2_SEL0 - Selects Code Watch Dog event as a trigger source.
 */
#define ITRC_OUT2_SEL0_IN2_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL0_IN2_SEL0_SHIFT)) & ITRC_OUT2_SEL0_IN2_SEL0_MASK)

#define ITRC_OUT2_SEL0_IN3_SEL0_MASK             (0xC0U)
#define ITRC_OUT2_SEL0_IN3_SEL0_SHIFT            (6U)
/*! IN3_SEL0 - Selects low-voltage event on VDD_MAIN rail as a trigger source.
 */
#define ITRC_OUT2_SEL0_IN3_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL0_IN3_SEL0_SHIFT)) & ITRC_OUT2_SEL0_IN3_SEL0_MASK)

#define ITRC_OUT2_SEL0_IN4_SEL0_MASK             (0x300U)
#define ITRC_OUT2_SEL0_IN4_SEL0_SHIFT            (8U)
/*! IN4_SEL0 - Selects low-voltage event on VDD_CORE rail as a trigger source.
 */
#define ITRC_OUT2_SEL0_IN4_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL0_IN4_SEL0_SHIFT)) & ITRC_OUT2_SEL0_IN4_SEL0_MASK)

#define ITRC_OUT2_SEL0_IN5_SEL0_MASK             (0xC00U)
#define ITRC_OUT2_SEL0_IN5_SEL0_SHIFT            (10U)
/*! IN5_SEL0 - Selects Watch Dog timer event as a trigger source.
 */
#define ITRC_OUT2_SEL0_IN5_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL0_IN5_SEL0_SHIFT)) & ITRC_OUT2_SEL0_IN5_SEL0_MASK)

#define ITRC_OUT2_SEL0_IN6_SEL0_MASK             (0x3000U)
#define ITRC_OUT2_SEL0_IN6_SEL0_SHIFT            (12U)
/*! IN6_SEL0 - Selects Flash ECC mismatch event as a trigger source.
 */
#define ITRC_OUT2_SEL0_IN6_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL0_IN6_SEL0_SHIFT)) & ITRC_OUT2_SEL0_IN6_SEL0_MASK)

#define ITRC_OUT2_SEL0_IN7_SEL0_MASK             (0xC000U)
#define ITRC_OUT2_SEL0_IN7_SEL0_SHIFT            (14U)
/*! IN7_SEL0 - Selects AHB secure bus illegal access event as a trigger source.
 */
#define ITRC_OUT2_SEL0_IN7_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL0_IN7_SEL0_SHIFT)) & ITRC_OUT2_SEL0_IN7_SEL0_MASK)

#define ITRC_OUT2_SEL0_IN8_SEL0_MASK             (0x30000U)
#define ITRC_OUT2_SEL0_IN8_SEL0_SHIFT            (16U)
/*! IN8_SEL0 - Selects CSS error event as a trigger source.
 */
#define ITRC_OUT2_SEL0_IN8_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL0_IN8_SEL0_SHIFT)) & ITRC_OUT2_SEL0_IN8_SEL0_MASK)

#define ITRC_OUT2_SEL0_IN10_SEL0_MASK            (0x300000U)
#define ITRC_OUT2_SEL0_IN10_SEL0_SHIFT           (20U)
/*! IN10_SEL0 - Selects PKC error event as a trigger source.
 */
#define ITRC_OUT2_SEL0_IN10_SEL0(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL0_IN10_SEL0_SHIFT)) & ITRC_OUT2_SEL0_IN10_SEL0_MASK)

#define ITRC_OUT2_SEL0_IN14_SEL0_MASK            (0x30000000U)
#define ITRC_OUT2_SEL0_IN14_SEL0_SHIFT           (28U)
/*! IN14_SEL0 - Selects software event 0 as a trigger source.
 */
#define ITRC_OUT2_SEL0_IN14_SEL0(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL0_IN14_SEL0_SHIFT)) & ITRC_OUT2_SEL0_IN14_SEL0_MASK)

#define ITRC_OUT2_SEL0_IN15_SEL0_MASK            (0xC0000000U)
#define ITRC_OUT2_SEL0_IN15_SEL0_SHIFT           (30U)
/*! IN15_SEL0 - Selects software event 1 as a trigger source.
 */
#define ITRC_OUT2_SEL0_IN15_SEL0(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL0_IN15_SEL0_SHIFT)) & ITRC_OUT2_SEL0_IN15_SEL0_MASK)
/*! @} */

/*! @name OUT2_SEL1 - PUF_ZEROIZE Trigger source IN0 to IN15 selector 1 */
/*! @{ */

#define ITRC_OUT2_SEL1_IN0_SEL1_MASK             (0x3U)
#define ITRC_OUT2_SEL1_IN0_SEL1_SHIFT            (0U)
/*! IN0_SEL1 - Selects digital glitch detector as a trigger source.
 */
#define ITRC_OUT2_SEL1_IN0_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL1_IN0_SEL1_SHIFT)) & ITRC_OUT2_SEL1_IN0_SEL1_MASK)

#define ITRC_OUT2_SEL1_IN1_SEL1_MASK             (0xCU)
#define ITRC_OUT2_SEL1_IN1_SEL1_SHIFT            (2U)
/*! IN1_SEL1 - Selects tamper pin event as a trigger source.
 */
#define ITRC_OUT2_SEL1_IN1_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL1_IN1_SEL1_SHIFT)) & ITRC_OUT2_SEL1_IN1_SEL1_MASK)

#define ITRC_OUT2_SEL1_IN2_SEL1_MASK             (0x30U)
#define ITRC_OUT2_SEL1_IN2_SEL1_SHIFT            (4U)
/*! IN2_SEL1 - Selects Code Watch Dog event as a trigger source.
 */
#define ITRC_OUT2_SEL1_IN2_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL1_IN2_SEL1_SHIFT)) & ITRC_OUT2_SEL1_IN2_SEL1_MASK)

#define ITRC_OUT2_SEL1_IN3_SEL1_MASK             (0xC0U)
#define ITRC_OUT2_SEL1_IN3_SEL1_SHIFT            (6U)
/*! IN3_SEL1 - Selects low-voltage event on VDD_MAIN rail as a trigger source.
 */
#define ITRC_OUT2_SEL1_IN3_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL1_IN3_SEL1_SHIFT)) & ITRC_OUT2_SEL1_IN3_SEL1_MASK)

#define ITRC_OUT2_SEL1_IN4_SEL1_MASK             (0x300U)
#define ITRC_OUT2_SEL1_IN4_SEL1_SHIFT            (8U)
/*! IN4_SEL1 - Selects low-voltage event on VDD_CORE rail as a trigger source.
 */
#define ITRC_OUT2_SEL1_IN4_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL1_IN4_SEL1_SHIFT)) & ITRC_OUT2_SEL1_IN4_SEL1_MASK)

#define ITRC_OUT2_SEL1_IN5_SEL1_MASK             (0xC00U)
#define ITRC_OUT2_SEL1_IN5_SEL1_SHIFT            (10U)
/*! IN5_SEL1 - Selects Watch Dog timer event as a trigger source.
 */
#define ITRC_OUT2_SEL1_IN5_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL1_IN5_SEL1_SHIFT)) & ITRC_OUT2_SEL1_IN5_SEL1_MASK)

#define ITRC_OUT2_SEL1_IN6_SEL1_MASK             (0x3000U)
#define ITRC_OUT2_SEL1_IN6_SEL1_SHIFT            (12U)
/*! IN6_SEL1 - Selects Flash ECC mismatch event as a trigger source.
 */
#define ITRC_OUT2_SEL1_IN6_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL1_IN6_SEL1_SHIFT)) & ITRC_OUT2_SEL1_IN6_SEL1_MASK)

#define ITRC_OUT2_SEL1_IN7_SEL1_MASK             (0xC000U)
#define ITRC_OUT2_SEL1_IN7_SEL1_SHIFT            (14U)
/*! IN7_SEL1 - Selects AHB secure bus illegal access event as a trigger source.
 */
#define ITRC_OUT2_SEL1_IN7_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL1_IN7_SEL1_SHIFT)) & ITRC_OUT2_SEL1_IN7_SEL1_MASK)

#define ITRC_OUT2_SEL1_IN8_SEL1_MASK             (0x30000U)
#define ITRC_OUT2_SEL1_IN8_SEL1_SHIFT            (16U)
/*! IN8_SEL1 - Selects CSS error event as a trigger source.
 */
#define ITRC_OUT2_SEL1_IN8_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL1_IN8_SEL1_SHIFT)) & ITRC_OUT2_SEL1_IN8_SEL1_MASK)

#define ITRC_OUT2_SEL1_IN10_SEL1_MASK            (0x300000U)
#define ITRC_OUT2_SEL1_IN10_SEL1_SHIFT           (20U)
/*! IN10_SEL1 - Selects PKC error event as a trigger source.
 */
#define ITRC_OUT2_SEL1_IN10_SEL1(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL1_IN10_SEL1_SHIFT)) & ITRC_OUT2_SEL1_IN10_SEL1_MASK)

#define ITRC_OUT2_SEL1_IN14_SEL1_MASK            (0x30000000U)
#define ITRC_OUT2_SEL1_IN14_SEL1_SHIFT           (28U)
/*! IN14_SEL1 - Selects software event 0 as a trigger source.
 */
#define ITRC_OUT2_SEL1_IN14_SEL1(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL1_IN14_SEL1_SHIFT)) & ITRC_OUT2_SEL1_IN14_SEL1_MASK)

#define ITRC_OUT2_SEL1_IN15_SEL1_MASK            (0xC0000000U)
#define ITRC_OUT2_SEL1_IN15_SEL1_SHIFT           (30U)
/*! IN15_SEL1 - Selects software event 1 as a trigger source.
 */
#define ITRC_OUT2_SEL1_IN15_SEL1(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT2_SEL1_IN15_SEL1_SHIFT)) & ITRC_OUT2_SEL1_IN15_SEL1_MASK)
/*! @} */

/*! @name OUT3_SEL0 - RAM_ZEROIZE Trigger source IN0 to IN15 selector 0 */
/*! @{ */

#define ITRC_OUT3_SEL0_IN0_SEL0_MASK             (0x3U)
#define ITRC_OUT3_SEL0_IN0_SEL0_SHIFT            (0U)
/*! IN0_SEL0 - CSS_RESET Trigger source selector 0 register.
 */
#define ITRC_OUT3_SEL0_IN0_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL0_IN0_SEL0_SHIFT)) & ITRC_OUT3_SEL0_IN0_SEL0_MASK)

#define ITRC_OUT3_SEL0_IN1_SEL0_MASK             (0xCU)
#define ITRC_OUT3_SEL0_IN1_SEL0_SHIFT            (2U)
/*! IN1_SEL0 - Selects tamper pin event as a trigger source.
 */
#define ITRC_OUT3_SEL0_IN1_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL0_IN1_SEL0_SHIFT)) & ITRC_OUT3_SEL0_IN1_SEL0_MASK)

#define ITRC_OUT3_SEL0_IN2_SEL0_MASK             (0x30U)
#define ITRC_OUT3_SEL0_IN2_SEL0_SHIFT            (4U)
/*! IN2_SEL0 - Selects Code Watch Dog event as a trigger source.
 */
#define ITRC_OUT3_SEL0_IN2_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL0_IN2_SEL0_SHIFT)) & ITRC_OUT3_SEL0_IN2_SEL0_MASK)

#define ITRC_OUT3_SEL0_IN3_SEL0_MASK             (0xC0U)
#define ITRC_OUT3_SEL0_IN3_SEL0_SHIFT            (6U)
/*! IN3_SEL0 - Selects low-voltage event on VDD_MAIN rail as a trigger source.
 */
#define ITRC_OUT3_SEL0_IN3_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL0_IN3_SEL0_SHIFT)) & ITRC_OUT3_SEL0_IN3_SEL0_MASK)

#define ITRC_OUT3_SEL0_IN4_SEL0_MASK             (0x300U)
#define ITRC_OUT3_SEL0_IN4_SEL0_SHIFT            (8U)
/*! IN4_SEL0 - Selects low-voltage event on VDD_CORE rail as a trigger source.
 */
#define ITRC_OUT3_SEL0_IN4_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL0_IN4_SEL0_SHIFT)) & ITRC_OUT3_SEL0_IN4_SEL0_MASK)

#define ITRC_OUT3_SEL0_IN5_SEL0_MASK             (0xC00U)
#define ITRC_OUT3_SEL0_IN5_SEL0_SHIFT            (10U)
/*! IN5_SEL0 - Selects Watch Dog timer event as a trigger source.
 */
#define ITRC_OUT3_SEL0_IN5_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL0_IN5_SEL0_SHIFT)) & ITRC_OUT3_SEL0_IN5_SEL0_MASK)

#define ITRC_OUT3_SEL0_IN6_SEL0_MASK             (0x3000U)
#define ITRC_OUT3_SEL0_IN6_SEL0_SHIFT            (12U)
/*! IN6_SEL0 - Selects Flash ECC mismatch event as a trigger source.
 */
#define ITRC_OUT3_SEL0_IN6_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL0_IN6_SEL0_SHIFT)) & ITRC_OUT3_SEL0_IN6_SEL0_MASK)

#define ITRC_OUT3_SEL0_IN7_SEL0_MASK             (0xC000U)
#define ITRC_OUT3_SEL0_IN7_SEL0_SHIFT            (14U)
/*! IN7_SEL0 - Selects AHB secure bus illegal access event as a trigger source.
 */
#define ITRC_OUT3_SEL0_IN7_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL0_IN7_SEL0_SHIFT)) & ITRC_OUT3_SEL0_IN7_SEL0_MASK)

#define ITRC_OUT3_SEL0_IN8_SEL0_MASK             (0x30000U)
#define ITRC_OUT3_SEL0_IN8_SEL0_SHIFT            (16U)
/*! IN8_SEL0 - Selects CSS error event as a trigger source.
 */
#define ITRC_OUT3_SEL0_IN8_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL0_IN8_SEL0_SHIFT)) & ITRC_OUT3_SEL0_IN8_SEL0_MASK)

#define ITRC_OUT3_SEL0_IN10_SEL0_MASK            (0x300000U)
#define ITRC_OUT3_SEL0_IN10_SEL0_SHIFT           (20U)
/*! IN10_SEL0 - Selects PKC error event as a trigger source.
 */
#define ITRC_OUT3_SEL0_IN10_SEL0(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL0_IN10_SEL0_SHIFT)) & ITRC_OUT3_SEL0_IN10_SEL0_MASK)

#define ITRC_OUT3_SEL0_IN14_SEL0_MASK            (0x30000000U)
#define ITRC_OUT3_SEL0_IN14_SEL0_SHIFT           (28U)
/*! IN14_SEL0 - Selects software event 0 as a trigger source.
 */
#define ITRC_OUT3_SEL0_IN14_SEL0(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL0_IN14_SEL0_SHIFT)) & ITRC_OUT3_SEL0_IN14_SEL0_MASK)

#define ITRC_OUT3_SEL0_IN15_SEL0_MASK            (0xC0000000U)
#define ITRC_OUT3_SEL0_IN15_SEL0_SHIFT           (30U)
/*! IN15_SEL0 - Selects software event 1 as a trigger source.
 */
#define ITRC_OUT3_SEL0_IN15_SEL0(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL0_IN15_SEL0_SHIFT)) & ITRC_OUT3_SEL0_IN15_SEL0_MASK)
/*! @} */

/*! @name OUT3_SEL1 - RAM_ZEROIZE Trigger source IN0 to IN15 selector 1 */
/*! @{ */

#define ITRC_OUT3_SEL1_IN0_SEL1_MASK             (0x3U)
#define ITRC_OUT3_SEL1_IN0_SEL1_SHIFT            (0U)
/*! IN0_SEL1 - Selects digital glitch detector as a trigger source.
 */
#define ITRC_OUT3_SEL1_IN0_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL1_IN0_SEL1_SHIFT)) & ITRC_OUT3_SEL1_IN0_SEL1_MASK)

#define ITRC_OUT3_SEL1_IN1_SEL1_MASK             (0xCU)
#define ITRC_OUT3_SEL1_IN1_SEL1_SHIFT            (2U)
/*! IN1_SEL1 - Selects tamper pin event as a trigger source.
 */
#define ITRC_OUT3_SEL1_IN1_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL1_IN1_SEL1_SHIFT)) & ITRC_OUT3_SEL1_IN1_SEL1_MASK)

#define ITRC_OUT3_SEL1_IN2_SEL1_MASK             (0x30U)
#define ITRC_OUT3_SEL1_IN2_SEL1_SHIFT            (4U)
/*! IN2_SEL1 - Selects Code Watch Dog event as a trigger source.
 */
#define ITRC_OUT3_SEL1_IN2_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL1_IN2_SEL1_SHIFT)) & ITRC_OUT3_SEL1_IN2_SEL1_MASK)

#define ITRC_OUT3_SEL1_IN3_SEL1_MASK             (0xC0U)
#define ITRC_OUT3_SEL1_IN3_SEL1_SHIFT            (6U)
/*! IN3_SEL1 - Selects low-voltage event on VDD_MAIN rail as a trigger source.
 */
#define ITRC_OUT3_SEL1_IN3_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL1_IN3_SEL1_SHIFT)) & ITRC_OUT3_SEL1_IN3_SEL1_MASK)

#define ITRC_OUT3_SEL1_IN4_SEL1_MASK             (0x300U)
#define ITRC_OUT3_SEL1_IN4_SEL1_SHIFT            (8U)
/*! IN4_SEL1 - Selects low-voltage event on VDD_CORE rail as a trigger source.
 */
#define ITRC_OUT3_SEL1_IN4_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL1_IN4_SEL1_SHIFT)) & ITRC_OUT3_SEL1_IN4_SEL1_MASK)

#define ITRC_OUT3_SEL1_IN5_SEL1_MASK             (0xC00U)
#define ITRC_OUT3_SEL1_IN5_SEL1_SHIFT            (10U)
/*! IN5_SEL1 - Selects Watch Dog timer event as a trigger source.
 */
#define ITRC_OUT3_SEL1_IN5_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL1_IN5_SEL1_SHIFT)) & ITRC_OUT3_SEL1_IN5_SEL1_MASK)

#define ITRC_OUT3_SEL1_IN6_SEL1_MASK             (0x3000U)
#define ITRC_OUT3_SEL1_IN6_SEL1_SHIFT            (12U)
/*! IN6_SEL1 - Selects Flash ECC mismatch event as a trigger source.
 */
#define ITRC_OUT3_SEL1_IN6_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL1_IN6_SEL1_SHIFT)) & ITRC_OUT3_SEL1_IN6_SEL1_MASK)

#define ITRC_OUT3_SEL1_IN7_SEL1_MASK             (0xC000U)
#define ITRC_OUT3_SEL1_IN7_SEL1_SHIFT            (14U)
/*! IN7_SEL1 - Selects AHB secure bus illegal access event as a trigger source.
 */
#define ITRC_OUT3_SEL1_IN7_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL1_IN7_SEL1_SHIFT)) & ITRC_OUT3_SEL1_IN7_SEL1_MASK)

#define ITRC_OUT3_SEL1_IN8_SEL1_MASK             (0x30000U)
#define ITRC_OUT3_SEL1_IN8_SEL1_SHIFT            (16U)
/*! IN8_SEL1 - Selects CSS error event as a trigger source.
 */
#define ITRC_OUT3_SEL1_IN8_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL1_IN8_SEL1_SHIFT)) & ITRC_OUT3_SEL1_IN8_SEL1_MASK)

#define ITRC_OUT3_SEL1_IN10_SEL1_MASK            (0x300000U)
#define ITRC_OUT3_SEL1_IN10_SEL1_SHIFT           (20U)
/*! IN10_SEL1 - Selects PKC error event as a trigger source.
 */
#define ITRC_OUT3_SEL1_IN10_SEL1(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL1_IN10_SEL1_SHIFT)) & ITRC_OUT3_SEL1_IN10_SEL1_MASK)

#define ITRC_OUT3_SEL1_IN14_SEL1_MASK            (0x30000000U)
#define ITRC_OUT3_SEL1_IN14_SEL1_SHIFT           (28U)
/*! IN14_SEL1 - Selects software event 0 as a trigger source.
 */
#define ITRC_OUT3_SEL1_IN14_SEL1(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL1_IN14_SEL1_SHIFT)) & ITRC_OUT3_SEL1_IN14_SEL1_MASK)

#define ITRC_OUT3_SEL1_IN15_SEL1_MASK            (0xC0000000U)
#define ITRC_OUT3_SEL1_IN15_SEL1_SHIFT           (30U)
/*! IN15_SEL1 - Selects software event 1 as a trigger source.
 */
#define ITRC_OUT3_SEL1_IN15_SEL1(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT3_SEL1_IN15_SEL1_SHIFT)) & ITRC_OUT3_SEL1_IN15_SEL1_MASK)
/*! @} */

/*! @name OUT4_SEL0 - CHIP_RESET Trigger source IN0 to IN15 selector 0 */
/*! @{ */

#define ITRC_OUT4_SEL0_IN0_SEL0_MASK             (0x3U)
#define ITRC_OUT4_SEL0_IN0_SEL0_SHIFT            (0U)
/*! IN0_SEL0 - CSS_RESET Trigger source selector 0 register.
 */
#define ITRC_OUT4_SEL0_IN0_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL0_IN0_SEL0_SHIFT)) & ITRC_OUT4_SEL0_IN0_SEL0_MASK)

#define ITRC_OUT4_SEL0_IN1_SEL0_MASK             (0xCU)
#define ITRC_OUT4_SEL0_IN1_SEL0_SHIFT            (2U)
/*! IN1_SEL0 - Selects tamper pin event as a trigger source.
 */
#define ITRC_OUT4_SEL0_IN1_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL0_IN1_SEL0_SHIFT)) & ITRC_OUT4_SEL0_IN1_SEL0_MASK)

#define ITRC_OUT4_SEL0_IN2_SEL0_MASK             (0x30U)
#define ITRC_OUT4_SEL0_IN2_SEL0_SHIFT            (4U)
/*! IN2_SEL0 - Selects Code Watch Dog event as a trigger source.
 */
#define ITRC_OUT4_SEL0_IN2_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL0_IN2_SEL0_SHIFT)) & ITRC_OUT4_SEL0_IN2_SEL0_MASK)

#define ITRC_OUT4_SEL0_IN3_SEL0_MASK             (0xC0U)
#define ITRC_OUT4_SEL0_IN3_SEL0_SHIFT            (6U)
/*! IN3_SEL0 - Selects low-voltage event on VDD_MAIN rail as a trigger source.
 */
#define ITRC_OUT4_SEL0_IN3_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL0_IN3_SEL0_SHIFT)) & ITRC_OUT4_SEL0_IN3_SEL0_MASK)

#define ITRC_OUT4_SEL0_IN4_SEL0_MASK             (0x300U)
#define ITRC_OUT4_SEL0_IN4_SEL0_SHIFT            (8U)
/*! IN4_SEL0 - Selects low-voltage event on VDD_CORE rail as a trigger source.
 */
#define ITRC_OUT4_SEL0_IN4_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL0_IN4_SEL0_SHIFT)) & ITRC_OUT4_SEL0_IN4_SEL0_MASK)

#define ITRC_OUT4_SEL0_IN5_SEL0_MASK             (0xC00U)
#define ITRC_OUT4_SEL0_IN5_SEL0_SHIFT            (10U)
/*! IN5_SEL0 - Selects Watch Dog timer event as a trigger source.
 */
#define ITRC_OUT4_SEL0_IN5_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL0_IN5_SEL0_SHIFT)) & ITRC_OUT4_SEL0_IN5_SEL0_MASK)

#define ITRC_OUT4_SEL0_IN6_SEL0_MASK             (0x3000U)
#define ITRC_OUT4_SEL0_IN6_SEL0_SHIFT            (12U)
/*! IN6_SEL0 - Selects Flash ECC mismatch event as a trigger source.
 */
#define ITRC_OUT4_SEL0_IN6_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL0_IN6_SEL0_SHIFT)) & ITRC_OUT4_SEL0_IN6_SEL0_MASK)

#define ITRC_OUT4_SEL0_IN7_SEL0_MASK             (0xC000U)
#define ITRC_OUT4_SEL0_IN7_SEL0_SHIFT            (14U)
/*! IN7_SEL0 - Selects AHB secure bus illegal access event as a trigger source.
 */
#define ITRC_OUT4_SEL0_IN7_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL0_IN7_SEL0_SHIFT)) & ITRC_OUT4_SEL0_IN7_SEL0_MASK)

#define ITRC_OUT4_SEL0_IN8_SEL0_MASK             (0x30000U)
#define ITRC_OUT4_SEL0_IN8_SEL0_SHIFT            (16U)
/*! IN8_SEL0 - Selects CSS error event as a trigger source.
 */
#define ITRC_OUT4_SEL0_IN8_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL0_IN8_SEL0_SHIFT)) & ITRC_OUT4_SEL0_IN8_SEL0_MASK)

#define ITRC_OUT4_SEL0_IN10_SEL0_MASK            (0x300000U)
#define ITRC_OUT4_SEL0_IN10_SEL0_SHIFT           (20U)
/*! IN10_SEL0 - Selects PKC error event as a trigger source.
 */
#define ITRC_OUT4_SEL0_IN10_SEL0(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL0_IN10_SEL0_SHIFT)) & ITRC_OUT4_SEL0_IN10_SEL0_MASK)

#define ITRC_OUT4_SEL0_IN14_SEL0_MASK            (0x30000000U)
#define ITRC_OUT4_SEL0_IN14_SEL0_SHIFT           (28U)
/*! IN14_SEL0 - Selects software event 0 as a trigger source.
 */
#define ITRC_OUT4_SEL0_IN14_SEL0(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL0_IN14_SEL0_SHIFT)) & ITRC_OUT4_SEL0_IN14_SEL0_MASK)

#define ITRC_OUT4_SEL0_IN15_SEL0_MASK            (0xC0000000U)
#define ITRC_OUT4_SEL0_IN15_SEL0_SHIFT           (30U)
/*! IN15_SEL0 - Selects software event 1 as a trigger source.
 */
#define ITRC_OUT4_SEL0_IN15_SEL0(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL0_IN15_SEL0_SHIFT)) & ITRC_OUT4_SEL0_IN15_SEL0_MASK)
/*! @} */

/*! @name OUT4_SEL1 - CHIP_RESET Trigger source IN0 to IN15 selector 1 */
/*! @{ */

#define ITRC_OUT4_SEL1_IN0_SEL1_MASK             (0x3U)
#define ITRC_OUT4_SEL1_IN0_SEL1_SHIFT            (0U)
/*! IN0_SEL1 - Selects digital glitch detector as a trigger source.
 */
#define ITRC_OUT4_SEL1_IN0_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL1_IN0_SEL1_SHIFT)) & ITRC_OUT4_SEL1_IN0_SEL1_MASK)

#define ITRC_OUT4_SEL1_IN1_SEL1_MASK             (0xCU)
#define ITRC_OUT4_SEL1_IN1_SEL1_SHIFT            (2U)
/*! IN1_SEL1 - Selects tamper pin event as a trigger source.
 */
#define ITRC_OUT4_SEL1_IN1_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL1_IN1_SEL1_SHIFT)) & ITRC_OUT4_SEL1_IN1_SEL1_MASK)

#define ITRC_OUT4_SEL1_IN2_SEL1_MASK             (0x30U)
#define ITRC_OUT4_SEL1_IN2_SEL1_SHIFT            (4U)
/*! IN2_SEL1 - Selects Code Watch Dog event as a trigger source.
 */
#define ITRC_OUT4_SEL1_IN2_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL1_IN2_SEL1_SHIFT)) & ITRC_OUT4_SEL1_IN2_SEL1_MASK)

#define ITRC_OUT4_SEL1_IN3_SEL1_MASK             (0xC0U)
#define ITRC_OUT4_SEL1_IN3_SEL1_SHIFT            (6U)
/*! IN3_SEL1 - Selects low-voltage event on VDD_MAIN rail as a trigger source.
 */
#define ITRC_OUT4_SEL1_IN3_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL1_IN3_SEL1_SHIFT)) & ITRC_OUT4_SEL1_IN3_SEL1_MASK)

#define ITRC_OUT4_SEL1_IN4_SEL1_MASK             (0x300U)
#define ITRC_OUT4_SEL1_IN4_SEL1_SHIFT            (8U)
/*! IN4_SEL1 - Selects low-voltage event on VDD_CORE rail as a trigger source.
 */
#define ITRC_OUT4_SEL1_IN4_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL1_IN4_SEL1_SHIFT)) & ITRC_OUT4_SEL1_IN4_SEL1_MASK)

#define ITRC_OUT4_SEL1_IN5_SEL1_MASK             (0xC00U)
#define ITRC_OUT4_SEL1_IN5_SEL1_SHIFT            (10U)
/*! IN5_SEL1 - Selects Watch Dog timer event as a trigger source.
 */
#define ITRC_OUT4_SEL1_IN5_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL1_IN5_SEL1_SHIFT)) & ITRC_OUT4_SEL1_IN5_SEL1_MASK)

#define ITRC_OUT4_SEL1_IN6_SEL1_MASK             (0x3000U)
#define ITRC_OUT4_SEL1_IN6_SEL1_SHIFT            (12U)
/*! IN6_SEL1 - Selects Flash ECC mismatch event as a trigger source.
 */
#define ITRC_OUT4_SEL1_IN6_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL1_IN6_SEL1_SHIFT)) & ITRC_OUT4_SEL1_IN6_SEL1_MASK)

#define ITRC_OUT4_SEL1_IN7_SEL1_MASK             (0xC000U)
#define ITRC_OUT4_SEL1_IN7_SEL1_SHIFT            (14U)
/*! IN7_SEL1 - Selects AHB secure bus illegal access event as a trigger source.
 */
#define ITRC_OUT4_SEL1_IN7_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL1_IN7_SEL1_SHIFT)) & ITRC_OUT4_SEL1_IN7_SEL1_MASK)

#define ITRC_OUT4_SEL1_IN8_SEL1_MASK             (0x30000U)
#define ITRC_OUT4_SEL1_IN8_SEL1_SHIFT            (16U)
/*! IN8_SEL1 - Selects CSS error event as a trigger source.
 */
#define ITRC_OUT4_SEL1_IN8_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL1_IN8_SEL1_SHIFT)) & ITRC_OUT4_SEL1_IN8_SEL1_MASK)

#define ITRC_OUT4_SEL1_IN10_SEL1_MASK            (0x300000U)
#define ITRC_OUT4_SEL1_IN10_SEL1_SHIFT           (20U)
/*! IN10_SEL1 - Selects PKC error event as a trigger source.
 */
#define ITRC_OUT4_SEL1_IN10_SEL1(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL1_IN10_SEL1_SHIFT)) & ITRC_OUT4_SEL1_IN10_SEL1_MASK)

#define ITRC_OUT4_SEL1_IN14_SEL1_MASK            (0x30000000U)
#define ITRC_OUT4_SEL1_IN14_SEL1_SHIFT           (28U)
/*! IN14_SEL1 - Selects software event 0 as a trigger source.
 */
#define ITRC_OUT4_SEL1_IN14_SEL1(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL1_IN14_SEL1_SHIFT)) & ITRC_OUT4_SEL1_IN14_SEL1_MASK)

#define ITRC_OUT4_SEL1_IN15_SEL1_MASK            (0xC0000000U)
#define ITRC_OUT4_SEL1_IN15_SEL1_SHIFT           (30U)
/*! IN15_SEL1 - Selects software event 1 as a trigger source.
 */
#define ITRC_OUT4_SEL1_IN15_SEL1(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT4_SEL1_IN15_SEL1_SHIFT)) & ITRC_OUT4_SEL1_IN15_SEL1_MASK)
/*! @} */

/*! @name OUT5_SEL0 - TMPR_OUT0 IN0 to IN15 selector 0 */
/*! @{ */

#define ITRC_OUT5_SEL0_IN0_SEL0_MASK             (0x3U)
#define ITRC_OUT5_SEL0_IN0_SEL0_SHIFT            (0U)
/*! IN0_SEL0 - CSS_RESET Trigger source selector 0 register.
 */
#define ITRC_OUT5_SEL0_IN0_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL0_IN0_SEL0_SHIFT)) & ITRC_OUT5_SEL0_IN0_SEL0_MASK)

#define ITRC_OUT5_SEL0_IN1_SEL0_MASK             (0xCU)
#define ITRC_OUT5_SEL0_IN1_SEL0_SHIFT            (2U)
/*! IN1_SEL0 - Selects tamper pin event as a trigger source.
 */
#define ITRC_OUT5_SEL0_IN1_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL0_IN1_SEL0_SHIFT)) & ITRC_OUT5_SEL0_IN1_SEL0_MASK)

#define ITRC_OUT5_SEL0_IN2_SEL0_MASK             (0x30U)
#define ITRC_OUT5_SEL0_IN2_SEL0_SHIFT            (4U)
/*! IN2_SEL0 - Selects Code Watch Dog event as a trigger source.
 */
#define ITRC_OUT5_SEL0_IN2_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL0_IN2_SEL0_SHIFT)) & ITRC_OUT5_SEL0_IN2_SEL0_MASK)

#define ITRC_OUT5_SEL0_IN3_SEL0_MASK             (0xC0U)
#define ITRC_OUT5_SEL0_IN3_SEL0_SHIFT            (6U)
/*! IN3_SEL0 - Selects low-voltage event on VDD_MAIN rail as a trigger source.
 */
#define ITRC_OUT5_SEL0_IN3_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL0_IN3_SEL0_SHIFT)) & ITRC_OUT5_SEL0_IN3_SEL0_MASK)

#define ITRC_OUT5_SEL0_IN4_SEL0_MASK             (0x300U)
#define ITRC_OUT5_SEL0_IN4_SEL0_SHIFT            (8U)
/*! IN4_SEL0 - Selects low-voltage event on VDD_CORE rail as a trigger source.
 */
#define ITRC_OUT5_SEL0_IN4_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL0_IN4_SEL0_SHIFT)) & ITRC_OUT5_SEL0_IN4_SEL0_MASK)

#define ITRC_OUT5_SEL0_IN5_SEL0_MASK             (0xC00U)
#define ITRC_OUT5_SEL0_IN5_SEL0_SHIFT            (10U)
/*! IN5_SEL0 - Selects Watch Dog timer event as a trigger source.
 */
#define ITRC_OUT5_SEL0_IN5_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL0_IN5_SEL0_SHIFT)) & ITRC_OUT5_SEL0_IN5_SEL0_MASK)

#define ITRC_OUT5_SEL0_IN6_SEL0_MASK             (0x3000U)
#define ITRC_OUT5_SEL0_IN6_SEL0_SHIFT            (12U)
/*! IN6_SEL0 - Selects Flash ECC mismatch event as a trigger source.
 */
#define ITRC_OUT5_SEL0_IN6_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL0_IN6_SEL0_SHIFT)) & ITRC_OUT5_SEL0_IN6_SEL0_MASK)

#define ITRC_OUT5_SEL0_IN7_SEL0_MASK             (0xC000U)
#define ITRC_OUT5_SEL0_IN7_SEL0_SHIFT            (14U)
/*! IN7_SEL0 - Selects AHB secure bus illegal access event as a trigger source.
 */
#define ITRC_OUT5_SEL0_IN7_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL0_IN7_SEL0_SHIFT)) & ITRC_OUT5_SEL0_IN7_SEL0_MASK)

#define ITRC_OUT5_SEL0_IN8_SEL0_MASK             (0x30000U)
#define ITRC_OUT5_SEL0_IN8_SEL0_SHIFT            (16U)
/*! IN8_SEL0 - Selects CSS error event as a trigger source.
 */
#define ITRC_OUT5_SEL0_IN8_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL0_IN8_SEL0_SHIFT)) & ITRC_OUT5_SEL0_IN8_SEL0_MASK)

#define ITRC_OUT5_SEL0_IN10_SEL0_MASK            (0x300000U)
#define ITRC_OUT5_SEL0_IN10_SEL0_SHIFT           (20U)
/*! IN10_SEL0 - Selects PKC error event as a trigger source.
 */
#define ITRC_OUT5_SEL0_IN10_SEL0(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL0_IN10_SEL0_SHIFT)) & ITRC_OUT5_SEL0_IN10_SEL0_MASK)

#define ITRC_OUT5_SEL0_IN14_SEL0_MASK            (0x30000000U)
#define ITRC_OUT5_SEL0_IN14_SEL0_SHIFT           (28U)
/*! IN14_SEL0 - Selects software event 0 as a trigger source.
 */
#define ITRC_OUT5_SEL0_IN14_SEL0(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL0_IN14_SEL0_SHIFT)) & ITRC_OUT5_SEL0_IN14_SEL0_MASK)

#define ITRC_OUT5_SEL0_IN15_SEL0_MASK            (0xC0000000U)
#define ITRC_OUT5_SEL0_IN15_SEL0_SHIFT           (30U)
/*! IN15_SEL0 - Selects software event 1 as a trigger source.
 */
#define ITRC_OUT5_SEL0_IN15_SEL0(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL0_IN15_SEL0_SHIFT)) & ITRC_OUT5_SEL0_IN15_SEL0_MASK)
/*! @} */

/*! @name OUT5_SEL1 - TMPR_OUT0 IN0 to IN15 selector 1 */
/*! @{ */

#define ITRC_OUT5_SEL1_IN0_SEL1_MASK             (0x3U)
#define ITRC_OUT5_SEL1_IN0_SEL1_SHIFT            (0U)
/*! IN0_SEL1 - Selects digital glitch detector as a trigger source.
 */
#define ITRC_OUT5_SEL1_IN0_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL1_IN0_SEL1_SHIFT)) & ITRC_OUT5_SEL1_IN0_SEL1_MASK)

#define ITRC_OUT5_SEL1_IN1_SEL1_MASK             (0xCU)
#define ITRC_OUT5_SEL1_IN1_SEL1_SHIFT            (2U)
/*! IN1_SEL1 - Selects tamper pin event as a trigger source.
 */
#define ITRC_OUT5_SEL1_IN1_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL1_IN1_SEL1_SHIFT)) & ITRC_OUT5_SEL1_IN1_SEL1_MASK)

#define ITRC_OUT5_SEL1_IN2_SEL1_MASK             (0x30U)
#define ITRC_OUT5_SEL1_IN2_SEL1_SHIFT            (4U)
/*! IN2_SEL1 - Selects Code Watch Dog event as a trigger source.
 */
#define ITRC_OUT5_SEL1_IN2_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL1_IN2_SEL1_SHIFT)) & ITRC_OUT5_SEL1_IN2_SEL1_MASK)

#define ITRC_OUT5_SEL1_IN3_SEL1_MASK             (0xC0U)
#define ITRC_OUT5_SEL1_IN3_SEL1_SHIFT            (6U)
/*! IN3_SEL1 - Selects low-voltage event on VDD_MAIN rail as a trigger source.
 */
#define ITRC_OUT5_SEL1_IN3_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL1_IN3_SEL1_SHIFT)) & ITRC_OUT5_SEL1_IN3_SEL1_MASK)

#define ITRC_OUT5_SEL1_IN4_SEL1_MASK             (0x300U)
#define ITRC_OUT5_SEL1_IN4_SEL1_SHIFT            (8U)
/*! IN4_SEL1 - Selects low-voltage event on VDD_CORE rail as a trigger source.
 */
#define ITRC_OUT5_SEL1_IN4_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL1_IN4_SEL1_SHIFT)) & ITRC_OUT5_SEL1_IN4_SEL1_MASK)

#define ITRC_OUT5_SEL1_IN5_SEL1_MASK             (0xC00U)
#define ITRC_OUT5_SEL1_IN5_SEL1_SHIFT            (10U)
/*! IN5_SEL1 - Selects Watch Dog timer event as a trigger source.
 */
#define ITRC_OUT5_SEL1_IN5_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL1_IN5_SEL1_SHIFT)) & ITRC_OUT5_SEL1_IN5_SEL1_MASK)

#define ITRC_OUT5_SEL1_IN6_SEL1_MASK             (0x3000U)
#define ITRC_OUT5_SEL1_IN6_SEL1_SHIFT            (12U)
/*! IN6_SEL1 - Selects Flash ECC mismatch event as a trigger source.
 */
#define ITRC_OUT5_SEL1_IN6_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL1_IN6_SEL1_SHIFT)) & ITRC_OUT5_SEL1_IN6_SEL1_MASK)

#define ITRC_OUT5_SEL1_IN7_SEL1_MASK             (0xC000U)
#define ITRC_OUT5_SEL1_IN7_SEL1_SHIFT            (14U)
/*! IN7_SEL1 - Selects AHB secure bus illegal access event as a trigger source.
 */
#define ITRC_OUT5_SEL1_IN7_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL1_IN7_SEL1_SHIFT)) & ITRC_OUT5_SEL1_IN7_SEL1_MASK)

#define ITRC_OUT5_SEL1_IN8_SEL1_MASK             (0x30000U)
#define ITRC_OUT5_SEL1_IN8_SEL1_SHIFT            (16U)
/*! IN8_SEL1 - Selects CSS error event as a trigger source.
 */
#define ITRC_OUT5_SEL1_IN8_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL1_IN8_SEL1_SHIFT)) & ITRC_OUT5_SEL1_IN8_SEL1_MASK)

#define ITRC_OUT5_SEL1_IN10_SEL1_MASK            (0x300000U)
#define ITRC_OUT5_SEL1_IN10_SEL1_SHIFT           (20U)
/*! IN10_SEL1 - Selects PKC error event as a trigger source.
 */
#define ITRC_OUT5_SEL1_IN10_SEL1(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL1_IN10_SEL1_SHIFT)) & ITRC_OUT5_SEL1_IN10_SEL1_MASK)

#define ITRC_OUT5_SEL1_IN14_SEL1_MASK            (0x30000000U)
#define ITRC_OUT5_SEL1_IN14_SEL1_SHIFT           (28U)
/*! IN14_SEL1 - Selects software event 0 as a trigger source.
 */
#define ITRC_OUT5_SEL1_IN14_SEL1(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL1_IN14_SEL1_SHIFT)) & ITRC_OUT5_SEL1_IN14_SEL1_MASK)

#define ITRC_OUT5_SEL1_IN15_SEL1_MASK            (0xC0000000U)
#define ITRC_OUT5_SEL1_IN15_SEL1_SHIFT           (30U)
/*! IN15_SEL1 - Selects software event 1 as a trigger source.
 */
#define ITRC_OUT5_SEL1_IN15_SEL1(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT5_SEL1_IN15_SEL1_SHIFT)) & ITRC_OUT5_SEL1_IN15_SEL1_MASK)
/*! @} */

/*! @name OUT6_SEL0 - TMPR_OUT1 IN0 to IN15 selector 0 */
/*! @{ */

#define ITRC_OUT6_SEL0_IN0_SEL0_MASK             (0x3U)
#define ITRC_OUT6_SEL0_IN0_SEL0_SHIFT            (0U)
/*! IN0_SEL0 - CSS_RESET Trigger source selector 0 register.
 */
#define ITRC_OUT6_SEL0_IN0_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL0_IN0_SEL0_SHIFT)) & ITRC_OUT6_SEL0_IN0_SEL0_MASK)

#define ITRC_OUT6_SEL0_IN1_SEL0_MASK             (0xCU)
#define ITRC_OUT6_SEL0_IN1_SEL0_SHIFT            (2U)
/*! IN1_SEL0 - Selects tamper pin event as a trigger source.
 */
#define ITRC_OUT6_SEL0_IN1_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL0_IN1_SEL0_SHIFT)) & ITRC_OUT6_SEL0_IN1_SEL0_MASK)

#define ITRC_OUT6_SEL0_IN2_SEL0_MASK             (0x30U)
#define ITRC_OUT6_SEL0_IN2_SEL0_SHIFT            (4U)
/*! IN2_SEL0 - Selects Code Watch Dog event as a trigger source.
 */
#define ITRC_OUT6_SEL0_IN2_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL0_IN2_SEL0_SHIFT)) & ITRC_OUT6_SEL0_IN2_SEL0_MASK)

#define ITRC_OUT6_SEL0_IN3_SEL0_MASK             (0xC0U)
#define ITRC_OUT6_SEL0_IN3_SEL0_SHIFT            (6U)
/*! IN3_SEL0 - Selects low-voltage event on VDD_MAIN rail as a trigger source.
 */
#define ITRC_OUT6_SEL0_IN3_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL0_IN3_SEL0_SHIFT)) & ITRC_OUT6_SEL0_IN3_SEL0_MASK)

#define ITRC_OUT6_SEL0_IN4_SEL0_MASK             (0x300U)
#define ITRC_OUT6_SEL0_IN4_SEL0_SHIFT            (8U)
/*! IN4_SEL0 - Selects low-voltage event on VDD_CORE rail as a trigger source.
 */
#define ITRC_OUT6_SEL0_IN4_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL0_IN4_SEL0_SHIFT)) & ITRC_OUT6_SEL0_IN4_SEL0_MASK)

#define ITRC_OUT6_SEL0_IN5_SEL0_MASK             (0xC00U)
#define ITRC_OUT6_SEL0_IN5_SEL0_SHIFT            (10U)
/*! IN5_SEL0 - Selects Watch Dog timer event as a trigger source.
 */
#define ITRC_OUT6_SEL0_IN5_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL0_IN5_SEL0_SHIFT)) & ITRC_OUT6_SEL0_IN5_SEL0_MASK)

#define ITRC_OUT6_SEL0_IN6_SEL0_MASK             (0x3000U)
#define ITRC_OUT6_SEL0_IN6_SEL0_SHIFT            (12U)
/*! IN6_SEL0 - Selects Flash ECC mismatch event as a trigger source.
 */
#define ITRC_OUT6_SEL0_IN6_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL0_IN6_SEL0_SHIFT)) & ITRC_OUT6_SEL0_IN6_SEL0_MASK)

#define ITRC_OUT6_SEL0_IN7_SEL0_MASK             (0xC000U)
#define ITRC_OUT6_SEL0_IN7_SEL0_SHIFT            (14U)
/*! IN7_SEL0 - Selects AHB secure bus illegal access event as a trigger source.
 */
#define ITRC_OUT6_SEL0_IN7_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL0_IN7_SEL0_SHIFT)) & ITRC_OUT6_SEL0_IN7_SEL0_MASK)

#define ITRC_OUT6_SEL0_IN8_SEL0_MASK             (0x30000U)
#define ITRC_OUT6_SEL0_IN8_SEL0_SHIFT            (16U)
/*! IN8_SEL0 - Selects CSS error event as a trigger source.
 */
#define ITRC_OUT6_SEL0_IN8_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL0_IN8_SEL0_SHIFT)) & ITRC_OUT6_SEL0_IN8_SEL0_MASK)

#define ITRC_OUT6_SEL0_IN10_SEL0_MASK            (0x300000U)
#define ITRC_OUT6_SEL0_IN10_SEL0_SHIFT           (20U)
/*! IN10_SEL0 - Selects PKC error event as a trigger source.
 */
#define ITRC_OUT6_SEL0_IN10_SEL0(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL0_IN10_SEL0_SHIFT)) & ITRC_OUT6_SEL0_IN10_SEL0_MASK)

#define ITRC_OUT6_SEL0_IN14_SEL0_MASK            (0x30000000U)
#define ITRC_OUT6_SEL0_IN14_SEL0_SHIFT           (28U)
/*! IN14_SEL0 - Selects software event 0 as a trigger source.
 */
#define ITRC_OUT6_SEL0_IN14_SEL0(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL0_IN14_SEL0_SHIFT)) & ITRC_OUT6_SEL0_IN14_SEL0_MASK)

#define ITRC_OUT6_SEL0_IN15_SEL0_MASK            (0xC0000000U)
#define ITRC_OUT6_SEL0_IN15_SEL0_SHIFT           (30U)
/*! IN15_SEL0 - Selects software event 1 as a trigger source.
 */
#define ITRC_OUT6_SEL0_IN15_SEL0(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL0_IN15_SEL0_SHIFT)) & ITRC_OUT6_SEL0_IN15_SEL0_MASK)
/*! @} */

/*! @name OUT6_SEL1 - TMPR_OUT1 IN0 to IN15 selector 1 */
/*! @{ */

#define ITRC_OUT6_SEL1_IN0_SEL1_MASK             (0x3U)
#define ITRC_OUT6_SEL1_IN0_SEL1_SHIFT            (0U)
/*! IN0_SEL1 - Selects digital glitch detector as a trigger source.
 */
#define ITRC_OUT6_SEL1_IN0_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL1_IN0_SEL1_SHIFT)) & ITRC_OUT6_SEL1_IN0_SEL1_MASK)

#define ITRC_OUT6_SEL1_IN1_SEL1_MASK             (0xCU)
#define ITRC_OUT6_SEL1_IN1_SEL1_SHIFT            (2U)
/*! IN1_SEL1 - Selects tamper pin event as a trigger source.
 */
#define ITRC_OUT6_SEL1_IN1_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL1_IN1_SEL1_SHIFT)) & ITRC_OUT6_SEL1_IN1_SEL1_MASK)

#define ITRC_OUT6_SEL1_IN2_SEL1_MASK             (0x30U)
#define ITRC_OUT6_SEL1_IN2_SEL1_SHIFT            (4U)
/*! IN2_SEL1 - Selects Code Watch Dog event as a trigger source.
 */
#define ITRC_OUT6_SEL1_IN2_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL1_IN2_SEL1_SHIFT)) & ITRC_OUT6_SEL1_IN2_SEL1_MASK)

#define ITRC_OUT6_SEL1_IN3_SEL1_MASK             (0xC0U)
#define ITRC_OUT6_SEL1_IN3_SEL1_SHIFT            (6U)
/*! IN3_SEL1 - Selects low-voltage event on VDD_MAIN rail as a trigger source.
 */
#define ITRC_OUT6_SEL1_IN3_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL1_IN3_SEL1_SHIFT)) & ITRC_OUT6_SEL1_IN3_SEL1_MASK)

#define ITRC_OUT6_SEL1_IN4_SEL1_MASK             (0x300U)
#define ITRC_OUT6_SEL1_IN4_SEL1_SHIFT            (8U)
/*! IN4_SEL1 - Selects low-voltage event on VDD_CORE rail as a trigger source.
 */
#define ITRC_OUT6_SEL1_IN4_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL1_IN4_SEL1_SHIFT)) & ITRC_OUT6_SEL1_IN4_SEL1_MASK)

#define ITRC_OUT6_SEL1_IN5_SEL1_MASK             (0xC00U)
#define ITRC_OUT6_SEL1_IN5_SEL1_SHIFT            (10U)
/*! IN5_SEL1 - Selects Watch Dog timer event as a trigger source.
 */
#define ITRC_OUT6_SEL1_IN5_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL1_IN5_SEL1_SHIFT)) & ITRC_OUT6_SEL1_IN5_SEL1_MASK)

#define ITRC_OUT6_SEL1_IN6_SEL1_MASK             (0x3000U)
#define ITRC_OUT6_SEL1_IN6_SEL1_SHIFT            (12U)
/*! IN6_SEL1 - Selects Flash ECC mismatch event as a trigger source.
 */
#define ITRC_OUT6_SEL1_IN6_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL1_IN6_SEL1_SHIFT)) & ITRC_OUT6_SEL1_IN6_SEL1_MASK)

#define ITRC_OUT6_SEL1_IN7_SEL1_MASK             (0xC000U)
#define ITRC_OUT6_SEL1_IN7_SEL1_SHIFT            (14U)
/*! IN7_SEL1 - Selects AHB secure bus illegal access event as a trigger source.
 */
#define ITRC_OUT6_SEL1_IN7_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL1_IN7_SEL1_SHIFT)) & ITRC_OUT6_SEL1_IN7_SEL1_MASK)

#define ITRC_OUT6_SEL1_IN8_SEL1_MASK             (0x30000U)
#define ITRC_OUT6_SEL1_IN8_SEL1_SHIFT            (16U)
/*! IN8_SEL1 - Selects CSS error event as a trigger source.
 */
#define ITRC_OUT6_SEL1_IN8_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL1_IN8_SEL1_SHIFT)) & ITRC_OUT6_SEL1_IN8_SEL1_MASK)

#define ITRC_OUT6_SEL1_IN10_SEL1_MASK            (0x300000U)
#define ITRC_OUT6_SEL1_IN10_SEL1_SHIFT           (20U)
/*! IN10_SEL1 - Selects PKC error event as a trigger source.
 */
#define ITRC_OUT6_SEL1_IN10_SEL1(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL1_IN10_SEL1_SHIFT)) & ITRC_OUT6_SEL1_IN10_SEL1_MASK)

#define ITRC_OUT6_SEL1_IN14_SEL1_MASK            (0x30000000U)
#define ITRC_OUT6_SEL1_IN14_SEL1_SHIFT           (28U)
/*! IN14_SEL1 - Selects software event 0 as a trigger source.
 */
#define ITRC_OUT6_SEL1_IN14_SEL1(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL1_IN14_SEL1_SHIFT)) & ITRC_OUT6_SEL1_IN14_SEL1_MASK)

#define ITRC_OUT6_SEL1_IN15_SEL1_MASK            (0xC0000000U)
#define ITRC_OUT6_SEL1_IN15_SEL1_SHIFT           (30U)
/*! IN15_SEL1 - Selects software event 1 as a trigger source.
 */
#define ITRC_OUT6_SEL1_IN15_SEL1(x)              (((uint32_t)(((uint32_t)(x)) << ITRC_OUT6_SEL1_IN15_SEL1_SHIFT)) & ITRC_OUT6_SEL1_IN15_SEL1_MASK)
/*! @} */

/*! @name SW_EVENT0 - Software event 0 */
/*! @{ */

#define ITRC_SW_EVENT0_TRIGGER_SW_EVENT_0_MASK   (0xFFFFFFFFU)
#define ITRC_SW_EVENT0_TRIGGER_SW_EVENT_0_SHIFT  (0U)
/*! TRIGGER_SW_EVENT_0 - Trigger software event 0.
 */
#define ITRC_SW_EVENT0_TRIGGER_SW_EVENT_0(x)     (((uint32_t)(((uint32_t)(x)) << ITRC_SW_EVENT0_TRIGGER_SW_EVENT_0_SHIFT)) & ITRC_SW_EVENT0_TRIGGER_SW_EVENT_0_MASK)
/*! @} */

/*! @name SW_EVENT1 - Software event 1 */
/*! @{ */

#define ITRC_SW_EVENT1_TRIGGER_SW_EVENT_1_MASK   (0xFFFFFFFFU)
#define ITRC_SW_EVENT1_TRIGGER_SW_EVENT_1_SHIFT  (0U)
/*! TRIGGER_SW_EVENT_1 - Trigger software event 1.
 */
#define ITRC_SW_EVENT1_TRIGGER_SW_EVENT_1(x)     (((uint32_t)(((uint32_t)(x)) << ITRC_SW_EVENT1_TRIGGER_SW_EVENT_1_SHIFT)) & ITRC_SW_EVENT1_TRIGGER_SW_EVENT_1_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group ITRC_Register_Masks */


/* ITRC - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral ITRC0 base address */
  #define ITRC0_BASE                               (0x5000F000u)
  /** Peripheral ITRC0 base address */
  #define ITRC0_BASE_NS                            (0x4000F000u)
  /** Peripheral ITRC0 base pointer */
  #define ITRC0                                    ((ITRC_Type *)ITRC0_BASE)
  /** Peripheral ITRC0 base pointer */
  #define ITRC0_NS                                 ((ITRC_Type *)ITRC0_BASE_NS)
  /** Array initializer of ITRC peripheral base addresses */
  #define ITRC_BASE_ADDRS                          { ITRC0_BASE }
  /** Array initializer of ITRC peripheral base pointers */
  #define ITRC_BASE_PTRS                           { ITRC0 }
  /** Array initializer of ITRC peripheral base addresses */
  #define ITRC_BASE_ADDRS_NS                       { ITRC0_BASE_NS }
  /** Array initializer of ITRC peripheral base pointers */
  #define ITRC_BASE_PTRS_NS                        { ITRC0_NS }
#else
  /** Peripheral ITRC0 base address */
  #define ITRC0_BASE                               (0x4000F000u)
  /** Peripheral ITRC0 base pointer */
  #define ITRC0                                    ((ITRC_Type *)ITRC0_BASE)
  /** Array initializer of ITRC peripheral base addresses */
  #define ITRC_BASE_ADDRS                          { ITRC0_BASE }
  /** Array initializer of ITRC peripheral base pointers */
  #define ITRC_BASE_PTRS                           { ITRC0 }
#endif

/*!
 * @}
 */ /* end of group ITRC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LPDAC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LPDAC_Peripheral_Access_Layer LPDAC Peripheral Access Layer
 * @{
 */

/** LPDAC - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version Identifier Register, offset: 0x0 */
  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
  __O  uint32_t DATA;                              /**< Data Register, offset: 0x8 */
  __IO uint32_t GCR;                               /**< Global Control Register, offset: 0xC */
  __IO uint32_t FCR;                               /**< DAC FIFO Control Register, offset: 0x10 */
  __I  uint32_t FPR;                               /**< DAC FIFO Pointer Register, offset: 0x14 */
  __IO uint32_t FSR;                               /**< FIFO Status Register, offset: 0x18 */
  __IO uint32_t IER;                               /**< Interrupt Enable Register, offset: 0x1C */
  __IO uint32_t DER;                               /**< DMA Enable Register, offset: 0x20 */
  __IO uint32_t RCR;                               /**< Reset Control Register, offset: 0x24 */
  __O  uint32_t TCR;                               /**< Trigger Control Register, offset: 0x28 */
  __IO uint32_t PCR;                               /**< Periodic Trigger Control Register, offset: 0x2C */
} LPDAC_Type;

/* ----------------------------------------------------------------------------
   -- LPDAC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LPDAC_Register_Masks LPDAC Register Masks
 * @{
 */

/*! @name VERID - Version Identifier Register */
/*! @{ */

#define LPDAC_VERID_FEATURE_MASK                 (0xFFFFU)
#define LPDAC_VERID_FEATURE_SHIFT                (0U)
/*! FEATURE - Feature Identification Number
 */
#define LPDAC_VERID_FEATURE(x)                   (((uint32_t)(((uint32_t)(x)) << LPDAC_VERID_FEATURE_SHIFT)) & LPDAC_VERID_FEATURE_MASK)

#define LPDAC_VERID_MINOR_MASK                   (0xFF0000U)
#define LPDAC_VERID_MINOR_SHIFT                  (16U)
/*! MINOR - Minor version number
 */
#define LPDAC_VERID_MINOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPDAC_VERID_MINOR_SHIFT)) & LPDAC_VERID_MINOR_MASK)

#define LPDAC_VERID_MAJOR_MASK                   (0xFF000000U)
#define LPDAC_VERID_MAJOR_SHIFT                  (24U)
/*! MAJOR - Major version number
 */
#define LPDAC_VERID_MAJOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPDAC_VERID_MAJOR_SHIFT)) & LPDAC_VERID_MAJOR_MASK)
/*! @} */

/*! @name PARAM - Parameter Register */
/*! @{ */

#define LPDAC_PARAM_FIFOSZ_MASK                  (0x7U)
#define LPDAC_PARAM_FIFOSZ_SHIFT                 (0U)
/*! FIFOSZ - FIFO size
 *  0b000..Reserved
 *  0b001..FIFO depth is 4
 *  0b010..FIFO depth is 8
 *  0b011..FIFO depth is 16
 *  0b100..FIFO depth is 32
 *  0b101..FIFO depth is 64
 *  0b110..FIFO depth is 128
 *  0b111..FIFO depth is 256
 */
#define LPDAC_PARAM_FIFOSZ(x)                    (((uint32_t)(((uint32_t)(x)) << LPDAC_PARAM_FIFOSZ_SHIFT)) & LPDAC_PARAM_FIFOSZ_MASK)
/*! @} */

/*! @name DATA - Data Register */
/*! @{ */

#define LPDAC_DATA_DATA_MASK                     (0xFFFU)
#define LPDAC_DATA_DATA_SHIFT                    (0U)
/*! DATA - FIFO entry or Buffer entry
 */
#define LPDAC_DATA_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPDAC_DATA_DATA_SHIFT)) & LPDAC_DATA_DATA_MASK)
/*! @} */

/*! @name GCR - Global Control Register */
/*! @{ */

#define LPDAC_GCR_DACEN_MASK                     (0x1U)
#define LPDAC_GCR_DACEN_SHIFT                    (0U)
/*! DACEN - DAC Enable
 *  0b0..The DAC system is disabled.
 *  0b1..The DAC system is enabled.
 */
#define LPDAC_GCR_DACEN(x)                       (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_DACEN_SHIFT)) & LPDAC_GCR_DACEN_MASK)

#define LPDAC_GCR_DACRFS_MASK                    (0x6U)
#define LPDAC_GCR_DACRFS_SHIFT                   (1U)
/*! DACRFS - DAC Reference Select
 *  0b00..The DAC selects VREFH1 as the reference voltage.
 *  0b01..The DAC selects VREFH2 as the reference voltage.
 *  0b10..The DAC selects VREFH3 as the reference voltage.
 *  0b11..Reserved.
 */
#define LPDAC_GCR_DACRFS(x)                      (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_DACRFS_SHIFT)) & LPDAC_GCR_DACRFS_MASK)

#define LPDAC_GCR_FIFOEN_MASK                    (0x8U)
#define LPDAC_GCR_FIFOEN_SHIFT                   (3U)
/*! FIFOEN - FIFO Enable
 *  0b0..FIFO mode is disabled and buffer mode is enabled. Any data written to DATA[DATA] goes to buffer then goes to conversion.
 *  0b1..FIFO mode is enabled. Data will be first read from FIFO to buffer then goes to conversion
 */
#define LPDAC_GCR_FIFOEN(x)                      (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_FIFOEN_SHIFT)) & LPDAC_GCR_FIFOEN_MASK)

#define LPDAC_GCR_SWMD_MASK                      (0x10U)
#define LPDAC_GCR_SWMD_SHIFT                     (4U)
/*! SWMD - Swing Back Mode
 *  0b0..Swing back mode disable
 *  0b1..Swing back mode enable
 */
#define LPDAC_GCR_SWMD(x)                        (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_SWMD_SHIFT)) & LPDAC_GCR_SWMD_MASK)

#define LPDAC_GCR_TRGSEL_MASK                    (0x20U)
#define LPDAC_GCR_TRGSEL_SHIFT                   (5U)
/*! TRGSEL - DAC Trigger Select
 *  0b0..The DAC hardware trigger is selected.
 *  0b1..The DAC software trigger is selected.
 */
#define LPDAC_GCR_TRGSEL(x)                      (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_TRGSEL_SHIFT)) & LPDAC_GCR_TRGSEL_MASK)

#define LPDAC_GCR_PTGEN_MASK                     (0x40U)
#define LPDAC_GCR_PTGEN_SHIFT                    (6U)
/*! PTGEN - DAC periodic trigger mode enable
 *  0b0..DAC periodic trigger mode is disabled.
 *  0b1..DAC periodic trigger mode is enabled.
 */
#define LPDAC_GCR_PTGEN(x)                       (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_PTGEN_SHIFT)) & LPDAC_GCR_PTGEN_MASK)

#define LPDAC_GCR_LATCH_CYC_MASK                 (0xF00U)
#define LPDAC_GCR_LATCH_CYC_SHIFT                (8U)
/*! LATCH_CYC - RCLK cycles before data latch
 *  0b0000..Sync time is 1 RCLK cycle, RCLK <= 25MHz
 *  0b0001..Sync time is 2 RCLK cycles, 25MHz < RCLK <= 50MHz
 *  0b0010..Sync time is 3 RCLK cycles, 50MHz < RCLK <= 75MHz
 *  0b0011..Sync time is 4 RCLK cycles, 75MHz < RCLK <= 100MHz
 *  0b0100..Sync time is 5 RCLK cycles, 100MHz < RCLK <= 125MHz
 *  0b0101..Sync time is 6 RCLK cycles, 125MHz < RCLK <= 150MHz
 *  0b0110..Sync time is 7 RCLK cycles, 150MHz < RCLK <= 175MHz
 *  0b0111..Sync time is 8 RCLK cycles, 175MHz < RCLK <= 200MHz
 *  0b1000..Sync time is 9 RCLK cycles, 200MHz < RCLK <= 225MHz
 *  0b1001..Sync time is 10 RCLK cycles, 225MHz < RCLK <= 250MHz
 *  0b1010..Sync time is 11 RCLK cycles, 250MHz < RCLK <= 275MHz
 *  0b1011..Sync time is 12 RCLK cycles, 275MHz < RCLK <= 300MHz
 *  0b1100..Sync time is 13 RCLK cycles, 300MHz < RCLK <= 325MHz
 *  0b1101..Sync time is 14 RCLK cycles, 325MHz < RCLK <= 350MHz
 *  0b1110..Sync time is 15 RCLK cycles, 350MHz < RCLK <= 375MHz
 *  0b1111..Sync time is 16 RCLK cycles, 375MHz < RCLK <= 400MHz
 */
#define LPDAC_GCR_LATCH_CYC(x)                   (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_LATCH_CYC_SHIFT)) & LPDAC_GCR_LATCH_CYC_MASK)

#define LPDAC_GCR_BUF_EN_MASK                    (0x20000U)
#define LPDAC_GCR_BUF_EN_SHIFT                   (17U)
/*! BUF_EN - Buffer Enable
 *  0b0..Opamp is not used as buffer
 *  0b1..Opamp is used as buffer
 */
#define LPDAC_GCR_BUF_EN(x)                      (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_BUF_EN_SHIFT)) & LPDAC_GCR_BUF_EN_MASK)

#define LPDAC_GCR_IREF_PTAT_EXT_SEL_MASK         (0x100000U)
#define LPDAC_GCR_IREF_PTAT_EXT_SEL_SHIFT        (20U)
/*! IREF_PTAT_EXT_SEL - Internal PTAT Current Reference Select
 *  0b0..Internal PTAT Current Reference not selected
 *  0b1..Internal PTAT Current Reference selected
 */
#define LPDAC_GCR_IREF_PTAT_EXT_SEL(x)           (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_IREF_PTAT_EXT_SEL_SHIFT)) & LPDAC_GCR_IREF_PTAT_EXT_SEL_MASK)

#define LPDAC_GCR_IREF_ZTC_EXT_SEL_MASK          (0x200000U)
#define LPDAC_GCR_IREF_ZTC_EXT_SEL_SHIFT         (21U)
/*! IREF_ZTC_EXT_SEL - Internal ZTC Current Reference Select
 *  0b0..Internal ZTC Current Reference not selected
 *  0b1..Internal ZTC Current Reference selected
 */
#define LPDAC_GCR_IREF_ZTC_EXT_SEL(x)            (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_IREF_ZTC_EXT_SEL_SHIFT)) & LPDAC_GCR_IREF_ZTC_EXT_SEL_MASK)

#define LPDAC_GCR_BUF_SPD_CTRL_MASK              (0x800000U)
#define LPDAC_GCR_BUF_SPD_CTRL_SHIFT             (23U)
/*! BUF_SPD_CTRL - OPAMP as buffer, speed control signal
 *  0b0..Lower low power mode
 *  0b1..Low power mode
 */
#define LPDAC_GCR_BUF_SPD_CTRL(x)                (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_BUF_SPD_CTRL_SHIFT)) & LPDAC_GCR_BUF_SPD_CTRL_MASK)
/*! @} */

/*! @name FCR - DAC FIFO Control Register */
/*! @{ */

#define LPDAC_FCR_WML_MASK                       (0xFU)
#define LPDAC_FCR_WML_SHIFT                      (0U)
/*! WML - Watermark Level
 */
#define LPDAC_FCR_WML(x)                         (((uint32_t)(((uint32_t)(x)) << LPDAC_FCR_WML_SHIFT)) & LPDAC_FCR_WML_MASK)
/*! @} */

/*! @name FPR - DAC FIFO Pointer Register */
/*! @{ */

#define LPDAC_FPR_FIFO_RPT_MASK                  (0xFU)
#define LPDAC_FPR_FIFO_RPT_SHIFT                 (0U)
/*! FIFO_RPT - FIFO Read Pointer
 */
#define LPDAC_FPR_FIFO_RPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPDAC_FPR_FIFO_RPT_SHIFT)) & LPDAC_FPR_FIFO_RPT_MASK)

#define LPDAC_FPR_FIFO_WPT_MASK                  (0xF0000U)
#define LPDAC_FPR_FIFO_WPT_SHIFT                 (16U)
/*! FIFO_WPT - FIFO Write Pointer
 */
#define LPDAC_FPR_FIFO_WPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPDAC_FPR_FIFO_WPT_SHIFT)) & LPDAC_FPR_FIFO_WPT_MASK)
/*! @} */

/*! @name FSR - FIFO Status Register */
/*! @{ */

#define LPDAC_FSR_FULL_MASK                      (0x1U)
#define LPDAC_FSR_FULL_SHIFT                     (0U)
/*! FULL - FIFO Full Flag
 *  0b0..FIFO is not full
 *  0b1..FIFO is full
 */
#define LPDAC_FSR_FULL(x)                        (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_FULL_SHIFT)) & LPDAC_FSR_FULL_MASK)

#define LPDAC_FSR_EMPTY_MASK                     (0x2U)
#define LPDAC_FSR_EMPTY_SHIFT                    (1U)
/*! EMPTY - FIFO Empty Flag
 *  0b0..FIFO is not empty
 *  0b1..FIFO is empty
 */
#define LPDAC_FSR_EMPTY(x)                       (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_EMPTY_SHIFT)) & LPDAC_FSR_EMPTY_MASK)

#define LPDAC_FSR_WM_MASK                        (0x4U)
#define LPDAC_FSR_WM_SHIFT                       (2U)
/*! WM - FIFO Watermark Status Flag
 *  0b0..Data in FIFO is more than watermark level
 *  0b1..Data in FIFO is less than or equal to watermark level
 */
#define LPDAC_FSR_WM(x)                          (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_WM_SHIFT)) & LPDAC_FSR_WM_MASK)

#define LPDAC_FSR_SWBK_MASK                      (0x8U)
#define LPDAC_FSR_SWBK_SHIFT                     (3U)
/*! SWBK - Swing Back One Cycle Complete Flag
 *  0b0..No swing back cycle has completed since the last time the flag was cleared.
 *  0b1..At least one swing back cycle has occurred since the last time the flag was cleared.
 */
#define LPDAC_FSR_SWBK(x)                        (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_SWBK_SHIFT)) & LPDAC_FSR_SWBK_MASK)

#define LPDAC_FSR_OF_MASK                        (0x40U)
#define LPDAC_FSR_OF_SHIFT                       (6U)
/*! OF - FIFO Overflow Flag
 *  0b0..No overflow has occurred since the last time the flag was cleared.
 *  0b1..At least one FIFO overflow has occurred since the last time the flag was cleared.
 */
#define LPDAC_FSR_OF(x)                          (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_OF_SHIFT)) & LPDAC_FSR_OF_MASK)

#define LPDAC_FSR_UF_MASK                        (0x80U)
#define LPDAC_FSR_UF_SHIFT                       (7U)
/*! UF - FIFO Underflow Flag
 *  0b0..No underflow has occurred since the last time the flag was cleared.
 *  0b1..At least one trigger underflow has occurred since the last time the flag was cleared.
 */
#define LPDAC_FSR_UF(x)                          (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_UF_SHIFT)) & LPDAC_FSR_UF_MASK)

#define LPDAC_FSR_PTGCOCO_MASK                   (0x100U)
#define LPDAC_FSR_PTGCOCO_SHIFT                  (8U)
/*! PTGCOCO - Period trigger mode conversion complete flag
 *  0b0..PTG mode conversion is not completed or not started.
 *  0b1..PTG mode conversion is completed.
 */
#define LPDAC_FSR_PTGCOCO(x)                     (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_PTGCOCO_SHIFT)) & LPDAC_FSR_PTGCOCO_MASK)
/*! @} */

/*! @name IER - Interrupt Enable Register */
/*! @{ */

#define LPDAC_IER_FULL_IE_MASK                   (0x1U)
#define LPDAC_IER_FULL_IE_SHIFT                  (0U)
/*! FULL_IE - FIFO Full Interrupt Enable
 *  0b0..FIFO Full interrupt is disabled.
 *  0b1..FIFO Full interrupt is enabled.
 */
#define LPDAC_IER_FULL_IE(x)                     (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_FULL_IE_SHIFT)) & LPDAC_IER_FULL_IE_MASK)

#define LPDAC_IER_EMPTY_IE_MASK                  (0x2U)
#define LPDAC_IER_EMPTY_IE_SHIFT                 (1U)
/*! EMPTY_IE - FIFO Empty Interrupt Enable
 *  0b0..FIFO Empty interrupt is disabled.
 *  0b1..FIFO Empty interrupt is enabled.
 */
#define LPDAC_IER_EMPTY_IE(x)                    (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_EMPTY_IE_SHIFT)) & LPDAC_IER_EMPTY_IE_MASK)

#define LPDAC_IER_WM_IE_MASK                     (0x4U)
#define LPDAC_IER_WM_IE_SHIFT                    (2U)
/*! WM_IE - FIFO Watermark Interrupt Enable
 *  0b0..Watermark interrupt is disabled.
 *  0b1..Watermark interrupt is enabled.
 */
#define LPDAC_IER_WM_IE(x)                       (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_WM_IE_SHIFT)) & LPDAC_IER_WM_IE_MASK)

#define LPDAC_IER_SWBK_IE_MASK                   (0x8U)
#define LPDAC_IER_SWBK_IE_SHIFT                  (3U)
/*! SWBK_IE - Swing back One Cycle Complete Interrupt Enable
 *  0b0..Swing back one time complete interrupt is disabled.
 *  0b1..Swing back one time complete interrupt is enabled.
 */
#define LPDAC_IER_SWBK_IE(x)                     (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_SWBK_IE_SHIFT)) & LPDAC_IER_SWBK_IE_MASK)

#define LPDAC_IER_OF_IE_MASK                     (0x40U)
#define LPDAC_IER_OF_IE_SHIFT                    (6U)
/*! OF_IE - FIFO Overflow Interrupt Enable
 *  0b0..Overflow interrupt is disabled
 *  0b1..Overflow interrupt is enabled.
 */
#define LPDAC_IER_OF_IE(x)                       (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_OF_IE_SHIFT)) & LPDAC_IER_OF_IE_MASK)

#define LPDAC_IER_UF_IE_MASK                     (0x80U)
#define LPDAC_IER_UF_IE_SHIFT                    (7U)
/*! UF_IE - FIFO Underflow Interrupt Enable
 *  0b0..Underflow interrupt is disabled.
 *  0b1..Underflow interrupt is enabled.
 */
#define LPDAC_IER_UF_IE(x)                       (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_UF_IE_SHIFT)) & LPDAC_IER_UF_IE_MASK)

#define LPDAC_IER_PTGCOCO_IE_MASK                (0x100U)
#define LPDAC_IER_PTGCOCO_IE_SHIFT               (8U)
/*! PTGCOCO_IE - PTG mode conversion complete interrupt enable
 *  0b0..PTG mode conversion complete interrupt is disabled.
 *  0b1..PTG mode conversion complete interrupt is enabled.
 */
#define LPDAC_IER_PTGCOCO_IE(x)                  (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_PTGCOCO_IE_SHIFT)) & LPDAC_IER_PTGCOCO_IE_MASK)
/*! @} */

/*! @name DER - DMA Enable Register */
/*! @{ */

#define LPDAC_DER_EMPTY_DMAEN_MASK               (0x2U)
#define LPDAC_DER_EMPTY_DMAEN_SHIFT              (1U)
/*! EMPTY_DMAEN - FIFO Empty DMA Enable
 *  0b0..FIFO Empty DMA request is disabled.
 *  0b1..FIFO Empty DMA request is enabled.
 */
#define LPDAC_DER_EMPTY_DMAEN(x)                 (((uint32_t)(((uint32_t)(x)) << LPDAC_DER_EMPTY_DMAEN_SHIFT)) & LPDAC_DER_EMPTY_DMAEN_MASK)

#define LPDAC_DER_WM_DMAEN_MASK                  (0x4U)
#define LPDAC_DER_WM_DMAEN_SHIFT                 (2U)
/*! WM_DMAEN - FIFO Watermark DMA Enable
 *  0b0..Watermark DMA request is disabled.
 *  0b1..Watermark DMA request is enabled.
 */
#define LPDAC_DER_WM_DMAEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPDAC_DER_WM_DMAEN_SHIFT)) & LPDAC_DER_WM_DMAEN_MASK)
/*! @} */

/*! @name RCR - Reset Control Register */
/*! @{ */

#define LPDAC_RCR_SWRST_MASK                     (0x1U)
#define LPDAC_RCR_SWRST_SHIFT                    (0U)
/*! SWRST - Software Reset
 *  0b0..No effect
 *  0b1..Software reset
 */
#define LPDAC_RCR_SWRST(x)                       (((uint32_t)(((uint32_t)(x)) << LPDAC_RCR_SWRST_SHIFT)) & LPDAC_RCR_SWRST_MASK)

#define LPDAC_RCR_FIFORST_MASK                   (0x2U)
#define LPDAC_RCR_FIFORST_SHIFT                  (1U)
/*! FIFORST - FIFO Reset
 *  0b0..No effect
 *  0b1..FIFO reset
 */
#define LPDAC_RCR_FIFORST(x)                     (((uint32_t)(((uint32_t)(x)) << LPDAC_RCR_FIFORST_SHIFT)) & LPDAC_RCR_FIFORST_MASK)
/*! @} */

/*! @name TCR - Trigger Control Register */
/*! @{ */

#define LPDAC_TCR_SWTRG_MASK                     (0x1U)
#define LPDAC_TCR_SWTRG_SHIFT                    (0U)
/*! SWTRG - Software Trigger
 *  0b0..The DAC soft trigger is not valid.
 *  0b1..The DAC soft trigger is valid.
 */
#define LPDAC_TCR_SWTRG(x)                       (((uint32_t)(((uint32_t)(x)) << LPDAC_TCR_SWTRG_SHIFT)) & LPDAC_TCR_SWTRG_MASK)
/*! @} */

/*! @name PCR - Periodic Trigger Control Register */
/*! @{ */

#define LPDAC_PCR_PTG_NUM_MASK                   (0xFFFFU)
#define LPDAC_PCR_PTG_NUM_SHIFT                  (0U)
/*! PTG_NUM - Periodic trigger number
 */
#define LPDAC_PCR_PTG_NUM(x)                     (((uint32_t)(((uint32_t)(x)) << LPDAC_PCR_PTG_NUM_SHIFT)) & LPDAC_PCR_PTG_NUM_MASK)

#define LPDAC_PCR_PTG_PERIOD_MASK                (0xFFFF0000U)
#define LPDAC_PCR_PTG_PERIOD_SHIFT               (16U)
/*! PTG_PERIOD - Periodic trigger period width
 */
#define LPDAC_PCR_PTG_PERIOD(x)                  (((uint32_t)(((uint32_t)(x)) << LPDAC_PCR_PTG_PERIOD_SHIFT)) & LPDAC_PCR_PTG_PERIOD_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LPDAC_Register_Masks */


/* LPDAC - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral DAC0 base address */
  #define DAC0_BASE                                (0x500B2000u)
  /** Peripheral DAC0 base address */
  #define DAC0_BASE_NS                             (0x400B2000u)
  /** Peripheral DAC0 base pointer */
  #define DAC0                                     ((LPDAC_Type *)DAC0_BASE)
  /** Peripheral DAC0 base pointer */
  #define DAC0_NS                                  ((LPDAC_Type *)DAC0_BASE_NS)
  /** Peripheral DAC1 base address */
  #define DAC1_BASE                                (0x500B6000u)
  /** Peripheral DAC1 base address */
  #define DAC1_BASE_NS                             (0x400B6000u)
  /** Peripheral DAC1 base pointer */
  #define DAC1                                     ((LPDAC_Type *)DAC1_BASE)
  /** Peripheral DAC1 base pointer */
  #define DAC1_NS                                  ((LPDAC_Type *)DAC1_BASE_NS)
  /** Peripheral DAC2 base address */
  #define DAC2_BASE                                (0x500B9000u)
  /** Peripheral DAC2 base address */
  #define DAC2_BASE_NS                             (0x400B9000u)
  /** Peripheral DAC2 base pointer */
  #define DAC2                                     ((LPDAC_Type *)DAC2_BASE)
  /** Peripheral DAC2 base pointer */
  #define DAC2_NS                                  ((LPDAC_Type *)DAC2_BASE_NS)
  /** Array initializer of LPDAC peripheral base addresses */
  #define LPDAC_BASE_ADDRS                         { DAC0_BASE, DAC1_BASE, DAC2_BASE }
  /** Array initializer of LPDAC peripheral base pointers */
  #define LPDAC_BASE_PTRS                          { DAC0, DAC1, DAC2 }
  /** Array initializer of LPDAC peripheral base addresses */
  #define LPDAC_BASE_ADDRS_NS                      { DAC0_BASE_NS, DAC1_BASE_NS, DAC2_BASE_NS }
  /** Array initializer of LPDAC peripheral base pointers */
  #define LPDAC_BASE_PTRS_NS                       { DAC0_NS, DAC1_NS, DAC2_NS }
#else
  /** Peripheral DAC0 base address */
  #define DAC0_BASE                                (0x400B2000u)
  /** Peripheral DAC0 base pointer */
  #define DAC0                                     ((LPDAC_Type *)DAC0_BASE)
  /** Peripheral DAC1 base address */
  #define DAC1_BASE                                (0x400B6000u)
  /** Peripheral DAC1 base pointer */
  #define DAC1                                     ((LPDAC_Type *)DAC1_BASE)
  /** Peripheral DAC2 base address */
  #define DAC2_BASE                                (0x400B9000u)
  /** Peripheral DAC2 base pointer */
  #define DAC2                                     ((LPDAC_Type *)DAC2_BASE)
  /** Array initializer of LPDAC peripheral base addresses */
  #define LPDAC_BASE_ADDRS                         { DAC0_BASE, DAC1_BASE, DAC2_BASE }
  /** Array initializer of LPDAC peripheral base pointers */
  #define LPDAC_BASE_PTRS                          { DAC0, DAC1, DAC2 }
#endif
/** Interrupt vectors for the LPDAC peripheral type */
#define LPDAC_IRQS                               { DAC0_IRQn, DAC1_IRQn, DAC2_IRQn }

/*!
 * @}
 */ /* end of group LPDAC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- MRT Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer
 * @{
 */

/** MRT - Register Layout Typedef */
typedef struct {
  struct {                                         /* offset: 0x0, array step: 0x10 */
    __IO uint32_t INTVAL;                            /**< Time Interval Value, array offset: 0x0, array step: 0x10 */
    __I  uint32_t TIMER;                             /**< Timer, array offset: 0x4, array step: 0x10 */
    __IO uint32_t CTRL;                              /**< Control, array offset: 0x8, array step: 0x10 */
    __IO uint32_t STAT;                              /**< Status, array offset: 0xC, array step: 0x10 */
  } CHANNEL[4];
       uint8_t RESERVED_0[176];
  __IO uint32_t MODCFG;                            /**< Module Configuration, offset: 0xF0 */
  __I  uint32_t IDLE_CH;                           /**< Idle Channel, offset: 0xF4 */
  __IO uint32_t IRQ_FLAG;                          /**< Global Interrupt Flag, offset: 0xF8 */
  __I  uint32_t ID_CODE;                           /**< Multi-Rate Timer ID code, offset: 0xFC */
} MRT_Type;

/* ----------------------------------------------------------------------------
   -- MRT Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup MRT_Register_Masks MRT Register Masks
 * @{
 */

/*! @name CHANNEL_INTVAL - Time Interval Value */
/*! @{ */

#define MRT_CHANNEL_INTVAL_IVALUE_MASK           (0xFFFFFFU)
#define MRT_CHANNEL_INTVAL_IVALUE_SHIFT          (0U)
/*! IVALUE - Time interval load value.
 */
#define MRT_CHANNEL_INTVAL_IVALUE(x)             (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK)

#define MRT_CHANNEL_INTVAL_LOAD_MASK             (0x80000000U)
#define MRT_CHANNEL_INTVAL_LOAD_SHIFT            (31U)
/*! LOAD - Determines how the timer interval value (IVALUE -1) is loaded into the TIMER n register.
 *  0b0..No force load.
 *  0b1..Force load. T
 */
#define MRT_CHANNEL_INTVAL_LOAD(x)               (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK)
/*! @} */

/* The count of MRT_CHANNEL_INTVAL */
#define MRT_CHANNEL_INTVAL_COUNT                 (4U)

/*! @name CHANNEL_TIMER - Timer */
/*! @{ */

#define MRT_CHANNEL_TIMER_VALUE_MASK             (0xFFFFFFU)
#define MRT_CHANNEL_TIMER_VALUE_SHIFT            (0U)
/*! VALUE - Holds the current timer value of the down-counter.
 */
#define MRT_CHANNEL_TIMER_VALUE(x)               (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK)
/*! @} */

/* The count of MRT_CHANNEL_TIMER */
#define MRT_CHANNEL_TIMER_COUNT                  (4U)

/*! @name CHANNEL_CTRL - Control */
/*! @{ */

#define MRT_CHANNEL_CTRL_INTEN_MASK              (0x1U)
#define MRT_CHANNEL_CTRL_INTEN_SHIFT             (0U)
/*! INTEN - Enable the TIMER n interrupt.
 *  0b0..Disabled. TIMER n interrupt is disabled.
 *  0b1..Enabled. TIMER n interrupt is enabled.
 */
#define MRT_CHANNEL_CTRL_INTEN(x)                (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK)

#define MRT_CHANNEL_CTRL_MODE_MASK               (0x6U)
#define MRT_CHANNEL_CTRL_MODE_SHIFT              (1U)
/*! MODE - Selects the timer mode
 *  0b00..Repeat interrupt mode
 *  0b01..One-shot interrupt mode
 *  0b10..One-shot stall mode
 *  0b11..Reserved
 */
#define MRT_CHANNEL_CTRL_MODE(x)                 (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK)
/*! @} */

/* The count of MRT_CHANNEL_CTRL */
#define MRT_CHANNEL_CTRL_COUNT                   (4U)

/*! @name CHANNEL_STAT - Status */
/*! @{ */

#define MRT_CHANNEL_STAT_INTFLAG_MASK            (0x1U)
#define MRT_CHANNEL_STAT_INTFLAG_SHIFT           (0U)
/*! INTFLAG - Monitors the interrupt flag
 *  0b0..No pending interrupt. Writing a zero is equivalent to no operation.
 *  0b1..Pending interrupt.
 */
#define MRT_CHANNEL_STAT_INTFLAG(x)              (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK)

#define MRT_CHANNEL_STAT_RUN_MASK                (0x2U)
#define MRT_CHANNEL_STAT_RUN_SHIFT               (1U)
/*! RUN - Indicates the state of TIMER n. RUN bit is read-only.
 *  0b0..Idle state. TIMER n has stopped.
 *  0b1..Running. TIMER n is running.
 */
#define MRT_CHANNEL_STAT_RUN(x)                  (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK)

#define MRT_CHANNEL_STAT_INUSE_MASK              (0x4U)
#define MRT_CHANNEL_STAT_INUSE_SHIFT             (2U)
/*! INUSE - Channel-In-Use flag
 *  0b0..This timer channel is not in use.
 *  0b1..This timer channel is in use. Writing a 1 to this bit clears the status.
 */
#define MRT_CHANNEL_STAT_INUSE(x)                (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK)
/*! @} */

/* The count of MRT_CHANNEL_STAT */
#define MRT_CHANNEL_STAT_COUNT                   (4U)

/*! @name MODCFG - Module Configuration */
/*! @{ */

#define MRT_MODCFG_NOC_MASK                      (0xFU)
#define MRT_MODCFG_NOC_SHIFT                     (0U)
/*! NOC - Number Of Channels: identifies the number of channels in this MRT. (Minus 1 encoded)
 */
#define MRT_MODCFG_NOC(x)                        (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK)

#define MRT_MODCFG_NOB_MASK                      (0x1F0U)
#define MRT_MODCFG_NOB_SHIFT                     (4U)
/*! NOB - Number Of Bits: identifies the number of timer bits in this MRT. (24 bits on this device)
 */
#define MRT_MODCFG_NOB(x)                        (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK)

#define MRT_MODCFG_MULTITASK_MASK                (0x80000000U)
#define MRT_MODCFG_MULTITASK_SHIFT               (31U)
/*! MULTITASK - Selects the operating mode for the INUSE flags and the IDLE_CH register.
 *  0b0..Hardware status mode. In this mode, the INUSE(n) flags for all channels are reset.
 *  0b1..Multi-task mode
 */
#define MRT_MODCFG_MULTITASK(x)                  (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK)
/*! @} */

/*! @name IDLE_CH - Idle Channel */
/*! @{ */

#define MRT_IDLE_CH_CHAN_MASK                    (0xF0U)
#define MRT_IDLE_CH_CHAN_SHIFT                   (4U)
/*! CHAN - Idle channel.
 */
#define MRT_IDLE_CH_CHAN(x)                      (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK)
/*! @} */

/*! @name IRQ_FLAG - Global Interrupt Flag */
/*! @{ */

#define MRT_IRQ_FLAG_GFLAG0_MASK                 (0x1U)
#define MRT_IRQ_FLAG_GFLAG0_SHIFT                (0U)
/*! GFLAG0 - Monitors the interrupt flag of TIMER0.
 *  0b0..No pending interrupt. Writing a zero is equivalent to no operation.
 *  0b1..Pending interrupt
 */
#define MRT_IRQ_FLAG_GFLAG0(x)                   (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK)

#define MRT_IRQ_FLAG_GFLAG1_MASK                 (0x2U)
#define MRT_IRQ_FLAG_GFLAG1_SHIFT                (1U)
/*! GFLAG1 - Monitors the interrupt flag of TIMER1, and acts similarly to channel 0.
 */
#define MRT_IRQ_FLAG_GFLAG1(x)                   (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK)

#define MRT_IRQ_FLAG_GFLAG2_MASK                 (0x4U)
#define MRT_IRQ_FLAG_GFLAG2_SHIFT                (2U)
/*! GFLAG2 - Monitors the interrupt flag of TIMER2, and acts similarly to channel 0.
 */
#define MRT_IRQ_FLAG_GFLAG2(x)                   (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK)

#define MRT_IRQ_FLAG_GFLAG3_MASK                 (0x8U)
#define MRT_IRQ_FLAG_GFLAG3_SHIFT                (3U)
/*! GFLAG3 - Monitors the interrupt flag of TIMER3, and acts similarly to channel 0.
 */
#define MRT_IRQ_FLAG_GFLAG3(x)                   (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK)
/*! @} */

/*! @name ID_CODE - Multi-Rate Timer ID code */
/*! @{ */

#define MRT_ID_CODE_ID_CODE_MASK                 (0xFFFFFFFFU)
#define MRT_ID_CODE_ID_CODE_SHIFT                (0U)
/*! ID_CODE - Multi-Rate Timer ID code
 */
#define MRT_ID_CODE_ID_CODE(x)                   (((uint32_t)(((uint32_t)(x)) << MRT_ID_CODE_ID_CODE_SHIFT)) & MRT_ID_CODE_ID_CODE_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group MRT_Register_Masks */


/* MRT - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral MRT0 base address */
  #define MRT0_BASE                                (0x5000D000u)
  /** Peripheral MRT0 base address */
  #define MRT0_BASE_NS                             (0x4000D000u)
  /** Peripheral MRT0 base pointer */
  #define MRT0                                     ((MRT_Type *)MRT0_BASE)
  /** Peripheral MRT0 base pointer */
  #define MRT0_NS                                  ((MRT_Type *)MRT0_BASE_NS)
  /** Array initializer of MRT peripheral base addresses */
  #define MRT_BASE_ADDRS                           { MRT0_BASE }
  /** Array initializer of MRT peripheral base pointers */
  #define MRT_BASE_PTRS                            { MRT0 }
  /** Array initializer of MRT peripheral base addresses */
  #define MRT_BASE_ADDRS_NS                        { MRT0_BASE_NS }
  /** Array initializer of MRT peripheral base pointers */
  #define MRT_BASE_PTRS_NS                         { MRT0_NS }
#else
  /** Peripheral MRT0 base address */
  #define MRT0_BASE                                (0x4000D000u)
  /** Peripheral MRT0 base pointer */
  #define MRT0                                     ((MRT_Type *)MRT0_BASE)
  /** Array initializer of MRT peripheral base addresses */
  #define MRT_BASE_ADDRS                           { MRT0_BASE }
  /** Array initializer of MRT peripheral base pointers */
  #define MRT_BASE_PTRS                            { MRT0 }
#endif
/** Interrupt vectors for the MRT peripheral type */
#define MRT_IRQS                                 { MRT0_IRQn }

/*!
 * @}
 */ /* end of group MRT_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- OPAMP Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup OPAMP_Peripheral_Access_Layer OPAMP Peripheral Access Layer
 * @{
 */

/** OPAMP - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
  __IO uint32_t OPAMP_CTR;                         /**< OPAMP control register, offset: 0x8 */
} OPAMP_Type;

/* ----------------------------------------------------------------------------
   -- OPAMP Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup OPAMP_Register_Masks OPAMP Register Masks
 * @{
 */

/*! @name VERID - Version ID Register */
/*! @{ */

#define OPAMP_VERID_FEATURE_MASK                 (0xFFFFU)
#define OPAMP_VERID_FEATURE_SHIFT                (0U)
/*! FEATURE - Feature Specification Number
 */
#define OPAMP_VERID_FEATURE(x)                   (((uint32_t)(((uint32_t)(x)) << OPAMP_VERID_FEATURE_SHIFT)) & OPAMP_VERID_FEATURE_MASK)

#define OPAMP_VERID_MINOR_MASK                   (0xFF0000U)
#define OPAMP_VERID_MINOR_SHIFT                  (16U)
/*! MINOR - Minor Version Number
 */
#define OPAMP_VERID_MINOR(x)                     (((uint32_t)(((uint32_t)(x)) << OPAMP_VERID_MINOR_SHIFT)) & OPAMP_VERID_MINOR_MASK)

#define OPAMP_VERID_MAJOR_MASK                   (0xFF000000U)
#define OPAMP_VERID_MAJOR_SHIFT                  (24U)
/*! MAJOR - Major Version Number
 */
#define OPAMP_VERID_MAJOR(x)                     (((uint32_t)(((uint32_t)(x)) << OPAMP_VERID_MAJOR_SHIFT)) & OPAMP_VERID_MAJOR_MASK)
/*! @} */

/*! @name PARAM - Parameter Register */
/*! @{ */

#define OPAMP_PARAM_PGA_FUNCTION_MASK            (0x1U)
#define OPAMP_PARAM_PGA_FUNCTION_SHIFT           (0U)
/*! PGA_FUNCTION - PGA Function Option
 *  0b0..Core amplifier is enabled.
 *  0b1..PGA function is enabled.
 */
#define OPAMP_PARAM_PGA_FUNCTION(x)              (((uint32_t)(((uint32_t)(x)) << OPAMP_PARAM_PGA_FUNCTION_SHIFT)) & OPAMP_PARAM_PGA_FUNCTION_MASK)
/*! @} */

/*! @name OPAMP_CTR - OPAMP control register */
/*! @{ */

#define OPAMP_OPAMP_CTR_EN_MASK                  (0x1U)
#define OPAMP_OPAMP_CTR_EN_SHIFT                 (0U)
/*! EN - OPAMP Enable
 *  0b0..OPAMP is disabled
 *  0b1..OPAMP is enabled
 */
#define OPAMP_OPAMP_CTR_EN(x)                    (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_EN_SHIFT)) & OPAMP_OPAMP_CTR_EN_MASK)

#define OPAMP_OPAMP_CTR_MODE_MASK                (0x2U)
#define OPAMP_OPAMP_CTR_MODE_SHIFT               (1U)
/*! MODE - Mode Selection
 *  0b0..Low noise mode.
 *  0b1..High speed mode.
 */
#define OPAMP_OPAMP_CTR_MODE(x)                  (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_MODE_SHIFT)) & OPAMP_OPAMP_CTR_MODE_MASK)

#define OPAMP_OPAMP_CTR_BIASC_MASK               (0xCU)
#define OPAMP_OPAMP_CTR_BIASC_SHIFT              (2U)
/*! BIASC - Bias Current Trim Selection
 *  0b00..Default.
 *  0b01..Increase current.
 *  0b10..Decrease current.
 *  0b11..Further decrease current.
 */
#define OPAMP_OPAMP_CTR_BIASC(x)                 (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_BIASC_SHIFT)) & OPAMP_OPAMP_CTR_BIASC_MASK)

#define OPAMP_OPAMP_CTR_INTREF_MASK              (0x30U)
#define OPAMP_OPAMP_CTR_INTREF_SHIFT             (4U)
/*! INTREF - Internal Reference Voltage Selection
 *  0b00..Select vdda/2.
 *  0b01..Select vdda_3v.
 *  0b10..Select vssa_3v.
 *  0b11..Not allowed.
 */
#define OPAMP_OPAMP_CTR_INTREF(x)                (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_INTREF_SHIFT)) & OPAMP_OPAMP_CTR_INTREF_MASK)

#define OPAMP_OPAMP_CTR_ADCSW_MASK               (0x10000U)
#define OPAMP_OPAMP_CTR_ADCSW_SHIFT              (16U)
/*! ADCSW - ADC Channel Switch
 */
#define OPAMP_OPAMP_CTR_ADCSW(x)                 (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_ADCSW_SHIFT)) & OPAMP_OPAMP_CTR_ADCSW_MASK)

#define OPAMP_OPAMP_CTR_PREF_MASK                (0x60000U)
#define OPAMP_OPAMP_CTR_PREF_SHIFT               (17U)
/*! PREF - Positive Reference Voltage Selection
 *  0b00..Select vrefh3.
 *  0b01..Select vrefh0.
 *  0b10..Select vrefh1.
 *  0b11..Reserved.
 */
#define OPAMP_OPAMP_CTR_PREF(x)                  (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_PREF_SHIFT)) & OPAMP_OPAMP_CTR_PREF_MASK)

#define OPAMP_OPAMP_CTR_PGAIN_MASK               (0x700000U)
#define OPAMP_OPAMP_CTR_PGAIN_SHIFT              (20U)
/*! PGAIN - Positive PGA Selection.
 *  0b000..Reserved.
 *  0b001..Inverting gain application 2X.
 *  0b010..Inverting gain application 3X.
 *  0b011..Inverting gain application 5X.
 *  0b100..Inverting gain application 9X.
 *  0b101..Inverting gain application 17X.
 *  0b110..Inverting gain application 34X.
 *  0b111..Inverting gain application 65X.
 */
#define OPAMP_OPAMP_CTR_PGAIN(x)                 (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_PGAIN_SHIFT)) & OPAMP_OPAMP_CTR_PGAIN_MASK)

#define OPAMP_OPAMP_CTR_NGAIN_MASK               (0x7000000U)
#define OPAMP_OPAMP_CTR_NGAIN_SHIFT              (24U)
/*! NGAIN - Negative PGA selection
 *  0b000..Buffer.
 *  0b001..Inverting gain application -1X.
 *  0b010..Inverting gain application -2X.
 *  0b011..Inverting gain application -4X.
 *  0b100..Inverting gain application -8X.
 *  0b101..Inverting gain application -16X.
 *  0b110..Inverting gain application -33X.
 *  0b111..Inverting gain application -64X.
 */
#define OPAMP_OPAMP_CTR_NGAIN(x)                 (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_NGAIN_SHIFT)) & OPAMP_OPAMP_CTR_NGAIN_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group OPAMP_Register_Masks */


/* OPAMP - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral OPAMP0 base address */
  #define OPAMP0_BASE                              (0x500B4000u)
  /** Peripheral OPAMP0 base address */
  #define OPAMP0_BASE_NS                           (0x400B4000u)
  /** Peripheral OPAMP0 base pointer */
  #define OPAMP0                                   ((OPAMP_Type *)OPAMP0_BASE)
  /** Peripheral OPAMP0 base pointer */
  #define OPAMP0_NS                                ((OPAMP_Type *)OPAMP0_BASE_NS)
  /** Peripheral OPAMP1 base address */
  #define OPAMP1_BASE                              (0x500B8000u)
  /** Peripheral OPAMP1 base address */
  #define OPAMP1_BASE_NS                           (0x400B8000u)
  /** Peripheral OPAMP1 base pointer */
  #define OPAMP1                                   ((OPAMP_Type *)OPAMP1_BASE)
  /** Peripheral OPAMP1 base pointer */
  #define OPAMP1_NS                                ((OPAMP_Type *)OPAMP1_BASE_NS)
  /** Peripheral OPAMP2 base address */
  #define OPAMP2_BASE                              (0x500BB000u)
  /** Peripheral OPAMP2 base address */
  #define OPAMP2_BASE_NS                           (0x400BB000u)
  /** Peripheral OPAMP2 base pointer */
  #define OPAMP2                                   ((OPAMP_Type *)OPAMP2_BASE)
  /** Peripheral OPAMP2 base pointer */
  #define OPAMP2_NS                                ((OPAMP_Type *)OPAMP2_BASE_NS)
  /** Array initializer of OPAMP peripheral base addresses */
  #define OPAMP_BASE_ADDRS                         { OPAMP0_BASE, OPAMP1_BASE, OPAMP2_BASE }
  /** Array initializer of OPAMP peripheral base pointers */
  #define OPAMP_BASE_PTRS                          { OPAMP0, OPAMP1, OPAMP2 }
  /** Array initializer of OPAMP peripheral base addresses */
  #define OPAMP_BASE_ADDRS_NS                      { OPAMP0_BASE_NS, OPAMP1_BASE_NS, OPAMP2_BASE_NS }
  /** Array initializer of OPAMP peripheral base pointers */
  #define OPAMP_BASE_PTRS_NS                       { OPAMP0_NS, OPAMP1_NS, OPAMP2_NS }
#else
  /** Peripheral OPAMP0 base address */
  #define OPAMP0_BASE                              (0x400B4000u)
  /** Peripheral OPAMP0 base pointer */
  #define OPAMP0                                   ((OPAMP_Type *)OPAMP0_BASE)
  /** Peripheral OPAMP1 base address */
  #define OPAMP1_BASE                              (0x400B8000u)
  /** Peripheral OPAMP1 base pointer */
  #define OPAMP1                                   ((OPAMP_Type *)OPAMP1_BASE)
  /** Peripheral OPAMP2 base address */
  #define OPAMP2_BASE                              (0x400BB000u)
  /** Peripheral OPAMP2 base pointer */
  #define OPAMP2                                   ((OPAMP_Type *)OPAMP2_BASE)
  /** Array initializer of OPAMP peripheral base addresses */
  #define OPAMP_BASE_ADDRS                         { OPAMP0_BASE, OPAMP1_BASE, OPAMP2_BASE }
  /** Array initializer of OPAMP peripheral base pointers */
  #define OPAMP_BASE_PTRS                          { OPAMP0, OPAMP1, OPAMP2 }
#endif

/*!
 * @}
 */ /* end of group OPAMP_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- OSTIMER Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup OSTIMER_Peripheral_Access_Layer OSTIMER Peripheral Access Layer
 * @{
 */

/** OSTIMER - Register Layout Typedef */
typedef struct {
  __I  uint32_t EVTIMERL;                          /**< EVTIMER Low Register, offset: 0x0 */
  __I  uint32_t EVTIMERH;                          /**< EVTIMER High Register, offset: 0x4 */
  __I  uint32_t CAPTURE_L;                         /**< Local Capture Low Register for CPU, offset: 0x8 */
  __I  uint32_t CAPTURE_H;                         /**< Local Capture High Register for CPU, offset: 0xC */
  __IO uint32_t MATCH_L;                           /**< Local Match Low Register for CPU, offset: 0x10 */
  __IO uint32_t MATCH_H;                           /**< Local Match High Register for CPU, offset: 0x14 */
       uint8_t RESERVED_0[4];
  __IO uint32_t OSEVENT_CTRL;                      /**< OS Event Timer Control Register for CPU, offset: 0x1C */
} OSTIMER_Type;

/* ----------------------------------------------------------------------------
   -- OSTIMER Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup OSTIMER_Register_Masks OSTIMER Register Masks
 * @{
 */

/*! @name EVTIMERL - EVTIMER Low Register */
/*! @{ */

#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK (0xFFFFFFFFU)
#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT (0U)
/*! EVTIMER_COUNT_VALUE - EVTimer Count value
 */
#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE(x)  (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK)
/*! @} */

/*! @name EVTIMERH - EVTIMER High Register */
/*! @{ */

#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK (0xFFFFFFFFU)
#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT (0U)
/*! EVTIMER_COUNT_VALUE - EVTimer Count value
 */
#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE(x)  (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK)
/*! @} */

/*! @name CAPTURE_L - Local Capture Low Register for CPU */
/*! @{ */

#define OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK     (0xFFFFFFFFU)
#define OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT    (0U)
/*! CAPTURE_VALUE - EVTimer Capture value
 */
#define OSTIMER_CAPTURE_L_CAPTURE_VALUE(x)       (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK)
/*! @} */

/*! @name CAPTURE_H - Local Capture High Register for CPU */
/*! @{ */

#define OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK     (0xFFFFFFFFU)
#define OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT    (0U)
/*! CAPTURE_VALUE - EVTimer Capture value
 */
#define OSTIMER_CAPTURE_H_CAPTURE_VALUE(x)       (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK)
/*! @} */

/*! @name MATCH_L - Local Match Low Register for CPU */
/*! @{ */

#define OSTIMER_MATCH_L_MATCH_VALUE_MASK         (0xFFFFFFFFU)
#define OSTIMER_MATCH_L_MATCH_VALUE_SHIFT        (0U)
/*! MATCH_VALUE - EVTimer Match value
 */
#define OSTIMER_MATCH_L_MATCH_VALUE(x)           (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_L_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_L_MATCH_VALUE_MASK)
/*! @} */

/*! @name MATCH_H - Local Match High Register for CPU */
/*! @{ */

#define OSTIMER_MATCH_H_MATCH_VALUE_MASK         (0xFFFFFFFFU)
#define OSTIMER_MATCH_H_MATCH_VALUE_SHIFT        (0U)
/*! MATCH_VALUE - EVTimer Match value
 */
#define OSTIMER_MATCH_H_MATCH_VALUE(x)           (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_H_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_H_MATCH_VALUE_MASK)
/*! @} */

/*! @name OSEVENT_CTRL - OS Event Timer Control Register for CPU */
/*! @{ */

#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK (0x1U)
#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT (0U)
/*! OSTIMER_INTRFLAG - Interrupt Flag
 */
#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK)

#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK (0x2U)
#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT (1U)
/*! OSTIMER_INTENA - Interrupt/Wake-up Request
 *  0b0..Interrupt/wake-up requests due to the OSTIMER_INTR flag are blocked.
 *  0b1..An interrupt/wake-up request to the domain processor will be asserted when the OSTIMER_INTR flag is set.
 */
#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA(x)   (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK)

#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK   (0x4U)
#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT  (2U)
/*! MATCH_WR_RDY - EVTimer Match Write Ready
 */
#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY(x)     (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT)) & OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group OSTIMER_Register_Masks */


/* OSTIMER - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral OSTIMER0 base address */
  #define OSTIMER0_BASE                            (0x5002D000u)
  /** Peripheral OSTIMER0 base address */
  #define OSTIMER0_BASE_NS                         (0x4002D000u)
  /** Peripheral OSTIMER0 base pointer */
  #define OSTIMER0                                 ((OSTIMER_Type *)OSTIMER0_BASE)
  /** Peripheral OSTIMER0 base pointer */
  #define OSTIMER0_NS                              ((OSTIMER_Type *)OSTIMER0_BASE_NS)
  /** Array initializer of OSTIMER peripheral base addresses */
  #define OSTIMER_BASE_ADDRS                       { OSTIMER0_BASE }
  /** Array initializer of OSTIMER peripheral base pointers */
  #define OSTIMER_BASE_PTRS                        { OSTIMER0 }
  /** Array initializer of OSTIMER peripheral base addresses */
  #define OSTIMER_BASE_ADDRS_NS                    { OSTIMER0_BASE_NS }
  /** Array initializer of OSTIMER peripheral base pointers */
  #define OSTIMER_BASE_PTRS_NS                     { OSTIMER0_NS }
#else
  /** Peripheral OSTIMER0 base address */
  #define OSTIMER0_BASE                            (0x4002D000u)
  /** Peripheral OSTIMER0 base pointer */
  #define OSTIMER0                                 ((OSTIMER_Type *)OSTIMER0_BASE)
  /** Array initializer of OSTIMER peripheral base addresses */
  #define OSTIMER_BASE_ADDRS                       { OSTIMER0_BASE }
  /** Array initializer of OSTIMER peripheral base pointers */
  #define OSTIMER_BASE_PTRS                        { OSTIMER0 }
#endif
/** Interrupt vectors for the OSTIMER peripheral type */
#define OSTIMER_IRQS                             { OS_EVENT_IRQn }

/*!
 * @}
 */ /* end of group OSTIMER_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- PINT Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer
 * @{
 */

/** PINT - Register Layout Typedef */
typedef struct {
  __IO uint32_t ISEL;                              /**< Pin Interrupt Mode, offset: 0x0 */
  __IO uint32_t IENR;                              /**< Pin Interrupt Level or Rising Edge Interrupt Enable, offset: 0x4 */
  __O  uint32_t SIENR;                             /**< Pin Interrupt Level or Rising Edge Interrupt Set, offset: 0x8 */
  __IO uint32_t CIENR;                             /**< Pin Interrupt Level (Rising Edge Interrupt) Clear, offset: 0xC */
  __IO uint32_t IENF;                              /**< Pin Interrupt Active Level or Falling Edge Interrupt Enable, offset: 0x10 */
  __O  uint32_t SIENF;                             /**< Pin Interrupt Active Level or Falling Edge Interrupt Set, offset: 0x14 */
  __O  uint32_t CIENF;                             /**< Pin Interrupt Active Level or Falling Edge Interrupt Clear, offset: 0x18 */
  __IO uint32_t RISE;                              /**< Pin Interrupt Rising Edge, offset: 0x1C */
  __IO uint32_t FALL;                              /**< Pin Interrupt Falling Edge, offset: 0x20 */
  __IO uint32_t IST;                               /**< Pin Interrupt Status, offset: 0x24 */
  __IO uint32_t PMCTRL;                            /**< Pattern Match Interrupt Control, offset: 0x28 */
  __IO uint32_t PMSRC;                             /**< Pattern Match Interrupt Bit-Slice Source, offset: 0x2C */
  __IO uint32_t PMCFG;                             /**< Pattern Match Interrupt Bit Slice Configuration, offset: 0x30 */
} PINT_Type;

/* ----------------------------------------------------------------------------
   -- PINT Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup PINT_Register_Masks PINT Register Masks
 * @{
 */

/*! @name ISEL - Pin Interrupt Mode */
/*! @{ */

#define PINT_ISEL_PMODE_MASK                     (0xFFU)  /* Merged from fields with different position or width, of widths (2, 8), largest definition used */
#define PINT_ISEL_PMODE_SHIFT                    (0U)
/*! PMODE - Interrupt mode
 *  0b00..Edge-sensitive
 *  0b01..Level-sensitive
 */
#define PINT_ISEL_PMODE(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK)  /* Merged from fields with different position or width, of widths (2, 8), largest definition used */
/*! @} */

/*! @name IENR - Pin Interrupt Level or Rising Edge Interrupt Enable */
/*! @{ */

#define PINT_IENR_ENRL_MASK                      (0xFFU)  /* Merged from fields with different position or width, of widths (2, 8), largest definition used */
#define PINT_IENR_ENRL_SHIFT                     (0U)
/*! ENRL - Enable Interrupt
 *  0b00..Disable rising edge or level interrupt
 *  0b01..Enable rising edge or level interrupt
 */
#define PINT_IENR_ENRL(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK)  /* Merged from fields with different position or width, of widths (2, 8), largest definition used */
/*! @} */

/*! @name SIENR - Pin Interrupt Level or Rising Edge Interrupt Set */
/*! @{ */

#define PINT_SIENR_SETENRL_MASK                  (0xFFU)  /* Merged from fields with different position or width, of widths (2, 8), largest definition used */
#define PINT_SIENR_SETENRL_SHIFT                 (0U)
/*! SETENRL - Set bits in the IENR
 *  0b00..No operation
 *  0b01..Enable rising edge or level interrupt
 */
#define PINT_SIENR_SETENRL(x)                    (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK)  /* Merged from fields with different position or width, of widths (2, 8), largest definition used */
/*! @} */

/*! @name CIENR - Pin Interrupt Level (Rising Edge Interrupt) Clear */
/*! @{ */

#define PINT_CIENR_CENRL_MASK                    (0xFFU)  /* Merged from fields with different position or width, of widths (2, 8), largest definition used */
#define PINT_CIENR_CENRL_SHIFT                   (0U)
/*! CENRL - Clear bits in the IENR
 *  0b00..No operation
 *  0b01..Disable rising edge or level interrupt
 */
#define PINT_CIENR_CENRL(x)                      (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK)  /* Merged from fields with different position or width, of widths (2, 8), largest definition used */
/*! @} */

/*! @name IENF - Pin Interrupt Active Level or Falling Edge Interrupt Enable */
/*! @{ */

#define PINT_IENF_ENAF_MASK                      (0xFFU)  /* Merged from fields with different position or width, of widths (2, 8), largest definition used */
#define PINT_IENF_ENAF_SHIFT                     (0U)
/*! ENAF - Enable Interrupt
 *  0b00..Disable falling edge interrupt or set active interrupt level LOW
 *  0b01..Enable falling edge interrupt enabled or set active interrupt level HIGH
 */
#define PINT_IENF_ENAF(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK)  /* Merged from fields with different position or width, of widths (2, 8), largest definition used */
/*! @} */

/*! @name SIENF - Pin Interrupt Active Level or Falling Edge Interrupt Set */
/*! @{ */

#define PINT_SIENF_SETENAF_MASK                  (0xFFU)  /* Merged from fields with different position or width, of widths (2, 8), largest definition used */
#define PINT_SIENF_SETENAF_SHIFT                 (0U)
/*! SETENAF - Set bits in the IENF
 *  0b00..No operation
 *  0b01..Select HIGH-active interrupt or enable falling edge interrupt
 */
#define PINT_SIENF_SETENAF(x)                    (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK)  /* Merged from fields with different position or width, of widths (2, 8), largest definition used */
/*! @} */

/*! @name CIENF - Pin Interrupt Active Level or Falling Edge Interrupt Clear */
/*! @{ */

#define PINT_CIENF_CENAF_MASK                    (0xFFU)  /* Merged from fields with different position or width, of widths (2, 8), largest definition used */
#define PINT_CIENF_CENAF_SHIFT                   (0U)
/*! CENAF - Clear bits in the IENF
 *  0b00..No operation
 *  0b01..LOW-active interrupt selected or falling edge interrupt disabled
 */
#define PINT_CIENF_CENAF(x)                      (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK)  /* Merged from fields with different position or width, of widths (2, 8), largest definition used */
/*! @} */

/*! @name RISE - Pin Interrupt Rising Edge */
/*! @{ */

#define PINT_RISE_RDET_MASK                      (0xFFU)  /* Merged from fields with different position or width, of widths (2, 8), largest definition used */
#define PINT_RISE_RDET_SHIFT                     (0U)
/*! RDET - Rising edge detect
 *  0b00..Read 0- No rising edge has been detected on this pin since Reset or the last time a one was written to this bit, Write 0- no operation
 *  0b01..Read 1- a rising edge has been detected since Reset or the last time a one was written to this bit,
 *        Write 1- clear rising edge detection for this pin
 */
#define PINT_RISE_RDET(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK)  /* Merged from fields with different position or width, of widths (2, 8), largest definition used */
/*! @} */

/*! @name FALL - Pin Interrupt Falling Edge */
/*! @{ */

#define PINT_FALL_FDET_MASK                      (0xFFU)  /* Merged from fields with different position or width, of widths (2, 8), largest definition used */
#define PINT_FALL_FDET_SHIFT                     (0U)
/*! FDET - Falling edge detect
 *  0b00..Read 0- No falling edge has been detected on this pin since Reset or the last time a one was written to this bit, Write 0- no operation
 *  0b01..Read 1- a falling edge has been detected since Reset or the last time a one was written to this bit,
 *        Write 1- clear falling edge detection for this bit
 */
#define PINT_FALL_FDET(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK)  /* Merged from fields with different position or width, of widths (2, 8), largest definition used */
/*! @} */

/*! @name IST - Pin Interrupt Status */
/*! @{ */

#define PINT_IST_PSTAT_MASK                      (0xFFU)  /* Merged from fields with different position or width, of widths (2, 8), largest definition used */
#define PINT_IST_PSTAT_SHIFT                     (0U)
/*! PSTAT - Pin interrupt status
 *  0b00..Read 0- interrupt is not being requested for this pin, Write 0- no operation.
 *  0b01..Read 1- interrupt is being requested for this pin, Write 1 (edge-sensitive)- clear rising- and
 *        falling-edge detection for this pin, Write 1 (level-sensitive)- switch the active level for this pin (in the IENF
 *        register).
 */
#define PINT_IST_PSTAT(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK)  /* Merged from fields with different position or width, of widths (2, 8), largest definition used */
/*! @} */

/*! @name PMCTRL - Pattern Match Interrupt Control */
/*! @{ */

#define PINT_PMCTRL_SEL_PMATCH_MASK              (0x1U)
#define PINT_PMCTRL_SEL_PMATCH_SHIFT             (0U)
/*! SEL_PMATCH - Specifies whether the pin interrupts are controlled by the pin interrupt function or by the pattern match function.
 *  0b0..Pin interrupt- interrupts are driven in response to the standard pin interrupt function.
 *  0b1..Pattern match- interrupts are driven in response to pattern matches.
 */
#define PINT_PMCTRL_SEL_PMATCH(x)                (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK)

#define PINT_PMCTRL_ENA_RXEV_MASK                (0x2U)
#define PINT_PMCTRL_ENA_RXEV_SHIFT               (1U)
/*! ENA_RXEV - Enables the RXEV output to the CPU and/or to a GPIO output, when the specified boolean expression evaluates to true.
 *  0b0..Disabled- RXEV output to the CPU is disabled.
 *  0b1..Enabled- RXEV output to the CPU is enabled.
 */
#define PINT_PMCTRL_ENA_RXEV(x)                  (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK)

#define PINT_PMCTRL_PMAT_MASK                    (0xFF000000U)
#define PINT_PMCTRL_PMAT_SHIFT                   (24U)
/*! PMAT - Pattern Matches
 *  0b00000001..The corresponding product term is matched by the current state of the appropriate inputs.
 */
#define PINT_PMCTRL_PMAT(x)                      (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK)
/*! @} */

/*! @name PMSRC - Pattern Match Interrupt Bit-Slice Source */
/*! @{ */

#define PINT_PMSRC_SRC0_MASK                     (0x700U)
#define PINT_PMSRC_SRC0_SHIFT                    (8U)
/*! SRC0 - Selects the input source for bit slice 0
 *  0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n.
 *  0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n.
 *  0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n.
 *  0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n.
 *  0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n.
 *  0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n.
 *  0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n.
 *  0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n.
 */
#define PINT_PMSRC_SRC0(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK)

#define PINT_PMSRC_SRC1_MASK                     (0x3800U)
#define PINT_PMSRC_SRC1_SHIFT                    (11U)
/*! SRC1 - Selects the input source for bit slice 1
 *  0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n.
 *  0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n.
 *  0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n.
 *  0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n.
 *  0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n.
 *  0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n.
 *  0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n.
 *  0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n.
 */
#define PINT_PMSRC_SRC1(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK)

#define PINT_PMSRC_SRC2_MASK                     (0x1C000U)
#define PINT_PMSRC_SRC2_SHIFT                    (14U)
/*! SRC2 - Selects the input source for bit slice 2
 *  0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n.
 *  0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n.
 *  0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n.
 *  0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n.
 *  0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n.
 *  0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n.
 *  0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n.
 *  0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n.
 */
#define PINT_PMSRC_SRC2(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK)

#define PINT_PMSRC_SRC3_MASK                     (0xE0000U)
#define PINT_PMSRC_SRC3_SHIFT                    (17U)
/*! SRC3 - Selects the input source for bit slice 3
 *  0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n.
 *  0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n.
 *  0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n.
 *  0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n.
 *  0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n.
 *  0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n.
 *  0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n.
 *  0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n.
 */
#define PINT_PMSRC_SRC3(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK)

#define PINT_PMSRC_SRC4_MASK                     (0x700000U)
#define PINT_PMSRC_SRC4_SHIFT                    (20U)
/*! SRC4 - Selects the input source for bit slice 4
 *  0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n.
 *  0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n.
 *  0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n.
 *  0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n.
 *  0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n.
 *  0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n.
 *  0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n.
 *  0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n.
 */
#define PINT_PMSRC_SRC4(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK)

#define PINT_PMSRC_SRC5_MASK                     (0x3800000U)
#define PINT_PMSRC_SRC5_SHIFT                    (23U)
/*! SRC5 - Selects the input source for bit slice 5
 *  0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n.
 *  0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n.
 *  0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n.
 *  0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n.
 *  0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n.
 *  0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n.
 *  0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n.
 *  0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n.
 */
#define PINT_PMSRC_SRC5(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK)

#define PINT_PMSRC_SRC6_MASK                     (0x1C000000U)
#define PINT_PMSRC_SRC6_SHIFT                    (26U)
/*! SRC6 - Selects the input source for bit slice 6
 *  0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n.
 *  0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n.
 *  0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n.
 *  0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n.
 *  0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n.
 *  0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n.
 *  0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n.
 *  0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n.
 */
#define PINT_PMSRC_SRC6(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK)

#define PINT_PMSRC_SRC7_MASK                     (0xE0000000U)
#define PINT_PMSRC_SRC7_SHIFT                    (29U)
/*! SRC7 - Selects the input source for bit slice 7
 *  0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n.
 *  0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n.
 *  0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n.
 *  0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n.
 *  0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n.
 *  0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n.
 *  0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n.
 *  0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n.
 */
#define PINT_PMSRC_SRC7(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK)
/*! @} */

/*! @name PMCFG - Pattern Match Interrupt Bit Slice Configuration */
/*! @{ */

#define PINT_PMCFG_PROD_ENDPTS0_MASK             (0x1U)
#define PINT_PMCFG_PROD_ENDPTS0_SHIFT            (0U)
/*! PROD_ENDPTS0 - Determines whether slice 0 is an endpoint.
 *  0b0..No effect. Slice 0 is not an endpoint.
 *  0b1..Endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true.
 */
#define PINT_PMCFG_PROD_ENDPTS0(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK)

#define PINT_PMCFG_PROD_ENDPTS1_MASK             (0x2U)
#define PINT_PMCFG_PROD_ENDPTS1_SHIFT            (1U)
/*! PROD_ENDPTS1 - Determines whether slice 1 is an endpoint.
 *  0b0..No effect. Slice 1 is not an endpoint.
 *  0b1..Endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true.
 */
#define PINT_PMCFG_PROD_ENDPTS1(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK)

#define PINT_PMCFG_PROD_ENDPTS2_MASK             (0x4U)
#define PINT_PMCFG_PROD_ENDPTS2_SHIFT            (2U)
/*! PROD_ENDPTS2 - Determines whether slice 2 is an endpoint.
 *  0b0..No effect. Slice 2 is not an endpoint.
 *  0b1..Endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true.
 */
#define PINT_PMCFG_PROD_ENDPTS2(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK)

#define PINT_PMCFG_PROD_ENDPTS3_MASK             (0x8U)
#define PINT_PMCFG_PROD_ENDPTS3_SHIFT            (3U)
/*! PROD_ENDPTS3 - Determines whether slice 3 is an endpoint.
 *  0b0..No effect. Slice 3 is not an endpoint.
 *  0b1..Endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true.
 */
#define PINT_PMCFG_PROD_ENDPTS3(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK)

#define PINT_PMCFG_PROD_ENDPTS4_MASK             (0x10U)
#define PINT_PMCFG_PROD_ENDPTS4_SHIFT            (4U)
/*! PROD_ENDPTS4 - Determines whether slice 4 is an endpoint.
 *  0b0..No effect. Slice 4 is not an endpoint.
 *  0b1..Endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true.
 */
#define PINT_PMCFG_PROD_ENDPTS4(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK)

#define PINT_PMCFG_PROD_ENDPTS5_MASK             (0x20U)
#define PINT_PMCFG_PROD_ENDPTS5_SHIFT            (5U)
/*! PROD_ENDPTS5 - Determines whether slice 5 is an endpoint.
 *  0b0..No effect. Slice 5 is not an endpoint.
 *  0b1..Endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true.
 */
#define PINT_PMCFG_PROD_ENDPTS5(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK)

#define PINT_PMCFG_PROD_ENDPTS6_MASK             (0x40U)
#define PINT_PMCFG_PROD_ENDPTS6_SHIFT            (6U)
/*! PROD_ENDPTS6 - Determines whether slice 6 is an endpoint.
 *  0b0..No effect. Slice 6 is not an endpoint.
 *  0b1..Endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true.
 */
#define PINT_PMCFG_PROD_ENDPTS6(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK)

#define PINT_PMCFG_CFG0_MASK                     (0x700U)
#define PINT_PMCFG_CFG0_SHIFT                    (8U)
/*! CFG0 - Specifies the match contribution condition for bit slice 0.
 *  0b000..Constant HIGH
 *  0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
 *         time the edge detection for this bit slice was cleared. This match condition is only cleared when the
 *         PMCFG or the PMSRC registers are written to.
 *  0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
 *         time the edge detection for this bit slice was cleared. This match condition is only cleared when the
 *         PMCFG or the PMSRC registers are written to.
 *  0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
 *         has occurred since the last time the edge detection for this bit slice was cleared. This match condition
 *         is only cleared when the PMCFG or the PMSRC registers are written to.
 *  0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
 *  0b101..Low level. Match occurs when there is a low level on the specified input.
 *  0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
 *  0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge
 *         is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is
 *         cleared after 1 clock cycle.
 */
#define PINT_PMCFG_CFG0(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK)

#define PINT_PMCFG_CFG1_MASK                     (0x3800U)
#define PINT_PMCFG_CFG1_SHIFT                    (11U)
/*! CFG1 - Specifies the match contribution condition for bit slice 1.
 *  0b000..Constant HIGH
 *  0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
 *         time the edge detection for this bit slice was cleared. This match condition is only cleared when the
 *         PMCFG or the PMSRC registers are written to.
 *  0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
 *         time the edge detection for this bit slice was cleared. This match condition is only cleared when the
 *         PMCFG or the PMSRC registers are written to.
 *  0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
 *         has occurred since the last time the edge detection for this bit slice was cleared. This match condition
 *         is only cleared when the PMCFG or the PMSRC registers are written to.
 *  0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
 *  0b101..Low level. Match occurs when there is a low level on the specified input.
 *  0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
 *  0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge
 *         is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is
 *         cleared after 1 clock cycle.
 */
#define PINT_PMCFG_CFG1(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK)

#define PINT_PMCFG_CFG2_MASK                     (0x1C000U)
#define PINT_PMCFG_CFG2_SHIFT                    (14U)
/*! CFG2 - Specifies the match contribution condition for bit slice 2.
 *  0b000..Constant HIGH
 *  0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
 *         time the edge detection for this bit slice was cleared. This match condition is only cleared when the
 *         PMCFG or the PMSRC registers are written to.
 *  0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
 *         time the edge detection for this bit slice was cleared. This match condition is only cleared when the
 *         PMCFG or the PMSRC registers are written to.
 *  0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
 *         has occurred since the last time the edge detection for this bit slice was cleared. This match condition
 *         is only cleared when the PMCFG or the PMSRC registers are written to.
 *  0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
 *  0b101..Low level. Match occurs when there is a low level on the specified input.
 *  0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
 *  0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge
 *         is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is
 *         cleared after 1 clock cycle.
 */
#define PINT_PMCFG_CFG2(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK)

#define PINT_PMCFG_CFG3_MASK                     (0xE0000U)
#define PINT_PMCFG_CFG3_SHIFT                    (17U)
/*! CFG3 - Specifies the match contribution condition for bit slice 3.
 *  0b000..Constant HIGH
 *  0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
 *         time the edge detection for this bit slice was cleared. This match condition is only cleared when the
 *         PMCFG or the PMSRC registers are written to.
 *  0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
 *         time the edge detection for this bit slice was cleared. This match condition is only cleared when the
 *         PMCFG or the PMSRC registers are written to.
 *  0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
 *         has occurred since the last time the edge detection for this bit slice was cleared. This match condition
 *         is only cleared when the PMCFG or the PMSRC registers are written to.
 *  0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
 *  0b101..Low level. Match occurs when there is a low level on the specified input.
 *  0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
 *  0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge
 *         is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is
 *         cleared after 1 clock cycle.
 */
#define PINT_PMCFG_CFG3(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK)

#define PINT_PMCFG_CFG4_MASK                     (0x700000U)
#define PINT_PMCFG_CFG4_SHIFT                    (20U)
/*! CFG4 - Specifies the match contribution condition for bit slice 4.
 *  0b000..Constant HIGH
 *  0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
 *         time the edge detection for this bit slice was cleared. This match condition is only cleared when the
 *         PMCFG or the PMSRC registers are written to.
 *  0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
 *         time the edge detection for this bit slice was cleared. This match condition is only cleared when the
 *         PMCFG or the PMSRC registers are written to.
 *  0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
 *         has occurred since the last time the edge detection for this bit slice was cleared. This match condition
 *         is only cleared when the PMCFG or the PMSRC registers are written to.
 *  0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
 *  0b101..Low level. Match occurs when there is a low level on the specified input.
 *  0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
 *  0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge
 *         is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is
 *         cleared after 1 clock cycle.
 */
#define PINT_PMCFG_CFG4(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK)

#define PINT_PMCFG_CFG5_MASK                     (0x3800000U)
#define PINT_PMCFG_CFG5_SHIFT                    (23U)
/*! CFG5 - Specifies the match contribution condition for bit slice 5.
 *  0b000..Constant HIGH
 *  0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
 *         time the edge detection for this bit slice was cleared. This match condition is only cleared when the
 *         PMCFG or the PMSRC registers are written to.
 *  0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
 *         time the edge detection for this bit slice was cleared. This match condition is only cleared when the
 *         PMCFG or the PMSRC registers are written to.
 *  0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
 *         has occurred since the last time the edge detection for this bit slice was cleared. This match condition
 *         is only cleared when the PMCFG or the PMSRC registers are written to.
 *  0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
 *  0b101..Low level. Match occurs when there is a low level on the specified input.
 *  0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
 *  0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge
 *         is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is
 *         cleared after 1 clock cycle.
 */
#define PINT_PMCFG_CFG5(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK)

#define PINT_PMCFG_CFG6_MASK                     (0x1C000000U)
#define PINT_PMCFG_CFG6_SHIFT                    (26U)
/*! CFG6 - Specifies the match contribution condition for bit slice 6.
 *  0b000..Constant HIGH
 *  0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
 *         time the edge detection for this bit slice was cleared. This match condition is only cleared when the
 *         PMCFG or the PMSRC registers are written to.
 *  0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
 *         time the edge detection for this bit slice was cleared. This match condition is only cleared when the
 *         PMCFG or the PMSRC registers are written to.
 *  0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
 *         has occurred since the last time the edge detection for this bit slice was cleared. This match condition
 *         is only cleared when the PMCFG or the PMSRC registers are written to.
 *  0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
 *  0b101..Low level. Match occurs when there is a low level on the specified input.
 *  0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
 *  0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge
 *         is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is
 *         cleared after 1 clock cycle.
 */
#define PINT_PMCFG_CFG6(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK)

#define PINT_PMCFG_CFG7_MASK                     (0xE0000000U)
#define PINT_PMCFG_CFG7_SHIFT                    (29U)
/*! CFG7 - Specifies the match contribution condition for bit slice 7.
 *  0b000..Constant HIGH
 *  0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
 *         time the edge detection for this bit slice was cleared. This match condition is only cleared when the
 *         PMCFG or the PMSRC registers are written to.
 *  0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
 *         time the edge detection for this bit slice was cleared. This match condition is only cleared when the
 *         PMCFG or the PMSRC registers are written to.
 *  0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
 *         has occurred since the last time the edge detection for this bit slice was cleared. This match condition
 *         is only cleared when the PMCFG or the PMSRC registers are written to.
 *  0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
 *  0b101..Low level. Match occurs when there is a low level on the specified input.
 *  0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
 *  0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge
 *         is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is
 *         cleared after 1 clock cycle.
 */
#define PINT_PMCFG_CFG7(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group PINT_Register_Masks */


/* PINT - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral PINT base address */
  #define PINT_BASE                                (0x50004000u)
  /** Peripheral PINT base address */
  #define PINT_BASE_NS                             (0x40004000u)
  /** Peripheral PINT base pointer */
  #define PINT                                     ((PINT_Type *)PINT_BASE)
  /** Peripheral PINT base pointer */
  #define PINT_NS                                  ((PINT_Type *)PINT_BASE_NS)
  /** Peripheral SECPINT base address */
  #define SECPINT_BASE                             (0x50005000u)
  /** Peripheral SECPINT base address */
  #define SECPINT_BASE_NS                          (0x40005000u)
  /** Peripheral SECPINT base pointer */
  #define SECPINT                                  ((PINT_Type *)SECPINT_BASE)
  /** Peripheral SECPINT base pointer */
  #define SECPINT_NS                               ((PINT_Type *)SECPINT_BASE_NS)
  /** Array initializer of PINT peripheral base addresses */
  #define PINT_BASE_ADDRS                          { PINT_BASE, SECPINT_BASE }
  /** Array initializer of PINT peripheral base pointers */
  #define PINT_BASE_PTRS                           { PINT, SECPINT }
  /** Array initializer of PINT peripheral base addresses */
  #define PINT_BASE_ADDRS_NS                       { PINT_BASE_NS, SECPINT_BASE_NS }
  /** Array initializer of PINT peripheral base pointers */
  #define PINT_BASE_PTRS_NS                        { PINT_NS, SECPINT_NS }
#else
  /** Peripheral PINT base address */
  #define PINT_BASE                                (0x40004000u)
  /** Peripheral PINT base pointer */
  #define PINT                                     ((PINT_Type *)PINT_BASE)
  /** Peripheral SECPINT base address */
  #define SECPINT_BASE                             (0x40005000u)
  /** Peripheral SECPINT base pointer */
  #define SECPINT                                  ((PINT_Type *)SECPINT_BASE)
  /** Array initializer of PINT peripheral base addresses */
  #define PINT_BASE_ADDRS                          { PINT_BASE, SECPINT_BASE }
  /** Array initializer of PINT peripheral base pointers */
  #define PINT_BASE_PTRS                           { PINT, SECPINT }
#endif
/** Interrupt vectors for the PINT peripheral type */
#define PINT_IRQS                                { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn, PIN_INT4_IRQn, PIN_INT5_IRQn, PIN_INT6_IRQn, PIN_INT7_IRQn, SEC_GPIO_INT0_IRQ0_IRQn, SEC_GPIO_INT0_IRQ1_IRQn }

/*!
 * @}
 */ /* end of group PINT_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- PKC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup PKC_Peripheral_Access_Layer PKC Peripheral Access Layer
 * @{
 */

/** PKC - Register Layout Typedef */
typedef struct {
  __I  uint32_t PKC_STATUS;                        /**< Status register, offset: 0x0 */
  __IO uint32_t PKC_CTRL;                          /**< Control register, offset: 0x4 */
  __IO uint32_t PKC_CFG;                           /**< Configuration register, offset: 0x8 */
       uint8_t RESERVED_0[4];
  __IO uint32_t PKC_MODE1;                         /**< Mode register, parameter set 1, offset: 0x10 */
  __IO uint32_t PKC_XYPTR1;                        /**< X+Y pointer register, parameter set 1, offset: 0x14 */
  __IO uint32_t PKC_ZRPTR1;                        /**< Z+R pointer register, parameter set 1, offset: 0x18 */
  __IO uint32_t PKC_LEN1;                          /**< Length register, parameter set 1, offset: 0x1C */
  __IO uint32_t PKC_MODE2;                         /**< Mode register, parameter set 2, offset: 0x20 */
  __IO uint32_t PKC_XYPTR2;                        /**< X+Y pointer register, parameter set 2, offset: 0x24 */
  __IO uint32_t PKC_ZRPTR2;                        /**< Z+R pointer register, parameter set 2, offset: 0x28 */
  __IO uint32_t PKC_LEN2;                          /**< Length register, parameter set 2, offset: 0x2C */
       uint8_t RESERVED_1[16];
  __IO uint32_t PKC_UPTR;                          /**< Universal pointer FUP program, offset: 0x40 */
  __IO uint32_t PKC_UPTRT;                         /**< Universal pointer FUP table, offset: 0x44 */
  __IO uint32_t PKC_ULEN;                          /**< Universal pointer length, offset: 0x48 */
       uint8_t RESERVED_2[4];
  __IO uint32_t PKC_MCDATA;                        /**< MC pattern data interface, offset: 0x50 */
       uint8_t RESERVED_3[12];
  __I  uint32_t PKC_VERSION;                       /**< PKC version register, offset: 0x60 */
       uint8_t RESERVED_4[3916];
  __O  uint32_t PKC_SOFT_RST;                      /**< Software reset, offset: 0xFB0 */
       uint8_t RESERVED_5[12];
  __I  uint32_t PKC_ACCESS_ERR;                    /**< Access Error, offset: 0xFC0 */
  __O  uint32_t PKC_ACCESS_ERR_CLR;                /**< Clear Access Error, offset: 0xFC4 */
       uint8_t RESERVED_6[16];
  __O  uint32_t PKC_INT_CLR_ENABLE;                /**< Interrupt enable clear, offset: 0xFD8 */
  __O  uint32_t PKC_INT_SET_ENABLE;                /**< Interrupt enable set, offset: 0xFDC */
  __I  uint32_t PKC_INT_STATUS;                    /**< Interrupt status, offset: 0xFE0 */
  __I  uint32_t PKC_INT_ENABLE;                    /**< Interrupt enable, offset: 0xFE4 */
  __O  uint32_t PKC_INT_CLR_STATUS;                /**< Interrupt status clear, offset: 0xFE8 */
  __O  uint32_t PKC_INT_SET_STATUS;                /**< Interrupt status set, offset: 0xFEC */
       uint8_t RESERVED_7[12];
  __I  uint32_t PKC_MODULE_ID;                     /**< Module ID, offset: 0xFFC */
} PKC_Type;

/* ----------------------------------------------------------------------------
   -- PKC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup PKC_Register_Masks PKC Register Masks
 * @{
 */

/*! @name PKC_STATUS - Status register */
/*! @{ */

#define PKC_PKC_STATUS_activ_MASK                (0x1U)
#define PKC_PKC_STATUS_activ_SHIFT               (0U)
/*! activ - PKC active: ACTIV=1 signals that a calculation is in progress or about to start. At the
 *    end of a calculation ACTIV is automatically reset to logic 0 in case no further GO bit is set.
 *    If the next PKC operation has been started by setting a GO bit during a calculation, ACTIV
 *    remains high. ACTIV is always '1' in case PKC_STATUS.GOANY is set. ACTIV is always '0' in case
 *    PKC_CTRL_RESET is set.
 */
#define PKC_PKC_STATUS_activ(x)                  (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_activ_SHIFT)) & PKC_PKC_STATUS_activ_MASK)

#define PKC_PKC_STATUS_carry_MASK                (0x2U)
#define PKC_PKC_STATUS_carry_SHIFT               (1U)
/*! carry - Carry overflow flag: CARRY is set by the PKC at the end of a calculation in case
 */
#define PKC_PKC_STATUS_carry(x)                  (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_carry_SHIFT)) & PKC_PKC_STATUS_carry_MASK)

#define PKC_PKC_STATUS_zero_MASK                 (0x4U)
#define PKC_PKC_STATUS_zero_SHIFT                (2U)
/*! zero - Zero result flag: ZERO is set by the PKC at the end of a calculation in case the result
 *    of the calculation is equal zero. ZERO is updated for each PKC calculation mode, except for
 *    MUL1 (opcode 0x20) and MUL1_GF2 (opcode 0x24).
 */
#define PKC_PKC_STATUS_zero(x)                   (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_zero_SHIFT)) & PKC_PKC_STATUS_zero_MASK)

#define PKC_PKC_STATUS_goany_MASK                (0x8U)
#define PKC_PKC_STATUS_goany_SHIFT               (3U)
/*! goany - Combined GO status flag: GOANY is set in case either PKC_CTRL.GOD1, GOD2, GOM1, GOM2 or
 *    GOU is set. The 1-to-0 transition of GOANY indicates that a calculation has been started and
 *    that a new GO bit can be set. If GOANY is cleared also all PKC_STATUS.LOCKED bits are cleared
 *    to indicate that the parameter set can be updated. GOANY is always '0' in case PKC_CTRL.RESET
 *    is set.
 */
#define PKC_PKC_STATUS_goany(x)                  (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_goany_SHIFT)) & PKC_PKC_STATUS_goany_MASK)

#define PKC_PKC_STATUS_reserved4_MASK            (0x10U)
#define PKC_PKC_STATUS_reserved4_SHIFT           (4U)
/*! reserved4 - reserved
 */
#define PKC_PKC_STATUS_reserved4(x)              (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_reserved4_SHIFT)) & PKC_PKC_STATUS_reserved4_MASK)

#define PKC_PKC_STATUS_locked_MASK               (0x60U)
#define PKC_PKC_STATUS_locked_SHIFT              (5U)
/*! locked - Parameter set locked: Indicates if parameter set is locked due to a pending calculation start or can be overwritten.
 */
#define PKC_PKC_STATUS_locked(x)                 (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_locked_SHIFT)) & PKC_PKC_STATUS_locked_MASK)

#define PKC_PKC_STATUS_reserved31_MASK           (0xFFFFFF80U)
#define PKC_PKC_STATUS_reserved31_SHIFT          (7U)
/*! reserved31 - reserved
 */
#define PKC_PKC_STATUS_reserved31(x)             (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_reserved31_SHIFT)) & PKC_PKC_STATUS_reserved31_MASK)
/*! @} */

/*! @name PKC_CTRL - Control register */
/*! @{ */

#define PKC_PKC_CTRL_reset_MASK                  (0x1U)
#define PKC_PKC_CTRL_reset_SHIFT                 (0U)
/*! reset - PKC reset control bit: RESET=1 enforces the PKC's reset state during which a calculation
 *    cannot be started and by which any ongoing calculation process is stopped. RESET can be
 *    set/cleared by the CPU in order to switch between PKC reset and calculation enable. RESET=1 is the
 *    default state after a chip reset.
 */
#define PKC_PKC_CTRL_reset(x)                    (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_reset_SHIFT)) & PKC_PKC_CTRL_reset_MASK)

#define PKC_PKC_CTRL_stop_MASK                   (0x2U)
#define PKC_PKC_CTRL_stop_SHIFT                  (1U)
/*! stop - Freeze PKC calculation: STOP=1 freezes all PKC activity incl. RAM accesses and reduces
 *    the PKC power consumption to its minimum. The difference compared to the reset of the PKC is
 *    that a stopped calculation can be continued when STOP is released (reset to '0') again. The
 *    status flags are not affected by the STOP control bit.
 */
#define PKC_PKC_CTRL_stop(x)                     (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_stop_SHIFT)) & PKC_PKC_CTRL_stop_MASK)

#define PKC_PKC_CTRL_god1_MASK                   (0x4U)
#define PKC_PKC_CTRL_god1_SHIFT                  (2U)
/*! god1 - Control bit to start direct operation using parameter set 1: If GOD1 is set PKC will
 *    start a direct / layer0 operation using parameter set 1 (PKC_MODE1, PKC_XYPTR1, PKC_ZRPTR1,
 *    PKC_LEN1).
 */
#define PKC_PKC_CTRL_god1(x)                     (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_god1_SHIFT)) & PKC_PKC_CTRL_god1_MASK)

#define PKC_PKC_CTRL_god2_MASK                   (0x8U)
#define PKC_PKC_CTRL_god2_SHIFT                  (3U)
/*! god2 - Control bit to start direct operation using parameter set 2: If GOD2 is set PKC will
 *    start a direct / layer0 operation using parameter set 2 (PKC_MODE2, PKC_XYPTR2, PKC_ZRPTR2,
 *    PKC_LEN2).
 */
#define PKC_PKC_CTRL_god2(x)                     (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_god2_SHIFT)) & PKC_PKC_CTRL_god2_MASK)

#define PKC_PKC_CTRL_gom1_MASK                   (0x10U)
#define PKC_PKC_CTRL_gom1_SHIFT                  (4U)
/*! gom1 - Control bit to start MC pattern using parameter set 1: If GOM1 is set PKC will start a MC
 *    pattern / layer1 operation using parameter set 1 (PKC_MODE1, PKC_XYPTR1, PKC_ZRPTR1,
 *    PKC_LEN1).
 */
#define PKC_PKC_CTRL_gom1(x)                     (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_gom1_SHIFT)) & PKC_PKC_CTRL_gom1_MASK)

#define PKC_PKC_CTRL_gom2_MASK                   (0x20U)
#define PKC_PKC_CTRL_gom2_SHIFT                  (5U)
/*! gom2 - Control bit to start MC pattern using parameter set 2: If GOM2 is set PKC will start a MC
 *    pattern / layer1 operation using parameter set 2 (PKC_MODE2, PKC_XYPTR2, PKC_ZRPTR2,
 *    PKC_LEN2).
 */
#define PKC_PKC_CTRL_gom2(x)                     (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_gom2_SHIFT)) & PKC_PKC_CTRL_gom2_MASK)

#define PKC_PKC_CTRL_gou_MASK                    (0x40U)
#define PKC_PKC_CTRL_gou_SHIFT                   (6U)
/*! gou - Control bit to start pipe operation: If GOU is set PKC will start the pipe / layer2
 *    operation (parameter fetch & calculation) described in section 'PKC Universal Pointer Fetch
 *    Operation'.
 */
#define PKC_PKC_CTRL_gou(x)                      (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_gou_SHIFT)) & PKC_PKC_CTRL_gou_MASK)

#define PKC_PKC_CTRL_gf2conv_MASK                (0x80U)
#define PKC_PKC_CTRL_gf2conv_SHIFT               (7U)
/*! gf2conv - Convert to GF2 calculation modes: If GF2CONV is set operations are mapped to their GF(2) equivalent operation modes.
 */
#define PKC_PKC_CTRL_gf2conv(x)                  (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_gf2conv_SHIFT)) & PKC_PKC_CTRL_gf2conv_MASK)

#define PKC_PKC_CTRL_clrcache_MASK               (0x100U)
#define PKC_PKC_CTRL_clrcache_SHIFT              (8U)
/*! clrcache - Clear universal pointer cache: Invalidates the cache such that all previously fetched
 *    parameters are withdrawn and have to be fetched again via DMA accesses.
 */
#define PKC_PKC_CTRL_clrcache(x)                 (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_clrcache_SHIFT)) & PKC_PKC_CTRL_clrcache_MASK)

#define PKC_PKC_CTRL_cache_en_MASK               (0x200U)
#define PKC_PKC_CTRL_cache_en_SHIFT              (9U)
/*! cache_en - Enable universal pointer cache: If CACHE_EN=1 the cache for the universal pointer
 *    parameters is enabled. In case a parameter value is found in the cache (from a previous fetch) no
 *    DMA access is triggered. As such the amount of DMA accesses for the parameter fetch vary
 *    between 0 and 4. To further optimize the cache utilization not used parameters, e.g. XPTR for a
 *    plain addition (opcode 0x0A), could be defined equal to a used one (e.g. equal YPTR or RPTR) or
 *    a previously fetched parameter.
 */
#define PKC_PKC_CTRL_cache_en(x)                 (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_cache_en_SHIFT)) & PKC_PKC_CTRL_cache_en_MASK)

#define PKC_PKC_CTRL_redmul_MASK                 (0xC00U)
#define PKC_PKC_CTRL_redmul_SHIFT                (10U)
/*! redmul - Reduced multiplier mode: REDMUL defines the operand width processed by the PKC coprocessor.
 *  0b00..full size mode, 3 least significant bits of pointer and length are ignored, minimum supported length 0x0008
 *  0b01..RFU Error Generated if selected
 *  0b10..64-bit mode, 3 least significant bits of pointer and length are ignored, minimum supported length 0x0008
 *  0b11..RFU Error Generated if selected
 */
#define PKC_PKC_CTRL_redmul(x)                   (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_redmul_SHIFT)) & PKC_PKC_CTRL_redmul_MASK)

#define PKC_PKC_CTRL_reserved31_MASK             (0xFFFFF000U)
#define PKC_PKC_CTRL_reserved31_SHIFT            (12U)
/*! reserved31 - reserved
 */
#define PKC_PKC_CTRL_reserved31(x)               (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_reserved31_SHIFT)) & PKC_PKC_CTRL_reserved31_MASK)
/*! @} */

/*! @name PKC_CFG - Configuration register */
/*! @{ */

#define PKC_PKC_CFG_idleop_MASK                  (0x1U)
#define PKC_PKC_CFG_idleop_SHIFT                 (0U)
/*! idleop - Idle operation feature not available in this version (flag is don't care).
 */
#define PKC_PKC_CFG_idleop(x)                    (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_idleop_SHIFT)) & PKC_PKC_CFG_idleop_MASK)

#define PKC_PKC_CFG_rfu1_MASK                    (0x2U)
#define PKC_PKC_CFG_rfu1_SHIFT                   (1U)
/*! rfu1 - RFU
 */
#define PKC_PKC_CFG_rfu1(x)                      (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_rfu1_SHIFT)) & PKC_PKC_CFG_rfu1_MASK)

#define PKC_PKC_CFG_rfu2_MASK                    (0x4U)
#define PKC_PKC_CFG_rfu2_SHIFT                   (2U)
/*! rfu2 - RFU
 */
#define PKC_PKC_CFG_rfu2(x)                      (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_rfu2_SHIFT)) & PKC_PKC_CFG_rfu2_MASK)

#define PKC_PKC_CFG_clkrnd_MASK                  (0x8U)
#define PKC_PKC_CFG_clkrnd_SHIFT                 (3U)
/*! clkrnd - Clock randomization feature not available in this version (flag is don't care).
 */
#define PKC_PKC_CFG_clkrnd(x)                    (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_clkrnd_SHIFT)) & PKC_PKC_CFG_clkrnd_MASK)

#define PKC_PKC_CFG_redmulnoise_MASK             (0x10U)
#define PKC_PKC_CFG_redmulnoise_SHIFT            (4U)
/*! redmulnoise - Noise in reduced multiplier mode feature not available in this version (flag is don't care).
 */
#define PKC_PKC_CFG_redmulnoise(x)               (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_redmulnoise_SHIFT)) & PKC_PKC_CFG_redmulnoise_MASK)

#define PKC_PKC_CFG_rnddly_MASK                  (0xE0U)
#define PKC_PKC_CFG_rnddly_SHIFT                 (5U)
/*! rnddly - Random delay feature not available in this version (flag is don't care).
 */
#define PKC_PKC_CFG_rnddly(x)                    (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_rnddly_SHIFT)) & PKC_PKC_CFG_rnddly_MASK)

#define PKC_PKC_CFG_sbxnoise_MASK                (0x100U)
#define PKC_PKC_CFG_sbxnoise_SHIFT               (8U)
/*! sbxnoise - Noise feature not available in this version (flag is don't care).
 */
#define PKC_PKC_CFG_sbxnoise(x)                  (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_sbxnoise_SHIFT)) & PKC_PKC_CFG_sbxnoise_MASK)

#define PKC_PKC_CFG_alpnoise_MASK                (0x200U)
#define PKC_PKC_CFG_alpnoise_SHIFT               (9U)
/*! alpnoise - Noise feature not available in this version (flag is don't care).
 */
#define PKC_PKC_CFG_alpnoise(x)                  (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_alpnoise_SHIFT)) & PKC_PKC_CFG_alpnoise_MASK)

#define PKC_PKC_CFG_fmulnoise_MASK               (0x400U)
#define PKC_PKC_CFG_fmulnoise_SHIFT              (10U)
/*! fmulnoise - Noise feature not available in this version (flag is don't care).
 */
#define PKC_PKC_CFG_fmulnoise(x)                 (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_fmulnoise_SHIFT)) & PKC_PKC_CFG_fmulnoise_MASK)

#define PKC_PKC_CFG_reserved31_MASK              (0xFFFFF800U)
#define PKC_PKC_CFG_reserved31_SHIFT             (11U)
/*! reserved31 - reserved
 */
#define PKC_PKC_CFG_reserved31(x)                (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_reserved31_SHIFT)) & PKC_PKC_CFG_reserved31_MASK)
/*! @} */

/*! @name PKC_MODE1 - Mode register, parameter set 1 */
/*! @{ */

#define PKC_PKC_MODE1_mode_MASK                  (0xFFU)
#define PKC_PKC_MODE1_mode_SHIFT                 (0U)
/*! mode - Calculation Mode / MC Start address:
 */
#define PKC_PKC_MODE1_mode(x)                    (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODE1_mode_SHIFT)) & PKC_PKC_MODE1_mode_MASK)

#define PKC_PKC_MODE1_reserved31_MASK            (0xFFFFFF00U)
#define PKC_PKC_MODE1_reserved31_SHIFT           (8U)
/*! reserved31 - reserved
 */
#define PKC_PKC_MODE1_reserved31(x)              (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODE1_reserved31_SHIFT)) & PKC_PKC_MODE1_reserved31_MASK)
/*! @} */

/*! @name PKC_XYPTR1 - X+Y pointer register, parameter set 1 */
/*! @{ */

#define PKC_PKC_XYPTR1_xptr_MASK                 (0xFFFFU)
#define PKC_PKC_XYPTR1_xptr_SHIFT                (0U)
/*! xptr - Start address of X operand in PKCRAM with byte granularity: Least significant bits are
 *    ignored depending on PKC_CTRL.REDMUL setting. Most significant bits are ignored depending on
 *    available PKCRAM size.
 */
#define PKC_PKC_XYPTR1_xptr(x)                   (((uint32_t)(((uint32_t)(x)) << PKC_PKC_XYPTR1_xptr_SHIFT)) & PKC_PKC_XYPTR1_xptr_MASK)

#define PKC_PKC_XYPTR1_yptr_MASK                 (0xFFFF0000U)
#define PKC_PKC_XYPTR1_yptr_SHIFT                (16U)
/*! yptr - Start address of Y operand in PKCRAM with byte granularity: Least significant bits are
 *    ignored depending on PKC_CTRL.REDMUL setting. Most significant bits are ignored depending on
 *    available PKCRAM size.
 */
#define PKC_PKC_XYPTR1_yptr(x)                   (((uint32_t)(((uint32_t)(x)) << PKC_PKC_XYPTR1_yptr_SHIFT)) & PKC_PKC_XYPTR1_yptr_MASK)
/*! @} */

/*! @name PKC_ZRPTR1 - Z+R pointer register, parameter set 1 */
/*! @{ */

#define PKC_PKC_ZRPTR1_zptr_MASK                 (0xFFFFU)
#define PKC_PKC_ZRPTR1_zptr_SHIFT                (0U)
/*! zptr - Start address of Z operand in PKCRAM with byte granularity or constant for calculation modes using CONST:
 */
#define PKC_PKC_ZRPTR1_zptr(x)                   (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR1_zptr_SHIFT)) & PKC_PKC_ZRPTR1_zptr_MASK)

#define PKC_PKC_ZRPTR1_rptr_MASK                 (0xFFFF0000U)
#define PKC_PKC_ZRPTR1_rptr_SHIFT                (16U)
/*! rptr - Start address of R result in PKCRAM with byte granularity: Least significant bits are
 *    ignored depending on PKC_CTRL.REDMUL setting. Most significant bits are ignored depending on
 *    available PKCRAM size.
 */
#define PKC_PKC_ZRPTR1_rptr(x)                   (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR1_rptr_SHIFT)) & PKC_PKC_ZRPTR1_rptr_MASK)
/*! @} */

/*! @name PKC_LEN1 - Length register, parameter set 1 */
/*! @{ */

#define PKC_PKC_LEN1_len_MASK                    (0xFFFFU)
#define PKC_PKC_LEN1_len_SHIFT                   (0U)
/*! len - Operand length: LEN defines the length of the operands and the result in bytes. The length
 *    of Y, Z and R depend furthermore on the selected calculation mode.
 */
#define PKC_PKC_LEN1_len(x)                      (((uint32_t)(((uint32_t)(x)) << PKC_PKC_LEN1_len_SHIFT)) & PKC_PKC_LEN1_len_MASK)

#define PKC_PKC_LEN1_mclen_MASK                  (0xFFFF0000U)
#define PKC_PKC_LEN1_mclen_SHIFT                 (16U)
/*! mclen - Loop counter for microcode pattern: MCLEN defines the length of the loop counter that
 *    can be used in layer1 calculation mode, e.g. in MC opcode DecrTBNZ. For the hardcoded MC
 *    patterns Modular Multiplication (MC start address 0x00), Plain Multiplication (0x13), Plain
 *    Multiplication with Addition (0x1D) and Modular Reduction (0x33) MCLEN defines the length of the X
 *    operand in bytes.
 */
#define PKC_PKC_LEN1_mclen(x)                    (((uint32_t)(((uint32_t)(x)) << PKC_PKC_LEN1_mclen_SHIFT)) & PKC_PKC_LEN1_mclen_MASK)
/*! @} */

/*! @name PKC_MODE2 - Mode register, parameter set 2 */
/*! @{ */

#define PKC_PKC_MODE2_mode_MASK                  (0xFFU)
#define PKC_PKC_MODE2_mode_SHIFT                 (0U)
/*! mode - Calculation Mode / MC Start address:
 */
#define PKC_PKC_MODE2_mode(x)                    (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODE2_mode_SHIFT)) & PKC_PKC_MODE2_mode_MASK)

#define PKC_PKC_MODE2_reserved31_MASK            (0xFFFFFF00U)
#define PKC_PKC_MODE2_reserved31_SHIFT           (8U)
/*! reserved31 - reserved
 */
#define PKC_PKC_MODE2_reserved31(x)              (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODE2_reserved31_SHIFT)) & PKC_PKC_MODE2_reserved31_MASK)
/*! @} */

/*! @name PKC_XYPTR2 - X+Y pointer register, parameter set 2 */
/*! @{ */

#define PKC_PKC_XYPTR2_xptr_MASK                 (0xFFFFU)
#define PKC_PKC_XYPTR2_xptr_SHIFT                (0U)
/*! xptr - Start address of X operand in PKCRAM with byte granularity: Least significant bits are
 *    ignored depending on PKC_CTRL.REDMUL setting. Most significant bits are ignored depending on
 *    available PKCRAM size.
 */
#define PKC_PKC_XYPTR2_xptr(x)                   (((uint32_t)(((uint32_t)(x)) << PKC_PKC_XYPTR2_xptr_SHIFT)) & PKC_PKC_XYPTR2_xptr_MASK)

#define PKC_PKC_XYPTR2_yptr_MASK                 (0xFFFF0000U)
#define PKC_PKC_XYPTR2_yptr_SHIFT                (16U)
/*! yptr - Start address of Y operand in PKCRAM with byte granularity: Least significant bits are
 *    ignored depending on PKC_CTRL.REDMUL setting. Most significant bits are ignored depending on
 *    available PKCRAM size.
 */
#define PKC_PKC_XYPTR2_yptr(x)                   (((uint32_t)(((uint32_t)(x)) << PKC_PKC_XYPTR2_yptr_SHIFT)) & PKC_PKC_XYPTR2_yptr_MASK)
/*! @} */

/*! @name PKC_ZRPTR2 - Z+R pointer register, parameter set 2 */
/*! @{ */

#define PKC_PKC_ZRPTR2_zptr_MASK                 (0xFFFFU)
#define PKC_PKC_ZRPTR2_zptr_SHIFT                (0U)
/*! zptr - Start address of Z operand in PKCRAM with byte granularity or constant for calculation modes using CONST:
 */
#define PKC_PKC_ZRPTR2_zptr(x)                   (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR2_zptr_SHIFT)) & PKC_PKC_ZRPTR2_zptr_MASK)

#define PKC_PKC_ZRPTR2_rptr_MASK                 (0xFFFF0000U)
#define PKC_PKC_ZRPTR2_rptr_SHIFT                (16U)
/*! rptr - Start address of R result in PKCRAM with byte granularity: Least significant bits are
 *    ignored depending on PKC_CTRL.REDMUL setting. Most significant bits are ignored depending on
 *    available PKCRAM size.
 */
#define PKC_PKC_ZRPTR2_rptr(x)                   (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR2_rptr_SHIFT)) & PKC_PKC_ZRPTR2_rptr_MASK)
/*! @} */

/*! @name PKC_LEN2 - Length register, parameter set 2 */
/*! @{ */

#define PKC_PKC_LEN2_len_MASK                    (0xFFFFU)
#define PKC_PKC_LEN2_len_SHIFT                   (0U)
/*! len - Operand length: LEN defines the length of the operands and the result in bytes. The length
 *    of Y, Z and R depend furthermore on the selected calculation mode.
 */
#define PKC_PKC_LEN2_len(x)                      (((uint32_t)(((uint32_t)(x)) << PKC_PKC_LEN2_len_SHIFT)) & PKC_PKC_LEN2_len_MASK)

#define PKC_PKC_LEN2_mclen_MASK                  (0xFFFF0000U)
#define PKC_PKC_LEN2_mclen_SHIFT                 (16U)
/*! mclen - Loop counter for microcode pattern: MCLEN defines the length of the loop counter that
 *    can be used in layer1 calculation mode, e.g. in MC opcode DecrTBNZ. For the hardcoded MC
 *    patterns Modular Multiplication (MC start address 0x00)
 */
#define PKC_PKC_LEN2_mclen(x)                    (((uint32_t)(((uint32_t)(x)) << PKC_PKC_LEN2_mclen_SHIFT)) & PKC_PKC_LEN2_mclen_MASK)
/*! @} */

/*! @name PKC_UPTR - Universal pointer FUP program */
/*! @{ */

#define PKC_PKC_UPTR_ptr_MASK                    (0xFFFFFFFFU)
#define PKC_PKC_UPTR_ptr_SHIFT                   (0U)
/*! ptr - Pointer to start address of PKC FUP program: PKC_UPTR needs to be defined before starting
 *    a universal pointer PKC calculation (layer2) via PKC_CTRL.GOU. The pointer address needs to be
 *    valid and the memory space the pointer addresses needs to be enabled for PKC access by the
 *    system. Otherwise a security alarm is triggered (PKC_ACCESS_ERR.AHB is set).
 */
#define PKC_PKC_UPTR_ptr(x)                      (((uint32_t)(((uint32_t)(x)) << PKC_PKC_UPTR_ptr_SHIFT)) & PKC_PKC_UPTR_ptr_MASK)
/*! @} */

/*! @name PKC_UPTRT - Universal pointer FUP table */
/*! @{ */

#define PKC_PKC_UPTRT_ptr_MASK                   (0xFFFFFFFFU)
#define PKC_PKC_UPTRT_ptr_SHIFT                  (0U)
/*! ptr - Pointer to start address of PKC FUP table: PKC_UPTRT needs to be defined before starting a
 *    universal pointer PKC calculation (layer2) via PKC_CTRL.GOU. The pointer address needs to be
 *    valid and the memory space the pointer addresses needs to be enabled for PKC access by the
 *    system. Otherwise a security alarm is triggered (PKC_ACCESS_ERR.AHB is set).
 */
#define PKC_PKC_UPTRT_ptr(x)                     (((uint32_t)(((uint32_t)(x)) << PKC_PKC_UPTRT_ptr_SHIFT)) & PKC_PKC_UPTRT_ptr_MASK)
/*! @} */

/*! @name PKC_ULEN - Universal pointer length */
/*! @{ */

#define PKC_PKC_ULEN_len_MASK                    (0xFFU)
#define PKC_PKC_ULEN_len_SHIFT                   (0U)
/*! len - Length of universal pointer calculation: PKC_ULEN defines how many FUP program entries
 *    shall be processed for one layer2 calculation started via PKC_CTRL.GOU. The FUP program entries
 *    include layer0 calculations, layer1 calculations and CRC entries for FUP program integrity
 *    protection.
 */
#define PKC_PKC_ULEN_len(x)                      (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ULEN_len_SHIFT)) & PKC_PKC_ULEN_len_MASK)

#define PKC_PKC_ULEN_reserved31_MASK             (0xFFFFFF00U)
#define PKC_PKC_ULEN_reserved31_SHIFT            (8U)
/*! reserved31 - reserved
 */
#define PKC_PKC_ULEN_reserved31(x)               (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ULEN_reserved31_SHIFT)) & PKC_PKC_ULEN_reserved31_MASK)
/*! @} */

/*! @name PKC_MCDATA - MC pattern data interface */
/*! @{ */

#define PKC_PKC_MCDATA_mcdata_MASK               (0xFFFFFFFFU)
#define PKC_PKC_MCDATA_mcdata_SHIFT              (0U)
/*! mcdata - Microcode read/write data: This IP version does not support flexible MC patterns (only
 *    hard coded ones). Any read or write access to PKC_MCDATA triggers a security alarm
 *    (PKC_ACCESS_ERR.CTRL is set).
 */
#define PKC_PKC_MCDATA_mcdata(x)                 (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MCDATA_mcdata_SHIFT)) & PKC_PKC_MCDATA_mcdata_MASK)
/*! @} */

/*! @name PKC_VERSION - PKC version register */
/*! @{ */

#define PKC_PKC_VERSION_mulsize_MASK             (0x3U)
#define PKC_PKC_VERSION_mulsize_SHIFT            (0U)
/*! mulsize - native multiplier size and operand granularity
 *  0b01..32-bit multiplier
 *  0b10..64-bit multiplier
 *  0b11..128-bit multiplier
 */
#define PKC_PKC_VERSION_mulsize(x)               (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_mulsize_SHIFT)) & PKC_PKC_VERSION_mulsize_MASK)

#define PKC_PKC_VERSION_mcavail_MASK             (0x4U)
#define PKC_PKC_VERSION_mcavail_SHIFT            (2U)
/*! mcavail - MC feature (layer1 calculation) is available
 */
#define PKC_PKC_VERSION_mcavail(x)               (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_mcavail_SHIFT)) & PKC_PKC_VERSION_mcavail_MASK)

#define PKC_PKC_VERSION_upavail_MASK             (0x8U)
#define PKC_PKC_VERSION_upavail_SHIFT            (3U)
/*! upavail - UP feature (layer2 calculation) is available
 */
#define PKC_PKC_VERSION_upavail(x)               (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_upavail_SHIFT)) & PKC_PKC_VERSION_upavail_MASK)

#define PKC_PKC_VERSION_upcacheavail_MASK        (0x10U)
#define PKC_PKC_VERSION_upcacheavail_SHIFT       (4U)
/*! upcacheavail - UP cache is available
 */
#define PKC_PKC_VERSION_upcacheavail(x)          (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_upcacheavail_SHIFT)) & PKC_PKC_VERSION_upcacheavail_MASK)

#define PKC_PKC_VERSION_gf2avail_MASK            (0x20U)
#define PKC_PKC_VERSION_gf2avail_SHIFT           (5U)
/*! gf2avail - GF2 calculation modes are available
 */
#define PKC_PKC_VERSION_gf2avail(x)              (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_gf2avail_SHIFT)) & PKC_PKC_VERSION_gf2avail_MASK)

#define PKC_PKC_VERSION_paramnum_MASK            (0xC0U)
#define PKC_PKC_VERSION_paramnum_SHIFT           (6U)
/*! paramnum - Number of parameter sets for real calculation
 */
#define PKC_PKC_VERSION_paramnum(x)              (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_paramnum_SHIFT)) & PKC_PKC_VERSION_paramnum_MASK)

#define PKC_PKC_VERSION_sbx0avail_MASK           (0x100U)
#define PKC_PKC_VERSION_sbx0avail_SHIFT          (8U)
/*! sbx0avail - SBX0 operation is available
 */
#define PKC_PKC_VERSION_sbx0avail(x)             (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_sbx0avail_SHIFT)) & PKC_PKC_VERSION_sbx0avail_MASK)

#define PKC_PKC_VERSION_sbx1avail_MASK           (0x200U)
#define PKC_PKC_VERSION_sbx1avail_SHIFT          (9U)
/*! sbx1avail - SBX1 operation is available
 */
#define PKC_PKC_VERSION_sbx1avail(x)             (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_sbx1avail_SHIFT)) & PKC_PKC_VERSION_sbx1avail_MASK)

#define PKC_PKC_VERSION_sbx2avail_MASK           (0x400U)
#define PKC_PKC_VERSION_sbx2avail_SHIFT          (10U)
/*! sbx2avail - SBX2 operation is available
 */
#define PKC_PKC_VERSION_sbx2avail(x)             (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_sbx2avail_SHIFT)) & PKC_PKC_VERSION_sbx2avail_MASK)

#define PKC_PKC_VERSION_sbx3avail_MASK           (0x800U)
#define PKC_PKC_VERSION_sbx3avail_SHIFT          (11U)
/*! sbx3avail - SBX3 operation is available
 */
#define PKC_PKC_VERSION_sbx3avail(x)             (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_sbx3avail_SHIFT)) & PKC_PKC_VERSION_sbx3avail_MASK)

#define PKC_PKC_VERSION_mcreconf_size_MASK       (0xFF000U)
#define PKC_PKC_VERSION_mcreconf_size_SHIFT      (12U)
/*! mcreconf_size - Size of reconfigurable MC table in bytes
 */
#define PKC_PKC_VERSION_mcreconf_size(x)         (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_mcreconf_size_SHIFT)) & PKC_PKC_VERSION_mcreconf_size_MASK)

#define PKC_PKC_VERSION_reserved31_MASK          (0xFFF00000U)
#define PKC_PKC_VERSION_reserved31_SHIFT         (20U)
/*! reserved31 - reserved
 */
#define PKC_PKC_VERSION_reserved31(x)            (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_reserved31_SHIFT)) & PKC_PKC_VERSION_reserved31_MASK)
/*! @} */

/*! @name PKC_SOFT_RST - Software reset */
/*! @{ */

#define PKC_PKC_SOFT_RST_soft_rst_MASK           (0x1U)
#define PKC_PKC_SOFT_RST_soft_rst_SHIFT          (0U)
/*! soft_rst - Write 1 to reset module (0 has no effect). All running and pending PKC calculation
 *    are stopped. All PKC SFRs are reset except PKC_ACCESS_ERR.
 */
#define PKC_PKC_SOFT_RST_soft_rst(x)             (((uint32_t)(((uint32_t)(x)) << PKC_PKC_SOFT_RST_soft_rst_SHIFT)) & PKC_PKC_SOFT_RST_soft_rst_MASK)

#define PKC_PKC_SOFT_RST_reserved31_MASK         (0xFFFFFFFEU)
#define PKC_PKC_SOFT_RST_reserved31_SHIFT        (1U)
/*! reserved31 - reserved
 */
#define PKC_PKC_SOFT_RST_reserved31(x)           (((uint32_t)(((uint32_t)(x)) << PKC_PKC_SOFT_RST_reserved31_SHIFT)) & PKC_PKC_SOFT_RST_reserved31_MASK)
/*! @} */

/*! @name PKC_ACCESS_ERR - Access Error */
/*! @{ */

#define PKC_PKC_ACCESS_ERR_apb_notav_MASK        (0x1U)
#define PKC_PKC_ACCESS_ERR_apb_notav_SHIFT       (0U)
/*! apb_notav - APB Error: address not available
 */
#define PKC_PKC_ACCESS_ERR_apb_notav(x)          (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_apb_notav_SHIFT)) & PKC_PKC_ACCESS_ERR_apb_notav_MASK)

#define PKC_PKC_ACCESS_ERR_apb_wrgmd_MASK        (0x2U)
#define PKC_PKC_ACCESS_ERR_apb_wrgmd_SHIFT       (1U)
/*! apb_wrgmd - APB Error: Wrong access mode
 */
#define PKC_PKC_ACCESS_ERR_apb_wrgmd(x)          (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_apb_wrgmd_SHIFT)) & PKC_PKC_ACCESS_ERR_apb_wrgmd_MASK)

#define PKC_PKC_ACCESS_ERR_reserved3_MASK        (0xCU)
#define PKC_PKC_ACCESS_ERR_reserved3_SHIFT       (2U)
/*! reserved3 - reserved for future erors on APB I/F
 */
#define PKC_PKC_ACCESS_ERR_reserved3(x)          (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_reserved3_SHIFT)) & PKC_PKC_ACCESS_ERR_reserved3_MASK)

#define PKC_PKC_ACCESS_ERR_apb_master_MASK       (0xF0U)
#define PKC_PKC_ACCESS_ERR_apb_master_SHIFT      (4U)
/*! apb_master - APB Master that triggered first APB error (APB_WRGMD or APB_NOTAV)
 */
#define PKC_PKC_ACCESS_ERR_apb_master(x)         (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_apb_master_SHIFT)) & PKC_PKC_ACCESS_ERR_apb_master_MASK)

#define PKC_PKC_ACCESS_ERR_reserved9_MASK        (0x300U)
#define PKC_PKC_ACCESS_ERR_reserved9_SHIFT       (8U)
/*! reserved9 - reserved for future erors on AHB I/F Layer2 Only
 */
#define PKC_PKC_ACCESS_ERR_reserved9(x)          (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_reserved9_SHIFT)) & PKC_PKC_ACCESS_ERR_reserved9_MASK)

#define PKC_PKC_ACCESS_ERR_ahb_MASK              (0x400U)
#define PKC_PKC_ACCESS_ERR_ahb_SHIFT             (10U)
/*! ahb - AHB Error: invalid AHB access Layer2 Only
 */
#define PKC_PKC_ACCESS_ERR_ahb(x)                (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_ahb_SHIFT)) & PKC_PKC_ACCESS_ERR_ahb_MASK)

#define PKC_PKC_ACCESS_ERR_reserved15_MASK       (0xF800U)
#define PKC_PKC_ACCESS_ERR_reserved15_SHIFT      (11U)
/*! reserved15 - reserved for future erors on AHB I/F Layer2 Only
 */
#define PKC_PKC_ACCESS_ERR_reserved15(x)         (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_reserved15_SHIFT)) & PKC_PKC_ACCESS_ERR_reserved15_MASK)

#define PKC_PKC_ACCESS_ERR_pkcc_MASK             (0x10000U)
#define PKC_PKC_ACCESS_ERR_pkcc_SHIFT            (16U)
/*! pkcc - Error in PKC coprocessor kernel
 */
#define PKC_PKC_ACCESS_ERR_pkcc(x)               (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_pkcc_SHIFT)) & PKC_PKC_ACCESS_ERR_pkcc_MASK)

#define PKC_PKC_ACCESS_ERR_fdet_MASK             (0x20000U)
#define PKC_PKC_ACCESS_ERR_fdet_SHIFT            (17U)
/*! fdet - Error due to error detection circuitry
 */
#define PKC_PKC_ACCESS_ERR_fdet(x)               (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_fdet_SHIFT)) & PKC_PKC_ACCESS_ERR_fdet_MASK)

#define PKC_PKC_ACCESS_ERR_ctrl_MASK             (0x40000U)
#define PKC_PKC_ACCESS_ERR_ctrl_SHIFT            (18U)
/*! ctrl - Error in PKC software control
 */
#define PKC_PKC_ACCESS_ERR_ctrl(x)               (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_ctrl_SHIFT)) & PKC_PKC_ACCESS_ERR_ctrl_MASK)

#define PKC_PKC_ACCESS_ERR_ucrc_MASK             (0x80000U)
#define PKC_PKC_ACCESS_ERR_ucrc_SHIFT            (19U)
/*! ucrc - Error in layer2 CRC check
 */
#define PKC_PKC_ACCESS_ERR_ucrc(x)               (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_ucrc_SHIFT)) & PKC_PKC_ACCESS_ERR_ucrc_MASK)

#define PKC_PKC_ACCESS_ERR_reserved20_MASK       (0x100000U)
#define PKC_PKC_ACCESS_ERR_reserved20_SHIFT      (20U)
/*! reserved20 - reserved
 */
#define PKC_PKC_ACCESS_ERR_reserved20(x)         (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_reserved20_SHIFT)) & PKC_PKC_ACCESS_ERR_reserved20_MASK)

#define PKC_PKC_ACCESS_ERR_reserved31_MASK       (0xFFE00000U)
#define PKC_PKC_ACCESS_ERR_reserved31_SHIFT      (21U)
/*! reserved31 - reserved for more block errors
 */
#define PKC_PKC_ACCESS_ERR_reserved31(x)         (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_reserved31_SHIFT)) & PKC_PKC_ACCESS_ERR_reserved31_MASK)
/*! @} */

/*! @name PKC_ACCESS_ERR_CLR - Clear Access Error */
/*! @{ */

#define PKC_PKC_ACCESS_ERR_CLR_err_clr_MASK      (0x1U)
#define PKC_PKC_ACCESS_ERR_CLR_err_clr_SHIFT     (0U)
/*! err_clr - Write 1 to reset PKC_ACCESS_ERR SFR.
 */
#define PKC_PKC_ACCESS_ERR_CLR_err_clr(x)        (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_CLR_err_clr_SHIFT)) & PKC_PKC_ACCESS_ERR_CLR_err_clr_MASK)

#define PKC_PKC_ACCESS_ERR_CLR_reserved31_MASK   (0xFFFFFFFEU)
#define PKC_PKC_ACCESS_ERR_CLR_reserved31_SHIFT  (1U)
/*! reserved31 - reserved
 */
#define PKC_PKC_ACCESS_ERR_CLR_reserved31(x)     (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_CLR_reserved31_SHIFT)) & PKC_PKC_ACCESS_ERR_CLR_reserved31_MASK)
/*! @} */

/*! @name PKC_INT_CLR_ENABLE - Interrupt enable clear */
/*! @{ */

#define PKC_PKC_INT_CLR_ENABLE_en_pdone_MASK     (0x1U)
#define PKC_PKC_INT_CLR_ENABLE_en_pdone_SHIFT    (0U)
/*! en_pdone - Write to clear PDONE interrupt enable flag (PKC_INT_ENABLE.EN_PDONE=0).
 */
#define PKC_PKC_INT_CLR_ENABLE_en_pdone(x)       (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_CLR_ENABLE_en_pdone_SHIFT)) & PKC_PKC_INT_CLR_ENABLE_en_pdone_MASK)

#define PKC_PKC_INT_CLR_ENABLE_reserved1_MASK    (0x2U)
#define PKC_PKC_INT_CLR_ENABLE_reserved1_SHIFT   (1U)
/*! reserved1 - reserved
 */
#define PKC_PKC_INT_CLR_ENABLE_reserved1(x)      (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_CLR_ENABLE_reserved1_SHIFT)) & PKC_PKC_INT_CLR_ENABLE_reserved1_MASK)

#define PKC_PKC_INT_CLR_ENABLE_reserved31_MASK   (0xFFFFFFFCU)
#define PKC_PKC_INT_CLR_ENABLE_reserved31_SHIFT  (2U)
/*! reserved31 - reserved
 */
#define PKC_PKC_INT_CLR_ENABLE_reserved31(x)     (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_CLR_ENABLE_reserved31_SHIFT)) & PKC_PKC_INT_CLR_ENABLE_reserved31_MASK)
/*! @} */

/*! @name PKC_INT_SET_ENABLE - Interrupt enable set */
/*! @{ */

#define PKC_PKC_INT_SET_ENABLE_en_pdone_MASK     (0x1U)
#define PKC_PKC_INT_SET_ENABLE_en_pdone_SHIFT    (0U)
/*! en_pdone - Write to set PDONE interrupt enable flag (PKC_INT_ENABLE.EN_PDONE=1).
 */
#define PKC_PKC_INT_SET_ENABLE_en_pdone(x)       (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_SET_ENABLE_en_pdone_SHIFT)) & PKC_PKC_INT_SET_ENABLE_en_pdone_MASK)

#define PKC_PKC_INT_SET_ENABLE_reserved1_MASK    (0x2U)
#define PKC_PKC_INT_SET_ENABLE_reserved1_SHIFT   (1U)
/*! reserved1 - reserved
 */
#define PKC_PKC_INT_SET_ENABLE_reserved1(x)      (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_SET_ENABLE_reserved1_SHIFT)) & PKC_PKC_INT_SET_ENABLE_reserved1_MASK)

#define PKC_PKC_INT_SET_ENABLE_reserved31_MASK   (0xFFFFFFFCU)
#define PKC_PKC_INT_SET_ENABLE_reserved31_SHIFT  (2U)
/*! reserved31 - reserved
 */
#define PKC_PKC_INT_SET_ENABLE_reserved31(x)     (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_SET_ENABLE_reserved31_SHIFT)) & PKC_PKC_INT_SET_ENABLE_reserved31_MASK)
/*! @} */

/*! @name PKC_INT_STATUS - Interrupt status */
/*! @{ */

#define PKC_PKC_INT_STATUS_int_pdone_MASK        (0x1U)
#define PKC_PKC_INT_STATUS_int_pdone_SHIFT       (0U)
/*! int_pdone - End-of-computation status flag: INT_PDONE is set after EACH single PKC layer0 or
 *    layer1 calculation. In case of a universal pointer calculation (layer2) INT_PDONE is set at the
 *    end of the pipe calculation when PKC_ULEN has been decremented to zero and the final PKC
 *    calculation has completed.
 */
#define PKC_PKC_INT_STATUS_int_pdone(x)          (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_STATUS_int_pdone_SHIFT)) & PKC_PKC_INT_STATUS_int_pdone_MASK)

#define PKC_PKC_INT_STATUS_reserved1_MASK        (0x2U)
#define PKC_PKC_INT_STATUS_reserved1_SHIFT       (1U)
/*! reserved1 - reserved
 */
#define PKC_PKC_INT_STATUS_reserved1(x)          (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_STATUS_reserved1_SHIFT)) & PKC_PKC_INT_STATUS_reserved1_MASK)

#define PKC_PKC_INT_STATUS_reserved31_MASK       (0xFFFFFFFCU)
#define PKC_PKC_INT_STATUS_reserved31_SHIFT      (2U)
/*! reserved31 - reserved
 */
#define PKC_PKC_INT_STATUS_reserved31(x)         (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_STATUS_reserved31_SHIFT)) & PKC_PKC_INT_STATUS_reserved31_MASK)
/*! @} */

/*! @name PKC_INT_ENABLE - Interrupt enable */
/*! @{ */

#define PKC_PKC_INT_ENABLE_en_pdone_MASK         (0x1U)
#define PKC_PKC_INT_ENABLE_en_pdone_SHIFT        (0U)
/*! en_pdone - PDONE interrupt enable flag: If EN_PDONE=1 an interrupt is triggered every time
 *    PKC_INT_STATUS.INT_PDONE is set. Otherwise the interrupt generation is suppressed.
 */
#define PKC_PKC_INT_ENABLE_en_pdone(x)           (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_ENABLE_en_pdone_SHIFT)) & PKC_PKC_INT_ENABLE_en_pdone_MASK)

#define PKC_PKC_INT_ENABLE_reserved1_MASK        (0x2U)
#define PKC_PKC_INT_ENABLE_reserved1_SHIFT       (1U)
/*! reserved1 - reserved
 */
#define PKC_PKC_INT_ENABLE_reserved1(x)          (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_ENABLE_reserved1_SHIFT)) & PKC_PKC_INT_ENABLE_reserved1_MASK)

#define PKC_PKC_INT_ENABLE_reserved31_MASK       (0xFFFFFFFCU)
#define PKC_PKC_INT_ENABLE_reserved31_SHIFT      (2U)
/*! reserved31 - reserved
 */
#define PKC_PKC_INT_ENABLE_reserved31(x)         (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_ENABLE_reserved31_SHIFT)) & PKC_PKC_INT_ENABLE_reserved31_MASK)
/*! @} */

/*! @name PKC_INT_CLR_STATUS - Interrupt status clear */
/*! @{ */

#define PKC_PKC_INT_CLR_STATUS_int_pdone_MASK    (0x1U)
#define PKC_PKC_INT_CLR_STATUS_int_pdone_SHIFT   (0U)
/*! int_pdone - Write to clear End-of-computation status flag (PKC_INT_STATUS.INT_PDONE=0).
 */
#define PKC_PKC_INT_CLR_STATUS_int_pdone(x)      (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_CLR_STATUS_int_pdone_SHIFT)) & PKC_PKC_INT_CLR_STATUS_int_pdone_MASK)

#define PKC_PKC_INT_CLR_STATUS_reserved1_MASK    (0x2U)
#define PKC_PKC_INT_CLR_STATUS_reserved1_SHIFT   (1U)
/*! reserved1 - reserved
 */
#define PKC_PKC_INT_CLR_STATUS_reserved1(x)      (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_CLR_STATUS_reserved1_SHIFT)) & PKC_PKC_INT_CLR_STATUS_reserved1_MASK)

#define PKC_PKC_INT_CLR_STATUS_reserved31_MASK   (0xFFFFFFFCU)
#define PKC_PKC_INT_CLR_STATUS_reserved31_SHIFT  (2U)
/*! reserved31 - reserved
 */
#define PKC_PKC_INT_CLR_STATUS_reserved31(x)     (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_CLR_STATUS_reserved31_SHIFT)) & PKC_PKC_INT_CLR_STATUS_reserved31_MASK)
/*! @} */

/*! @name PKC_INT_SET_STATUS - Interrupt status set */
/*! @{ */

#define PKC_PKC_INT_SET_STATUS_int_pdone_MASK    (0x1U)
#define PKC_PKC_INT_SET_STATUS_int_pdone_SHIFT   (0U)
/*! int_pdone - Write to set End-of-computation status flag (PKC_INT_STATUS.INT_PDONE=1) to trigger
 *    a PKC interrupt via software, e.g. for debug purposes.
 */
#define PKC_PKC_INT_SET_STATUS_int_pdone(x)      (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_SET_STATUS_int_pdone_SHIFT)) & PKC_PKC_INT_SET_STATUS_int_pdone_MASK)

#define PKC_PKC_INT_SET_STATUS_reserved1_MASK    (0x2U)
#define PKC_PKC_INT_SET_STATUS_reserved1_SHIFT   (1U)
/*! reserved1 - reserved
 */
#define PKC_PKC_INT_SET_STATUS_reserved1(x)      (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_SET_STATUS_reserved1_SHIFT)) & PKC_PKC_INT_SET_STATUS_reserved1_MASK)

#define PKC_PKC_INT_SET_STATUS_reserved31_MASK   (0xFFFFFFFCU)
#define PKC_PKC_INT_SET_STATUS_reserved31_SHIFT  (2U)
/*! reserved31 - reserved
 */
#define PKC_PKC_INT_SET_STATUS_reserved31(x)     (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_SET_STATUS_reserved31_SHIFT)) & PKC_PKC_INT_SET_STATUS_reserved31_MASK)
/*! @} */

/*! @name PKC_MODULE_ID - Module ID */
/*! @{ */

#define PKC_PKC_MODULE_ID_size_MASK              (0xFFU)
#define PKC_PKC_MODULE_ID_size_SHIFT             (0U)
/*! size - Address space of the IP
 */
#define PKC_PKC_MODULE_ID_size(x)                (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODULE_ID_size_SHIFT)) & PKC_PKC_MODULE_ID_size_MASK)

#define PKC_PKC_MODULE_ID_minor_rev_MASK         (0xF00U)
#define PKC_PKC_MODULE_ID_minor_rev_SHIFT        (8U)
/*! minor_rev - Minor revision
 */
#define PKC_PKC_MODULE_ID_minor_rev(x)           (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODULE_ID_minor_rev_SHIFT)) & PKC_PKC_MODULE_ID_minor_rev_MASK)

#define PKC_PKC_MODULE_ID_major_rev_MASK         (0xF000U)
#define PKC_PKC_MODULE_ID_major_rev_SHIFT        (12U)
/*! major_rev - Major revision
 */
#define PKC_PKC_MODULE_ID_major_rev(x)           (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODULE_ID_major_rev_SHIFT)) & PKC_PKC_MODULE_ID_major_rev_MASK)

#define PKC_PKC_MODULE_ID_id_MASK                (0xFFFF0000U)
#define PKC_PKC_MODULE_ID_id_SHIFT               (16U)
/*! id - Module ID
 */
#define PKC_PKC_MODULE_ID_id(x)                  (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODULE_ID_id_SHIFT)) & PKC_PKC_MODULE_ID_id_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group PKC_Register_Masks */


/* PKC - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral PKC base address */
  #define PKC_BASE                                 (0x5002F000u)
  /** Peripheral PKC base address */
  #define PKC_BASE_NS                              (0x4002F000u)
  /** Peripheral PKC base pointer */
  #define PKC                                      ((PKC_Type *)PKC_BASE)
  /** Peripheral PKC base pointer */
  #define PKC_NS                                   ((PKC_Type *)PKC_BASE_NS)
  /** Array initializer of PKC peripheral base addresses */
  #define PKC_BASE_ADDRS                           { PKC_BASE }
  /** Array initializer of PKC peripheral base pointers */
  #define PKC_BASE_PTRS                            { PKC }
  /** Array initializer of PKC peripheral base addresses */
  #define PKC_BASE_ADDRS_NS                        { PKC_BASE_NS }
  /** Array initializer of PKC peripheral base pointers */
  #define PKC_BASE_PTRS_NS                         { PKC_NS }
#else
  /** Peripheral PKC base address */
  #define PKC_BASE                                 (0x4002F000u)
  /** Peripheral PKC base pointer */
  #define PKC                                      ((PKC_Type *)PKC_BASE)
  /** Array initializer of PKC peripheral base addresses */
  #define PKC_BASE_ADDRS                           { PKC_BASE }
  /** Array initializer of PKC peripheral base pointers */
  #define PKC_BASE_PTRS                            { PKC }
#endif

/*!
 * @}
 */ /* end of group PKC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- PMC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
 * @{
 */

/** PMC - Register Layout Typedef */
typedef struct {
  __IO uint32_t CTRL;                              /**< Power Management Control [Reset by: PoR, Pin Reset, Software Reset and BoDs reset], offset: 0x0 */
  __I  uint32_t STATUS;                            /**< Power Management Controller FSM (Finite State Machines) status, offset: 0x4 */
  __IO uint32_t RESETCTRL;                         /**< Reset Control, offset: 0x8 */
  __IO uint32_t RESETCAUSE;                        /**< Reset Cause, offset: 0xC */
  __IO uint32_t DCDC0;                             /**< DCDC (first) control, offset: 0x10 */
  __IO uint32_t DCDC1;                             /**< DCDC (second) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x14 */
       uint8_t RESERVED_0[4];
  __IO uint32_t LDOPMU;                            /**< Power Management Unit (PMU) and Always-On domains LDO control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x1C */
  __IO uint32_t LDOMEM;                            /**< Memories LDO control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x20 */
  __IO uint32_t LDOCORE0;                          /**< LDO CORE (first) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x24 */
  __IO uint32_t LDOFLASHNV;                        /**< Flash High Voltage LDO control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x28 */
  __IO uint32_t LDOEFUSEPROG;                      /**< eFUSE (One Time Programmable Memory) Programming LDO control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x2C */
  __IO uint32_t BODVDDMAIN;                        /**< VDDMAIN Brown Out Dectector control, offset: 0x30 */
       uint8_t RESERVED_1[4];
  __IO uint32_t BODCORE;                           /**< Digital Core logic Brown Out Dectector control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x38 */
       uint8_t RESERVED_2[4];
  __IO uint32_t REFFASTWKUP;                       /**< Analog References fast wake-up Control register [Reset by: PoR], offset: 0x40 */
       uint8_t RESERVED_3[8];
  __IO uint32_t XTAL32K;                           /**< 32 KHz Crystal oscillator (XTAL) control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x4C */
  __IO uint32_t COMP;                              /**< Analog Comparator control, offset: 0x50 */
       uint8_t RESERVED_4[12];
  __O  uint32_t CMD;                               /**< DCDC and LDOCORE power state (enable/disable) control., offset: 0x60 */
  __IO uint32_t WAKEUPIOCTRL;                      /**< Deep Power Down wake-up source [Reset by: PoR, Pin Reset, Software Reset], offset: 0x64 */
  __IO uint32_t WAKEIOCAUSE;                       /**< Wake-up I/O source, offset: 0x68 */
  __IO uint32_t LIFECYCLESTATE;                    /**< Life Cycle State as configured in the OTP, offset: 0x6C */
  __I  uint32_t STATUSPWR;                         /**< Power status from various analog modules (DCDC, LDO, etc), offset: 0x70 */
  __IO uint32_t STATUSCLK;                         /**< Clock status, offset: 0x74 */
       uint8_t RESERVED_5[8];
  __IO uint32_t AOREG0;                            /**< Always-on 0, offset: 0x80 */
  __IO uint32_t AOREG1;                            /**< Always-on 1, offset: 0x84 */
       uint8_t RESERVED_6[8];
  __IO uint32_t MISCCTRL;                          /**< Miscellaneous Control Register for PMU [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x90 */
       uint8_t RESERVED_7[4];
  __IO uint32_t RTCOSC32K;                         /**< 32 KHz clocks source control, offset: 0x98 */
  __IO uint32_t OSEVENTTIMER;                      /**< OS Event Timer control, offset: 0x9C */
  __IO uint32_t PDSLEEPCFG1;                       /**< Controls the power to various modules during Low Power modes - DEEP-SLEEP, POWER-DOWN and DEEP-POWER-DOWN [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset], offset: 0xA0 */
  __IO uint32_t TIMEOUTEVENTS;                     /**< Record time-out errors that might occur at different stages during IC power up, offset: 0xA4 */
       uint8_t RESERVED_8[8];
  __IO uint32_t PDSLEEPCFG0;                       /**< Controls the power to various modules during Low Power modes - DEEP-SLEEP, POWER-DOWN and DEEP-POWER-DOWN [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset], offset: 0xB0 */
  __IO uint32_t SRAMRETCTRL;                       /**< Controls all SRAM instances power down modes during Low Power modes [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset], offset: 0xB4 */
  __IO uint32_t PDRUNCFG0;                         /**< Power configuration 0, offset: 0xB8 */
  __IO uint32_t PDRUNCFG1;                         /**< Power configuration 1, offset: 0xBC */
  __O  uint32_t PDRUNCFGSET0;                      /**< Power configuration set 0, offset: 0xC0 */
  __O  uint32_t PDRUNCFGSET1;                      /**< Power configuration set 1, offset: 0xC4 */
  __O  uint32_t PDRUNCFGCLR0;                      /**< Power configuration clear 0, offset: 0xC8 */
  __O  uint32_t PDRUNCFGCLR1;                      /**< Power configuration clear 1, offset: 0xCC */
       uint8_t RESERVED_9[4];
  __IO uint32_t SRAMCTRL;                          /**< All SRAMs common control signals [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset], offset: 0xD4 */
  __IO uint32_t SRAMCTRL0;                         /**< RAM_X0, and RAM_00 to RAM_30 power modes controls [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] When [LS, LSDEL, DSB, DSBDEL] is: 0011 : Normal Mode 1111 : Light sleep mode 0100 : Deep-sleep mode 1100 : Shut down Mode, offset: 0xD8 */
  __IO uint32_t SRAMCTRL1;                         /**< RAM_40 to RAM_43 power modes controls [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] When [LS, LSDEL, DSB, DSBDEL] is: 0011 : Normal Mode 1111 : Light sleep mode 0100 : Deep-sleep mode 1100 : Shut down Mode, offset: 0xDC */
} PMC_Type;

/* ----------------------------------------------------------------------------
   -- PMC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup PMC_Register_Masks PMC Register Masks
 * @{
 */

/*! @name CTRL - Power Management Control [Reset by: PoR, Pin Reset, Software Reset and BoDs reset] */
/*! @{ */

#define PMC_CTRL_LPMODE_MASK                     (0x3U)
#define PMC_CTRL_LPMODE_SHIFT                    (0U)
/*! LPMODE - Power Mode Control.
 *  0b00..ACTIVE power mode.
 *  0b01..DEEP-SLEEP low power mode.
 *  0b10..POWER-DOWN low power mode.
 *  0b11..DEEP-POWER-DOWN low power mode.
 */
#define PMC_CTRL_LPMODE(x)                       (((uint32_t)(((uint32_t)(x)) << PMC_CTRL_LPMODE_SHIFT)) & PMC_CTRL_LPMODE_MASK)

#define PMC_CTRL_SELCLOCK_MASK                   (0x4U)
#define PMC_CTRL_SELCLOCK_SHIFT                  (2U)
/*! SELCLOCK - Select the Power Management Controller (PMC) functional clock :
 *  0b0..1 MHz Free Running Oscillator.
 *  0b1..12 MHz Free Running Oscillator.
 */
#define PMC_CTRL_SELCLOCK(x)                     (((uint32_t)(((uint32_t)(x)) << PMC_CTRL_SELCLOCK_SHIFT)) & PMC_CTRL_SELCLOCK_MASK)

#define PMC_CTRL_SELMEMSUPPLY_MASK               (0x8U)
#define PMC_CTRL_SELMEMSUPPLY_SHIFT              (3U)
/*! SELMEMSUPPLY - Select Memories supply source in DEEP-SLEEP low power mode: Note: in POWER-DOWN
 *    and DEEP-POWER-DOWN, memories are always supplied by LDO_MEM.
 *  0b0..Memories are supplied by LDO_MEM in 'DEEP-SLEEP' low power mode.
 *  0b1..Memories are supplied by DCDC/LDO_CORE in 'DEEP-SLEEP' low power mode.
 */
#define PMC_CTRL_SELMEMSUPPLY(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_CTRL_SELMEMSUPPLY_SHIFT)) & PMC_CTRL_SELMEMSUPPLY_MASK)

#define PMC_CTRL_SELCORESUPPLYWK_MASK            (0x10U)
#define PMC_CTRL_SELCORESUPPLYWK_SHIFT           (4U)
/*! SELCORESUPPLYWK - Select Core Logic supply source when waking up from DEEP-SLEEP and POWER-DOWN low power modes :
 *  0b0..Core Logic is supplied by DCDC Converter.
 *  0b1..Core Logic is supplied by LDO CORE (configured in High Power mode).
 */
#define PMC_CTRL_SELCORESUPPLYWK(x)              (((uint32_t)(((uint32_t)(x)) << PMC_CTRL_SELCORESUPPLYWK_SHIFT)) & PMC_CTRL_SELCORESUPPLYWK_MASK)

#define PMC_CTRL_DEEPSLEEPCORESUPPLY_MASK        (0x60U)
#define PMC_CTRL_DEEPSLEEPCORESUPPLY_SHIFT       (5U)
/*! DEEPSLEEPCORESUPPLY - Select Core Logic supply source during DEEP-SLEEP low power mode :
 *  0b00..LDO CORE in Low Power Mode.
 *  0b01..LDO CORE in High Power Mode.
 *  0b10..DCDC Converter.
 */
#define PMC_CTRL_DEEPSLEEPCORESUPPLY(x)          (((uint32_t)(((uint32_t)(x)) << PMC_CTRL_DEEPSLEEPCORESUPPLY_SHIFT)) & PMC_CTRL_DEEPSLEEPCORESUPPLY_MASK)
/*! @} */

/*! @name STATUS - Power Management Controller FSM (Finite State Machines) status */
/*! @{ */

#define PMC_STATUS_BOOTMODE_MASK                 (0xC0000U)
#define PMC_STATUS_BOOTMODE_SHIFT                (18U)
/*! BOOTMODE - Latest IC Boot cause:.
 *  0b00..Latest IC boot was a Full power cycle boot sequence (PoR, Pin Reset, Brown Out Detectors Reset, Software Reset).
 *  0b01..Latest IC boot was from DEEP-SLEEP low power mode.
 *  0b10..Latest IC boot was from POWER-DOWN low power mode.
 *  0b11..Latest IC boot was from DEEP-POWER-DOWN low power mode.
 */
#define PMC_STATUS_BOOTMODE(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_STATUS_BOOTMODE_SHIFT)) & PMC_STATUS_BOOTMODE_MASK)

#define PMC_STATUS_FSMDCDCENABLE_MASK            (0x100000U)
#define PMC_STATUS_FSMDCDCENABLE_SHIFT           (20U)
/*! FSMDCDCENABLE - Indicates the power status of the DCDC (enabled or disabled) as driven by the Hardware Finite State Machines (FSM).
 *  0b0..DCDC is currently disabled by the Hardware Finite State Machine (FSM).
 *  0b1..DCDC is currently enabled by the Hardware Finite State Machine (FSM).
 */
#define PMC_STATUS_FSMDCDCENABLE(x)              (((uint32_t)(((uint32_t)(x)) << PMC_STATUS_FSMDCDCENABLE_SHIFT)) & PMC_STATUS_FSMDCDCENABLE_MASK)

#define PMC_STATUS_FSMLDOCOREHPENABLE_MASK       (0x200000U)
#define PMC_STATUS_FSMLDOCOREHPENABLE_SHIFT      (21U)
/*! FSMLDOCOREHPENABLE - Indicates the power status of the LDO CORE High Power Mode (enabled or
 *    disabled) as driven by the Hardware Finite State Machines (FSM).
 *  0b0..LDO CORE High Power Mode is currently disabled by the Hardware Finite State Machine (FSM).
 *  0b1..LDO CORE High Power Mode is currently enabled by the Hardware Finite State Machine (FSM).
 */
#define PMC_STATUS_FSMLDOCOREHPENABLE(x)         (((uint32_t)(((uint32_t)(x)) << PMC_STATUS_FSMLDOCOREHPENABLE_SHIFT)) & PMC_STATUS_FSMLDOCOREHPENABLE_MASK)

#define PMC_STATUS_FSMLDOCORELPENABLE_MASK       (0x400000U)
#define PMC_STATUS_FSMLDOCORELPENABLE_SHIFT      (22U)
/*! FSMLDOCORELPENABLE - Indicates the power status of the LDO CORE Low Power Mode (enabled or
 *    disabled) as driven by the Hardware Finite State Machines (FSM).
 *  0b0..LDO CORE Low Power Mode is currently disabled by the Hardware Finite State Machine (FSM).
 *  0b1..LDO CORE Low Power Mode is currently enabled by the Hardware Finite State Machine (FSM).
 */
#define PMC_STATUS_FSMLDOCORELPENABLE(x)         (((uint32_t)(((uint32_t)(x)) << PMC_STATUS_FSMLDOCORELPENABLE_SHIFT)) & PMC_STATUS_FSMLDOCORELPENABLE_MASK)

#define PMC_STATUS_FSMLDOCOREEXPTMRENABLE_MASK   (0x800000U)
#define PMC_STATUS_FSMLDOCOREEXPTMRENABLE_SHIFT  (23U)
/*! FSMLDOCOREEXPTMRENABLE - Indicates the status of the LDO CORE Exponential Timer (enabled or
 *    disabled) as driven by the Hardware Finite State Machines (FSM).
 */
#define PMC_STATUS_FSMLDOCOREEXPTMRENABLE(x)     (((uint32_t)(((uint32_t)(x)) << PMC_STATUS_FSMLDOCOREEXPTMRENABLE_SHIFT)) & PMC_STATUS_FSMLDOCOREEXPTMRENABLE_MASK)
/*! @} */

/*! @name RESETCTRL - Reset Control */
/*! @{ */

#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK  (0x1U)
#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE_SHIFT (0U)
/*! DPDWAKEUPRESETENABLE - Wake-up from DEEP-POWER-DOWN reset event (either from wake up I/O or RTC or OS Event Timer).
 *  0b0..Reset event from DEEP-POWER-DOWN mode is disabled.
 *  0b1..Reset event from DEEP-POWER-DOWN mode is enabled.
 */
#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE(x)    (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_DPDWAKEUPRESETENABLE_SHIFT)) & PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK)

#define PMC_RESETCTRL_SWRRESETENABLE_MASK        (0x8U)
#define PMC_RESETCTRL_SWRRESETENABLE_SHIFT       (3U)
/*! SWRRESETENABLE - Software reset enable.
 *  0b0..Software reset is disabled.
 *  0b1..Software reset is enabled.
 */
#define PMC_RESETCTRL_SWRRESETENABLE(x)          (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_SWRRESETENABLE_SHIFT)) & PMC_RESETCTRL_SWRRESETENABLE_MASK)

#define PMC_RESETCTRL_BODVDDMAINRESETENA_SECURE_MASK (0x30U)
#define PMC_RESETCTRL_BODVDDMAINRESETENA_SECURE_SHIFT (4U)
/*! BODVDDMAINRESETENA_SECURE - BOD_VDDMAIN reset enabled.
 *  0b10..BOD_VDDMAIN reset is disabled.
 *  0b01..And any other value than b10: BOD_VDDMAIN reset is enabled.
 */
#define PMC_RESETCTRL_BODVDDMAINRESETENA_SECURE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODVDDMAINRESETENA_SECURE_SHIFT)) & PMC_RESETCTRL_BODVDDMAINRESETENA_SECURE_MASK)

#define PMC_RESETCTRL_BODCORERESETENA_SECURE_MASK (0xC0U)
#define PMC_RESETCTRL_BODCORERESETENA_SECURE_SHIFT (6U)
/*! BODCORERESETENA_SECURE - BOD_CORE reset enabled.
 *  0b10..BODCORE reset is disabled.
 *  0b01..And any other value than b10: BOD_CORE reset is enabled.
 */
#define PMC_RESETCTRL_BODCORERESETENA_SECURE(x)  (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODCORERESETENA_SECURE_SHIFT)) & PMC_RESETCTRL_BODCORERESETENA_SECURE_MASK)

#define PMC_RESETCTRL_BODVDDMAINRESETENA_SECURE_DP_MASK (0x30000000U)
#define PMC_RESETCTRL_BODVDDMAINRESETENA_SECURE_DP_SHIFT (28U)
/*! BODVDDMAINRESETENA_SECURE_DP - BOD_VDDMAIN reset enabled.
 *  0b10..BOD_VDDMAIN reset is disabled.
 *  0b01..And any other value than b10: BOD_VDDMAIN reset is enabled.
 */
#define PMC_RESETCTRL_BODVDDMAINRESETENA_SECURE_DP(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODVDDMAINRESETENA_SECURE_DP_SHIFT)) & PMC_RESETCTRL_BODVDDMAINRESETENA_SECURE_DP_MASK)

#define PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_MASK (0xC0000000U)
#define PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_SHIFT (30U)
/*! BODCORERESETENA_SECURE_DP - BOD_CORE reset enable.
 *  0b10..BOD_CORE reset is disabled.
 *  0b01..And any other value than b10: BOD_CORE reset is enabled.
 */
#define PMC_RESETCTRL_BODCORERESETENA_SECURE_DP(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_SHIFT)) & PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_MASK)
/*! @} */

/*! @name RESETCAUSE - Reset Cause */
/*! @{ */

#define PMC_RESETCAUSE_POR_MASK                  (0x1U)
#define PMC_RESETCAUSE_POR_SHIFT                 (0U)
/*! POR - 1 : The last chip reset was caused by a Power On Reset. Write '1' to clear this bit.
 */
#define PMC_RESETCAUSE_POR(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_POR_SHIFT)) & PMC_RESETCAUSE_POR_MASK)

#define PMC_RESETCAUSE_PADRESET_MASK             (0x2U)
#define PMC_RESETCAUSE_PADRESET_SHIFT            (1U)
/*! PADRESET - 1 : The last chip reset was caused by a Pin Reset. Write '1' to clear this bit.
 */
#define PMC_RESETCAUSE_PADRESET(x)               (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_PADRESET_SHIFT)) & PMC_RESETCAUSE_PADRESET_MASK)

#define PMC_RESETCAUSE_BODRESET_MASK             (0x4U)
#define PMC_RESETCAUSE_BODRESET_SHIFT            (2U)
/*! BODRESET - 1 : The last chip reset was caused by a Brown Out Detector (BoD), either BOD_VDDMAIN
 *    or BOD_CORE. Write '1' to clear this bit.
 */
#define PMC_RESETCAUSE_BODRESET(x)               (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_BODRESET_SHIFT)) & PMC_RESETCAUSE_BODRESET_MASK)

#define PMC_RESETCAUSE_SYSTEMRESET_MASK          (0x8U)
#define PMC_RESETCAUSE_SYSTEMRESET_SHIFT         (3U)
/*! SYSTEMRESET - 1 : The last chip reset was caused by a System Reset requested by the ARM CPU. Write '1' to clear this bit.
 */
#define PMC_RESETCAUSE_SYSTEMRESET(x)            (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_SYSTEMRESET_SHIFT)) & PMC_RESETCAUSE_SYSTEMRESET_MASK)

#define PMC_RESETCAUSE_WDTRESET_MASK             (0x10U)
#define PMC_RESETCAUSE_WDTRESET_SHIFT            (4U)
/*! WDTRESET - 1 : The last chip reset was caused by the Watchdog Timer. Write '1' to clear this bit.
 */
#define PMC_RESETCAUSE_WDTRESET(x)               (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_WDTRESET_SHIFT)) & PMC_RESETCAUSE_WDTRESET_MASK)

#define PMC_RESETCAUSE_SWRRESET_MASK             (0x20U)
#define PMC_RESETCAUSE_SWRRESET_SHIFT            (5U)
/*! SWRRESET - 1 : The last chip reset was caused by a Software. Write '1' to clear this bit.
 */
#define PMC_RESETCAUSE_SWRRESET(x)               (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_SWRRESET_SHIFT)) & PMC_RESETCAUSE_SWRRESET_MASK)

#define PMC_RESETCAUSE_DPDRESET_WAKEUPIO_MASK    (0x40U)
#define PMC_RESETCAUSE_DPDRESET_WAKEUPIO_SHIFT   (6U)
/*! DPDRESET_WAKEUPIO - 1 : A Wake-up I/O reset event occured during DEEP-POWER-DOWN mode. Write '1' to clear this bit.
 */
#define PMC_RESETCAUSE_DPDRESET_WAKEUPIO(x)      (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_DPDRESET_WAKEUPIO_SHIFT)) & PMC_RESETCAUSE_DPDRESET_WAKEUPIO_MASK)

#define PMC_RESETCAUSE_DPDRESET_RTC_MASK         (0x80U)
#define PMC_RESETCAUSE_DPDRESET_RTC_SHIFT        (7U)
/*! DPDRESET_RTC - 1 : A RTC (either RTC Alarm or RTC wake up) reset event occured during
 *    DEEP-POWER-DOWN mode. Write '1' to clear this bit.
 */
#define PMC_RESETCAUSE_DPDRESET_RTC(x)           (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_DPDRESET_RTC_SHIFT)) & PMC_RESETCAUSE_DPDRESET_RTC_MASK)

#define PMC_RESETCAUSE_DPDRESET_OSTIMER_MASK     (0x100U)
#define PMC_RESETCAUSE_DPDRESET_OSTIMER_SHIFT    (8U)
/*! DPDRESET_OSTIMER - 1 : A OS Event Timer reset event occured during DEEP-POWER-DOWN mode. Write '1' to clear this bit.
 */
#define PMC_RESETCAUSE_DPDRESET_OSTIMER(x)       (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_DPDRESET_OSTIMER_SHIFT)) & PMC_RESETCAUSE_DPDRESET_OSTIMER_MASK)

#define PMC_RESETCAUSE_CDOGRESET_MASK            (0x200U)
#define PMC_RESETCAUSE_CDOGRESET_SHIFT           (9U)
/*! CDOGRESET - 1 : The last chip reset was caused by the code Watchdog. Write '1' to clear this bit.
 */
#define PMC_RESETCAUSE_CDOGRESET(x)              (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_CDOGRESET_SHIFT)) & PMC_RESETCAUSE_CDOGRESET_MASK)

#define PMC_RESETCAUSE_DPD_EVENTS_ORDER_MASK     (0x1C00U)
#define PMC_RESETCAUSE_DPD_EVENTS_ORDER_SHIFT    (10U)
/*! DPD_EVENTS_ORDER - In DEEP-POWER-DOWN mode, indicates which reset event occured first between
 *    DPDRESET_WAKEUPIO, DPDRESET_RTC and DPDRESET_OSTIMER. Write 'b001' to clear these bit field.
 *  0b000..No event
 *  0b001..WAKEUPIO
 *  0b010..RTC
 *  0b011..Both WAKEUPIO and RTC events occured at the same time (less than 1 nano-second from each other)
 *  0b100..OSTIMER
 *  0b101..Both WAKEUPIO and OSTIMER events occured at the same time (less than 1 nano-second from each other)
 *  0b110..Both RTC and OSTIMER events occured at the same time (less than 1 nano-second from each other)
 *  0b111..WAKEUPIO, RTC and OSTIMER events occured at the same time (less than 1 nano-second from each other)
 */
#define PMC_RESETCAUSE_DPD_EVENTS_ORDER(x)       (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_DPD_EVENTS_ORDER_SHIFT)) & PMC_RESETCAUSE_DPD_EVENTS_ORDER_MASK)
/*! @} */

/*! @name DCDC0 - DCDC (first) control */
/*! @{ */

#define PMC_DCDC0_RC_MASK                        (0x3FU)
#define PMC_DCDC0_RC_SHIFT                       (0U)
/*! RC - Constant On-Time calibration.
 */
#define PMC_DCDC0_RC(x)                          (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_RC_SHIFT)) & PMC_DCDC0_RC_MASK)

#define PMC_DCDC0_ICOMP_MASK                     (0xC0U)
#define PMC_DCDC0_ICOMP_SHIFT                    (6U)
/*! ICOMP - Select the type of ZCD comparator.
 */
#define PMC_DCDC0_ICOMP(x)                       (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_ICOMP_SHIFT)) & PMC_DCDC0_ICOMP_MASK)

#define PMC_DCDC0_ISEL_MASK                      (0x300U)
#define PMC_DCDC0_ISEL_SHIFT                     (8U)
/*! ISEL - Alter Internal biasing currents.
 */
#define PMC_DCDC0_ISEL(x)                        (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_ISEL_SHIFT)) & PMC_DCDC0_ISEL_MASK)

#define PMC_DCDC0_ICENABLE_MASK                  (0x400U)
#define PMC_DCDC0_ICENABLE_SHIFT                 (10U)
/*! ICENABLE - Selection of auto scaling of COT period with variations in VDD.
 */
#define PMC_DCDC0_ICENABLE(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_ICENABLE_SHIFT)) & PMC_DCDC0_ICENABLE_MASK)

#define PMC_DCDC0_TMOS_MASK                      (0xF800U)
#define PMC_DCDC0_TMOS_SHIFT                     (11U)
/*! TMOS - One-shot generator reference current trimming signal.
 */
#define PMC_DCDC0_TMOS(x)                        (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_TMOS_SHIFT)) & PMC_DCDC0_TMOS_MASK)

#define PMC_DCDC0_DISABLEISENSE_MASK             (0x10000U)
#define PMC_DCDC0_DISABLEISENSE_SHIFT            (16U)
/*! DISABLEISENSE - Disable Current sensing.
 */
#define PMC_DCDC0_DISABLEISENSE(x)               (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_DISABLEISENSE_SHIFT)) & PMC_DCDC0_DISABLEISENSE_MASK)

#define PMC_DCDC0_VOUT_MASK                      (0x1E0000U)
#define PMC_DCDC0_VOUT_SHIFT                     (17U)
/*! VOUT - Set output regulation voltage.
 *  0b0000..0.95 V.
 *  0b0001..0.975 V.
 *  0b0010..1 V.
 *  0b0011..1.025 V.
 *  0b0100..1.05 V.
 *  0b0101..1.075 V.
 *  0b0110..1.1 V.
 *  0b0111..1.125 V.
 *  0b1000..1.15 V.
 *  0b1001..1.175 V.
 *  0b1010..1.2 V.
 */
#define PMC_DCDC0_VOUT(x)                        (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_VOUT_SHIFT)) & PMC_DCDC0_VOUT_MASK)

#define PMC_DCDC0_SLICINGENABLE_MASK             (0x200000U)
#define PMC_DCDC0_SLICINGENABLE_SHIFT            (21U)
/*! SLICINGENABLE - Enable staggered switching of power switches.
 */
#define PMC_DCDC0_SLICINGENABLE(x)               (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_SLICINGENABLE_SHIFT)) & PMC_DCDC0_SLICINGENABLE_MASK)

#define PMC_DCDC0_INDUCTORCLAMPENABLE_MASK       (0x400000U)
#define PMC_DCDC0_INDUCTORCLAMPENABLE_SHIFT      (22U)
/*! INDUCTORCLAMPENABLE - Enable shorting of Inductor during PFM idle time.
 */
#define PMC_DCDC0_INDUCTORCLAMPENABLE(x)         (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_INDUCTORCLAMPENABLE_SHIFT)) & PMC_DCDC0_INDUCTORCLAMPENABLE_MASK)

#define PMC_DCDC0_VOUT_PWD_MASK                  (0x7800000U)
#define PMC_DCDC0_VOUT_PWD_SHIFT                 (23U)
/*! VOUT_PWD - Set output regulation voltage during Deep Sleep.
 */
#define PMC_DCDC0_VOUT_PWD(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_VOUT_PWD_SHIFT)) & PMC_DCDC0_VOUT_PWD_MASK)
/*! @} */

/*! @name DCDC1 - DCDC (second) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */
/*! @{ */

#define PMC_DCDC1_RTRIMOFFET_MASK                (0xFU)
#define PMC_DCDC1_RTRIMOFFET_SHIFT               (0U)
/*! RTRIMOFFET - Adjust the offset voltage of BJT based comparator.
 */
#define PMC_DCDC1_RTRIMOFFET(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_RTRIMOFFET_SHIFT)) & PMC_DCDC1_RTRIMOFFET_MASK)

#define PMC_DCDC1_RSENSETRIM_MASK                (0xF0U)
#define PMC_DCDC1_RSENSETRIM_SHIFT               (4U)
/*! RSENSETRIM - Adjust Max inductor peak current limiting.
 */
#define PMC_DCDC1_RSENSETRIM(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_RSENSETRIM_SHIFT)) & PMC_DCDC1_RSENSETRIM_MASK)

#define PMC_DCDC1_DTESTENABLE_MASK               (0x100U)
#define PMC_DCDC1_DTESTENABLE_SHIFT              (8U)
/*! DTESTENABLE - Enable Digital test signals.
 */
#define PMC_DCDC1_DTESTENABLE(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_DTESTENABLE_SHIFT)) & PMC_DCDC1_DTESTENABLE_MASK)

#define PMC_DCDC1_SETCURVE_MASK                  (0x600U)
#define PMC_DCDC1_SETCURVE_SHIFT                 (9U)
/*! SETCURVE - Bandgap calibration parameter.
 */
#define PMC_DCDC1_SETCURVE(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_SETCURVE_SHIFT)) & PMC_DCDC1_SETCURVE_MASK)

#define PMC_DCDC1_SETDC_MASK                     (0x7800U)
#define PMC_DCDC1_SETDC_SHIFT                    (11U)
/*! SETDC - Bandgap calibration parameter.
 */
#define PMC_DCDC1_SETDC(x)                       (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_SETDC_SHIFT)) & PMC_DCDC1_SETDC_MASK)

#define PMC_DCDC1_DTESTSEL_MASK                  (0x38000U)
#define PMC_DCDC1_DTESTSEL_SHIFT                 (15U)
/*! DTESTSEL - Select the output signal for test.
 */
#define PMC_DCDC1_DTESTSEL(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_DTESTSEL_SHIFT)) & PMC_DCDC1_DTESTSEL_MASK)

#define PMC_DCDC1_ISCALEENABLE_MASK              (0x40000U)
#define PMC_DCDC1_ISCALEENABLE_SHIFT             (18U)
/*! ISCALEENABLE - Modify COT behavior.
 */
#define PMC_DCDC1_ISCALEENABLE(x)                (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_ISCALEENABLE_SHIFT)) & PMC_DCDC1_ISCALEENABLE_MASK)

#define PMC_DCDC1_FORCEBYPASS_MASK               (0x80000U)
#define PMC_DCDC1_FORCEBYPASS_SHIFT              (19U)
/*! FORCEBYPASS - Force bypass mode.
 */
#define PMC_DCDC1_FORCEBYPASS(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_FORCEBYPASS_SHIFT)) & PMC_DCDC1_FORCEBYPASS_MASK)

#define PMC_DCDC1_TRIMAUTOCOT_MASK               (0xF00000U)
#define PMC_DCDC1_TRIMAUTOCOT_SHIFT              (20U)
/*! TRIMAUTOCOT - Change the scaling ratio of the feedforward compensation.
 */
#define PMC_DCDC1_TRIMAUTOCOT(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_TRIMAUTOCOT_SHIFT)) & PMC_DCDC1_TRIMAUTOCOT_MASK)

#define PMC_DCDC1_FORCEFULLCYCLE_MASK            (0x1000000U)
#define PMC_DCDC1_FORCEFULLCYCLE_SHIFT           (24U)
/*! FORCEFULLCYCLE - Force full PFM PMOS and NMOS cycle.
 */
#define PMC_DCDC1_FORCEFULLCYCLE(x)              (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_FORCEFULLCYCLE_SHIFT)) & PMC_DCDC1_FORCEFULLCYCLE_MASK)

#define PMC_DCDC1_LCENABLE_MASK                  (0x2000000U)
#define PMC_DCDC1_LCENABLE_SHIFT                 (25U)
/*! LCENABLE - Change the range of the peak detector of current inside the inductor.
 */
#define PMC_DCDC1_LCENABLE(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_LCENABLE_SHIFT)) & PMC_DCDC1_LCENABLE_MASK)

#define PMC_DCDC1_TOFF_MASK                      (0x7C000000U)
#define PMC_DCDC1_TOFF_SHIFT                     (26U)
/*! TOFF - Constant Off-Time calibration input.
 */
#define PMC_DCDC1_TOFF(x)                        (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_TOFF_SHIFT)) & PMC_DCDC1_TOFF_MASK)

#define PMC_DCDC1_TOFFENABLE_MASK                (0x80000000U)
#define PMC_DCDC1_TOFFENABLE_SHIFT               (31U)
/*! TOFFENABLE - Enable Constant Off-Time feature.
 */
#define PMC_DCDC1_TOFFENABLE(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_TOFFENABLE_SHIFT)) & PMC_DCDC1_TOFFENABLE_MASK)
/*! @} */

/*! @name LDOPMU - Power Management Unit (PMU) and Always-On domains LDO control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */
/*! @{ */

#define PMC_LDOPMU_VADJ_MASK                     (0x1FU)
#define PMC_LDOPMU_VADJ_SHIFT                    (0U)
/*! VADJ - Sets the Always-On domain LDO output level.
 *  0b00000..1.22 V.
 *  0b00001..0.7 V.
 *  0b00010..0.725 V.
 *  0b00011..0.75 V.
 *  0b00100..0.775 V.
 *  0b00101..0.8 V.
 *  0b00110..0.825 V.
 *  0b00111..0.85 V.
 *  0b01000..0.875 V.
 *  0b01001..0.9 V.
 *  0b01010..0.96 V.
 *  0b01011..0.97 V.
 *  0b01100..0.98 V.
 *  0b01101..0.99 V.
 *  0b01110..1 V.
 *  0b01111..1.01 V.
 *  0b10000..1.02 V.
 *  0b10001..1.03 V.
 *  0b10010..1.04 V.
 *  0b10011..1.05 V.
 *  0b10100..1.06 V.
 *  0b10101..1.07 V.
 *  0b10110..1.08 V.
 *  0b10111..1.09 V.
 *  0b11000..1.1 V.
 *  0b11001..1.11 V.
 *  0b11010..1.12 V.
 *  0b11011..1.13 V.
 *  0b11100..1.14 V.
 *  0b11101..1.15 V.
 *  0b11110..1.16 V.
 *  0b11111..1.22 V.
 */
#define PMC_LDOPMU_VADJ(x)                       (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_SHIFT)) & PMC_LDOPMU_VADJ_MASK)

#define PMC_LDOPMU_VADJ_PWD_MASK                 (0x3E0U)
#define PMC_LDOPMU_VADJ_PWD_SHIFT                (5U)
/*! VADJ_PWD - Sets the Always-On domain LDO output level in all power down modes.
 */
#define PMC_LDOPMU_VADJ_PWD(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_PWD_SHIFT)) & PMC_LDOPMU_VADJ_PWD_MASK)

#define PMC_LDOPMU_VADJ_BOOST_MASK               (0x7C00U)
#define PMC_LDOPMU_VADJ_BOOST_SHIFT              (10U)
/*! VADJ_BOOST - Sets the Always-On domain LDO Boost output level.
 */
#define PMC_LDOPMU_VADJ_BOOST(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_BOOST_SHIFT)) & PMC_LDOPMU_VADJ_BOOST_MASK)

#define PMC_LDOPMU_VADJ_BOOST_PWD_MASK           (0xF8000U)
#define PMC_LDOPMU_VADJ_BOOST_PWD_SHIFT          (15U)
/*! VADJ_BOOST_PWD - Sets the Always-On domain LDO Boost output level in all power down modes.
 */
#define PMC_LDOPMU_VADJ_BOOST_PWD(x)             (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_BOOST_PWD_SHIFT)) & PMC_LDOPMU_VADJ_BOOST_PWD_MASK)
/*! @} */

/*! @name LDOMEM - Memories LDO control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */
/*! @{ */

#define PMC_LDOMEM_VADJ_MASK                     (0x1FU)
#define PMC_LDOMEM_VADJ_SHIFT                    (0U)
/*! VADJ - Sets the Memories LDO output level.
 *  0b00000..1.22 V.
 *  0b00001..0.7 V.
 *  0b00010..0.725 V.
 *  0b00011..0.75 V.
 *  0b00100..0.775 V.
 *  0b00101..0.8 V.
 *  0b00110..0.825 V.
 *  0b00111..0.85 V.
 *  0b01000..0.875 V.
 *  0b01001..0.9 V.
 *  0b01010..0.96 V.
 *  0b01011..0.97 V.
 *  0b01100..0.98 V.
 *  0b01101..0.99 V.
 *  0b01110..1 V.
 *  0b01111..1.01 V.
 *  0b10000..1.02 V.
 *  0b10001..1.03 V.
 *  0b10010..1.04 V.
 *  0b10011..1.05 V.
 *  0b10100..1.06 V.
 *  0b10101..1.07 V.
 *  0b10110..1.08 V.
 *  0b10111..1.09 V.
 *  0b11000..1.1 V.
 *  0b11001..1.11 V.
 *  0b11010..1.12 V.
 *  0b11011..1.13 V.
 *  0b11100..1.14 V.
 *  0b11101..1.15 V.
 *  0b11110..1.16 V.
 *  0b11111..1.22 V.
 */
#define PMC_LDOMEM_VADJ(x)                       (((uint32_t)(((uint32_t)(x)) << PMC_LDOMEM_VADJ_SHIFT)) & PMC_LDOMEM_VADJ_MASK)

#define PMC_LDOMEM_VADJ_PWD_MASK                 (0x3E0U)
#define PMC_LDOMEM_VADJ_PWD_SHIFT                (5U)
/*! VADJ_PWD - Sets the Memories LDO output level in all power down modes.
 */
#define PMC_LDOMEM_VADJ_PWD(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_LDOMEM_VADJ_PWD_SHIFT)) & PMC_LDOMEM_VADJ_PWD_MASK)

#define PMC_LDOMEM_VADJ_BOOST_MASK               (0x7C00U)
#define PMC_LDOMEM_VADJ_BOOST_SHIFT              (10U)
/*! VADJ_BOOST - Sets the Memories LDO Boost output level.
 */
#define PMC_LDOMEM_VADJ_BOOST(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_LDOMEM_VADJ_BOOST_SHIFT)) & PMC_LDOMEM_VADJ_BOOST_MASK)

#define PMC_LDOMEM_VADJ_BOOST_PWD_MASK           (0xF8000U)
#define PMC_LDOMEM_VADJ_BOOST_PWD_SHIFT          (15U)
/*! VADJ_BOOST_PWD - Sets the Memories LDO Boost output level in all power down modes.
 */
#define PMC_LDOMEM_VADJ_BOOST_PWD(x)             (((uint32_t)(((uint32_t)(x)) << PMC_LDOMEM_VADJ_BOOST_PWD_SHIFT)) & PMC_LDOMEM_VADJ_BOOST_PWD_MASK)
/*! @} */

/*! @name LDOCORE0 - LDO CORE (first) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */
/*! @{ */

#define PMC_LDOCORE0_LPREGREFSEL_MASK            (0x60000U)
#define PMC_LDOCORE0_LPREGREFSEL_SHIFT           (17U)
/*! LPREGREFSEL - Low Power regulation point select.
 *  0b00..900 mV.
 *  0b01..850 mV.
 *  0b10..800 mV.
 *  0b11..750 mV.
 */
#define PMC_LDOCORE0_LPREGREFSEL(x)              (((uint32_t)(((uint32_t)(x)) << PMC_LDOCORE0_LPREGREFSEL_SHIFT)) & PMC_LDOCORE0_LPREGREFSEL_MASK)

#define PMC_LDOCORE0_REGREFTRIM_MASK             (0x7F000000U)
#define PMC_LDOCORE0_REGREFTRIM_SHIFT            (24U)
/*! REGREFTRIM - High Power regulation point select.
 */
#define PMC_LDOCORE0_REGREFTRIM(x)               (((uint32_t)(((uint32_t)(x)) << PMC_LDOCORE0_REGREFTRIM_SHIFT)) & PMC_LDOCORE0_REGREFTRIM_MASK)
/*! @} */

/*! @name LDOFLASHNV - Flash High Voltage LDO control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */
/*! @{ */

#define PMC_LDOFLASHNV_VADJ_MASK                 (0x7U)
#define PMC_LDOFLASHNV_VADJ_SHIFT                (0U)
/*! VADJ - Sets the LDO output level.
 *  0b000..1.650 V.
 *  0b001..1.700 V.
 *  0b010..1.750 V.
 *  0b011..1.800 V.
 *  0b100..1.850 V.
 *  0b101..1.900 V.
 *  0b110..1.950 V.
 *  0b111..2.0 V.
 */
#define PMC_LDOFLASHNV_VADJ(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_LDOFLASHNV_VADJ_SHIFT)) & PMC_LDOFLASHNV_VADJ_MASK)
/*! @} */

/*! @name LDOEFUSEPROG - eFUSE (One Time Programmable Memory) Programming LDO control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */
/*! @{ */

#define PMC_LDOEFUSEPROG_VADJ_MASK               (0x7U)
#define PMC_LDOEFUSEPROG_VADJ_SHIFT              (0U)
/*! VADJ - Sets the LDO output level.
 *  0b000..1.650 V.
 *  0b001..1.700 V.
 *  0b010..1.750 V.
 *  0b011..1.800 V.
 *  0b100..1.850 V.
 *  0b101..1.900 V.
 *  0b110..1.950 V.
 *  0b111..2.0 V.
 */
#define PMC_LDOEFUSEPROG_VADJ(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_LDOEFUSEPROG_VADJ_SHIFT)) & PMC_LDOEFUSEPROG_VADJ_MASK)
/*! @} */

/*! @name BODVDDMAIN - VDDMAIN Brown Out Dectector control */
/*! @{ */

#define PMC_BODVDDMAIN_TRIGLVL_MASK              (0x1FU)
#define PMC_BODVDDMAIN_TRIGLVL_SHIFT             (0U)
/*! TRIGLVL - BoD trigger level.
 *  0b00000..1.00 V.
 *  0b00001..1.10 V.
 *  0b00010..1.20 V.
 *  0b00011..1.30 V.
 *  0b00100..1.40 V.
 *  0b00101..1.50 V.
 *  0b00110..1.60 V.
 *  0b00111..1.65 V.
 *  0b01000..1.70 V.
 *  0b01001..1.75 V.
 *  0b01010..1.80 V.
 *  0b01011..1.90 V.
 *  0b01100..2.00 V.
 *  0b01101..2.10 V.
 *  0b01110..2.20 V.
 *  0b01111..2.30 V.
 *  0b10000..2.40 V.
 *  0b10001..2.50 V.
 *  0b10010..2.60 V.
 *  0b10011..2.70 V.
 *  0b10100..2.80 V.
 *  0b10101..2.90 V.
 *  0b10110..3.00 V.
 *  0b10111..3.10 V.
 *  0b11000..3.20 V.
 *  0b11001..3.30 V.
 *  0b11010..3.30 V.
 *  0b11011..3.30 V.
 *  0b11100..3.30 V.
 *  0b11101..3.30 V.
 *  0b11110..3.30 V.
 *  0b11111..3.30 V.
 */
#define PMC_BODVDDMAIN_TRIGLVL(x)                (((uint32_t)(((uint32_t)(x)) << PMC_BODVDDMAIN_TRIGLVL_SHIFT)) & PMC_BODVDDMAIN_TRIGLVL_MASK)

#define PMC_BODVDDMAIN_HYST_MASK                 (0x60U)
#define PMC_BODVDDMAIN_HYST_SHIFT                (5U)
/*! HYST - BoD Hysteresis control.
 *  0b00..25 mV.
 *  0b01..50 mV.
 *  0b10..75 mV.
 *  0b11..100 mV.
 */
#define PMC_BODVDDMAIN_HYST(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_BODVDDMAIN_HYST_SHIFT)) & PMC_BODVDDMAIN_HYST_MASK)
/*! @} */

/*! @name BODCORE - Digital Core logic Brown Out Dectector control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */
/*! @{ */

#define PMC_BODCORE_TRIGLVL_MASK                 (0x7U)
#define PMC_BODCORE_TRIGLVL_SHIFT                (0U)
/*! TRIGLVL - BoD trigger level.
 *  0b000..0.60 V.
 *  0b001..0.65 V.
 *  0b010..0.70 V.
 *  0b011..0.75 V.
 *  0b100..0.80 V.
 *  0b101..0.85 V.
 *  0b110..0.90 V.
 *  0b111..0.95 V.
 */
#define PMC_BODCORE_TRIGLVL(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_BODCORE_TRIGLVL_SHIFT)) & PMC_BODCORE_TRIGLVL_MASK)

#define PMC_BODCORE_HYST_MASK                    (0x30U)
#define PMC_BODCORE_HYST_SHIFT                   (4U)
/*! HYST - BOD_CORE Hysteresis control.
 *  0b00..25 mV.
 *  0b01..50 mV.
 *  0b10..75 mV.
 *  0b11..100 mV.
 */
#define PMC_BODCORE_HYST(x)                      (((uint32_t)(((uint32_t)(x)) << PMC_BODCORE_HYST_SHIFT)) & PMC_BODCORE_HYST_MASK)
/*! @} */

/*! @name REFFASTWKUP - Analog References fast wake-up Control register [Reset by: PoR] */
/*! @{ */

#define PMC_REFFASTWKUP_LPWKUP_MASK              (0x1U)
#define PMC_REFFASTWKUP_LPWKUP_SHIFT             (0U)
/*! LPWKUP - Analog References fast wake-up in case of wake-up from a low power mode (DEEP-SLEEP, POWER-DOWN and DEEP-POWER-DOWN):
 *  0b0..Analog References fast wake-up feature is disabled in case of wake-up from any Low power mode.
 *  0b1..Analog References fast wake-up feature is enabled in case of wake-up from any Low power mode.
 */
#define PMC_REFFASTWKUP_LPWKUP(x)                (((uint32_t)(((uint32_t)(x)) << PMC_REFFASTWKUP_LPWKUP_SHIFT)) & PMC_REFFASTWKUP_LPWKUP_MASK)

#define PMC_REFFASTWKUP_HWWKUP_MASK              (0x2U)
#define PMC_REFFASTWKUP_HWWKUP_SHIFT             (1U)
/*! HWWKUP - Analog References fast wake-up in case of Hardware Pin reset:
 *  0b0..Analog References fast wake-up feature is disabled in case of Hardware Pin reset.
 *  0b1..Analog References fast wake-up feature is enabled in case of Hardware Pin reset.
 */
#define PMC_REFFASTWKUP_HWWKUP(x)                (((uint32_t)(((uint32_t)(x)) << PMC_REFFASTWKUP_HWWKUP_SHIFT)) & PMC_REFFASTWKUP_HWWKUP_MASK)
/*! @} */

/*! @name XTAL32K - 32 KHz Crystal oscillator (XTAL) control register [Reset by: PoR, Brown Out Detectors Reset] */
/*! @{ */

#define PMC_XTAL32K_TEST_MASK                    (0x8U)
#define PMC_XTAL32K_TEST_SHIFT                   (3U)
/*! TEST - Oscillator Bypass Test Mode control.
 *  0b0..Oscillation mode.
 *  0b1..Bypass test mode is enabled.
 */
#define PMC_XTAL32K_TEST(x)                      (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_TEST_SHIFT)) & PMC_XTAL32K_TEST_MASK)

#define PMC_XTAL32K_CAPBANKIN_MASK               (0x7F00U)
#define PMC_XTAL32K_CAPBANKIN_SHIFT              (8U)
/*! CAPBANKIN - Capa bank setting input.
 */
#define PMC_XTAL32K_CAPBANKIN(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPBANKIN_SHIFT)) & PMC_XTAL32K_CAPBANKIN_MASK)

#define PMC_XTAL32K_CAPBANKOUT_MASK              (0x3F8000U)
#define PMC_XTAL32K_CAPBANKOUT_SHIFT             (15U)
/*! CAPBANKOUT - Capa bank setting output.
 */
#define PMC_XTAL32K_CAPBANKOUT(x)                (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPBANKOUT_SHIFT)) & PMC_XTAL32K_CAPBANKOUT_MASK)
/*! @} */

/*! @name COMP - Analog Comparator control */
/*! @{ */

#define PMC_COMP_HYST_MASK                       (0x2U)
#define PMC_COMP_HYST_SHIFT                      (1U)
/*! HYST - Hysteris when hyst = '1'.
 *  0b0..Hysteresis is disabled.
 *  0b1..Hysteresis is enabled.
 */
#define PMC_COMP_HYST(x)                         (((uint32_t)(((uint32_t)(x)) << PMC_COMP_HYST_SHIFT)) & PMC_COMP_HYST_MASK)

#define PMC_COMP_VREFINPUT_MASK                  (0x4U)
#define PMC_COMP_VREFINPUT_SHIFT                 (2U)
/*! VREFINPUT - Dedicated control bit to select between internal VREF and VDDA (for the resistive ladder).
 *  0b0..Select internal VREF.
 *  0b1..Select VDDA.
 */
#define PMC_COMP_VREFINPUT(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_COMP_VREFINPUT_SHIFT)) & PMC_COMP_VREFINPUT_MASK)

#define PMC_COMP_LOWPOWER_MASK                   (0x8U)
#define PMC_COMP_LOWPOWER_SHIFT                  (3U)
/*! LOWPOWER - Low power mode.
 *  0b0..High speed mode.
 *  0b1..Low power mode (Low speed).
 */
#define PMC_COMP_LOWPOWER(x)                     (((uint32_t)(((uint32_t)(x)) << PMC_COMP_LOWPOWER_SHIFT)) & PMC_COMP_LOWPOWER_MASK)

#define PMC_COMP_PMUX_MASK                       (0x70U)
#define PMC_COMP_PMUX_SHIFT                      (4U)
/*! PMUX - Control word for P multiplexer:.
 *  0b000..VREF (See field VREFINPUT).
 *  0b001..Pin P0_0.
 *  0b010..Pin P0_9.
 *  0b011..Pin P0_18.
 *  0b100..Pin P1_14.
 *  0b101..Pin P2_23.
 */
#define PMC_COMP_PMUX(x)                         (((uint32_t)(((uint32_t)(x)) << PMC_COMP_PMUX_SHIFT)) & PMC_COMP_PMUX_MASK)

#define PMC_COMP_NMUX_MASK                       (0x380U)
#define PMC_COMP_NMUX_SHIFT                      (7U)
/*! NMUX - Control word for N multiplexer:.
 *  0b000..VREF (See field VREFINPUT).
 *  0b001..Pin P0_0.
 *  0b010..Pin P0_9.
 *  0b011..Pin P0_18.
 *  0b100..Pin P1_14.
 *  0b101..Pin P2_23.
 */
#define PMC_COMP_NMUX(x)                         (((uint32_t)(((uint32_t)(x)) << PMC_COMP_NMUX_SHIFT)) & PMC_COMP_NMUX_MASK)

#define PMC_COMP_VREF_MASK                       (0x7C00U)
#define PMC_COMP_VREF_SHIFT                      (10U)
/*! VREF - Control reference voltage step, per steps of (VREFINPUT/31).
 */
#define PMC_COMP_VREF(x)                         (((uint32_t)(((uint32_t)(x)) << PMC_COMP_VREF_SHIFT)) & PMC_COMP_VREF_MASK)

#define PMC_COMP_FILTERCGF_SAMPLEMODE_MASK       (0x30000U)
#define PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT      (16U)
/*! FILTERCGF_SAMPLEMODE - Control the filtering of the Analog Comparator output.
 *  0b00..Bypass mode.
 *  0b01..Filter 1 clock period.
 *  0b10..Filter 2 clock period.
 *  0b11..Filter 3 clock period.
 */
#define PMC_COMP_FILTERCGF_SAMPLEMODE(x)         (((uint32_t)(((uint32_t)(x)) << PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT)) & PMC_COMP_FILTERCGF_SAMPLEMODE_MASK)

#define PMC_COMP_FILTERCGF_CLKDIV_MASK           (0x1C0000U)
#define PMC_COMP_FILTERCGF_CLKDIV_SHIFT          (18U)
/*! FILTERCGF_CLKDIV - Filter Clock divider.
 *  0b000..Filter clock period duration equals 1 Analog Comparator clock period.
 *  0b001..Filter clock period duration equals 2 Analog Comparator clock period.
 *  0b010..Filter clock period duration equals 4 Analog Comparator clock period.
 *  0b011..Filter clock period duration equals 8 Analog Comparator clock period.
 *  0b100..Filter clock period duration equals 16 Analog Comparator clock period.
 *  0b101..Filter clock period duration equals 32 Analog Comparator clock period.
 *  0b110..Filter clock period duration equals 64 Analog Comparator clock period.
 *  0b111..Filter clock period duration equals 128 Analog Comparator clock period.
 */
#define PMC_COMP_FILTERCGF_CLKDIV(x)             (((uint32_t)(((uint32_t)(x)) << PMC_COMP_FILTERCGF_CLKDIV_SHIFT)) & PMC_COMP_FILTERCGF_CLKDIV_MASK)
/*! @} */

/*! @name CMD - DCDC and LDOCORE power state (enable/disable) control. */
/*! @{ */

#define PMC_CMD_DCDCENABLE_MASK                  (0x1U)
#define PMC_CMD_DCDCENABLE_SHIFT                 (0U)
/*! DCDCENABLE - Enable DCDC (self clearing bit).
 *  0b0..No effect.
 *  0b1..Enable DCDC. Automatically reset to '0' by the Hardware.
 */
#define PMC_CMD_DCDCENABLE(x)                    (((uint32_t)(((uint32_t)(x)) << PMC_CMD_DCDCENABLE_SHIFT)) & PMC_CMD_DCDCENABLE_MASK)

#define PMC_CMD_DCDCDISABLE_MASK                 (0x2U)
#define PMC_CMD_DCDCDISABLE_SHIFT                (1U)
/*! DCDCDISABLE - Disable DCDC (self clearing bit).
 *  0b0..No effect.
 *  0b1..Disbale DCDC. Automatically reset to '0' by the Hardware.
 */
#define PMC_CMD_DCDCDISABLE(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_CMD_DCDCDISABLE_SHIFT)) & PMC_CMD_DCDCDISABLE_MASK)

#define PMC_CMD_LDOCOREHIGHPWRENABLE_MASK        (0x4U)
#define PMC_CMD_LDOCOREHIGHPWRENABLE_SHIFT       (2U)
/*! LDOCOREHIGHPWRENABLE - Enable LDO CORE High Power Mode (self clearing bit).
 *  0b0..No effect.
 *  0b1..Enable LDO CORE High Power Mode. Automatically reset to '0' by the Hardware.
 */
#define PMC_CMD_LDOCOREHIGHPWRENABLE(x)          (((uint32_t)(((uint32_t)(x)) << PMC_CMD_LDOCOREHIGHPWRENABLE_SHIFT)) & PMC_CMD_LDOCOREHIGHPWRENABLE_MASK)

#define PMC_CMD_LDOCOREHIGHPWRDISABLE_MASK       (0x8U)
#define PMC_CMD_LDOCOREHIGHPWRDISABLE_SHIFT      (3U)
/*! LDOCOREHIGHPWRDISABLE - Disable LDO CORE High Power Mode (self clearing bit).
 *  0b0..No effect.
 *  0b1..Disable LDO CORE High Power Mode. Automatically reset to '0' by the Hardware.
 */
#define PMC_CMD_LDOCOREHIGHPWRDISABLE(x)         (((uint32_t)(((uint32_t)(x)) << PMC_CMD_LDOCOREHIGHPWRDISABLE_SHIFT)) & PMC_CMD_LDOCOREHIGHPWRDISABLE_MASK)

#define PMC_CMD_LDOCORELOWPWRENABLE_MASK         (0x10U)
#define PMC_CMD_LDOCORELOWPWRENABLE_SHIFT        (4U)
/*! LDOCORELOWPWRENABLE - Enable LDO CORE Low Power Mode (self clearing bit).
 *  0b0..No effect.
 *  0b1..Enable LDO CORE Low Power Mode. Automatically reset to '0' by the Hardware.
 */
#define PMC_CMD_LDOCORELOWPWRENABLE(x)           (((uint32_t)(((uint32_t)(x)) << PMC_CMD_LDOCORELOWPWRENABLE_SHIFT)) & PMC_CMD_LDOCORELOWPWRENABLE_MASK)

#define PMC_CMD_LDOCORELOWPWRDISABLE_MASK        (0x20U)
#define PMC_CMD_LDOCORELOWPWRDISABLE_SHIFT       (5U)
/*! LDOCORELOWPWRDISABLE - Disable LDO CORE Low Power Mode (self clearing bit).
 *  0b0..No effect.
 *  0b1..Disable LDO CORE Low Power Mode. Automatically reset to '0' by the Hardware.
 */
#define PMC_CMD_LDOCORELOWPWRDISABLE(x)          (((uint32_t)(((uint32_t)(x)) << PMC_CMD_LDOCORELOWPWRDISABLE_SHIFT)) & PMC_CMD_LDOCORELOWPWRDISABLE_MASK)
/*! @} */

/*! @name WAKEUPIOCTRL - Deep Power Down wake-up source [Reset by: PoR, Pin Reset, Software Reset] */
/*! @{ */

#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_MASK  (0x1U)
#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_SHIFT (0U)
/*! RISINGEDGEWAKEUP0 - Enable / disable detection of rising edge events on Wake Up 0 pin in Deep Power Down modes:.
 *  0b0..Rising edge detection is disabled.
 *  0b1..Rising edge detection is enabled.
 */
#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0(x)    (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_MASK)

#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_MASK (0x2U)
#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_SHIFT (1U)
/*! FALLINGEDGEWAKEUP0 - Enable / disable detection of falling edge events on Wake Up 0 pin in Deep Power Down modes:.
 *  0b0..Falling edge detection is disabled.
 *  0b1..Falling edge detection is enabled.
 */
#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0(x)   (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_MASK)

#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_MASK  (0x4U)
#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_SHIFT (2U)
/*! RISINGEDGEWAKEUP1 - Enable / disable detection of rising edge events on Wake Up 1 pin in Deep Power Down modes:.
 *  0b0..Rising edge detection is disabled.
 *  0b1..Rising edge detection is enabled.
 */
#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1(x)    (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_MASK)

#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_MASK (0x8U)
#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_SHIFT (3U)
/*! FALLINGEDGEWAKEUP1 - Enable / disable detection of falling edge events on Wake Up 1 pin in Deep Power Down modes:.
 *  0b0..Falling edge detection is disabled.
 *  0b1..Falling edge detection is enabled.
 */
#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1(x)   (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_MASK)

#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_MASK  (0x10U)
#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_SHIFT (4U)
/*! RISINGEDGEWAKEUP2 - Enable / disable detection of rising edge events on Wake Up 2 pin in Deep Power Down modes:.
 *  0b0..Rising edge detection is disabled.
 *  0b1..Rising edge detection is enabled.
 */
#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2(x)    (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_MASK)

#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_MASK (0x20U)
#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_SHIFT (5U)
/*! FALLINGEDGEWAKEUP2 - Enable / disable detection of falling edge events on Wake Up 2 pin in Deep Power Down modes:.
 *  0b0..Falling edge detection is disabled.
 *  0b1..Falling edge detection is enabled.
 */
#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2(x)   (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_MASK)

#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_MASK  (0x40U)
#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_SHIFT (6U)
/*! RISINGEDGEWAKEUP3 - Enable / disable detection of rising edge events on Wake Up 3 pin in Deep Power Down modes:
 *  0b0..Rising edge detection is disabled.
 *  0b1..Rising edge detection is enabled.
 */
#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3(x)    (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_MASK)

#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_MASK (0x80U)
#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_SHIFT (7U)
/*! FALLINGEDGEWAKEUP3 - Enable / disable detection of falling edge events on Wake Up 3 pin in Deep Power Down modes:
 *  0b0..Falling edge detection is disabled.
 *  0b1..Falling edge detection is enabled.
 */
#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3(x)   (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_MASK)

#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP4_MASK  (0x100U)
#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP4_SHIFT (8U)
/*! RISINGEDGEWAKEUP4 - Enable / disable detection of rising edge events on Wake Up 4 pin in Deep Power Down modes:
 *  0b0..Rising edge detection is disabled.
 *  0b1..Rising edge detection is enabled.
 */
#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP4(x)    (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP4_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP4_MASK)

#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP4_MASK (0x200U)
#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP4_SHIFT (9U)
/*! FALLINGEDGEWAKEUP4 - Enable / disable detection of falling edge events on Wake Up 4 pin in Deep Power Down modes:
 *  0b0..Falling edge detection is disabled.
 *  0b1..Falling edge detection is enabled.
 */
#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP4(x)   (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP4_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP4_MASK)

#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD0_MASK   (0xC00U)
#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD0_SHIFT  (10U)
/*! MODEWAKEUPIOPAD0 - Selects function mode (on-chip pull-up/pull-down resistor control).
 *  0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled).
 *  0b01..Pull-down. Pull-down resistor enabled.
 *  0b10..Pull-up. Pull-up resistor enabled.
 *  0b11..Repeater. Repeater mode.
 */
#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD0(x)     (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD0_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD0_MASK)

#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD1_MASK   (0x3000U)
#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD1_SHIFT  (12U)
/*! MODEWAKEUPIOPAD1 - Selects function mode (on-chip pull-up/pull-down resistor control).
 *  0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled).
 *  0b01..Pull-down. Pull-down resistor enabled.
 *  0b10..Pull-up. Pull-up resistor enabled.
 *  0b11..Repeater. Repeater mode.
 */
#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD1(x)     (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD1_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD1_MASK)

#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD2_MASK   (0xC000U)
#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD2_SHIFT  (14U)
/*! MODEWAKEUPIOPAD2 - Selects function mode (on-chip pull-up/pull-down resistor control).
 *  0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled).
 *  0b01..Pull-down. Pull-down resistor enabled.
 *  0b10..Pull-up. Pull-up resistor enabled.
 *  0b11..Repeater. Repeater mode.
 */
#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD2(x)     (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD2_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD2_MASK)

#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD3_MASK   (0x30000U)
#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD3_SHIFT  (16U)
/*! MODEWAKEUPIOPAD3 - Selects function mode (on-chip pull-up/pull-down resistor control).
 *  0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled).
 *  0b01..Pull-down. Pull-down resistor enabled.
 *  0b10..Pull-up. Pull-up resistor enabled.
 *  0b11..Repeater. Repeater mode.
 */
#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD3(x)     (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD3_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD3_MASK)

#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD4_MASK   (0xC0000U)
#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD4_SHIFT  (18U)
/*! MODEWAKEUPIOPAD4 - Selects function mode (on-chip pull-up/pull-down resistor control).
 *  0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled).
 *  0b01..Pull-down. Pull-down resistor enabled.
 *  0b10..Pull-up. Pull-up resistor enabled.
 *  0b11..Repeater. Repeater mode.
 */
#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD4(x)     (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD4_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD4_MASK)

#define PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL_MASK (0x100000U)
#define PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL_SHIFT (20U)
/*! WAKEUPIO_ENABLE_CTRL - Enable WAKEUP IO PAD control from MODEWAKEUPIOPAD (bits 10 to 19).
 *  0b0..WAKEUP IO PAD mode control comes from IOCON.
 *  0b1..WAKEUP IO PAD mode control comes from MODEWAKEUPIOPAD (bits 10 to 19).
 */
#define PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL_SHIFT)) & PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL_MASK)

#define PMC_WAKEUPIOCTRL_WAKEUPIO_RSTN_MASK      (0x200000U)
#define PMC_WAKEUPIOCTRL_WAKEUPIO_RSTN_SHIFT     (21U)
/*! WAKEUPIO_RSTN - WAKEUP IO event detector reset control.
 *  0b0..Bloc is reset.
 *  0b1..Bloc is not reset.
 */
#define PMC_WAKEUPIOCTRL_WAKEUPIO_RSTN(x)        (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_WAKEUPIO_RSTN_SHIFT)) & PMC_WAKEUPIOCTRL_WAKEUPIO_RSTN_MASK)
/*! @} */

/*! @name WAKEIOCAUSE - Wake-up I/O source */
/*! @{ */

#define PMC_WAKEIOCAUSE_WAKEUP0_MASK             (0x1U)
#define PMC_WAKEIOCAUSE_WAKEUP0_SHIFT            (0U)
/*! WAKEUP0 - Allows to identify Wake up I/O 0 as the wake-up source from Deep Power Down mode.
 *  0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 0.
 *  0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 0.
 */
#define PMC_WAKEIOCAUSE_WAKEUP0(x)               (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP0_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP0_MASK)

#define PMC_WAKEIOCAUSE_WAKEUP1_MASK             (0x2U)
#define PMC_WAKEIOCAUSE_WAKEUP1_SHIFT            (1U)
/*! WAKEUP1 - Allows to identify Wake up I/O 1 as the wake-up source from Deep Power Down mode.
 *  0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 1.
 *  0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 1.
 */
#define PMC_WAKEIOCAUSE_WAKEUP1(x)               (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP1_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP1_MASK)

#define PMC_WAKEIOCAUSE_WAKEUP2_MASK             (0x4U)
#define PMC_WAKEIOCAUSE_WAKEUP2_SHIFT            (2U)
/*! WAKEUP2 - Allows to identify Wake up I/O 2 as the wake-up source from Deep Power Down mode.
 *  0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 2.
 *  0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 2.
 */
#define PMC_WAKEIOCAUSE_WAKEUP2(x)               (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP2_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP2_MASK)

#define PMC_WAKEIOCAUSE_WAKEUP3_MASK             (0x8U)
#define PMC_WAKEIOCAUSE_WAKEUP3_SHIFT            (3U)
/*! WAKEUP3 - Allows to identify Wake up I/O 3 as the wake-up source from Deep Power Down mode.
 *  0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 3.
 *  0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 3.
 */
#define PMC_WAKEIOCAUSE_WAKEUP3(x)               (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP3_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP3_MASK)

#define PMC_WAKEIOCAUSE_WAKEUP4_MASK             (0x10U)
#define PMC_WAKEIOCAUSE_WAKEUP4_SHIFT            (4U)
/*! WAKEUP4 - Allows to identify Wake up I/O 4 as the wake-up source from Deep Power Down mode.
 *  0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 4.
 *  0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 4.
 */
#define PMC_WAKEIOCAUSE_WAKEUP4(x)               (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP4_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP4_MASK)

#define PMC_WAKEIOCAUSE_WAKEUPIO_EVENTS_ORDER_MASK (0x3E0U)
#define PMC_WAKEIOCAUSE_WAKEUPIO_EVENTS_ORDER_SHIFT (5U)
/*! WAKEUPIO_EVENTS_ORDER - In DEEP-POWER-DOWN mode, indicates which wake up I/O event occured first when several wake up I/Os are enabled.
 *  0b00000..None
 *  0b00001..Wake up I/O 0
 *  0b00010..Wake up I/O 1
 *  0b00100..Wake up I/O 2
 *  0b01000..Wake up I/O 3
 *  0b10000..Wake up I/O 4
 */
#define PMC_WAKEIOCAUSE_WAKEUPIO_EVENTS_ORDER(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUPIO_EVENTS_ORDER_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUPIO_EVENTS_ORDER_MASK)
/*! @} */

/*! @name LIFECYCLESTATE - Life Cycle State as configured in the OTP */
/*! @{ */

#define PMC_LIFECYCLESTATE_LC_MASK               (0xFFU)
#define PMC_LIFECYCLESTATE_LC_SHIFT              (0U)
/*! LC - Life Cycle state
 */
#define PMC_LIFECYCLESTATE_LC(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_LIFECYCLESTATE_LC_SHIFT)) & PMC_LIFECYCLESTATE_LC_MASK)
/*! @} */

/*! @name STATUSPWR - Power status from various analog modules (DCDC, LDO, etc) */
/*! @{ */

#define PMC_STATUSPWR_DCDCPWROK_MASK             (0x1U)
#define PMC_STATUSPWR_DCDCPWROK_SHIFT            (0U)
/*! DCDCPWROK - DCDC converter power OK.
 */
#define PMC_STATUSPWR_DCDCPWROK(x)               (((uint32_t)(((uint32_t)(x)) << PMC_STATUSPWR_DCDCPWROK_SHIFT)) & PMC_STATUSPWR_DCDCPWROK_MASK)

#define PMC_STATUSPWR_LDOCOREPWROK_MASK          (0x10U)
#define PMC_STATUSPWR_LDOCOREPWROK_SHIFT         (4U)
/*! LDOCOREPWROK - CORE LDO power OK.
 */
#define PMC_STATUSPWR_LDOCOREPWROK(x)            (((uint32_t)(((uint32_t)(x)) << PMC_STATUSPWR_LDOCOREPWROK_SHIFT)) & PMC_STATUSPWR_LDOCOREPWROK_MASK)
/*! @} */

/*! @name STATUSCLK - Clock status */
/*! @{ */

#define PMC_STATUSCLK_XTAL32KOK_MASK             (0x1U)
#define PMC_STATUSCLK_XTAL32KOK_SHIFT            (0U)
/*! XTAL32KOK - XTAL oscillator 32 K OK signal.
 */
#define PMC_STATUSCLK_XTAL32KOK(x)               (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_XTAL32KOK_SHIFT)) & PMC_STATUSCLK_XTAL32KOK_MASK)

#define PMC_STATUSCLK_XTAL32KOSCFAILURE_MASK     (0x4U)
#define PMC_STATUSCLK_XTAL32KOSCFAILURE_SHIFT    (2U)
/*! XTAL32KOSCFAILURE - XTAL32 KHZ oscillator oscillation failure detection indicator.
 *  0b0..No oscillation failure has been detetced since the last time this bit has been cleared.
 *  0b1..At least one oscillation failure has been detetced since the last time this bit has been cleared.
 */
#define PMC_STATUSCLK_XTAL32KOSCFAILURE(x)       (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_XTAL32KOSCFAILURE_SHIFT)) & PMC_STATUSCLK_XTAL32KOSCFAILURE_MASK)
/*! @} */

/*! @name AOREG0 - Always-on 0 */
/*! @{ */

#define PMC_AOREG0_DATA_15_0_MASK                (0xFFFFU)
#define PMC_AOREG0_DATA_15_0_SHIFT               (0U)
/*! DATA_15_0 - General purpose always on domain data storage.
 */
#define PMC_AOREG0_DATA_15_0(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_AOREG0_DATA_15_0_SHIFT)) & PMC_AOREG0_DATA_15_0_MASK)
/*! @} */

/*! @name AOREG1 - Always-on 1 */
/*! @{ */

#define PMC_AOREG1_POR_MASK                      (0x10U)
#define PMC_AOREG1_POR_SHIFT                     (4U)
/*! POR - The last chip reset was caused by a Power On Reset.
 */
#define PMC_AOREG1_POR(x)                        (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_POR_SHIFT)) & PMC_AOREG1_POR_MASK)

#define PMC_AOREG1_PADRESET_MASK                 (0x20U)
#define PMC_AOREG1_PADRESET_SHIFT                (5U)
/*! PADRESET - The last chip reset was caused by a Pin Reset.
 */
#define PMC_AOREG1_PADRESET(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_PADRESET_SHIFT)) & PMC_AOREG1_PADRESET_MASK)

#define PMC_AOREG1_BODRESET_MASK                 (0x40U)
#define PMC_AOREG1_BODRESET_SHIFT                (6U)
/*! BODRESET - The last chip reset was caused by a Brown Out Detector (BoD), either BOD_VDDMAIN or BOD_CORE.
 */
#define PMC_AOREG1_BODRESET(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_BODRESET_SHIFT)) & PMC_AOREG1_BODRESET_MASK)

#define PMC_AOREG1_SYSTEMRESET_MASK              (0x80U)
#define PMC_AOREG1_SYSTEMRESET_SHIFT             (7U)
/*! SYSTEMRESET - The last chip reset was caused by a System Reset requested by the ARM CPU.
 */
#define PMC_AOREG1_SYSTEMRESET(x)                (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_SYSTEMRESET_SHIFT)) & PMC_AOREG1_SYSTEMRESET_MASK)

#define PMC_AOREG1_WDTRESET_MASK                 (0x100U)
#define PMC_AOREG1_WDTRESET_SHIFT                (8U)
/*! WDTRESET - The last chip reset was caused by the Watchdog Timer.
 */
#define PMC_AOREG1_WDTRESET(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_WDTRESET_SHIFT)) & PMC_AOREG1_WDTRESET_MASK)

#define PMC_AOREG1_SWRRESET_MASK                 (0x200U)
#define PMC_AOREG1_SWRRESET_SHIFT                (9U)
/*! SWRRESET - The last chip reset was caused by a Software event.
 */
#define PMC_AOREG1_SWRRESET(x)                   (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_SWRRESET_SHIFT)) & PMC_AOREG1_SWRRESET_MASK)

#define PMC_AOREG1_DPDRESET_WAKEUPIO_MASK        (0x400U)
#define PMC_AOREG1_DPDRESET_WAKEUPIO_SHIFT       (10U)
/*! DPDRESET_WAKEUPIO - A Wake-up I/O reset event occured during DEEP-POWER-DOWN mode.
 */
#define PMC_AOREG1_DPDRESET_WAKEUPIO(x)          (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_WAKEUPIO_SHIFT)) & PMC_AOREG1_DPDRESET_WAKEUPIO_MASK)

#define PMC_AOREG1_DPDRESET_RTC_MASK             (0x800U)
#define PMC_AOREG1_DPDRESET_RTC_SHIFT            (11U)
/*! DPDRESET_RTC - A RTC event occured during DEEP-POWER-DOWN mode.
 */
#define PMC_AOREG1_DPDRESET_RTC(x)               (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_RTC_SHIFT)) & PMC_AOREG1_DPDRESET_RTC_MASK)

#define PMC_AOREG1_DPDRESET_OSTIMER_MASK         (0x1000U)
#define PMC_AOREG1_DPDRESET_OSTIMER_SHIFT        (12U)
/*! DPDRESET_OSTIMER - An OS Timer event occured during a DEEP-POWER-DOWN mode.
 */
#define PMC_AOREG1_DPDRESET_OSTIMER(x)           (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_OSTIMER_SHIFT)) & PMC_AOREG1_DPDRESET_OSTIMER_MASK)

#define PMC_AOREG1_CDOGRESET_MASK                (0x2000U)
#define PMC_AOREG1_CDOGRESET_SHIFT               (13U)
/*! CDOGRESET - The last chip reset was caused by the code Watchdog.
 */
#define PMC_AOREG1_CDOGRESET(x)                  (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_CDOGRESET_SHIFT)) & PMC_AOREG1_CDOGRESET_MASK)

#define PMC_AOREG1_DPD_EVENTS_ORDER_MASK         (0x1C000U)
#define PMC_AOREG1_DPD_EVENTS_ORDER_SHIFT        (14U)
/*! DPD_EVENTS_ORDER - In DEEP-POWER-DOWN mode, indicates which reset event occured first, between a
 *    wake up I/O event (in DEEP-POWER-DOWN), a RTC event (in DEEP-POWER-DOWN) and a OS Timer event
 *    (in DEEP-POWER-DOWN). May be usefull when several reset events are enabled during
 *    DEEP-POWER-DOWN.
 *  0b000..No event
 *  0b001..WAKEUPIO
 *  0b010..RTC
 *  0b011..Both WAKEUPIO and RTC events occured at the same time (the 2 events occured within 1 nano-second of each other)
 *  0b100..OSTIMER
 *  0b101..Both WAKEUPIO and OSTIMER events occured at the same time (the 2 events occured within 1 nano-second of each other)
 *  0b110..Both RTC and OSTIMER events occured at the same time (the 2 events occured within 1 nano-second of each other)
 *  0b111..WAKEUPIO, RTC and OSTIMER events occured at the same time (the 3 events occured within 1 nano-second of each other)
 */
#define PMC_AOREG1_DPD_EVENTS_ORDER(x)           (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPD_EVENTS_ORDER_SHIFT)) & PMC_AOREG1_DPD_EVENTS_ORDER_MASK)

#define PMC_AOREG1_BOOTERRORCOUNTER_MASK         (0xF000000U)
#define PMC_AOREG1_BOOTERRORCOUNTER_SHIFT        (24U)
/*! BOOTERRORCOUNTER - ROM Boot Fatal Error Counter.
 */
#define PMC_AOREG1_BOOTERRORCOUNTER(x)           (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_BOOTERRORCOUNTER_SHIFT)) & PMC_AOREG1_BOOTERRORCOUNTER_MASK)
/*! @} */

/*! @name MISCCTRL - Miscellaneous Control Register for PMU [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */
/*! @{ */

#define PMC_MISCCTRL_VREF_ISO_MASK               (0x10000U)
#define PMC_MISCCTRL_VREF_ISO_SHIFT              (16U)
/*! VREF_ISO - VREF isolation control.
 *  0b0..VREF module isolation is disabled.
 *  0b1..VREF module isolation is enabled.
 */
#define PMC_MISCCTRL_VREF_ISO(x)                 (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_VREF_ISO_SHIFT)) & PMC_MISCCTRL_VREF_ISO_MASK)
/*! @} */

/*! @name RTCOSC32K - 32 KHz clocks source control */
/*! @{ */

#define PMC_RTCOSC32K_SEL_MASK                   (0x1U)
#define PMC_RTCOSC32K_SEL_SHIFT                  (0U)
/*! SEL - Select the 32K oscillator to be used in for the RTC, the OS Event Timer and the rest of
 *    the SoC (either XTAL32KHz or FRO32KHz) .
 *  0b0..FRO 32 KHz.
 *  0b1..XTAL 32KHz.
 */
#define PMC_RTCOSC32K_SEL(x)                     (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_SEL_SHIFT)) & PMC_RTCOSC32K_SEL_MASK)
/*! @} */

/*! @name OSEVENTTIMER - OS Event Timer control */
/*! @{ */

#define PMC_OSEVENTTIMER_SOFTRESET_MASK          (0x1U)
#define PMC_OSEVENTTIMER_SOFTRESET_SHIFT         (0U)
/*! SOFTRESET - Active high reset.
 */
#define PMC_OSEVENTTIMER_SOFTRESET(x)            (((uint32_t)(((uint32_t)(x)) << PMC_OSEVENTTIMER_SOFTRESET_SHIFT)) & PMC_OSEVENTTIMER_SOFTRESET_MASK)

#define PMC_OSEVENTTIMER_CLOCKENABLE_MASK        (0x2U)
#define PMC_OSEVENTTIMER_CLOCKENABLE_SHIFT       (1U)
/*! CLOCKENABLE - Enable OSTIMER 32 KHz clock.
 */
#define PMC_OSEVENTTIMER_CLOCKENABLE(x)          (((uint32_t)(((uint32_t)(x)) << PMC_OSEVENTTIMER_CLOCKENABLE_SHIFT)) & PMC_OSEVENTTIMER_CLOCKENABLE_MASK)

#define PMC_OSEVENTTIMER_DPDWAKEUPENABLE_MASK    (0x4U)
#define PMC_OSEVENTTIMER_DPDWAKEUPENABLE_SHIFT   (2U)
/*! DPDWAKEUPENABLE - Wake up enable in Deep Power Down mode (To be used in Enable Deep Power Down mode).
 */
#define PMC_OSEVENTTIMER_DPDWAKEUPENABLE(x)      (((uint32_t)(((uint32_t)(x)) << PMC_OSEVENTTIMER_DPDWAKEUPENABLE_SHIFT)) & PMC_OSEVENTTIMER_DPDWAKEUPENABLE_MASK)

#define PMC_OSEVENTTIMER_SELCLOCK_MASK           (0x18U)
#define PMC_OSEVENTTIMER_SELCLOCK_SHIFT          (3U)
/*! SELCLOCK - Select OS Event Timer Clock source
 *  0b00..32-KHz Free Running Oscillator (FRO)
 *  0b01..32-KHz Crystal Oscillator (XTAL)
 *  0b10..1-MHz FRO
 *  0b11..System Bus clock
 */
#define PMC_OSEVENTTIMER_SELCLOCK(x)             (((uint32_t)(((uint32_t)(x)) << PMC_OSEVENTTIMER_SELCLOCK_SHIFT)) & PMC_OSEVENTTIMER_SELCLOCK_MASK)
/*! @} */

/*! @name PDSLEEPCFG1 - Controls the power to various modules during Low Power modes - DEEP-SLEEP, POWER-DOWN and DEEP-POWER-DOWN [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset] */
/*! @{ */

#define PMC_PDSLEEPCFG1_PDEN_CMPBIAS_MASK        (0x1U)
#define PMC_PDSLEEPCFG1_PDEN_CMPBIAS_SHIFT       (0U)
/*! PDEN_CMPBIAS - Controls Comparators 1/2/3 Bias power during DEEP-SLEEP (always shut down during POWER-DOWN & DEEP-POWER-DOWN).
 *  0b0..Analog Bias is powered on during low power mode.
 *  0b1..Analog Bias is powered off during low power mode.
 */
#define PMC_PDSLEEPCFG1_PDEN_CMPBIAS(x)          (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG1_PDEN_CMPBIAS_SHIFT)) & PMC_PDSLEEPCFG1_PDEN_CMPBIAS_MASK)

#define PMC_PDSLEEPCFG1_PDEN_HSCMP0_DAC_MASK     (0x2U)
#define PMC_PDSLEEPCFG1_PDEN_HSCMP0_DAC_SHIFT    (1U)
/*! PDEN_HSCMP0_DAC - Controls High Speed Comparator0 DAC power during DEEP-SLEEP (always shut down during POWER-DOWN & DEEP-POWER-DOWN).
 *  0b0..High Speed Comparator0 DAC is powered on during low power mode.
 *  0b1..High Speed Comparator0 DAC is powered off during low power mode.
 */
#define PMC_PDSLEEPCFG1_PDEN_HSCMP0_DAC(x)       (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG1_PDEN_HSCMP0_DAC_SHIFT)) & PMC_PDSLEEPCFG1_PDEN_HSCMP0_DAC_MASK)

#define PMC_PDSLEEPCFG1_PDEN_HSCMP1_DAC_MASK     (0x4U)
#define PMC_PDSLEEPCFG1_PDEN_HSCMP1_DAC_SHIFT    (2U)
/*! PDEN_HSCMP1_DAC - Controls High Speed Comparator1 DAC power during DEEP-SLEEP (always shut down during POWER-DOWN & DEEP-POWER-DOWN).
 *  0b0..High Speed Comparator1 DAC is powered on during low power mode.
 *  0b1..High Speed Comparator1 DAC is powered off during low power mode.
 */
#define PMC_PDSLEEPCFG1_PDEN_HSCMP1_DAC(x)       (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG1_PDEN_HSCMP1_DAC_SHIFT)) & PMC_PDSLEEPCFG1_PDEN_HSCMP1_DAC_MASK)

#define PMC_PDSLEEPCFG1_PDEN_HSCMP2_DAC_MASK     (0x8U)
#define PMC_PDSLEEPCFG1_PDEN_HSCMP2_DAC_SHIFT    (3U)
/*! PDEN_HSCMP2_DAC - Controls High Speed Comparator2 DAC power during DEEP-SLEEP (always shut down during POWER-DOWN & DEEP-POWER-DOWN).
 *  0b0..High Speed Comparator2 DAC is powered on during low power mode.
 *  0b1..High Speed Comparator2 DAC is powered off during low power mode.
 */
#define PMC_PDSLEEPCFG1_PDEN_HSCMP2_DAC(x)       (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG1_PDEN_HSCMP2_DAC_SHIFT)) & PMC_PDSLEEPCFG1_PDEN_HSCMP2_DAC_MASK)

#define PMC_PDSLEEPCFG1_PDEN_DAC0_MASK           (0x10U)
#define PMC_PDSLEEPCFG1_PDEN_DAC0_SHIFT          (4U)
/*! PDEN_DAC0 - Controls DAC0 power during DEEP-SLEEP & POWER-DOWN (always shut down during DEEP-POWER-DOWN).
 *  0b0..DAC0 is powered on during low power mode.
 *  0b1..DAC0 is powered off during low power mode.
 */
#define PMC_PDSLEEPCFG1_PDEN_DAC0(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG1_PDEN_DAC0_SHIFT)) & PMC_PDSLEEPCFG1_PDEN_DAC0_MASK)

#define PMC_PDSLEEPCFG1_PDEN_DAC1_MASK           (0x20U)
#define PMC_PDSLEEPCFG1_PDEN_DAC1_SHIFT          (5U)
/*! PDEN_DAC1 - Controls DAC1 power during DEEP-SLEEP & POWER-DOWN (always shut down during DEEP-POWER-DOWN).
 *  0b0..DAC1 is powered on during low power mode.
 *  0b1..DAC1 is powered off during low power mode.
 */
#define PMC_PDSLEEPCFG1_PDEN_DAC1(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG1_PDEN_DAC1_SHIFT)) & PMC_PDSLEEPCFG1_PDEN_DAC1_MASK)

#define PMC_PDSLEEPCFG1_PDEN_DAC2_MASK           (0x40U)
#define PMC_PDSLEEPCFG1_PDEN_DAC2_SHIFT          (6U)
/*! PDEN_DAC2 - Controls DAC2 power during DEEP-SLEEP & POWER-DOWN (always shut down during DEEP-POWER-DOWN).
 *  0b0..DAC2 is powered on during low power mode.
 *  0b1..DAC2 is powered off during low power mode.
 */
#define PMC_PDSLEEPCFG1_PDEN_DAC2(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG1_PDEN_DAC2_SHIFT)) & PMC_PDSLEEPCFG1_PDEN_DAC2_MASK)

#define PMC_PDSLEEPCFG1_STOPEN_DAC0_MASK         (0x80U)
#define PMC_PDSLEEPCFG1_STOPEN_DAC0_SHIFT        (7U)
/*! STOPEN_DAC0 - Controls DAC0 Stop mode during DEEP-SLEEP & POWER-DOWN (DAC stop mode is always disabled in DEEP-POWER-DOWN).
 *  0b0..DAC Stop Mode is disabled.
 *  0b1..DAC Stop Mode is enabled.
 */
#define PMC_PDSLEEPCFG1_STOPEN_DAC0(x)           (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG1_STOPEN_DAC0_SHIFT)) & PMC_PDSLEEPCFG1_STOPEN_DAC0_MASK)

#define PMC_PDSLEEPCFG1_STOPEN_DAC1_MASK         (0x100U)
#define PMC_PDSLEEPCFG1_STOPEN_DAC1_SHIFT        (8U)
/*! STOPEN_DAC1 - Controls DAC1 Stop mode during DEEP-SLEEP & POWER-DOWN (DAC stop mode is always disabled in DEEP-POWER-DOWN).
 *  0b0..DAC Stop Mode is disabled.
 *  0b1..DAC Stop Mode is enabled.
 */
#define PMC_PDSLEEPCFG1_STOPEN_DAC1(x)           (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG1_STOPEN_DAC1_SHIFT)) & PMC_PDSLEEPCFG1_STOPEN_DAC1_MASK)

#define PMC_PDSLEEPCFG1_STOPEN_DAC2_MASK         (0x200U)
#define PMC_PDSLEEPCFG1_STOPEN_DAC2_SHIFT        (9U)
/*! STOPEN_DAC2 - Controls DAC2 Stop mode during DEEP-SLEEP & POWER-DOWN (DAC stop mode is always disabled in DEEP-POWER-DOWN).
 *  0b0..DAC Stop Mode is disabled.
 *  0b1..DAC Stop Mode is enabled.
 */
#define PMC_PDSLEEPCFG1_STOPEN_DAC2(x)           (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG1_STOPEN_DAC2_SHIFT)) & PMC_PDSLEEPCFG1_STOPEN_DAC2_MASK)
/*! @} */

/*! @name TIMEOUTEVENTS - Record time-out errors that might occur at different stages during IC power up */
/*! @{ */

#define PMC_TIMEOUTEVENTS_PWUP_DCDC_OK_MASK      (0x1U)
#define PMC_TIMEOUTEVENTS_PWUP_DCDC_OK_SHIFT     (0U)
/*! PWUP_DCDC_OK - 1: a time out event occured during power up when waiting for DCDC to become functional.
 */
#define PMC_TIMEOUTEVENTS_PWUP_DCDC_OK(x)        (((uint32_t)(((uint32_t)(x)) << PMC_TIMEOUTEVENTS_PWUP_DCDC_OK_SHIFT)) & PMC_TIMEOUTEVENTS_PWUP_DCDC_OK_MASK)

#define PMC_TIMEOUTEVENTS_PWUP_LDOFLASHNV_OK_MASK (0x2U)
#define PMC_TIMEOUTEVENTS_PWUP_LDOFLASHNV_OK_SHIFT (1U)
/*! PWUP_LDOFLASHNV_OK - 1: a time out event occured during power up when waiting for LDO Flash NV to become functional.
 */
#define PMC_TIMEOUTEVENTS_PWUP_LDOFLASHNV_OK(x)  (((uint32_t)(((uint32_t)(x)) << PMC_TIMEOUTEVENTS_PWUP_LDOFLASHNV_OK_SHIFT)) & PMC_TIMEOUTEVENTS_PWUP_LDOFLASHNV_OK_MASK)

#define PMC_TIMEOUTEVENTS_PWUP_SRAM_WAKEUP_MASK  (0x4U)
#define PMC_TIMEOUTEVENTS_PWUP_SRAM_WAKEUP_SHIFT (2U)
/*! PWUP_SRAM_WAKEUP - 1: a time out event occured during power up when waiting for SRAM to become functional.
 */
#define PMC_TIMEOUTEVENTS_PWUP_SRAM_WAKEUP(x)    (((uint32_t)(((uint32_t)(x)) << PMC_TIMEOUTEVENTS_PWUP_SRAM_WAKEUP_SHIFT)) & PMC_TIMEOUTEVENTS_PWUP_SRAM_WAKEUP_MASK)

#define PMC_TIMEOUTEVENTS_PWUP_FLASHINIT_DONE_MASK (0x8U)
#define PMC_TIMEOUTEVENTS_PWUP_FLASHINIT_DONE_SHIFT (3U)
/*! PWUP_FLASHINIT_DONE - 1: a time out event occured during power up when waiting for Flash initialization.
 */
#define PMC_TIMEOUTEVENTS_PWUP_FLASHINIT_DONE(x) (((uint32_t)(((uint32_t)(x)) << PMC_TIMEOUTEVENTS_PWUP_FLASHINIT_DONE_SHIFT)) & PMC_TIMEOUTEVENTS_PWUP_FLASHINIT_DONE_MASK)

#define PMC_TIMEOUTEVENTS_DSLP_LDOFLASH_SRAM_OFF_MASK (0x10U)
#define PMC_TIMEOUTEVENTS_DSLP_LDOFLASH_SRAM_OFF_SHIFT (4U)
/*! DSLP_LDOFLASH_SRAM_OFF - 1: a time out event occured during deep sleep when waiting for LDO Flash NV or SRAM shut off.
 */
#define PMC_TIMEOUTEVENTS_DSLP_LDOFLASH_SRAM_OFF(x) (((uint32_t)(((uint32_t)(x)) << PMC_TIMEOUTEVENTS_DSLP_LDOFLASH_SRAM_OFF_SHIFT)) & PMC_TIMEOUTEVENTS_DSLP_LDOFLASH_SRAM_OFF_MASK)

#define PMC_TIMEOUTEVENTS_DSLP_DCDC_OK_MASK      (0x20U)
#define PMC_TIMEOUTEVENTS_DSLP_DCDC_OK_SHIFT     (5U)
/*! DSLP_DCDC_OK - 1: a time out event occured during deep sleep when waiting for DCDC to become functional.
 */
#define PMC_TIMEOUTEVENTS_DSLP_DCDC_OK(x)        (((uint32_t)(((uint32_t)(x)) << PMC_TIMEOUTEVENTS_DSLP_DCDC_OK_SHIFT)) & PMC_TIMEOUTEVENTS_DSLP_DCDC_OK_MASK)

#define PMC_TIMEOUTEVENTS_DSLP_LDOFLASHNV_OK_MASK (0x40U)
#define PMC_TIMEOUTEVENTS_DSLP_LDOFLASHNV_OK_SHIFT (6U)
/*! DSLP_LDOFLASHNV_OK - 1: a time out event occured during deep sleep when waiting for LDO Flash NV to become functional.
 */
#define PMC_TIMEOUTEVENTS_DSLP_LDOFLASHNV_OK(x)  (((uint32_t)(((uint32_t)(x)) << PMC_TIMEOUTEVENTS_DSLP_LDOFLASHNV_OK_SHIFT)) & PMC_TIMEOUTEVENTS_DSLP_LDOFLASHNV_OK_MASK)

#define PMC_TIMEOUTEVENTS_DSLP_SRAM_WAKEUP_MASK  (0x80U)
#define PMC_TIMEOUTEVENTS_DSLP_SRAM_WAKEUP_SHIFT (7U)
/*! DSLP_SRAM_WAKEUP - 1: a time out event occured during deep sleep when waiting for SRAM to become functional.
 */
#define PMC_TIMEOUTEVENTS_DSLP_SRAM_WAKEUP(x)    (((uint32_t)(((uint32_t)(x)) << PMC_TIMEOUTEVENTS_DSLP_SRAM_WAKEUP_SHIFT)) & PMC_TIMEOUTEVENTS_DSLP_SRAM_WAKEUP_MASK)

#define PMC_TIMEOUTEVENTS_PDWN_LDOFLASH_SRAM_OFF_MASK (0x100U)
#define PMC_TIMEOUTEVENTS_PDWN_LDOFLASH_SRAM_OFF_SHIFT (8U)
/*! PDWN_LDOFLASH_SRAM_OFF - 1: a time out event occured during power down when waiting for for LDO Flash NV or SRAM shut off.
 */
#define PMC_TIMEOUTEVENTS_PDWN_LDOFLASH_SRAM_OFF(x) (((uint32_t)(((uint32_t)(x)) << PMC_TIMEOUTEVENTS_PDWN_LDOFLASH_SRAM_OFF_SHIFT)) & PMC_TIMEOUTEVENTS_PDWN_LDOFLASH_SRAM_OFF_MASK)

#define PMC_TIMEOUTEVENTS_PDWN_DCDC_BODVDDMAIN_OK_MASK (0x200U)
#define PMC_TIMEOUTEVENTS_PDWN_DCDC_BODVDDMAIN_OK_SHIFT (9U)
/*! PDWN_DCDC_BODVDDMAIN_OK - 1: a time out event occured during power down when waiting for DCDC or BOD_VDDMAIN to become functional.
 */
#define PMC_TIMEOUTEVENTS_PDWN_DCDC_BODVDDMAIN_OK(x) (((uint32_t)(((uint32_t)(x)) << PMC_TIMEOUTEVENTS_PDWN_DCDC_BODVDDMAIN_OK_SHIFT)) & PMC_TIMEOUTEVENTS_PDWN_DCDC_BODVDDMAIN_OK_MASK)

#define PMC_TIMEOUTEVENTS_PDWN_LDOFLASHNV_OK_MASK (0x400U)
#define PMC_TIMEOUTEVENTS_PDWN_LDOFLASHNV_OK_SHIFT (10U)
/*! PDWN_LDOFLASHNV_OK - 1: a time out event occured during power down when waiting for LDO Flash NV to become functional.
 */
#define PMC_TIMEOUTEVENTS_PDWN_LDOFLASHNV_OK(x)  (((uint32_t)(((uint32_t)(x)) << PMC_TIMEOUTEVENTS_PDWN_LDOFLASHNV_OK_SHIFT)) & PMC_TIMEOUTEVENTS_PDWN_LDOFLASHNV_OK_MASK)

#define PMC_TIMEOUTEVENTS_PDWN_SRAM_WAKEUP_MASK  (0x800U)
#define PMC_TIMEOUTEVENTS_PDWN_SRAM_WAKEUP_SHIFT (11U)
/*! PDWN_SRAM_WAKEUP - 1: a time out event occured during power down when waiting for SRAM to become functional.
 */
#define PMC_TIMEOUTEVENTS_PDWN_SRAM_WAKEUP(x)    (((uint32_t)(((uint32_t)(x)) << PMC_TIMEOUTEVENTS_PDWN_SRAM_WAKEUP_SHIFT)) & PMC_TIMEOUTEVENTS_PDWN_SRAM_WAKEUP_MASK)

#define PMC_TIMEOUTEVENTS_PDWN_FLASHINIT_DONE_MASK (0x1000U)
#define PMC_TIMEOUTEVENTS_PDWN_FLASHINIT_DONE_SHIFT (12U)
/*! PDWN_FLASHINIT_DONE - 1: a time out event occured during power down when waiting for Flash initialization.
 */
#define PMC_TIMEOUTEVENTS_PDWN_FLASHINIT_DONE(x) (((uint32_t)(((uint32_t)(x)) << PMC_TIMEOUTEVENTS_PDWN_FLASHINIT_DONE_SHIFT)) & PMC_TIMEOUTEVENTS_PDWN_FLASHINIT_DONE_MASK)
/*! @} */

/*! @name PDSLEEPCFG0 - Controls the power to various modules during Low Power modes - DEEP-SLEEP, POWER-DOWN and DEEP-POWER-DOWN [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset] */
/*! @{ */

#define PMC_PDSLEEPCFG0_PDEN_BIAS_MASK           (0x2U)
#define PMC_PDSLEEPCFG0_PDEN_BIAS_SHIFT          (1U)
/*! PDEN_BIAS - Controls Analog Bias power during DEEP-SLEEP and POWER-DOWN (always shut down during DEEP-POWER-DOWN).
 *  0b0..Analog Bias is powered on during low power mode.
 *  0b1..Analog Bias is powered off during low power mode.
 */
#define PMC_PDSLEEPCFG0_PDEN_BIAS(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_BIAS_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_BIAS_MASK)

#define PMC_PDSLEEPCFG0_PDEN_BODCORE_MASK        (0x4U)
#define PMC_PDSLEEPCFG0_PDEN_BODCORE_SHIFT       (2U)
/*! PDEN_BODCORE - Controls Core Logic BoD power during DEEP-SLEEP and POWER-DOWN (always shut down during DEEP-POWER-DOWN).
 *  0b0..BOD_CORE is powered on during low power mode.
 *  0b1..BOD_CORE is powered off during low power mode.
 */
#define PMC_PDSLEEPCFG0_PDEN_BODCORE(x)          (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_BODCORE_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_BODCORE_MASK)

#define PMC_PDSLEEPCFG0_PDEN_BODVDDMAIN_MASK     (0x8U)
#define PMC_PDSLEEPCFG0_PDEN_BODVDDMAIN_SHIFT    (3U)
/*! PDEN_BODVDDMAIN - Controls BOD_VDDMAIN power during DEEP-SLEEP and POWER-DOWN (always shut down during DEEP-POWER-DOWN).
 *  0b0..BOD_VDDMAIN is powered on during low power mode.
 *  0b1..BOD_VDDMAIN is powered off during low power mode.
 */
#define PMC_PDSLEEPCFG0_PDEN_BODVDDMAIN(x)       (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_BODVDDMAIN_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_BODVDDMAIN_MASK)

#define PMC_PDSLEEPCFG0_PDEN_FRO1M_MASK          (0x10U)
#define PMC_PDSLEEPCFG0_PDEN_FRO1M_SHIFT         (4U)
/*! PDEN_FRO1M - Controls 1 MHz Free Running Oscillator power during DEEP-SLEEP, POWER-DOWN and DEEP-POWER-DOWN.
 *  0b0..FRO 1MHz is powered on during low power mode.
 *  0b1..FRO 1MHz is powered off during low power mode.
 */
#define PMC_PDSLEEPCFG0_PDEN_FRO1M(x)            (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_FRO1M_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_FRO1M_MASK)

#define PMC_PDSLEEPCFG0_PDEN_FRO192M_MASK        (0x20U)
#define PMC_PDSLEEPCFG0_PDEN_FRO192M_SHIFT       (5U)
/*! PDEN_FRO192M - Controls 192MHz Free Running Oscillator power during DEEP-SLEEP (always shut down
 *    during POWER-DOWN and DEEP-POWER-DOWN).
 *  0b0..FRO 192 MHz is powered on during low power mode.
 *  0b1..FRO 192 MHz is powered off during low power mode.
 */
#define PMC_PDSLEEPCFG0_PDEN_FRO192M(x)          (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_FRO192M_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_FRO192M_MASK)

#define PMC_PDSLEEPCFG0_PDEN_FRO32K_MASK         (0x40U)
#define PMC_PDSLEEPCFG0_PDEN_FRO32K_SHIFT        (6U)
/*! PDEN_FRO32K - Controls power during DEEP-SLEEP, POWER-DOWN and DEEP-POWER-DOWN.
 *  0b0..FRO 32 KHz is powered on during low power mode.
 *  0b1..FRO 32 KHz is powered off during low power mode.
 */
#define PMC_PDSLEEPCFG0_PDEN_FRO32K(x)           (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_FRO32K_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_FRO32K_MASK)

#define PMC_PDSLEEPCFG0_PDEN_XTAL32K_MASK        (0x80U)
#define PMC_PDSLEEPCFG0_PDEN_XTAL32K_SHIFT       (7U)
/*! PDEN_XTAL32K - Controls crystal 32 KHz power during DEEP-SLEEP, POWER-DOWN and DEEP-POWER-DOWN.
 *  0b0..crystal 32 KHz is powered on during low power mode.
 *  0b1..crystal 32 KHz is powered off during low power mode.
 */
#define PMC_PDSLEEPCFG0_PDEN_XTAL32K(x)          (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_XTAL32K_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_XTAL32K_MASK)

#define PMC_PDSLEEPCFG0_PDEN_XTALHF_MASK         (0x100U)
#define PMC_PDSLEEPCFG0_PDEN_XTALHF_SHIFT        (8U)
/*! PDEN_XTALHF - Controls high speed crystal power during DEEP-SLEEP (always shut down during POWER-DOWN and DEEP-POWER-DOWN).
 *  0b0..High speed crystal is powered on during low power mode.
 *  0b1..High speed crystal is powered off during low power mode.
 */
#define PMC_PDSLEEPCFG0_PDEN_XTALHF(x)           (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_XTALHF_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_XTALHF_MASK)

#define PMC_PDSLEEPCFG0_PDEN_PLL0_MASK           (0x200U)
#define PMC_PDSLEEPCFG0_PDEN_PLL0_SHIFT          (9U)
/*! PDEN_PLL0 - Controls System PLL (also refered as PLL0) power during DEEP-SLEEP (always shut down
 *    during POWER-DOWN and DEEP-POWER-DOWN).
 *  0b0..System PLL (also refered as PLL0) is powered on during low power mode.
 *  0b1..System PLL (also refered as PLL0) is powered off during low power mode.
 */
#define PMC_PDSLEEPCFG0_PDEN_PLL0(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_PLL0_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_PLL0_MASK)

#define PMC_PDSLEEPCFG0_PDEN_PLL1_MASK           (0x400U)
#define PMC_PDSLEEPCFG0_PDEN_PLL1_SHIFT          (10U)
/*! PDEN_PLL1 - Controls USB PLL (also refered as PLL1) power during DEEP-SLEEP (always shut down
 *    during POWER-DOWN and DEEP-POWER-DOWN).
 *  0b0..USB PLL (also refered as PLL1) is powered on during low power mode.
 *  0b1..USB PLL (also refered as PLL1) is powered off during low power mode.
 */
#define PMC_PDSLEEPCFG0_PDEN_PLL1(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_PLL1_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_PLL1_MASK)

#define PMC_PDSLEEPCFG0_PDEN_USBFSPHY_MASK       (0x800U)
#define PMC_PDSLEEPCFG0_PDEN_USBFSPHY_SHIFT      (11U)
/*! PDEN_USBFSPHY - Controls USB Full Speed phy power during DEEP-SLEEP (always shut down during POWER-DOWN and DEEP-POWER-DOWN).
 *  0b0..USB Full Speed phy is powered on during low power mode.
 *  0b1..USB Full Speed phy is powered off during low power mode.
 */
#define PMC_PDSLEEPCFG0_PDEN_USBFSPHY(x)         (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_USBFSPHY_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_USBFSPHY_MASK)

#define PMC_PDSLEEPCFG0_PDEN_COMP_MASK           (0x2000U)
#define PMC_PDSLEEPCFG0_PDEN_COMP_SHIFT          (13U)
/*! PDEN_COMP - Controls Analog Comparator power during DEEP-SLEEP and POWER-DOWN (always shut down during DEEP-POWER-DOWN).
 *  0b0..Analog Comparator is powered on during low power mode.
 *  0b1..Analog Comparator is powered off during low power mode.
 */
#define PMC_PDSLEEPCFG0_PDEN_COMP(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_COMP_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_COMP_MASK)

#define PMC_PDSLEEPCFG0_PDEN_LDOMEM_MASK         (0x10000U)
#define PMC_PDSLEEPCFG0_PDEN_LDOMEM_SHIFT        (16U)
/*! PDEN_LDOMEM - Controls Memories LDO power during DEEP-SLEEP, POWER-DOWN and DEEP-POWER-DOWN.
 *  0b0..Memories LDO is powered on during low power mode.
 *  0b1..Memories LDO is powered off during low power mode.
 */
#define PMC_PDSLEEPCFG0_PDEN_LDOMEM(x)           (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_LDOMEM_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_LDOMEM_MASK)

#define PMC_PDSLEEPCFG0_PDEN_LDOEFUSEPROG_MASK   (0x40000U)
#define PMC_PDSLEEPCFG0_PDEN_LDOEFUSEPROG_SHIFT  (18U)
/*! PDEN_LDOEFUSEPROG - Controls USB high speed LDO power during DEEP-SLEEP (always shut down during POWER-DOWN and DEEP-POWER-DOWN).
 *  0b0..USB high speed LDO is powered on during low power mode.
 *  0b1..USB high speed LDO is powered off during low power mode.
 */
#define PMC_PDSLEEPCFG0_PDEN_LDOEFUSEPROG(x)     (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_LDOEFUSEPROG_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_LDOEFUSEPROG_MASK)

#define PMC_PDSLEEPCFG0_PDEN_LDOXTALHF_MASK      (0x100000U)
#define PMC_PDSLEEPCFG0_PDEN_LDOXTALHF_SHIFT     (20U)
/*! PDEN_LDOXTALHF - Controls High speed crystal LDO power during DEEP-SLEEP (always shut down during POWER-DOWN and DEEP-POWER-DOWN).
 *  0b0..High speed crystal LDO is powered on during low power mode.
 *  0b1..High speed crystal LDO is powered off during low power mode.
 */
#define PMC_PDSLEEPCFG0_PDEN_LDOXTALHF(x)        (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_LDOXTALHF_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_LDOXTALHF_MASK)

#define PMC_PDSLEEPCFG0_PDEN_LDOFLASHNV_MASK     (0x200000U)
#define PMC_PDSLEEPCFG0_PDEN_LDOFLASHNV_SHIFT    (21U)
/*! PDEN_LDOFLASHNV - Controls Flash NV (high voltage) LDO power during DEEP-SLEEP (always shut down during POWER-DOWN and DEEP-POWER-DOWN).
 *  0b0..Flash NV (high voltage) is powered on during low power mode.
 *  0b1..Flash NV (high voltage) is powered off during low power mode.
 */
#define PMC_PDSLEEPCFG0_PDEN_LDOFLASHNV(x)       (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_LDOFLASHNV_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_LDOFLASHNV_MASK)

#define PMC_PDSLEEPCFG0_PDEN_PLL0_SSCG_MASK      (0x800000U)
#define PMC_PDSLEEPCFG0_PDEN_PLL0_SSCG_SHIFT     (23U)
/*! PDEN_PLL0_SSCG - Controls PLL0 Spread Sprectrum module power during DEEP-SLEEP (PLL0 Spread
 *    Spectrum is always shut down during POWER-DOWN and DEEP-POWER-DOWN).
 *  0b0..PLL0 Spread Sprectrum module is powered on during low power mode.
 *  0b1..PLL0 Spread Sprectrum module is powered off during low power mode.
 */
#define PMC_PDSLEEPCFG0_PDEN_PLL0_SSCG(x)        (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_PLL0_SSCG_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_PLL0_SSCG_MASK)

#define PMC_PDSLEEPCFG0_PDEN_ROM_MASK            (0x1000000U)
#define PMC_PDSLEEPCFG0_PDEN_ROM_SHIFT           (24U)
/*! PDEN_ROM - Controls ROM power during DEEP-SLEEP (ROM is always shut down during POWER-DOWN and DEEP-POWER-DOWN).
 *  0b0..ROM is powered on during low power mode.
 *  0b1..ROM is powered off during low power mode.
 */
#define PMC_PDSLEEPCFG0_PDEN_ROM(x)              (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_ROM_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_ROM_MASK)

#define PMC_PDSLEEPCFG0_PDEN_HSCMP0_MASK         (0x2000000U)
#define PMC_PDSLEEPCFG0_PDEN_HSCMP0_SHIFT        (25U)
/*! PDEN_HSCMP0 - Controls High Speed Comparator0 power during DEEP-SLEEP (always shut down during POWER-DOWN and DEEP-POWER-DOWN).
 *  0b0..High Speed Comparator is powered on during low power mode.
 *  0b1..High Speed Comparator is powered off during low power mode.
 */
#define PMC_PDSLEEPCFG0_PDEN_HSCMP0(x)           (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_HSCMP0_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_HSCMP0_MASK)

#define PMC_PDSLEEPCFG0_PDEN_HSCMP1_MASK         (0x4000000U)
#define PMC_PDSLEEPCFG0_PDEN_HSCMP1_SHIFT        (26U)
/*! PDEN_HSCMP1 - Controls High Speed Comparator1 power during DEEP-SLEEP (always shut down during POWER-DOWN and DEEP-POWER-DOWN).
 *  0b0..High Speed Comparator is powered on during low power mode.
 *  0b1..High Speed Comparator is powered off during low power mode.
 */
#define PMC_PDSLEEPCFG0_PDEN_HSCMP1(x)           (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_HSCMP1_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_HSCMP1_MASK)

#define PMC_PDSLEEPCFG0_PDEN_HSCMP2_MASK         (0x8000000U)
#define PMC_PDSLEEPCFG0_PDEN_HSCMP2_SHIFT        (27U)
/*! PDEN_HSCMP2 - Controls High Speed Comparator2 power during DEEP-SLEEP (always shut down during POWER-DOWN and DEEP-POWER-DOWN).
 *  0b0..High Speed Comparator is powered on during low power mode.
 *  0b1..High Speed Comparator is powered off during low power mode.
 */
#define PMC_PDSLEEPCFG0_PDEN_HSCMP2(x)           (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_HSCMP2_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_HSCMP2_MASK)

#define PMC_PDSLEEPCFG0_PDEN_OPAMP0_MASK         (0x10000000U)
#define PMC_PDSLEEPCFG0_PDEN_OPAMP0_SHIFT        (28U)
/*! PDEN_OPAMP0 - Controls Operational Amplifier0 power during DEEP-SLEEP (always shut down during POWER-DOWN and DEEP-POWER-DOWN).
 *  0b0..Operational Amplifier is powered on during low power mode.
 *  0b1..Operational Amplifier is powered off during low power mode.
 */
#define PMC_PDSLEEPCFG0_PDEN_OPAMP0(x)           (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_OPAMP0_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_OPAMP0_MASK)

#define PMC_PDSLEEPCFG0_PDEN_OPAMP1_MASK         (0x20000000U)
#define PMC_PDSLEEPCFG0_PDEN_OPAMP1_SHIFT        (29U)
/*! PDEN_OPAMP1 - Controls Operational Amplifier1 power during DEEP-SLEEP (always shut down during POWER-DOWN and DEEP-POWER-DOWN).
 *  0b0..Operational Amplifier is powered on during low power mode.
 *  0b1..Operational Amplifier is powered off during low power mode.
 */
#define PMC_PDSLEEPCFG0_PDEN_OPAMP1(x)           (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_OPAMP1_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_OPAMP1_MASK)

#define PMC_PDSLEEPCFG0_PDEN_OPAMP2_MASK         (0x40000000U)
#define PMC_PDSLEEPCFG0_PDEN_OPAMP2_SHIFT        (30U)
/*! PDEN_OPAMP2 - Controls Operational Amplifier2 power during DEEP-SLEEP (always shut down during POWER-DOWN and DEEP-POWER-DOWN).
 *  0b0..Operational Amplifier is powered on during low power mode.
 *  0b1..Operational Amplifier is powered off during low power mode.
 */
#define PMC_PDSLEEPCFG0_PDEN_OPAMP2(x)           (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_OPAMP2_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_OPAMP2_MASK)

#define PMC_PDSLEEPCFG0_PDEN_VREF_MASK           (0x80000000U)
#define PMC_PDSLEEPCFG0_PDEN_VREF_SHIFT          (31U)
/*! PDEN_VREF - Controls VREF power during DEEP-SLEEP (always shut down during POWER-DOWN and DEEP-POWER-DOWN).
 *  0b0..VREF is powered on during low power mode.
 *  0b1..VREF is powered off during low power mode.
 */
#define PMC_PDSLEEPCFG0_PDEN_VREF(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_VREF_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_VREF_MASK)
/*! @} */

/*! @name SRAMRETCTRL - Controls all SRAM instances power down modes during Low Power modes [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset] */
/*! @{ */

#define PMC_SRAMRETCTRL_RETEN_RAM_X0_MASK        (0x1U)
#define PMC_SRAMRETCTRL_RETEN_RAM_X0_SHIFT       (0U)
/*! RETEN_RAM_X0 - Controls RAM_X0 power down modes during low power modes.
 *  0b0..DEEP-SLEEP: the SRAM instance keeps the configuration it has before entering DEEP-SLEEP, what evere it is
 *       (Normal, Light Sleep, Deep-Sleep mode and Shut down modes) POWER-DOWN and DEEP-POWER-DOWN: the SRAM
 *       instance is in 'Shutdown mode' (In this mode there is no data retention).
 *  0b1..The SRAM is in 'Deep Sleep' mode (In this mode there is data retention).
 */
#define PMC_SRAMRETCTRL_RETEN_RAM_X0(x)          (((uint32_t)(((uint32_t)(x)) << PMC_SRAMRETCTRL_RETEN_RAM_X0_SHIFT)) & PMC_SRAMRETCTRL_RETEN_RAM_X0_MASK)

#define PMC_SRAMRETCTRL_RETEN_RAM_00_MASK        (0x2U)
#define PMC_SRAMRETCTRL_RETEN_RAM_00_SHIFT       (1U)
/*! RETEN_RAM_00 - Controls RAM_00 power down modes during low power modes.
 *  0b0..DEEP-SLEEP: the SRAM instance keeps the configuration it has before entering DEEP-SLEEP, what evere it is
 *       (Normal, Light Sleep, Deep-Sleep mode and Shut down modes) POWER-DOWN and DEEP-POWER-DOWN: the SRAM
 *       instance is in 'Shutdown mode' (In this mode there is no data retention).
 *  0b1..The SRAM is in 'Deep Sleep' mode (In this mode there is data retention).
 */
#define PMC_SRAMRETCTRL_RETEN_RAM_00(x)          (((uint32_t)(((uint32_t)(x)) << PMC_SRAMRETCTRL_RETEN_RAM_00_SHIFT)) & PMC_SRAMRETCTRL_RETEN_RAM_00_MASK)

#define PMC_SRAMRETCTRL_RETEN_RAM_01_MASK        (0x4U)
#define PMC_SRAMRETCTRL_RETEN_RAM_01_SHIFT       (2U)
/*! RETEN_RAM_01 - Controls RAM_01 power down modes during low power modes.
 *  0b0..DEEP-SLEEP: the SRAM instance keeps the configuration it has before entering DEEP-SLEEP, what evere it is
 *       (Normal, Light Sleep, Deep-Sleep mode and Shut down modes) POWER-DOWN and DEEP-POWER-DOWN: the SRAM
 *       instance is in 'Shutdown mode' (In this mode there is no data retention).
 *  0b1..The SRAM is in 'Deep Sleep' mode (In this mode there is data retention).
 */
#define PMC_SRAMRETCTRL_RETEN_RAM_01(x)          (((uint32_t)(((uint32_t)(x)) << PMC_SRAMRETCTRL_RETEN_RAM_01_SHIFT)) & PMC_SRAMRETCTRL_RETEN_RAM_01_MASK)

#define PMC_SRAMRETCTRL_RETEN_RAM_02_MASK        (0x8U)
#define PMC_SRAMRETCTRL_RETEN_RAM_02_SHIFT       (3U)
/*! RETEN_RAM_02 - Controls RAM_02 power down modes during low power modes.
 *  0b0..DEEP-SLEEP: the SRAM instance keeps the configuration it has before entering DEEP-SLEEP, what evere it is
 *       (Normal, Light Sleep, Deep-Sleep mode and Shut down modes) POWER-DOWN and DEEP-POWER-DOWN: the SRAM
 *       instance is in 'Shutdown mode' (In this mode there is no data retention).
 *  0b1..The SRAM is in 'Deep Sleep' mode (In this mode there is data retention).
 */
#define PMC_SRAMRETCTRL_RETEN_RAM_02(x)          (((uint32_t)(((uint32_t)(x)) << PMC_SRAMRETCTRL_RETEN_RAM_02_SHIFT)) & PMC_SRAMRETCTRL_RETEN_RAM_02_MASK)

#define PMC_SRAMRETCTRL_RETEN_RAM_03_MASK        (0x10U)
#define PMC_SRAMRETCTRL_RETEN_RAM_03_SHIFT       (4U)
/*! RETEN_RAM_03 - Controls RAM_03 power down modes during low power modes.
 *  0b0..DEEP-SLEEP: the SRAM instance keeps the configuration it has before entering DEEP-SLEEP, what evere it is
 *       (Normal, Light Sleep, Deep-Sleep mode and Shut down modes) POWER-DOWN and DEEP-POWER-DOWN: the SRAM
 *       instance is in 'Shutdown mode' (In this mode there is no data retention).
 *  0b1..The SRAM is in 'Deep Sleep' mode (In this mode there is data retention).
 */
#define PMC_SRAMRETCTRL_RETEN_RAM_03(x)          (((uint32_t)(((uint32_t)(x)) << PMC_SRAMRETCTRL_RETEN_RAM_03_SHIFT)) & PMC_SRAMRETCTRL_RETEN_RAM_03_MASK)

#define PMC_SRAMRETCTRL_RETEN_RAM_10_MASK        (0x20U)
#define PMC_SRAMRETCTRL_RETEN_RAM_10_SHIFT       (5U)
/*! RETEN_RAM_10 - Controls RAM_10 power down modes during low power modes.
 *  0b0..DEEP-SLEEP: the SRAM instance keeps the configuration it has before entering DEEP-SLEEP, whatever it is
 *       (Normal, Light Sleep, Deep-Sleep mode and Shut down modes) POWER-DOWN and DEEP-POWER-DOWN: the SRAM
 *       instance is in 'Shutdown mode' (In this mode there is no data retention).
 *  0b1..The SRAM is in 'Deep Sleep' mode (In this mode there is data retention).
 */
#define PMC_SRAMRETCTRL_RETEN_RAM_10(x)          (((uint32_t)(((uint32_t)(x)) << PMC_SRAMRETCTRL_RETEN_RAM_10_SHIFT)) & PMC_SRAMRETCTRL_RETEN_RAM_10_MASK)

#define PMC_SRAMRETCTRL_RETEN_RAM_20_MASK        (0x40U)
#define PMC_SRAMRETCTRL_RETEN_RAM_20_SHIFT       (6U)
/*! RETEN_RAM_20 - Controls RAM_20 power down modes during low power modes.
 *  0b0..DEEP-SLEEP: the SRAM instance keeps the configuration it has before entering DEEP-SLEEP, whatever it is
 *       (Normal, Light Sleep, Deep-Sleep mode and Shut down modes) POWER-DOWN and DEEP-POWER-DOWN: the SRAM
 *       instance is in 'Shutdown mode' (In this mode there is no data retention).
 *  0b1..The SRAM is in 'Deep Sleep' mode (In this mode there is data retention).
 */
#define PMC_SRAMRETCTRL_RETEN_RAM_20(x)          (((uint32_t)(((uint32_t)(x)) << PMC_SRAMRETCTRL_RETEN_RAM_20_SHIFT)) & PMC_SRAMRETCTRL_RETEN_RAM_20_MASK)

#define PMC_SRAMRETCTRL_RETEN_RAM_30_MASK        (0x80U)
#define PMC_SRAMRETCTRL_RETEN_RAM_30_SHIFT       (7U)
/*! RETEN_RAM_30 - Controls RAM_30 power down modes during low power modes.
 *  0b0..DEEP-SLEEP: the SRAM instance keeps the configuration it has before entering DEEP-SLEEP, whatever it is
 *       (Normal, Light Sleep, Deep-Sleep mode and Shut down modes) POWER-DOWN and DEEP-POWER-DOWN: the SRAM
 *       instance is in 'Shutdown mode' (In this mode there is no data retention).
 *  0b1..The SRAM is in 'Deep Sleep' mode (In this mode there is data retention).
 */
#define PMC_SRAMRETCTRL_RETEN_RAM_30(x)          (((uint32_t)(((uint32_t)(x)) << PMC_SRAMRETCTRL_RETEN_RAM_30_SHIFT)) & PMC_SRAMRETCTRL_RETEN_RAM_30_MASK)

#define PMC_SRAMRETCTRL_RETEN_RAM_40_MASK        (0x100U)
#define PMC_SRAMRETCTRL_RETEN_RAM_40_SHIFT       (8U)
/*! RETEN_RAM_40 - Controls RAM_40 power down modes during low power modes.
 *  0b0..DEEP-SLEEP: the SRAM instance keeps the configuration it has before entering DEEP-SLEEP, what evere it is
 *       (Normal, Light Sleep, Deep-Sleep mode and Shut down modes) POWER-DOWN and DEEP-POWER-DOWN: the SRAM
 *       instance is in 'Shutdown mode' (In this mode there is no data retention).
 *  0b1..The SRAM is in 'Deep Sleep' mode (In this mode there is data retention).
 */
#define PMC_SRAMRETCTRL_RETEN_RAM_40(x)          (((uint32_t)(((uint32_t)(x)) << PMC_SRAMRETCTRL_RETEN_RAM_40_SHIFT)) & PMC_SRAMRETCTRL_RETEN_RAM_40_MASK)

#define PMC_SRAMRETCTRL_RETEN_RAM_41_MASK        (0x200U)
#define PMC_SRAMRETCTRL_RETEN_RAM_41_SHIFT       (9U)
/*! RETEN_RAM_41 - Controls RAM_41 power down modes during low power modes.
 *  0b0..DEEP-SLEEP: the SRAM instance keeps the configuration it has before entering DEEP-SLEEP, what evere it is
 *       (Normal, Light Sleep, Deep-Sleep mode and Shut down modes) POWER-DOWN and DEEP-POWER-DOWN: the SRAM
 *       instance is in 'Shutdown mode' (In this mode there is no data retention).
 *  0b1..The SRAM is in 'Deep Sleep' mode (In this mode there is data retention).
 */
#define PMC_SRAMRETCTRL_RETEN_RAM_41(x)          (((uint32_t)(((uint32_t)(x)) << PMC_SRAMRETCTRL_RETEN_RAM_41_SHIFT)) & PMC_SRAMRETCTRL_RETEN_RAM_41_MASK)

#define PMC_SRAMRETCTRL_RETEN_RAM_42_MASK        (0x400U)
#define PMC_SRAMRETCTRL_RETEN_RAM_42_SHIFT       (10U)
/*! RETEN_RAM_42 - Controls RAM_42 power down modes during low power modes.
 *  0b0..DEEP-SLEEP: the SRAM instance keeps the configuration it has before entering DEEP-SLEEP, what evere it is
 *       (Normal, Light Sleep, Deep-Sleep mode and Shut down modes) POWER-DOWN and DEEP-POWER-DOWN: the SRAM
 *       instance is in 'Shutdown mode' (In this mode there is no data retention).
 *  0b1..The SRAM is in 'Deep Sleep' mode (In this mode there is data retention).
 */
#define PMC_SRAMRETCTRL_RETEN_RAM_42(x)          (((uint32_t)(((uint32_t)(x)) << PMC_SRAMRETCTRL_RETEN_RAM_42_SHIFT)) & PMC_SRAMRETCTRL_RETEN_RAM_42_MASK)

#define PMC_SRAMRETCTRL_RETEN_RAM_43_MASK        (0x800U)
#define PMC_SRAMRETCTRL_RETEN_RAM_43_SHIFT       (11U)
/*! RETEN_RAM_43 - Controls RAM_43 power down modes during low power modes.
 *  0b0..DEEP-SLEEP: the SRAM instance keeps the configuration it has before entering DEEP-SLEEP, what evere it is
 *       (Normal, Light Sleep, Deep-Sleep mode and Shut down modes) POWER-DOWN and DEEP-POWER-DOWN: the SRAM
 *       instance is in 'Shutdown mode' (In this mode there is no data retention).
 *  0b1..The SRAM is in 'Deep Sleep' mode (In this mode there is data retention).
 */
#define PMC_SRAMRETCTRL_RETEN_RAM_43(x)          (((uint32_t)(((uint32_t)(x)) << PMC_SRAMRETCTRL_RETEN_RAM_43_SHIFT)) & PMC_SRAMRETCTRL_RETEN_RAM_43_MASK)

#define PMC_SRAMRETCTRL_RETEN_RAM_FLASHLPCACHE_MASK (0x1000U)
#define PMC_SRAMRETCTRL_RETEN_RAM_FLASHLPCACHE_SHIFT (12U)
/*! RETEN_RAM_FLASHLPCACHE - Controls Embedded Flash Cache SRAM power down modes during low power modes.
 */
#define PMC_SRAMRETCTRL_RETEN_RAM_FLASHLPCACHE(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMRETCTRL_RETEN_RAM_FLASHLPCACHE_SHIFT)) & PMC_SRAMRETCTRL_RETEN_RAM_FLASHLPCACHE_MASK)

#define PMC_SRAMRETCTRL_RETEN_RAM_FLEXSPILPCACHE_MASK (0x2000U)
#define PMC_SRAMRETCTRL_RETEN_RAM_FLEXSPILPCACHE_SHIFT (13U)
/*! RETEN_RAM_FLEXSPILPCACHE - Controls FlexSPI Cache SRAM power down modes during low power modes.
 */
#define PMC_SRAMRETCTRL_RETEN_RAM_FLEXSPILPCACHE(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMRETCTRL_RETEN_RAM_FLEXSPILPCACHE_SHIFT)) & PMC_SRAMRETCTRL_RETEN_RAM_FLEXSPILPCACHE_MASK)

#define PMC_SRAMRETCTRL_RETEN_H2PREG_FLEXSPI_MASK (0x4000U)
#define PMC_SRAMRETCTRL_RETEN_H2PREG_FLEXSPI_SHIFT (14U)
/*! RETEN_H2PREG_FLEXSPI - Controls FlexSPI Dual Port Register Files power down modes during deep
 *    sleep. In power-down and deep power-down modes, FlexSPI Dual Port Register Files are always
 *    shutoff.
 *  0b0..DEEP-SLEEP: all FlexSPI dual port register files keep the configuration they had before entering
 *       DEEP-SLEEP. POWER-DOWN and DEEP-POWER-DOWN: all FlexSPI dual port register instances are shut off (In this mode
 *       there is no data retention).
 *  0b1..DEEP-SLEEP: all FlexSPI Dual Port egister files are in 'Power Down' mode (In this mode there is data
 *       retention). POWER-DOWN and DEEP-POWER-DOWN: all FlexSPI dual port register instances are shut off (In this
 *       mode there is no data retention).
 */
#define PMC_SRAMRETCTRL_RETEN_H2PREG_FLEXSPI(x)  (((uint32_t)(((uint32_t)(x)) << PMC_SRAMRETCTRL_RETEN_H2PREG_FLEXSPI_SHIFT)) & PMC_SRAMRETCTRL_RETEN_H2PREG_FLEXSPI_MASK)
/*! @} */

/*! @name PDRUNCFG0 - Power configuration 0 */
/*! @{ */

#define PMC_PDRUNCFG0_PDEN_DCDC_MASK             (0x1U)
#define PMC_PDRUNCFG0_PDEN_DCDC_SHIFT            (0U)
/*! PDEN_DCDC - Controls power to Bulk DCDC Converter.
 *  0b0..DCDC is powered.
 *  0b1..DCDC is powered down.
 */
#define PMC_PDRUNCFG0_PDEN_DCDC(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_DCDC_SHIFT)) & PMC_PDRUNCFG0_PDEN_DCDC_MASK)

#define PMC_PDRUNCFG0_PDEN_BIAS_MASK             (0x2U)
#define PMC_PDRUNCFG0_PDEN_BIAS_SHIFT            (1U)
/*! PDEN_BIAS - Controls power to .
 *  0b0..Analog Bias is powered.
 *  0b1..Analog Bias is powered down.
 */
#define PMC_PDRUNCFG0_PDEN_BIAS(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_BIAS_SHIFT)) & PMC_PDRUNCFG0_PDEN_BIAS_MASK)

#define PMC_PDRUNCFG0_PDEN_BODCORE_MASK          (0x4U)
#define PMC_PDRUNCFG0_PDEN_BODCORE_SHIFT         (2U)
/*! PDEN_BODCORE - Controls power to Core Brown Out Detector (BOD_CORE).
 *  0b0..BOD_CORE is powered.
 *  0b1..BOD_CORE is powered down.
 */
#define PMC_PDRUNCFG0_PDEN_BODCORE(x)            (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_BODCORE_SHIFT)) & PMC_PDRUNCFG0_PDEN_BODCORE_MASK)

#define PMC_PDRUNCFG0_PDEN_BODVDDMAIN_MASK       (0x8U)
#define PMC_PDRUNCFG0_PDEN_BODVDDMAIN_SHIFT      (3U)
/*! PDEN_BODVDDMAIN - Controls power to VDDMAIN Brown Out Detector (BOD_VDDMAIN).
 *  0b0..BOD_VDDMAIN is powered.
 *  0b1..BOD_VDDMAIN is powered down.
 */
#define PMC_PDRUNCFG0_PDEN_BODVDDMAIN(x)         (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_BODVDDMAIN_SHIFT)) & PMC_PDRUNCFG0_PDEN_BODVDDMAIN_MASK)

#define PMC_PDRUNCFG0_PDEN_FRO192M_MASK          (0x20U)
#define PMC_PDRUNCFG0_PDEN_FRO192M_SHIFT         (5U)
/*! PDEN_FRO192M - Controls power to the Free Running Oscillator (FRO) 192 MHz; The 12MHz, 48 MHz
 *    and 96 MHz clocks are derived from this FRO.
 *  0b0..FRO 192MHz is powered.
 *  0b1..FRO 192MHz is powered down.
 */
#define PMC_PDRUNCFG0_PDEN_FRO192M(x)            (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_FRO192M_SHIFT)) & PMC_PDRUNCFG0_PDEN_FRO192M_MASK)

#define PMC_PDRUNCFG0_PDEN_FRO32K_MASK           (0x40U)
#define PMC_PDRUNCFG0_PDEN_FRO32K_SHIFT          (6U)
/*! PDEN_FRO32K - Controls power to the Free Running Oscillator (FRO) 32 KHz.
 *  0b0..FRO32KHz is powered.
 *  0b1..FRO32KHz is powered down.
 */
#define PMC_PDRUNCFG0_PDEN_FRO32K(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_FRO32K_SHIFT)) & PMC_PDRUNCFG0_PDEN_FRO32K_MASK)

#define PMC_PDRUNCFG0_PDEN_XTAL32K_MASK          (0x80U)
#define PMC_PDRUNCFG0_PDEN_XTAL32K_SHIFT         (7U)
/*! PDEN_XTAL32K - Controls power to crystal 32 KHz.
 *  0b0..Crystal 32KHz is powered.
 *  0b1..Crystal 32KHz is powered down.
 */
#define PMC_PDRUNCFG0_PDEN_XTAL32K(x)            (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_XTAL32K_SHIFT)) & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK)

#define PMC_PDRUNCFG0_PDEN_XTALHF_MASK           (0x100U)
#define PMC_PDRUNCFG0_PDEN_XTALHF_SHIFT          (8U)
/*! PDEN_XTALHF - Controls power to high speed crystal.
 *  0b0..High speed crystal is powered.
 *  0b1..High speed crystal is powered down.
 */
#define PMC_PDRUNCFG0_PDEN_XTALHF(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_XTALHF_SHIFT)) & PMC_PDRUNCFG0_PDEN_XTALHF_MASK)

#define PMC_PDRUNCFG0_PDEN_PLL0_MASK             (0x200U)
#define PMC_PDRUNCFG0_PDEN_PLL0_SHIFT            (9U)
/*! PDEN_PLL0 - Controls power to System PLL (also refered as PLL0).
 *  0b0..PLL0 is powered.
 *  0b1..PLL0 is powered down.
 */
#define PMC_PDRUNCFG0_PDEN_PLL0(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL0_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL0_MASK)

#define PMC_PDRUNCFG0_PDEN_PLL1_MASK             (0x400U)
#define PMC_PDRUNCFG0_PDEN_PLL1_SHIFT            (10U)
/*! PDEN_PLL1 - Controls power to USB PLL (also refered as PLL1).
 *  0b0..PLL1 is powered.
 *  0b1..PLL1 is powered down.
 */
#define PMC_PDRUNCFG0_PDEN_PLL1(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL1_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL1_MASK)

#define PMC_PDRUNCFG0_PDEN_USBFSPHY_MASK         (0x800U)
#define PMC_PDRUNCFG0_PDEN_USBFSPHY_SHIFT        (11U)
/*! PDEN_USBFSPHY - Controls power to USB Full Speed phy.
 *  0b0..USB Full Speed phy is powered.
 *  0b1..USB Full Speed phy is powered down.
 */
#define PMC_PDRUNCFG0_PDEN_USBFSPHY(x)           (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_USBFSPHY_SHIFT)) & PMC_PDRUNCFG0_PDEN_USBFSPHY_MASK)

#define PMC_PDRUNCFG0_PDEN_COMP_MASK             (0x2000U)
#define PMC_PDRUNCFG0_PDEN_COMP_SHIFT            (13U)
/*! PDEN_COMP - Controls power to Analog Comparator.
 *  0b0..Analog Comparator is powered.
 *  0b1..Analog Comparator is powered down.
 */
#define PMC_PDRUNCFG0_PDEN_COMP(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_COMP_SHIFT)) & PMC_PDRUNCFG0_PDEN_COMP_MASK)

#define PMC_PDRUNCFG0_PDEN_LDOMEM_MASK           (0x10000U)
#define PMC_PDRUNCFG0_PDEN_LDOMEM_SHIFT          (16U)
/*! PDEN_LDOMEM - Controls power to Memories LDO.
 *  0b0..Memories LDO is powered.
 *  0b1..Memories LDO is powered down.
 */
#define PMC_PDRUNCFG0_PDEN_LDOMEM(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOMEM_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOMEM_MASK)

#define PMC_PDRUNCFG0_PDEN_LDOEFUSEPROG_MASK     (0x40000U)
#define PMC_PDRUNCFG0_PDEN_LDOEFUSEPROG_SHIFT    (18U)
/*! PDEN_LDOEFUSEPROG - Controls power to eFUSE Programming LDO.
 *  0b0..USB high speed LDO is powered.
 *  0b1..USB high speed LDO is powered down.
 */
#define PMC_PDRUNCFG0_PDEN_LDOEFUSEPROG(x)       (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOEFUSEPROG_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOEFUSEPROG_MASK)

#define PMC_PDRUNCFG0_PDEN_LDOXTALHF_MASK        (0x100000U)
#define PMC_PDRUNCFG0_PDEN_LDOXTALHF_SHIFT       (20U)
/*! PDEN_LDOXTALHF - Controls power to high speed crystal LDO.
 *  0b0..High speed crystal LDO is powered.
 *  0b1..High speed crystal LDO is powered down.
 */
#define PMC_PDRUNCFG0_PDEN_LDOXTALHF(x)          (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOXTALHF_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOXTALHF_MASK)

#define PMC_PDRUNCFG0_PDEN_LDOFLASHNV_MASK       (0x200000U)
#define PMC_PDRUNCFG0_PDEN_LDOFLASHNV_SHIFT      (21U)
/*! PDEN_LDOFLASHNV - Controls power to Flasn NV (high voltage) LDO.
 *  0b0..Flash NV LDO is powered.
 *  0b1..Flash NV LDO is powered down.
 */
#define PMC_PDRUNCFG0_PDEN_LDOFLASHNV(x)         (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOFLASHNV_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOFLASHNV_MASK)

#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK        (0x800000U)
#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG_SHIFT       (23U)
/*! PDEN_PLL0_SSCG - Controls power to System PLL (PLL0) Spread Spectrum module.
 *  0b0..PLL0 Sread spectrum module is powered.
 *  0b1..PLL0 Sread spectrum module is powered down.
 */
#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG(x)          (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL0_SSCG_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK)

#define PMC_PDRUNCFG0_PDEN_HSCMP0_MASK           (0x2000000U)
#define PMC_PDRUNCFG0_PDEN_HSCMP0_SHIFT          (25U)
/*! PDEN_HSCMP0 - Controls power to High Speed Comparator0
 *  0b0..High Speed Comparator0 is powered on.
 *  0b1..High Speed Comparator0 is powered down.
 */
#define PMC_PDRUNCFG0_PDEN_HSCMP0(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_HSCMP0_SHIFT)) & PMC_PDRUNCFG0_PDEN_HSCMP0_MASK)

#define PMC_PDRUNCFG0_PDEN_HSCMP1_MASK           (0x4000000U)
#define PMC_PDRUNCFG0_PDEN_HSCMP1_SHIFT          (26U)
/*! PDEN_HSCMP1 - Controls power to High Speed Comparator1
 *  0b0..High Speed Comparator1 is powered on
 *  0b1..High Speed Comparator1 is powered down
 */
#define PMC_PDRUNCFG0_PDEN_HSCMP1(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_HSCMP1_SHIFT)) & PMC_PDRUNCFG0_PDEN_HSCMP1_MASK)

#define PMC_PDRUNCFG0_PDEN_HSCMP2_MASK           (0x8000000U)
#define PMC_PDRUNCFG0_PDEN_HSCMP2_SHIFT          (27U)
/*! PDEN_HSCMP2 - Controls power to High Speed Comparator2
 *  0b0..High Speed Comparator2 is powered on
 *  0b1..High Speed Comparator2 is powered down
 */
#define PMC_PDRUNCFG0_PDEN_HSCMP2(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_HSCMP2_SHIFT)) & PMC_PDRUNCFG0_PDEN_HSCMP2_MASK)

#define PMC_PDRUNCFG0_PDEN_OPAMP0_MASK           (0x10000000U)
#define PMC_PDRUNCFG0_PDEN_OPAMP0_SHIFT          (28U)
/*! PDEN_OPAMP0 - Controls power to Operational Amplifier0
 *  0b0..Operational Amplifier0 is powered on.
 *  0b1..Operational Amplifier0 is powered down.
 */
#define PMC_PDRUNCFG0_PDEN_OPAMP0(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_OPAMP0_SHIFT)) & PMC_PDRUNCFG0_PDEN_OPAMP0_MASK)

#define PMC_PDRUNCFG0_PDEN_OPAMP1_MASK           (0x20000000U)
#define PMC_PDRUNCFG0_PDEN_OPAMP1_SHIFT          (29U)
/*! PDEN_OPAMP1 - Controls power to Operational Amplifier1
 *  0b0..Operational Amplifier1 is powered on
 *  0b1..Operational Amplifier1 is powered down
 */
#define PMC_PDRUNCFG0_PDEN_OPAMP1(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_OPAMP1_SHIFT)) & PMC_PDRUNCFG0_PDEN_OPAMP1_MASK)

#define PMC_PDRUNCFG0_PDEN_OPAMP2_MASK           (0x40000000U)
#define PMC_PDRUNCFG0_PDEN_OPAMP2_SHIFT          (30U)
/*! PDEN_OPAMP2 - Controls power to Operational Amplifier2
 *  0b0..Operational Amplifier2 is powered on
 *  0b1..Operational Amplifier2 is powered down
 */
#define PMC_PDRUNCFG0_PDEN_OPAMP2(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_OPAMP2_SHIFT)) & PMC_PDRUNCFG0_PDEN_OPAMP2_MASK)

#define PMC_PDRUNCFG0_PDEN_VREF_MASK             (0x80000000U)
#define PMC_PDRUNCFG0_PDEN_VREF_SHIFT            (31U)
/*! PDEN_VREF - Controls power to VREF module
 *  0b0..VREF is powered on.
 *  0b1..VREF is powered down.
 */
#define PMC_PDRUNCFG0_PDEN_VREF(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_VREF_SHIFT)) & PMC_PDRUNCFG0_PDEN_VREF_MASK)
/*! @} */

/*! @name PDRUNCFG1 - Power configuration 1 */
/*! @{ */

#define PMC_PDRUNCFG1_PDEN_CMPBIAS_MASK          (0x1U)
#define PMC_PDRUNCFG1_PDEN_CMPBIAS_SHIFT         (0U)
/*! PDEN_CMPBIAS - Controls power of Comparators 1/2/3 bias.
 *  0b0..Comparators 1/2/3 bias is powered.
 *  0b1..Comparators 1/2/3 bias is powered down.
 */
#define PMC_PDRUNCFG1_PDEN_CMPBIAS(x)            (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG1_PDEN_CMPBIAS_SHIFT)) & PMC_PDRUNCFG1_PDEN_CMPBIAS_MASK)

#define PMC_PDRUNCFG1_PDEN_HSCMP0_DAC_MASK       (0x2U)
#define PMC_PDRUNCFG1_PDEN_HSCMP0_DAC_SHIFT      (1U)
/*! PDEN_HSCMP0_DAC - Controls power to High Speed Comparator0 DAC.
 *  0b0..High Speed Comparator0 DAC is powered.
 *  0b1..High Speed Comparator0 DAC is powered down.
 */
#define PMC_PDRUNCFG1_PDEN_HSCMP0_DAC(x)         (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG1_PDEN_HSCMP0_DAC_SHIFT)) & PMC_PDRUNCFG1_PDEN_HSCMP0_DAC_MASK)

#define PMC_PDRUNCFG1_PDEN_HSCMP1_DAC_MASK       (0x4U)
#define PMC_PDRUNCFG1_PDEN_HSCMP1_DAC_SHIFT      (2U)
/*! PDEN_HSCMP1_DAC - Controls power to High Speed Comparator1 DAC.
 *  0b0..High Speed Comparator1 DAC is powered.
 *  0b1..High Speed Comparator1 DAC is powered down.
 */
#define PMC_PDRUNCFG1_PDEN_HSCMP1_DAC(x)         (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG1_PDEN_HSCMP1_DAC_SHIFT)) & PMC_PDRUNCFG1_PDEN_HSCMP1_DAC_MASK)

#define PMC_PDRUNCFG1_PDEN_HSCMP2_DAC_MASK       (0x8U)
#define PMC_PDRUNCFG1_PDEN_HSCMP2_DAC_SHIFT      (3U)
/*! PDEN_HSCMP2_DAC - Controls power to High Speed Comparator2 DAC.
 *  0b0..High Speed Comparator2 DAC is powered.
 *  0b1..High Speed Comparator2 DAC is powered down.
 */
#define PMC_PDRUNCFG1_PDEN_HSCMP2_DAC(x)         (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG1_PDEN_HSCMP2_DAC_SHIFT)) & PMC_PDRUNCFG1_PDEN_HSCMP2_DAC_MASK)

#define PMC_PDRUNCFG1_PDEN_DAC0_MASK             (0x10U)
#define PMC_PDRUNCFG1_PDEN_DAC0_SHIFT            (4U)
/*! PDEN_DAC0 - Controls power to DAC0.
 *  0b0..DAC0 is powered.
 *  0b1..DAC0 is powered down.
 */
#define PMC_PDRUNCFG1_PDEN_DAC0(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG1_PDEN_DAC0_SHIFT)) & PMC_PDRUNCFG1_PDEN_DAC0_MASK)

#define PMC_PDRUNCFG1_PDEN_DAC1_MASK             (0x20U)
#define PMC_PDRUNCFG1_PDEN_DAC1_SHIFT            (5U)
/*! PDEN_DAC1 - Controls power to DAC1.
 *  0b0..DAC1 is powered.
 *  0b1..DAC1 is powered down.
 */
#define PMC_PDRUNCFG1_PDEN_DAC1(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG1_PDEN_DAC1_SHIFT)) & PMC_PDRUNCFG1_PDEN_DAC1_MASK)

#define PMC_PDRUNCFG1_PDEN_DAC2_MASK             (0x40U)
#define PMC_PDRUNCFG1_PDEN_DAC2_SHIFT            (6U)
/*! PDEN_DAC2 - Controls power to DAC2.
 *  0b0..DAC2 is powered.
 *  0b1..DAC2 is powered down.
 */
#define PMC_PDRUNCFG1_PDEN_DAC2(x)               (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG1_PDEN_DAC2_SHIFT)) & PMC_PDRUNCFG1_PDEN_DAC2_MASK)

#define PMC_PDRUNCFG1_STOPEN_DAC0_MASK           (0x80U)
#define PMC_PDRUNCFG1_STOPEN_DAC0_SHIFT          (7U)
/*! STOPEN_DAC0 - Controls DAC0 Stop mode.
 *  0b0..DAC0 Stop mode is disabled.
 *  0b1..DAC0 Stop mode is enabled.
 */
#define PMC_PDRUNCFG1_STOPEN_DAC0(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG1_STOPEN_DAC0_SHIFT)) & PMC_PDRUNCFG1_STOPEN_DAC0_MASK)

#define PMC_PDRUNCFG1_STOPEN_DAC1_MASK           (0x100U)
#define PMC_PDRUNCFG1_STOPEN_DAC1_SHIFT          (8U)
/*! STOPEN_DAC1 - Controls DAC1 Stop mode.
 *  0b0..DAC1 Stop mode is disabled.
 *  0b1..DAC1 Stop mode is enabled.
 */
#define PMC_PDRUNCFG1_STOPEN_DAC1(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG1_STOPEN_DAC1_SHIFT)) & PMC_PDRUNCFG1_STOPEN_DAC1_MASK)

#define PMC_PDRUNCFG1_STOPEN_DAC2_MASK           (0x200U)
#define PMC_PDRUNCFG1_STOPEN_DAC2_SHIFT          (9U)
/*! STOPEN_DAC2 - Controls DAC2 Stop mode.
 *  0b0..DAC2 Stop mode is disabled.
 *  0b1..DAC2 Stop mode is enabled.
 */
#define PMC_PDRUNCFG1_STOPEN_DAC2(x)             (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG1_STOPEN_DAC2_SHIFT)) & PMC_PDRUNCFG1_STOPEN_DAC2_MASK)
/*! @} */

/*! @name PDRUNCFGSET0 - Power configuration set 0 */
/*! @{ */

#define PMC_PDRUNCFGSET0_PDRUNCFGSET0_MASK       (0xFFFFFFFFU)
#define PMC_PDRUNCFGSET0_PDRUNCFGSET0_SHIFT      (0U)
/*! PDRUNCFGSET0 - Writing ones to this register sets the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented.
 */
#define PMC_PDRUNCFGSET0_PDRUNCFGSET0(x)         (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGSET0_PDRUNCFGSET0_SHIFT)) & PMC_PDRUNCFGSET0_PDRUNCFGSET0_MASK)
/*! @} */

/*! @name PDRUNCFGSET1 - Power configuration set 1 */
/*! @{ */

#define PMC_PDRUNCFGSET1_PDRUNCFGSET1_MASK       (0x3FFU)
#define PMC_PDRUNCFGSET1_PDRUNCFGSET1_SHIFT      (0U)
/*! PDRUNCFGSET1 - Writing ones to this register sets the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented.
 */
#define PMC_PDRUNCFGSET1_PDRUNCFGSET1(x)         (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGSET1_PDRUNCFGSET1_SHIFT)) & PMC_PDRUNCFGSET1_PDRUNCFGSET1_MASK)
/*! @} */

/*! @name PDRUNCFGCLR0 - Power configuration clear 0 */
/*! @{ */

#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_MASK       (0xFFFFFFFFU)
#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_SHIFT      (0U)
/*! PDRUNCFGCLR0 - Writing ones to this register clears the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented.
 */
#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0(x)         (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_SHIFT)) & PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_MASK)
/*! @} */

/*! @name PDRUNCFGCLR1 - Power configuration clear 1 */
/*! @{ */

#define PMC_PDRUNCFGCLR1_PDRUNCFGCLR1_MASK       (0x3FFU)
#define PMC_PDRUNCFGCLR1_PDRUNCFGCLR1_SHIFT      (0U)
/*! PDRUNCFGCLR1 - Writing ones to this register clears the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented.
 */
#define PMC_PDRUNCFGCLR1_PDRUNCFGCLR1(x)         (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGCLR1_PDRUNCFGCLR1_SHIFT)) & PMC_PDRUNCFGCLR1_PDRUNCFGCLR1_MASK)
/*! @} */

/*! @name SRAMCTRL - All SRAMs common control signals [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset] */
/*! @{ */

#define PMC_SRAMCTRL_SMB_MASK                    (0x3U)
#define PMC_SRAMCTRL_SMB_SHIFT                   (0U)
/*! SMB - Source Biasing voltage.
 *  0b00..Low leakage.
 *  0b01..Medium leakage.
 *  0b10..Highest leakage.
 *  0b11..Disable.
 */
#define PMC_SRAMCTRL_SMB(x)                      (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL_SMB_SHIFT)) & PMC_SRAMCTRL_SMB_MASK)
/*! @} */

/*! @name SRAMCTRL0 - RAM_X0, and RAM_00 to RAM_30 power modes controls [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] When [LS, LSDEL, DSB, DSBDEL] is: 0011 : Normal Mode 1111 : Light sleep mode 0100 : Deep-sleep mode 1100 : Shut down Mode */
/*! @{ */

#define PMC_SRAMCTRL0_RAM_X0_LS_MASK             (0x1U)
#define PMC_SRAMCTRL0_RAM_X0_LS_SHIFT            (0U)
/*! RAM_X0_LS - RAM_X0 Light Sleep mode.
 */
#define PMC_SRAMCTRL0_RAM_X0_LS(x)               (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_X0_LS_SHIFT)) & PMC_SRAMCTRL0_RAM_X0_LS_MASK)

#define PMC_SRAMCTRL0_RAM_X0_DSB_MASK            (0x2U)
#define PMC_SRAMCTRL0_RAM_X0_DSB_SHIFT           (1U)
/*! RAM_X0_DSB - RAM_X0 Deep sleep mode.
 */
#define PMC_SRAMCTRL0_RAM_X0_DSB(x)              (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_X0_DSB_SHIFT)) & PMC_SRAMCTRL0_RAM_X0_DSB_MASK)

#define PMC_SRAMCTRL0_RAM_X0_DSBDEL_MASK         (0x4U)
#define PMC_SRAMCTRL0_RAM_X0_DSBDEL_SHIFT        (2U)
/*! RAM_X0_DSBDEL - RAM_X0 Deep sleep delayed.
 */
#define PMC_SRAMCTRL0_RAM_X0_DSBDEL(x)           (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_X0_DSBDEL_SHIFT)) & PMC_SRAMCTRL0_RAM_X0_DSBDEL_MASK)

#define PMC_SRAMCTRL0_RAM_X0_LSDEL_MASK          (0x8U)
#define PMC_SRAMCTRL0_RAM_X0_LSDEL_SHIFT         (3U)
/*! RAM_X0_LSDEL - RAM_X0 Sleep mode disable.
 */
#define PMC_SRAMCTRL0_RAM_X0_LSDEL(x)            (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_X0_LSDEL_SHIFT)) & PMC_SRAMCTRL0_RAM_X0_LSDEL_MASK)

#define PMC_SRAMCTRL0_RAM_00_LS_MASK             (0x10U)
#define PMC_SRAMCTRL0_RAM_00_LS_SHIFT            (4U)
/*! RAM_00_LS - RAM_00 Light Sleep mode.
 */
#define PMC_SRAMCTRL0_RAM_00_LS(x)               (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_00_LS_SHIFT)) & PMC_SRAMCTRL0_RAM_00_LS_MASK)

#define PMC_SRAMCTRL0_RAM_00_DSB_MASK            (0x20U)
#define PMC_SRAMCTRL0_RAM_00_DSB_SHIFT           (5U)
/*! RAM_00_DSB - RAM_00 Deep sleep mode.
 */
#define PMC_SRAMCTRL0_RAM_00_DSB(x)              (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_00_DSB_SHIFT)) & PMC_SRAMCTRL0_RAM_00_DSB_MASK)

#define PMC_SRAMCTRL0_RAM_00_DSBDEL_MASK         (0x40U)
#define PMC_SRAMCTRL0_RAM_00_DSBDEL_SHIFT        (6U)
/*! RAM_00_DSBDEL - RAM_00 Deep sleep delayed.
 */
#define PMC_SRAMCTRL0_RAM_00_DSBDEL(x)           (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_00_DSBDEL_SHIFT)) & PMC_SRAMCTRL0_RAM_00_DSBDEL_MASK)

#define PMC_SRAMCTRL0_RAM_00_LSDEL_MASK          (0x80U)
#define PMC_SRAMCTRL0_RAM_00_LSDEL_SHIFT         (7U)
/*! RAM_00_LSDEL - RAM_00 Sleep mode disable.
 */
#define PMC_SRAMCTRL0_RAM_00_LSDEL(x)            (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_00_LSDEL_SHIFT)) & PMC_SRAMCTRL0_RAM_00_LSDEL_MASK)

#define PMC_SRAMCTRL0_RAM_01_LS_MASK             (0x100U)
#define PMC_SRAMCTRL0_RAM_01_LS_SHIFT            (8U)
/*! RAM_01_LS - RAM_01 Light Sleep mode.
 */
#define PMC_SRAMCTRL0_RAM_01_LS(x)               (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_01_LS_SHIFT)) & PMC_SRAMCTRL0_RAM_01_LS_MASK)

#define PMC_SRAMCTRL0_RAM_01_DSB_MASK            (0x200U)
#define PMC_SRAMCTRL0_RAM_01_DSB_SHIFT           (9U)
/*! RAM_01_DSB - RAM_01 Deep sleep mode.
 */
#define PMC_SRAMCTRL0_RAM_01_DSB(x)              (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_01_DSB_SHIFT)) & PMC_SRAMCTRL0_RAM_01_DSB_MASK)

#define PMC_SRAMCTRL0_RAM_01_DSBDEL_MASK         (0x400U)
#define PMC_SRAMCTRL0_RAM_01_DSBDEL_SHIFT        (10U)
/*! RAM_01_DSBDEL - RAM_01 Deep sleep delayed.
 */
#define PMC_SRAMCTRL0_RAM_01_DSBDEL(x)           (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_01_DSBDEL_SHIFT)) & PMC_SRAMCTRL0_RAM_01_DSBDEL_MASK)

#define PMC_SRAMCTRL0_RAM_01_LSDEL_MASK          (0x800U)
#define PMC_SRAMCTRL0_RAM_01_LSDEL_SHIFT         (11U)
/*! RAM_01_LSDEL - RAM_01 Sleep mode disable.
 */
#define PMC_SRAMCTRL0_RAM_01_LSDEL(x)            (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_01_LSDEL_SHIFT)) & PMC_SRAMCTRL0_RAM_01_LSDEL_MASK)

#define PMC_SRAMCTRL0_RAM_02_LS_MASK             (0x1000U)
#define PMC_SRAMCTRL0_RAM_02_LS_SHIFT            (12U)
/*! RAM_02_LS - RAM_02 Light Sleep mode.
 */
#define PMC_SRAMCTRL0_RAM_02_LS(x)               (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_02_LS_SHIFT)) & PMC_SRAMCTRL0_RAM_02_LS_MASK)

#define PMC_SRAMCTRL0_RAM_02_DSB_MASK            (0x2000U)
#define PMC_SRAMCTRL0_RAM_02_DSB_SHIFT           (13U)
/*! RAM_02_DSB - RAM_02 Deep sleep mode.
 */
#define PMC_SRAMCTRL0_RAM_02_DSB(x)              (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_02_DSB_SHIFT)) & PMC_SRAMCTRL0_RAM_02_DSB_MASK)

#define PMC_SRAMCTRL0_RAM_02_DSBDEL_MASK         (0x4000U)
#define PMC_SRAMCTRL0_RAM_02_DSBDEL_SHIFT        (14U)
/*! RAM_02_DSBDEL - RAM_02 Deep sleep delayed.
 */
#define PMC_SRAMCTRL0_RAM_02_DSBDEL(x)           (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_02_DSBDEL_SHIFT)) & PMC_SRAMCTRL0_RAM_02_DSBDEL_MASK)

#define PMC_SRAMCTRL0_RAM_02_LSDEL_MASK          (0x8000U)
#define PMC_SRAMCTRL0_RAM_02_LSDEL_SHIFT         (15U)
/*! RAM_02_LSDEL - RAM_02 Sleep mode disable.
 */
#define PMC_SRAMCTRL0_RAM_02_LSDEL(x)            (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_02_LSDEL_SHIFT)) & PMC_SRAMCTRL0_RAM_02_LSDEL_MASK)

#define PMC_SRAMCTRL0_RAM_03_LS_MASK             (0x10000U)
#define PMC_SRAMCTRL0_RAM_03_LS_SHIFT            (16U)
/*! RAM_03_LS - RAM_03 Light Sleep mode.
 */
#define PMC_SRAMCTRL0_RAM_03_LS(x)               (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_03_LS_SHIFT)) & PMC_SRAMCTRL0_RAM_03_LS_MASK)

#define PMC_SRAMCTRL0_RAM_03_DSB_MASK            (0x20000U)
#define PMC_SRAMCTRL0_RAM_03_DSB_SHIFT           (17U)
/*! RAM_03_DSB - RAM_03 Deep sleep mode.
 */
#define PMC_SRAMCTRL0_RAM_03_DSB(x)              (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_03_DSB_SHIFT)) & PMC_SRAMCTRL0_RAM_03_DSB_MASK)

#define PMC_SRAMCTRL0_RAM_03_DSBDEL_MASK         (0x40000U)
#define PMC_SRAMCTRL0_RAM_03_DSBDEL_SHIFT        (18U)
/*! RAM_03_DSBDEL - RAM_03 Deep sleep delayed.
 */
#define PMC_SRAMCTRL0_RAM_03_DSBDEL(x)           (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_03_DSBDEL_SHIFT)) & PMC_SRAMCTRL0_RAM_03_DSBDEL_MASK)

#define PMC_SRAMCTRL0_RAM_03_LSDEL_MASK          (0x80000U)
#define PMC_SRAMCTRL0_RAM_03_LSDEL_SHIFT         (19U)
/*! RAM_03_LSDEL - RAM_03 Sleep mode disable.
 */
#define PMC_SRAMCTRL0_RAM_03_LSDEL(x)            (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_03_LSDEL_SHIFT)) & PMC_SRAMCTRL0_RAM_03_LSDEL_MASK)

#define PMC_SRAMCTRL0_RAM_10_LS_MASK             (0x100000U)
#define PMC_SRAMCTRL0_RAM_10_LS_SHIFT            (20U)
/*! RAM_10_LS - RAM_10 Light Sleep mode.
 */
#define PMC_SRAMCTRL0_RAM_10_LS(x)               (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_10_LS_SHIFT)) & PMC_SRAMCTRL0_RAM_10_LS_MASK)

#define PMC_SRAMCTRL0_RAM_10_DSB_MASK            (0x200000U)
#define PMC_SRAMCTRL0_RAM_10_DSB_SHIFT           (21U)
/*! RAM_10_DSB - RAM_10 Deep sleep mode.
 */
#define PMC_SRAMCTRL0_RAM_10_DSB(x)              (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_10_DSB_SHIFT)) & PMC_SRAMCTRL0_RAM_10_DSB_MASK)

#define PMC_SRAMCTRL0_RAM_10_DSBDEL_MASK         (0x400000U)
#define PMC_SRAMCTRL0_RAM_10_DSBDEL_SHIFT        (22U)
/*! RAM_10_DSBDEL - RAM_10 Deep sleep delayed.
 */
#define PMC_SRAMCTRL0_RAM_10_DSBDEL(x)           (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_10_DSBDEL_SHIFT)) & PMC_SRAMCTRL0_RAM_10_DSBDEL_MASK)

#define PMC_SRAMCTRL0_RAM_10_LSDEL_MASK          (0x800000U)
#define PMC_SRAMCTRL0_RAM_10_LSDEL_SHIFT         (23U)
/*! RAM_10_LSDEL - RAM_10 Sleep mode disable.
 */
#define PMC_SRAMCTRL0_RAM_10_LSDEL(x)            (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_10_LSDEL_SHIFT)) & PMC_SRAMCTRL0_RAM_10_LSDEL_MASK)

#define PMC_SRAMCTRL0_RAM_20_LS_MASK             (0x1000000U)
#define PMC_SRAMCTRL0_RAM_20_LS_SHIFT            (24U)
/*! RAM_20_LS - RAM_20 Light Sleep mode.
 */
#define PMC_SRAMCTRL0_RAM_20_LS(x)               (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_20_LS_SHIFT)) & PMC_SRAMCTRL0_RAM_20_LS_MASK)

#define PMC_SRAMCTRL0_RAM_20_DSB_MASK            (0x2000000U)
#define PMC_SRAMCTRL0_RAM_20_DSB_SHIFT           (25U)
/*! RAM_20_DSB - RAM_20 Deep sleep mode.
 */
#define PMC_SRAMCTRL0_RAM_20_DSB(x)              (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_20_DSB_SHIFT)) & PMC_SRAMCTRL0_RAM_20_DSB_MASK)

#define PMC_SRAMCTRL0_RAM_20_DSBDEL_MASK         (0x4000000U)
#define PMC_SRAMCTRL0_RAM_20_DSBDEL_SHIFT        (26U)
/*! RAM_20_DSBDEL - RAM_20 Deep sleep delayed.
 */
#define PMC_SRAMCTRL0_RAM_20_DSBDEL(x)           (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_20_DSBDEL_SHIFT)) & PMC_SRAMCTRL0_RAM_20_DSBDEL_MASK)

#define PMC_SRAMCTRL0_RAM_20_LSDEL_MASK          (0x8000000U)
#define PMC_SRAMCTRL0_RAM_20_LSDEL_SHIFT         (27U)
/*! RAM_20_LSDEL - RAM_20 Sleep mode disable.
 */
#define PMC_SRAMCTRL0_RAM_20_LSDEL(x)            (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_20_LSDEL_SHIFT)) & PMC_SRAMCTRL0_RAM_20_LSDEL_MASK)

#define PMC_SRAMCTRL0_RAM_30_LS_MASK             (0x10000000U)
#define PMC_SRAMCTRL0_RAM_30_LS_SHIFT            (28U)
/*! RAM_30_LS - RAM_30 Light Sleep mode.
 */
#define PMC_SRAMCTRL0_RAM_30_LS(x)               (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_30_LS_SHIFT)) & PMC_SRAMCTRL0_RAM_30_LS_MASK)

#define PMC_SRAMCTRL0_RAM_30_DSB_MASK            (0x20000000U)
#define PMC_SRAMCTRL0_RAM_30_DSB_SHIFT           (29U)
/*! RAM_30_DSB - RAM_30 Deep sleep mode.
 */
#define PMC_SRAMCTRL0_RAM_30_DSB(x)              (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_30_DSB_SHIFT)) & PMC_SRAMCTRL0_RAM_30_DSB_MASK)

#define PMC_SRAMCTRL0_RAM_30_DSBDEL_MASK         (0x40000000U)
#define PMC_SRAMCTRL0_RAM_30_DSBDEL_SHIFT        (30U)
/*! RAM_30_DSBDEL - RAM_30 Deep sleep delayed.
 */
#define PMC_SRAMCTRL0_RAM_30_DSBDEL(x)           (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_30_DSBDEL_SHIFT)) & PMC_SRAMCTRL0_RAM_30_DSBDEL_MASK)

#define PMC_SRAMCTRL0_RAM_30_LSDEL_MASK          (0x80000000U)
#define PMC_SRAMCTRL0_RAM_30_LSDEL_SHIFT         (31U)
/*! RAM_30_LSDEL - RAM_30 Light Sleep mode delayed.
 */
#define PMC_SRAMCTRL0_RAM_30_LSDEL(x)            (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL0_RAM_30_LSDEL_SHIFT)) & PMC_SRAMCTRL0_RAM_30_LSDEL_MASK)
/*! @} */

/*! @name SRAMCTRL1 - RAM_40 to RAM_43 power modes controls [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] When [LS, LSDEL, DSB, DSBDEL] is: 0011 : Normal Mode 1111 : Light sleep mode 0100 : Deep-sleep mode 1100 : Shut down Mode */
/*! @{ */

#define PMC_SRAMCTRL1_RAM_40_LS_MASK             (0x1U)
#define PMC_SRAMCTRL1_RAM_40_LS_SHIFT            (0U)
/*! RAM_40_LS - RAM_40 Light Sleep mode.
 */
#define PMC_SRAMCTRL1_RAM_40_LS(x)               (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_40_LS_SHIFT)) & PMC_SRAMCTRL1_RAM_40_LS_MASK)

#define PMC_SRAMCTRL1_RAM_40_DSB_MASK            (0x2U)
#define PMC_SRAMCTRL1_RAM_40_DSB_SHIFT           (1U)
/*! RAM_40_DSB - RAM_40 Deep sleep mode.
 */
#define PMC_SRAMCTRL1_RAM_40_DSB(x)              (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_40_DSB_SHIFT)) & PMC_SRAMCTRL1_RAM_40_DSB_MASK)

#define PMC_SRAMCTRL1_RAM_40_DSBDEL_MASK         (0x4U)
#define PMC_SRAMCTRL1_RAM_40_DSBDEL_SHIFT        (2U)
/*! RAM_40_DSBDEL - RAM_40 Deep sleep delayed.
 */
#define PMC_SRAMCTRL1_RAM_40_DSBDEL(x)           (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_40_DSBDEL_SHIFT)) & PMC_SRAMCTRL1_RAM_40_DSBDEL_MASK)

#define PMC_SRAMCTRL1_RAM_40_LSDEL_MASK          (0x8U)
#define PMC_SRAMCTRL1_RAM_40_LSDEL_SHIFT         (3U)
/*! RAM_40_LSDEL - RAM_40 Sleep mode disable.
 */
#define PMC_SRAMCTRL1_RAM_40_LSDEL(x)            (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_40_LSDEL_SHIFT)) & PMC_SRAMCTRL1_RAM_40_LSDEL_MASK)

#define PMC_SRAMCTRL1_RAM_41_LS_MASK             (0x10U)
#define PMC_SRAMCTRL1_RAM_41_LS_SHIFT            (4U)
/*! RAM_41_LS - RAM_41 Light Sleep mode.
 */
#define PMC_SRAMCTRL1_RAM_41_LS(x)               (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_41_LS_SHIFT)) & PMC_SRAMCTRL1_RAM_41_LS_MASK)

#define PMC_SRAMCTRL1_RAM_41_DSB_MASK            (0x20U)
#define PMC_SRAMCTRL1_RAM_41_DSB_SHIFT           (5U)
/*! RAM_41_DSB - RAM_41 Deep sleep mode.
 */
#define PMC_SRAMCTRL1_RAM_41_DSB(x)              (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_41_DSB_SHIFT)) & PMC_SRAMCTRL1_RAM_41_DSB_MASK)

#define PMC_SRAMCTRL1_RAM_41_DSBDEL_MASK         (0x40U)
#define PMC_SRAMCTRL1_RAM_41_DSBDEL_SHIFT        (6U)
/*! RAM_41_DSBDEL - RAM_41 Deep sleep delayed.
 */
#define PMC_SRAMCTRL1_RAM_41_DSBDEL(x)           (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_41_DSBDEL_SHIFT)) & PMC_SRAMCTRL1_RAM_41_DSBDEL_MASK)

#define PMC_SRAMCTRL1_RAM_41_LSDEL_MASK          (0x80U)
#define PMC_SRAMCTRL1_RAM_41_LSDEL_SHIFT         (7U)
/*! RAM_41_LSDEL - RAM_41 Sleep mode disable.
 */
#define PMC_SRAMCTRL1_RAM_41_LSDEL(x)            (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_41_LSDEL_SHIFT)) & PMC_SRAMCTRL1_RAM_41_LSDEL_MASK)

#define PMC_SRAMCTRL1_RAM_42_LS_MASK             (0x100U)
#define PMC_SRAMCTRL1_RAM_42_LS_SHIFT            (8U)
/*! RAM_42_LS - RAM_42 Light Sleep mode.
 */
#define PMC_SRAMCTRL1_RAM_42_LS(x)               (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_42_LS_SHIFT)) & PMC_SRAMCTRL1_RAM_42_LS_MASK)

#define PMC_SRAMCTRL1_RAM_42_DSB_MASK            (0x200U)
#define PMC_SRAMCTRL1_RAM_42_DSB_SHIFT           (9U)
/*! RAM_42_DSB - RAM_42 Deep sleep mode.
 */
#define PMC_SRAMCTRL1_RAM_42_DSB(x)              (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_42_DSB_SHIFT)) & PMC_SRAMCTRL1_RAM_42_DSB_MASK)

#define PMC_SRAMCTRL1_RAM_42_DSBDEL_MASK         (0x400U)
#define PMC_SRAMCTRL1_RAM_42_DSBDEL_SHIFT        (10U)
/*! RAM_42_DSBDEL - RAM_42 Deep sleep delayed.
 */
#define PMC_SRAMCTRL1_RAM_42_DSBDEL(x)           (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_42_DSBDEL_SHIFT)) & PMC_SRAMCTRL1_RAM_42_DSBDEL_MASK)

#define PMC_SRAMCTRL1_RAM_42_LSDEL_MASK          (0x800U)
#define PMC_SRAMCTRL1_RAM_42_LSDEL_SHIFT         (11U)
/*! RAM_42_LSDEL - RAM_42 Sleep mode disable.
 */
#define PMC_SRAMCTRL1_RAM_42_LSDEL(x)            (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_42_LSDEL_SHIFT)) & PMC_SRAMCTRL1_RAM_42_LSDEL_MASK)

#define PMC_SRAMCTRL1_RAM_43_LS_MASK             (0x1000U)
#define PMC_SRAMCTRL1_RAM_43_LS_SHIFT            (12U)
/*! RAM_43_LS - RAM_43 Light Sleep mode.
 */
#define PMC_SRAMCTRL1_RAM_43_LS(x)               (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_43_LS_SHIFT)) & PMC_SRAMCTRL1_RAM_43_LS_MASK)

#define PMC_SRAMCTRL1_RAM_43_DSB_MASK            (0x2000U)
#define PMC_SRAMCTRL1_RAM_43_DSB_SHIFT           (13U)
/*! RAM_43_DSB - RAM_43 Deep sleep mode.
 */
#define PMC_SRAMCTRL1_RAM_43_DSB(x)              (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_43_DSB_SHIFT)) & PMC_SRAMCTRL1_RAM_43_DSB_MASK)

#define PMC_SRAMCTRL1_RAM_43_DSBDEL_MASK         (0x4000U)
#define PMC_SRAMCTRL1_RAM_43_DSBDEL_SHIFT        (14U)
/*! RAM_43_DSBDEL - RAM_43 Deep sleep delayed.
 */
#define PMC_SRAMCTRL1_RAM_43_DSBDEL(x)           (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_43_DSBDEL_SHIFT)) & PMC_SRAMCTRL1_RAM_43_DSBDEL_MASK)

#define PMC_SRAMCTRL1_RAM_43_LSDEL_MASK          (0x8000U)
#define PMC_SRAMCTRL1_RAM_43_LSDEL_SHIFT         (15U)
/*! RAM_43_LSDEL - RAM_43 Sleep mode disable.
 */
#define PMC_SRAMCTRL1_RAM_43_LSDEL(x)            (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_43_LSDEL_SHIFT)) & PMC_SRAMCTRL1_RAM_43_LSDEL_MASK)

#define PMC_SRAMCTRL1_RAM_FLASHLPCACHE_LS_MASK   (0x10000U)
#define PMC_SRAMCTRL1_RAM_FLASHLPCACHE_LS_SHIFT  (16U)
/*! RAM_FLASHLPCACHE_LS - Flash Cache RAM Light Sleep mode.
 */
#define PMC_SRAMCTRL1_RAM_FLASHLPCACHE_LS(x)     (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_FLASHLPCACHE_LS_SHIFT)) & PMC_SRAMCTRL1_RAM_FLASHLPCACHE_LS_MASK)

#define PMC_SRAMCTRL1_RAM_FLASHLPCACHE_DSB_MASK  (0x20000U)
#define PMC_SRAMCTRL1_RAM_FLASHLPCACHE_DSB_SHIFT (17U)
/*! RAM_FLASHLPCACHE_DSB - Flash Cache RAM Deep sleep mode.
 */
#define PMC_SRAMCTRL1_RAM_FLASHLPCACHE_DSB(x)    (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_FLASHLPCACHE_DSB_SHIFT)) & PMC_SRAMCTRL1_RAM_FLASHLPCACHE_DSB_MASK)

#define PMC_SRAMCTRL1_RAM_FLASHLPCACHE_DSBDEL_MASK (0x40000U)
#define PMC_SRAMCTRL1_RAM_FLASHLPCACHE_DSBDEL_SHIFT (18U)
/*! RAM_FLASHLPCACHE_DSBDEL - Flash Cache RAM Deep sleep delayed.
 */
#define PMC_SRAMCTRL1_RAM_FLASHLPCACHE_DSBDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_FLASHLPCACHE_DSBDEL_SHIFT)) & PMC_SRAMCTRL1_RAM_FLASHLPCACHE_DSBDEL_MASK)

#define PMC_SRAMCTRL1_RAM_FLASHLPCACHE_LSDEL_MASK (0x80000U)
#define PMC_SRAMCTRL1_RAM_FLASHLPCACHE_LSDEL_SHIFT (19U)
/*! RAM_FLASHLPCACHE_LSDEL - Flash Cache RAM Sleep mode disable.
 */
#define PMC_SRAMCTRL1_RAM_FLASHLPCACHE_LSDEL(x)  (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_FLASHLPCACHE_LSDEL_SHIFT)) & PMC_SRAMCTRL1_RAM_FLASHLPCACHE_LSDEL_MASK)

#define PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_LS_MASK (0x100000U)
#define PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_LS_SHIFT (20U)
/*! RAM_FLEXSPILPCACHE_LS - Flex SPI Cache RAM Light Sleep mode.
 */
#define PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_LS(x)   (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_LS_SHIFT)) & PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_LS_MASK)

#define PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_DSB_MASK (0x200000U)
#define PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_DSB_SHIFT (21U)
/*! RAM_FLEXSPILPCACHE_DSB - Flex SPI Cache RAM Deep sleep mode.
 */
#define PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_DSB(x)  (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_DSB_SHIFT)) & PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_DSB_MASK)

#define PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_DSBDEL_MASK (0x400000U)
#define PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_DSBDEL_SHIFT (22U)
/*! RAM_FLEXSPILPCACHE_DSBDEL - Flex SPI Cache RAM Deep sleep delayed.
 */
#define PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_DSBDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_DSBDEL_SHIFT)) & PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_DSBDEL_MASK)

#define PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_LSDEL_MASK (0x800000U)
#define PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_LSDEL_SHIFT (23U)
/*! RAM_FLEXSPILPCACHE_LSDEL - Flex SPI Cache RAM Sleep mode disable.
 */
#define PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_LSDEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_LSDEL_SHIFT)) & PMC_SRAMCTRL1_RAM_FLEXSPILPCACHE_LSDEL_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group PMC_Register_Masks */


/* PMC - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral PMC base address */
  #define PMC_BASE                                 (0x50020000u)
  /** Peripheral PMC base address */
  #define PMC_BASE_NS                              (0x40020000u)
  /** Peripheral PMC base pointer */
  #define PMC                                      ((PMC_Type *)PMC_BASE)
  /** Peripheral PMC base pointer */
  #define PMC_NS                                   ((PMC_Type *)PMC_BASE_NS)
  /** Array initializer of PMC peripheral base addresses */
  #define PMC_BASE_ADDRS                           { PMC_BASE }
  /** Array initializer of PMC peripheral base pointers */
  #define PMC_BASE_PTRS                            { PMC }
  /** Array initializer of PMC peripheral base addresses */
  #define PMC_BASE_ADDRS_NS                        { PMC_BASE_NS }
  /** Array initializer of PMC peripheral base pointers */
  #define PMC_BASE_PTRS_NS                         { PMC_NS }
#else
  /** Peripheral PMC base address */
  #define PMC_BASE                                 (0x40020000u)
  /** Peripheral PMC base pointer */
  #define PMC                                      ((PMC_Type *)PMC_BASE)
  /** Array initializer of PMC peripheral base addresses */
  #define PMC_BASE_ADDRS                           { PMC_BASE }
  /** Array initializer of PMC peripheral base pointers */
  #define PMC_BASE_PTRS                            { PMC }
#endif

/*!
 * @}
 */ /* end of group PMC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- POWERQUAD Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup POWERQUAD_Peripheral_Access_Layer POWERQUAD Peripheral Access Layer
 * @{
 */

/** POWERQUAD - Register Layout Typedef */
typedef struct {
  __IO uint32_t OUTBASE;                           /**< Output Base, offset: 0x0 */
  __IO uint32_t OUTFORMAT;                         /**< Output Format, offset: 0x4 */
  __IO uint32_t TMPBASE;                           /**< Temporary Base, offset: 0x8 */
  __IO uint32_t TMPFORMAT;                         /**< Temporary Format, offset: 0xC */
  __IO uint32_t INABASE;                           /**< Input A Base, offset: 0x10 */
  __IO uint32_t INAFORMAT;                         /**< Input A Format, offset: 0x14 */
  __IO uint32_t INBBASE;                           /**< Input B Base, offset: 0x18 */
  __IO uint32_t INBFORMAT;                         /**< Input B Format, offset: 0x1C */
       uint8_t RESERVED_0[224];
  __IO uint32_t CONTROL;                           /**< Control, offset: 0x100 */
  __IO uint32_t LENGTH;                            /**< Length, offset: 0x104 */
  __IO uint32_t CPPRE;                             /**< Coprocessor Pre-scale, offset: 0x108 */
  __IO uint32_t MISC;                              /**< Miscellaneous, offset: 0x10C */
  __IO uint32_t CURSORY;                           /**< Cursory, offset: 0x110 */
       uint8_t RESERVED_1[108];
  __IO uint32_t CORDIC_X;                          /**< Cordic input X, offset: 0x180 */
  __IO uint32_t CORDIC_Y;                          /**< Cordic Input Y, offset: 0x184 */
  __IO uint32_t CORDIC_Z;                          /**< Cordic Input Z, offset: 0x188 */
  __IO uint32_t ERRSTAT;                           /**< Error Status, offset: 0x18C */
  __IO uint32_t INTREN;                            /**< Interrupt Enable, offset: 0x190 */
  __IO uint32_t EVENTEN;                           /**< Event Enable, offset: 0x194 */
  __IO uint32_t INTRSTAT;                          /**< Interrupt Status, offset: 0x198 */
       uint8_t RESERVED_2[100];
  __IO uint32_t GPREG[16];                         /**< General Purpose Register Bank n, array offset: 0x200, array step: 0x4 */
  __IO uint32_t COMPREG[8];                        /**< Compute Register Bank n, array offset: 0x240, array step: 0x4 */
} POWERQUAD_Type;

/* ----------------------------------------------------------------------------
   -- POWERQUAD Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup POWERQUAD_Register_Masks POWERQUAD Register Masks
 * @{
 */

/*! @name OUTBASE - Output Base */
/*! @{ */

#define POWERQUAD_OUTBASE_OUTBASE_MASK           (0xFFFFFFFFU)
#define POWERQUAD_OUTBASE_OUTBASE_SHIFT          (0U)
/*! OUTBASE - Base address register for the output region
 */
#define POWERQUAD_OUTBASE_OUTBASE(x)             (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTBASE_OUTBASE_SHIFT)) & POWERQUAD_OUTBASE_OUTBASE_MASK)
/*! @} */

/*! @name OUTFORMAT - Output Format */
/*! @{ */

#define POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK   (0x3U)
#define POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT  (0U)
/*! OUT_FORMATINT - Output Internal Format
 */
#define POWERQUAD_OUTFORMAT_OUT_FORMATINT(x)     (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK)

#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK   (0x30U)
#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT  (4U)
/*! OUT_FORMATEXT - Output External Format
 */
#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT(x)     (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK)

#define POWERQUAD_OUTFORMAT_OUT_SCALER_MASK      (0xFF00U)
#define POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT     (8U)
/*! OUT_SCALER - Output Scaler Value
 */
#define POWERQUAD_OUTFORMAT_OUT_SCALER(x)        (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_SCALER_MASK)
/*! @} */

/*! @name TMPBASE - Temporary Base */
/*! @{ */

#define POWERQUAD_TMPBASE_TMPBASE_MASK           (0xFFFFFFFFU)
#define POWERQUAD_TMPBASE_TMPBASE_SHIFT          (0U)
/*! TMPBASE - Base address register for the temporary region
 */
#define POWERQUAD_TMPBASE_TMPBASE(x)             (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPBASE_TMPBASE_SHIFT)) & POWERQUAD_TMPBASE_TMPBASE_MASK)
/*! @} */

/*! @name TMPFORMAT - Temporary Format */
/*! @{ */

#define POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK   (0x3U)
#define POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT  (0U)
/*! TMP_FORMATINT - Temporary Internal Format
 */
#define POWERQUAD_TMPFORMAT_TMP_FORMATINT(x)     (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK)

#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK   (0x30U)
#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT  (4U)
/*! TMP_FORMATEXT - Temporary External Format
 */
#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT(x)     (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK)

#define POWERQUAD_TMPFORMAT_TMP_SCALER_MASK      (0xFF00U)
#define POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT     (8U)
/*! TMP_SCALER - Temporary Scaler Value
 */
#define POWERQUAD_TMPFORMAT_TMP_SCALER(x)        (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_SCALER_MASK)
/*! @} */

/*! @name INABASE - Input A Base */
/*! @{ */

#define POWERQUAD_INABASE_INABASE_MASK           (0xFFFFFFFFU)
#define POWERQUAD_INABASE_INABASE_SHIFT          (0U)
/*! INABASE - Input A Base
 */
#define POWERQUAD_INABASE_INABASE(x)             (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INABASE_INABASE_SHIFT)) & POWERQUAD_INABASE_INABASE_MASK)
/*! @} */

/*! @name INAFORMAT - Input A Format */
/*! @{ */

#define POWERQUAD_INAFORMAT_INA_FORMATINT_MASK   (0x3U)
#define POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT  (0U)
/*! INA_FORMATINT - Input A Internal Format
 */
#define POWERQUAD_INAFORMAT_INA_FORMATINT(x)     (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATINT_MASK)

#define POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK   (0x30U)
#define POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT  (4U)
/*! INA_FORMATEXT - Input A External Format
 */
#define POWERQUAD_INAFORMAT_INA_FORMATEXT(x)     (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK)

#define POWERQUAD_INAFORMAT_INA_SCALER_MASK      (0xFF00U)
#define POWERQUAD_INAFORMAT_INA_SCALER_SHIFT     (8U)
/*! INA_SCALER - Input A Scaler Value
 */
#define POWERQUAD_INAFORMAT_INA_SCALER(x)        (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_SCALER_SHIFT)) & POWERQUAD_INAFORMAT_INA_SCALER_MASK)
/*! @} */

/*! @name INBBASE - Input B Base */
/*! @{ */

#define POWERQUAD_INBBASE_INBBASE_MASK           (0xFFFFFFFFU)
#define POWERQUAD_INBBASE_INBBASE_SHIFT          (0U)
/*! INBBASE - Input B Base
 */
#define POWERQUAD_INBBASE_INBBASE(x)             (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBBASE_INBBASE_SHIFT)) & POWERQUAD_INBBASE_INBBASE_MASK)
/*! @} */

/*! @name INBFORMAT - Input B Format */
/*! @{ */

#define POWERQUAD_INBFORMAT_INB_FORMATINT_MASK   (0x3U)
#define POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT  (0U)
/*! INB_FORMATINT - Input B Internal Format
 */
#define POWERQUAD_INBFORMAT_INB_FORMATINT(x)     (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATINT_MASK)

#define POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK   (0x30U)
#define POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT  (4U)
/*! INB_FORMATEXT - Input B External Format
 */
#define POWERQUAD_INBFORMAT_INB_FORMATEXT(x)     (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK)

#define POWERQUAD_INBFORMAT_INB_SCALER_MASK      (0xFF00U)
#define POWERQUAD_INBFORMAT_INB_SCALER_SHIFT     (8U)
/*! INB_SCALER - Input B Scaler Value
 */
#define POWERQUAD_INBFORMAT_INB_SCALER(x)        (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_SCALER_SHIFT)) & POWERQUAD_INBFORMAT_INB_SCALER_MASK)
/*! @} */

/*! @name CONTROL - Control */
/*! @{ */

#define POWERQUAD_CONTROL_DECODE_OPCODE_MASK     (0xFU)
#define POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT    (0U)
/*! DECODE_OPCODE - Decode Opcode
 */
#define POWERQUAD_CONTROL_DECODE_OPCODE(x)       (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT)) & POWERQUAD_CONTROL_DECODE_OPCODE_MASK)

#define POWERQUAD_CONTROL_DECODE_MACHINE_MASK    (0xF0U)
#define POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT   (4U)
/*! DECODE_MACHINE - Decode Machine
 */
#define POWERQUAD_CONTROL_DECODE_MACHINE(x)      (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT)) & POWERQUAD_CONTROL_DECODE_MACHINE_MASK)

#define POWERQUAD_CONTROL_INST_BUSY_MASK         (0x80000000U)
#define POWERQUAD_CONTROL_INST_BUSY_SHIFT        (31U)
/*! INST_BUSY - Instruction Busy
 */
#define POWERQUAD_CONTROL_INST_BUSY(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_INST_BUSY_SHIFT)) & POWERQUAD_CONTROL_INST_BUSY_MASK)
/*! @} */

/*! @name LENGTH - Length */
/*! @{ */

#define POWERQUAD_LENGTH_INST_LENGTH_MASK        (0xFFFFFFFFU)
#define POWERQUAD_LENGTH_INST_LENGTH_SHIFT       (0U)
/*! INST_LENGTH - Instruction Length
 */
#define POWERQUAD_LENGTH_INST_LENGTH(x)          (((uint32_t)(((uint32_t)(x)) << POWERQUAD_LENGTH_INST_LENGTH_SHIFT)) & POWERQUAD_LENGTH_INST_LENGTH_MASK)
/*! @} */

/*! @name CPPRE - Coprocessor Pre-scale */
/*! @{ */

#define POWERQUAD_CPPRE_CPPRE_IN_MASK            (0xFFU)
#define POWERQUAD_CPPRE_CPPRE_IN_SHIFT           (0U)
/*! CPPRE_IN - Input
 */
#define POWERQUAD_CPPRE_CPPRE_IN(x)              (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_IN_SHIFT)) & POWERQUAD_CPPRE_CPPRE_IN_MASK)

#define POWERQUAD_CPPRE_CPPRE_OUT_MASK           (0xFF00U)
#define POWERQUAD_CPPRE_CPPRE_OUT_SHIFT          (8U)
/*! CPPRE_OUT - Output
 */
#define POWERQUAD_CPPRE_CPPRE_OUT(x)             (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_OUT_SHIFT)) & POWERQUAD_CPPRE_CPPRE_OUT_MASK)

#define POWERQUAD_CPPRE_CPPRE_SAT_MASK           (0x10000U)
#define POWERQUAD_CPPRE_CPPRE_SAT_SHIFT          (16U)
/*! CPPRE_SAT - Saturation
 *  0b0..No saturation
 *  0b1..Forces sub-32 bit saturation
 */
#define POWERQUAD_CPPRE_CPPRE_SAT(x)             (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_SAT_SHIFT)) & POWERQUAD_CPPRE_CPPRE_SAT_MASK)

#define POWERQUAD_CPPRE_CPPRE_SAT8_MASK          (0x20000U)
#define POWERQUAD_CPPRE_CPPRE_SAT8_SHIFT         (17U)
/*! CPPRE_SAT8 - Saturation 8
 *  0b0..8 bits
 *  0b1..16 bits
 */
#define POWERQUAD_CPPRE_CPPRE_SAT8(x)            (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_SAT8_SHIFT)) & POWERQUAD_CPPRE_CPPRE_SAT8_MASK)
/*! @} */

/*! @name MISC - Miscellaneous */
/*! @{ */

#define POWERQUAD_MISC_INST_MISC_MASK            (0xFFFFFFFFU)
#define POWERQUAD_MISC_INST_MISC_SHIFT           (0U)
/*! INST_MISC - For Matrix : Used for scaling factor
 */
#define POWERQUAD_MISC_INST_MISC(x)              (((uint32_t)(((uint32_t)(x)) << POWERQUAD_MISC_INST_MISC_SHIFT)) & POWERQUAD_MISC_INST_MISC_MASK)
/*! @} */

/*! @name CURSORY - Cursory */
/*! @{ */

#define POWERQUAD_CURSORY_CURSORY_MASK           (0x1U)
#define POWERQUAD_CURSORY_CURSORY_SHIFT          (0U)
/*! CURSORY - Cursory Mode
 *  0b0..Disable Cursory mode
 *  0b1..Enable Cursory Mode
 */
#define POWERQUAD_CURSORY_CURSORY(x)             (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CURSORY_CURSORY_SHIFT)) & POWERQUAD_CURSORY_CURSORY_MASK)
/*! @} */

/*! @name CORDIC_X - Cordic input X */
/*! @{ */

#define POWERQUAD_CORDIC_X_CORDIC_X_MASK         (0xFFFFFFFFU)
#define POWERQUAD_CORDIC_X_CORDIC_X_SHIFT        (0U)
/*! CORDIC_X - Cordic Input x
 */
#define POWERQUAD_CORDIC_X_CORDIC_X(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_X_CORDIC_X_SHIFT)) & POWERQUAD_CORDIC_X_CORDIC_X_MASK)
/*! @} */

/*! @name CORDIC_Y - Cordic Input Y */
/*! @{ */

#define POWERQUAD_CORDIC_Y_CORDIC_Y_MASK         (0xFFFFFFFFU)
#define POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT        (0U)
/*! CORDIC_Y - Cordic Input y
 */
#define POWERQUAD_CORDIC_Y_CORDIC_Y(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT)) & POWERQUAD_CORDIC_Y_CORDIC_Y_MASK)
/*! @} */

/*! @name CORDIC_Z - Cordic Input Z */
/*! @{ */

#define POWERQUAD_CORDIC_Z_CORDIC_Z_MASK         (0xFFFFFFFFU)
#define POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT        (0U)
/*! CORDIC_Z - Cordic Input z
 */
#define POWERQUAD_CORDIC_Z_CORDIC_Z(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT)) & POWERQUAD_CORDIC_Z_CORDIC_Z_MASK)
/*! @} */

/*! @name ERRSTAT - Error Status */
/*! @{ */

#define POWERQUAD_ERRSTAT_OVERFLOW_MASK          (0x1U)
#define POWERQUAD_ERRSTAT_OVERFLOW_SHIFT         (0U)
/*! OVERFLOW - Floating Point Overflow
 *  0b0..No Error
 *  0b1..Error on Floating Point Overflow
 */
#define POWERQUAD_ERRSTAT_OVERFLOW(x)            (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_OVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_OVERFLOW_MASK)

#define POWERQUAD_ERRSTAT_NAN_MASK               (0x2U)
#define POWERQUAD_ERRSTAT_NAN_SHIFT              (1U)
/*! NAN - Floating Point NaN
 *  0b0..No Error
 *  0b1..Error on Floating Point NaN
 */
#define POWERQUAD_ERRSTAT_NAN(x)                 (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_NAN_SHIFT)) & POWERQUAD_ERRSTAT_NAN_MASK)

#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK     (0x4U)
#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT    (2U)
/*! FIXEDOVERFLOW - Fixed Point Overflow
 *  0b0..No Error
 *  0b1..Error on Fixed Point Overflow
 */
#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW(x)       (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK)

#define POWERQUAD_ERRSTAT_UNDERFLOW_MASK         (0x8U)
#define POWERQUAD_ERRSTAT_UNDERFLOW_SHIFT        (3U)
/*! UNDERFLOW - Underflow
 *  0b0..No Error
 *  0b1..Error on Underflow
 */
#define POWERQUAD_ERRSTAT_UNDERFLOW(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_UNDERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_UNDERFLOW_MASK)

#define POWERQUAD_ERRSTAT_BUSERROR_MASK          (0x10U)
#define POWERQUAD_ERRSTAT_BUSERROR_SHIFT         (4U)
/*! BUSERROR - Bus Error
 *  0b0..No Error
 *  0b1..Error on Bus
 */
#define POWERQUAD_ERRSTAT_BUSERROR(x)            (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_BUSERROR_SHIFT)) & POWERQUAD_ERRSTAT_BUSERROR_MASK)
/*! @} */

/*! @name INTREN - Interrupt Enable */
/*! @{ */

#define POWERQUAD_INTREN_INTR_OFLOW_MASK         (0x1U)
#define POWERQUAD_INTREN_INTR_OFLOW_SHIFT        (0U)
/*! INTR_OFLOW - Interrupt Floating Point Overflow
 *  0b0..Disable
 *  0b1..Enable interrupt on floating point overflow
 */
#define POWERQUAD_INTREN_INTR_OFLOW(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_OFLOW_SHIFT)) & POWERQUAD_INTREN_INTR_OFLOW_MASK)

#define POWERQUAD_INTREN_INTR_NAN_MASK           (0x2U)
#define POWERQUAD_INTREN_INTR_NAN_SHIFT          (1U)
/*! INTR_NAN - Interrupt Floating Point NaN
 *  0b0..Disable
 *  0b1..Enable interrupt on floating point NaN
 */
#define POWERQUAD_INTREN_INTR_NAN(x)             (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_NAN_SHIFT)) & POWERQUAD_INTREN_INTR_NAN_MASK)

#define POWERQUAD_INTREN_INTR_FIXED_MASK         (0x4U)
#define POWERQUAD_INTREN_INTR_FIXED_SHIFT        (2U)
/*! INTR_FIXED - Interrupt on Fixed Point Overflow
 *  0b0..Disable
 *  0b1..Enable interrupt on fixed point overflow
 */
#define POWERQUAD_INTREN_INTR_FIXED(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_FIXED_SHIFT)) & POWERQUAD_INTREN_INTR_FIXED_MASK)

#define POWERQUAD_INTREN_INTR_UFLOW_MASK         (0x8U)
#define POWERQUAD_INTREN_INTR_UFLOW_SHIFT        (3U)
/*! INTR_UFLOW - Interrupt on Subnormal Truncation
 *  0b0..Disable
 *  0b1..Enable interrupt on subnormal truncation
 */
#define POWERQUAD_INTREN_INTR_UFLOW(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_UFLOW_SHIFT)) & POWERQUAD_INTREN_INTR_UFLOW_MASK)

#define POWERQUAD_INTREN_INTR_BERR_MASK          (0x10U)
#define POWERQUAD_INTREN_INTR_BERR_SHIFT         (4U)
/*! INTR_BERR - Interrupt on AHBM Bus Error
 *  0b0..Disable
 *  0b1..Enable interrupt on AHBM Bus Error
 */
#define POWERQUAD_INTREN_INTR_BERR(x)            (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_BERR_SHIFT)) & POWERQUAD_INTREN_INTR_BERR_MASK)

#define POWERQUAD_INTREN_INTR_COMP_MASK          (0x80U)
#define POWERQUAD_INTREN_INTR_COMP_SHIFT         (7U)
/*! INTR_COMP - Interrupt on Instruction Completion
 *  0b0..Disable
 *  0b1..Enable interrupt on instruction completion
 */
#define POWERQUAD_INTREN_INTR_COMP(x)            (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_COMP_SHIFT)) & POWERQUAD_INTREN_INTR_COMP_MASK)
/*! @} */

/*! @name EVENTEN - Event Enable */
/*! @{ */

#define POWERQUAD_EVENTEN_EVENT_OFLOW_MASK       (0x1U)
#define POWERQUAD_EVENTEN_EVENT_OFLOW_SHIFT      (0U)
/*! EVENT_OFLOW - Event Trigger on Floating Point Overflow
 *  0b0..Disable
 *  0b1..Enable event trigger on Floating point overflow
 */
#define POWERQUAD_EVENTEN_EVENT_OFLOW(x)         (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_OFLOW_SHIFT)) & POWERQUAD_EVENTEN_EVENT_OFLOW_MASK)

#define POWERQUAD_EVENTEN_EVENT_NAN_MASK         (0x2U)
#define POWERQUAD_EVENTEN_EVENT_NAN_SHIFT        (1U)
/*! EVENT_NAN - Event Trigger on Floating Point NaN
 *  0b0..Disable
 *  0b1..Enable event trigger on floating point NaN
 */
#define POWERQUAD_EVENTEN_EVENT_NAN(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_NAN_SHIFT)) & POWERQUAD_EVENTEN_EVENT_NAN_MASK)

#define POWERQUAD_EVENTEN_EVENT_FIXED_MASK       (0x4U)
#define POWERQUAD_EVENTEN_EVENT_FIXED_SHIFT      (2U)
/*! EVENT_FIXED - Event Trigger on Fixed Point Overflow
 *  0b0..Disable
 *  0b1..Enable event trigger on fixed point overflow
 */
#define POWERQUAD_EVENTEN_EVENT_FIXED(x)         (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_FIXED_SHIFT)) & POWERQUAD_EVENTEN_EVENT_FIXED_MASK)

#define POWERQUAD_EVENTEN_EVENT_UFLOW_MASK       (0x8U)
#define POWERQUAD_EVENTEN_EVENT_UFLOW_SHIFT      (3U)
/*! EVENT_UFLOW - Event Trigger on Subnormal Truncation
 *  0b0..Disable
 *  0b1..Enable event trigger on subnormal truncation
 */
#define POWERQUAD_EVENTEN_EVENT_UFLOW(x)         (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_UFLOW_SHIFT)) & POWERQUAD_EVENTEN_EVENT_UFLOW_MASK)

#define POWERQUAD_EVENTEN_EVENT_BERR_MASK        (0x10U)
#define POWERQUAD_EVENTEN_EVENT_BERR_SHIFT       (4U)
/*! EVENT_BERR - Event Trigger on AHBM Bus Error
 *  0b0..Disable
 *  0b1..Enable event trigger on AHBM bus error
 */
#define POWERQUAD_EVENTEN_EVENT_BERR(x)          (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_BERR_SHIFT)) & POWERQUAD_EVENTEN_EVENT_BERR_MASK)

#define POWERQUAD_EVENTEN_EVENT_COMP_MASK        (0x80U)
#define POWERQUAD_EVENTEN_EVENT_COMP_SHIFT       (7U)
/*! EVENT_COMP - Event Trigger on Instruction Completion
 *  0b0..Disable
 *  0b1..Enable event trigger on instruction completion
 */
#define POWERQUAD_EVENTEN_EVENT_COMP(x)          (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_COMP_SHIFT)) & POWERQUAD_EVENTEN_EVENT_COMP_MASK)
/*! @} */

/*! @name INTRSTAT - Interrupt Status */
/*! @{ */

#define POWERQUAD_INTRSTAT_INTR_STAT_MASK        (0x1U)
#define POWERQUAD_INTRSTAT_INTR_STAT_SHIFT       (0U)
/*! INTR_STAT - Interrupt Status
 *  0b0..No new interrupt
 *  0b1..Interrupt captured
 */
#define POWERQUAD_INTRSTAT_INTR_STAT(x)          (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTRSTAT_INTR_STAT_SHIFT)) & POWERQUAD_INTRSTAT_INTR_STAT_MASK)
/*! @} */

/*! @name GPREG - General Purpose Register Bank n */
/*! @{ */

#define POWERQUAD_GPREG_GPREG_MASK               (0xFFFFFFFFU)
#define POWERQUAD_GPREG_GPREG_SHIFT              (0U)
/*! GPREG - General Purpose Register Bank
 */
#define POWERQUAD_GPREG_GPREG(x)                 (((uint32_t)(((uint32_t)(x)) << POWERQUAD_GPREG_GPREG_SHIFT)) & POWERQUAD_GPREG_GPREG_MASK)
/*! @} */

/* The count of POWERQUAD_GPREG */
#define POWERQUAD_GPREG_COUNT                    (16U)

/*! @name COMPREGS_COMPREG - Compute Register Bank n */
/*! @{ */

#define POWERQUAD_COMPREGS_COMPREG_COMPREG_MASK  (0xFFFFFFFFU)
#define POWERQUAD_COMPREGS_COMPREG_COMPREG_SHIFT (0U)
/*! COMPREG - Compute Register Bank
 */
#define POWERQUAD_COMPREGS_COMPREG_COMPREG(x)    (((uint32_t)(((uint32_t)(x)) << POWERQUAD_COMPREGS_COMPREG_COMPREG_SHIFT)) & POWERQUAD_COMPREGS_COMPREG_COMPREG_MASK)
/*! @} */

/* The count of POWERQUAD_COMPREGS_COMPREG */
#define POWERQUAD_COMPREGS_COMPREG_COUNT         (8U)


/*!
 * @}
 */ /* end of group POWERQUAD_Register_Masks */


/* POWERQUAD - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral POWERQUAD base address */
  #define POWERQUAD_BASE                           (0x500A6000u)
  /** Peripheral POWERQUAD base address */
  #define POWERQUAD_BASE_NS                        (0x400A6000u)
  /** Peripheral POWERQUAD base pointer */
  #define POWERQUAD                                ((POWERQUAD_Type *)POWERQUAD_BASE)
  /** Peripheral POWERQUAD base pointer */
  #define POWERQUAD_NS                             ((POWERQUAD_Type *)POWERQUAD_BASE_NS)
  /** Array initializer of POWERQUAD peripheral base addresses */
  #define POWERQUAD_BASE_ADDRS                     { POWERQUAD_BASE }
  /** Array initializer of POWERQUAD peripheral base pointers */
  #define POWERQUAD_BASE_PTRS                      { POWERQUAD }
  /** Array initializer of POWERQUAD peripheral base addresses */
  #define POWERQUAD_BASE_ADDRS_NS                  { POWERQUAD_BASE_NS }
  /** Array initializer of POWERQUAD peripheral base pointers */
  #define POWERQUAD_BASE_PTRS_NS                   { POWERQUAD_NS }
#else
  /** Peripheral POWERQUAD base address */
  #define POWERQUAD_BASE                           (0x400A6000u)
  /** Peripheral POWERQUAD base pointer */
  #define POWERQUAD                                ((POWERQUAD_Type *)POWERQUAD_BASE)
  /** Array initializer of POWERQUAD peripheral base addresses */
  #define POWERQUAD_BASE_ADDRS                     { POWERQUAD_BASE }
  /** Array initializer of POWERQUAD peripheral base pointers */
  #define POWERQUAD_BASE_PTRS                      { POWERQUAD }
#endif
/** Interrupt vectors for the POWERQUAD peripheral type */
#define POWERQUAD_IRQS                           { POWERQUAD_IRQn }

/*!
 * @}
 */ /* end of group POWERQUAD_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- PRINCE Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup PRINCE_Peripheral_Access_Layer PRINCE Peripheral Access Layer
 * @{
 */

/** PRINCE - Register Layout Typedef */
typedef struct {
  __IO uint32_t ENC_ENABLE;                        /**< Encryption Enable register, offset: 0x0 */
  __O  uint32_t MASK_LSB;                          /**< Data Mask register, 32 Least Significant Bits, offset: 0x4 */
  __O  uint32_t MASK_MSB;                          /**< Data Mask register, 32 Most Significant Bits, offset: 0x8 */
  __IO uint32_t LOCK;                              /**< Lock register, offset: 0xC */
  __O  uint32_t IV_LSB0;                           /**< Initial Vector register for region 0, Least Significant Bits, offset: 0x10 */
  __O  uint32_t IV_MSB0;                           /**< Initial Vector register for region 0, Most Significant Bits, offset: 0x14 */
  __IO uint32_t BASE_ADDR0;                        /**< Base Address for region 0 register, offset: 0x18 */
  __IO uint32_t SR_ENABLE0;                        /**< Sub-Region Enable register for region 0, offset: 0x1C */
  __O  uint32_t IV_LSB1;                           /**< Initial Vector register for region 1, Least Significant Bits, offset: 0x20 */
  __O  uint32_t IV_MSB1;                           /**< Initial Vector register for region 1, Most Significant Bits, offset: 0x24 */
  __IO uint32_t BASE_ADDR1;                        /**< Base Address for region 1 register, offset: 0x28 */
  __IO uint32_t SR_ENABLE1;                        /**< Sub-Region Enable register for region 1, offset: 0x2C */
  __O  uint32_t IV_LSB2;                           /**< Initial Vector register for region 2, Least Significant Bits, offset: 0x30 */
  __O  uint32_t IV_MSB2;                           /**< Initial Vector register for region 2, Most Significant Bits, offset: 0x34 */
  __IO uint32_t BASE_ADDR2;                        /**< Base Address for region 2 register, offset: 0x38 */
  __IO uint32_t SR_ENABLE2;                        /**< Sub-Region Enable register for region 2, offset: 0x3C */
       uint8_t RESERVED_0[80];
  __IO uint32_t ERR;                               /**< Error status register, offset: 0x90 */
       uint8_t RESERVED_1[108];
  __IO uint32_t SR_XOM[3];                         /**< XOM enable for sub region 0..XOM enable for sub region 2, array offset: 0x100, array step: 0x4 */
} PRINCE_Type;

/* ----------------------------------------------------------------------------
   -- PRINCE Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup PRINCE_Register_Masks PRINCE Register Masks
 * @{
 */

/*! @name ENC_ENABLE - Encryption Enable register */
/*! @{ */

#define PRINCE_ENC_ENABLE_EN_MASK                (0x1U)
#define PRINCE_ENC_ENABLE_EN_SHIFT               (0U)
/*! EN - Enables PRINCE encryption for flash programming.
 *  0b0..Encryption of writes to the flash controller DATAW* registers is disabled.
 *  0b1..Encryption of writes to the flash controller DATAW* registers is enabled. Reading of PRINCE-encrypted flash regions is disabled.
 */
#define PRINCE_ENC_ENABLE_EN(x)                  (((uint32_t)(((uint32_t)(x)) << PRINCE_ENC_ENABLE_EN_SHIFT)) & PRINCE_ENC_ENABLE_EN_MASK)
/*! @} */

/*! @name MASK_LSB - Data Mask register, 32 Least Significant Bits */
/*! @{ */

#define PRINCE_MASK_LSB_MASKVAL_MASK             (0xFFFFFFFFU)
#define PRINCE_MASK_LSB_MASKVAL_SHIFT            (0U)
/*! MASKVAL - Value of the 32 Least Significant Bits of the 64-bit data mask.
 */
#define PRINCE_MASK_LSB_MASKVAL(x)               (((uint32_t)(((uint32_t)(x)) << PRINCE_MASK_LSB_MASKVAL_SHIFT)) & PRINCE_MASK_LSB_MASKVAL_MASK)
/*! @} */

/*! @name MASK_MSB - Data Mask register, 32 Most Significant Bits */
/*! @{ */

#define PRINCE_MASK_MSB_MASKVAL_MASK             (0xFFFFFFFFU)
#define PRINCE_MASK_MSB_MASKVAL_SHIFT            (0U)
/*! MASKVAL - Value of the 32 Most Significant Bits of the 64-bit data mask.
 */
#define PRINCE_MASK_MSB_MASKVAL(x)               (((uint32_t)(((uint32_t)(x)) << PRINCE_MASK_MSB_MASKVAL_SHIFT)) & PRINCE_MASK_MSB_MASKVAL_MASK)
/*! @} */

/*! @name LOCK - Lock register */
/*! @{ */

#define PRINCE_LOCK_LOCKREG0_MASK                (0x1U)
#define PRINCE_LOCK_LOCKREG0_SHIFT               (0U)
/*! LOCKREG0 - Lock Region 0 registers.
 *  0b0..Disabled. IV_LSB0, IV_MSB0, and SR_ENABLE0 are writable.
 *  0b1..Enabled. IV_LSB0, IV_MSB0, and SR_ENABLE0 are not writable.
 */
#define PRINCE_LOCK_LOCKREG0(x)                  (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG0_SHIFT)) & PRINCE_LOCK_LOCKREG0_MASK)

#define PRINCE_LOCK_LOCKREG1_MASK                (0x2U)
#define PRINCE_LOCK_LOCKREG1_SHIFT               (1U)
/*! LOCKREG1 - Lock Region 1 registers.
 *  0b0..Disabled. IV_LSB1, IV_MSB1, and SR_ENABLE1 are writable.
 *  0b1..Enabled. IV_LSB1, IV_MSB1, and SR_ENABLE1 are not writable.
 */
#define PRINCE_LOCK_LOCKREG1(x)                  (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG1_SHIFT)) & PRINCE_LOCK_LOCKREG1_MASK)

#define PRINCE_LOCK_LOCKREG2_MASK                (0x4U)
#define PRINCE_LOCK_LOCKREG2_SHIFT               (2U)
/*! LOCKREG2 - Lock Region 2 registers.
 *  0b0..Disabled. IV_LSB2, IV_MSB2, and SR_ENABLE2 are writable.
 *  0b1..Enabled. IV_LSB2, IV_MSB2, and SR_ENABLE2 are not writable.
 */
#define PRINCE_LOCK_LOCKREG2(x)                  (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG2_SHIFT)) & PRINCE_LOCK_LOCKREG2_MASK)

#define PRINCE_LOCK_LOCKMASK_MASK                (0x100U)
#define PRINCE_LOCK_LOCKMASK_SHIFT               (8U)
/*! LOCKMASK - Lock the Mask registers.
 *  0b0..Disabled. MASK_LSB, and MASK_MSB are writable.
 *  0b1..Enabled. MASK_LSB, and MASK_MSB are not writable.
 */
#define PRINCE_LOCK_LOCKMASK(x)                  (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKMASK_SHIFT)) & PRINCE_LOCK_LOCKMASK_MASK)
/*! @} */

/*! @name IV_LSB0 - Initial Vector register for region 0, Least Significant Bits */
/*! @{ */

#define PRINCE_IV_LSB0_IVVAL_MASK                (0xFFFFFFFFU)
#define PRINCE_IV_LSB0_IVVAL_SHIFT               (0U)
/*! IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector.
 */
#define PRINCE_IV_LSB0_IVVAL(x)                  (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB0_IVVAL_SHIFT)) & PRINCE_IV_LSB0_IVVAL_MASK)
/*! @} */

/*! @name IV_MSB0 - Initial Vector register for region 0, Most Significant Bits */
/*! @{ */

#define PRINCE_IV_MSB0_IVVAL_MASK                (0xFFFFFFFFU)
#define PRINCE_IV_MSB0_IVVAL_SHIFT               (0U)
/*! IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector.
 */
#define PRINCE_IV_MSB0_IVVAL(x)                  (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB0_IVVAL_SHIFT)) & PRINCE_IV_MSB0_IVVAL_MASK)
/*! @} */

/*! @name BASE_ADDR0 - Base Address for region 0 register */
/*! @{ */

#define PRINCE_BASE_ADDR0_ADDR_FIXED_MASK        (0x3FFFFU)
#define PRINCE_BASE_ADDR0_ADDR_FIXED_SHIFT       (0U)
/*! ADDR_FIXED - Fixed portion of the base address of region 0.
 */
#define PRINCE_BASE_ADDR0_ADDR_FIXED(x)          (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR0_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR0_ADDR_FIXED_MASK)

#define PRINCE_BASE_ADDR0_ADDR_PRG_MASK          (0xC0000U)
#define PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT         (18U)
/*! ADDR_PRG - Programmable portion of the base address of region 0.
 */
#define PRINCE_BASE_ADDR0_ADDR_PRG(x)            (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR0_ADDR_PRG_MASK)
/*! @} */

/*! @name SR_ENABLE0 - Sub-Region Enable register for region 0 */
/*! @{ */

#define PRINCE_SR_ENABLE0_EN_MASK                (0xFFFFFFFFU)
#define PRINCE_SR_ENABLE0_EN_SHIFT               (0U)
/*! EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 0.
 *  0b00000000000000000000000000000000..Encryption disabled for the corresponding sub-region.
 *  0b00000000000000000000000000000001..Encryption enabled for the corresponding sub-region.
 */
#define PRINCE_SR_ENABLE0_EN(x)                  (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE0_EN_SHIFT)) & PRINCE_SR_ENABLE0_EN_MASK)
/*! @} */

/*! @name IV_LSB1 - Initial Vector register for region 1, Least Significant Bits */
/*! @{ */

#define PRINCE_IV_LSB1_IVVAL_MASK                (0xFFFFFFFFU)
#define PRINCE_IV_LSB1_IVVAL_SHIFT               (0U)
/*! IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector.
 */
#define PRINCE_IV_LSB1_IVVAL(x)                  (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB1_IVVAL_SHIFT)) & PRINCE_IV_LSB1_IVVAL_MASK)
/*! @} */

/*! @name IV_MSB1 - Initial Vector register for region 1, Most Significant Bits */
/*! @{ */

#define PRINCE_IV_MSB1_IVVAL_MASK                (0xFFFFFFFFU)
#define PRINCE_IV_MSB1_IVVAL_SHIFT               (0U)
/*! IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector.
 */
#define PRINCE_IV_MSB1_IVVAL(x)                  (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB1_IVVAL_SHIFT)) & PRINCE_IV_MSB1_IVVAL_MASK)
/*! @} */

/*! @name BASE_ADDR1 - Base Address for region 1 register */
/*! @{ */

#define PRINCE_BASE_ADDR1_ADDR_FIXED_MASK        (0x3FFFFU)
#define PRINCE_BASE_ADDR1_ADDR_FIXED_SHIFT       (0U)
/*! ADDR_FIXED - Fixed portion of the base address of region 1.
 */
#define PRINCE_BASE_ADDR1_ADDR_FIXED(x)          (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR1_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR1_ADDR_FIXED_MASK)

#define PRINCE_BASE_ADDR1_ADDR_PRG_MASK          (0xC0000U)
#define PRINCE_BASE_ADDR1_ADDR_PRG_SHIFT         (18U)
/*! ADDR_PRG - Programmable portion of the base address of region 1.
 */
#define PRINCE_BASE_ADDR1_ADDR_PRG(x)            (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR1_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR1_ADDR_PRG_MASK)
/*! @} */

/*! @name SR_ENABLE1 - Sub-Region Enable register for region 1 */
/*! @{ */

#define PRINCE_SR_ENABLE1_EN_MASK                (0xFFFFFFFFU)
#define PRINCE_SR_ENABLE1_EN_SHIFT               (0U)
/*! EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 1.
 *  0b00000000000000000000000000000000..Encryption disabled for the corresponding sub-region.
 *  0b00000000000000000000000000000001..Encryption enabled for the corresponding sub-region.
 */
#define PRINCE_SR_ENABLE1_EN(x)                  (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE1_EN_SHIFT)) & PRINCE_SR_ENABLE1_EN_MASK)
/*! @} */

/*! @name IV_LSB2 - Initial Vector register for region 2, Least Significant Bits */
/*! @{ */

#define PRINCE_IV_LSB2_IVVAL_MASK                (0xFFFFFFFFU)
#define PRINCE_IV_LSB2_IVVAL_SHIFT               (0U)
/*! IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector.
 */
#define PRINCE_IV_LSB2_IVVAL(x)                  (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB2_IVVAL_SHIFT)) & PRINCE_IV_LSB2_IVVAL_MASK)
/*! @} */

/*! @name IV_MSB2 - Initial Vector register for region 2, Most Significant Bits */
/*! @{ */

#define PRINCE_IV_MSB2_IVVAL_MASK                (0xFFFFFFFFU)
#define PRINCE_IV_MSB2_IVVAL_SHIFT               (0U)
/*! IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector.
 */
#define PRINCE_IV_MSB2_IVVAL(x)                  (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB2_IVVAL_SHIFT)) & PRINCE_IV_MSB2_IVVAL_MASK)
/*! @} */

/*! @name BASE_ADDR2 - Base Address for region 2 register */
/*! @{ */

#define PRINCE_BASE_ADDR2_ADDR_FIXED_MASK        (0x3FFFFU)
#define PRINCE_BASE_ADDR2_ADDR_FIXED_SHIFT       (0U)
/*! ADDR_FIXED - Fixed portion of the base address of region 2.
 */
#define PRINCE_BASE_ADDR2_ADDR_FIXED(x)          (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR2_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR2_ADDR_FIXED_MASK)

#define PRINCE_BASE_ADDR2_ADDR_PRG_MASK          (0xC0000U)
#define PRINCE_BASE_ADDR2_ADDR_PRG_SHIFT         (18U)
/*! ADDR_PRG - Programmable portion of the base address of region 2.
 */
#define PRINCE_BASE_ADDR2_ADDR_PRG(x)            (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR2_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR2_ADDR_PRG_MASK)
/*! @} */

/*! @name SR_ENABLE2 - Sub-Region Enable register for region 2 */
/*! @{ */

#define PRINCE_SR_ENABLE2_EN_MASK                (0xFFFFFFFFU)
#define PRINCE_SR_ENABLE2_EN_SHIFT               (0U)
/*! EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 2.
 *  0b00000000000000000000000000000000..Encryption disabled for the corresponding sub-region.
 *  0b00000000000000000000000000000001..Encryption enabled for the corresponding sub-region.
 */
#define PRINCE_SR_ENABLE2_EN(x)                  (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE2_EN_SHIFT)) & PRINCE_SR_ENABLE2_EN_MASK)
/*! @} */

/*! @name ERR - Error status register */
/*! @{ */

#define PRINCE_ERR_ERRSTAT_MASK                  (0x1U)
#define PRINCE_ERR_ERRSTAT_SHIFT                 (0U)
/*! ERRSTAT - PRINCE Error Status. This bit is write-1 to clear.
 *  0b0..No PRINCE error.
 *  0b1..Error. A read of a PRINCE-encrypted region was attempted while ENC_ENABLE[EN]=1.
 */
#define PRINCE_ERR_ERRSTAT(x)                    (((uint32_t)(((uint32_t)(x)) << PRINCE_ERR_ERRSTAT_SHIFT)) & PRINCE_ERR_ERRSTAT_MASK)
/*! @} */

/*! @name SR_XOMX_SR_XOM - XOM enable for sub region 0..XOM enable for sub region 2 */
/*! @{ */

#define PRINCE_SR_XOMX_SR_XOM_XOM_EN_MASK        (0xFFFFFFFFU)
#define PRINCE_SR_XOMX_SR_XOM_XOM_EN_SHIFT       (0U)
/*! XOM_EN - XOM enable
 *  0b00000000000000000000000000000000..A 0 in bit n means that decryption of data associated with sub-region n is done for both data and code read transactions.
 *  0b00000000000000000000000000000001..A 1 in bit n means that decryption of data associated with sub-region n is done for code fetch transactions only.
 */
#define PRINCE_SR_XOMX_SR_XOM_XOM_EN(x)          (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_XOMX_SR_XOM_XOM_EN_SHIFT)) & PRINCE_SR_XOMX_SR_XOM_XOM_EN_MASK)
/*! @} */

/* The count of PRINCE_SR_XOMX_SR_XOM */
#define PRINCE_SR_XOMX_SR_XOM_COUNT              (3U)


/*!
 * @}
 */ /* end of group PRINCE_Register_Masks */


/* PRINCE - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral PRINCE0 base address */
  #define PRINCE0_BASE                             (0x50035000u)
  /** Peripheral PRINCE0 base address */
  #define PRINCE0_BASE_NS                          (0x40035000u)
  /** Peripheral PRINCE0 base pointer */
  #define PRINCE0                                  ((PRINCE_Type *)PRINCE0_BASE)
  /** Peripheral PRINCE0 base pointer */
  #define PRINCE0_NS                               ((PRINCE_Type *)PRINCE0_BASE_NS)
  /** Array initializer of PRINCE peripheral base addresses */
  #define PRINCE_BASE_ADDRS                        { PRINCE0_BASE }
  /** Array initializer of PRINCE peripheral base pointers */
  #define PRINCE_BASE_PTRS                         { PRINCE0 }
  /** Array initializer of PRINCE peripheral base addresses */
  #define PRINCE_BASE_ADDRS_NS                     { PRINCE0_BASE_NS }
  /** Array initializer of PRINCE peripheral base pointers */
  #define PRINCE_BASE_PTRS_NS                      { PRINCE0_NS }
#else
  /** Peripheral PRINCE0 base address */
  #define PRINCE0_BASE                             (0x40035000u)
  /** Peripheral PRINCE0 base pointer */
  #define PRINCE0                                  ((PRINCE_Type *)PRINCE0_BASE)
  /** Array initializer of PRINCE peripheral base addresses */
  #define PRINCE_BASE_ADDRS                        { PRINCE0_BASE }
  /** Array initializer of PRINCE peripheral base pointers */
  #define PRINCE_BASE_PTRS                         { PRINCE0 }
#endif

/*!
 * @}
 */ /* end of group PRINCE_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- PUF Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup PUF_Peripheral_Access_Layer PUF Peripheral Access Layer
 * @{
 */

/** PUF - Register Layout Typedef */
typedef struct {
  __IO uint32_t CR;                                /**< Control, offset: 0x0 */
  __I  uint32_t ORR;                               /**< Operation Result, offset: 0x4 */
  __IO uint32_t SR;                                /**< Status, offset: 0x8 */
  __I  uint32_t AR;                                /**< Allow, offset: 0xC */
  __IO uint32_t IER;                               /**< Interrupt Enable, offset: 0x10 */
  __IO uint32_t IMR;                               /**< Interrupt Mask, offset: 0x14 */
  __IO uint32_t ISR;                               /**< Interrupt Status, offset: 0x18 */
       uint8_t RESERVED_0[4];
  __IO uint32_t KEY_DEST;                          /**< Key Destination, offset: 0x20 */
       uint8_t RESERVED_1[124];
  __O  uint32_t DIR;                               /**< Data Input, offset: 0xA0 */
       uint8_t RESERVED_2[4];
  __I  uint32_t DOR;                               /**< Data Output, offset: 0xA8 */
       uint8_t RESERVED_3[20];
  __IO uint32_t MISC;                              /**< Miscellaneous, offset: 0xC0 */
       uint8_t RESERVED_4[12];
  __IO uint32_t IF_SR;                             /**< Interface Status, offset: 0xD0 */
       uint8_t RESERVED_5[8];
  __I  uint32_t PSR;                               /**< PUF Score, offset: 0xDC */
  __I  uint32_t HW_RUC0;                           /**< Hardware Restrict User Context 0, offset: 0xE0 */
  __I  uint32_t HW_RUC1;                           /**< Hardware Restrict User Context 1, offset: 0xE4 */
       uint8_t RESERVED_6[12];
  __I  uint32_t HW_INFO;                           /**< Hardware Information, offset: 0xF4 */
  __I  uint32_t HW_ID;                             /**< Hardware Identifier, offset: 0xF8 */
  __I  uint32_t HW_VER;                            /**< Hardware Version, offset: 0xFC */
  __IO uint32_t CONFIG;                            /**< PUF command blocking configuration, offset: 0x100 */
  __IO uint32_t SEC_LOCK;                          /**< Lock the security level of PUF block until key generate, wrap or unwrap operation is completed., offset: 0x104 */
  __IO uint32_t APP_CTX_MASK;                      /**< Application defined context mask, offset: 0x108 */
       uint8_t RESERVED_7[500];
  __IO uint32_t SRAM_CFG;                          /**< SRAM Configuration, offset: 0x300 */
  __I  uint32_t SRAM_STATUS;                       /**< Status, offset: 0x304 */
       uint8_t RESERVED_8[208];
  __O  uint32_t SRAM_INT_CLR_ENABLE;               /**< Interrupt Enable Clear, offset: 0x3D8 */
  __O  uint32_t SRAM_INT_SET_ENABLE;               /**< Interrupt Enable Set, offset: 0x3DC */
  __I  uint32_t SRAM_INT_STATUS;                   /**< Interrupt Status, offset: 0x3E0 */
  __I  uint32_t SRAM_INT_ENABLE;                   /**< Interrupt Enable, offset: 0x3E4 */
  __O  uint32_t SRAM_INT_CLR_STATUS;               /**< Interrupt Status Clear, offset: 0x3E8 */
  __O  uint32_t SRAM_INT_SET_STATUS;               /**< Interrupt Status set, offset: 0x3EC */
} PUF_Type;

/* ----------------------------------------------------------------------------
   -- PUF Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup PUF_Register_Masks PUF Register Masks
 * @{
 */

/*! @name CR - Control */
/*! @{ */

#define PUF_CR_ZEROIZE_MASK                      (0x1U)
#define PUF_CR_ZEROIZE_SHIFT                     (0U)
/*! ZEROIZE - Begin Zeroize operation
 */
#define PUF_CR_ZEROIZE(x)                        (((uint32_t)(((uint32_t)(x)) << PUF_CR_ZEROIZE_SHIFT)) & PUF_CR_ZEROIZE_MASK)

#define PUF_CR_ENROLL_MASK                       (0x2U)
#define PUF_CR_ENROLL_SHIFT                      (1U)
/*! ENROLL - Begin Enroll operation
 */
#define PUF_CR_ENROLL(x)                         (((uint32_t)(((uint32_t)(x)) << PUF_CR_ENROLL_SHIFT)) & PUF_CR_ENROLL_MASK)

#define PUF_CR_START_MASK                        (0x4U)
#define PUF_CR_START_SHIFT                       (2U)
/*! START - Begin Start operation
 */
#define PUF_CR_START(x)                          (((uint32_t)(((uint32_t)(x)) << PUF_CR_START_SHIFT)) & PUF_CR_START_MASK)

#define PUF_CR_STOP_MASK                         (0x20U)
#define PUF_CR_STOP_SHIFT                        (5U)
/*! STOP - Begin Stop operation
 */
#define PUF_CR_STOP(x)                           (((uint32_t)(((uint32_t)(x)) << PUF_CR_STOP_SHIFT)) & PUF_CR_STOP_MASK)

#define PUF_CR_GET_KEY_MASK                      (0x40U)
#define PUF_CR_GET_KEY_SHIFT                     (6U)
/*! GET_KEY - Begin Get Key operation
 */
#define PUF_CR_GET_KEY(x)                        (((uint32_t)(((uint32_t)(x)) << PUF_CR_GET_KEY_SHIFT)) & PUF_CR_GET_KEY_MASK)

#define PUF_CR_UNWRAP_MASK                       (0x80U)
#define PUF_CR_UNWRAP_SHIFT                      (7U)
/*! UNWRAP - Begin Unwrap operation
 */
#define PUF_CR_UNWRAP(x)                         (((uint32_t)(((uint32_t)(x)) << PUF_CR_UNWRAP_SHIFT)) & PUF_CR_UNWRAP_MASK)

#define PUF_CR_WRAP_GENERATED_RANDOM_MASK        (0x100U)
#define PUF_CR_WRAP_GENERATED_RANDOM_SHIFT       (8U)
/*! WRAP_GENERATED_RANDOM - Begin Wrap Generated Random operation
 */
#define PUF_CR_WRAP_GENERATED_RANDOM(x)          (((uint32_t)(((uint32_t)(x)) << PUF_CR_WRAP_GENERATED_RANDOM_SHIFT)) & PUF_CR_WRAP_GENERATED_RANDOM_MASK)

#define PUF_CR_WRAP_MASK                         (0x200U)
#define PUF_CR_WRAP_SHIFT                        (9U)
/*! WRAP - Begin Wrap operation
 */
#define PUF_CR_WRAP(x)                           (((uint32_t)(((uint32_t)(x)) << PUF_CR_WRAP_SHIFT)) & PUF_CR_WRAP_MASK)

#define PUF_CR_GENERATE_RANDOM_MASK              (0x8000U)
#define PUF_CR_GENERATE_RANDOM_SHIFT             (15U)
/*! GENERATE_RANDOM - Begin Generate Random operation
 */
#define PUF_CR_GENERATE_RANDOM(x)                (((uint32_t)(((uint32_t)(x)) << PUF_CR_GENERATE_RANDOM_SHIFT)) & PUF_CR_GENERATE_RANDOM_MASK)

#define PUF_CR_TEST_PUF_MASK                     (0x80000000U)
#define PUF_CR_TEST_PUF_SHIFT                    (31U)
/*! TEST_PUF - Begin Test PUF operation
 */
#define PUF_CR_TEST_PUF(x)                       (((uint32_t)(((uint32_t)(x)) << PUF_CR_TEST_PUF_SHIFT)) & PUF_CR_TEST_PUF_MASK)
/*! @} */

/*! @name ORR - Operation Result */
/*! @{ */

#define PUF_ORR_RESULT_CODE_MASK                 (0xFFU)
#define PUF_ORR_RESULT_CODE_SHIFT                (0U)
/*! RESULT_CODE - Result code of last operation
 *  0b00000000..Last operation was successful or operation is in progress.
 *  0b11110000..Provided AC is not for the current product/version.
 *  0b11110001..AC in the second phase is not for the current product/version.
 *  0b11110010..Provided AC is corrupted.
 *  0b11110011..AC in the second phase is corrupted.
 *  0b11110100..Authentication of the provided AC failed.
 *  0b11110101..Authentication of the provided AC failed in the second phase.
 *  0b11110110..SRAM PUF quality verification fails.
 *  0b11110111..Incorrect or unsupported context is provided.
 *  0b11111000..A data destination was set that is not allowed according to other settings and the current PUF state.
 *  0b11111111..PUF SRAM access has failed.
 */
#define PUF_ORR_RESULT_CODE(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_ORR_RESULT_CODE_SHIFT)) & PUF_ORR_RESULT_CODE_MASK)

#define PUF_ORR_LAST_OPERATION_MASK              (0xFF000000U)
#define PUF_ORR_LAST_OPERATION_SHIFT             (24U)
/*! LAST_OPERATION - Number of last operation
 *  0b00000000..Operation is in progress.
 *  0b00000001..Last operation was Enroll.
 *  0b00000010..Last operation was Start.
 *  0b00000101..Last operation was Stop.
 *  0b00000110..Last operation was Get Key.
 *  0b00000111..Last operation was Unwrap.
 *  0b00001000..Last operation was Wrap Generated Random.
 *  0b00001001..Last operation was Wrap.
 *  0b00001111..Last operation was Generate Random.
 *  0b00011110..Last operation was Test Memory.
 *  0b00011111..Last operation was Test PUF.
 *  0b00100000..Last operation was Initialization.
 *  0b00101111..Last operation was Zeroize.
 */
#define PUF_ORR_LAST_OPERATION(x)                (((uint32_t)(((uint32_t)(x)) << PUF_ORR_LAST_OPERATION_SHIFT)) & PUF_ORR_LAST_OPERATION_MASK)
/*! @} */

/*! @name SR - Status */
/*! @{ */

#define PUF_SR_BUSY_MASK                         (0x1U)
#define PUF_SR_BUSY_SHIFT                        (0U)
/*! BUSY - Operation is in progress
 */
#define PUF_SR_BUSY(x)                           (((uint32_t)(((uint32_t)(x)) << PUF_SR_BUSY_SHIFT)) & PUF_SR_BUSY_MASK)

#define PUF_SR_OK_MASK                           (0x2U)
#define PUF_SR_OK_SHIFT                          (1U)
/*! OK - Last operation was successful
 */
#define PUF_SR_OK(x)                             (((uint32_t)(((uint32_t)(x)) << PUF_SR_OK_SHIFT)) & PUF_SR_OK_MASK)

#define PUF_SR_ERROR_MASK                        (0x4U)
#define PUF_SR_ERROR_SHIFT                       (2U)
/*! ERROR - Last operation failed
 */
#define PUF_SR_ERROR(x)                          (((uint32_t)(((uint32_t)(x)) << PUF_SR_ERROR_SHIFT)) & PUF_SR_ERROR_MASK)

#define PUF_SR_ZEROIZED_MASK                     (0x8U)
#define PUF_SR_ZEROIZED_SHIFT                    (3U)
/*! ZEROIZED - Zeroized or Locked state
 */
#define PUF_SR_ZEROIZED(x)                       (((uint32_t)(((uint32_t)(x)) << PUF_SR_ZEROIZED_SHIFT)) & PUF_SR_ZEROIZED_MASK)

#define PUF_SR_REJECTED_MASK                     (0x10U)
#define PUF_SR_REJECTED_SHIFT                    (4U)
/*! REJECTED - Operation rejected
 */
#define PUF_SR_REJECTED(x)                       (((uint32_t)(((uint32_t)(x)) << PUF_SR_REJECTED_SHIFT)) & PUF_SR_REJECTED_MASK)

#define PUF_SR_DI_REQUEST_MASK                   (0x20U)
#define PUF_SR_DI_REQUEST_SHIFT                  (5U)
/*! DI_REQUEST - Request for data in transfer via the DIR register
 */
#define PUF_SR_DI_REQUEST(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_SR_DI_REQUEST_SHIFT)) & PUF_SR_DI_REQUEST_MASK)

#define PUF_SR_DO_REQUEST_MASK                   (0x40U)
#define PUF_SR_DO_REQUEST_SHIFT                  (6U)
/*! DO_REQUEST - Request for data out transfer via the DOR register
 */
#define PUF_SR_DO_REQUEST(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_SR_DO_REQUEST_SHIFT)) & PUF_SR_DO_REQUEST_MASK)
/*! @} */

/*! @name AR - Allow */
/*! @{ */

#define PUF_AR_ALLOW_ENROLL_MASK                 (0x2U)
#define PUF_AR_ALLOW_ENROLL_SHIFT                (1U)
/*! ALLOW_ENROLL - Enroll operation
 *  0b0..Enroll operation is not allowed
 *  0b1..Enroll operation is allowed
 */
#define PUF_AR_ALLOW_ENROLL(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_ENROLL_SHIFT)) & PUF_AR_ALLOW_ENROLL_MASK)

#define PUF_AR_ALLOW_START_MASK                  (0x4U)
#define PUF_AR_ALLOW_START_SHIFT                 (2U)
/*! ALLOW_START - Start operation
 *  0b0..Start operation is not allowed
 *  0b1..Start operation is allowed
 */
#define PUF_AR_ALLOW_START(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_START_SHIFT)) & PUF_AR_ALLOW_START_MASK)

#define PUF_AR_ALLOW_STOP_MASK                   (0x20U)
#define PUF_AR_ALLOW_STOP_SHIFT                  (5U)
/*! ALLOW_STOP - Stop operation
 *  0b1..Stop operation is allowed
 *  0b0..Stop operation is not allowed
 */
#define PUF_AR_ALLOW_STOP(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_STOP_SHIFT)) & PUF_AR_ALLOW_STOP_MASK)

#define PUF_AR_ALLOW_GET_KEY_MASK                (0x40U)
#define PUF_AR_ALLOW_GET_KEY_SHIFT               (6U)
/*! ALLOW_GET_KEY - Get Key operation
 *  0b0..Get Key operation is not allowed
 *  0b1..Get Key operation is allowed
 */
#define PUF_AR_ALLOW_GET_KEY(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_GET_KEY_SHIFT)) & PUF_AR_ALLOW_GET_KEY_MASK)

#define PUF_AR_ALLOW_UNWRAP_MASK                 (0x80U)
#define PUF_AR_ALLOW_UNWRAP_SHIFT                (7U)
/*! ALLOW_UNWRAP - Unwrap operation
 *  0b0..Unwrap operation is not allowed
 *  0b1..Unwrap operation is allowed
 */
#define PUF_AR_ALLOW_UNWRAP(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_UNWRAP_SHIFT)) & PUF_AR_ALLOW_UNWRAP_MASK)

#define PUF_AR_ALLOW_WRAP_GENERATED_RANDOM_MASK  (0x100U)
#define PUF_AR_ALLOW_WRAP_GENERATED_RANDOM_SHIFT (8U)
/*! ALLOW_WRAP_GENERATED_RANDOM - Wrap Generated Random operation
 *  0b0..Wrap Generated Random operation is not allowed
 *  0b1..Wrap Generated Random operation is allowed
 */
#define PUF_AR_ALLOW_WRAP_GENERATED_RANDOM(x)    (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_WRAP_GENERATED_RANDOM_SHIFT)) & PUF_AR_ALLOW_WRAP_GENERATED_RANDOM_MASK)

#define PUF_AR_ALLOW_WRAP_MASK                   (0x200U)
#define PUF_AR_ALLOW_WRAP_SHIFT                  (9U)
/*! ALLOW_WRAP - Wrap operation
 *  0b0..Wrap operation is not allowed
 *  0b1..Wrap operation is allowed
 */
#define PUF_AR_ALLOW_WRAP(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_WRAP_SHIFT)) & PUF_AR_ALLOW_WRAP_MASK)

#define PUF_AR_ALLOW_GENERATE_RANDOM_MASK        (0x8000U)
#define PUF_AR_ALLOW_GENERATE_RANDOM_SHIFT       (15U)
/*! ALLOW_GENERATE_RANDOM - Generate Random operation
 *  0b0..Generate Random operation is not allowed
 *  0b1..Generate Random operation is allowed
 */
#define PUF_AR_ALLOW_GENERATE_RANDOM(x)          (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_GENERATE_RANDOM_SHIFT)) & PUF_AR_ALLOW_GENERATE_RANDOM_MASK)

#define PUF_AR_ALLOW_TEST_PUF_MASK               (0x80000000U)
#define PUF_AR_ALLOW_TEST_PUF_SHIFT              (31U)
/*! ALLOW_TEST_PUF - Test PUF operation
 *  0b0..Test PUF operation is not allowed
 *  0b1..Test PUF operation is allowed
 */
#define PUF_AR_ALLOW_TEST_PUF(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_TEST_PUF_SHIFT)) & PUF_AR_ALLOW_TEST_PUF_MASK)
/*! @} */

/*! @name IER - Interrupt Enable */
/*! @{ */

#define PUF_IER_INT_EN_MASK                      (0x1U)
#define PUF_IER_INT_EN_SHIFT                     (0U)
/*! INT_EN - Interrupt enable
 *  0b0..Disables all PUF interrupts
 *  0b1..Enables all PUF interrupts that are enabled in the Interrupt Mask register
 */
#define PUF_IER_INT_EN(x)                        (((uint32_t)(((uint32_t)(x)) << PUF_IER_INT_EN_SHIFT)) & PUF_IER_INT_EN_MASK)
/*! @} */

/*! @name IMR - Interrupt Mask */
/*! @{ */

#define PUF_IMR_INT_EN_BUSY_MASK                 (0x1U)
#define PUF_IMR_INT_EN_BUSY_SHIFT                (0U)
/*! INT_EN_BUSY - Enable busy interrupt
 */
#define PUF_IMR_INT_EN_BUSY(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_BUSY_SHIFT)) & PUF_IMR_INT_EN_BUSY_MASK)

#define PUF_IMR_INT_EN_OK_MASK                   (0x2U)
#define PUF_IMR_INT_EN_OK_SHIFT                  (1U)
/*! INT_EN_OK - Enable ok interrupt
 */
#define PUF_IMR_INT_EN_OK(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_OK_SHIFT)) & PUF_IMR_INT_EN_OK_MASK)

#define PUF_IMR_INT_EN_ERROR_MASK                (0x4U)
#define PUF_IMR_INT_EN_ERROR_SHIFT               (2U)
/*! INT_EN_ERROR - Enable error interrupt
 */
#define PUF_IMR_INT_EN_ERROR(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_ERROR_SHIFT)) & PUF_IMR_INT_EN_ERROR_MASK)

#define PUF_IMR_INT_EN_ZEROIZED_MASK             (0x8U)
#define PUF_IMR_INT_EN_ZEROIZED_SHIFT            (3U)
/*! INT_EN_ZEROIZED - Enable zeroized interrupt
 */
#define PUF_IMR_INT_EN_ZEROIZED(x)               (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_ZEROIZED_SHIFT)) & PUF_IMR_INT_EN_ZEROIZED_MASK)

#define PUF_IMR_INT_EN_REJECTED_MASK             (0x10U)
#define PUF_IMR_INT_EN_REJECTED_SHIFT            (4U)
/*! INT_EN_REJECTED - Enable rejected interrupt
 */
#define PUF_IMR_INT_EN_REJECTED(x)               (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_REJECTED_SHIFT)) & PUF_IMR_INT_EN_REJECTED_MASK)

#define PUF_IMR_INT_EN_DI_REQUEST_MASK           (0x20U)
#define PUF_IMR_INT_EN_DI_REQUEST_SHIFT          (5U)
/*! INT_EN_DI_REQUEST - Enable data in request interrupt
 */
#define PUF_IMR_INT_EN_DI_REQUEST(x)             (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_DI_REQUEST_SHIFT)) & PUF_IMR_INT_EN_DI_REQUEST_MASK)

#define PUF_IMR_INT_EN_DO_REQUEST_MASK           (0x40U)
#define PUF_IMR_INT_EN_DO_REQUEST_SHIFT          (6U)
/*! INT_EN_DO_REQUEST - Enable data out request interrupt
 */
#define PUF_IMR_INT_EN_DO_REQUEST(x)             (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_DO_REQUEST_SHIFT)) & PUF_IMR_INT_EN_DO_REQUEST_MASK)
/*! @} */

/*! @name ISR - Interrupt Status */
/*! @{ */

#define PUF_ISR_INT_BUSY_MASK                    (0x1U)
#define PUF_ISR_INT_BUSY_SHIFT                   (0U)
/*! INT_BUSY - Negative edge occurred on busy, which means that an operation has completed
 */
#define PUF_ISR_INT_BUSY(x)                      (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_BUSY_SHIFT)) & PUF_ISR_INT_BUSY_MASK)

#define PUF_ISR_INT_OK_MASK                      (0x2U)
#define PUF_ISR_INT_OK_SHIFT                     (1U)
/*! INT_OK - Positive edge occurred on ok, which means that an operation successfully completed
 */
#define PUF_ISR_INT_OK(x)                        (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_OK_SHIFT)) & PUF_ISR_INT_OK_MASK)

#define PUF_ISR_INT_ERROR_MASK                   (0x4U)
#define PUF_ISR_INT_ERROR_SHIFT                  (2U)
/*! INT_ERROR - Positive edge occurred on error, which means that an operation has failed
 */
#define PUF_ISR_INT_ERROR(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_ERROR_SHIFT)) & PUF_ISR_INT_ERROR_MASK)

#define PUF_ISR_INT_ZEROIZED_MASK                (0x8U)
#define PUF_ISR_INT_ZEROIZED_SHIFT               (3U)
/*! INT_ZEROIZED - Positive edge occurred on zeroized, which means that PUF has moved to the Zeroized or Locked state
 */
#define PUF_ISR_INT_ZEROIZED(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_ZEROIZED_SHIFT)) & PUF_ISR_INT_ZEROIZED_MASK)

#define PUF_ISR_INT_REJECTED_MASK                (0x10U)
#define PUF_ISR_INT_REJECTED_SHIFT               (4U)
/*! INT_REJECTED - Positive edge occurred on rejected, which means that a command was rejected
 */
#define PUF_ISR_INT_REJECTED(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_REJECTED_SHIFT)) & PUF_ISR_INT_REJECTED_MASK)

#define PUF_ISR_INT_DI_REQUEST_MASK              (0x20U)
#define PUF_ISR_INT_DI_REQUEST_SHIFT             (5U)
/*! INT_DI_REQUEST - Positive edge occurred on di_request, which means that a data in transfer is requested via the DIR register
 */
#define PUF_ISR_INT_DI_REQUEST(x)                (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_DI_REQUEST_SHIFT)) & PUF_ISR_INT_DI_REQUEST_MASK)

#define PUF_ISR_INT_DO_REQUEST_MASK              (0x40U)
#define PUF_ISR_INT_DO_REQUEST_SHIFT             (6U)
/*! INT_DO_REQUEST - Positive edge occurred on do_request, which means that a data out transfer is requested via the DOR register
 */
#define PUF_ISR_INT_DO_REQUEST(x)                (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_DO_REQUEST_SHIFT)) & PUF_ISR_INT_DO_REQUEST_MASK)
/*! @} */

/*! @name KEY_DEST - Key Destination */
/*! @{ */

#define PUF_KEY_DEST_DEST_DOR_MASK               (0x1U)
#define PUF_KEY_DEST_DEST_DOR_SHIFT              (0U)
/*! DEST_DOR - Key will be made available via the DOR register
 */
#define PUF_KEY_DEST_DEST_DOR(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_KEY_DEST_DEST_DOR_SHIFT)) & PUF_KEY_DEST_DEST_DOR_MASK)

#define PUF_KEY_DEST_DEST_KO_MASK                (0x2U)
#define PUF_KEY_DEST_DEST_KO_SHIFT               (1U)
/*! DEST_KO - Key will be made available via the KO interface
 */
#define PUF_KEY_DEST_DEST_KO(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_KEY_DEST_DEST_KO_SHIFT)) & PUF_KEY_DEST_DEST_KO_MASK)
/*! @} */

/*! @name DIR - Data Input */
/*! @{ */

#define PUF_DIR_DI_MASK                          (0xFFFFFFFFU)
#define PUF_DIR_DI_SHIFT                         (0U)
/*! DI - Input data to PUF
 */
#define PUF_DIR_DI(x)                            (((uint32_t)(((uint32_t)(x)) << PUF_DIR_DI_SHIFT)) & PUF_DIR_DI_MASK)
/*! @} */

/*! @name DOR - Data Output */
/*! @{ */

#define PUF_DOR_DO_MASK                          (0xFFFFFFFFU)
#define PUF_DOR_DO_SHIFT                         (0U)
/*! DO - Output data from PUF
 */
#define PUF_DOR_DO(x)                            (((uint32_t)(((uint32_t)(x)) << PUF_DOR_DO_SHIFT)) & PUF_DOR_DO_MASK)
/*! @} */

/*! @name MISC - Miscellaneous */
/*! @{ */

#define PUF_MISC_DATA_ENDIANNESS_MASK            (0x1U)
#define PUF_MISC_DATA_ENDIANNESS_SHIFT           (0U)
/*! DATA_ENDIANNESS - Defines the endianness of data in DIR and DOR:
 *  0b0..Little endian
 *  0b1..Big endian (default)
 */
#define PUF_MISC_DATA_ENDIANNESS(x)              (((uint32_t)(((uint32_t)(x)) << PUF_MISC_DATA_ENDIANNESS_SHIFT)) & PUF_MISC_DATA_ENDIANNESS_MASK)
/*! @} */

/*! @name IF_SR - Interface Status */
/*! @{ */

#define PUF_IF_SR_APB_ERROR_MASK                 (0x1U)
#define PUF_IF_SR_APB_ERROR_SHIFT                (0U)
/*! APB_ERROR - An APB error occurred
 */
#define PUF_IF_SR_APB_ERROR(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_IF_SR_APB_ERROR_SHIFT)) & PUF_IF_SR_APB_ERROR_MASK)
/*! @} */

/*! @name PSR - PUF Score */
/*! @{ */

#define PUF_PSR_PUF_SCORE_MASK                   (0xFU)
#define PUF_PSR_PUF_SCORE_SHIFT                  (0U)
/*! PUF_SCORE - PUF score obtained during the last Test PUF, Enroll or Start operation
 */
#define PUF_PSR_PUF_SCORE(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_PSR_PUF_SCORE_SHIFT)) & PUF_PSR_PUF_SCORE_MASK)
/*! @} */

/*! @name HW_RUC0 - Hardware Restrict User Context 0 */
/*! @{ */

#define PUF_HW_RUC0_LC_STATE_MASK                (0xFFU)
#define PUF_HW_RUC0_LC_STATE_SHIFT               (0U)
/*! LC_STATE - Life cycle state based restrictions
 *  0b00000011..OEM Develop
 *  0b00000111..OEM Develop 2
 *  0b00001111..OEM In-field
 *  0b00011111..OEM Field return
 *  0b00111111..NXP Field Return/Failure Analysis
 *  0b11001111..In-field Locked
 *  0b11111111..Bricked
 */
#define PUF_HW_RUC0_LC_STATE(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_LC_STATE_SHIFT)) & PUF_HW_RUC0_LC_STATE_MASK)

#define PUF_HW_RUC0_BOOT_STATE_MASK              (0xFFFF00U)
#define PUF_HW_RUC0_BOOT_STATE_SHIFT             (8U)
/*! BOOT_STATE - Temporal boot state
 */
#define PUF_HW_RUC0_BOOT_STATE(x)                (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_BOOT_STATE_SHIFT)) & PUF_HW_RUC0_BOOT_STATE_MASK)

#define PUF_HW_RUC0_CPU0_DEBUG_MASK              (0x1000000U)
#define PUF_HW_RUC0_CPU0_DEBUG_SHIFT             (24U)
/*! CPU0_DEBUG - Disable key access when debugger is attached to CPU0 after power-up
 */
#define PUF_HW_RUC0_CPU0_DEBUG(x)                (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_CPU0_DEBUG_SHIFT)) & PUF_HW_RUC0_CPU0_DEBUG_MASK)

#define PUF_HW_RUC0_RUC026_MASK                  (0x4000000U)
#define PUF_HW_RUC0_RUC026_SHIFT                 (26U)
/*! RUC026 - Restrict user context 0
 *  0b0..Bit can be used
 *  0b1..Bit cannot be used
 */
#define PUF_HW_RUC0_RUC026(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_RUC026_SHIFT)) & PUF_HW_RUC0_RUC026_MASK)

#define PUF_HW_RUC0_ACCESS_LEVEL_MASK            (0xF0000000U)
#define PUF_HW_RUC0_ACCESS_LEVEL_SHIFT           (28U)
/*! ACCESS_LEVEL - Restrict the key access based on TrustZone security level
 */
#define PUF_HW_RUC0_ACCESS_LEVEL(x)              (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_ACCESS_LEVEL_SHIFT)) & PUF_HW_RUC0_ACCESS_LEVEL_MASK)
/*! @} */

/*! @name HW_RUC1 - Hardware Restrict User Context 1 */
/*! @{ */

#define PUF_HW_RUC1_APP_CTX_MASK                 (0xFFFFFFFFU)
#define PUF_HW_RUC1_APP_CTX_SHIFT                (0U)
/*! APP_CTX - Application customizable context
 */
#define PUF_HW_RUC1_APP_CTX(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC1_APP_CTX_SHIFT)) & PUF_HW_RUC1_APP_CTX_MASK)
/*! @} */

/*! @name HW_INFO - Hardware Information */
/*! @{ */

#define PUF_HW_INFO_CONFIG_BIST_MASK             (0x400000U)
#define PUF_HW_INFO_CONFIG_BIST_SHIFT            (22U)
/*! CONFIG_BIST - BIST configuration
 *  0b0..BIST is not included
 *  0b1..BIST is included
 */
#define PUF_HW_INFO_CONFIG_BIST(x)               (((uint32_t)(((uint32_t)(x)) << PUF_HW_INFO_CONFIG_BIST_SHIFT)) & PUF_HW_INFO_CONFIG_BIST_MASK)

#define PUF_HW_INFO_CONFIG_WRAP_MASK             (0x1000000U)
#define PUF_HW_INFO_CONFIG_WRAP_SHIFT            (24U)
/*! CONFIG_WRAP - Wrap configuration
 *  0b0..Wrap is not included
 *  0b1..Wrap is included
 */
#define PUF_HW_INFO_CONFIG_WRAP(x)               (((uint32_t)(((uint32_t)(x)) << PUF_HW_INFO_CONFIG_WRAP_SHIFT)) & PUF_HW_INFO_CONFIG_WRAP_MASK)

#define PUF_HW_INFO_CONFIG_TYPE_MASK             (0xF0000000U)
#define PUF_HW_INFO_CONFIG_TYPE_SHIFT            (28U)
/*! CONFIG_TYPE - PUF configuration
 *  0b0001..PUF configuration is Safe.
 *  0b0010..PUF configuration is Plus.
 */
#define PUF_HW_INFO_CONFIG_TYPE(x)               (((uint32_t)(((uint32_t)(x)) << PUF_HW_INFO_CONFIG_TYPE_SHIFT)) & PUF_HW_INFO_CONFIG_TYPE_MASK)
/*! @} */

/*! @name HW_ID - Hardware Identifier */
/*! @{ */

#define PUF_HW_ID_HW_ID_MASK                     (0xFFFFFFFFU)
#define PUF_HW_ID_HW_ID_SHIFT                    (0U)
/*! HW_ID - Hardware identifier
 */
#define PUF_HW_ID_HW_ID(x)                       (((uint32_t)(((uint32_t)(x)) << PUF_HW_ID_HW_ID_SHIFT)) & PUF_HW_ID_HW_ID_MASK)
/*! @} */

/*! @name HW_VER - Hardware Version */
/*! @{ */

#define PUF_HW_VER_HW_REV_MASK                   (0xFFU)
#define PUF_HW_VER_HW_REV_SHIFT                  (0U)
/*! HW_REV - Hardware version, patch part
 */
#define PUF_HW_VER_HW_REV(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_HW_VER_HW_REV_SHIFT)) & PUF_HW_VER_HW_REV_MASK)

#define PUF_HW_VER_HW_VERSION_MINOR_MASK         (0xFF00U)
#define PUF_HW_VER_HW_VERSION_MINOR_SHIFT        (8U)
/*! HW_VERSION_MINOR - Hardware version, minor part
 */
#define PUF_HW_VER_HW_VERSION_MINOR(x)           (((uint32_t)(((uint32_t)(x)) << PUF_HW_VER_HW_VERSION_MINOR_SHIFT)) & PUF_HW_VER_HW_VERSION_MINOR_MASK)

#define PUF_HW_VER_HW_VERSION_MAJOR_MASK         (0xFF0000U)
#define PUF_HW_VER_HW_VERSION_MAJOR_SHIFT        (16U)
/*! HW_VERSION_MAJOR - Hardware version, major part
 */
#define PUF_HW_VER_HW_VERSION_MAJOR(x)           (((uint32_t)(((uint32_t)(x)) << PUF_HW_VER_HW_VERSION_MAJOR_SHIFT)) & PUF_HW_VER_HW_VERSION_MAJOR_MASK)
/*! @} */

/*! @name CONFIG - PUF command blocking configuration */
/*! @{ */

#define PUF_CONFIG_DIS_PUF_ENROLL_MASK           (0x2U)
#define PUF_CONFIG_DIS_PUF_ENROLL_SHIFT          (1U)
/*! DIS_PUF_ENROLL - Disable PUF enroll command
 */
#define PUF_CONFIG_DIS_PUF_ENROLL(x)             (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_ENROLL_SHIFT)) & PUF_CONFIG_DIS_PUF_ENROLL_MASK)

#define PUF_CONFIG_DIS_PUF_START_MASK            (0x4U)
#define PUF_CONFIG_DIS_PUF_START_SHIFT           (2U)
/*! DIS_PUF_START - Disable PUF start command
 */
#define PUF_CONFIG_DIS_PUF_START(x)              (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_START_SHIFT)) & PUF_CONFIG_DIS_PUF_START_MASK)

#define PUF_CONFIG_DIS_PUF_STOP_MASK             (0x20U)
#define PUF_CONFIG_DIS_PUF_STOP_SHIFT            (5U)
/*! DIS_PUF_STOP - Disable PUF stop command
 */
#define PUF_CONFIG_DIS_PUF_STOP(x)               (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_STOP_SHIFT)) & PUF_CONFIG_DIS_PUF_STOP_MASK)

#define PUF_CONFIG_DIS_PUF_GET_KEY_MASK          (0x40U)
#define PUF_CONFIG_DIS_PUF_GET_KEY_SHIFT         (6U)
/*! DIS_PUF_GET_KEY - Disable PUF get key command
 */
#define PUF_CONFIG_DIS_PUF_GET_KEY(x)            (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_GET_KEY_SHIFT)) & PUF_CONFIG_DIS_PUF_GET_KEY_MASK)

#define PUF_CONFIG_DIS_PUF_UNWRAP_KEY_MASK       (0x80U)
#define PUF_CONFIG_DIS_PUF_UNWRAP_KEY_SHIFT      (7U)
/*! DIS_PUF_UNWRAP_KEY - Disable PUF unwrap key command
 */
#define PUF_CONFIG_DIS_PUF_UNWRAP_KEY(x)         (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_UNWRAP_KEY_SHIFT)) & PUF_CONFIG_DIS_PUF_UNWRAP_KEY_MASK)

#define PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY_MASK     (0x100U)
#define PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY_SHIFT    (8U)
/*! DIS_PUF_GEN_WRAP_KEY - Disable PUF generate and wrap key command
 */
#define PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY(x)       (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY_SHIFT)) & PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY_MASK)

#define PUF_CONFIG_DIS_PUF_WRAP_KEY_MASK         (0x200U)
#define PUF_CONFIG_DIS_PUF_WRAP_KEY_SHIFT        (9U)
/*! DIS_PUF_WRAP_KEY - Disable PUF wrap key command
 */
#define PUF_CONFIG_DIS_PUF_WRAP_KEY(x)           (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_WRAP_KEY_SHIFT)) & PUF_CONFIG_DIS_PUF_WRAP_KEY_MASK)

#define PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER_MASK (0x8000U)
#define PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER_SHIFT (15U)
/*! DIS_PUF_GEN_RANDOM_NUMBER - Disable PUF generate and wrap key command
 */
#define PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER(x)  (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER_SHIFT)) & PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER_MASK)

#define PUF_CONFIG_DIS_PUF_TEST_MASK             (0x80000000U)
#define PUF_CONFIG_DIS_PUF_TEST_SHIFT            (31U)
/*! DIS_PUF_TEST - Disable PUF test command
 */
#define PUF_CONFIG_DIS_PUF_TEST(x)               (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_TEST_SHIFT)) & PUF_CONFIG_DIS_PUF_TEST_MASK)
/*! @} */

/*! @name SEC_LOCK - Lock the security level of PUF block until key generate, wrap or unwrap operation is completed. */
/*! @{ */

#define PUF_SEC_LOCK_SEC_LEVEL_MASK              (0x3U)
#define PUF_SEC_LOCK_SEC_LEVEL_SHIFT             (0U)
/*! SEC_LEVEL - Disable PUF enroll command
 *  0b00..Nonsecure user
 *  0b00..Nonsecure privilege
 *  0b00..Secure user
 *  0b00..Secure privilege
 */
#define PUF_SEC_LOCK_SEC_LEVEL(x)                (((uint32_t)(((uint32_t)(x)) << PUF_SEC_LOCK_SEC_LEVEL_SHIFT)) & PUF_SEC_LOCK_SEC_LEVEL_MASK)

#define PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL_MASK    (0xCU)
#define PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL_SHIFT   (2U)
/*! ANTI_POLE_SEC_LEVEL - Anti-pole of security level
 */
#define PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL(x)      (((uint32_t)(((uint32_t)(x)) << PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL_SHIFT)) & PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL_MASK)

#define PUF_SEC_LOCK_PATTERN_MASK                (0xFFF0U)
#define PUF_SEC_LOCK_PATTERN_SHIFT               (4U)
/*! PATTERN - Pattern
 */
#define PUF_SEC_LOCK_PATTERN(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_SEC_LOCK_PATTERN_SHIFT)) & PUF_SEC_LOCK_PATTERN_MASK)
/*! @} */

/*! @name APP_CTX_MASK - Application defined context mask */
/*! @{ */

#define PUF_APP_CTX_MASK_APP_CTX_MASK_MASK       (0xFFFFFFFFU)
#define PUF_APP_CTX_MASK_APP_CTX_MASK_SHIFT      (0U)
/*! APP_CTX_MASK - Application defined context
 */
#define PUF_APP_CTX_MASK_APP_CTX_MASK(x)         (((uint32_t)(((uint32_t)(x)) << PUF_APP_CTX_MASK_APP_CTX_MASK_SHIFT)) & PUF_APP_CTX_MASK_APP_CTX_MASK_MASK)
/*! @} */

/*! @name SRAM_CFG - SRAM Configuration */
/*! @{ */

#define PUF_SRAM_CFG_ENABLE_MASK                 (0x1U)
#define PUF_SRAM_CFG_ENABLE_SHIFT                (0U)
/*! ENABLE - PUF SRAM Controller activation
 *  0b1..Enabled
 *  0b1..Disabled
 */
#define PUF_SRAM_CFG_ENABLE(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CFG_ENABLE_SHIFT)) & PUF_SRAM_CFG_ENABLE_MASK)

#define PUF_SRAM_CFG_CKGATING_MASK               (0x4U)
#define PUF_SRAM_CFG_CKGATING_SHIFT              (2U)
/*! CKGATING - PUF SRAM Clock Gating control
 *  0b1..Enabled
 *  0b1..Disabled
 */
#define PUF_SRAM_CFG_CKGATING(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CFG_CKGATING_SHIFT)) & PUF_SRAM_CFG_CKGATING_MASK)
/*! @} */

/*! @name SRAM_STATUS - Status */
/*! @{ */

#define PUF_SRAM_STATUS_READY_MASK               (0x1U)
#define PUF_SRAM_STATUS_READY_SHIFT              (0U)
/*! READY - PUF SRAM Controller State
 */
#define PUF_SRAM_STATUS_READY(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_STATUS_READY_SHIFT)) & PUF_SRAM_STATUS_READY_MASK)
/*! @} */

/*! @name SRAM_INT_CLR_ENABLE - Interrupt Enable Clear */
/*! @{ */

#define PUF_SRAM_INT_CLR_ENABLE_READY_MASK       (0x1U)
#define PUF_SRAM_INT_CLR_ENABLE_READY_SHIFT      (0U)
/*! READY - READY Interrupt Enable clear
 */
#define PUF_SRAM_INT_CLR_ENABLE_READY(x)         (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_CLR_ENABLE_READY_SHIFT)) & PUF_SRAM_INT_CLR_ENABLE_READY_MASK)

#define PUF_SRAM_INT_CLR_ENABLE_APB_ERR_MASK     (0x2U)
#define PUF_SRAM_INT_CLR_ENABLE_APB_ERR_SHIFT    (1U)
/*! APB_ERR - APB_ERR Interrupt Enable clear
 */
#define PUF_SRAM_INT_CLR_ENABLE_APB_ERR(x)       (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_CLR_ENABLE_APB_ERR_SHIFT)) & PUF_SRAM_INT_CLR_ENABLE_APB_ERR_MASK)
/*! @} */

/*! @name SRAM_INT_SET_ENABLE - Interrupt Enable Set */
/*! @{ */

#define PUF_SRAM_INT_SET_ENABLE_READY_MASK       (0x1U)
#define PUF_SRAM_INT_SET_ENABLE_READY_SHIFT      (0U)
/*! READY - READY Interrupt Enable set
 */
#define PUF_SRAM_INT_SET_ENABLE_READY(x)         (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_SET_ENABLE_READY_SHIFT)) & PUF_SRAM_INT_SET_ENABLE_READY_MASK)

#define PUF_SRAM_INT_SET_ENABLE_APB_ERR_MASK     (0x2U)
#define PUF_SRAM_INT_SET_ENABLE_APB_ERR_SHIFT    (1U)
/*! APB_ERR - APB_ERR Interrupt Enable set
 */
#define PUF_SRAM_INT_SET_ENABLE_APB_ERR(x)       (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_SET_ENABLE_APB_ERR_SHIFT)) & PUF_SRAM_INT_SET_ENABLE_APB_ERR_MASK)
/*! @} */

/*! @name SRAM_INT_STATUS - Interrupt Status */
/*! @{ */

#define PUF_SRAM_INT_STATUS_READY_MASK           (0x1U)
#define PUF_SRAM_INT_STATUS_READY_SHIFT          (0U)
/*! READY - READY Interrupt Status
 */
#define PUF_SRAM_INT_STATUS_READY(x)             (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_STATUS_READY_SHIFT)) & PUF_SRAM_INT_STATUS_READY_MASK)

#define PUF_SRAM_INT_STATUS_APB_ERR_MASK         (0x2U)
#define PUF_SRAM_INT_STATUS_APB_ERR_SHIFT        (1U)
/*! APB_ERR - APB_ERR Interrupt Status
 */
#define PUF_SRAM_INT_STATUS_APB_ERR(x)           (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_STATUS_APB_ERR_SHIFT)) & PUF_SRAM_INT_STATUS_APB_ERR_MASK)
/*! @} */

/*! @name SRAM_INT_ENABLE - Interrupt Enable */
/*! @{ */

#define PUF_SRAM_INT_ENABLE_READY_MASK           (0x1U)
#define PUF_SRAM_INT_ENABLE_READY_SHIFT          (0U)
/*! READY - READY Interrupt Enable
 *  0b1..Enabled
 *  0b1..Disabled
 */
#define PUF_SRAM_INT_ENABLE_READY(x)             (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_ENABLE_READY_SHIFT)) & PUF_SRAM_INT_ENABLE_READY_MASK)

#define PUF_SRAM_INT_ENABLE_SRAM_APB_ERR_MASK    (0x2U)
#define PUF_SRAM_INT_ENABLE_SRAM_APB_ERR_SHIFT   (1U)
/*! SRAM_APB_ERR - APB_ERR Interrupt Enable
 *  0b1..Enabled
 *  0b1..Disabled
 */
#define PUF_SRAM_INT_ENABLE_SRAM_APB_ERR(x)      (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_ENABLE_SRAM_APB_ERR_SHIFT)) & PUF_SRAM_INT_ENABLE_SRAM_APB_ERR_MASK)
/*! @} */

/*! @name SRAM_INT_CLR_STATUS - Interrupt Status Clear */
/*! @{ */

#define PUF_SRAM_INT_CLR_STATUS_READY_MASK       (0x1U)
#define PUF_SRAM_INT_CLR_STATUS_READY_SHIFT      (0U)
/*! READY - READY Interrupt Status clear
 */
#define PUF_SRAM_INT_CLR_STATUS_READY(x)         (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_CLR_STATUS_READY_SHIFT)) & PUF_SRAM_INT_CLR_STATUS_READY_MASK)

#define PUF_SRAM_INT_CLR_STATUS_APB_ERR_MASK     (0x2U)
#define PUF_SRAM_INT_CLR_STATUS_APB_ERR_SHIFT    (1U)
/*! APB_ERR - APB_ERR Interrupt Status Clear
 */
#define PUF_SRAM_INT_CLR_STATUS_APB_ERR(x)       (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_CLR_STATUS_APB_ERR_SHIFT)) & PUF_SRAM_INT_CLR_STATUS_APB_ERR_MASK)
/*! @} */

/*! @name SRAM_INT_SET_STATUS - Interrupt Status set */
/*! @{ */

#define PUF_SRAM_INT_SET_STATUS_READY_MASK       (0x1U)
#define PUF_SRAM_INT_SET_STATUS_READY_SHIFT      (0U)
/*! READY - READY Interrupt Status set
 */
#define PUF_SRAM_INT_SET_STATUS_READY(x)         (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_SET_STATUS_READY_SHIFT)) & PUF_SRAM_INT_SET_STATUS_READY_MASK)

#define PUF_SRAM_INT_SET_STATUS_APB_ERR_MASK     (0x2U)
#define PUF_SRAM_INT_SET_STATUS_APB_ERR_SHIFT    (1U)
/*! APB_ERR - APB_ERR Interrupt Status Set
 */
#define PUF_SRAM_INT_SET_STATUS_APB_ERR(x)       (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_SET_STATUS_APB_ERR_SHIFT)) & PUF_SRAM_INT_SET_STATUS_APB_ERR_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group PUF_Register_Masks */


/* PUF - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral PUF base address 0 */
  #define PUF_BASE_0                              (0x5003A000u)
  /** Peripheral PUF base address 0 */
  #define PUF_BASE_0_NS                           (0x4003A000u)
  /** Peripheral PUF base address 1 */
  #define PUF_BASE_1                              (0x5003B000u)
  /** Peripheral PUF base address 1 */
  #define PUF_BASE_1_NS                           (0x4003B000u)
  /** Peripheral PUF base address 2 */
  #define PUF_BASE_2                              (0x5003C000u)
  /** Peripheral PUF base address 2 */
  #define PUF_BASE_2_NS                           (0x4003C000u)
  /** Peripheral PUF base address 3 */
  #define PUF_BASE_3                              (0x5003D000u)
  /** Peripheral PUF base address 3 */
  #define PUF_BASE_3_NS                           (0x4003D000u)
  /** Peripheral PUF base pointer 0 */
  #define PUF_ALIAS_0                             ((PUF_Type *)PUF_BASE_0)
  /** Peripheral PUF base pointer 0 */
  #define PUF_ALIAS_0_NS                          ((PUF_Type *)PUF_BASE_0_NS)
  /** Peripheral PUF base pointer 1 */
  #define PUF_ALIAS_1                             ((PUF_Type *)PUF_BASE_1)
  /** Peripheral PUF base pointer 1 */
  #define PUF_ALIAS_1_NS                          ((PUF_Type *)PUF_BASE_1_NS)
  /** Peripheral PUF base pointer 2 */
  #define PUF_ALIAS_2                             ((PUF_Type *)PUF_BASE_2)
  /** Peripheral PUF base pointer 2 */
  #define PUF_ALIAS_2_NS                          ((PUF_Type *)PUF_BASE_2_NS)
  /** Peripheral PUF base pointer 3 */
  #define PUF_ALIAS_3                             ((PUF_Type *)PUF_BASE_3)
  /** Peripheral PUF base pointer 3 */
  #define PUF_ALIAS_3_NS                          ((PUF_Type *)PUF_BASE_3_NS)
  /** Array initializer of PUF peripheral base addresses */
  #define PUF_BASE_ADDRS_0                         { PUF_BASE_0 }
  /** Array initializer of PUF peripheral base addresses */
  #define PUF_BASE_ADDRS_1                         { PUF_BASE_1 }
  /** Array initializer of PUF peripheral base addresses */
  #define PUF_BASE_ADDRS_2                         { PUF_BASE_2 }
  /** Array initializer of PUF peripheral base addresses */
  #define PUF_BASE_ADDRS_3                         { PUF_BASE_3 }
  /** Array initializer of PUF peripheral base pointers */
  #define PUF_BASE_PTRS_0                          { PUF_ALIAS_0 }
  /** Array initializer of PUF peripheral base pointers */
  #define PUF_BASE_PTRS_1                          { PUF_ALIAS_1 }
  /** Array initializer of PUF peripheral base pointers */
  #define PUF_BASE_PTRS_2                          { PUF_ALIAS_2 }
  /** Array initializer of PUF peripheral base pointers */
  #define PUF_BASE_PTRS_3                          { PUF_ALIAS_3 }
  /** Array initializer of PUF peripheral base addresses */
  #define PUF_BASE_ADDRS_0_NS                      { PUF_BASE_0_NS }
  /** Array initializer of PUF peripheral base addresses */
  #define PUF_BASE_ADDRS_1_NS                      { PUF_BASE_1_NS }
  /** Array initializer of PUF peripheral base addresses */
  #define PUF_BASE_ADDRS_2_NS                      { PUF_BASE_2_NS }
  /** Array initializer of PUF peripheral base addresses */
  #define PUF_BASE_ADDRS_3_NS                      { PUF_BASE_3_NS }
  /** Array initializer of PUF peripheral base pointers */
  #define PUF_BASE_PTRS_0_NS                       { PUF_ALIAS_0_NS }
  /** Array initializer of PUF peripheral base pointers */
  #define PUF_BASE_PTRS_1_NS                       { PUF_ALIAS_1_NS }
  /** Array initializer of PUF peripheral base pointers */
  #define PUF_BASE_PTRS_2_NS                       { PUF_ALIAS_2_NS }
  /** Array initializer of PUF peripheral base pointers */
  #define PUF_BASE_PTRS_3_NS                       { PUF_ALIAS_3_NS }
#else
  /** Peripheral PUF base address 0 */
  #define PUF_BASE_0                              (0x4003A000u)
  /** Peripheral PUF base address 1 */
  #define PUF_BASE_1                              (0x4003B000u)
  /** Peripheral PUF base address 2 */
  #define PUF_BASE_2                              (0x4003C000u)
  /** Peripheral PUF base address 3 */
  #define PUF_BASE_3                              (0x4003D000u)
  /** Peripheral PUF base pointer 0 */
  #define PUF_ALIAS_0                             ((PUF_Type *)PUF_BASE_0)
  /** Peripheral PUF base pointer 1 */
  #define PUF_ALIAS_1                             ((PUF_Type *)PUF_BASE_1)
  /** Peripheral PUF base pointer 2 */
  #define PUF_ALIAS_2                             ((PUF_Type *)PUF_BASE_2)
  /** Peripheral PUF base pointer 3 */
  #define PUF_ALIAS_3                             ((PUF_Type *)PUF_BASE_3)
  /** Array initializer of PUF peripheral base addresses */
  #define PUF_BASE_ADDRS_0                         { PUF_BASE_0 }
  /** Array initializer of PUF peripheral base addresses */
  #define PUF_BASE_ADDRS_1                         { PUF_BASE_1 }
  /** Array initializer of PUF peripheral base addresses */
  #define PUF_BASE_ADDRS_2                         { PUF_BASE_2 }
  /** Array initializer of PUF peripheral base addresses */
  #define PUF_BASE_ADDRS_3                         { PUF_BASE_3 }
  /** Array initializer of PUF peripheral base pointers */
  #define PUF_BASE_PTRS_0                          { PUF_ALIAS_0 }
  /** Array initializer of PUF peripheral base pointers */
  #define PUF_BASE_PTRS_1                          { PUF_ALIAS_1 }
  /** Array initializer of PUF peripheral base pointers */
  #define PUF_BASE_PTRS_2                          { PUF_ALIAS_2 }
  /** Array initializer of PUF peripheral base pointers */
  #define PUF_BASE_PTRS_3                          { PUF_ALIAS_3 }
#endif
/** Interrupt vectors for the PUF peripheral type */
#define PUF_IRQS                                 { PUF_IRQn }

/*!
 * @}
 */ /* end of group PUF_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- PWM Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup PWM_Peripheral_Access_Layer PWM Peripheral Access Layer
 * @{
 */

/** PWM - Register Layout Typedef */
typedef struct {
  struct {                                         /* offset: 0x0, array step: 0x60 */
    __I  uint16_t CNT;                               /**< Counter Register, array offset: 0x0, array step: 0x60 */
    __IO uint16_t INIT;                              /**< Initial Count Register, array offset: 0x2, array step: 0x60 */
    __IO uint16_t CTRL2;                             /**< Control 2 Register, array offset: 0x4, array step: 0x60 */
    __IO uint16_t CTRL;                              /**< Control Register, array offset: 0x6, array step: 0x60 */
         uint8_t RESERVED_0[2];
    __IO uint16_t VAL0;                              /**< Value Register 0, array offset: 0xA, array step: 0x60 */
    __IO uint16_t FRACVAL1;                          /**< Fractional Value Register 1, array offset: 0xC, array step: 0x60 */
    __IO uint16_t VAL1;                              /**< Value Register 1, array offset: 0xE, array step: 0x60 */
    __IO uint16_t FRACVAL2;                          /**< Fractional Value Register 2, array offset: 0x10, array step: 0x60 */
    __IO uint16_t VAL2;                              /**< Value Register 2, array offset: 0x12, array step: 0x60 */
    __IO uint16_t FRACVAL3;                          /**< Fractional Value Register 3, array offset: 0x14, array step: 0x60 */
    __IO uint16_t VAL3;                              /**< Value Register 3, array offset: 0x16, array step: 0x60 */
    __IO uint16_t FRACVAL4;                          /**< Fractional Value Register 4, array offset: 0x18, array step: 0x60 */
    __IO uint16_t VAL4;                              /**< Value Register 4, array offset: 0x1A, array step: 0x60 */
    __IO uint16_t FRACVAL5;                          /**< Fractional Value Register 5, array offset: 0x1C, array step: 0x60 */
    __IO uint16_t VAL5;                              /**< Value Register 5, array offset: 0x1E, array step: 0x60 */
    __IO uint16_t FRCTRL;                            /**< Fractional Control Register, array offset: 0x20, array step: 0x60 */
    __IO uint16_t OCTRL;                             /**< Output Control Register, array offset: 0x22, array step: 0x60 */
    __IO uint16_t STS;                               /**< Status Register, array offset: 0x24, array step: 0x60 */
    __IO uint16_t INTEN;                             /**< Interrupt Enable Register, array offset: 0x26, array step: 0x60 */
    __IO uint16_t DMAEN;                             /**< DMA Enable Register, array offset: 0x28, array step: 0x60 */
    __IO uint16_t TCTRL;                             /**< Output Trigger Control Register, array offset: 0x2A, array step: 0x60 */
    __IO uint16_t DISMAP[1];                         /**< Fault Disable Mapping Register 0, array offset: 0x2C, array step: index*0x60, index2*0x2 */
         uint8_t RESERVED_1[2];
    __IO uint16_t DTCNT0;                            /**< Deadtime Count Register 0, array offset: 0x30, array step: 0x60 */
    __IO uint16_t DTCNT1;                            /**< Deadtime Count Register 1, array offset: 0x32, array step: 0x60 */
    __IO uint16_t CAPTCTRLA;                         /**< Capture Control A Register, array offset: 0x34, array step: 0x60 */
    __IO uint16_t CAPTCOMPA;                         /**< Capture Compare A Register, array offset: 0x36, array step: 0x60 */
    __IO uint16_t CAPTCTRLB;                         /**< Capture Control B Register, array offset: 0x38, array step: 0x60 */
    __IO uint16_t CAPTCOMPB;                         /**< Capture Compare B Register, array offset: 0x3A, array step: 0x60 */
    __IO uint16_t CAPTCTRLX;                         /**< Capture Control X Register, array offset: 0x3C, array step: 0x60 */
    __IO uint16_t CAPTCOMPX;                         /**< Capture Compare X Register, array offset: 0x3E, array step: 0x60 */
    __I  uint16_t CVAL0;                             /**< Capture Value 0 Register, array offset: 0x40, array step: 0x60 */
    __I  uint16_t CVAL0CYC;                          /**< Capture Value 0 Cycle Register, array offset: 0x42, array step: 0x60 */
    __I  uint16_t CVAL1;                             /**< Capture Value 1 Register, array offset: 0x44, array step: 0x60 */
    __I  uint16_t CVAL1CYC;                          /**< Capture Value 1 Cycle Register, array offset: 0x46, array step: 0x60 */
    __I  uint16_t CVAL2;                             /**< Capture Value 2 Register, array offset: 0x48, array step: 0x60 */
    __I  uint16_t CVAL2CYC;                          /**< Capture Value 2 Cycle Register, array offset: 0x4A, array step: 0x60 */
    __I  uint16_t CVAL3;                             /**< Capture Value 3 Register, array offset: 0x4C, array step: 0x60 */
    __I  uint16_t CVAL3CYC;                          /**< Capture Value 3 Cycle Register, array offset: 0x4E, array step: 0x60 */
    __I  uint16_t CVAL4;                             /**< Capture Value 4 Register, array offset: 0x50, array step: 0x60 */
    __I  uint16_t CVAL4CYC;                          /**< Capture Value 4 Cycle Register, array offset: 0x52, array step: 0x60 */
    __I  uint16_t CVAL5;                             /**< Capture Value 5 Register, array offset: 0x54, array step: 0x60 */
    __I  uint16_t CVAL5CYC;                          /**< Capture Value 5 Cycle Register, array offset: 0x56, array step: 0x60 */
    __IO uint16_t PHASEDLY;                          /**< Phase Delay Register, array offset: 0x58, array step: 0x60 */
    __IO uint16_t CAPTFILTA;                         /**< Capture PWMA Input Filter Register, array offset: 0x5A, array step: 0x60 */
    __IO uint16_t CAPTFILTB;                         /**< Capture PWMB Input Filter Register, array offset: 0x5C, array step: 0x60 */
    __IO uint16_t CAPTFILTX;                         /**< Capture PWMX Input Filter Register, array offset: 0x5E, array step: 0x60 */
  } SM[4];
  __IO uint16_t OUTEN;                             /**< Output Enable Register, offset: 0x180 */
  __IO uint16_t MASK;                              /**< Mask Register, offset: 0x182 */
  __IO uint16_t SWCOUT;                            /**< Software Controlled Output Register, offset: 0x184 */
  __IO uint16_t DTSRCSEL;                          /**< PWM Source Select Register, offset: 0x186 */
  __IO uint16_t MCTRL;                             /**< Master Control Register, offset: 0x188 */
  __IO uint16_t MCTRL2;                            /**< Master Control 2 Register, offset: 0x18A */
  __IO uint16_t FCTRL;                             /**< Fault Control Register, offset: 0x18C */
  __IO uint16_t FSTS;                              /**< Fault Status Register, offset: 0x18E */
  __IO uint16_t FFILT;                             /**< Fault Filter Register, offset: 0x190 */
  __IO uint16_t FTST;                              /**< Fault Test Register, offset: 0x192 */
  __IO uint16_t FCTRL2;                            /**< Fault Control 2 Register, offset: 0x194 */
} PWM_Type;

/* ----------------------------------------------------------------------------
   -- PWM Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup PWM_Register_Masks PWM Register Masks
 * @{
 */

/*! @name CNT - Counter Register */
/*! @{ */

#define PWM_CNT_CNT_MASK                         (0xFFFFU)
#define PWM_CNT_CNT_SHIFT                        (0U)
/*! CNT - Counter Register Bits
 */
#define PWM_CNT_CNT(x)                           (((uint16_t)(((uint16_t)(x)) << PWM_CNT_CNT_SHIFT)) & PWM_CNT_CNT_MASK)
/*! @} */

/* The count of PWM_CNT */
#define PWM_CNT_COUNT                            (4U)

/*! @name INIT - Initial Count Register */
/*! @{ */

#define PWM_INIT_INIT_MASK                       (0xFFFFU)
#define PWM_INIT_INIT_SHIFT                      (0U)
/*! INIT - Initial Count Register Bits
 */
#define PWM_INIT_INIT(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_INIT_INIT_SHIFT)) & PWM_INIT_INIT_MASK)
/*! @} */

/* The count of PWM_INIT */
#define PWM_INIT_COUNT                           (4U)

/*! @name CTRL2 - Control 2 Register */
/*! @{ */

#define PWM_CTRL2_CLK_SEL_MASK                   (0x3U)
#define PWM_CTRL2_CLK_SEL_SHIFT                  (0U)
/*! CLK_SEL - Clock Source Select
 *  0b00..The IPBus clock is used as the clock for the local prescaler and counter.
 *  0b01..EXT_CLK is used as the clock for the local prescaler and counter.
 *  0b10..Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This
 *        setting should not be used in submodule 0 as it will force the clock to logic 0.
 *  0b11..reserved
 */
#define PWM_CTRL2_CLK_SEL(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK)

#define PWM_CTRL2_RELOAD_SEL_MASK                (0x4U)
#define PWM_CTRL2_RELOAD_SEL_SHIFT               (2U)
/*! RELOAD_SEL - Reload Source Select
 *  0b0..The local RELOAD signal is used to reload registers.
 *  0b1..The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used
 *       in submodule 0 as it will force the RELOAD signal to logic 0.
 */
#define PWM_CTRL2_RELOAD_SEL(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK)

#define PWM_CTRL2_FORCE_SEL_MASK                 (0x38U)
#define PWM_CTRL2_FORCE_SEL_SHIFT                (3U)
/*! FORCE_SEL - This read/write bit determines the source of the FORCE OUTPUT signal for this submodule.
 *  0b000..The local force signal, CTRL2[FORCE], from this submodule is used to force updates.
 *  0b001..The master force signal from submodule 0 is used to force updates. This setting should not be used in
 *         submodule 0 as it will hold the FORCE OUTPUT signal to logic 0.
 *  0b010..The local reload signal from this submodule is used to force updates without regard to the state of LDOK.
 *  0b011..The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should
 *         not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0.
 *  0b100..The local sync signal from this submodule is used to force updates.
 *  0b101..The master sync signal from submodule0 is used to force updates. This setting should not be used in
 *         submodule0 as it will hold the FORCE OUTPUT signal to logic 0.
 *  0b110..The external force signal, EXT_FORCE, from outside the PWM module causes updates.
 *  0b111..The external sync signal, EXT_SYNC, from outside the PWM module causes updates.
 */
#define PWM_CTRL2_FORCE_SEL(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK)

#define PWM_CTRL2_FORCE_MASK                     (0x40U)
#define PWM_CTRL2_FORCE_SHIFT                    (6U)
/*! FORCE - Force Initialization
 */
#define PWM_CTRL2_FORCE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK)

#define PWM_CTRL2_FRCEN_MASK                     (0x80U)
#define PWM_CTRL2_FRCEN_SHIFT                    (7U)
/*! FRCEN - FRCEN
 *  0b0..Initialization from a FORCE_OUT is disabled.
 *  0b1..Initialization from a FORCE_OUT is enabled.
 */
#define PWM_CTRL2_FRCEN(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK)

#define PWM_CTRL2_INIT_SEL_MASK                  (0x300U)
#define PWM_CTRL2_INIT_SEL_SHIFT                 (8U)
/*! INIT_SEL - Initialization Control Select
 *  0b00..Local sync (PWM_X) causes initialization.
 *  0b01..Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as
 *        it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master
 *        reload occurs.
 *  0b10..Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it
 *        will force the INIT signal to logic 0.
 *  0b11..EXT_SYNC causes initialization.
 */
#define PWM_CTRL2_INIT_SEL(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK)

#define PWM_CTRL2_PWMX_INIT_MASK                 (0x400U)
#define PWM_CTRL2_PWMX_INIT_SHIFT                (10U)
/*! PWMX_INIT - PWM_X Initial Value
 */
#define PWM_CTRL2_PWMX_INIT(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK)

#define PWM_CTRL2_PWM45_INIT_MASK                (0x800U)
#define PWM_CTRL2_PWM45_INIT_SHIFT               (11U)
/*! PWM45_INIT - PWM45 Initial Value
 */
#define PWM_CTRL2_PWM45_INIT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK)

#define PWM_CTRL2_PWM23_INIT_MASK                (0x1000U)
#define PWM_CTRL2_PWM23_INIT_SHIFT               (12U)
/*! PWM23_INIT - PWM23 Initial Value
 */
#define PWM_CTRL2_PWM23_INIT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK)

#define PWM_CTRL2_INDEP_MASK                     (0x2000U)
#define PWM_CTRL2_INDEP_SHIFT                    (13U)
/*! INDEP - Independent or Complementary Pair Operation
 *  0b0..PWM_A and PWM_B form a complementary PWM pair.
 *  0b1..PWM_A and PWM_B outputs are independent PWMs.
 */
#define PWM_CTRL2_INDEP(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK)

#define PWM_CTRL2_WAITEN_MASK                    (0x4000U)
#define PWM_CTRL2_WAITEN_SHIFT                   (14U)
/*! WAITEN - Sleep Enable
 */
#define PWM_CTRL2_WAITEN(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_WAITEN_SHIFT)) & PWM_CTRL2_WAITEN_MASK)

#define PWM_CTRL2_DBGEN_MASK                     (0x8000U)
#define PWM_CTRL2_DBGEN_SHIFT                    (15U)
/*! DBGEN - Debug Enable
 */
#define PWM_CTRL2_DBGEN(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK)
/*! @} */

/* The count of PWM_CTRL2 */
#define PWM_CTRL2_COUNT                          (4U)

/*! @name CTRL - Control Register */
/*! @{ */

#define PWM_CTRL_DBLEN_MASK                      (0x1U)
#define PWM_CTRL_DBLEN_SHIFT                     (0U)
/*! DBLEN - Double Switching Enable
 *  0b0..Double switching disabled.
 *  0b1..Double switching enabled.
 */
#define PWM_CTRL_DBLEN(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK)

#define PWM_CTRL_DBLX_MASK                       (0x2U)
#define PWM_CTRL_DBLX_SHIFT                      (1U)
/*! DBLX - PWMX Double Switching Enable
 *  0b0..PWMX double pulse disabled.
 *  0b1..PWMX double pulse enabled.
 */
#define PWM_CTRL_DBLX(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK)

#define PWM_CTRL_LDMOD_MASK                      (0x4U)
#define PWM_CTRL_LDMOD_SHIFT                     (2U)
/*! LDMOD - Load Mode Select
 *  0b0..Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set.
 *  0b1..Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set.
 *       In this case it is not necessary to set CTRL[FULL] or CTRL[HALF].
 */
#define PWM_CTRL_LDMOD(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK)

#define PWM_CTRL_SPLIT_MASK                      (0x8U)
#define PWM_CTRL_SPLIT_SHIFT                     (3U)
/*! SPLIT - Split the DBLPWM signal to PWMA and PWMB
 *  0b0..DBLPWM is not split. PWMA and PWMB each have double pulses.
 *  0b1..DBLPWM is split to PWMA and PWMB.
 */
#define PWM_CTRL_SPLIT(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK)

#define PWM_CTRL_PRSC_MASK                       (0x70U)
#define PWM_CTRL_PRSC_SHIFT                      (4U)
/*! PRSC - Prescaler
 *  0b000..Prescaler 1
 *  0b001..Prescaler 2
 *  0b010..Prescaler 4
 *  0b011..Prescaler 8
 *  0b100..Prescaler 16
 *  0b101..Prescaler 32
 *  0b110..Prescaler 64
 *  0b111..Prescaler 128
 */
#define PWM_CTRL_PRSC(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK)

#define PWM_CTRL_COMPMODE_MASK                   (0x80U)
#define PWM_CTRL_COMPMODE_SHIFT                  (7U)
/*! COMPMODE - Compare Mode
 *  0b0..The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges
 *       are only produced when the counter is equal to one of the VAL* register values. This implies that a PWMA
 *       output that is high at the end of a period will maintain this state until a match with VAL3 clears the
 *       output in the following period.
 *  0b1..The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This
 *       means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register
 *       values. This implies that a PWMA output that is high at the end of a period could go low at the start of the
 *       next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value.
 */
#define PWM_CTRL_COMPMODE(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK)

#define PWM_CTRL_DT_MASK                         (0x300U)
#define PWM_CTRL_DT_SHIFT                        (8U)
/*! DT - Deadtime
 */
#define PWM_CTRL_DT(x)                           (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK)

#define PWM_CTRL_FULL_MASK                       (0x400U)
#define PWM_CTRL_FULL_SHIFT                      (10U)
/*! FULL - Full Cycle Reload
 *  0b0..Full-cycle reloads disabled.
 *  0b1..Full-cycle reloads enabled.
 */
#define PWM_CTRL_FULL(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK)

#define PWM_CTRL_HALF_MASK                       (0x800U)
#define PWM_CTRL_HALF_SHIFT                      (11U)
/*! HALF - Half Cycle Reload
 *  0b0..Half-cycle reloads disabled.
 *  0b1..Half-cycle reloads enabled.
 */
#define PWM_CTRL_HALF(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK)

#define PWM_CTRL_LDFQ_MASK                       (0xF000U)
#define PWM_CTRL_LDFQ_SHIFT                      (12U)
/*! LDFQ - Load Frequency
 *  0b0000..Every PWM opportunity
 *  0b0001..Every 2 PWM opportunities
 *  0b0010..Every 3 PWM opportunities
 *  0b0011..Every 4 PWM opportunities
 *  0b0100..Every 5 PWM opportunities
 *  0b0101..Every 6 PWM opportunities
 *  0b0110..Every 7 PWM opportunities
 *  0b0111..Every 8 PWM opportunities
 *  0b1000..Every 9 PWM opportunities
 *  0b1001..Every 10 PWM opportunities
 *  0b1010..Every 11 PWM opportunities
 *  0b1011..Every 12 PWM opportunities
 *  0b1100..Every 13 PWM opportunities
 *  0b1101..Every 14 PWM opportunities
 *  0b1110..Every 15 PWM opportunities
 *  0b1111..Every 16 PWM opportunities
 */
#define PWM_CTRL_LDFQ(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK)
/*! @} */

/* The count of PWM_CTRL */
#define PWM_CTRL_COUNT                           (4U)

/*! @name VAL0 - Value Register 0 */
/*! @{ */

#define PWM_VAL0_VAL0_MASK                       (0xFFFFU)
#define PWM_VAL0_VAL0_SHIFT                      (0U)
/*! VAL0 - Value Register 0
 */
#define PWM_VAL0_VAL0(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_VAL0_VAL0_SHIFT)) & PWM_VAL0_VAL0_MASK)
/*! @} */

/* The count of PWM_VAL0 */
#define PWM_VAL0_COUNT                           (4U)

/*! @name FRACVAL1 - Fractional Value Register 1 */
/*! @{ */

#define PWM_FRACVAL1_FRACVAL1_MASK               (0xF800U)
#define PWM_FRACVAL1_FRACVAL1_SHIFT              (11U)
/*! FRACVAL1 - Fractional Value 1 Register
 */
#define PWM_FRACVAL1_FRACVAL1(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL1_FRACVAL1_SHIFT)) & PWM_FRACVAL1_FRACVAL1_MASK)
/*! @} */

/* The count of PWM_FRACVAL1 */
#define PWM_FRACVAL1_COUNT                       (4U)

/*! @name VAL1 - Value Register 1 */
/*! @{ */

#define PWM_VAL1_VAL1_MASK                       (0xFFFFU)
#define PWM_VAL1_VAL1_SHIFT                      (0U)
/*! VAL1 - Value Register 1
 */
#define PWM_VAL1_VAL1(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_VAL1_VAL1_SHIFT)) & PWM_VAL1_VAL1_MASK)
/*! @} */

/* The count of PWM_VAL1 */
#define PWM_VAL1_COUNT                           (4U)

/*! @name FRACVAL2 - Fractional Value Register 2 */
/*! @{ */

#define PWM_FRACVAL2_FRACVAL2_MASK               (0xF800U)
#define PWM_FRACVAL2_FRACVAL2_SHIFT              (11U)
/*! FRACVAL2 - Fractional Value 2
 */
#define PWM_FRACVAL2_FRACVAL2(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL2_FRACVAL2_SHIFT)) & PWM_FRACVAL2_FRACVAL2_MASK)
/*! @} */

/* The count of PWM_FRACVAL2 */
#define PWM_FRACVAL2_COUNT                       (4U)

/*! @name VAL2 - Value Register 2 */
/*! @{ */

#define PWM_VAL2_VAL2_MASK                       (0xFFFFU)
#define PWM_VAL2_VAL2_SHIFT                      (0U)
/*! VAL2 - Value Register 2
 */
#define PWM_VAL2_VAL2(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_VAL2_VAL2_SHIFT)) & PWM_VAL2_VAL2_MASK)
/*! @} */

/* The count of PWM_VAL2 */
#define PWM_VAL2_COUNT                           (4U)

/*! @name FRACVAL3 - Fractional Value Register 3 */
/*! @{ */

#define PWM_FRACVAL3_FRACVAL3_MASK               (0xF800U)
#define PWM_FRACVAL3_FRACVAL3_SHIFT              (11U)
/*! FRACVAL3 - Fractional Value 3
 */
#define PWM_FRACVAL3_FRACVAL3(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL3_FRACVAL3_SHIFT)) & PWM_FRACVAL3_FRACVAL3_MASK)
/*! @} */

/* The count of PWM_FRACVAL3 */
#define PWM_FRACVAL3_COUNT                       (4U)

/*! @name VAL3 - Value Register 3 */
/*! @{ */

#define PWM_VAL3_VAL3_MASK                       (0xFFFFU)
#define PWM_VAL3_VAL3_SHIFT                      (0U)
/*! VAL3 - Value Register 3
 */
#define PWM_VAL3_VAL3(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_VAL3_VAL3_SHIFT)) & PWM_VAL3_VAL3_MASK)
/*! @} */

/* The count of PWM_VAL3 */
#define PWM_VAL3_COUNT                           (4U)

/*! @name FRACVAL4 - Fractional Value Register 4 */
/*! @{ */

#define PWM_FRACVAL4_FRACVAL4_MASK               (0xF800U)
#define PWM_FRACVAL4_FRACVAL4_SHIFT              (11U)
/*! FRACVAL4 - Fractional Value 4
 */
#define PWM_FRACVAL4_FRACVAL4(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL4_FRACVAL4_SHIFT)) & PWM_FRACVAL4_FRACVAL4_MASK)
/*! @} */

/* The count of PWM_FRACVAL4 */
#define PWM_FRACVAL4_COUNT                       (4U)

/*! @name VAL4 - Value Register 4 */
/*! @{ */

#define PWM_VAL4_VAL4_MASK                       (0xFFFFU)
#define PWM_VAL4_VAL4_SHIFT                      (0U)
/*! VAL4 - Value Register 4
 */
#define PWM_VAL4_VAL4(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_VAL4_VAL4_SHIFT)) & PWM_VAL4_VAL4_MASK)
/*! @} */

/* The count of PWM_VAL4 */
#define PWM_VAL4_COUNT                           (4U)

/*! @name FRACVAL5 - Fractional Value Register 5 */
/*! @{ */

#define PWM_FRACVAL5_FRACVAL5_MASK               (0xF800U)
#define PWM_FRACVAL5_FRACVAL5_SHIFT              (11U)
/*! FRACVAL5 - Fractional Value 5
 */
#define PWM_FRACVAL5_FRACVAL5(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL5_FRACVAL5_SHIFT)) & PWM_FRACVAL5_FRACVAL5_MASK)
/*! @} */

/* The count of PWM_FRACVAL5 */
#define PWM_FRACVAL5_COUNT                       (4U)

/*! @name VAL5 - Value Register 5 */
/*! @{ */

#define PWM_VAL5_VAL5_MASK                       (0xFFFFU)
#define PWM_VAL5_VAL5_SHIFT                      (0U)
/*! VAL5 - Value Register 5
 */
#define PWM_VAL5_VAL5(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_VAL5_VAL5_SHIFT)) & PWM_VAL5_VAL5_MASK)
/*! @} */

/* The count of PWM_VAL5 */
#define PWM_VAL5_COUNT                           (4U)

/*! @name FRCTRL - Fractional Control Register */
/*! @{ */

#define PWM_FRCTRL_FRAC1_EN_MASK                 (0x2U)
#define PWM_FRCTRL_FRAC1_EN_SHIFT                (1U)
/*! FRAC1_EN - Fractional Cycle PWM Period Enable
 *  0b0..Disable fractional cycle length for the PWM period.
 *  0b1..Enable fractional cycle length for the PWM period.
 */
#define PWM_FRCTRL_FRAC1_EN(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC1_EN_SHIFT)) & PWM_FRCTRL_FRAC1_EN_MASK)

#define PWM_FRCTRL_FRAC23_EN_MASK                (0x4U)
#define PWM_FRCTRL_FRAC23_EN_SHIFT               (2U)
/*! FRAC23_EN - Fractional Cycle Placement Enable for PWM_A
 *  0b0..Disable fractional cycle placement for PWM_A.
 *  0b1..Enable fractional cycle placement for PWM_A.
 */
#define PWM_FRCTRL_FRAC23_EN(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC23_EN_SHIFT)) & PWM_FRCTRL_FRAC23_EN_MASK)

#define PWM_FRCTRL_FRAC45_EN_MASK                (0x10U)
#define PWM_FRCTRL_FRAC45_EN_SHIFT               (4U)
/*! FRAC45_EN - Fractional Cycle Placement Enable for PWM_B
 *  0b0..Disable fractional cycle placement for PWM_B.
 *  0b1..Enable fractional cycle placement for PWM_B.
 */
#define PWM_FRCTRL_FRAC45_EN(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC45_EN_SHIFT)) & PWM_FRCTRL_FRAC45_EN_MASK)

#define PWM_FRCTRL_TEST_MASK                     (0x8000U)
#define PWM_FRCTRL_TEST_SHIFT                    (15U)
/*! TEST - Test Status Bit
 */
#define PWM_FRCTRL_TEST(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_TEST_SHIFT)) & PWM_FRCTRL_TEST_MASK)
/*! @} */

/* The count of PWM_FRCTRL */
#define PWM_FRCTRL_COUNT                         (4U)

/*! @name OCTRL - Output Control Register */
/*! @{ */

#define PWM_OCTRL_PWMXFS_MASK                    (0x3U)
#define PWM_OCTRL_PWMXFS_SHIFT                   (0U)
/*! PWMXFS - PWM_X Fault State
 *  0b00..Output is forced to logic 0 state prior to consideration of output polarity control.
 *  0b01..Output is forced to logic 1 state prior to consideration of output polarity control.
 *  0b10, 0b11..Output is tristated.
 */
#define PWM_OCTRL_PWMXFS(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMXFS_SHIFT)) & PWM_OCTRL_PWMXFS_MASK)

#define PWM_OCTRL_PWMBFS_MASK                    (0xCU)
#define PWM_OCTRL_PWMBFS_SHIFT                   (2U)
/*! PWMBFS - PWM_B Fault State
 *  0b00..Output is forced to logic 0 state prior to consideration of output polarity control.
 *  0b01..Output is forced to logic 1 state prior to consideration of output polarity control.
 *  0b10, 0b11..Output is tristated.
 */
#define PWM_OCTRL_PWMBFS(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMBFS_SHIFT)) & PWM_OCTRL_PWMBFS_MASK)

#define PWM_OCTRL_PWMAFS_MASK                    (0x30U)
#define PWM_OCTRL_PWMAFS_SHIFT                   (4U)
/*! PWMAFS - PWM_A Fault State
 *  0b00..Output is forced to logic 0 state prior to consideration of output polarity control.
 *  0b01..Output is forced to logic 1 state prior to consideration of output polarity control.
 *  0b10, 0b11..Output is tristated.
 */
#define PWM_OCTRL_PWMAFS(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMAFS_SHIFT)) & PWM_OCTRL_PWMAFS_MASK)

#define PWM_OCTRL_POLX_MASK                      (0x100U)
#define PWM_OCTRL_POLX_SHIFT                     (8U)
/*! POLX - PWM_X Output Polarity
 *  0b0..PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state.
 *  0b1..PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state.
 */
#define PWM_OCTRL_POLX(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLX_SHIFT)) & PWM_OCTRL_POLX_MASK)

#define PWM_OCTRL_POLB_MASK                      (0x200U)
#define PWM_OCTRL_POLB_SHIFT                     (9U)
/*! POLB - PWM_B Output Polarity
 *  0b0..PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state.
 *  0b1..PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state.
 */
#define PWM_OCTRL_POLB(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLB_SHIFT)) & PWM_OCTRL_POLB_MASK)

#define PWM_OCTRL_POLA_MASK                      (0x400U)
#define PWM_OCTRL_POLA_SHIFT                     (10U)
/*! POLA - PWM_A Output Polarity
 *  0b0..PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state.
 *  0b1..PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state.
 */
#define PWM_OCTRL_POLA(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLA_SHIFT)) & PWM_OCTRL_POLA_MASK)

#define PWM_OCTRL_PWMX_IN_MASK                   (0x2000U)
#define PWM_OCTRL_PWMX_IN_SHIFT                  (13U)
/*! PWMX_IN - PWM_X Input
 */
#define PWM_OCTRL_PWMX_IN(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMX_IN_SHIFT)) & PWM_OCTRL_PWMX_IN_MASK)

#define PWM_OCTRL_PWMB_IN_MASK                   (0x4000U)
#define PWM_OCTRL_PWMB_IN_SHIFT                  (14U)
/*! PWMB_IN - PWM_B Input
 */
#define PWM_OCTRL_PWMB_IN(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMB_IN_SHIFT)) & PWM_OCTRL_PWMB_IN_MASK)

#define PWM_OCTRL_PWMA_IN_MASK                   (0x8000U)
#define PWM_OCTRL_PWMA_IN_SHIFT                  (15U)
/*! PWMA_IN - PWM_A Input
 */
#define PWM_OCTRL_PWMA_IN(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMA_IN_SHIFT)) & PWM_OCTRL_PWMA_IN_MASK)
/*! @} */

/* The count of PWM_OCTRL */
#define PWM_OCTRL_COUNT                          (4U)

/*! @name STS - Status Register */
/*! @{ */

#define PWM_STS_CMPF_MASK                        (0x3FU)
#define PWM_STS_CMPF_SHIFT                       (0U)
/*! CMPF - Compare Flags
 *  0b000000..No compare event has occurred for a particular VALx value.
 *  0b000001..A compare event has occurred for a particular VALx value.
 */
#define PWM_STS_CMPF(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CMPF_SHIFT)) & PWM_STS_CMPF_MASK)

#define PWM_STS_CFX0_MASK                        (0x40U)
#define PWM_STS_CFX0_SHIFT                       (6U)
/*! CFX0 - Capture Flag X0
 */
#define PWM_STS_CFX0(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX0_SHIFT)) & PWM_STS_CFX0_MASK)

#define PWM_STS_CFX1_MASK                        (0x80U)
#define PWM_STS_CFX1_SHIFT                       (7U)
/*! CFX1 - Capture Flag X1
 */
#define PWM_STS_CFX1(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX1_SHIFT)) & PWM_STS_CFX1_MASK)

#define PWM_STS_CFB0_MASK                        (0x100U)
#define PWM_STS_CFB0_SHIFT                       (8U)
/*! CFB0 - Capture Flag B0
 */
#define PWM_STS_CFB0(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB0_SHIFT)) & PWM_STS_CFB0_MASK)

#define PWM_STS_CFB1_MASK                        (0x200U)
#define PWM_STS_CFB1_SHIFT                       (9U)
/*! CFB1 - Capture Flag B1
 */
#define PWM_STS_CFB1(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB1_SHIFT)) & PWM_STS_CFB1_MASK)

#define PWM_STS_CFA0_MASK                        (0x400U)
#define PWM_STS_CFA0_SHIFT                       (10U)
/*! CFA0 - Capture Flag A0
 */
#define PWM_STS_CFA0(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA0_SHIFT)) & PWM_STS_CFA0_MASK)

#define PWM_STS_CFA1_MASK                        (0x800U)
#define PWM_STS_CFA1_SHIFT                       (11U)
/*! CFA1 - Capture Flag A1
 */
#define PWM_STS_CFA1(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA1_SHIFT)) & PWM_STS_CFA1_MASK)

#define PWM_STS_RF_MASK                          (0x1000U)
#define PWM_STS_RF_SHIFT                         (12U)
/*! RF - Reload Flag
 *  0b0..No new reload cycle since last STS[RF] clearing
 *  0b1..New reload cycle since last STS[RF] clearing
 */
#define PWM_STS_RF(x)                            (((uint16_t)(((uint16_t)(x)) << PWM_STS_RF_SHIFT)) & PWM_STS_RF_MASK)

#define PWM_STS_REF_MASK                         (0x2000U)
#define PWM_STS_REF_SHIFT                        (13U)
/*! REF - Reload Error Flag
 *  0b0..No reload error occurred.
 *  0b1..Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0.
 */
#define PWM_STS_REF(x)                           (((uint16_t)(((uint16_t)(x)) << PWM_STS_REF_SHIFT)) & PWM_STS_REF_MASK)

#define PWM_STS_RUF_MASK                         (0x4000U)
#define PWM_STS_RUF_SHIFT                        (14U)
/*! RUF - Registers Updated Flag
 *  0b0..No register update has occurred since last reload.
 *  0b1..At least one of the double buffered registers has been updated since the last reload.
 */
#define PWM_STS_RUF(x)                           (((uint16_t)(((uint16_t)(x)) << PWM_STS_RUF_SHIFT)) & PWM_STS_RUF_MASK)
/*! @} */

/* The count of PWM_STS */
#define PWM_STS_COUNT                            (4U)

/*! @name INTEN - Interrupt Enable Register */
/*! @{ */

#define PWM_INTEN_CMPIE_MASK                     (0x3FU)
#define PWM_INTEN_CMPIE_SHIFT                    (0U)
/*! CMPIE - Compare Interrupt Enables
 *  0b000000..The corresponding STS[CMPF] bit will not cause an interrupt request.
 *  0b000001..The corresponding STS[CMPF] bit will cause an interrupt request.
 */
#define PWM_INTEN_CMPIE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK)

#define PWM_INTEN_CX0IE_MASK                     (0x40U)
#define PWM_INTEN_CX0IE_SHIFT                    (6U)
/*! CX0IE - Capture X 0 Interrupt Enable
 *  0b0..Interrupt request disabled for STS[CFX0].
 *  0b1..Interrupt request enabled for STS[CFX0].
 */
#define PWM_INTEN_CX0IE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK)

#define PWM_INTEN_CX1IE_MASK                     (0x80U)
#define PWM_INTEN_CX1IE_SHIFT                    (7U)
/*! CX1IE - Capture X 1 Interrupt Enable
 *  0b0..Interrupt request disabled for STS[CFX1].
 *  0b1..Interrupt request enabled for STS[CFX1].
 */
#define PWM_INTEN_CX1IE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK)

#define PWM_INTEN_CB0IE_MASK                     (0x100U)
#define PWM_INTEN_CB0IE_SHIFT                    (8U)
/*! CB0IE - Capture B 0 Interrupt Enable
 *  0b0..Interrupt request disabled for STS[CFB0].
 *  0b1..Interrupt request enabled for STS[CFB0].
 */
#define PWM_INTEN_CB0IE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB0IE_SHIFT)) & PWM_INTEN_CB0IE_MASK)

#define PWM_INTEN_CB1IE_MASK                     (0x200U)
#define PWM_INTEN_CB1IE_SHIFT                    (9U)
/*! CB1IE - Capture B 1 Interrupt Enable
 *  0b0..Interrupt request disabled for STS[CFB1].
 *  0b1..Interrupt request enabled for STS[CFB1].
 */
#define PWM_INTEN_CB1IE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB1IE_SHIFT)) & PWM_INTEN_CB1IE_MASK)

#define PWM_INTEN_CA0IE_MASK                     (0x400U)
#define PWM_INTEN_CA0IE_SHIFT                    (10U)
/*! CA0IE - Capture A 0 Interrupt Enable
 *  0b0..Interrupt request disabled for STS[CFA0].
 *  0b1..Interrupt request enabled for STS[CFA0].
 */
#define PWM_INTEN_CA0IE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA0IE_SHIFT)) & PWM_INTEN_CA0IE_MASK)

#define PWM_INTEN_CA1IE_MASK                     (0x800U)
#define PWM_INTEN_CA1IE_SHIFT                    (11U)
/*! CA1IE - Capture A 1 Interrupt Enable
 *  0b0..Interrupt request disabled for STS[CFA1].
 *  0b1..Interrupt request enabled for STS[CFA1].
 */
#define PWM_INTEN_CA1IE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA1IE_SHIFT)) & PWM_INTEN_CA1IE_MASK)

#define PWM_INTEN_RIE_MASK                       (0x1000U)
#define PWM_INTEN_RIE_SHIFT                      (12U)
/*! RIE - Reload Interrupt Enable
 *  0b0..STS[RF] CPU interrupt requests disabled
 *  0b1..STS[RF] CPU interrupt requests enabled
 */
#define PWM_INTEN_RIE(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK)

#define PWM_INTEN_REIE_MASK                      (0x2000U)
#define PWM_INTEN_REIE_SHIFT                     (13U)
/*! REIE - Reload Error Interrupt Enable
 *  0b0..STS[REF] CPU interrupt requests disabled
 *  0b1..STS[REF] CPU interrupt requests enabled
 */
#define PWM_INTEN_REIE(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK)
/*! @} */

/* The count of PWM_INTEN */
#define PWM_INTEN_COUNT                          (4U)

/*! @name DMAEN - DMA Enable Register */
/*! @{ */

#define PWM_DMAEN_CX0DE_MASK                     (0x1U)
#define PWM_DMAEN_CX0DE_SHIFT                    (0U)
/*! CX0DE - Capture X0 FIFO DMA Enable
 */
#define PWM_DMAEN_CX0DE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX0DE_SHIFT)) & PWM_DMAEN_CX0DE_MASK)

#define PWM_DMAEN_CX1DE_MASK                     (0x2U)
#define PWM_DMAEN_CX1DE_SHIFT                    (1U)
/*! CX1DE - Capture X1 FIFO DMA Enable
 */
#define PWM_DMAEN_CX1DE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX1DE_SHIFT)) & PWM_DMAEN_CX1DE_MASK)

#define PWM_DMAEN_CB0DE_MASK                     (0x4U)
#define PWM_DMAEN_CB0DE_SHIFT                    (2U)
/*! CB0DE - Capture B0 FIFO DMA Enable
 */
#define PWM_DMAEN_CB0DE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB0DE_SHIFT)) & PWM_DMAEN_CB0DE_MASK)

#define PWM_DMAEN_CB1DE_MASK                     (0x8U)
#define PWM_DMAEN_CB1DE_SHIFT                    (3U)
/*! CB1DE - Capture B1 FIFO DMA Enable
 */
#define PWM_DMAEN_CB1DE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB1DE_SHIFT)) & PWM_DMAEN_CB1DE_MASK)

#define PWM_DMAEN_CA0DE_MASK                     (0x10U)
#define PWM_DMAEN_CA0DE_SHIFT                    (4U)
/*! CA0DE - Capture A0 FIFO DMA Enable
 */
#define PWM_DMAEN_CA0DE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA0DE_SHIFT)) & PWM_DMAEN_CA0DE_MASK)

#define PWM_DMAEN_CA1DE_MASK                     (0x20U)
#define PWM_DMAEN_CA1DE_SHIFT                    (5U)
/*! CA1DE - Capture A1 FIFO DMA Enable
 */
#define PWM_DMAEN_CA1DE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA1DE_SHIFT)) & PWM_DMAEN_CA1DE_MASK)

#define PWM_DMAEN_CAPTDE_MASK                    (0xC0U)
#define PWM_DMAEN_CAPTDE_SHIFT                   (6U)
/*! CAPTDE - Capture DMA Enable Source Select
 *  0b00..Read DMA requests disabled.
 *  0b01..Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE],
 *        DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to
 *        which watermark(s) the DMA request is sensitive.
 *  0b10..A local sync (VAL1 matches counter) sets the read DMA request.
 *  0b11..A local reload (STS[RF] being set) sets the read DMA request.
 */
#define PWM_DMAEN_CAPTDE(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CAPTDE_SHIFT)) & PWM_DMAEN_CAPTDE_MASK)

#define PWM_DMAEN_FAND_MASK                      (0x100U)
#define PWM_DMAEN_FAND_SHIFT                     (8U)
/*! FAND - FIFO Watermark AND Control
 *  0b0..Selected FIFO watermarks are OR'ed together.
 *  0b1..Selected FIFO watermarks are AND'ed together.
 */
#define PWM_DMAEN_FAND(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_FAND_SHIFT)) & PWM_DMAEN_FAND_MASK)

#define PWM_DMAEN_VALDE_MASK                     (0x200U)
#define PWM_DMAEN_VALDE_SHIFT                    (9U)
/*! VALDE - Value Registers DMA Enable
 *  0b0..DMA write requests disabled
 *  0b1..Enabled
 */
#define PWM_DMAEN_VALDE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_VALDE_SHIFT)) & PWM_DMAEN_VALDE_MASK)
/*! @} */

/* The count of PWM_DMAEN */
#define PWM_DMAEN_COUNT                          (4U)

/*! @name TCTRL - Output Trigger Control Register */
/*! @{ */

#define PWM_TCTRL_OUT_TRIG_EN_MASK               (0x3FU)
#define PWM_TCTRL_OUT_TRIG_EN_SHIFT              (0U)
/*! OUT_TRIG_EN - Output Trigger Enables
 *  0bxxxxx1..PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value.
 *  0bxxxx1x..PWM_OUT_TRIG1 will set when the counter value matches the VAL1 value.
 *  0bxxx1xx..PWM_OUT_TRIG0 will set when the counter value matches the VAL2 value.
 *  0bxx1xxx..PWM_OUT_TRIG1 will set when the counter value matches the VAL3 value.
 *  0bx1xxxx..PWM_OUT_TRIG0 will set when the counter value matches the VAL4 value.
 *  0b1xxxxx..PWM_OUT_TRIG1 will set when the counter value matches the VAL5 value.
 */
#define PWM_TCTRL_OUT_TRIG_EN(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_OUT_TRIG_EN_SHIFT)) & PWM_TCTRL_OUT_TRIG_EN_MASK)

#define PWM_TCTRL_TRGFRQ_MASK                    (0x1000U)
#define PWM_TCTRL_TRGFRQ_SHIFT                   (12U)
/*! TRGFRQ - Trigger frequency
 *  0b0..Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero.
 *  0b1..Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM
 *       is not reloaded every period due to CTRL[LDFQ] being non-zero.
 */
#define PWM_TCTRL_TRGFRQ(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_TRGFRQ_SHIFT)) & PWM_TCTRL_TRGFRQ_MASK)

#define PWM_TCTRL_PWBOT1_MASK                    (0x4000U)
#define PWM_TCTRL_PWBOT1_SHIFT                   (14U)
/*! PWBOT1 - Mux Output Trigger 1 Source Select
 *  0b0..Route the PWM_OUT_TRIG1 signal to PWM_MUX_TRIG1 port.
 *  0b1..Route the PWMB output to the PWM_MUX_TRIG1 port.
 */
#define PWM_TCTRL_PWBOT1(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWBOT1_SHIFT)) & PWM_TCTRL_PWBOT1_MASK)

#define PWM_TCTRL_PWAOT0_MASK                    (0x8000U)
#define PWM_TCTRL_PWAOT0_SHIFT                   (15U)
/*! PWAOT0 - Mux Output Trigger 0 Source Select
 *  0b0..Route the PWM_OUT_TRIG0 signal to PWM_MUX_TRIG0 port.
 *  0b1..Route the PWMA output to the PWM_MUX_TRIG0 port.
 */
#define PWM_TCTRL_PWAOT0(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWAOT0_SHIFT)) & PWM_TCTRL_PWAOT0_MASK)
/*! @} */

/* The count of PWM_TCTRL */
#define PWM_TCTRL_COUNT                          (4U)

/*! @name DISMAP - Fault Disable Mapping Register 0 */
/*! @{ */

#define PWM_DISMAP_DIS0A_MASK                    (0xFU)
#define PWM_DISMAP_DIS0A_SHIFT                   (0U)
/*! DIS0A - PWM_A Fault Disable Mask 0
 */
#define PWM_DISMAP_DIS0A(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0A_SHIFT)) & PWM_DISMAP_DIS0A_MASK)

#define PWM_DISMAP_DIS0B_MASK                    (0xF0U)
#define PWM_DISMAP_DIS0B_SHIFT                   (4U)
/*! DIS0B - PWM_B Fault Disable Mask 0
 */
#define PWM_DISMAP_DIS0B(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0B_SHIFT)) & PWM_DISMAP_DIS0B_MASK)

#define PWM_DISMAP_DIS0X_MASK                    (0xF00U)
#define PWM_DISMAP_DIS0X_SHIFT                   (8U)
/*! DIS0X - PWM_X Fault Disable Mask 0
 */
#define PWM_DISMAP_DIS0X(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0X_SHIFT)) & PWM_DISMAP_DIS0X_MASK)
/*! @} */

/* The count of PWM_DISMAP */
#define PWM_DISMAP_COUNT                         (4U)

/* The count of PWM_DISMAP */
#define PWM_DISMAP_COUNT2                        (1U)

/*! @name DTCNT0 - Deadtime Count Register 0 */
/*! @{ */

#define PWM_DTCNT0_DTCNT0_MASK                   (0x7FFU)
#define PWM_DTCNT0_DTCNT0_SHIFT                  (0U)
/*! DTCNT0 - Deadtime Count Register 0
 */
#define PWM_DTCNT0_DTCNT0(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT0_DTCNT0_SHIFT)) & PWM_DTCNT0_DTCNT0_MASK)
/*! @} */

/* The count of PWM_DTCNT0 */
#define PWM_DTCNT0_COUNT                         (4U)

/*! @name DTCNT1 - Deadtime Count Register 1 */
/*! @{ */

#define PWM_DTCNT1_DTCNT1_MASK                   (0x7FFU)
#define PWM_DTCNT1_DTCNT1_SHIFT                  (0U)
/*! DTCNT1 - Deadtime Count Register 1
 */
#define PWM_DTCNT1_DTCNT1(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT1_DTCNT1_SHIFT)) & PWM_DTCNT1_DTCNT1_MASK)
/*! @} */

/* The count of PWM_DTCNT1 */
#define PWM_DTCNT1_COUNT                         (4U)

/*! @name CAPTCTRLA - Capture Control A Register */
/*! @{ */

#define PWM_CAPTCTRLA_ARMA_MASK                  (0x1U)
#define PWM_CAPTCTRLA_ARMA_SHIFT                 (0U)
/*! ARMA - Arm A
 *  0b0..Input capture operation is disabled.
 *  0b1..Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled.
 */
#define PWM_CAPTCTRLA_ARMA(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ARMA_SHIFT)) & PWM_CAPTCTRLA_ARMA_MASK)

#define PWM_CAPTCTRLA_ONESHOTA_MASK              (0x2U)
#define PWM_CAPTCTRLA_ONESHOTA_SHIFT             (1U)
/*! ONESHOTA - One Shot Mode A
 *  0b0..Free Running
 *  0b1..One Shot
 */
#define PWM_CAPTCTRLA_ONESHOTA(x)                (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ONESHOTA_SHIFT)) & PWM_CAPTCTRLA_ONESHOTA_MASK)

#define PWM_CAPTCTRLA_EDGA0_MASK                 (0xCU)
#define PWM_CAPTCTRLA_EDGA0_SHIFT                (2U)
/*! EDGA0 - Edge A 0
 *  0b00..Disabled
 *  0b01..Capture falling edges
 *  0b10..Capture rising edges
 *  0b11..Capture any edge
 */
#define PWM_CAPTCTRLA_EDGA0(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA0_SHIFT)) & PWM_CAPTCTRLA_EDGA0_MASK)

#define PWM_CAPTCTRLA_EDGA1_MASK                 (0x30U)
#define PWM_CAPTCTRLA_EDGA1_SHIFT                (4U)
/*! EDGA1 - Edge A 1
 *  0b00..Disabled
 *  0b01..Capture falling edges
 *  0b10..Capture rising edges
 *  0b11..Capture any edge
 */
#define PWM_CAPTCTRLA_EDGA1(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA1_SHIFT)) & PWM_CAPTCTRLA_EDGA1_MASK)

#define PWM_CAPTCTRLA_INP_SELA_MASK              (0x40U)
#define PWM_CAPTCTRLA_INP_SELA_SHIFT             (6U)
/*! INP_SELA - Input Select A
 *  0b0..Raw PWM_A input signal selected as source.
 *  0b1..Edge Counter
 */
#define PWM_CAPTCTRLA_INP_SELA(x)                (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_INP_SELA_SHIFT)) & PWM_CAPTCTRLA_INP_SELA_MASK)

#define PWM_CAPTCTRLA_EDGCNTA_EN_MASK            (0x80U)
#define PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT           (7U)
/*! EDGCNTA_EN - Edge Counter A Enable
 *  0b0..Edge counter disabled and held in reset
 *  0b1..Edge counter enabled
 */
#define PWM_CAPTCTRLA_EDGCNTA_EN(x)              (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT)) & PWM_CAPTCTRLA_EDGCNTA_EN_MASK)

#define PWM_CAPTCTRLA_CFAWM_MASK                 (0x300U)
#define PWM_CAPTCTRLA_CFAWM_SHIFT                (8U)
/*! CFAWM - Capture A FIFOs Water Mark
 */
#define PWM_CAPTCTRLA_CFAWM(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CFAWM_SHIFT)) & PWM_CAPTCTRLA_CFAWM_MASK)

#define PWM_CAPTCTRLA_CA0CNT_MASK                (0x1C00U)
#define PWM_CAPTCTRLA_CA0CNT_SHIFT               (10U)
/*! CA0CNT - Capture A0 FIFO Word Count
 */
#define PWM_CAPTCTRLA_CA0CNT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA0CNT_SHIFT)) & PWM_CAPTCTRLA_CA0CNT_MASK)

#define PWM_CAPTCTRLA_CA1CNT_MASK                (0xE000U)
#define PWM_CAPTCTRLA_CA1CNT_SHIFT               (13U)
/*! CA1CNT - Capture A1 FIFO Word Count
 */
#define PWM_CAPTCTRLA_CA1CNT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA1CNT_SHIFT)) & PWM_CAPTCTRLA_CA1CNT_MASK)
/*! @} */

/* The count of PWM_CAPTCTRLA */
#define PWM_CAPTCTRLA_COUNT                      (4U)

/*! @name CAPTCOMPA - Capture Compare A Register */
/*! @{ */

#define PWM_CAPTCOMPA_EDGCMPA_MASK               (0xFFU)
#define PWM_CAPTCOMPA_EDGCMPA_SHIFT              (0U)
/*! EDGCMPA - Edge Compare A
 */
#define PWM_CAPTCOMPA_EDGCMPA(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCMPA_SHIFT)) & PWM_CAPTCOMPA_EDGCMPA_MASK)

#define PWM_CAPTCOMPA_EDGCNTA_MASK               (0xFF00U)
#define PWM_CAPTCOMPA_EDGCNTA_SHIFT              (8U)
/*! EDGCNTA - Edge Counter A
 */
#define PWM_CAPTCOMPA_EDGCNTA(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCNTA_SHIFT)) & PWM_CAPTCOMPA_EDGCNTA_MASK)
/*! @} */

/* The count of PWM_CAPTCOMPA */
#define PWM_CAPTCOMPA_COUNT                      (4U)

/*! @name CAPTCTRLB - Capture Control B Register */
/*! @{ */

#define PWM_CAPTCTRLB_ARMB_MASK                  (0x1U)
#define PWM_CAPTCTRLB_ARMB_SHIFT                 (0U)
/*! ARMB - Arm B
 *  0b0..Input capture operation is disabled.
 *  0b1..Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled.
 */
#define PWM_CAPTCTRLB_ARMB(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ARMB_SHIFT)) & PWM_CAPTCTRLB_ARMB_MASK)

#define PWM_CAPTCTRLB_ONESHOTB_MASK              (0x2U)
#define PWM_CAPTCTRLB_ONESHOTB_SHIFT             (1U)
/*! ONESHOTB - One Shot Mode B
 *  0b0..Free Running
 *  0b1..One Shot
 */
#define PWM_CAPTCTRLB_ONESHOTB(x)                (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ONESHOTB_SHIFT)) & PWM_CAPTCTRLB_ONESHOTB_MASK)

#define PWM_CAPTCTRLB_EDGB0_MASK                 (0xCU)
#define PWM_CAPTCTRLB_EDGB0_SHIFT                (2U)
/*! EDGB0 - Edge B 0
 *  0b00..Disabled
 *  0b01..Capture falling edges
 *  0b10..Capture rising edges
 *  0b11..Capture any edge
 */
#define PWM_CAPTCTRLB_EDGB0(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB0_SHIFT)) & PWM_CAPTCTRLB_EDGB0_MASK)

#define PWM_CAPTCTRLB_EDGB1_MASK                 (0x30U)
#define PWM_CAPTCTRLB_EDGB1_SHIFT                (4U)
/*! EDGB1 - Edge B 1
 *  0b00..Disabled
 *  0b01..Capture falling edges
 *  0b10..Capture rising edges
 *  0b11..Capture any edge
 */
#define PWM_CAPTCTRLB_EDGB1(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB1_SHIFT)) & PWM_CAPTCTRLB_EDGB1_MASK)

#define PWM_CAPTCTRLB_INP_SELB_MASK              (0x40U)
#define PWM_CAPTCTRLB_INP_SELB_SHIFT             (6U)
/*! INP_SELB - Input Select B
 *  0b0..Raw PWM_B input signal selected as source.
 *  0b1..Edge Counter
 */
#define PWM_CAPTCTRLB_INP_SELB(x)                (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_INP_SELB_SHIFT)) & PWM_CAPTCTRLB_INP_SELB_MASK)

#define PWM_CAPTCTRLB_EDGCNTB_EN_MASK            (0x80U)
#define PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT           (7U)
/*! EDGCNTB_EN - Edge Counter B Enable
 *  0b0..Edge counter disabled and held in reset
 *  0b1..Edge counter enabled
 */
#define PWM_CAPTCTRLB_EDGCNTB_EN(x)              (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT)) & PWM_CAPTCTRLB_EDGCNTB_EN_MASK)

#define PWM_CAPTCTRLB_CFBWM_MASK                 (0x300U)
#define PWM_CAPTCTRLB_CFBWM_SHIFT                (8U)
/*! CFBWM - Capture B FIFOs Water Mark
 */
#define PWM_CAPTCTRLB_CFBWM(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CFBWM_SHIFT)) & PWM_CAPTCTRLB_CFBWM_MASK)

#define PWM_CAPTCTRLB_CB0CNT_MASK                (0x1C00U)
#define PWM_CAPTCTRLB_CB0CNT_SHIFT               (10U)
/*! CB0CNT - Capture B0 FIFO Word Count
 */
#define PWM_CAPTCTRLB_CB0CNT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB0CNT_SHIFT)) & PWM_CAPTCTRLB_CB0CNT_MASK)

#define PWM_CAPTCTRLB_CB1CNT_MASK                (0xE000U)
#define PWM_CAPTCTRLB_CB1CNT_SHIFT               (13U)
/*! CB1CNT - Capture B1 FIFO Word Count
 */
#define PWM_CAPTCTRLB_CB1CNT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB1CNT_SHIFT)) & PWM_CAPTCTRLB_CB1CNT_MASK)
/*! @} */

/* The count of PWM_CAPTCTRLB */
#define PWM_CAPTCTRLB_COUNT                      (4U)

/*! @name CAPTCOMPB - Capture Compare B Register */
/*! @{ */

#define PWM_CAPTCOMPB_EDGCMPB_MASK               (0xFFU)
#define PWM_CAPTCOMPB_EDGCMPB_SHIFT              (0U)
/*! EDGCMPB - Edge Compare B
 */
#define PWM_CAPTCOMPB_EDGCMPB(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCMPB_SHIFT)) & PWM_CAPTCOMPB_EDGCMPB_MASK)

#define PWM_CAPTCOMPB_EDGCNTB_MASK               (0xFF00U)
#define PWM_CAPTCOMPB_EDGCNTB_SHIFT              (8U)
/*! EDGCNTB - Edge Counter B
 */
#define PWM_CAPTCOMPB_EDGCNTB(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCNTB_SHIFT)) & PWM_CAPTCOMPB_EDGCNTB_MASK)
/*! @} */

/* The count of PWM_CAPTCOMPB */
#define PWM_CAPTCOMPB_COUNT                      (4U)

/*! @name CAPTCTRLX - Capture Control X Register */
/*! @{ */

#define PWM_CAPTCTRLX_ARMX_MASK                  (0x1U)
#define PWM_CAPTCTRLX_ARMX_SHIFT                 (0U)
/*! ARMX - Arm X
 *  0b0..Input capture operation is disabled.
 *  0b1..Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled.
 */
#define PWM_CAPTCTRLX_ARMX(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ARMX_SHIFT)) & PWM_CAPTCTRLX_ARMX_MASK)

#define PWM_CAPTCTRLX_ONESHOTX_MASK              (0x2U)
#define PWM_CAPTCTRLX_ONESHOTX_SHIFT             (1U)
/*! ONESHOTX - One Shot Mode Aux
 *  0b0..Free Running
 *  0b1..One Shot
 */
#define PWM_CAPTCTRLX_ONESHOTX(x)                (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ONESHOTX_SHIFT)) & PWM_CAPTCTRLX_ONESHOTX_MASK)

#define PWM_CAPTCTRLX_EDGX0_MASK                 (0xCU)
#define PWM_CAPTCTRLX_EDGX0_SHIFT                (2U)
/*! EDGX0 - Edge X 0
 *  0b00..Disabled
 *  0b01..Capture falling edges
 *  0b10..Capture rising edges
 *  0b11..Capture any edge
 */
#define PWM_CAPTCTRLX_EDGX0(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX0_SHIFT)) & PWM_CAPTCTRLX_EDGX0_MASK)

#define PWM_CAPTCTRLX_EDGX1_MASK                 (0x30U)
#define PWM_CAPTCTRLX_EDGX1_SHIFT                (4U)
/*! EDGX1 - Edge X 1
 *  0b00..Disabled
 *  0b01..Capture falling edges
 *  0b10..Capture rising edges
 *  0b11..Capture any edge
 */
#define PWM_CAPTCTRLX_EDGX1(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX1_SHIFT)) & PWM_CAPTCTRLX_EDGX1_MASK)

#define PWM_CAPTCTRLX_INP_SELX_MASK              (0x40U)
#define PWM_CAPTCTRLX_INP_SELX_SHIFT             (6U)
/*! INP_SELX - Input Select X
 *  0b0..Raw PWM_X input signal selected as source.
 *  0b1..Edge Counter
 */
#define PWM_CAPTCTRLX_INP_SELX(x)                (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_INP_SELX_SHIFT)) & PWM_CAPTCTRLX_INP_SELX_MASK)

#define PWM_CAPTCTRLX_EDGCNTX_EN_MASK            (0x80U)
#define PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT           (7U)
/*! EDGCNTX_EN - Edge Counter X Enable
 *  0b0..Edge counter disabled and held in reset
 *  0b1..Edge counter enabled
 */
#define PWM_CAPTCTRLX_EDGCNTX_EN(x)              (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT)) & PWM_CAPTCTRLX_EDGCNTX_EN_MASK)

#define PWM_CAPTCTRLX_CFXWM_MASK                 (0x300U)
#define PWM_CAPTCTRLX_CFXWM_SHIFT                (8U)
/*! CFXWM - Capture X FIFOs Water Mark
 */
#define PWM_CAPTCTRLX_CFXWM(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CFXWM_SHIFT)) & PWM_CAPTCTRLX_CFXWM_MASK)

#define PWM_CAPTCTRLX_CX0CNT_MASK                (0x1C00U)
#define PWM_CAPTCTRLX_CX0CNT_SHIFT               (10U)
/*! CX0CNT - Capture X0 FIFO Word Count
 */
#define PWM_CAPTCTRLX_CX0CNT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX0CNT_SHIFT)) & PWM_CAPTCTRLX_CX0CNT_MASK)

#define PWM_CAPTCTRLX_CX1CNT_MASK                (0xE000U)
#define PWM_CAPTCTRLX_CX1CNT_SHIFT               (13U)
/*! CX1CNT - Capture X1 FIFO Word Count
 */
#define PWM_CAPTCTRLX_CX1CNT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX1CNT_SHIFT)) & PWM_CAPTCTRLX_CX1CNT_MASK)
/*! @} */

/* The count of PWM_CAPTCTRLX */
#define PWM_CAPTCTRLX_COUNT                      (4U)

/*! @name CAPTCOMPX - Capture Compare X Register */
/*! @{ */

#define PWM_CAPTCOMPX_EDGCMPX_MASK               (0xFFU)
#define PWM_CAPTCOMPX_EDGCMPX_SHIFT              (0U)
/*! EDGCMPX - Edge Compare X
 */
#define PWM_CAPTCOMPX_EDGCMPX(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCMPX_SHIFT)) & PWM_CAPTCOMPX_EDGCMPX_MASK)

#define PWM_CAPTCOMPX_EDGCNTX_MASK               (0xFF00U)
#define PWM_CAPTCOMPX_EDGCNTX_SHIFT              (8U)
/*! EDGCNTX - Edge Counter X
 */
#define PWM_CAPTCOMPX_EDGCNTX(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCNTX_SHIFT)) & PWM_CAPTCOMPX_EDGCNTX_MASK)
/*! @} */

/* The count of PWM_CAPTCOMPX */
#define PWM_CAPTCOMPX_COUNT                      (4U)

/*! @name CVAL0 - Capture Value 0 Register */
/*! @{ */

#define PWM_CVAL0_CAPTVAL0_MASK                  (0xFFFFU)
#define PWM_CVAL0_CAPTVAL0_SHIFT                 (0U)
/*! CAPTVAL0 - CAPTVAL0
 */
#define PWM_CVAL0_CAPTVAL0(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0_CAPTVAL0_SHIFT)) & PWM_CVAL0_CAPTVAL0_MASK)
/*! @} */

/* The count of PWM_CVAL0 */
#define PWM_CVAL0_COUNT                          (4U)

/*! @name CVAL0CYC - Capture Value 0 Cycle Register */
/*! @{ */

#define PWM_CVAL0CYC_CVAL0CYC_MASK               (0xFU)
#define PWM_CVAL0CYC_CVAL0CYC_SHIFT              (0U)
/*! CVAL0CYC - CVAL0CYC
 */
#define PWM_CVAL0CYC_CVAL0CYC(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0CYC_CVAL0CYC_SHIFT)) & PWM_CVAL0CYC_CVAL0CYC_MASK)
/*! @} */

/* The count of PWM_CVAL0CYC */
#define PWM_CVAL0CYC_COUNT                       (4U)

/*! @name CVAL1 - Capture Value 1 Register */
/*! @{ */

#define PWM_CVAL1_CAPTVAL1_MASK                  (0xFFFFU)
#define PWM_CVAL1_CAPTVAL1_SHIFT                 (0U)
/*! CAPTVAL1 - CAPTVAL1
 */
#define PWM_CVAL1_CAPTVAL1(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1_CAPTVAL1_SHIFT)) & PWM_CVAL1_CAPTVAL1_MASK)
/*! @} */

/* The count of PWM_CVAL1 */
#define PWM_CVAL1_COUNT                          (4U)

/*! @name CVAL1CYC - Capture Value 1 Cycle Register */
/*! @{ */

#define PWM_CVAL1CYC_CVAL1CYC_MASK               (0xFU)
#define PWM_CVAL1CYC_CVAL1CYC_SHIFT              (0U)
/*! CVAL1CYC - CVAL1CYC
 */
#define PWM_CVAL1CYC_CVAL1CYC(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1CYC_CVAL1CYC_SHIFT)) & PWM_CVAL1CYC_CVAL1CYC_MASK)
/*! @} */

/* The count of PWM_CVAL1CYC */
#define PWM_CVAL1CYC_COUNT                       (4U)

/*! @name CVAL2 - Capture Value 2 Register */
/*! @{ */

#define PWM_CVAL2_CAPTVAL2_MASK                  (0xFFFFU)
#define PWM_CVAL2_CAPTVAL2_SHIFT                 (0U)
/*! CAPTVAL2 - CAPTVAL2
 */
#define PWM_CVAL2_CAPTVAL2(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2_CAPTVAL2_SHIFT)) & PWM_CVAL2_CAPTVAL2_MASK)
/*! @} */

/* The count of PWM_CVAL2 */
#define PWM_CVAL2_COUNT                          (4U)

/*! @name CVAL2CYC - Capture Value 2 Cycle Register */
/*! @{ */

#define PWM_CVAL2CYC_CVAL2CYC_MASK               (0xFU)
#define PWM_CVAL2CYC_CVAL2CYC_SHIFT              (0U)
/*! CVAL2CYC - CVAL2CYC
 */
#define PWM_CVAL2CYC_CVAL2CYC(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2CYC_CVAL2CYC_SHIFT)) & PWM_CVAL2CYC_CVAL2CYC_MASK)
/*! @} */

/* The count of PWM_CVAL2CYC */
#define PWM_CVAL2CYC_COUNT                       (4U)

/*! @name CVAL3 - Capture Value 3 Register */
/*! @{ */

#define PWM_CVAL3_CAPTVAL3_MASK                  (0xFFFFU)
#define PWM_CVAL3_CAPTVAL3_SHIFT                 (0U)
/*! CAPTVAL3 - CAPTVAL3
 */
#define PWM_CVAL3_CAPTVAL3(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3_CAPTVAL3_SHIFT)) & PWM_CVAL3_CAPTVAL3_MASK)
/*! @} */

/* The count of PWM_CVAL3 */
#define PWM_CVAL3_COUNT                          (4U)

/*! @name CVAL3CYC - Capture Value 3 Cycle Register */
/*! @{ */

#define PWM_CVAL3CYC_CVAL3CYC_MASK               (0xFU)
#define PWM_CVAL3CYC_CVAL3CYC_SHIFT              (0U)
/*! CVAL3CYC - CVAL3CYC
 */
#define PWM_CVAL3CYC_CVAL3CYC(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3CYC_CVAL3CYC_SHIFT)) & PWM_CVAL3CYC_CVAL3CYC_MASK)
/*! @} */

/* The count of PWM_CVAL3CYC */
#define PWM_CVAL3CYC_COUNT                       (4U)

/*! @name CVAL4 - Capture Value 4 Register */
/*! @{ */

#define PWM_CVAL4_CAPTVAL4_MASK                  (0xFFFFU)
#define PWM_CVAL4_CAPTVAL4_SHIFT                 (0U)
/*! CAPTVAL4 - CAPTVAL4
 */
#define PWM_CVAL4_CAPTVAL4(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4_CAPTVAL4_SHIFT)) & PWM_CVAL4_CAPTVAL4_MASK)
/*! @} */

/* The count of PWM_CVAL4 */
#define PWM_CVAL4_COUNT                          (4U)

/*! @name CVAL4CYC - Capture Value 4 Cycle Register */
/*! @{ */

#define PWM_CVAL4CYC_CVAL4CYC_MASK               (0xFU)
#define PWM_CVAL4CYC_CVAL4CYC_SHIFT              (0U)
/*! CVAL4CYC - CVAL4CYC
 */
#define PWM_CVAL4CYC_CVAL4CYC(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4CYC_CVAL4CYC_SHIFT)) & PWM_CVAL4CYC_CVAL4CYC_MASK)
/*! @} */

/* The count of PWM_CVAL4CYC */
#define PWM_CVAL4CYC_COUNT                       (4U)

/*! @name CVAL5 - Capture Value 5 Register */
/*! @{ */

#define PWM_CVAL5_CAPTVAL5_MASK                  (0xFFFFU)
#define PWM_CVAL5_CAPTVAL5_SHIFT                 (0U)
/*! CAPTVAL5 - CAPTVAL5
 */
#define PWM_CVAL5_CAPTVAL5(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5_CAPTVAL5_SHIFT)) & PWM_CVAL5_CAPTVAL5_MASK)
/*! @} */

/* The count of PWM_CVAL5 */
#define PWM_CVAL5_COUNT                          (4U)

/*! @name CVAL5CYC - Capture Value 5 Cycle Register */
/*! @{ */

#define PWM_CVAL5CYC_CVAL5CYC_MASK               (0xFU)
#define PWM_CVAL5CYC_CVAL5CYC_SHIFT              (0U)
/*! CVAL5CYC - CVAL5CYC
 */
#define PWM_CVAL5CYC_CVAL5CYC(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5CYC_CVAL5CYC_SHIFT)) & PWM_CVAL5CYC_CVAL5CYC_MASK)
/*! @} */

/* The count of PWM_CVAL5CYC */
#define PWM_CVAL5CYC_COUNT                       (4U)

/*! @name PHASEDLY - Phase Delay Register */
/*! @{ */

#define PWM_PHASEDLY_PHASEDLY_MASK               (0xFFFFU)
#define PWM_PHASEDLY_PHASEDLY_SHIFT              (0U)
/*! PHASEDLY - Initial Count Register Bits
 */
#define PWM_PHASEDLY_PHASEDLY(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_PHASEDLY_PHASEDLY_SHIFT)) & PWM_PHASEDLY_PHASEDLY_MASK)
/*! @} */

/* The count of PWM_PHASEDLY */
#define PWM_PHASEDLY_COUNT                       (4U)

/*! @name CAPTFILTA - Capture PWMA Input Filter Register */
/*! @{ */

#define PWM_CAPTFILTA_CAPTA_FILT_PER_MASK        (0xFFU)
#define PWM_CAPTFILTA_CAPTA_FILT_PER_SHIFT       (0U)
/*! CAPTA_FILT_PER - Fault Filter Period
 */
#define PWM_CAPTFILTA_CAPTA_FILT_PER(x)          (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTA_CAPTA_FILT_PER_SHIFT)) & PWM_CAPTFILTA_CAPTA_FILT_PER_MASK)

#define PWM_CAPTFILTA_CAPTA_FILT_CNT_MASK        (0x700U)
#define PWM_CAPTFILTA_CAPTA_FILT_CNT_SHIFT       (8U)
/*! CAPTA_FILT_CNT - Fault Filter Count
 */
#define PWM_CAPTFILTA_CAPTA_FILT_CNT(x)          (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTA_CAPTA_FILT_CNT_SHIFT)) & PWM_CAPTFILTA_CAPTA_FILT_CNT_MASK)
/*! @} */

/* The count of PWM_CAPTFILTA */
#define PWM_CAPTFILTA_COUNT                      (4U)

/*! @name CAPTFILTB - Capture PWMB Input Filter Register */
/*! @{ */

#define PWM_CAPTFILTB_CAPTB_FILT_PER_MASK        (0xFFU)
#define PWM_CAPTFILTB_CAPTB_FILT_PER_SHIFT       (0U)
/*! CAPTB_FILT_PER - Fault Filter Period
 */
#define PWM_CAPTFILTB_CAPTB_FILT_PER(x)          (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTB_CAPTB_FILT_PER_SHIFT)) & PWM_CAPTFILTB_CAPTB_FILT_PER_MASK)

#define PWM_CAPTFILTB_CAPTB_FILT_CNT_MASK        (0x700U)
#define PWM_CAPTFILTB_CAPTB_FILT_CNT_SHIFT       (8U)
/*! CAPTB_FILT_CNT - Fault Filter Count
 */
#define PWM_CAPTFILTB_CAPTB_FILT_CNT(x)          (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTB_CAPTB_FILT_CNT_SHIFT)) & PWM_CAPTFILTB_CAPTB_FILT_CNT_MASK)
/*! @} */

/* The count of PWM_CAPTFILTB */
#define PWM_CAPTFILTB_COUNT                      (4U)

/*! @name CAPTFILTX - Capture PWMX Input Filter Register */
/*! @{ */

#define PWM_CAPTFILTX_CAPTX_FILT_PER_MASK        (0xFFU)
#define PWM_CAPTFILTX_CAPTX_FILT_PER_SHIFT       (0U)
/*! CAPTX_FILT_PER - Fault Filter Period
 */
#define PWM_CAPTFILTX_CAPTX_FILT_PER(x)          (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTX_CAPTX_FILT_PER_SHIFT)) & PWM_CAPTFILTX_CAPTX_FILT_PER_MASK)

#define PWM_CAPTFILTX_CAPTX_FILT_CNT_MASK        (0x700U)
#define PWM_CAPTFILTX_CAPTX_FILT_CNT_SHIFT       (8U)
/*! CAPTX_FILT_CNT - Fault Filter Count
 */
#define PWM_CAPTFILTX_CAPTX_FILT_CNT(x)          (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTX_CAPTX_FILT_CNT_SHIFT)) & PWM_CAPTFILTX_CAPTX_FILT_CNT_MASK)
/*! @} */

/* The count of PWM_CAPTFILTX */
#define PWM_CAPTFILTX_COUNT                      (4U)

/*! @name OUTEN - Output Enable Register */
/*! @{ */

#define PWM_OUTEN_PWMX_EN_MASK                   (0xFU)
#define PWM_OUTEN_PWMX_EN_SHIFT                  (0U)
/*! PWMX_EN - PWM_X Output Enables
 *  0b0000..PWM_X output disabled.
 *  0b0001..PWM_X output enabled.
 */
#define PWM_OUTEN_PWMX_EN(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMX_EN_SHIFT)) & PWM_OUTEN_PWMX_EN_MASK)

#define PWM_OUTEN_PWMB_EN_MASK                   (0xF0U)
#define PWM_OUTEN_PWMB_EN_SHIFT                  (4U)
/*! PWMB_EN - PWM_B Output Enables
 *  0b0000..PWM_B output disabled.
 *  0b0001..PWM_B output enabled.
 */
#define PWM_OUTEN_PWMB_EN(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMB_EN_SHIFT)) & PWM_OUTEN_PWMB_EN_MASK)

#define PWM_OUTEN_PWMA_EN_MASK                   (0xF00U)
#define PWM_OUTEN_PWMA_EN_SHIFT                  (8U)
/*! PWMA_EN - PWM_A Output Enables
 *  0b0000..PWM_A output disabled.
 *  0b0001..PWM_A output enabled.
 */
#define PWM_OUTEN_PWMA_EN(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMA_EN_SHIFT)) & PWM_OUTEN_PWMA_EN_MASK)
/*! @} */

/*! @name MASK - Mask Register */
/*! @{ */

#define PWM_MASK_MASKX_MASK                      (0xFU)
#define PWM_MASK_MASKX_SHIFT                     (0U)
/*! MASKX - PWM_X Masks
 *  0b0000..PWM_X output normal.
 *  0b0001..PWM_X output masked.
 */
#define PWM_MASK_MASKX(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKX_SHIFT)) & PWM_MASK_MASKX_MASK)

#define PWM_MASK_MASKB_MASK                      (0xF0U)
#define PWM_MASK_MASKB_SHIFT                     (4U)
/*! MASKB - PWM_B Masks
 *  0b0000..PWM_B output normal.
 *  0b0001..PWM_B output masked.
 */
#define PWM_MASK_MASKB(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKB_SHIFT)) & PWM_MASK_MASKB_MASK)

#define PWM_MASK_MASKA_MASK                      (0xF00U)
#define PWM_MASK_MASKA_SHIFT                     (8U)
/*! MASKA - PWM_A Masks
 *  0b0000..PWM_A output normal.
 *  0b0001..PWM_A output masked.
 */
#define PWM_MASK_MASKA(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKA_SHIFT)) & PWM_MASK_MASKA_MASK)

#define PWM_MASK_UPDATE_MASK_MASK                (0xF000U)
#define PWM_MASK_UPDATE_MASK_SHIFT               (12U)
/*! UPDATE_MASK - Update Mask Bits Immediately
 *  0b0000..Normal operation. MASK* bits within the corresponding submodule are not updated until a FORCE_OUT event occurs within the submodule.
 *  0b0001..Immediate operation. MASK* bits within the corresponding submodule are updated on the following clock edge after setting this bit.
 */
#define PWM_MASK_UPDATE_MASK(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_MASK_UPDATE_MASK_SHIFT)) & PWM_MASK_UPDATE_MASK_MASK)
/*! @} */

/*! @name SWCOUT - Software Controlled Output Register */
/*! @{ */

#define PWM_SWCOUT_SM0OUT45_MASK                 (0x1U)
#define PWM_SWCOUT_SM0OUT45_SHIFT                (0U)
/*! SM0OUT45 - Submodule 0 Software Controlled Output 45
 *  0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM45.
 *  0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM45.
 */
#define PWM_SWCOUT_SM0OUT45(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT45_SHIFT)) & PWM_SWCOUT_SM0OUT45_MASK)

#define PWM_SWCOUT_SM0OUT23_MASK                 (0x2U)
#define PWM_SWCOUT_SM0OUT23_SHIFT                (1U)
/*! SM0OUT23 - Submodule 0 Software Controlled Output 23
 *  0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM23.
 *  0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23.
 */
#define PWM_SWCOUT_SM0OUT23(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT23_SHIFT)) & PWM_SWCOUT_SM0OUT23_MASK)

#define PWM_SWCOUT_SM1OUT45_MASK                 (0x4U)
#define PWM_SWCOUT_SM1OUT45_SHIFT                (2U)
/*! SM1OUT45 - Submodule 1 Software Controlled Output 45
 *  0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM45.
 *  0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM45.
 */
#define PWM_SWCOUT_SM1OUT45(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT45_SHIFT)) & PWM_SWCOUT_SM1OUT45_MASK)

#define PWM_SWCOUT_SM1OUT23_MASK                 (0x8U)
#define PWM_SWCOUT_SM1OUT23_SHIFT                (3U)
/*! SM1OUT23 - Submodule 1 Software Controlled Output 23
 *  0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM23.
 *  0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM23.
 */
#define PWM_SWCOUT_SM1OUT23(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT23_SHIFT)) & PWM_SWCOUT_SM1OUT23_MASK)

#define PWM_SWCOUT_SM2OUT45_MASK                 (0x10U)
#define PWM_SWCOUT_SM2OUT45_SHIFT                (4U)
/*! SM2OUT45 - Submodule 2 Software Controlled Output 45
 *  0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM45.
 *  0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM45.
 */
#define PWM_SWCOUT_SM2OUT45(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT45_SHIFT)) & PWM_SWCOUT_SM2OUT45_MASK)

#define PWM_SWCOUT_SM2OUT23_MASK                 (0x20U)
#define PWM_SWCOUT_SM2OUT23_SHIFT                (5U)
/*! SM2OUT23 - Submodule 2 Software Controlled Output 23
 *  0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM23.
 *  0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM23.
 */
#define PWM_SWCOUT_SM2OUT23(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT23_SHIFT)) & PWM_SWCOUT_SM2OUT23_MASK)

#define PWM_SWCOUT_SM3OUT45_MASK                 (0x40U)
#define PWM_SWCOUT_SM3OUT45_SHIFT                (6U)
/*! SM3OUT45 - Submodule 3 Software Controlled Output 45
 *  0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM45.
 *  0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM45.
 */
#define PWM_SWCOUT_SM3OUT45(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT45_SHIFT)) & PWM_SWCOUT_SM3OUT45_MASK)

#define PWM_SWCOUT_SM3OUT23_MASK                 (0x80U)
#define PWM_SWCOUT_SM3OUT23_SHIFT                (7U)
/*! SM3OUT23 - Submodule 3 Software Controlled Output 23
 *  0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM23.
 *  0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM23.
 */
#define PWM_SWCOUT_SM3OUT23(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT23_SHIFT)) & PWM_SWCOUT_SM3OUT23_MASK)
/*! @} */

/*! @name DTSRCSEL - PWM Source Select Register */
/*! @{ */

#define PWM_DTSRCSEL_SM0SEL45_MASK               (0x3U)
#define PWM_DTSRCSEL_SM0SEL45_SHIFT              (0U)
/*! SM0SEL45 - Submodule 0 PWM45 Control Select
 *  0b00..Generated SM0PWM45 signal is used by the deadtime logic.
 *  0b01..Inverted generated SM0PWM45 signal is used by the deadtime logic.
 *  0b10..SWCOUT[SM0OUT45] is used by the deadtime logic.
 *  0b11..PWM0_EXTB signal is used by the deadtime logic.
 */
#define PWM_DTSRCSEL_SM0SEL45(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL45_SHIFT)) & PWM_DTSRCSEL_SM0SEL45_MASK)

#define PWM_DTSRCSEL_SM0SEL23_MASK               (0xCU)
#define PWM_DTSRCSEL_SM0SEL23_SHIFT              (2U)
/*! SM0SEL23 - Submodule 0 PWM23 Control Select
 *  0b00..Generated SM0PWM23 signal is used by the deadtime logic.
 *  0b01..Inverted generated SM0PWM23 signal is used by the deadtime logic.
 *  0b10..SWCOUT[SM0OUT23] is used by the deadtime logic.
 *  0b11..PWM0_EXTA signal is used by the deadtime logic.
 */
#define PWM_DTSRCSEL_SM0SEL23(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL23_SHIFT)) & PWM_DTSRCSEL_SM0SEL23_MASK)

#define PWM_DTSRCSEL_SM1SEL45_MASK               (0x30U)
#define PWM_DTSRCSEL_SM1SEL45_SHIFT              (4U)
/*! SM1SEL45 - Submodule 1 PWM45 Control Select
 *  0b00..Generated SM1PWM45 signal is used by the deadtime logic.
 *  0b01..Inverted generated SM1PWM45 signal is used by the deadtime logic.
 *  0b10..SWCOUT[SM1OUT45] is used by the deadtime logic.
 *  0b11..PWM1_EXTB signal is used by the deadtime logic.
 */
#define PWM_DTSRCSEL_SM1SEL45(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL45_SHIFT)) & PWM_DTSRCSEL_SM1SEL45_MASK)

#define PWM_DTSRCSEL_SM1SEL23_MASK               (0xC0U)
#define PWM_DTSRCSEL_SM1SEL23_SHIFT              (6U)
/*! SM1SEL23 - Submodule 1 PWM23 Control Select
 *  0b00..Generated SM1PWM23 signal is used by the deadtime logic.
 *  0b01..Inverted generated SM1PWM23 signal is used by the deadtime logic.
 *  0b10..SWCOUT[SM1OUT23] is used by the deadtime logic.
 *  0b11..PWM1_EXTA signal is used by the deadtime logic.
 */
#define PWM_DTSRCSEL_SM1SEL23(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL23_SHIFT)) & PWM_DTSRCSEL_SM1SEL23_MASK)

#define PWM_DTSRCSEL_SM2SEL45_MASK               (0x300U)
#define PWM_DTSRCSEL_SM2SEL45_SHIFT              (8U)
/*! SM2SEL45 - Submodule 2 PWM45 Control Select
 *  0b00..Generated SM2PWM45 signal is used by the deadtime logic.
 *  0b01..Inverted generated SM2PWM45 signal is used by the deadtime logic.
 *  0b10..SWCOUT[SM2OUT45] is used by the deadtime logic.
 *  0b11..PWM2_EXTB signal is used by the deadtime logic.
 */
#define PWM_DTSRCSEL_SM2SEL45(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL45_SHIFT)) & PWM_DTSRCSEL_SM2SEL45_MASK)

#define PWM_DTSRCSEL_SM2SEL23_MASK               (0xC00U)
#define PWM_DTSRCSEL_SM2SEL23_SHIFT              (10U)
/*! SM2SEL23 - Submodule 2 PWM23 Control Select
 *  0b00..Generated SM2PWM23 signal is used by the deadtime logic.
 *  0b01..Inverted generated SM2PWM23 signal is used by the deadtime logic.
 *  0b10..SWCOUT[SM2OUT23] is used by the deadtime logic.
 *  0b11..PWM2_EXTA signal is used by the deadtime logic.
 */
#define PWM_DTSRCSEL_SM2SEL23(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL23_SHIFT)) & PWM_DTSRCSEL_SM2SEL23_MASK)

#define PWM_DTSRCSEL_SM3SEL45_MASK               (0x3000U)
#define PWM_DTSRCSEL_SM3SEL45_SHIFT              (12U)
/*! SM3SEL45 - Submodule 3 PWM45 Control Select
 *  0b00..Generated SM3PWM45 signal is used by the deadtime logic.
 *  0b01..Inverted generated SM3PWM45 signal is used by the deadtime logic.
 *  0b10..SWCOUT[SM3OUT45] is used by the deadtime logic.
 *  0b11..PWM3_EXTB signal is used by the deadtime logic.
 */
#define PWM_DTSRCSEL_SM3SEL45(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL45_SHIFT)) & PWM_DTSRCSEL_SM3SEL45_MASK)

#define PWM_DTSRCSEL_SM3SEL23_MASK               (0xC000U)
#define PWM_DTSRCSEL_SM3SEL23_SHIFT              (14U)
/*! SM3SEL23 - Submodule 3 PWM23 Control Select
 *  0b00..Generated SM3PWM23 signal is used by the deadtime logic.
 *  0b01..Inverted generated SM3PWM23 signal is used by the deadtime logic.
 *  0b10..SWCOUT[SM3OUT23] is used by the deadtime logic.
 *  0b11..PWM3_EXTA signal is used by the deadtime logic.
 */
#define PWM_DTSRCSEL_SM3SEL23(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL23_SHIFT)) & PWM_DTSRCSEL_SM3SEL23_MASK)
/*! @} */

/*! @name MCTRL - Master Control Register */
/*! @{ */

#define PWM_MCTRL_LDOK_MASK                      (0xFU)
#define PWM_MCTRL_LDOK_SHIFT                     (0U)
/*! LDOK - Load Okay
 *  0b0000..Do not load new values.
 *  0b0001..Load prescaler, modulus, and PWM values of the corresponding submodule.
 */
#define PWM_MCTRL_LDOK(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_LDOK_SHIFT)) & PWM_MCTRL_LDOK_MASK)

#define PWM_MCTRL_CLDOK_MASK                     (0xF0U)
#define PWM_MCTRL_CLDOK_SHIFT                    (4U)
/*! CLDOK - Clear Load Okay
 */
#define PWM_MCTRL_CLDOK(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_CLDOK_SHIFT)) & PWM_MCTRL_CLDOK_MASK)

#define PWM_MCTRL_RUN_MASK                       (0xF00U)
#define PWM_MCTRL_RUN_SHIFT                      (8U)
/*! RUN - Run
 *  0b0000..PWM counter is stopped, but PWM outputs will hold the current state.
 *  0b0001..PWM counter is started in the corresponding submodule.
 */
#define PWM_MCTRL_RUN(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_RUN_SHIFT)) & PWM_MCTRL_RUN_MASK)

#define PWM_MCTRL_IPOL_MASK                      (0xF000U)
#define PWM_MCTRL_IPOL_SHIFT                     (12U)
/*! IPOL - Current Polarity
 *  0b0000..PWM23 is used to generate complementary PWM pair in the corresponding submodule.
 *  0b0001..PWM45 is used to generate complementary PWM pair in the corresponding submodule.
 */
#define PWM_MCTRL_IPOL(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_IPOL_SHIFT)) & PWM_MCTRL_IPOL_MASK)
/*! @} */

/*! @name MCTRL2 - Master Control 2 Register */
/*! @{ */

#define PWM_MCTRL2_MONPLL_MASK                   (0x3U)
#define PWM_MCTRL2_MONPLL_SHIFT                  (0U)
/*! MONPLL - Monitor PLL State
 *  0b00..Not locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock will be controlled by software.
 *  0b01..Not locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL encounters problems.
 *  0b10..Locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock
 *        will be controlled by software. These bits are write protected until the next reset.
 *  0b11..Locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL
 *        encounters problems. These bits are write protected until the next reset.
 */
#define PWM_MCTRL2_MONPLL(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_MONPLL_SHIFT)) & PWM_MCTRL2_MONPLL_MASK)
/*! @} */

/*! @name FCTRL - Fault Control Register */
/*! @{ */

#define PWM_FCTRL_FIE_MASK                       (0xFU)
#define PWM_FCTRL_FIE_SHIFT                      (0U)
/*! FIE - Fault Interrupt Enables
 *  0b0000..FAULTx CPU interrupt requests disabled.
 *  0b0001..FAULTx CPU interrupt requests enabled.
 */
#define PWM_FCTRL_FIE(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FIE_SHIFT)) & PWM_FCTRL_FIE_MASK)

#define PWM_FCTRL_FSAFE_MASK                     (0xF0U)
#define PWM_FCTRL_FSAFE_SHIFT                    (4U)
/*! FSAFE - Fault Safety Mode
 *  0b0000..Normal mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the
 *          start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without regard
 *          to the state of FSTS[FFPINx]. If neither FHALF nor FFULL is set then the fault condition cannot be
 *          cleared. The PWM outputs disabled by this fault input will not be re-enabled until the actual FAULTx input
 *          signal de-asserts since the fault input will combinationally disable the PWM outputs (as programmed in
 *          DISMAPn).
 *  0b0001..Safe mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear and
 *          FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and
 *          FSTS[FFULL]. If neither FHLAF nor FFULL is set, then the fault condition cannot be cleared.
 */
#define PWM_FCTRL_FSAFE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FSAFE_SHIFT)) & PWM_FCTRL_FSAFE_MASK)

#define PWM_FCTRL_FAUTO_MASK                     (0xF00U)
#define PWM_FCTRL_FAUTO_SHIFT                    (8U)
/*! FAUTO - Automatic Fault Clearing
 *  0b0000..Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear
 *          at the start of a half cycle or full cycle depending the states of FSTS[FHALF] and FSTS[FFULL]. If
 *          neither FFULL nor FHALF is set, then the fault condition cannot be cleared. This is further controlled by
 *          FCTRL[FSAFE].
 *  0b0001..Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS[FFPINx] is clear at
 *          the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without
 *          regard to the state of FSTS[FFLAGx]. If neither FFULL nor FHALF is set, then the fault condition
 *          cannot be cleared.
 */
#define PWM_FCTRL_FAUTO(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FAUTO_SHIFT)) & PWM_FCTRL_FAUTO_MASK)

#define PWM_FCTRL_FLVL_MASK                      (0xF000U)
#define PWM_FCTRL_FLVL_SHIFT                     (12U)
/*! FLVL - Fault Level
 *  0b0000..A logic 0 on the fault input indicates a fault condition.
 *  0b0001..A logic 1 on the fault input indicates a fault condition.
 */
#define PWM_FCTRL_FLVL(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FLVL_SHIFT)) & PWM_FCTRL_FLVL_MASK)
/*! @} */

/*! @name FSTS - Fault Status Register */
/*! @{ */

#define PWM_FSTS_FFLAG_MASK                      (0xFU)
#define PWM_FSTS_FFLAG_SHIFT                     (0U)
/*! FFLAG - Fault Flags
 *  0b0000..No fault on the FAULTx pin.
 *  0b0001..Fault on the FAULTx pin.
 */
#define PWM_FSTS_FFLAG(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFLAG_SHIFT)) & PWM_FSTS_FFLAG_MASK)

#define PWM_FSTS_FFULL_MASK                      (0xF0U)
#define PWM_FSTS_FFULL_SHIFT                     (4U)
/*! FFULL - Full Cycle
 *  0b0000..PWM outputs are not re-enabled at the start of a full cycle
 *  0b0001..PWM outputs are re-enabled at the start of a full cycle
 */
#define PWM_FSTS_FFULL(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFULL_SHIFT)) & PWM_FSTS_FFULL_MASK)

#define PWM_FSTS_FFPIN_MASK                      (0xF00U)
#define PWM_FSTS_FFPIN_SHIFT                     (8U)
/*! FFPIN - Filtered Fault Pins
 */
#define PWM_FSTS_FFPIN(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFPIN_SHIFT)) & PWM_FSTS_FFPIN_MASK)

#define PWM_FSTS_FHALF_MASK                      (0xF000U)
#define PWM_FSTS_FHALF_SHIFT                     (12U)
/*! FHALF - Half Cycle Fault Recovery
 *  0b0000..PWM outputs are not re-enabled at the start of a half cycle.
 *  0b0001..PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0).
 */
#define PWM_FSTS_FHALF(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FHALF_SHIFT)) & PWM_FSTS_FHALF_MASK)
/*! @} */

/*! @name FFILT - Fault Filter Register */
/*! @{ */

#define PWM_FFILT_FILT_PER_MASK                  (0xFFU)
#define PWM_FFILT_FILT_PER_SHIFT                 (0U)
/*! FILT_PER - Fault Filter Period
 */
#define PWM_FFILT_FILT_PER(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_PER_SHIFT)) & PWM_FFILT_FILT_PER_MASK)

#define PWM_FFILT_FILT_CNT_MASK                  (0x700U)
#define PWM_FFILT_FILT_CNT_SHIFT                 (8U)
/*! FILT_CNT - Fault Filter Count
 */
#define PWM_FFILT_FILT_CNT(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_CNT_SHIFT)) & PWM_FFILT_FILT_CNT_MASK)

#define PWM_FFILT_GSTR_MASK                      (0x8000U)
#define PWM_FFILT_GSTR_SHIFT                     (15U)
/*! GSTR - Fault Glitch Stretch Enable
 *  0b0..Fault input glitch stretching is disabled.
 *  0b1..Input fault signals will be stretched to at least 2 IPBus clock cycles.
 */
#define PWM_FFILT_GSTR(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_GSTR_SHIFT)) & PWM_FFILT_GSTR_MASK)
/*! @} */

/*! @name FTST - Fault Test Register */
/*! @{ */

#define PWM_FTST_FTEST_MASK                      (0x1U)
#define PWM_FTST_FTEST_SHIFT                     (0U)
/*! FTEST - Fault Test
 *  0b0..No fault
 *  0b1..Cause a simulated fault
 */
#define PWM_FTST_FTEST(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FTST_FTEST_SHIFT)) & PWM_FTST_FTEST_MASK)
/*! @} */

/*! @name FCTRL2 - Fault Control 2 Register */
/*! @{ */

#define PWM_FCTRL2_NOCOMB_MASK                   (0xFU)
#define PWM_FCTRL2_NOCOMB_SHIFT                  (0U)
/*! NOCOMB - No Combinational Path From Fault Input To PWM Output
 *  0b0000..There is a combinational link from the fault inputs to the PWM outputs. The fault inputs are combined
 *          with the filtered and latched fault signals to disable the PWM outputs.
 *  0b0001..The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered
 *          and latched fault signals are used to disable the PWM outputs.
 */
#define PWM_FCTRL2_NOCOMB(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL2_NOCOMB_SHIFT)) & PWM_FCTRL2_NOCOMB_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group PWM_Register_Masks */


/* PWM - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral PWM0 base address */
  #define PWM0_BASE                                (0x500C3000u)
  /** Peripheral PWM0 base address */
  #define PWM0_BASE_NS                             (0x400C3000u)
  /** Peripheral PWM0 base pointer */
  #define PWM0                                     ((PWM_Type *)PWM0_BASE)
  /** Peripheral PWM0 base pointer */
  #define PWM0_NS                                  ((PWM_Type *)PWM0_BASE_NS)
  /** Peripheral PWM1 base address */
  #define PWM1_BASE                                (0x500C5000u)
  /** Peripheral PWM1 base address */
  #define PWM1_BASE_NS                             (0x400C5000u)
  /** Peripheral PWM1 base pointer */
  #define PWM1                                     ((PWM_Type *)PWM1_BASE)
  /** Peripheral PWM1 base pointer */
  #define PWM1_NS                                  ((PWM_Type *)PWM1_BASE_NS)
  /** Array initializer of PWM peripheral base addresses */
  #define PWM_BASE_ADDRS                           { PWM0_BASE, PWM1_BASE }
  /** Array initializer of PWM peripheral base pointers */
  #define PWM_BASE_PTRS                            { PWM0, PWM1 }
  /** Array initializer of PWM peripheral base addresses */
  #define PWM_BASE_ADDRS_NS                        { PWM0_BASE_NS, PWM1_BASE_NS }
  /** Array initializer of PWM peripheral base pointers */
  #define PWM_BASE_PTRS_NS                         { PWM0_NS, PWM1_NS }
#else
  /** Peripheral PWM0 base address */
  #define PWM0_BASE                                (0x400C3000u)
  /** Peripheral PWM0 base pointer */
  #define PWM0                                     ((PWM_Type *)PWM0_BASE)
  /** Peripheral PWM1 base address */
  #define PWM1_BASE                                (0x400C5000u)
  /** Peripheral PWM1 base pointer */
  #define PWM1                                     ((PWM_Type *)PWM1_BASE)
  /** Array initializer of PWM peripheral base addresses */
  #define PWM_BASE_ADDRS                           { PWM0_BASE, PWM1_BASE }
  /** Array initializer of PWM peripheral base pointers */
  #define PWM_BASE_PTRS                            { PWM0, PWM1 }
#endif
/** Interrupt vectors for the PWM peripheral type */
#define PWM_CMP_IRQS                             { { FLEXPWM0_COMPARE0_IRQn, FLEXPWM0_COMPARE1_IRQn, FLEXPWM0_COMPARE2_IRQn, FLEXPWM0_COMPARE3_IRQn }, { FLEXPWM1_COMPARE0_IRQn, FLEXPWM1_COMPARE1_IRQn, FLEXPWM1_COMPARE2_IRQn, FLEXPWM1_COMPARE3_IRQn } }
#define PWM_RELOAD_IRQS                          { { FLEXPWM0_RELOAD0_IRQn, FLEXPWM0_RELOAD1_IRQn, FLEXPWM0_RELOAD2_IRQn, FLEXPWM0_RELOAD3_IRQn }, { FLEXPWM1_RELOAD0_IRQn, FLEXPWM1_RELOAD1_IRQn, FLEXPWM1_RELOAD2_IRQn, FLEXPWM1_RELOAD3_IRQn } }
#define PWM_CAPTURE_IRQS                         { { FLEXPWM0_CAPTURE_IRQn, FLEXPWM0_CAPTURE_IRQn, FLEXPWM0_CAPTURE_IRQn, FLEXPWM0_CAPTURE_IRQn }, { FLEXPWM1_CAPTURE_IRQn, FLEXPWM1_CAPTURE_IRQn, FLEXPWM1_CAPTURE_IRQn, FLEXPWM1_CAPTURE_IRQn } }
#define PWM_FAULT_IRQS                           { FLEXPWM0_FAULT_IRQn, FLEXPWM1_FAULT_IRQn }

/*!
 * @}
 */ /* end of group PWM_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- RTC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
 * @{
 */

/** RTC - Register Layout Typedef */
typedef struct {
  __IO uint16_t YEARMON;                           /**< Year and Month Counters, offset: 0x0 */
  __IO uint16_t DAYS;                              /**< Days and Day-of-Week Counters, offset: 0x2 */
  __IO uint16_t HOURMIN;                           /**< Hours and Minutes Counters, offset: 0x4 */
  __IO uint16_t SECONDS;                           /**< Seconds Counters, offset: 0x6 */
  __IO uint16_t ALM_YEARMON;                       /**< Year and Months Alarm, offset: 0x8 */
  __IO uint16_t ALM_DAYS;                          /**< Days Alarm, offset: 0xA */
  __IO uint16_t ALM_HOURMIN;                       /**< Hours and Minutes Alarm, offset: 0xC */
  __IO uint16_t ALM_SECONDS;                       /**< Seconds Alarm, offset: 0xE */
  __IO uint16_t CTRL;                              /**< Control, offset: 0x10 */
  __IO uint16_t STATUS;                            /**< Status, offset: 0x12 */
  __IO uint16_t ISR;                               /**< Interrupt Status, offset: 0x14 */
  __IO uint16_t IER;                               /**< Interrupt Enable, offset: 0x16 */
       uint8_t RESERVED_0[8];
  __IO uint16_t GP_DATA_REG;                       /**< General Purpose Data, offset: 0x20 */
  __IO uint16_t DST_HOUR;                          /**< Daylight Saving Hour, offset: 0x22 */
  __IO uint16_t DST_MONTH;                         /**< Daylight Saving Month, offset: 0x24 */
  __IO uint16_t DST_DAY;                           /**< Daylight Saving Day, offset: 0x26 */
  __IO uint16_t COMPEN;                            /**< Compensation, offset: 0x28 */
       uint8_t RESERVED_1[4];
  __IO uint16_t TAMPER_QSCR;                       /**< Tamper Queue Status and Control, offset: 0x2E */
       uint8_t RESERVED_2[2];
  __IO uint16_t TAMPER_SCR;                        /**< Tamper Status and Control, offset: 0x32 */
  __IO uint16_t FILTER01_CFG;                      /**< Tamper 01 Filter Configuration, offset: 0x34 */
  __IO uint16_t FILTER23_CFG;                      /**< Tamper 23 Filter Configuration, offset: 0x36 */
       uint8_t RESERVED_3[8];
  __I  uint16_t TAMPER_QUEUE;                      /**< Tamper Queue, offset: 0x40 */
  __IO uint16_t CTRL2;                             /**< Control 2, offset: 0x42 */
       uint8_t RESERVED_4[1980];
  __IO uint32_t SUBSECOND_CTRL;                    /**< Sub-second control, offset: 0x800 */
  __I  uint32_t SUBSECOND_CNT;                     /**< Sub-second counter, offset: 0x804 */
       uint8_t RESERVED_5[1016];
  __IO uint32_t WAKE_TIMER_CTRL;                   /**< Wake timer control, offset: 0xC00 */
       uint8_t RESERVED_6[8];
  __IO uint32_t WAKE_TIMER_CNT;                    /**< Wake timer counter, offset: 0xC0C */
} RTC_Type;

/* ----------------------------------------------------------------------------
   -- RTC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup RTC_Register_Masks RTC Register Masks
 * @{
 */

/*! @name YEARMON - Year and Month Counters */
/*! @{ */

#define RTC_YEARMON_MON_CNT_MASK                 (0xFU)
#define RTC_YEARMON_MON_CNT_SHIFT                (0U)
/*! MON_CNT - Month Counter
 *  0b0000, 0b1101, 0b1110, 0b1111..Illegal Value
 *  0b0001..January
 *  0b0010..February
 *  0b0011..March
 *  0b0100..April
 *  0b0101..May
 *  0b0110..June
 *  0b0111..July
 *  0b1000..August
 *  0b1001..September
 *  0b1010..October
 *  0b1011..November
 *  0b1100..December
 */
#define RTC_YEARMON_MON_CNT(x)                   (((uint16_t)(((uint16_t)(x)) << RTC_YEARMON_MON_CNT_SHIFT)) & RTC_YEARMON_MON_CNT_MASK)

#define RTC_YEARMON_YROFST_MASK                  (0xFF00U)
#define RTC_YEARMON_YROFST_SHIFT                 (8U)
/*! YROFST - Year Offset Count Value
 */
#define RTC_YEARMON_YROFST(x)                    (((uint16_t)(((uint16_t)(x)) << RTC_YEARMON_YROFST_SHIFT)) & RTC_YEARMON_YROFST_MASK)
/*! @} */

/*! @name DAYS - Days and Day-of-Week Counters */
/*! @{ */

#define RTC_DAYS_DAY_CNT_MASK                    (0x1FU)
#define RTC_DAYS_DAY_CNT_SHIFT                   (0U)
/*! DAY_CNT - Days Counter Value
 */
#define RTC_DAYS_DAY_CNT(x)                      (((uint16_t)(((uint16_t)(x)) << RTC_DAYS_DAY_CNT_SHIFT)) & RTC_DAYS_DAY_CNT_MASK)

#define RTC_DAYS_DOW_MASK                        (0x700U)
#define RTC_DAYS_DOW_SHIFT                       (8U)
/*! DOW - Day of Week Counter Value
 *  0b000..Sunday
 *  0b001..Monday
 *  0b010..Tuesday
 *  0b011..Wednesday
 *  0b100..Thursday
 *  0b101..Friday
 *  0b110..Saturday
 *  0b111..
 */
#define RTC_DAYS_DOW(x)                          (((uint16_t)(((uint16_t)(x)) << RTC_DAYS_DOW_SHIFT)) & RTC_DAYS_DOW_MASK)
/*! @} */

/*! @name HOURMIN - Hours and Minutes Counters */
/*! @{ */

#define RTC_HOURMIN_MIN_CNT_MASK                 (0x3FU)
#define RTC_HOURMIN_MIN_CNT_SHIFT                (0U)
/*! MIN_CNT - Minutes Counter Value
 */
#define RTC_HOURMIN_MIN_CNT(x)                   (((uint16_t)(((uint16_t)(x)) << RTC_HOURMIN_MIN_CNT_SHIFT)) & RTC_HOURMIN_MIN_CNT_MASK)

#define RTC_HOURMIN_HOUR_CNT_MASK                (0x1F00U)
#define RTC_HOURMIN_HOUR_CNT_SHIFT               (8U)
/*! HOUR_CNT - Hours Counter Value
 */
#define RTC_HOURMIN_HOUR_CNT(x)                  (((uint16_t)(((uint16_t)(x)) << RTC_HOURMIN_HOUR_CNT_SHIFT)) & RTC_HOURMIN_HOUR_CNT_MASK)
/*! @} */

/*! @name SECONDS - Seconds Counters */
/*! @{ */

#define RTC_SECONDS_SEC_CNT_MASK                 (0x3FU)
#define RTC_SECONDS_SEC_CNT_SHIFT                (0U)
/*! SEC_CNT - Seconds Counter Value
 */
#define RTC_SECONDS_SEC_CNT(x)                   (((uint16_t)(((uint16_t)(x)) << RTC_SECONDS_SEC_CNT_SHIFT)) & RTC_SECONDS_SEC_CNT_MASK)
/*! @} */

/*! @name ALM_YEARMON - Year and Months Alarm */
/*! @{ */

#define RTC_ALM_YEARMON_ALM_MON_MASK             (0xFU)
#define RTC_ALM_YEARMON_ALM_MON_SHIFT            (0U)
/*! ALM_MON - Months Value for Alarm
 */
#define RTC_ALM_YEARMON_ALM_MON(x)               (((uint16_t)(((uint16_t)(x)) << RTC_ALM_YEARMON_ALM_MON_SHIFT)) & RTC_ALM_YEARMON_ALM_MON_MASK)

#define RTC_ALM_YEARMON_ALM_YEAR_MASK            (0xFF00U)
#define RTC_ALM_YEARMON_ALM_YEAR_SHIFT           (8U)
/*! ALM_YEAR - Year Value for Alarm
 */
#define RTC_ALM_YEARMON_ALM_YEAR(x)              (((uint16_t)(((uint16_t)(x)) << RTC_ALM_YEARMON_ALM_YEAR_SHIFT)) & RTC_ALM_YEARMON_ALM_YEAR_MASK)
/*! @} */

/*! @name ALM_DAYS - Days Alarm */
/*! @{ */

#define RTC_ALM_DAYS_ALM_DAY_MASK                (0x1FU)
#define RTC_ALM_DAYS_ALM_DAY_SHIFT               (0U)
/*! ALM_DAY - Days Value for Alarm
 */
#define RTC_ALM_DAYS_ALM_DAY(x)                  (((uint16_t)(((uint16_t)(x)) << RTC_ALM_DAYS_ALM_DAY_SHIFT)) & RTC_ALM_DAYS_ALM_DAY_MASK)
/*! @} */

/*! @name ALM_HOURMIN - Hours and Minutes Alarm */
/*! @{ */

#define RTC_ALM_HOURMIN_ALM_MIN_MASK             (0x3FU)
#define RTC_ALM_HOURMIN_ALM_MIN_SHIFT            (0U)
/*! ALM_MIN - Minutes Value for Alarm
 */
#define RTC_ALM_HOURMIN_ALM_MIN(x)               (((uint16_t)(((uint16_t)(x)) << RTC_ALM_HOURMIN_ALM_MIN_SHIFT)) & RTC_ALM_HOURMIN_ALM_MIN_MASK)

#define RTC_ALM_HOURMIN_ALM_HOUR_MASK            (0x1F00U)
#define RTC_ALM_HOURMIN_ALM_HOUR_SHIFT           (8U)
/*! ALM_HOUR - Hours Value for Alarm
 */
#define RTC_ALM_HOURMIN_ALM_HOUR(x)              (((uint16_t)(((uint16_t)(x)) << RTC_ALM_HOURMIN_ALM_HOUR_SHIFT)) & RTC_ALM_HOURMIN_ALM_HOUR_MASK)
/*! @} */

/*! @name ALM_SECONDS - Seconds Alarm */
/*! @{ */

#define RTC_ALM_SECONDS_ALM_SEC_MASK             (0x3FU)
#define RTC_ALM_SECONDS_ALM_SEC_SHIFT            (0U)
/*! ALM_SEC - Seconds Alarm Value
 */
#define RTC_ALM_SECONDS_ALM_SEC(x)               (((uint16_t)(((uint16_t)(x)) << RTC_ALM_SECONDS_ALM_SEC_SHIFT)) & RTC_ALM_SECONDS_ALM_SEC_MASK)

#define RTC_ALM_SECONDS_DEC_SEC_MASK             (0x100U)
#define RTC_ALM_SECONDS_DEC_SEC_SHIFT            (8U)
/*! DEC_SEC - Decrement Seconds Counter by 1.
 */
#define RTC_ALM_SECONDS_DEC_SEC(x)               (((uint16_t)(((uint16_t)(x)) << RTC_ALM_SECONDS_DEC_SEC_SHIFT)) & RTC_ALM_SECONDS_DEC_SEC_MASK)

#define RTC_ALM_SECONDS_INC_SEC_MASK             (0x200U)
#define RTC_ALM_SECONDS_INC_SEC_SHIFT            (9U)
/*! INC_SEC - Increment Seconds Counter by 1.
 */
#define RTC_ALM_SECONDS_INC_SEC(x)               (((uint16_t)(((uint16_t)(x)) << RTC_ALM_SECONDS_INC_SEC_SHIFT)) & RTC_ALM_SECONDS_INC_SEC_MASK)
/*! @} */

/*! @name CTRL - Control */
/*! @{ */

#define RTC_CTRL_FINEEN_MASK                     (0x1U)
#define RTC_CTRL_FINEEN_SHIFT                    (0U)
/*! FINEEN - Fine Compensation Enable
 *  0b1..Fine compensation is enabled.
 *  0b0..Fine compensation is disabled
 */
#define RTC_CTRL_FINEEN(x)                       (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_FINEEN_SHIFT)) & RTC_CTRL_FINEEN_MASK)

#define RTC_CTRL_COMP_EN_MASK                    (0x2U)
#define RTC_CTRL_COMP_EN_SHIFT                   (1U)
/*! COMP_EN - Compensation Enable
 *  0b0..Coarse Compensation is disabled.
 *  0b1..Coarse Compensation is enabled.
 */
#define RTC_CTRL_COMP_EN(x)                      (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_COMP_EN_SHIFT)) & RTC_CTRL_COMP_EN_MASK)

#define RTC_CTRL_ALM_MATCH_MASK                  (0xCU)
#define RTC_CTRL_ALM_MATCH_SHIFT                 (2U)
/*! ALM_MATCH - Alarm Match
 *  0b00..Only Seconds, Minutes, and Hours matched.
 *  0b01..Only Seconds, Minutes, Hours, and Days matched.
 *  0b10..Only Seconds, Minutes, Hours, Days, and Months matched.
 *  0b11..Only Seconds, Minutes, Hours, Days, Months, and Year (offset) matched.
 */
#define RTC_CTRL_ALM_MATCH(x)                    (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_ALM_MATCH_SHIFT)) & RTC_CTRL_ALM_MATCH_MASK)

#define RTC_CTRL_TIMER_STB_MASK_MASK             (0x10U)
#define RTC_CTRL_TIMER_STB_MASK_SHIFT            (4U)
/*! TIMER_STB_MASK - Sampling Timer Clocks Mask
 *  0b1..Sampling clocks are gated in standby mode
 *  0b0..Sampling clocks are not gated when in standby mode
 */
#define RTC_CTRL_TIMER_STB_MASK(x)               (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_TIMER_STB_MASK_SHIFT)) & RTC_CTRL_TIMER_STB_MASK_MASK)

#define RTC_CTRL_DST_EN_MASK                     (0x40U)
#define RTC_CTRL_DST_EN_SHIFT                    (6U)
/*! DST_EN - Daylight Saving Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define RTC_CTRL_DST_EN(x)                       (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_DST_EN_SHIFT)) & RTC_CTRL_DST_EN_MASK)

#define RTC_CTRL_SWR_MASK                        (0x100U)
#define RTC_CTRL_SWR_SHIFT                       (8U)
/*! SWR - Software Reset
 *  0b0..Software Reset cleared
 *  0b1..Software Reset asserted
 */
#define RTC_CTRL_SWR(x)                          (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_SWR_SHIFT)) & RTC_CTRL_SWR_MASK)

#define RTC_CTRL_CLKOUT_MASK                     (0x6000U)
#define RTC_CTRL_CLKOUT_SHIFT                    (13U)
/*! CLKOUT - RTC Clock Output Selection
 *  0b00..No Output Clock
 *  0b01..Fine 1 Hz Clock with both precise edges
 *  0b10..32.768 kHz Clock
 *  0b11..Coarse 1 Hz Clock with both precise edges
 */
#define RTC_CTRL_CLKOUT(x)                       (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_CLKOUT_SHIFT)) & RTC_CTRL_CLKOUT_MASK)
/*! @} */

/*! @name STATUS - Status */
/*! @{ */

#define RTC_STATUS_INVAL_BIT_MASK                (0x1U)
#define RTC_STATUS_INVAL_BIT_SHIFT               (0U)
/*! INVAL_BIT - Invalidate CPU Read/Write Access
 *  0b0..Time /Date Counters can be read/written. Time /Date is valid.
 *  0b1..Time /Date Counter values are changing or Time /Date is invalid and cannot be read or written.
 */
#define RTC_STATUS_INVAL_BIT(x)                  (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_INVAL_BIT_SHIFT)) & RTC_STATUS_INVAL_BIT_MASK)

#define RTC_STATUS_WRITE_PROT_EN_MASK            (0x2U)
#define RTC_STATUS_WRITE_PROT_EN_SHIFT           (1U)
/*! WRITE_PROT_EN - Write Protect Enable Status
 *  0b0..Registers are unlocked and can be accessed.
 *  0b1..Registers are locked and in read-only mode.
 */
#define RTC_STATUS_WRITE_PROT_EN(x)              (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_WRITE_PROT_EN_SHIFT)) & RTC_STATUS_WRITE_PROT_EN_MASK)

#define RTC_STATUS_CPU_LOW_VOLT_MASK             (0x4U)
#define RTC_STATUS_CPU_LOW_VOLT_SHIFT            (2U)
/*! CPU_LOW_VOLT - CPU Low Voltage Warning Status
 *  0b0..CPU in Normal Operating Voltage.
 *  0b1..CPU Voltage is below Normal Operating Voltage. RTC Registers in read-only mode.
 */
#define RTC_STATUS_CPU_LOW_VOLT(x)               (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_CPU_LOW_VOLT_SHIFT)) & RTC_STATUS_CPU_LOW_VOLT_MASK)

#define RTC_STATUS_RST_SRC_MASK                  (0x8U)
#define RTC_STATUS_RST_SRC_SHIFT                 (3U)
/*! RST_SRC - Reset Source
 *  0b0..Standby Mode Exit
 *  0b1..Power-On Reset
 */
#define RTC_STATUS_RST_SRC(x)                    (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_RST_SRC_SHIFT)) & RTC_STATUS_RST_SRC_MASK)

#define RTC_STATUS_CMP_INT_MASK                  (0x20U)
#define RTC_STATUS_CMP_INT_SHIFT                 (5U)
/*! CMP_INT - Compensation Interval
 */
#define RTC_STATUS_CMP_INT(x)                    (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_CMP_INT_SHIFT)) & RTC_STATUS_CMP_INT_MASK)

#define RTC_STATUS_WE_MASK                       (0xC0U)
#define RTC_STATUS_WE_SHIFT                      (6U)
/*! WE - Write Enable
 *  0b10..Enable Write Protection - Registers are locked.
 *  0b00, 0b01, 0b11, 0b10..Disable Write Protection - Registers are unlocked.
 */
#define RTC_STATUS_WE(x)                         (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_WE_SHIFT)) & RTC_STATUS_WE_MASK)

#define RTC_STATUS_BUS_ERR_MASK                  (0x100U)
#define RTC_STATUS_BUS_ERR_SHIFT                 (8U)
/*! BUS_ERR - Bus Error
 *  0b0..Read and Write accesses are normal.
 *  0b1..Read or Write accesses occurred when INVAL_BIT was asserted.
 */
#define RTC_STATUS_BUS_ERR(x)                    (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_BUS_ERR_SHIFT)) & RTC_STATUS_BUS_ERR_MASK)

#define RTC_STATUS_CMP_DONE_MASK                 (0x800U)
#define RTC_STATUS_CMP_DONE_SHIFT                (11U)
/*! CMP_DONE - Compensation Done
 *  0b0..Compensation busy or not enabled
 *  0b1..Compensation completed
 */
#define RTC_STATUS_CMP_DONE(x)                   (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_CMP_DONE_SHIFT)) & RTC_STATUS_CMP_DONE_MASK)
/*! @} */

/*! @name ISR - Interrupt Status */
/*! @{ */

#define RTC_ISR_TAMPER_IS_MASK                   (0x1U)
#define RTC_ISR_TAMPER_IS_SHIFT                  (0U)
/*! TAMPER_IS - Tamper Interrupt Status
 *  0b0..Interrupt is de-asserted.
 *  0b1..Interrupt is asserted (Default on reset) .
 */
#define RTC_ISR_TAMPER_IS(x)                     (((uint16_t)(((uint16_t)(x)) << RTC_ISR_TAMPER_IS_SHIFT)) & RTC_ISR_TAMPER_IS_MASK)

#define RTC_ISR_ALM_IS_MASK                      (0x4U)
#define RTC_ISR_ALM_IS_SHIFT                     (2U)
/*! ALM_IS - Alarm Interrupt Status
 *  0b0..Interrupt is de-asserted.
 *  0b1..Interrupt is asserted.
 */
#define RTC_ISR_ALM_IS(x)                        (((uint16_t)(((uint16_t)(x)) << RTC_ISR_ALM_IS_SHIFT)) & RTC_ISR_ALM_IS_MASK)

#define RTC_ISR_DAY_IS_MASK                      (0x8U)
#define RTC_ISR_DAY_IS_SHIFT                     (3U)
/*! DAY_IS - Days Interrupt Status
 *  0b0..Interrupt is de-asserted.
 *  0b1..Interrupt is asserted.
 */
#define RTC_ISR_DAY_IS(x)                        (((uint16_t)(((uint16_t)(x)) << RTC_ISR_DAY_IS_SHIFT)) & RTC_ISR_DAY_IS_MASK)

#define RTC_ISR_HOUR_IS_MASK                     (0x10U)
#define RTC_ISR_HOUR_IS_SHIFT                    (4U)
/*! HOUR_IS - Hours Interrupt Status
 *  0b0..Interrupt is de-asserted.
 *  0b1..Interrupt is asserted.
 */
#define RTC_ISR_HOUR_IS(x)                       (((uint16_t)(((uint16_t)(x)) << RTC_ISR_HOUR_IS_SHIFT)) & RTC_ISR_HOUR_IS_MASK)

#define RTC_ISR_MIN_IS_MASK                      (0x20U)
#define RTC_ISR_MIN_IS_SHIFT                     (5U)
/*! MIN_IS - Minutes Interrupt Status
 *  0b0..Interrupt is de-asserted.
 *  0b1..Interrupt is asserted.
 */
#define RTC_ISR_MIN_IS(x)                        (((uint16_t)(((uint16_t)(x)) << RTC_ISR_MIN_IS_SHIFT)) & RTC_ISR_MIN_IS_MASK)

#define RTC_ISR_IS_1HZ_MASK                      (0x40U)
#define RTC_ISR_IS_1HZ_SHIFT                     (6U)
/*! IS_1HZ - 1 Hz Interval Interrupt Status
 *  0b0..Interrupt is de-asserted.
 *  0b1..Interrupt is asserted.
 */
#define RTC_ISR_IS_1HZ(x)                        (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_1HZ_SHIFT)) & RTC_ISR_IS_1HZ_MASK)

#define RTC_ISR_IS_2HZ_MASK                      (0x80U)
#define RTC_ISR_IS_2HZ_SHIFT                     (7U)
/*! IS_2HZ - 2 Hz Interval Interrupt Status
 *  0b0..Interrupt is de-asserted.
 *  0b1..Interrupt is asserted.
 */
#define RTC_ISR_IS_2HZ(x)                        (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_2HZ_SHIFT)) & RTC_ISR_IS_2HZ_MASK)

#define RTC_ISR_IS_4HZ_MASK                      (0x100U)
#define RTC_ISR_IS_4HZ_SHIFT                     (8U)
/*! IS_4HZ - 4 Hz Interval Interrupt Status
 *  0b0..Interrupt is de-asserted.
 *  0b1..Interrupt is asserted.
 */
#define RTC_ISR_IS_4HZ(x)                        (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_4HZ_SHIFT)) & RTC_ISR_IS_4HZ_MASK)

#define RTC_ISR_IS_8HZ_MASK                      (0x200U)
#define RTC_ISR_IS_8HZ_SHIFT                     (9U)
/*! IS_8HZ - 8 Hz Interval Interrupt Status
 *  0b0..Interrupt is de-asserted.
 *  0b1..Interrupt is asserted.
 */
#define RTC_ISR_IS_8HZ(x)                        (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_8HZ_SHIFT)) & RTC_ISR_IS_8HZ_MASK)

#define RTC_ISR_IS_16HZ_MASK                     (0x400U)
#define RTC_ISR_IS_16HZ_SHIFT                    (10U)
/*! IS_16HZ - 16 Hz Interval Interrupt Status
 *  0b0..Interrupt is de-asserted.
 *  0b1..Interrupt is asserted.
 */
#define RTC_ISR_IS_16HZ(x)                       (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_16HZ_SHIFT)) & RTC_ISR_IS_16HZ_MASK)

#define RTC_ISR_IS_32HZ_MASK                     (0x800U)
#define RTC_ISR_IS_32HZ_SHIFT                    (11U)
/*! IS_32HZ - 32 Hz Interval Interrupt Status
 *  0b0..Interrupt is de-asserted.
 *  0b1..Interrupt is asserted.
 */
#define RTC_ISR_IS_32HZ(x)                       (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_32HZ_SHIFT)) & RTC_ISR_IS_32HZ_MASK)

#define RTC_ISR_IS_64HZ_MASK                     (0x1000U)
#define RTC_ISR_IS_64HZ_SHIFT                    (12U)
/*! IS_64HZ - 64 Hz Interval Interrupt Status
 *  0b0..Interrupt is de-asserted.
 *  0b1..Interrupt is asserted.
 */
#define RTC_ISR_IS_64HZ(x)                       (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_64HZ_SHIFT)) & RTC_ISR_IS_64HZ_MASK)

#define RTC_ISR_IS_128HZ_MASK                    (0x2000U)
#define RTC_ISR_IS_128HZ_SHIFT                   (13U)
/*! IS_128HZ - 128 Hz Interval Interrupt Status
 *  0b0..Interrupt is de-asserted.
 *  0b1..Interrupt is asserted.
 */
#define RTC_ISR_IS_128HZ(x)                      (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_128HZ_SHIFT)) & RTC_ISR_IS_128HZ_MASK)

#define RTC_ISR_IS_256HZ_MASK                    (0x4000U)
#define RTC_ISR_IS_256HZ_SHIFT                   (14U)
/*! IS_256HZ - 256 Hz Interval Interrupt Status
 *  0b0..Interrupt is de-asserted.
 *  0b1..Interrupt is asserted.
 */
#define RTC_ISR_IS_256HZ(x)                      (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_256HZ_SHIFT)) & RTC_ISR_IS_256HZ_MASK)

#define RTC_ISR_IS_512HZ_MASK                    (0x8000U)
#define RTC_ISR_IS_512HZ_SHIFT                   (15U)
/*! IS_512HZ - 512 Hz Interval Interrupt Status
 *  0b0..Interrupt is de-asserted.
 *  0b1..Interrupt is asserted.
 */
#define RTC_ISR_IS_512HZ(x)                      (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_512HZ_SHIFT)) & RTC_ISR_IS_512HZ_MASK)
/*! @} */

/*! @name IER - Interrupt Enable */
/*! @{ */

#define RTC_IER_TAMPER_IE_MASK                   (0x1U)
#define RTC_IER_TAMPER_IE_SHIFT                  (0U)
/*! TAMPER_IE - Tamper Interrupt Enable
 *  0b0..Interrupt is disabled.
 *  0b1..Interrupt is enabled (Default on reset).
 */
#define RTC_IER_TAMPER_IE(x)                     (((uint16_t)(((uint16_t)(x)) << RTC_IER_TAMPER_IE_SHIFT)) & RTC_IER_TAMPER_IE_MASK)

#define RTC_IER_ALM_IE_MASK                      (0x4U)
#define RTC_IER_ALM_IE_SHIFT                     (2U)
/*! ALM_IE - Alarm Interrupt Enable
 *  0b0..Interrupt is disabled.
 *  0b1..Interrupt is enabled.
 */
#define RTC_IER_ALM_IE(x)                        (((uint16_t)(((uint16_t)(x)) << RTC_IER_ALM_IE_SHIFT)) & RTC_IER_ALM_IE_MASK)

#define RTC_IER_DAY_IE_MASK                      (0x8U)
#define RTC_IER_DAY_IE_SHIFT                     (3U)
/*! DAY_IE - Days Interrupt Enable
 *  0b0..Interrupt is disabled.
 *  0b1..Interrupt is enabled.
 */
#define RTC_IER_DAY_IE(x)                        (((uint16_t)(((uint16_t)(x)) << RTC_IER_DAY_IE_SHIFT)) & RTC_IER_DAY_IE_MASK)

#define RTC_IER_HOUR_IE_MASK                     (0x10U)
#define RTC_IER_HOUR_IE_SHIFT                    (4U)
/*! HOUR_IE - Hours Interrupt Enable
 *  0b0..Interrupt is disabled.
 *  0b1..Interrupt is enabled.
 */
#define RTC_IER_HOUR_IE(x)                       (((uint16_t)(((uint16_t)(x)) << RTC_IER_HOUR_IE_SHIFT)) & RTC_IER_HOUR_IE_MASK)

#define RTC_IER_MIN_IE_MASK                      (0x20U)
#define RTC_IER_MIN_IE_SHIFT                     (5U)
/*! MIN_IE - Minutes Interrupt Enable
 *  0b0..Interrupt is disabled.
 *  0b1..Interrupt is enabled.
 */
#define RTC_IER_MIN_IE(x)                        (((uint16_t)(((uint16_t)(x)) << RTC_IER_MIN_IE_SHIFT)) & RTC_IER_MIN_IE_MASK)

#define RTC_IER_IE_1HZ_MASK                      (0x40U)
#define RTC_IER_IE_1HZ_SHIFT                     (6U)
/*! IE_1HZ - 1 Hz Interval Interrupt Enable
 *  0b0..Interrupt is disabled.
 *  0b1..Interrupt is enabled.
 */
#define RTC_IER_IE_1HZ(x)                        (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_1HZ_SHIFT)) & RTC_IER_IE_1HZ_MASK)

#define RTC_IER_IE_2HZ_MASK                      (0x80U)
#define RTC_IER_IE_2HZ_SHIFT                     (7U)
/*! IE_2HZ - 2 Hz Interval Interrupt Enable
 *  0b0..Interrupt is disabled.
 *  0b1..Interrupt is enabled.
 */
#define RTC_IER_IE_2HZ(x)                        (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_2HZ_SHIFT)) & RTC_IER_IE_2HZ_MASK)

#define RTC_IER_IE_4HZ_MASK                      (0x100U)
#define RTC_IER_IE_4HZ_SHIFT                     (8U)
/*! IE_4HZ - 4 Hz Interval Interrupt Enable
 *  0b0..Interrupt is disabled.
 *  0b1..Interrupt is enabled.
 */
#define RTC_IER_IE_4HZ(x)                        (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_4HZ_SHIFT)) & RTC_IER_IE_4HZ_MASK)

#define RTC_IER_IE_8HZ_MASK                      (0x200U)
#define RTC_IER_IE_8HZ_SHIFT                     (9U)
/*! IE_8HZ - 8 Hz Interval Interrupt Enable
 *  0b0..Interrupt is disabled.
 *  0b1..Interrupt is enabled.
 */
#define RTC_IER_IE_8HZ(x)                        (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_8HZ_SHIFT)) & RTC_IER_IE_8HZ_MASK)

#define RTC_IER_IE_16HZ_MASK                     (0x400U)
#define RTC_IER_IE_16HZ_SHIFT                    (10U)
/*! IE_16HZ - 16 Hz Interval Interrupt Enable
 *  0b0..Interrupt is disabled.
 *  0b1..Interrupt is enabled.
 */
#define RTC_IER_IE_16HZ(x)                       (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_16HZ_SHIFT)) & RTC_IER_IE_16HZ_MASK)

#define RTC_IER_IE_32HZ_MASK                     (0x800U)
#define RTC_IER_IE_32HZ_SHIFT                    (11U)
/*! IE_32HZ - 32 Hz Interval Interrupt Enable
 *  0b0..Interrupt is disabled.
 *  0b1..Interrupt is enabled.
 */
#define RTC_IER_IE_32HZ(x)                       (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_32HZ_SHIFT)) & RTC_IER_IE_32HZ_MASK)

#define RTC_IER_IE_64HZ_MASK                     (0x1000U)
#define RTC_IER_IE_64HZ_SHIFT                    (12U)
/*! IE_64HZ - 64 Hz Interval Interrupt Enable
 *  0b0..Interrupt is disabled.
 *  0b1..Interrupt is enabled.
 */
#define RTC_IER_IE_64HZ(x)                       (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_64HZ_SHIFT)) & RTC_IER_IE_64HZ_MASK)

#define RTC_IER_IE_128HZ_MASK                    (0x2000U)
#define RTC_IER_IE_128HZ_SHIFT                   (13U)
/*! IE_128HZ - 128 Hz Interval Interrupt Enable
 *  0b0..Interrupt is disabled.
 *  0b1..Interrupt is enabled.
 */
#define RTC_IER_IE_128HZ(x)                      (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_128HZ_SHIFT)) & RTC_IER_IE_128HZ_MASK)

#define RTC_IER_IE_256HZ_MASK                    (0x4000U)
#define RTC_IER_IE_256HZ_SHIFT                   (14U)
/*! IE_256HZ - 256 Hz Interval Interrupt Enable
 *  0b0..Interrupt is disabled.
 *  0b1..Interrupt is enabled.
 */
#define RTC_IER_IE_256HZ(x)                      (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_256HZ_SHIFT)) & RTC_IER_IE_256HZ_MASK)

#define RTC_IER_IE_512HZ_MASK                    (0x8000U)
#define RTC_IER_IE_512HZ_SHIFT                   (15U)
/*! IE_512HZ - 512 Hz Interval Interrupt Enable
 *  0b0..Interrupt is disabled.
 *  0b1..Interrupt is enabled.
 */
#define RTC_IER_IE_512HZ(x)                      (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_512HZ_SHIFT)) & RTC_IER_IE_512HZ_MASK)
/*! @} */

/*! @name GP_DATA_REG - General Purpose Data */
/*! @{ */

#define RTC_GP_DATA_REG_CFG0_MASK                (0x1U)
#define RTC_GP_DATA_REG_CFG0_SHIFT               (0U)
/*! CFG0 - CFGn
 */
#define RTC_GP_DATA_REG_CFG0(x)                  (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG0_SHIFT)) & RTC_GP_DATA_REG_CFG0_MASK)

#define RTC_GP_DATA_REG_CFG1_MASK                (0x2U)
#define RTC_GP_DATA_REG_CFG1_SHIFT               (1U)
/*! CFG1 - CFGn
 */
#define RTC_GP_DATA_REG_CFG1(x)                  (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG1_SHIFT)) & RTC_GP_DATA_REG_CFG1_MASK)

#define RTC_GP_DATA_REG_CFG2_MASK                (0x4U)
#define RTC_GP_DATA_REG_CFG2_SHIFT               (2U)
/*! CFG2 - CFGn
 */
#define RTC_GP_DATA_REG_CFG2(x)                  (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG2_SHIFT)) & RTC_GP_DATA_REG_CFG2_MASK)

#define RTC_GP_DATA_REG_CFG3_MASK                (0x8U)
#define RTC_GP_DATA_REG_CFG3_SHIFT               (3U)
/*! CFG3 - CFGn
 */
#define RTC_GP_DATA_REG_CFG3(x)                  (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG3_SHIFT)) & RTC_GP_DATA_REG_CFG3_MASK)

#define RTC_GP_DATA_REG_CFG4_MASK                (0x10U)
#define RTC_GP_DATA_REG_CFG4_SHIFT               (4U)
/*! CFG4 - CFGn
 */
#define RTC_GP_DATA_REG_CFG4(x)                  (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG4_SHIFT)) & RTC_GP_DATA_REG_CFG4_MASK)

#define RTC_GP_DATA_REG_CFG5_MASK                (0x20U)
#define RTC_GP_DATA_REG_CFG5_SHIFT               (5U)
/*! CFG5 - CFGn
 */
#define RTC_GP_DATA_REG_CFG5(x)                  (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG5_SHIFT)) & RTC_GP_DATA_REG_CFG5_MASK)

#define RTC_GP_DATA_REG_CFG6_MASK                (0x40U)
#define RTC_GP_DATA_REG_CFG6_SHIFT               (6U)
/*! CFG6 - CFGn
 */
#define RTC_GP_DATA_REG_CFG6(x)                  (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG6_SHIFT)) & RTC_GP_DATA_REG_CFG6_MASK)

#define RTC_GP_DATA_REG_CFG7_MASK                (0x80U)
#define RTC_GP_DATA_REG_CFG7_SHIFT               (7U)
/*! CFG7 - CFGn
 */
#define RTC_GP_DATA_REG_CFG7(x)                  (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG7_SHIFT)) & RTC_GP_DATA_REG_CFG7_MASK)

#define RTC_GP_DATA_REG_CFG8_MASK                (0x100U)
#define RTC_GP_DATA_REG_CFG8_SHIFT               (8U)
/*! CFG8 - CFGn
 */
#define RTC_GP_DATA_REG_CFG8(x)                  (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG8_SHIFT)) & RTC_GP_DATA_REG_CFG8_MASK)

#define RTC_GP_DATA_REG_CFG9_MASK                (0x200U)
#define RTC_GP_DATA_REG_CFG9_SHIFT               (9U)
/*! CFG9 - CFGn
 */
#define RTC_GP_DATA_REG_CFG9(x)                  (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG9_SHIFT)) & RTC_GP_DATA_REG_CFG9_MASK)

#define RTC_GP_DATA_REG_CFG10_MASK               (0x400U)
#define RTC_GP_DATA_REG_CFG10_SHIFT              (10U)
/*! CFG10 - CFGn
 */
#define RTC_GP_DATA_REG_CFG10(x)                 (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG10_SHIFT)) & RTC_GP_DATA_REG_CFG10_MASK)

#define RTC_GP_DATA_REG_CFG11_MASK               (0x800U)
#define RTC_GP_DATA_REG_CFG11_SHIFT              (11U)
/*! CFG11 - CFGn
 */
#define RTC_GP_DATA_REG_CFG11(x)                 (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG11_SHIFT)) & RTC_GP_DATA_REG_CFG11_MASK)

#define RTC_GP_DATA_REG_CFG12_MASK               (0x1000U)
#define RTC_GP_DATA_REG_CFG12_SHIFT              (12U)
/*! CFG12 - CFGn
 */
#define RTC_GP_DATA_REG_CFG12(x)                 (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG12_SHIFT)) & RTC_GP_DATA_REG_CFG12_MASK)

#define RTC_GP_DATA_REG_CFG13_MASK               (0x2000U)
#define RTC_GP_DATA_REG_CFG13_SHIFT              (13U)
/*! CFG13 - CFGn
 */
#define RTC_GP_DATA_REG_CFG13(x)                 (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG13_SHIFT)) & RTC_GP_DATA_REG_CFG13_MASK)

#define RTC_GP_DATA_REG_CFG14_MASK               (0x4000U)
#define RTC_GP_DATA_REG_CFG14_SHIFT              (14U)
/*! CFG14 - CFGn
 */
#define RTC_GP_DATA_REG_CFG14(x)                 (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG14_SHIFT)) & RTC_GP_DATA_REG_CFG14_MASK)

#define RTC_GP_DATA_REG_CFG15_MASK               (0x8000U)
#define RTC_GP_DATA_REG_CFG15_SHIFT              (15U)
/*! CFG15 - CFGn
 */
#define RTC_GP_DATA_REG_CFG15(x)                 (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG15_SHIFT)) & RTC_GP_DATA_REG_CFG15_MASK)
/*! @} */

/*! @name DST_HOUR - Daylight Saving Hour */
/*! @{ */

#define RTC_DST_HOUR_DST_END_HOUR_MASK           (0x1FU)
#define RTC_DST_HOUR_DST_END_HOUR_SHIFT          (0U)
/*! DST_END_HOUR - Daylight Saving Time (DST) Hours End Value
 */
#define RTC_DST_HOUR_DST_END_HOUR(x)             (((uint16_t)(((uint16_t)(x)) << RTC_DST_HOUR_DST_END_HOUR_SHIFT)) & RTC_DST_HOUR_DST_END_HOUR_MASK)

#define RTC_DST_HOUR_DST_START_HOUR_MASK         (0x1F00U)
#define RTC_DST_HOUR_DST_START_HOUR_SHIFT        (8U)
/*! DST_START_HOUR - Daylight Saving Time (DST) Hours Start Value
 */
#define RTC_DST_HOUR_DST_START_HOUR(x)           (((uint16_t)(((uint16_t)(x)) << RTC_DST_HOUR_DST_START_HOUR_SHIFT)) & RTC_DST_HOUR_DST_START_HOUR_MASK)
/*! @} */

/*! @name DST_MONTH - Daylight Saving Month */
/*! @{ */

#define RTC_DST_MONTH_DST_END_MONTH_MASK         (0xFU)
#define RTC_DST_MONTH_DST_END_MONTH_SHIFT        (0U)
/*! DST_END_MONTH - Daylight Saving Time (DST) Month End Value
 */
#define RTC_DST_MONTH_DST_END_MONTH(x)           (((uint16_t)(((uint16_t)(x)) << RTC_DST_MONTH_DST_END_MONTH_SHIFT)) & RTC_DST_MONTH_DST_END_MONTH_MASK)

#define RTC_DST_MONTH_DST_START_MONTH_MASK       (0xF00U)
#define RTC_DST_MONTH_DST_START_MONTH_SHIFT      (8U)
/*! DST_START_MONTH - Daylight Saving Time (DST) Month Start Value
 */
#define RTC_DST_MONTH_DST_START_MONTH(x)         (((uint16_t)(((uint16_t)(x)) << RTC_DST_MONTH_DST_START_MONTH_SHIFT)) & RTC_DST_MONTH_DST_START_MONTH_MASK)
/*! @} */

/*! @name DST_DAY - Daylight Saving Day */
/*! @{ */

#define RTC_DST_DAY_DST_END_DAY_MASK             (0x1FU)
#define RTC_DST_DAY_DST_END_DAY_SHIFT            (0U)
/*! DST_END_DAY - Daylight Saving Time (DST) Day End Value
 */
#define RTC_DST_DAY_DST_END_DAY(x)               (((uint16_t)(((uint16_t)(x)) << RTC_DST_DAY_DST_END_DAY_SHIFT)) & RTC_DST_DAY_DST_END_DAY_MASK)

#define RTC_DST_DAY_DST_START_DAY_MASK           (0x1F00U)
#define RTC_DST_DAY_DST_START_DAY_SHIFT          (8U)
/*! DST_START_DAY - Daylight Saving Time (DST) Day Start Value
 */
#define RTC_DST_DAY_DST_START_DAY(x)             (((uint16_t)(((uint16_t)(x)) << RTC_DST_DAY_DST_START_DAY_SHIFT)) & RTC_DST_DAY_DST_START_DAY_MASK)
/*! @} */

/*! @name COMPEN - Compensation */
/*! @{ */

#define RTC_COMPEN_COMPEN_VAL_MASK               (0xFFFFU)
#define RTC_COMPEN_COMPEN_VAL_SHIFT              (0U)
/*! COMPEN_VAL - Compensation Value
 */
#define RTC_COMPEN_COMPEN_VAL(x)                 (((uint16_t)(((uint16_t)(x)) << RTC_COMPEN_COMPEN_VAL_SHIFT)) & RTC_COMPEN_COMPEN_VAL_MASK)
/*! @} */

/*! @name TAMPER_QSCR - Tamper Queue Status and Control */
/*! @{ */

#define RTC_TAMPER_QSCR_Q_FULL_MASK              (0x1U)
#define RTC_TAMPER_QSCR_Q_FULL_SHIFT             (0U)
/*! Q_FULL - Q_FULL
 *  0b1..The tamper queue is full.
 *  0b0..The tamper queue is not full.
 */
#define RTC_TAMPER_QSCR_Q_FULL(x)                (((uint16_t)(((uint16_t)(x)) << RTC_TAMPER_QSCR_Q_FULL_SHIFT)) & RTC_TAMPER_QSCR_Q_FULL_MASK)

#define RTC_TAMPER_QSCR_Q_FULL_INT_EN_MASK       (0x2U)
#define RTC_TAMPER_QSCR_Q_FULL_INT_EN_SHIFT      (1U)
/*! Q_FULL_INT_EN - Q_FULL_INT_EN
 *  0b1..Queue full interrupt is enabled.
 *  0b0..Queue full interrupt is disabled.
 */
#define RTC_TAMPER_QSCR_Q_FULL_INT_EN(x)         (((uint16_t)(((uint16_t)(x)) << RTC_TAMPER_QSCR_Q_FULL_INT_EN_SHIFT)) & RTC_TAMPER_QSCR_Q_FULL_INT_EN_MASK)

#define RTC_TAMPER_QSCR_Q_CLEAR_MASK             (0x4U)
#define RTC_TAMPER_QSCR_Q_CLEAR_SHIFT            (2U)
/*! Q_CLEAR - Q_CLEAR
 */
#define RTC_TAMPER_QSCR_Q_CLEAR(x)               (((uint16_t)(((uint16_t)(x)) << RTC_TAMPER_QSCR_Q_CLEAR_SHIFT)) & RTC_TAMPER_QSCR_Q_CLEAR_MASK)
/*! @} */

/*! @name TAMPER_SCR - Tamper Status and Control */
/*! @{ */

#define RTC_TAMPER_SCR_TMPR_EN_MASK              (0xFU)
#define RTC_TAMPER_SCR_TMPR_EN_SHIFT             (0U)
/*! TMPR_EN - Tamper Control
 *  0b0000..Tamper Status reporting disabled.
 *  0b0001..Tamper Status reporting enabled.
 */
#define RTC_TAMPER_SCR_TMPR_EN(x)                (((uint16_t)(((uint16_t)(x)) << RTC_TAMPER_SCR_TMPR_EN_SHIFT)) & RTC_TAMPER_SCR_TMPR_EN_MASK)

#define RTC_TAMPER_SCR_TMPR_STS_MASK             (0xF00U)
#define RTC_TAMPER_SCR_TMPR_STS_SHIFT            (8U)
/*! TMPR_STS - Tamper Status
 *  0b0000..No Tamper Detected
 *  0b0001..Tamper Event Detected
 */
#define RTC_TAMPER_SCR_TMPR_STS(x)               (((uint16_t)(((uint16_t)(x)) << RTC_TAMPER_SCR_TMPR_STS_SHIFT)) & RTC_TAMPER_SCR_TMPR_STS_MASK)
/*! @} */

/*! @name FILTER01_CFG - Tamper 01 Filter Configuration */
/*! @{ */

#define RTC_FILTER01_CFG_FIL_DUR1_MASK           (0xFU)
#define RTC_FILTER01_CFG_FIL_DUR1_SHIFT          (0U)
/*! FIL_DUR1 - Tamper Detect Bit 1 Filter Duration
 *  0b0000..Filtering operation disabled.
 *  0b0001-0b1111..Number of tamper filter clock cycles to be counted when tamper is asserted.
 */
#define RTC_FILTER01_CFG_FIL_DUR1(x)             (((uint16_t)(((uint16_t)(x)) << RTC_FILTER01_CFG_FIL_DUR1_SHIFT)) & RTC_FILTER01_CFG_FIL_DUR1_MASK)

#define RTC_FILTER01_CFG_CLK_SEL1_MASK           (0x70U)
#define RTC_FILTER01_CFG_CLK_SEL1_SHIFT          (4U)
/*! CLK_SEL1 - Tamper Filter 1 Clock Select
 *  0b000..32 kHz clock
 *  0b001..512 Hz clock
 *  0b010..128 Hz clock
 *  0b011..64 Hz clock
 *  0b100..16 Hz clock
 *  0b101..8 Hz clock
 *  0b110..4 Hz clock
 *  0b111..2 Hz clock
 */
#define RTC_FILTER01_CFG_CLK_SEL1(x)             (((uint16_t)(((uint16_t)(x)) << RTC_FILTER01_CFG_CLK_SEL1_SHIFT)) & RTC_FILTER01_CFG_CLK_SEL1_MASK)

#define RTC_FILTER01_CFG_POL1_MASK               (0x80U)
#define RTC_FILTER01_CFG_POL1_SHIFT              (7U)
/*! POL1 - Tamper Detect Input Bit 1 Polarity Control
 *  0b0..Tamper detect input bit 1 is active high.
 *  0b1..Tamper detect input bit 1 is active low.
 */
#define RTC_FILTER01_CFG_POL1(x)                 (((uint16_t)(((uint16_t)(x)) << RTC_FILTER01_CFG_POL1_SHIFT)) & RTC_FILTER01_CFG_POL1_MASK)

#define RTC_FILTER01_CFG_FIL_DUR0_MASK           (0xF00U)
#define RTC_FILTER01_CFG_FIL_DUR0_SHIFT          (8U)
/*! FIL_DUR0 - Tamper Detect Bit 0 Filter Duration
 *  0b0000..Filtering operation disabled.
 *  0b0001-0b1111..Number of tamper filter clock cycles to be counted when tamper is asserted.
 */
#define RTC_FILTER01_CFG_FIL_DUR0(x)             (((uint16_t)(((uint16_t)(x)) << RTC_FILTER01_CFG_FIL_DUR0_SHIFT)) & RTC_FILTER01_CFG_FIL_DUR0_MASK)

#define RTC_FILTER01_CFG_CLK_SEL0_MASK           (0x7000U)
#define RTC_FILTER01_CFG_CLK_SEL0_SHIFT          (12U)
/*! CLK_SEL0 - Tamper Filter 0 Clock Select
 *  0b000..32 kHz clock
 *  0b001..512 Hz clock
 *  0b010..128 Hz clock
 *  0b011..64 Hz clock
 *  0b100..16 Hz clock
 *  0b101..8 Hz clock
 *  0b110..4 Hz clock
 *  0b111..2 Hz clock
 */
#define RTC_FILTER01_CFG_CLK_SEL0(x)             (((uint16_t)(((uint16_t)(x)) << RTC_FILTER01_CFG_CLK_SEL0_SHIFT)) & RTC_FILTER01_CFG_CLK_SEL0_MASK)

#define RTC_FILTER01_CFG_POL0_MASK               (0x8000U)
#define RTC_FILTER01_CFG_POL0_SHIFT              (15U)
/*! POL0 - Tamper Detect Input Bit 0 Polarity Control
 *  0b0..Tamper detect input bit 0 is active high.
 *  0b1..Tamper detect input bit 0 is active low.
 */
#define RTC_FILTER01_CFG_POL0(x)                 (((uint16_t)(((uint16_t)(x)) << RTC_FILTER01_CFG_POL0_SHIFT)) & RTC_FILTER01_CFG_POL0_MASK)
/*! @} */

/*! @name FILTER23_CFG - Tamper 23 Filter Configuration */
/*! @{ */

#define RTC_FILTER23_CFG_FIL_DUR3_MASK           (0xFU)
#define RTC_FILTER23_CFG_FIL_DUR3_SHIFT          (0U)
/*! FIL_DUR3 - Tamper Detect Bit 3 Filter Duration
 *  0b0000..Filtering operation disabled.
 *  0b0001-0b1111..Number of tamper filter clock cycles to be counted when tamper is asserted.
 */
#define RTC_FILTER23_CFG_FIL_DUR3(x)             (((uint16_t)(((uint16_t)(x)) << RTC_FILTER23_CFG_FIL_DUR3_SHIFT)) & RTC_FILTER23_CFG_FIL_DUR3_MASK)

#define RTC_FILTER23_CFG_CLK_SEL3_MASK           (0x70U)
#define RTC_FILTER23_CFG_CLK_SEL3_SHIFT          (4U)
/*! CLK_SEL3 - Tamper Filter 3 Clock Select
 *  0b000..32 kHz clock
 *  0b001..512 Hz clock
 *  0b010..128 Hz clock
 *  0b011..64 Hz clock
 *  0b100..16 Hz clock
 *  0b101..8 Hz clock
 *  0b110..4 Hz clock
 *  0b111..2 Hz clock
 */
#define RTC_FILTER23_CFG_CLK_SEL3(x)             (((uint16_t)(((uint16_t)(x)) << RTC_FILTER23_CFG_CLK_SEL3_SHIFT)) & RTC_FILTER23_CFG_CLK_SEL3_MASK)

#define RTC_FILTER23_CFG_POL3_MASK               (0x80U)
#define RTC_FILTER23_CFG_POL3_SHIFT              (7U)
/*! POL3 - Tamper Detect Input Bit 3 Polarity Control
 *  0b0..Tamper detect input bit 3 is active high.
 *  0b1..Tamper detect input bit 3 is active low.
 */
#define RTC_FILTER23_CFG_POL3(x)                 (((uint16_t)(((uint16_t)(x)) << RTC_FILTER23_CFG_POL3_SHIFT)) & RTC_FILTER23_CFG_POL3_MASK)

#define RTC_FILTER23_CFG_FIL_DUR2_MASK           (0xF00U)
#define RTC_FILTER23_CFG_FIL_DUR2_SHIFT          (8U)
/*! FIL_DUR2 - Tamper Detect Bit 2 Filter Duration
 *  0b0000..Filtering operation disabled.
 *  0b0001-0b1111..Number of tamper filter clock cycles to be counted when tamper is asserted.
 */
#define RTC_FILTER23_CFG_FIL_DUR2(x)             (((uint16_t)(((uint16_t)(x)) << RTC_FILTER23_CFG_FIL_DUR2_SHIFT)) & RTC_FILTER23_CFG_FIL_DUR2_MASK)

#define RTC_FILTER23_CFG_CLK_SEL2_MASK           (0x7000U)
#define RTC_FILTER23_CFG_CLK_SEL2_SHIFT          (12U)
/*! CLK_SEL2 - Tamper Filter 2 Clock Select
 *  0b000..32 kHz clock
 *  0b001..512 Hz clock
 *  0b010..128 Hz clock
 *  0b011..64 Hz clock
 *  0b100..16 Hz clock
 *  0b101..8 Hz clock
 *  0b110..4 Hz clock
 *  0b111..2 Hz clock
 */
#define RTC_FILTER23_CFG_CLK_SEL2(x)             (((uint16_t)(((uint16_t)(x)) << RTC_FILTER23_CFG_CLK_SEL2_SHIFT)) & RTC_FILTER23_CFG_CLK_SEL2_MASK)

#define RTC_FILTER23_CFG_POL2_MASK               (0x8000U)
#define RTC_FILTER23_CFG_POL2_SHIFT              (15U)
/*! POL2 - Tamper Detect Input Bit 2 Polarity Control
 *  0b0..Tamper detect input bit 2 is active high.
 *  0b1..Tamper detect input bit 2 is active low.
 */
#define RTC_FILTER23_CFG_POL2(x)                 (((uint16_t)(((uint16_t)(x)) << RTC_FILTER23_CFG_POL2_SHIFT)) & RTC_FILTER23_CFG_POL2_MASK)
/*! @} */

/*! @name TAMPER_QUEUE - Tamper Queue */
/*! @{ */

#define RTC_TAMPER_QUEUE_TAMPER_DATA_MASK        (0xFFFFU)
#define RTC_TAMPER_QUEUE_TAMPER_DATA_SHIFT       (0U)
/*! TAMPER_DATA - Tamper type stamp and pin number information register
 */
#define RTC_TAMPER_QUEUE_TAMPER_DATA(x)          (((uint16_t)(((uint16_t)(x)) << RTC_TAMPER_QUEUE_TAMPER_DATA_SHIFT)) & RTC_TAMPER_QUEUE_TAMPER_DATA_MASK)
/*! @} */

/*! @name CTRL2 - Control 2 */
/*! @{ */

#define RTC_CTRL2_TAMP_CFG_OVER_MASK             (0x1U)
#define RTC_CTRL2_TAMP_CFG_OVER_SHIFT            (0U)
/*! TAMP_CFG_OVER - Tamper Configuration Over
 *  0b0..Tamper filter processing disabled.
 *  0b1..Tamper filter processing enabled.
 */
#define RTC_CTRL2_TAMP_CFG_OVER(x)               (((uint16_t)(((uint16_t)(x)) << RTC_CTRL2_TAMP_CFG_OVER_SHIFT)) & RTC_CTRL2_TAMP_CFG_OVER_MASK)
/*! @} */

/*! @name SUBSECOND_CTRL - Sub-second control */
/*! @{ */

#define RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN_MASK (0x1U)
#define RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN_SHIFT (0U)
/*! SUB_SECOND_CNT_EN - Sub-second counter enable bit
 *  0b0..Disabled.
 *  0b1..Enabled.
 */
#define RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN(x)  (((uint32_t)(((uint32_t)(x)) << RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN_SHIFT)) & RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN_MASK)
/*! @} */

/*! @name SUBSECOND_CNT - Sub-second counter */
/*! @{ */

#define RTC_SUBSECOND_CNT_SUBSECOND_CNT_MASK     (0xFFFFU)
#define RTC_SUBSECOND_CNT_SUBSECOND_CNT_SHIFT    (0U)
/*! SUBSECOND_CNT - Current sub-second counter value
 */
#define RTC_SUBSECOND_CNT_SUBSECOND_CNT(x)       (((uint32_t)(((uint32_t)(x)) << RTC_SUBSECOND_CNT_SUBSECOND_CNT_SHIFT)) & RTC_SUBSECOND_CNT_SUBSECOND_CNT_MASK)
/*! @} */

/*! @name WAKE_TIMER_CTRL - Wake timer control */
/*! @{ */

#define RTC_WAKE_TIMER_CTRL_WAKE_FLAG_MASK       (0x2U)
#define RTC_WAKE_TIMER_CTRL_WAKE_FLAG_SHIFT      (1U)
/*! WAKE_FLAG - Wake timer status flag
 *  0b0..Wake timer has not timed out.
 *  0b1..Wake timer has timed out.
 */
#define RTC_WAKE_TIMER_CTRL_WAKE_FLAG(x)         (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CTRL_WAKE_FLAG_SHIFT)) & RTC_WAKE_TIMER_CTRL_WAKE_FLAG_MASK)

#define RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_MASK  (0x4U)
#define RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_SHIFT (2U)
/*! CLR_WAKE_TIMER - Clear wake timer
 *  0b0..No effect.
 *  0b1..Clears the wake counter and halt operation until a new count value is loaded.
 */
#define RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER(x)    (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_SHIFT)) & RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_MASK)

#define RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA_MASK     (0x10U)
#define RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA_SHIFT    (4U)
/*! OSC_DIV_ENA - Enable the 5-bit clock divider to divide down the 32Khz input clock to generate
 *    the 1Khz clock source for the wake timer.
 *  0b0..Disabled.
 *  0b1..Enabled.
 */
#define RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA(x)       (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA_SHIFT)) & RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA_MASK)

#define RTC_WAKE_TIMER_CTRL_INTR_EN_MASK         (0x20U)
#define RTC_WAKE_TIMER_CTRL_INTR_EN_SHIFT        (5U)
/*! INTR_EN - Enable interrupt when WAKE_FLAG is set.
 *  0b0..Disabled.
 *  0b1..Enabled.
 */
#define RTC_WAKE_TIMER_CTRL_INTR_EN(x)           (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CTRL_INTR_EN_SHIFT)) & RTC_WAKE_TIMER_CTRL_INTR_EN_MASK)
/*! @} */

/*! @name WAKE_TIMER_CNT - Wake timer counter */
/*! @{ */

#define RTC_WAKE_TIMER_CNT_WAKE_CNT_MASK         (0xFFFFFFFFU)
#define RTC_WAKE_TIMER_CNT_WAKE_CNT_SHIFT        (0U)
/*! WAKE_CNT - Wake counter
 */
#define RTC_WAKE_TIMER_CNT_WAKE_CNT(x)           (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CNT_WAKE_CNT_SHIFT)) & RTC_WAKE_TIMER_CNT_WAKE_CNT_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group RTC_Register_Masks */


/* RTC - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral RTC base address */
  #define RTC_BASE                                 (0x5002C000u)
  /** Peripheral RTC base address */
  #define RTC_BASE_NS                              (0x4002C000u)
  /** Peripheral RTC base pointer */
  #define RTC                                      ((RTC_Type *)RTC_BASE)
  /** Peripheral RTC base pointer */
  #define RTC_NS                                   ((RTC_Type *)RTC_BASE_NS)
  /** Array initializer of RTC peripheral base addresses */
  #define RTC_BASE_ADDRS                           { RTC_BASE }
  /** Array initializer of RTC peripheral base pointers */
  #define RTC_BASE_PTRS                            { RTC }
  /** Array initializer of RTC peripheral base addresses */
  #define RTC_BASE_ADDRS_NS                        { RTC_BASE_NS }
  /** Array initializer of RTC peripheral base pointers */
  #define RTC_BASE_PTRS_NS                         { RTC_NS }
#else
  /** Peripheral RTC base address */
  #define RTC_BASE                                 (0x4002C000u)
  /** Peripheral RTC base pointer */
  #define RTC                                      ((RTC_Type *)RTC_BASE)
  /** Array initializer of RTC peripheral base addresses */
  #define RTC_BASE_ADDRS                           { RTC_BASE }
  /** Array initializer of RTC peripheral base pointers */
  #define RTC_BASE_PTRS                            { RTC }
#endif
/** Interrupt vectors for the RTC peripheral type */
#define RTC_IRQS                                 { RTC_IRQn }

/*!
 * @}
 */ /* end of group RTC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- SCT Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer
 * @{
 */

/** SCT - Register Layout Typedef */
typedef struct {
  __IO uint32_t CONFIG;                            /**< SCTimer Configuration, offset: 0x0 */
  union {                                          /* offset: 0x4 */
    struct {                                         /* offset: 0x4 */
      __IO uint16_t CTRLL;                             /**< SCT_CTRLL register, offset: 0x4 */
      __IO uint16_t CTRLH;                             /**< SCT_CTRLH register, offset: 0x6 */
    } CTRL_ACCESS16BIT;
    __IO uint32_t CTRL;                              /**< SCT Control, offset: 0x4 */
  };
  union {                                          /* offset: 0x8 */
    struct {                                         /* offset: 0x8 */
      __IO uint16_t LIMITL;                            /**< SCT_LIMITL register, offset: 0x8 */
      __IO uint16_t LIMITH;                            /**< SCT_LIMITH register, offset: 0xA */
    } LIMIT_ACCESS16BIT;
    __IO uint32_t LIMIT;                             /**< SCT Limit Event Select, offset: 0x8 */
  };
  union {                                          /* offset: 0xC */
    struct {                                         /* offset: 0xC */
      __IO uint16_t HALTL;                             /**< SCT_HALTL register, offset: 0xC */
      __IO uint16_t HALTH;                             /**< SCT_HALTH register, offset: 0xE */
    } HALT_ACCESS16BIT;
    __IO uint32_t HALT;                              /**< Halt Event Select, offset: 0xC */
  };
  union {                                          /* offset: 0x10 */
    struct {                                         /* offset: 0x10 */
      __IO uint16_t STOPL;                             /**< SCT_STOPL register, offset: 0x10 */
      __IO uint16_t STOPH;                             /**< SCT_STOPH register, offset: 0x12 */
    } STOP_ACCESS16BIT;
    __IO uint32_t STOP;                              /**< Stop Event Select, offset: 0x10 */
  };
  union {                                          /* offset: 0x14 */
    struct {                                         /* offset: 0x14 */
      __IO uint16_t STARTL;                            /**< SCT_STARTL register, offset: 0x14 */
      __IO uint16_t STARTH;                            /**< SCT_STARTH register, offset: 0x16 */
    } START_ACCESS16BIT;
    __IO uint32_t START;                             /**< Start Event Select, offset: 0x14 */
  };
  __IO uint32_t DITHER;                            /**< Dither Condition, offset: 0x18 */
       uint8_t RESERVED_0[36];
  union {                                          /* offset: 0x40 */
    struct {                                         /* offset: 0x40 */
      __IO uint16_t COUNTL;                            /**< SCT_COUNTL register, offset: 0x40 */
      __IO uint16_t COUNTH;                            /**< SCT_COUNTH register, offset: 0x42 */
    } COUNT_ACCESS16BIT;
    __IO uint32_t COUNT;                             /**< Counter, offset: 0x40 */
  };
  union {                                          /* offset: 0x44 */
    struct {                                         /* offset: 0x44 */
      __IO uint16_t STATEL;                            /**< SCT_STATEL register, offset: 0x44 */
      __IO uint16_t STATEH;                            /**< SCT_STATEH register, offset: 0x46 */
    } STATE_ACCESS16BIT;
    __IO uint32_t STATE;                             /**< State, offset: 0x44 */
  };
  __I  uint32_t INPUT;                             /**< Input, offset: 0x48 */
  union {                                          /* offset: 0x4C */
    struct {                                         /* offset: 0x4C */
      __IO uint16_t REGMODEL;                          /**< SCT_REGMODEL register, offset: 0x4C */
      __IO uint16_t REGMODEH;                          /**< SCT_REGMODEH register, offset: 0x4E */
    } REGMODE_ACCESS16BIT;
    __IO uint32_t REGMODE;                           /**< Match/Capture Mode, offset: 0x4C */
  };
  __IO uint32_t OUTPUT;                            /**< Output, offset: 0x50 */
  __IO uint32_t OUTPUTDIRCTRL;                     /**< Output Counter Direction Control, offset: 0x54 */
  __IO uint32_t RES;                               /**< Output Conflict Resolution, offset: 0x58 */
  __IO uint32_t DMAREQ0;                           /**< DMA Request 0, offset: 0x5C */
  __IO uint32_t DMAREQ1;                           /**< DMA Request 1, offset: 0x60 */
       uint8_t RESERVED_1[140];
  __IO uint32_t EVEN;                              /**< Event Interrupt Enable, offset: 0xF0 */
  __IO uint32_t EVFLAG;                            /**< Event Flag, offset: 0xF4 */
  __IO uint32_t CONEN;                             /**< Conflict Interrupt Enable, offset: 0xF8 */
  __IO uint32_t CONFLAG;                           /**< Conflict Flag, offset: 0xFC */
  union {                                          /* offset: 0x100 */
    union {                                          /* offset: 0x100, array step: 0x4 */
      struct {                                         /* offset: 0x100, array step: 0x4 */
        __IO uint16_t CAPL;                              /**< SCT_CAPL register, array offset: 0x100, array step: 0x4 */
        __IO uint16_t CAPH;                              /**< SCT_CAPH register, array offset: 0x102, array step: 0x4 */
      } CAP_ACCESS16BIT[16];
      __IO uint32_t CAP[16];                           /**< Capture Value, array offset: 0x100, array step: 0x4 */
    };
    union {                                          /* offset: 0x100, array step: 0x4 */
      struct {                                         /* offset: 0x100, array step: 0x4 */
        __IO uint16_t MATCHL;                            /**< SCT_MATCHL register, array offset: 0x100, array step: 0x4 */
        __IO uint16_t MATCHH;                            /**< SCT_MATCHH register, array offset: 0x102, array step: 0x4 */
      } MATCH_ACCESS16BIT[16];
      __IO uint32_t MATCH[16];                         /**< Match Value, array offset: 0x100, array step: 0x4 */
    };
  };
  __IO uint32_t FRACMAT[6];                        /**< Fractional Match, array offset: 0x140, array step: 0x4 */
       uint8_t RESERVED_2[168];
  union {                                          /* offset: 0x200 */
    union {                                          /* offset: 0x200, array step: 0x4 */
      struct {                                         /* offset: 0x200, array step: 0x4 */
        __IO uint16_t CAPCTRLL;                          /**< SCT_CAPCTRLL register, array offset: 0x200, array step: 0x4 */
        __IO uint16_t CAPCTRLH;                          /**< SCT_CAPCTRLH register, array offset: 0x202, array step: 0x4 */
      } CAPCTRL_ACCESS16BIT[16];
      __IO uint32_t CAPCTRL[16];                       /**< Capture Control, array offset: 0x200, array step: 0x4 */
    };
    union {                                          /* offset: 0x200, array step: 0x4 */
      struct {                                         /* offset: 0x200, array step: 0x4 */
        __IO uint16_t MATCHRELL;                         /**< SCT_MATCHRELL register, array offset: 0x200, array step: 0x4 */
        __IO uint16_t MATCHRELH;                         /**< SCT_MATCHRELH register, array offset: 0x202, array step: 0x4 */
      } MATCHREL_ACCESS16BIT[16];
      __IO uint32_t MATCHREL[16];                      /**< Match Reload Value, array offset: 0x200, array step: 0x4 */
    };
  };
  __IO uint32_t FRACMATREL[6];                     /**< Fractional Match Reload, array offset: 0x240, array step: 0x4 */
       uint8_t RESERVED_3[168];
  struct {                                         /* offset: 0x300, array step: 0x8 */
    __IO uint32_t STATE;                             /**< Event n State, array offset: 0x300, array step: 0x8 */
    __IO uint32_t CTRL;                              /**< Event n Control, array offset: 0x304, array step: 0x8 */
  } EV[16];
       uint8_t RESERVED_4[384];
  struct {                                         /* offset: 0x500, array step: 0x8 */
    __IO uint32_t SET;                               /**< Output n Set, array offset: 0x500, array step: 0x8 */
    __IO uint32_t CLR;                               /**< Output n Clear, array offset: 0x504, array step: 0x8 */
  } OUT[10];
} SCT_Type;

/* ----------------------------------------------------------------------------
   -- SCT Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SCT_Register_Masks SCT Register Masks
 * @{
 */

/*! @name CONFIG - SCTimer Configuration */
/*! @{ */

#define SCT_CONFIG_UNIFY_MASK                    (0x1U)
#define SCT_CONFIG_UNIFY_SHIFT                   (0U)
/*! UNIFY - SCT Operation
 *  0b0..Dual counter. The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H.
 *  0b1..Unified counter. The SCT operates as a unified 32-bit counter.
 */
#define SCT_CONFIG_UNIFY(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK)

#define SCT_CONFIG_CLKMODE_MASK                  (0x6U)
#define SCT_CONFIG_CLKMODE_SHIFT                 (1U)
/*! CLKMODE - SCT Clock Mode
 *  0b00..System Clock Mode. The system clock clocks the entire SCT module including all counters and counter prescalers.
 *  0b01..Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are
 *        only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The
 *        minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the
 *        high-performance, sampled-clock mode.
 *  0b10..SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including all
 *        counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the
 *        clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode.
 *  0b11..Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL
 *        field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system
 *        clock. The input clock rate must be at least half the system clock rate and can be the same or faster than
 *        the system clock.
 */
#define SCT_CONFIG_CLKMODE(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK)

#define SCT_CONFIG_CKSEL_MASK                    (0x78U)
#define SCT_CONFIG_CKSEL_SHIFT                   (3U)
/*! CKSEL - SCT Clock Select. The specific functionality of the designated input/edge is dependent
 *    on the CLKMODE bit selection in this register.
 *  0b0000..Rising edges on input 0
 *  0b0001..Falling edges on input 0
 *  0b0010..Rising edges on input 1
 *  0b0011..Falling edges on input 1
 *  0b0100..Rising edges on input 2
 *  0b0101..Falling edges on input 2
 *  0b0110..Rising edges on input 3
 *  0b0111..Falling edges on input 3
 *  0b1000..Rising edges on input 4
 *  0b1001..Falling edges on input 4
 *  0b1010..Rising edges on input 5
 *  0b1011..Falling edges on input 5
 *  0b1100..Rising edges on input 6
 *  0b1101..Falling edges on input 6
 *  0b1110..Rising edges on input 7
 *  0b1111..Falling edges on input 7
 */
#define SCT_CONFIG_CKSEL(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK)

#define SCT_CONFIG_NORELOAD_L_MASK               (0x80U)
#define SCT_CONFIG_NORELOAD_L_SHIFT              (7U)
/*! NORELOAD_L - No Reload Lower Match
 *  0b0..Reload. The default setting.
 *  0b1..No Reload. Prevents the lower match registers from being reloaded from their respective reload registers.
 */
#define SCT_CONFIG_NORELOAD_L(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_L_SHIFT)) & SCT_CONFIG_NORELOAD_L_MASK)

#define SCT_CONFIG_NORELOAD_H_MASK               (0x100U)
#define SCT_CONFIG_NORELOAD_H_SHIFT              (8U)
/*! NORELOAD_H - No Reload Higher Match
 *  0b0..Reload. The default setting.
 *  0b1..No Reload. Prevents the higher match registers from being reloaded from their respective reload registers.
 */
#define SCT_CONFIG_NORELOAD_H(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK)

#define SCT_CONFIG_INSYNC_MASK                   (0x1FE00U)
#define SCT_CONFIG_INSYNC_SHIFT                  (9U)
/*! INSYNC - Input Synchronization
 */
#define SCT_CONFIG_INSYNC(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK)

#define SCT_CONFIG_AUTOLIMIT_L_MASK              (0x20000U)
#define SCT_CONFIG_AUTOLIMIT_L_SHIFT             (17U)
/*! AUTOLIMIT_L - Auto Limit Lower
 *  0b0..Disable.
 *  0b1..Enable. A match on match register 0 is the LIMIT condition. No need to define an associated event.
 */
#define SCT_CONFIG_AUTOLIMIT_L(x)                (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK)

#define SCT_CONFIG_AUTOLIMIT_H_MASK              (0x40000U)
#define SCT_CONFIG_AUTOLIMIT_H_SHIFT             (18U)
/*! AUTOLIMIT_H - Auto Limit Higher
 *  0b0..Disable.
 *  0b1..Enable. A match on match register 0 is the LIMIT condition. No need to define an associated event.
 */
#define SCT_CONFIG_AUTOLIMIT_H(x)                (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK)
/*! @} */

/*! @name CTRLL - SCT_CTRLL register */
/*! @{ */

#define SCT_CTRLL_DOWN_L_MASK                    (0x1U)
#define SCT_CTRLL_DOWN_L_SHIFT                   (0U)
/*! DOWN_L - Down Counter Low
 *  0b0..Up. The L or unified counter is counting up.
 *  0b1..Down. The L or unified counter is counting down.
 */
#define SCT_CTRLL_DOWN_L(x)                      (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_DOWN_L_SHIFT)) & SCT_CTRLL_DOWN_L_MASK)

#define SCT_CTRLL_STOP_L_MASK                    (0x2U)
#define SCT_CTRLL_STOP_L_SHIFT                   (1U)
/*! STOP_L - Stop Counter Low
 *  0b0..Disable
 *  0b1..Enable
 */
#define SCT_CTRLL_STOP_L(x)                      (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_STOP_L_SHIFT)) & SCT_CTRLL_STOP_L_MASK)

#define SCT_CTRLL_HALT_L_MASK                    (0x4U)
#define SCT_CTRLL_HALT_L_SHIFT                   (2U)
/*! HALT_L - Halt Counter Low
 *  0b0..Disable
 *  0b1..Enable
 */
#define SCT_CTRLL_HALT_L(x)                      (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_HALT_L_SHIFT)) & SCT_CTRLL_HALT_L_MASK)

#define SCT_CTRLL_CLRCTR_L_MASK                  (0x8U)
#define SCT_CTRLL_CLRCTR_L_SHIFT                 (3U)
/*! CLRCTR_L - Clear Counter Low
 */
#define SCT_CTRLL_CLRCTR_L(x)                    (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_CLRCTR_L_SHIFT)) & SCT_CTRLL_CLRCTR_L_MASK)

#define SCT_CTRLL_BIDIR_L_MASK                   (0x10U)
#define SCT_CTRLL_BIDIR_L_SHIFT                  (4U)
/*! BIDIR_L - Bidirectional Select Low
 *  0b0..Up. The counter counts up to a limit condition, then is cleared to zero.
 *  0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0.
 */
#define SCT_CTRLL_BIDIR_L(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_BIDIR_L_SHIFT)) & SCT_CTRLL_BIDIR_L_MASK)

#define SCT_CTRLL_PRE_L_MASK                     (0x1FE0U)
#define SCT_CTRLL_PRE_L_SHIFT                    (5U)
/*! PRE_L - Prescaler for Low Counter
 */
#define SCT_CTRLL_PRE_L(x)                       (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_PRE_L_SHIFT)) & SCT_CTRLL_PRE_L_MASK)
/*! @} */

/*! @name CTRLH - SCT_CTRLH register */
/*! @{ */

#define SCT_CTRLH_DOWN_H_MASK                    (0x1U)
#define SCT_CTRLH_DOWN_H_SHIFT                   (0U)
/*! DOWN_H - Down Counter High
 *  0b0..Up. The H counter is counting up.
 *  0b1..Down. The H counter is counting down.
 */
#define SCT_CTRLH_DOWN_H(x)                      (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_DOWN_H_SHIFT)) & SCT_CTRLH_DOWN_H_MASK)

#define SCT_CTRLH_STOP_H_MASK                    (0x2U)
#define SCT_CTRLH_STOP_H_SHIFT                   (1U)
/*! STOP_H - Stop Counter High
 *  0b0..Disable
 *  0b1..Enable
 */
#define SCT_CTRLH_STOP_H(x)                      (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_STOP_H_SHIFT)) & SCT_CTRLH_STOP_H_MASK)

#define SCT_CTRLH_HALT_H_MASK                    (0x4U)
#define SCT_CTRLH_HALT_H_SHIFT                   (2U)
/*! HALT_H - Halt Counter High
 *  0b0..Disable
 *  0b1..Enable
 */
#define SCT_CTRLH_HALT_H(x)                      (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_HALT_H_SHIFT)) & SCT_CTRLH_HALT_H_MASK)

#define SCT_CTRLH_CLRCTR_H_MASK                  (0x8U)
#define SCT_CTRLH_CLRCTR_H_SHIFT                 (3U)
/*! CLRCTR_H - Clear Counter High
 */
#define SCT_CTRLH_CLRCTR_H(x)                    (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_CLRCTR_H_SHIFT)) & SCT_CTRLH_CLRCTR_H_MASK)

#define SCT_CTRLH_BIDIR_H_MASK                   (0x10U)
#define SCT_CTRLH_BIDIR_H_SHIFT                  (4U)
/*! BIDIR_H - Bidirectional Select High
 *  0b0..Up. The H counter counts up to its limit condition, then is cleared to zero.
 *  0b1..Up-down. The H counter counts up to its limit, then counts down to a limit condition or to 0.
 */
#define SCT_CTRLH_BIDIR_H(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_BIDIR_H_SHIFT)) & SCT_CTRLH_BIDIR_H_MASK)

#define SCT_CTRLH_PRE_H_MASK                     (0x1FE0U)
#define SCT_CTRLH_PRE_H_SHIFT                    (5U)
/*! PRE_H - Prescaler for High Counter
 */
#define SCT_CTRLH_PRE_H(x)                       (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_PRE_H_SHIFT)) & SCT_CTRLH_PRE_H_MASK)
/*! @} */

/*! @name CTRL - SCT Control */
/*! @{ */

#define SCT_CTRL_DOWN_L_MASK                     (0x1U)
#define SCT_CTRL_DOWN_L_SHIFT                    (0U)
/*! DOWN_L - Down Counter Low
 *  0b0..Up. The L or unified counter is counting up.
 *  0b1..Down. The L or unified counter is counting down.
 */
#define SCT_CTRL_DOWN_L(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK)

#define SCT_CTRL_STOP_L_MASK                     (0x2U)
#define SCT_CTRL_STOP_L_SHIFT                    (1U)
/*! STOP_L - Stop Counter Low
 *  0b0..Disable
 *  0b1..Enable
 */
#define SCT_CTRL_STOP_L(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK)

#define SCT_CTRL_HALT_L_MASK                     (0x4U)
#define SCT_CTRL_HALT_L_SHIFT                    (2U)
/*! HALT_L - Halt Counter Low
 *  0b0..Disable
 *  0b1..Enable
 */
#define SCT_CTRL_HALT_L(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK)

#define SCT_CTRL_CLRCTR_L_MASK                   (0x8U)
#define SCT_CTRL_CLRCTR_L_SHIFT                  (3U)
/*! CLRCTR_L - Clear Counter Low
 */
#define SCT_CTRL_CLRCTR_L(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK)

#define SCT_CTRL_BIDIR_L_MASK                    (0x10U)
#define SCT_CTRL_BIDIR_L_SHIFT                   (4U)
/*! BIDIR_L - Bidirectional Select Low
 *  0b0..Up. The counter counts up to a limit condition, then is cleared to zero.
 *  0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0.
 */
#define SCT_CTRL_BIDIR_L(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK)

#define SCT_CTRL_PRE_L_MASK                      (0x1FE0U)
#define SCT_CTRL_PRE_L_SHIFT                     (5U)
/*! PRE_L - Prescaler for Low Counter
 */
#define SCT_CTRL_PRE_L(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK)

#define SCT_CTRL_DOWN_H_MASK                     (0x10000U)
#define SCT_CTRL_DOWN_H_SHIFT                    (16U)
/*! DOWN_H - Down Counter High
 *  0b0..Up. The H counter is counting up.
 *  0b1..Down. The H counter is counting down.
 */
#define SCT_CTRL_DOWN_H(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK)

#define SCT_CTRL_STOP_H_MASK                     (0x20000U)
#define SCT_CTRL_STOP_H_SHIFT                    (17U)
/*! STOP_H - Stop Counter High
 *  0b0..Disable
 *  0b1..Enable
 */
#define SCT_CTRL_STOP_H(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK)

#define SCT_CTRL_HALT_H_MASK                     (0x40000U)
#define SCT_CTRL_HALT_H_SHIFT                    (18U)
/*! HALT_H - Halt Counter High
 *  0b0..Disable
 *  0b1..Enable
 */
#define SCT_CTRL_HALT_H(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK)

#define SCT_CTRL_CLRCTR_H_MASK                   (0x80000U)
#define SCT_CTRL_CLRCTR_H_SHIFT                  (19U)
/*! CLRCTR_H - Clear Counter High
 */
#define SCT_CTRL_CLRCTR_H(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK)

#define SCT_CTRL_BIDIR_H_MASK                    (0x100000U)
#define SCT_CTRL_BIDIR_H_SHIFT                   (20U)
/*! BIDIR_H - Bidirectional Select High
 *  0b0..Up. The H counter counts up to its limit condition, then is cleared to zero.
 *  0b1..Up-down. The H counter counts up to its limit, then counts down to a limit condition or to 0.
 */
#define SCT_CTRL_BIDIR_H(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK)

#define SCT_CTRL_PRE_H_MASK                      (0x1FE00000U)
#define SCT_CTRL_PRE_H_SHIFT                     (21U)
/*! PRE_H - Prescaler for High Counter
 */
#define SCT_CTRL_PRE_H(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK)
/*! @} */

/*! @name LIMITL - SCT_LIMITL register */
/*! @{ */

#define SCT_LIMITL_LIMITL_MASK                   (0xFFFFU)
#define SCT_LIMITL_LIMITL_SHIFT                  (0U)
#define SCT_LIMITL_LIMITL(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_LIMITL_LIMITL_SHIFT)) & SCT_LIMITL_LIMITL_MASK)
/*! @} */

/*! @name LIMITH - SCT_LIMITH register */
/*! @{ */

#define SCT_LIMITH_LIMITH_MASK                   (0xFFFFU)
#define SCT_LIMITH_LIMITH_SHIFT                  (0U)
#define SCT_LIMITH_LIMITH(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_LIMITH_LIMITH_SHIFT)) & SCT_LIMITH_LIMITH_MASK)
/*! @} */

/*! @name LIMIT - SCT Limit Event Select */
/*! @{ */

#define SCT_LIMIT_LIMMSK_L_MASK                  (0xFFFFU)
#define SCT_LIMIT_LIMMSK_L_SHIFT                 (0U)
/*! LIMMSK_L - Limit Event Counter Low
 */
#define SCT_LIMIT_LIMMSK_L(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK)

#define SCT_LIMIT_LIMMSK_H_MASK                  (0xFFFF0000U)
#define SCT_LIMIT_LIMMSK_H_SHIFT                 (16U)
/*! LIMMSK_H - Limit Event Counter High
 */
#define SCT_LIMIT_LIMMSK_H(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK)
/*! @} */

/*! @name HALTL - SCT_HALTL register */
/*! @{ */

#define SCT_HALTL_HALTL_MASK                     (0xFFFFU)
#define SCT_HALTL_HALTL_SHIFT                    (0U)
#define SCT_HALTL_HALTL(x)                       (((uint16_t)(((uint16_t)(x)) << SCT_HALTL_HALTL_SHIFT)) & SCT_HALTL_HALTL_MASK)
/*! @} */

/*! @name HALTH - SCT_HALTH register */
/*! @{ */

#define SCT_HALTH_HALTH_MASK                     (0xFFFFU)
#define SCT_HALTH_HALTH_SHIFT                    (0U)
#define SCT_HALTH_HALTH(x)                       (((uint16_t)(((uint16_t)(x)) << SCT_HALTH_HALTH_SHIFT)) & SCT_HALTH_HALTH_MASK)
/*! @} */

/*! @name HALT - Halt Event Select */
/*! @{ */

#define SCT_HALT_HALTMSK_L_MASK                  (0xFFFFU)
#define SCT_HALT_HALTMSK_L_SHIFT                 (0U)
/*! HALTMSK_L - Halt Event Low
 */
#define SCT_HALT_HALTMSK_L(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK)

#define SCT_HALT_HALTMSK_H_MASK                  (0xFFFF0000U)
#define SCT_HALT_HALTMSK_H_SHIFT                 (16U)
/*! HALTMSK_H - Halt Event High
 */
#define SCT_HALT_HALTMSK_H(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK)
/*! @} */

/*! @name STOPL - SCT_STOPL register */
/*! @{ */

#define SCT_STOPL_STOPL_MASK                     (0xFFFFU)
#define SCT_STOPL_STOPL_SHIFT                    (0U)
#define SCT_STOPL_STOPL(x)                       (((uint16_t)(((uint16_t)(x)) << SCT_STOPL_STOPL_SHIFT)) & SCT_STOPL_STOPL_MASK)
/*! @} */

/*! @name STOPH - SCT_STOPH register */
/*! @{ */

#define SCT_STOPH_STOPH_MASK                     (0xFFFFU)
#define SCT_STOPH_STOPH_SHIFT                    (0U)
#define SCT_STOPH_STOPH(x)                       (((uint16_t)(((uint16_t)(x)) << SCT_STOPH_STOPH_SHIFT)) & SCT_STOPH_STOPH_MASK)
/*! @} */

/*! @name STOP - Stop Event Select */
/*! @{ */

#define SCT_STOP_STOPMSK_L_MASK                  (0xFFFFU)
#define SCT_STOP_STOPMSK_L_SHIFT                 (0U)
/*! STOPMSK_L - Stop Event Low
 */
#define SCT_STOP_STOPMSK_L(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK)

#define SCT_STOP_STOPMSK_H_MASK                  (0xFFFF0000U)
#define SCT_STOP_STOPMSK_H_SHIFT                 (16U)
/*! STOPMSK_H - Stop Event High
 */
#define SCT_STOP_STOPMSK_H(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK)
/*! @} */

/*! @name STARTL - SCT_STARTL register */
/*! @{ */

#define SCT_STARTL_STARTL_MASK                   (0xFFFFU)
#define SCT_STARTL_STARTL_SHIFT                  (0U)
#define SCT_STARTL_STARTL(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_STARTL_STARTL_SHIFT)) & SCT_STARTL_STARTL_MASK)
/*! @} */

/*! @name STARTH - SCT_STARTH register */
/*! @{ */

#define SCT_STARTH_STARTH_MASK                   (0xFFFFU)
#define SCT_STARTH_STARTH_SHIFT                  (0U)
#define SCT_STARTH_STARTH(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_STARTH_STARTH_SHIFT)) & SCT_STARTH_STARTH_MASK)
/*! @} */

/*! @name START - Start Event Select */
/*! @{ */

#define SCT_START_STARTMSK_L_MASK                (0xFFFFU)
#define SCT_START_STARTMSK_L_SHIFT               (0U)
/*! STARTMSK_L - If bit n is one, event n clears the CTRL[STOP_L] = 0 (event 0 = bit 0, event 1 =
 *    bit 1, etc.). The number of bits = number of events in this SCT.
 */
#define SCT_START_STARTMSK_L(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK)

#define SCT_START_STARTMSK_H_MASK                (0xFFFF0000U)
#define SCT_START_STARTMSK_H_SHIFT               (16U)
/*! STARTMSK_H - If bit n is one, event n clears the CTRL[STOP_H] = 0 (event 0 = bit 16, event 1 =
 *    bit 17, etc.). The number of bits = number of events in this SCT.
 */
#define SCT_START_STARTMSK_H(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK)
/*! @} */

/*! @name DITHER - Dither Condition */
/*! @{ */

#define SCT_DITHER_DITHER_L_MASK                 (0xFFFFU)
#define SCT_DITHER_DITHER_L_SHIFT                (0U)
/*! DITHER_L - If bit n is one, event n clears the CTRL[STOP_L] = 0 (event 0 = bit 0, event 1 = bit
 *    1, etc.). The number of bits = number of events in this SCT.
 */
#define SCT_DITHER_DITHER_L(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_DITHER_DITHER_L_SHIFT)) & SCT_DITHER_DITHER_L_MASK)

#define SCT_DITHER_DITHER_H_MASK                 (0xFFFF0000U)
#define SCT_DITHER_DITHER_H_SHIFT                (16U)
/*! DITHER_H - If bit n is one, event n clears the CTRL[STOP_H] = 0 (event 0 = bit 16, event 1 = bit
 *    17, etc.). The number of bits = number of events in this SCT.
 */
#define SCT_DITHER_DITHER_H(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_DITHER_DITHER_H_SHIFT)) & SCT_DITHER_DITHER_H_MASK)
/*! @} */

/*! @name COUNTL - SCT_COUNTL register */
/*! @{ */

#define SCT_COUNTL_COUNTL_MASK                   (0xFFFFU)
#define SCT_COUNTL_COUNTL_SHIFT                  (0U)
#define SCT_COUNTL_COUNTL(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_COUNTL_COUNTL_SHIFT)) & SCT_COUNTL_COUNTL_MASK)
/*! @} */

/*! @name COUNTH - SCT_COUNTH register */
/*! @{ */

#define SCT_COUNTH_COUNTH_MASK                   (0xFFFFU)
#define SCT_COUNTH_COUNTH_SHIFT                  (0U)
#define SCT_COUNTH_COUNTH(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_COUNTH_COUNTH_SHIFT)) & SCT_COUNTH_COUNTH_MASK)
/*! @} */

/*! @name COUNT - Counter */
/*! @{ */

#define SCT_COUNT_CTR_L_MASK                     (0xFFFFU)
#define SCT_COUNT_CTR_L_SHIFT                    (0U)
/*! CTR_L - Counter Low
 */
#define SCT_COUNT_CTR_L(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK)

#define SCT_COUNT_CTR_H_MASK                     (0xFFFF0000U)
#define SCT_COUNT_CTR_H_SHIFT                    (16U)
/*! CTR_H - Counter High
 */
#define SCT_COUNT_CTR_H(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK)
/*! @} */

/*! @name STATEL - SCT_STATEL register */
/*! @{ */

#define SCT_STATEL_STATEL_MASK                   (0xFFFFU)
#define SCT_STATEL_STATEL_SHIFT                  (0U)
#define SCT_STATEL_STATEL(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_STATEL_STATEL_SHIFT)) & SCT_STATEL_STATEL_MASK)
/*! @} */

/*! @name STATEH - SCT_STATEH register */
/*! @{ */

#define SCT_STATEH_STATEH_MASK                   (0xFFFFU)
#define SCT_STATEH_STATEH_SHIFT                  (0U)
#define SCT_STATEH_STATEH(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_STATEH_STATEH_SHIFT)) & SCT_STATEH_STATEH_MASK)
/*! @} */

/*! @name STATE - State */
/*! @{ */

#define SCT_STATE_STATE_L_MASK                   (0x1FU)
#define SCT_STATE_STATE_L_SHIFT                  (0U)
/*! STATE_L - State variable
 */
#define SCT_STATE_STATE_L(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK)

#define SCT_STATE_STATE_H_MASK                   (0x1F0000U)
#define SCT_STATE_STATE_H_SHIFT                  (16U)
/*! STATE_H - State variable
 */
#define SCT_STATE_STATE_H(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK)
/*! @} */

/*! @name INPUT - Input */
/*! @{ */

#define SCT_INPUT_AIN0_MASK                      (0x1U)
#define SCT_INPUT_AIN0_SHIFT                     (0U)
/*! AIN0 - Input 0 state. Input 0 state on the last SCT clock edge.
 */
#define SCT_INPUT_AIN0(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK)

#define SCT_INPUT_AIN1_MASK                      (0x2U)
#define SCT_INPUT_AIN1_SHIFT                     (1U)
/*! AIN1 - Input 1 state. Input 1 state on the last SCT clock edge.
 */
#define SCT_INPUT_AIN1(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK)

#define SCT_INPUT_AIN2_MASK                      (0x4U)
#define SCT_INPUT_AIN2_SHIFT                     (2U)
/*! AIN2 - Input 2 state. Input 2 state on the last SCT clock edge.
 */
#define SCT_INPUT_AIN2(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK)

#define SCT_INPUT_AIN3_MASK                      (0x8U)
#define SCT_INPUT_AIN3_SHIFT                     (3U)
/*! AIN3 - Input 3 state. Input 3 state on the last SCT clock edge.
 */
#define SCT_INPUT_AIN3(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK)

#define SCT_INPUT_AIN4_MASK                      (0x10U)
#define SCT_INPUT_AIN4_SHIFT                     (4U)
/*! AIN4 - Input 4 state. Input 4 state on the last SCT clock edge.
 */
#define SCT_INPUT_AIN4(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK)

#define SCT_INPUT_AIN5_MASK                      (0x20U)
#define SCT_INPUT_AIN5_SHIFT                     (5U)
/*! AIN5 - Input 5 state. Input 5 state on the last SCT clock edge.
 */
#define SCT_INPUT_AIN5(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK)

#define SCT_INPUT_AIN6_MASK                      (0x40U)
#define SCT_INPUT_AIN6_SHIFT                     (6U)
/*! AIN6 - Input 6 state. Input 6 state on the last SCT clock edge.
 */
#define SCT_INPUT_AIN6(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK)

#define SCT_INPUT_AIN7_MASK                      (0x80U)
#define SCT_INPUT_AIN7_SHIFT                     (7U)
/*! AIN7 - Input 7 state. Input 7 state on the last SCT clock edge.
 */
#define SCT_INPUT_AIN7(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK)

#define SCT_INPUT_AIN8_MASK                      (0x100U)
#define SCT_INPUT_AIN8_SHIFT                     (8U)
/*! AIN8 - Input 8 state. Input 8 state on the last SCT clock edge.
 */
#define SCT_INPUT_AIN8(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK)

#define SCT_INPUT_AIN9_MASK                      (0x200U)
#define SCT_INPUT_AIN9_SHIFT                     (9U)
/*! AIN9 - Input 9 state. Input 9 state on the last SCT clock edge.
 */
#define SCT_INPUT_AIN9(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK)

#define SCT_INPUT_AIN10_MASK                     (0x400U)
#define SCT_INPUT_AIN10_SHIFT                    (10U)
/*! AIN10 - Input 10 state. Input 10 state on the last SCT clock edge.
 */
#define SCT_INPUT_AIN10(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK)

#define SCT_INPUT_AIN11_MASK                     (0x800U)
#define SCT_INPUT_AIN11_SHIFT                    (11U)
/*! AIN11 - Input 11 state. Input 11 state on the last SCT clock edge.
 */
#define SCT_INPUT_AIN11(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK)

#define SCT_INPUT_AIN12_MASK                     (0x1000U)
#define SCT_INPUT_AIN12_SHIFT                    (12U)
/*! AIN12 - Input 12 state. Input 12 state on the last SCT clock edge.
 */
#define SCT_INPUT_AIN12(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK)

#define SCT_INPUT_AIN13_MASK                     (0x2000U)
#define SCT_INPUT_AIN13_SHIFT                    (13U)
/*! AIN13 - Input 13 state. Input 13 state on the last SCT clock edge.
 */
#define SCT_INPUT_AIN13(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK)

#define SCT_INPUT_AIN14_MASK                     (0x4000U)
#define SCT_INPUT_AIN14_SHIFT                    (14U)
/*! AIN14 - Input 14 state. Input 14 state on the last SCT clock edge.
 */
#define SCT_INPUT_AIN14(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK)

#define SCT_INPUT_AIN15_MASK                     (0x8000U)
#define SCT_INPUT_AIN15_SHIFT                    (15U)
/*! AIN15 - Input 15 state. Input 15 state on the last SCT clock edge.
 */
#define SCT_INPUT_AIN15(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK)

#define SCT_INPUT_SIN0_MASK                      (0x10000U)
#define SCT_INPUT_SIN0_SHIFT                     (16U)
/*! SIN0 - Input 0 state. Input 0 state following the synchronization specified by INSYNC.
 */
#define SCT_INPUT_SIN0(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK)

#define SCT_INPUT_SIN1_MASK                      (0x20000U)
#define SCT_INPUT_SIN1_SHIFT                     (17U)
/*! SIN1 - Input 1 state. Input 1 state following the synchronization specified by INSYNC.
 */
#define SCT_INPUT_SIN1(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK)

#define SCT_INPUT_SIN2_MASK                      (0x40000U)
#define SCT_INPUT_SIN2_SHIFT                     (18U)
/*! SIN2 - Input 2 state. Input 2 state following the synchronization specified by INSYNC.
 */
#define SCT_INPUT_SIN2(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK)

#define SCT_INPUT_SIN3_MASK                      (0x80000U)
#define SCT_INPUT_SIN3_SHIFT                     (19U)
/*! SIN3 - Input 3 state. Input 3 state following the synchronization specified by INSYNC.
 */
#define SCT_INPUT_SIN3(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK)

#define SCT_INPUT_SIN4_MASK                      (0x100000U)
#define SCT_INPUT_SIN4_SHIFT                     (20U)
/*! SIN4 - Input 4 state. Input 4 state following the synchronization specified by INSYNC.
 */
#define SCT_INPUT_SIN4(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK)

#define SCT_INPUT_SIN5_MASK                      (0x200000U)
#define SCT_INPUT_SIN5_SHIFT                     (21U)
/*! SIN5 - Input 5 state. Input 5 state following the synchronization specified by INSYNC.
 */
#define SCT_INPUT_SIN5(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK)

#define SCT_INPUT_SIN6_MASK                      (0x400000U)
#define SCT_INPUT_SIN6_SHIFT                     (22U)
/*! SIN6 - Input 6 state. Input 6 state following the synchronization specified by INSYNC.
 */
#define SCT_INPUT_SIN6(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK)

#define SCT_INPUT_SIN7_MASK                      (0x800000U)
#define SCT_INPUT_SIN7_SHIFT                     (23U)
/*! SIN7 - Input 7 state. Input 7 state following the synchronization specified by INSYNC.
 */
#define SCT_INPUT_SIN7(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK)

#define SCT_INPUT_SIN8_MASK                      (0x1000000U)
#define SCT_INPUT_SIN8_SHIFT                     (24U)
/*! SIN8 - Input 8 state. Input 8 state following the synchronization specified by INSYNC.
 */
#define SCT_INPUT_SIN8(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK)

#define SCT_INPUT_SIN9_MASK                      (0x2000000U)
#define SCT_INPUT_SIN9_SHIFT                     (25U)
/*! SIN9 - Input 9 state. Input 9 state following the synchronization specified by INSYNC.
 */
#define SCT_INPUT_SIN9(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK)

#define SCT_INPUT_SIN10_MASK                     (0x4000000U)
#define SCT_INPUT_SIN10_SHIFT                    (26U)
/*! SIN10 - Input 10 state. Input 10 state following the synchronization specified by INSYNC.
 */
#define SCT_INPUT_SIN10(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK)

#define SCT_INPUT_SIN11_MASK                     (0x8000000U)
#define SCT_INPUT_SIN11_SHIFT                    (27U)
/*! SIN11 - Input 11 state. Input 11 state following the synchronization specified by INSYNC.
 */
#define SCT_INPUT_SIN11(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK)

#define SCT_INPUT_SIN12_MASK                     (0x10000000U)
#define SCT_INPUT_SIN12_SHIFT                    (28U)
/*! SIN12 - Input 12 state. Input 12 state following the synchronization specified by INSYNC.
 */
#define SCT_INPUT_SIN12(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK)

#define SCT_INPUT_SIN13_MASK                     (0x20000000U)
#define SCT_INPUT_SIN13_SHIFT                    (29U)
/*! SIN13 - Input 13 state. Input 13 state following the synchronization specified by INSYNC.
 */
#define SCT_INPUT_SIN13(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK)

#define SCT_INPUT_SIN14_MASK                     (0x40000000U)
#define SCT_INPUT_SIN14_SHIFT                    (30U)
/*! SIN14 - Input 14 state. Input 14 state following the synchronization specified by INSYNC.
 */
#define SCT_INPUT_SIN14(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK)

#define SCT_INPUT_SIN15_MASK                     (0x80000000U)
#define SCT_INPUT_SIN15_SHIFT                    (31U)
/*! SIN15 - Input 15 state. Input 15 state following the synchronization specified by INSYNC.
 */
#define SCT_INPUT_SIN15(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK)
/*! @} */

/*! @name REGMODEL - SCT_REGMODEL register */
/*! @{ */

#define SCT_REGMODEL_REGMODEL_MASK               (0xFFFFU)
#define SCT_REGMODEL_REGMODEL_SHIFT              (0U)
/*! REGMODEL
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODEL_REGMODEL(x)                 (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEL_REGMODEL_SHIFT)) & SCT_REGMODEL_REGMODEL_MASK)

#define SCT_REGMODEL_REGMOD_L_MASK               (0xFFFFU)
#define SCT_REGMODEL_REGMOD_L_SHIFT              (0U)
#define SCT_REGMODEL_REGMOD_L(x)                 (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEL_REGMOD_L_SHIFT)) & SCT_REGMODEL_REGMOD_L_MASK)

#define SCT_REGMODEL_REGMOD_H_MASK               (0xFFFF0000U)
#define SCT_REGMODEL_REGMOD_H_SHIFT              (16U)
#define SCT_REGMODEL_REGMOD_H(x)                 (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEL_REGMOD_H_SHIFT)) & SCT_REGMODEL_REGMOD_H_MASK)
/*! @} */

/*! @name REGMODEH - SCT_REGMODEH register */
/*! @{ */

#define SCT_REGMODEH_REGMODEH_MASK               (0xFFFFU)
#define SCT_REGMODEH_REGMODEH_SHIFT              (0U)
/*! REGMODEH
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODEH_REGMODEH(x)                 (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEH_REGMODEH_SHIFT)) & SCT_REGMODEH_REGMODEH_MASK)

#define SCT_REGMODEH_REGMOD_L_MASK               (0xFFFFU)
#define SCT_REGMODEH_REGMOD_L_SHIFT              (0U)
#define SCT_REGMODEH_REGMOD_L(x)                 (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEH_REGMOD_L_SHIFT)) & SCT_REGMODEH_REGMOD_L_MASK)

#define SCT_REGMODEH_REGMOD_H_MASK               (0xFFFF0000U)
#define SCT_REGMODEH_REGMOD_H_SHIFT              (16U)
#define SCT_REGMODEH_REGMOD_H(x)                 (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEH_REGMOD_H_SHIFT)) & SCT_REGMODEH_REGMOD_H_MASK)
/*! @} */

/*! @name REGMODE - Match/Capture Mode */
/*! @{ */

#define SCT_REGMODE_REGMOD_L_MASK                (0xFFFFU)
#define SCT_REGMODE_REGMOD_L_SHIFT               (0U)
#define SCT_REGMODE_REGMOD_L(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK)

#define SCT_REGMODE_REGMOD_L0_MASK               (0x1U)
#define SCT_REGMODE_REGMOD_L0_SHIFT              (0U)
/*! REGMOD_L0 - Register Mode Low n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_L0(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L0_SHIFT)) & SCT_REGMODE_REGMOD_L0_MASK)

#define SCT_REGMODE_REGMOD_L1_MASK               (0x2U)
#define SCT_REGMODE_REGMOD_L1_SHIFT              (1U)
/*! REGMOD_L1 - Register Mode Low n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_L1(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L1_SHIFT)) & SCT_REGMODE_REGMOD_L1_MASK)

#define SCT_REGMODE_REGMOD_L2_MASK               (0x4U)
#define SCT_REGMODE_REGMOD_L2_SHIFT              (2U)
/*! REGMOD_L2 - Register Mode Low n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_L2(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L2_SHIFT)) & SCT_REGMODE_REGMOD_L2_MASK)

#define SCT_REGMODE_REGMOD_L3_MASK               (0x8U)
#define SCT_REGMODE_REGMOD_L3_SHIFT              (3U)
/*! REGMOD_L3 - Register Mode Low n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_L3(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L3_SHIFT)) & SCT_REGMODE_REGMOD_L3_MASK)

#define SCT_REGMODE_REGMOD_L4_MASK               (0x10U)
#define SCT_REGMODE_REGMOD_L4_SHIFT              (4U)
/*! REGMOD_L4 - Register Mode Low n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_L4(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L4_SHIFT)) & SCT_REGMODE_REGMOD_L4_MASK)

#define SCT_REGMODE_REGMOD_L5_MASK               (0x20U)
#define SCT_REGMODE_REGMOD_L5_SHIFT              (5U)
/*! REGMOD_L5 - Register Mode Low n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_L5(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L5_SHIFT)) & SCT_REGMODE_REGMOD_L5_MASK)

#define SCT_REGMODE_REGMOD_L6_MASK               (0x40U)
#define SCT_REGMODE_REGMOD_L6_SHIFT              (6U)
/*! REGMOD_L6 - Register Mode Low n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_L6(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L6_SHIFT)) & SCT_REGMODE_REGMOD_L6_MASK)

#define SCT_REGMODE_REGMOD_L7_MASK               (0x80U)
#define SCT_REGMODE_REGMOD_L7_SHIFT              (7U)
/*! REGMOD_L7 - Register Mode Low n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_L7(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L7_SHIFT)) & SCT_REGMODE_REGMOD_L7_MASK)

#define SCT_REGMODE_REGMOD_L8_MASK               (0x100U)
#define SCT_REGMODE_REGMOD_L8_SHIFT              (8U)
/*! REGMOD_L8 - Register Mode Low n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_L8(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L8_SHIFT)) & SCT_REGMODE_REGMOD_L8_MASK)

#define SCT_REGMODE_REGMOD_L9_MASK               (0x200U)
#define SCT_REGMODE_REGMOD_L9_SHIFT              (9U)
/*! REGMOD_L9 - Register Mode Low n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_L9(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L9_SHIFT)) & SCT_REGMODE_REGMOD_L9_MASK)

#define SCT_REGMODE_REGMOD_L10_MASK              (0x400U)
#define SCT_REGMODE_REGMOD_L10_SHIFT             (10U)
/*! REGMOD_L10 - Register Mode Low n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_L10(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L10_SHIFT)) & SCT_REGMODE_REGMOD_L10_MASK)

#define SCT_REGMODE_REGMOD_L11_MASK              (0x800U)
#define SCT_REGMODE_REGMOD_L11_SHIFT             (11U)
/*! REGMOD_L11 - Register Mode Low n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_L11(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L11_SHIFT)) & SCT_REGMODE_REGMOD_L11_MASK)

#define SCT_REGMODE_REGMOD_L12_MASK              (0x1000U)
#define SCT_REGMODE_REGMOD_L12_SHIFT             (12U)
/*! REGMOD_L12 - Register Mode Low n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_L12(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L12_SHIFT)) & SCT_REGMODE_REGMOD_L12_MASK)

#define SCT_REGMODE_REGMOD_L13_MASK              (0x2000U)
#define SCT_REGMODE_REGMOD_L13_SHIFT             (13U)
/*! REGMOD_L13 - Register Mode Low n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_L13(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L13_SHIFT)) & SCT_REGMODE_REGMOD_L13_MASK)

#define SCT_REGMODE_REGMOD_L14_MASK              (0x4000U)
#define SCT_REGMODE_REGMOD_L14_SHIFT             (14U)
/*! REGMOD_L14 - Register Mode Low n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_L14(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L14_SHIFT)) & SCT_REGMODE_REGMOD_L14_MASK)

#define SCT_REGMODE_REGMOD_L15_MASK              (0x8000U)
#define SCT_REGMODE_REGMOD_L15_SHIFT             (15U)
/*! REGMOD_L15 - Register Mode Low n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_L15(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L15_SHIFT)) & SCT_REGMODE_REGMOD_L15_MASK)

#define SCT_REGMODE_REGMOD_H_MASK                (0xFFFF0000U)
#define SCT_REGMODE_REGMOD_H_SHIFT               (16U)
#define SCT_REGMODE_REGMOD_H(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK)

#define SCT_REGMODE_REGMOD_H0_MASK               (0x10000U)
#define SCT_REGMODE_REGMOD_H0_SHIFT              (16U)
/*! REGMOD_H0 - Register Mode High n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_H0(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H0_SHIFT)) & SCT_REGMODE_REGMOD_H0_MASK)

#define SCT_REGMODE_REGMOD_H1_MASK               (0x20000U)
#define SCT_REGMODE_REGMOD_H1_SHIFT              (17U)
/*! REGMOD_H1 - Register Mode High n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_H1(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H1_SHIFT)) & SCT_REGMODE_REGMOD_H1_MASK)

#define SCT_REGMODE_REGMOD_H2_MASK               (0x40000U)
#define SCT_REGMODE_REGMOD_H2_SHIFT              (18U)
/*! REGMOD_H2 - Register Mode High n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_H2(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H2_SHIFT)) & SCT_REGMODE_REGMOD_H2_MASK)

#define SCT_REGMODE_REGMOD_H3_MASK               (0x80000U)
#define SCT_REGMODE_REGMOD_H3_SHIFT              (19U)
/*! REGMOD_H3 - Register Mode High n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_H3(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H3_SHIFT)) & SCT_REGMODE_REGMOD_H3_MASK)

#define SCT_REGMODE_REGMOD_H4_MASK               (0x100000U)
#define SCT_REGMODE_REGMOD_H4_SHIFT              (20U)
/*! REGMOD_H4 - Register Mode High n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_H4(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H4_SHIFT)) & SCT_REGMODE_REGMOD_H4_MASK)

#define SCT_REGMODE_REGMOD_H5_MASK               (0x200000U)
#define SCT_REGMODE_REGMOD_H5_SHIFT              (21U)
/*! REGMOD_H5 - Register Mode High n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_H5(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H5_SHIFT)) & SCT_REGMODE_REGMOD_H5_MASK)

#define SCT_REGMODE_REGMOD_H6_MASK               (0x400000U)
#define SCT_REGMODE_REGMOD_H6_SHIFT              (22U)
/*! REGMOD_H6 - Register Mode High n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_H6(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H6_SHIFT)) & SCT_REGMODE_REGMOD_H6_MASK)

#define SCT_REGMODE_REGMOD_H7_MASK               (0x800000U)
#define SCT_REGMODE_REGMOD_H7_SHIFT              (23U)
/*! REGMOD_H7 - Register Mode High n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_H7(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H7_SHIFT)) & SCT_REGMODE_REGMOD_H7_MASK)

#define SCT_REGMODE_REGMOD_H8_MASK               (0x1000000U)
#define SCT_REGMODE_REGMOD_H8_SHIFT              (24U)
/*! REGMOD_H8 - Register Mode High n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_H8(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H8_SHIFT)) & SCT_REGMODE_REGMOD_H8_MASK)

#define SCT_REGMODE_REGMOD_H9_MASK               (0x2000000U)
#define SCT_REGMODE_REGMOD_H9_SHIFT              (25U)
/*! REGMOD_H9 - Register Mode High n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_H9(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H9_SHIFT)) & SCT_REGMODE_REGMOD_H9_MASK)

#define SCT_REGMODE_REGMOD_H10_MASK              (0x4000000U)
#define SCT_REGMODE_REGMOD_H10_SHIFT             (26U)
/*! REGMOD_H10 - Register Mode High n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_H10(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H10_SHIFT)) & SCT_REGMODE_REGMOD_H10_MASK)

#define SCT_REGMODE_REGMOD_H11_MASK              (0x8000000U)
#define SCT_REGMODE_REGMOD_H11_SHIFT             (27U)
/*! REGMOD_H11 - Register Mode High n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_H11(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H11_SHIFT)) & SCT_REGMODE_REGMOD_H11_MASK)

#define SCT_REGMODE_REGMOD_H12_MASK              (0x10000000U)
#define SCT_REGMODE_REGMOD_H12_SHIFT             (28U)
/*! REGMOD_H12 - Register Mode High n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_H12(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H12_SHIFT)) & SCT_REGMODE_REGMOD_H12_MASK)

#define SCT_REGMODE_REGMOD_H13_MASK              (0x20000000U)
#define SCT_REGMODE_REGMOD_H13_SHIFT             (29U)
/*! REGMOD_H13 - Register Mode High n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_H13(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H13_SHIFT)) & SCT_REGMODE_REGMOD_H13_MASK)

#define SCT_REGMODE_REGMOD_H14_MASK              (0x40000000U)
#define SCT_REGMODE_REGMOD_H14_SHIFT             (30U)
/*! REGMOD_H14 - Register Mode High n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_H14(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H14_SHIFT)) & SCT_REGMODE_REGMOD_H14_MASK)

#define SCT_REGMODE_REGMOD_H15_MASK              (0x80000000U)
#define SCT_REGMODE_REGMOD_H15_SHIFT             (31U)
/*! REGMOD_H15 - Register Mode High n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_H15(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H15_SHIFT)) & SCT_REGMODE_REGMOD_H15_MASK)
/*! @} */

/*! @name OUTPUT - Output */
/*! @{ */

#define SCT_OUTPUT_OUT0_MASK                     (0x1U)
#define SCT_OUTPUT_OUT0_SHIFT                    (0U)
/*! OUT0 - Output n
 *  0b0..Writing a 0 forces the corresponding output low
 *  0b1..Writing a 1 forces the corresponding output high
 */
#define SCT_OUTPUT_OUT0(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT0_SHIFT)) & SCT_OUTPUT_OUT0_MASK)

#define SCT_OUTPUT_OUT1_MASK                     (0x2U)
#define SCT_OUTPUT_OUT1_SHIFT                    (1U)
/*! OUT1 - Output n
 *  0b0..Writing a 0 forces the corresponding output low
 *  0b1..Writing a 1 forces the corresponding output high
 */
#define SCT_OUTPUT_OUT1(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT1_SHIFT)) & SCT_OUTPUT_OUT1_MASK)

#define SCT_OUTPUT_OUT2_MASK                     (0x4U)
#define SCT_OUTPUT_OUT2_SHIFT                    (2U)
/*! OUT2 - Output n
 *  0b0..Writing a 0 forces the corresponding output low
 *  0b1..Writing a 1 forces the corresponding output high
 */
#define SCT_OUTPUT_OUT2(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT2_SHIFT)) & SCT_OUTPUT_OUT2_MASK)

#define SCT_OUTPUT_OUT3_MASK                     (0x8U)
#define SCT_OUTPUT_OUT3_SHIFT                    (3U)
/*! OUT3 - Output n
 *  0b0..Writing a 0 forces the corresponding output low
 *  0b1..Writing a 1 forces the corresponding output high
 */
#define SCT_OUTPUT_OUT3(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT3_SHIFT)) & SCT_OUTPUT_OUT3_MASK)

#define SCT_OUTPUT_OUT4_MASK                     (0x10U)
#define SCT_OUTPUT_OUT4_SHIFT                    (4U)
/*! OUT4 - Output n
 *  0b0..Writing a 0 forces the corresponding output low
 *  0b1..Writing a 1 forces the corresponding output high
 */
#define SCT_OUTPUT_OUT4(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT4_SHIFT)) & SCT_OUTPUT_OUT4_MASK)

#define SCT_OUTPUT_OUT5_MASK                     (0x20U)
#define SCT_OUTPUT_OUT5_SHIFT                    (5U)
/*! OUT5 - Output n
 *  0b0..Writing a 0 forces the corresponding output low
 *  0b1..Writing a 1 forces the corresponding output high
 */
#define SCT_OUTPUT_OUT5(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT5_SHIFT)) & SCT_OUTPUT_OUT5_MASK)

#define SCT_OUTPUT_OUT6_MASK                     (0x40U)
#define SCT_OUTPUT_OUT6_SHIFT                    (6U)
/*! OUT6 - Output n
 *  0b0..Writing a 0 forces the corresponding output low
 *  0b1..Writing a 1 forces the corresponding output high
 */
#define SCT_OUTPUT_OUT6(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT6_SHIFT)) & SCT_OUTPUT_OUT6_MASK)

#define SCT_OUTPUT_OUT7_MASK                     (0x80U)
#define SCT_OUTPUT_OUT7_SHIFT                    (7U)
/*! OUT7 - Output n
 *  0b0..Writing a 0 forces the corresponding output low
 *  0b1..Writing a 1 forces the corresponding output high
 */
#define SCT_OUTPUT_OUT7(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT7_SHIFT)) & SCT_OUTPUT_OUT7_MASK)

#define SCT_OUTPUT_OUT8_MASK                     (0x100U)
#define SCT_OUTPUT_OUT8_SHIFT                    (8U)
/*! OUT8 - Output n
 *  0b0..Writing a 0 forces the corresponding output low
 *  0b1..Writing a 1 forces the corresponding output high
 */
#define SCT_OUTPUT_OUT8(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT8_SHIFT)) & SCT_OUTPUT_OUT8_MASK)

#define SCT_OUTPUT_OUT9_MASK                     (0x200U)
#define SCT_OUTPUT_OUT9_SHIFT                    (9U)
/*! OUT9 - Output n
 *  0b0..Writing a 0 forces the corresponding output low
 *  0b1..Writing a 1 forces the corresponding output high
 */
#define SCT_OUTPUT_OUT9(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT9_SHIFT)) & SCT_OUTPUT_OUT9_MASK)
/*! @} */

/*! @name OUTPUTDIRCTRL - Output Counter Direction Control */
/*! @{ */

#define SCT_OUTPUTDIRCTRL_SETCLR0_MASK           (0x3U)
#define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT          (0U)
/*! SETCLR0 - Set/Clear Operation on Output n
 *  0b00..Set and clear do not depend on the direction of any counter.
 *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
 *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
 *  0b11..Reserved. Do not program this value.
 */
#define SCT_OUTPUTDIRCTRL_SETCLR0(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK)

#define SCT_OUTPUTDIRCTRL_SETCLR1_MASK           (0xCU)
#define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT          (2U)
/*! SETCLR1 - Set/Clear Operation on Output n
 *  0b00..Set and clear do not depend on the direction of any counter.
 *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
 *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
 *  0b11..Reserved. Do not program this value.
 */
#define SCT_OUTPUTDIRCTRL_SETCLR1(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK)

#define SCT_OUTPUTDIRCTRL_SETCLR2_MASK           (0x30U)
#define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT          (4U)
/*! SETCLR2 - Set/Clear Operation on Output n
 *  0b00..Set and clear do not depend on the direction of any counter.
 *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
 *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
 *  0b11..Reserved. Do not program this value.
 */
#define SCT_OUTPUTDIRCTRL_SETCLR2(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK)

#define SCT_OUTPUTDIRCTRL_SETCLR3_MASK           (0xC0U)
#define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT          (6U)
/*! SETCLR3 - Set/Clear Operation on Output n
 *  0b00..Set and clear do not depend on the direction of any counter.
 *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
 *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
 *  0b11..Reserved. Do not program this value.
 */
#define SCT_OUTPUTDIRCTRL_SETCLR3(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK)

#define SCT_OUTPUTDIRCTRL_SETCLR4_MASK           (0x300U)
#define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT          (8U)
/*! SETCLR4 - Set/Clear Operation on Output n
 *  0b00..Set and clear do not depend on the direction of any counter.
 *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
 *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
 *  0b11..Reserved. Do not program this value.
 */
#define SCT_OUTPUTDIRCTRL_SETCLR4(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK)

#define SCT_OUTPUTDIRCTRL_SETCLR5_MASK           (0xC00U)
#define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT          (10U)
/*! SETCLR5 - Set/Clear Operation on Output n
 *  0b00..Set and clear do not depend on the direction of any counter.
 *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
 *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
 *  0b11..Reserved. Do not program this value.
 */
#define SCT_OUTPUTDIRCTRL_SETCLR5(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK)

#define SCT_OUTPUTDIRCTRL_SETCLR6_MASK           (0x3000U)
#define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT          (12U)
/*! SETCLR6 - Set/Clear Operation on Output n
 *  0b00..Set and clear do not depend on the direction of any counter.
 *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
 *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
 *  0b11..Reserved. Do not program this value.
 */
#define SCT_OUTPUTDIRCTRL_SETCLR6(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK)

#define SCT_OUTPUTDIRCTRL_SETCLR7_MASK           (0xC000U)
#define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT          (14U)
/*! SETCLR7 - Set/Clear Operation on Output n
 *  0b00..Set and clear do not depend on the direction of any counter.
 *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
 *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
 *  0b11..Reserved. Do not program this value.
 */
#define SCT_OUTPUTDIRCTRL_SETCLR7(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK)

#define SCT_OUTPUTDIRCTRL_SETCLR8_MASK           (0x30000U)
#define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT          (16U)
/*! SETCLR8 - Set/Clear Operation on Output n
 *  0b00..Set and clear do not depend on the direction of any counter.
 *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
 *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
 *  0b11..Reserved. Do not program this value.
 */
#define SCT_OUTPUTDIRCTRL_SETCLR8(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK)

#define SCT_OUTPUTDIRCTRL_SETCLR9_MASK           (0xC0000U)
#define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT          (18U)
/*! SETCLR9 - Set/Clear Operation on Output n
 *  0b00..Set and clear do not depend on the direction of any counter.
 *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
 *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
 *  0b11..Reserved. Do not program this value.
 */
#define SCT_OUTPUTDIRCTRL_SETCLR9(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK)
/*! @} */

/*! @name RES - Output Conflict Resolution */
/*! @{ */

#define SCT_RES_O0RES_MASK                       (0x3U)
#define SCT_RES_O0RES_SHIFT                      (0U)
/*! O0RES - Effect of simultaneous set and clear on output n
 *  0b00..No change
 *  0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field)
 *  0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field)
 *  0b11..Toggle output
 */
#define SCT_RES_O0RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK)

#define SCT_RES_O1RES_MASK                       (0xCU)
#define SCT_RES_O1RES_SHIFT                      (2U)
/*! O1RES - Effect of simultaneous set and clear on output n
 *  0b00..No change
 *  0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field)
 *  0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field)
 *  0b11..Toggle output
 */
#define SCT_RES_O1RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK)

#define SCT_RES_O2RES_MASK                       (0x30U)
#define SCT_RES_O2RES_SHIFT                      (4U)
/*! O2RES - Effect of simultaneous set and clear on output n
 *  0b00..No change
 *  0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field)
 *  0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field)
 *  0b11..Toggle output
 */
#define SCT_RES_O2RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK)

#define SCT_RES_O3RES_MASK                       (0xC0U)
#define SCT_RES_O3RES_SHIFT                      (6U)
/*! O3RES - Effect of simultaneous set and clear on output n
 *  0b00..No change
 *  0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field)
 *  0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field)
 *  0b11..Toggle output
 */
#define SCT_RES_O3RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK)

#define SCT_RES_O4RES_MASK                       (0x300U)
#define SCT_RES_O4RES_SHIFT                      (8U)
/*! O4RES - Effect of simultaneous set and clear on output n
 *  0b00..No change
 *  0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field)
 *  0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field)
 *  0b11..Toggle output
 */
#define SCT_RES_O4RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK)

#define SCT_RES_O5RES_MASK                       (0xC00U)
#define SCT_RES_O5RES_SHIFT                      (10U)
/*! O5RES - Effect of simultaneous set and clear on output n
 *  0b00..No change
 *  0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field)
 *  0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field)
 *  0b11..Toggle output
 */
#define SCT_RES_O5RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK)

#define SCT_RES_O6RES_MASK                       (0x3000U)
#define SCT_RES_O6RES_SHIFT                      (12U)
/*! O6RES - Effect of simultaneous set and clear on output n
 *  0b00..No change
 *  0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field)
 *  0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field)
 *  0b11..Toggle output
 */
#define SCT_RES_O6RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK)

#define SCT_RES_O7RES_MASK                       (0xC000U)
#define SCT_RES_O7RES_SHIFT                      (14U)
/*! O7RES - Effect of simultaneous set and clear on output n
 *  0b00..No change
 *  0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field)
 *  0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field)
 *  0b11..Toggle output
 */
#define SCT_RES_O7RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK)

#define SCT_RES_O8RES_MASK                       (0x30000U)
#define SCT_RES_O8RES_SHIFT                      (16U)
/*! O8RES - Effect of simultaneous set and clear on output n
 *  0b00..No change
 *  0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field)
 *  0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field)
 *  0b11..Toggle output
 */
#define SCT_RES_O8RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK)

#define SCT_RES_O9RES_MASK                       (0xC0000U)
#define SCT_RES_O9RES_SHIFT                      (18U)
/*! O9RES - Effect of simultaneous set and clear on output n
 *  0b00..No change
 *  0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field)
 *  0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field)
 *  0b11..Toggle output
 */
#define SCT_RES_O9RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK)
/*! @} */

/*! @name DMAREQ0 - DMA Request 0 */
/*! @{ */

#define SCT_DMAREQ0_DEV_0_MASK                   (0x1U)
#define SCT_DMAREQ0_DEV_0_SHIFT                  (0U)
/*! DEV_0 - DMA Request Event n
 */
#define SCT_DMAREQ0_DEV_0(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_0_SHIFT)) & SCT_DMAREQ0_DEV_0_MASK)

#define SCT_DMAREQ0_DEV_1_MASK                   (0x2U)
#define SCT_DMAREQ0_DEV_1_SHIFT                  (1U)
/*! DEV_1 - DMA Request Event n
 */
#define SCT_DMAREQ0_DEV_1(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_1_SHIFT)) & SCT_DMAREQ0_DEV_1_MASK)

#define SCT_DMAREQ0_DEV_2_MASK                   (0x4U)
#define SCT_DMAREQ0_DEV_2_SHIFT                  (2U)
/*! DEV_2 - DMA Request Event n
 */
#define SCT_DMAREQ0_DEV_2(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_2_SHIFT)) & SCT_DMAREQ0_DEV_2_MASK)

#define SCT_DMAREQ0_DEV_3_MASK                   (0x8U)
#define SCT_DMAREQ0_DEV_3_SHIFT                  (3U)
/*! DEV_3 - DMA Request Event n
 */
#define SCT_DMAREQ0_DEV_3(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_3_SHIFT)) & SCT_DMAREQ0_DEV_3_MASK)

#define SCT_DMAREQ0_DEV_4_MASK                   (0x10U)
#define SCT_DMAREQ0_DEV_4_SHIFT                  (4U)
/*! DEV_4 - DMA Request Event n
 */
#define SCT_DMAREQ0_DEV_4(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_4_SHIFT)) & SCT_DMAREQ0_DEV_4_MASK)

#define SCT_DMAREQ0_DEV_5_MASK                   (0x20U)
#define SCT_DMAREQ0_DEV_5_SHIFT                  (5U)
/*! DEV_5 - DMA Request Event n
 */
#define SCT_DMAREQ0_DEV_5(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_5_SHIFT)) & SCT_DMAREQ0_DEV_5_MASK)

#define SCT_DMAREQ0_DEV_6_MASK                   (0x40U)
#define SCT_DMAREQ0_DEV_6_SHIFT                  (6U)
/*! DEV_6 - DMA Request Event n
 */
#define SCT_DMAREQ0_DEV_6(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_6_SHIFT)) & SCT_DMAREQ0_DEV_6_MASK)

#define SCT_DMAREQ0_DEV_7_MASK                   (0x80U)
#define SCT_DMAREQ0_DEV_7_SHIFT                  (7U)
/*! DEV_7 - DMA Request Event n
 */
#define SCT_DMAREQ0_DEV_7(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_7_SHIFT)) & SCT_DMAREQ0_DEV_7_MASK)

#define SCT_DMAREQ0_DEV_8_MASK                   (0x100U)
#define SCT_DMAREQ0_DEV_8_SHIFT                  (8U)
/*! DEV_8 - DMA Request Event n
 */
#define SCT_DMAREQ0_DEV_8(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_8_SHIFT)) & SCT_DMAREQ0_DEV_8_MASK)

#define SCT_DMAREQ0_DEV_9_MASK                   (0x200U)
#define SCT_DMAREQ0_DEV_9_SHIFT                  (9U)
/*! DEV_9 - DMA Request Event n
 */
#define SCT_DMAREQ0_DEV_9(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_9_SHIFT)) & SCT_DMAREQ0_DEV_9_MASK)

#define SCT_DMAREQ0_DEV_10_MASK                  (0x400U)
#define SCT_DMAREQ0_DEV_10_SHIFT                 (10U)
/*! DEV_10 - DMA Request Event n
 */
#define SCT_DMAREQ0_DEV_10(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_10_SHIFT)) & SCT_DMAREQ0_DEV_10_MASK)

#define SCT_DMAREQ0_DEV_11_MASK                  (0x800U)
#define SCT_DMAREQ0_DEV_11_SHIFT                 (11U)
/*! DEV_11 - DMA Request Event n
 */
#define SCT_DMAREQ0_DEV_11(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_11_SHIFT)) & SCT_DMAREQ0_DEV_11_MASK)

#define SCT_DMAREQ0_DEV_12_MASK                  (0x1000U)
#define SCT_DMAREQ0_DEV_12_SHIFT                 (12U)
/*! DEV_12 - DMA Request Event n
 */
#define SCT_DMAREQ0_DEV_12(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_12_SHIFT)) & SCT_DMAREQ0_DEV_12_MASK)

#define SCT_DMAREQ0_DEV_13_MASK                  (0x2000U)
#define SCT_DMAREQ0_DEV_13_SHIFT                 (13U)
/*! DEV_13 - DMA Request Event n
 */
#define SCT_DMAREQ0_DEV_13(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_13_SHIFT)) & SCT_DMAREQ0_DEV_13_MASK)

#define SCT_DMAREQ0_DEV_14_MASK                  (0x4000U)
#define SCT_DMAREQ0_DEV_14_SHIFT                 (14U)
/*! DEV_14 - DMA Request Event n
 */
#define SCT_DMAREQ0_DEV_14(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_14_SHIFT)) & SCT_DMAREQ0_DEV_14_MASK)

#define SCT_DMAREQ0_DEV_15_MASK                  (0x8000U)
#define SCT_DMAREQ0_DEV_15_SHIFT                 (15U)
/*! DEV_15 - DMA Request Event n
 */
#define SCT_DMAREQ0_DEV_15(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_15_SHIFT)) & SCT_DMAREQ0_DEV_15_MASK)

#define SCT_DMAREQ0_DRL0_MASK                    (0x40000000U)
#define SCT_DMAREQ0_DRL0_SHIFT                   (30U)
/*! DRL0 - A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers.
 */
#define SCT_DMAREQ0_DRL0(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRL0_SHIFT)) & SCT_DMAREQ0_DRL0_MASK)

#define SCT_DMAREQ0_DRQ0_MASK                    (0x80000000U)
#define SCT_DMAREQ0_DRQ0_SHIFT                   (31U)
/*! DRQ0 - DMA Request 0 State
 */
#define SCT_DMAREQ0_DRQ0(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRQ0_SHIFT)) & SCT_DMAREQ0_DRQ0_MASK)
/*! @} */

/*! @name DMAREQ1 - DMA Request 1 */
/*! @{ */

#define SCT_DMAREQ1_DEV_0_MASK                   (0x1U)
#define SCT_DMAREQ1_DEV_0_SHIFT                  (0U)
/*! DEV_0 - DMA Request Event n
 */
#define SCT_DMAREQ1_DEV_0(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_0_SHIFT)) & SCT_DMAREQ1_DEV_0_MASK)

#define SCT_DMAREQ1_DEV_1_MASK                   (0x2U)
#define SCT_DMAREQ1_DEV_1_SHIFT                  (1U)
/*! DEV_1 - DMA Request Event n
 */
#define SCT_DMAREQ1_DEV_1(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_1_SHIFT)) & SCT_DMAREQ1_DEV_1_MASK)

#define SCT_DMAREQ1_DEV_2_MASK                   (0x4U)
#define SCT_DMAREQ1_DEV_2_SHIFT                  (2U)
/*! DEV_2 - DMA Request Event n
 */
#define SCT_DMAREQ1_DEV_2(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_2_SHIFT)) & SCT_DMAREQ1_DEV_2_MASK)

#define SCT_DMAREQ1_DEV_3_MASK                   (0x8U)
#define SCT_DMAREQ1_DEV_3_SHIFT                  (3U)
/*! DEV_3 - DMA Request Event n
 */
#define SCT_DMAREQ1_DEV_3(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_3_SHIFT)) & SCT_DMAREQ1_DEV_3_MASK)

#define SCT_DMAREQ1_DEV_4_MASK                   (0x10U)
#define SCT_DMAREQ1_DEV_4_SHIFT                  (4U)
/*! DEV_4 - DMA Request Event n
 */
#define SCT_DMAREQ1_DEV_4(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_4_SHIFT)) & SCT_DMAREQ1_DEV_4_MASK)

#define SCT_DMAREQ1_DEV_5_MASK                   (0x20U)
#define SCT_DMAREQ1_DEV_5_SHIFT                  (5U)
/*! DEV_5 - DMA Request Event n
 */
#define SCT_DMAREQ1_DEV_5(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_5_SHIFT)) & SCT_DMAREQ1_DEV_5_MASK)

#define SCT_DMAREQ1_DEV_6_MASK                   (0x40U)
#define SCT_DMAREQ1_DEV_6_SHIFT                  (6U)
/*! DEV_6 - DMA Request Event n
 */
#define SCT_DMAREQ1_DEV_6(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_6_SHIFT)) & SCT_DMAREQ1_DEV_6_MASK)

#define SCT_DMAREQ1_DEV_7_MASK                   (0x80U)
#define SCT_DMAREQ1_DEV_7_SHIFT                  (7U)
/*! DEV_7 - DMA Request Event n
 */
#define SCT_DMAREQ1_DEV_7(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_7_SHIFT)) & SCT_DMAREQ1_DEV_7_MASK)

#define SCT_DMAREQ1_DEV_8_MASK                   (0x100U)
#define SCT_DMAREQ1_DEV_8_SHIFT                  (8U)
/*! DEV_8 - DMA Request Event n
 */
#define SCT_DMAREQ1_DEV_8(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_8_SHIFT)) & SCT_DMAREQ1_DEV_8_MASK)

#define SCT_DMAREQ1_DEV_9_MASK                   (0x200U)
#define SCT_DMAREQ1_DEV_9_SHIFT                  (9U)
/*! DEV_9 - DMA Request Event n
 */
#define SCT_DMAREQ1_DEV_9(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_9_SHIFT)) & SCT_DMAREQ1_DEV_9_MASK)

#define SCT_DMAREQ1_DEV_10_MASK                  (0x400U)
#define SCT_DMAREQ1_DEV_10_SHIFT                 (10U)
/*! DEV_10 - DMA Request Event n
 */
#define SCT_DMAREQ1_DEV_10(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_10_SHIFT)) & SCT_DMAREQ1_DEV_10_MASK)

#define SCT_DMAREQ1_DEV_11_MASK                  (0x800U)
#define SCT_DMAREQ1_DEV_11_SHIFT                 (11U)
/*! DEV_11 - DMA Request Event n
 */
#define SCT_DMAREQ1_DEV_11(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_11_SHIFT)) & SCT_DMAREQ1_DEV_11_MASK)

#define SCT_DMAREQ1_DEV_12_MASK                  (0x1000U)
#define SCT_DMAREQ1_DEV_12_SHIFT                 (12U)
/*! DEV_12 - DMA Request Event n
 */
#define SCT_DMAREQ1_DEV_12(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_12_SHIFT)) & SCT_DMAREQ1_DEV_12_MASK)

#define SCT_DMAREQ1_DEV_13_MASK                  (0x2000U)
#define SCT_DMAREQ1_DEV_13_SHIFT                 (13U)
/*! DEV_13 - DMA Request Event n
 */
#define SCT_DMAREQ1_DEV_13(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_13_SHIFT)) & SCT_DMAREQ1_DEV_13_MASK)

#define SCT_DMAREQ1_DEV_14_MASK                  (0x4000U)
#define SCT_DMAREQ1_DEV_14_SHIFT                 (14U)
/*! DEV_14 - DMA Request Event n
 */
#define SCT_DMAREQ1_DEV_14(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_14_SHIFT)) & SCT_DMAREQ1_DEV_14_MASK)

#define SCT_DMAREQ1_DEV_15_MASK                  (0x8000U)
#define SCT_DMAREQ1_DEV_15_SHIFT                 (15U)
/*! DEV_15 - DMA Request Event n
 */
#define SCT_DMAREQ1_DEV_15(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_15_SHIFT)) & SCT_DMAREQ1_DEV_15_MASK)

#define SCT_DMAREQ1_DRL1_MASK                    (0x40000000U)
#define SCT_DMAREQ1_DRL1_SHIFT                   (30U)
/*! DRL1 - A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers.
 */
#define SCT_DMAREQ1_DRL1(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRL1_SHIFT)) & SCT_DMAREQ1_DRL1_MASK)

#define SCT_DMAREQ1_DRQ1_MASK                    (0x80000000U)
#define SCT_DMAREQ1_DRQ1_SHIFT                   (31U)
/*! DRQ1 - DMA Request 1 State
 */
#define SCT_DMAREQ1_DRQ1(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRQ1_SHIFT)) & SCT_DMAREQ1_DRQ1_MASK)
/*! @} */

/*! @name EVEN - Event Interrupt Enable */
/*! @{ */

#define SCT_EVEN_IEN0_MASK                       (0x1U)
#define SCT_EVEN_IEN0_SHIFT                      (0U)
/*! IEN0 - Event Interrupt Enable n
 *  0b0..Disable
 *  0b1..Enable
 */
#define SCT_EVEN_IEN0(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN0_SHIFT)) & SCT_EVEN_IEN0_MASK)

#define SCT_EVEN_IEN1_MASK                       (0x2U)
#define SCT_EVEN_IEN1_SHIFT                      (1U)
/*! IEN1 - Event Interrupt Enable n
 *  0b0..Disable
 *  0b1..Enable
 */
#define SCT_EVEN_IEN1(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN1_SHIFT)) & SCT_EVEN_IEN1_MASK)

#define SCT_EVEN_IEN2_MASK                       (0x4U)
#define SCT_EVEN_IEN2_SHIFT                      (2U)
/*! IEN2 - Event Interrupt Enable n
 *  0b0..Disable
 *  0b1..Enable
 */
#define SCT_EVEN_IEN2(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN2_SHIFT)) & SCT_EVEN_IEN2_MASK)

#define SCT_EVEN_IEN3_MASK                       (0x8U)
#define SCT_EVEN_IEN3_SHIFT                      (3U)
/*! IEN3 - Event Interrupt Enable n
 *  0b0..Disable
 *  0b1..Enable
 */
#define SCT_EVEN_IEN3(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN3_SHIFT)) & SCT_EVEN_IEN3_MASK)

#define SCT_EVEN_IEN4_MASK                       (0x10U)
#define SCT_EVEN_IEN4_SHIFT                      (4U)
/*! IEN4 - Event Interrupt Enable n
 *  0b0..Disable
 *  0b1..Enable
 */
#define SCT_EVEN_IEN4(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN4_SHIFT)) & SCT_EVEN_IEN4_MASK)

#define SCT_EVEN_IEN5_MASK                       (0x20U)
#define SCT_EVEN_IEN5_SHIFT                      (5U)
/*! IEN5 - Event Interrupt Enable n
 *  0b0..Disable
 *  0b1..Enable
 */
#define SCT_EVEN_IEN5(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN5_SHIFT)) & SCT_EVEN_IEN5_MASK)

#define SCT_EVEN_IEN6_MASK                       (0x40U)
#define SCT_EVEN_IEN6_SHIFT                      (6U)
/*! IEN6 - Event Interrupt Enable n
 *  0b0..Disable
 *  0b1..Enable
 */
#define SCT_EVEN_IEN6(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN6_SHIFT)) & SCT_EVEN_IEN6_MASK)

#define SCT_EVEN_IEN7_MASK                       (0x80U)
#define SCT_EVEN_IEN7_SHIFT                      (7U)
/*! IEN7 - Event Interrupt Enable n
 *  0b0..Disable
 *  0b1..Enable
 */
#define SCT_EVEN_IEN7(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN7_SHIFT)) & SCT_EVEN_IEN7_MASK)

#define SCT_EVEN_IEN8_MASK                       (0x100U)
#define SCT_EVEN_IEN8_SHIFT                      (8U)
/*! IEN8 - Event Interrupt Enable n
 *  0b0..Disable
 *  0b1..Enable
 */
#define SCT_EVEN_IEN8(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN8_SHIFT)) & SCT_EVEN_IEN8_MASK)

#define SCT_EVEN_IEN9_MASK                       (0x200U)
#define SCT_EVEN_IEN9_SHIFT                      (9U)
/*! IEN9 - Event Interrupt Enable n
 *  0b0..Disable
 *  0b1..Enable
 */
#define SCT_EVEN_IEN9(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN9_SHIFT)) & SCT_EVEN_IEN9_MASK)

#define SCT_EVEN_IEN10_MASK                      (0x400U)
#define SCT_EVEN_IEN10_SHIFT                     (10U)
/*! IEN10 - Event Interrupt Enable n
 *  0b0..Disable
 *  0b1..Enable
 */
#define SCT_EVEN_IEN10(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN10_SHIFT)) & SCT_EVEN_IEN10_MASK)

#define SCT_EVEN_IEN11_MASK                      (0x800U)
#define SCT_EVEN_IEN11_SHIFT                     (11U)
/*! IEN11 - Event Interrupt Enable n
 *  0b0..Disable
 *  0b1..Enable
 */
#define SCT_EVEN_IEN11(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN11_SHIFT)) & SCT_EVEN_IEN11_MASK)

#define SCT_EVEN_IEN12_MASK                      (0x1000U)
#define SCT_EVEN_IEN12_SHIFT                     (12U)
/*! IEN12 - Event Interrupt Enable n
 *  0b0..Disable
 *  0b1..Enable
 */
#define SCT_EVEN_IEN12(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN12_SHIFT)) & SCT_EVEN_IEN12_MASK)

#define SCT_EVEN_IEN13_MASK                      (0x2000U)
#define SCT_EVEN_IEN13_SHIFT                     (13U)
/*! IEN13 - Event Interrupt Enable n
 *  0b0..Disable
 *  0b1..Enable
 */
#define SCT_EVEN_IEN13(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN13_SHIFT)) & SCT_EVEN_IEN13_MASK)

#define SCT_EVEN_IEN14_MASK                      (0x4000U)
#define SCT_EVEN_IEN14_SHIFT                     (14U)
/*! IEN14 - Event Interrupt Enable n
 *  0b0..Disable
 *  0b1..Enable
 */
#define SCT_EVEN_IEN14(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN14_SHIFT)) & SCT_EVEN_IEN14_MASK)

#define SCT_EVEN_IEN15_MASK                      (0x8000U)
#define SCT_EVEN_IEN15_SHIFT                     (15U)
/*! IEN15 - Event Interrupt Enable n
 *  0b0..Disable
 *  0b1..Enable
 */
#define SCT_EVEN_IEN15(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN15_SHIFT)) & SCT_EVEN_IEN15_MASK)
/*! @} */

/*! @name EVFLAG - Event Flag */
/*! @{ */

#define SCT_EVFLAG_FLAG0_MASK                    (0x1U)
#define SCT_EVFLAG_FLAG0_SHIFT                   (0U)
/*! FLAG0 - Event Flag n
 *  0b0..No Flag
 *  0b1..Event n Flag
 */
#define SCT_EVFLAG_FLAG0(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG0_SHIFT)) & SCT_EVFLAG_FLAG0_MASK)

#define SCT_EVFLAG_FLAG1_MASK                    (0x2U)
#define SCT_EVFLAG_FLAG1_SHIFT                   (1U)
/*! FLAG1 - Event Flag n
 *  0b0..No Flag
 *  0b1..Event n Flag
 */
#define SCT_EVFLAG_FLAG1(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG1_SHIFT)) & SCT_EVFLAG_FLAG1_MASK)

#define SCT_EVFLAG_FLAG2_MASK                    (0x4U)
#define SCT_EVFLAG_FLAG2_SHIFT                   (2U)
/*! FLAG2 - Event Flag n
 *  0b0..No Flag
 *  0b1..Event n Flag
 */
#define SCT_EVFLAG_FLAG2(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG2_SHIFT)) & SCT_EVFLAG_FLAG2_MASK)

#define SCT_EVFLAG_FLAG3_MASK                    (0x8U)
#define SCT_EVFLAG_FLAG3_SHIFT                   (3U)
/*! FLAG3 - Event Flag n
 *  0b0..No Flag
 *  0b1..Event n Flag
 */
#define SCT_EVFLAG_FLAG3(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG3_SHIFT)) & SCT_EVFLAG_FLAG3_MASK)

#define SCT_EVFLAG_FLAG4_MASK                    (0x10U)
#define SCT_EVFLAG_FLAG4_SHIFT                   (4U)
/*! FLAG4 - Event Flag n
 *  0b0..No Flag
 *  0b1..Event n Flag
 */
#define SCT_EVFLAG_FLAG4(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG4_SHIFT)) & SCT_EVFLAG_FLAG4_MASK)

#define SCT_EVFLAG_FLAG5_MASK                    (0x20U)
#define SCT_EVFLAG_FLAG5_SHIFT                   (5U)
/*! FLAG5 - Event Flag n
 *  0b0..No Flag
 *  0b1..Event n Flag
 */
#define SCT_EVFLAG_FLAG5(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG5_SHIFT)) & SCT_EVFLAG_FLAG5_MASK)

#define SCT_EVFLAG_FLAG6_MASK                    (0x40U)
#define SCT_EVFLAG_FLAG6_SHIFT                   (6U)
/*! FLAG6 - Event Flag n
 *  0b0..No Flag
 *  0b1..Event n Flag
 */
#define SCT_EVFLAG_FLAG6(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG6_SHIFT)) & SCT_EVFLAG_FLAG6_MASK)

#define SCT_EVFLAG_FLAG7_MASK                    (0x80U)
#define SCT_EVFLAG_FLAG7_SHIFT                   (7U)
/*! FLAG7 - Event Flag n
 *  0b0..No Flag
 *  0b1..Event n Flag
 */
#define SCT_EVFLAG_FLAG7(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG7_SHIFT)) & SCT_EVFLAG_FLAG7_MASK)

#define SCT_EVFLAG_FLAG8_MASK                    (0x100U)
#define SCT_EVFLAG_FLAG8_SHIFT                   (8U)
/*! FLAG8 - Event Flag n
 *  0b0..No Flag
 *  0b1..Event n Flag
 */
#define SCT_EVFLAG_FLAG8(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG8_SHIFT)) & SCT_EVFLAG_FLAG8_MASK)

#define SCT_EVFLAG_FLAG9_MASK                    (0x200U)
#define SCT_EVFLAG_FLAG9_SHIFT                   (9U)
/*! FLAG9 - Event Flag n
 *  0b0..No Flag
 *  0b1..Event n Flag
 */
#define SCT_EVFLAG_FLAG9(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG9_SHIFT)) & SCT_EVFLAG_FLAG9_MASK)

#define SCT_EVFLAG_FLAG10_MASK                   (0x400U)
#define SCT_EVFLAG_FLAG10_SHIFT                  (10U)
/*! FLAG10 - Event Flag n
 *  0b0..No Flag
 *  0b1..Event n Flag
 */
#define SCT_EVFLAG_FLAG10(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG10_SHIFT)) & SCT_EVFLAG_FLAG10_MASK)

#define SCT_EVFLAG_FLAG11_MASK                   (0x800U)
#define SCT_EVFLAG_FLAG11_SHIFT                  (11U)
/*! FLAG11 - Event Flag n
 *  0b0..No Flag
 *  0b1..Event n Flag
 */
#define SCT_EVFLAG_FLAG11(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG11_SHIFT)) & SCT_EVFLAG_FLAG11_MASK)

#define SCT_EVFLAG_FLAG12_MASK                   (0x1000U)
#define SCT_EVFLAG_FLAG12_SHIFT                  (12U)
/*! FLAG12 - Event Flag n
 *  0b0..No Flag
 *  0b1..Event n Flag
 */
#define SCT_EVFLAG_FLAG12(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG12_SHIFT)) & SCT_EVFLAG_FLAG12_MASK)

#define SCT_EVFLAG_FLAG13_MASK                   (0x2000U)
#define SCT_EVFLAG_FLAG13_SHIFT                  (13U)
/*! FLAG13 - Event Flag n
 *  0b0..No Flag
 *  0b1..Event n Flag
 */
#define SCT_EVFLAG_FLAG13(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG13_SHIFT)) & SCT_EVFLAG_FLAG13_MASK)

#define SCT_EVFLAG_FLAG14_MASK                   (0x4000U)
#define SCT_EVFLAG_FLAG14_SHIFT                  (14U)
/*! FLAG14 - Event Flag n
 *  0b0..No Flag
 *  0b1..Event n Flag
 */
#define SCT_EVFLAG_FLAG14(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG14_SHIFT)) & SCT_EVFLAG_FLAG14_MASK)

#define SCT_EVFLAG_FLAG15_MASK                   (0x8000U)
#define SCT_EVFLAG_FLAG15_SHIFT                  (15U)
/*! FLAG15 - Event Flag n
 *  0b0..No Flag
 *  0b1..Event n Flag
 */
#define SCT_EVFLAG_FLAG15(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG15_SHIFT)) & SCT_EVFLAG_FLAG15_MASK)
/*! @} */

/*! @name CONEN - Conflict Interrupt Enable */
/*! @{ */

#define SCT_CONEN_NCEN0_MASK                     (0x1U)
#define SCT_CONEN_NCEN0_SHIFT                    (0U)
/*! NCEN0 - No Change Conflict Event/Interrupt Enable
 *  0b0..No interrupt
 *  0b1..Interrupt
 */
#define SCT_CONEN_NCEN0(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN0_SHIFT)) & SCT_CONEN_NCEN0_MASK)

#define SCT_CONEN_NCEN1_MASK                     (0x2U)
#define SCT_CONEN_NCEN1_SHIFT                    (1U)
/*! NCEN1 - No Change Conflict Event/Interrupt Enable
 *  0b0..No interrupt
 *  0b1..Interrupt
 */
#define SCT_CONEN_NCEN1(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN1_SHIFT)) & SCT_CONEN_NCEN1_MASK)

#define SCT_CONEN_NCEN2_MASK                     (0x4U)
#define SCT_CONEN_NCEN2_SHIFT                    (2U)
/*! NCEN2 - No Change Conflict Event/Interrupt Enable
 *  0b0..No interrupt
 *  0b1..Interrupt
 */
#define SCT_CONEN_NCEN2(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN2_SHIFT)) & SCT_CONEN_NCEN2_MASK)

#define SCT_CONEN_NCEN3_MASK                     (0x8U)
#define SCT_CONEN_NCEN3_SHIFT                    (3U)
/*! NCEN3 - No Change Conflict Event/Interrupt Enable
 *  0b0..No interrupt
 *  0b1..Interrupt
 */
#define SCT_CONEN_NCEN3(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN3_SHIFT)) & SCT_CONEN_NCEN3_MASK)

#define SCT_CONEN_NCEN4_MASK                     (0x10U)
#define SCT_CONEN_NCEN4_SHIFT                    (4U)
/*! NCEN4 - No Change Conflict Event/Interrupt Enable
 *  0b0..No interrupt
 *  0b1..Interrupt
 */
#define SCT_CONEN_NCEN4(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN4_SHIFT)) & SCT_CONEN_NCEN4_MASK)

#define SCT_CONEN_NCEN5_MASK                     (0x20U)
#define SCT_CONEN_NCEN5_SHIFT                    (5U)
/*! NCEN5 - No Change Conflict Event/Interrupt Enable
 *  0b0..No interrupt
 *  0b1..Interrupt
 */
#define SCT_CONEN_NCEN5(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN5_SHIFT)) & SCT_CONEN_NCEN5_MASK)

#define SCT_CONEN_NCEN6_MASK                     (0x40U)
#define SCT_CONEN_NCEN6_SHIFT                    (6U)
/*! NCEN6 - No Change Conflict Event/Interrupt Enable
 *  0b0..No interrupt
 *  0b1..Interrupt
 */
#define SCT_CONEN_NCEN6(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN6_SHIFT)) & SCT_CONEN_NCEN6_MASK)

#define SCT_CONEN_NCEN7_MASK                     (0x80U)
#define SCT_CONEN_NCEN7_SHIFT                    (7U)
/*! NCEN7 - No Change Conflict Event/Interrupt Enable
 *  0b0..No interrupt
 *  0b1..Interrupt
 */
#define SCT_CONEN_NCEN7(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN7_SHIFT)) & SCT_CONEN_NCEN7_MASK)

#define SCT_CONEN_NCEN8_MASK                     (0x100U)
#define SCT_CONEN_NCEN8_SHIFT                    (8U)
/*! NCEN8 - No Change Conflict Event/Interrupt Enable
 *  0b0..No interrupt
 *  0b1..Interrupt
 */
#define SCT_CONEN_NCEN8(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN8_SHIFT)) & SCT_CONEN_NCEN8_MASK)

#define SCT_CONEN_NCEN9_MASK                     (0x200U)
#define SCT_CONEN_NCEN9_SHIFT                    (9U)
/*! NCEN9 - No Change Conflict Event/Interrupt Enable
 *  0b0..No interrupt
 *  0b1..Interrupt
 */
#define SCT_CONEN_NCEN9(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN9_SHIFT)) & SCT_CONEN_NCEN9_MASK)
/*! @} */

/*! @name CONFLAG - Conflict Flag */
/*! @{ */

#define SCT_CONFLAG_NCFLAG0_MASK                 (0x1U)
#define SCT_CONFLAG_NCFLAG0_SHIFT                (0U)
/*! NCFLAG0 - No Change Conflict Event Flag
 *  0b0..No Conflict Event
 *  0b1..A No Change Conflict Event occured
 */
#define SCT_CONFLAG_NCFLAG0(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG0_SHIFT)) & SCT_CONFLAG_NCFLAG0_MASK)

#define SCT_CONFLAG_NCFLAG1_MASK                 (0x2U)
#define SCT_CONFLAG_NCFLAG1_SHIFT                (1U)
/*! NCFLAG1 - No Change Conflict Event Flag
 *  0b0..No Conflict Event
 *  0b1..A No Change Conflict Event occured
 */
#define SCT_CONFLAG_NCFLAG1(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG1_SHIFT)) & SCT_CONFLAG_NCFLAG1_MASK)

#define SCT_CONFLAG_NCFLAG2_MASK                 (0x4U)
#define SCT_CONFLAG_NCFLAG2_SHIFT                (2U)
/*! NCFLAG2 - No Change Conflict Event Flag
 *  0b0..No Conflict Event
 *  0b1..A No Change Conflict Event occured
 */
#define SCT_CONFLAG_NCFLAG2(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG2_SHIFT)) & SCT_CONFLAG_NCFLAG2_MASK)

#define SCT_CONFLAG_NCFLAG3_MASK                 (0x8U)
#define SCT_CONFLAG_NCFLAG3_SHIFT                (3U)
/*! NCFLAG3 - No Change Conflict Event Flag
 *  0b0..No Conflict Event
 *  0b1..A No Change Conflict Event occured
 */
#define SCT_CONFLAG_NCFLAG3(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG3_SHIFT)) & SCT_CONFLAG_NCFLAG3_MASK)

#define SCT_CONFLAG_NCFLAG4_MASK                 (0x10U)
#define SCT_CONFLAG_NCFLAG4_SHIFT                (4U)
/*! NCFLAG4 - No Change Conflict Event Flag
 *  0b0..No Conflict Event
 *  0b1..A No Change Conflict Event occured
 */
#define SCT_CONFLAG_NCFLAG4(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG4_SHIFT)) & SCT_CONFLAG_NCFLAG4_MASK)

#define SCT_CONFLAG_NCFLAG5_MASK                 (0x20U)
#define SCT_CONFLAG_NCFLAG5_SHIFT                (5U)
/*! NCFLAG5 - No Change Conflict Event Flag
 *  0b0..No Conflict Event
 *  0b1..A No Change Conflict Event occured
 */
#define SCT_CONFLAG_NCFLAG5(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG5_SHIFT)) & SCT_CONFLAG_NCFLAG5_MASK)

#define SCT_CONFLAG_NCFLAG6_MASK                 (0x40U)
#define SCT_CONFLAG_NCFLAG6_SHIFT                (6U)
/*! NCFLAG6 - No Change Conflict Event Flag
 *  0b0..No Conflict Event
 *  0b1..A No Change Conflict Event occured
 */
#define SCT_CONFLAG_NCFLAG6(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG6_SHIFT)) & SCT_CONFLAG_NCFLAG6_MASK)

#define SCT_CONFLAG_NCFLAG7_MASK                 (0x80U)
#define SCT_CONFLAG_NCFLAG7_SHIFT                (7U)
/*! NCFLAG7 - No Change Conflict Event Flag
 *  0b0..No Conflict Event
 *  0b1..A No Change Conflict Event occured
 */
#define SCT_CONFLAG_NCFLAG7(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG7_SHIFT)) & SCT_CONFLAG_NCFLAG7_MASK)

#define SCT_CONFLAG_NCFLAG8_MASK                 (0x100U)
#define SCT_CONFLAG_NCFLAG8_SHIFT                (8U)
/*! NCFLAG8 - No Change Conflict Event Flag
 *  0b0..No Conflict Event
 *  0b1..A No Change Conflict Event occured
 */
#define SCT_CONFLAG_NCFLAG8(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG8_SHIFT)) & SCT_CONFLAG_NCFLAG8_MASK)

#define SCT_CONFLAG_NCFLAG9_MASK                 (0x200U)
#define SCT_CONFLAG_NCFLAG9_SHIFT                (9U)
/*! NCFLAG9 - No Change Conflict Event Flag
 *  0b0..No Conflict Event
 *  0b1..A No Change Conflict Event occured
 */
#define SCT_CONFLAG_NCFLAG9(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG9_SHIFT)) & SCT_CONFLAG_NCFLAG9_MASK)

#define SCT_CONFLAG_BUSERRL_MASK                 (0x40000000U)
#define SCT_CONFLAG_BUSERRL_SHIFT                (30U)
/*! BUSERRL - Bus Error Low/Unified
 */
#define SCT_CONFLAG_BUSERRL(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK)

#define SCT_CONFLAG_BUSERRH_MASK                 (0x80000000U)
#define SCT_CONFLAG_BUSERRH_SHIFT                (31U)
/*! BUSERRH - Bus Error High
 */
#define SCT_CONFLAG_BUSERRH(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK)
/*! @} */

/*! @name CAPL - SCT_CAPL register */
/*! @{ */

#define SCT_CAPL_CAPL_MASK                       (0xFFFFU)
#define SCT_CAPL_CAPL_SHIFT                      (0U)
#define SCT_CAPL_CAPL(x)                         (((uint16_t)(((uint16_t)(x)) << SCT_CAPL_CAPL_SHIFT)) & SCT_CAPL_CAPL_MASK)
/*! @} */

/* The count of SCT_CAPL */
#define SCT_CAPL_COUNT                           (16U)

/*! @name CAPH - SCT_CAPH register */
/*! @{ */

#define SCT_CAPH_CAPH_MASK                       (0xFFFFU)
#define SCT_CAPH_CAPH_SHIFT                      (0U)
#define SCT_CAPH_CAPH(x)                         (((uint16_t)(((uint16_t)(x)) << SCT_CAPH_CAPH_SHIFT)) & SCT_CAPH_CAPH_MASK)
/*! @} */

/* The count of SCT_CAPH */
#define SCT_CAPH_COUNT                           (16U)

/*! @name CAP - Capture Value */
/*! @{ */

#define SCT_CAP_CAPn_L_MASK                      (0xFFFFU)
#define SCT_CAP_CAPn_L_SHIFT                     (0U)
/*! CAPn_L - Capture n Low
 */
#define SCT_CAP_CAPn_L(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_L_SHIFT)) & SCT_CAP_CAPn_L_MASK)

#define SCT_CAP_CAPn_H_MASK                      (0xFFFF0000U)
#define SCT_CAP_CAPn_H_SHIFT                     (16U)
/*! CAPn_H - Capture n High
 */
#define SCT_CAP_CAPn_H(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_H_SHIFT)) & SCT_CAP_CAPn_H_MASK)
/*! @} */

/* The count of SCT_CAP */
#define SCT_CAP_COUNT                            (16U)

/*! @name MATCHL - SCT_MATCHL register */
/*! @{ */

#define SCT_MATCHL_MATCHL_MASK                   (0xFFFFU)
#define SCT_MATCHL_MATCHL_SHIFT                  (0U)
#define SCT_MATCHL_MATCHL(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_MATCHL_MATCHL_SHIFT)) & SCT_MATCHL_MATCHL_MASK)
/*! @} */

/* The count of SCT_MATCHL */
#define SCT_MATCHL_COUNT                         (16U)

/*! @name MATCHH - SCT_MATCHH register */
/*! @{ */

#define SCT_MATCHH_MATCHH_MASK                   (0xFFFFU)
#define SCT_MATCHH_MATCHH_SHIFT                  (0U)
#define SCT_MATCHH_MATCHH(x)                     (((uint16_t)(((uint16_t)(x)) << SCT_MATCHH_MATCHH_SHIFT)) & SCT_MATCHH_MATCHH_MASK)
/*! @} */

/* The count of SCT_MATCHH */
#define SCT_MATCHH_COUNT                         (16U)

/*! @name MATCH - Match Value */
/*! @{ */

#define SCT_MATCH_MATCHn_L_MASK                  (0xFFFFU)
#define SCT_MATCH_MATCHn_L_SHIFT                 (0U)
/*! MATCHn_L - Match n Low
 */
#define SCT_MATCH_MATCHn_L(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_L_SHIFT)) & SCT_MATCH_MATCHn_L_MASK)

#define SCT_MATCH_MATCHn_H_MASK                  (0xFFFF0000U)
#define SCT_MATCH_MATCHn_H_SHIFT                 (16U)
/*! MATCHn_H - Match n High
 */
#define SCT_MATCH_MATCHn_H(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_H_SHIFT)) & SCT_MATCH_MATCHn_H_MASK)
/*! @} */

/* The count of SCT_MATCH */
#define SCT_MATCH_COUNT                          (16U)

/*! @name FRACMAT - Fractional Match */
/*! @{ */

#define SCT_FRACMAT_FRACMAT_L_MASK               (0xFU)
#define SCT_FRACMAT_FRACMAT_L_SHIFT              (0U)
/*! FRACMAT_L - Fractional Match Low
 */
#define SCT_FRACMAT_FRACMAT_L(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_FRACMAT_FRACMAT_L_SHIFT)) & SCT_FRACMAT_FRACMAT_L_MASK)

#define SCT_FRACMAT_FRACMAT_H_MASK               (0xF0000U)
#define SCT_FRACMAT_FRACMAT_H_SHIFT              (16U)
/*! FRACMAT_H - Fractional Match High
 */
#define SCT_FRACMAT_FRACMAT_H(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_FRACMAT_FRACMAT_H_SHIFT)) & SCT_FRACMAT_FRACMAT_H_MASK)
/*! @} */

/* The count of SCT_FRACMAT */
#define SCT_FRACMAT_COUNT                        (6U)

/*! @name CAPCTRLL - SCT_CAPCTRLL register */
/*! @{ */

#define SCT_CAPCTRLL_CAPCTRLL_MASK               (0xFFFFU)
#define SCT_CAPCTRLL_CAPCTRLL_SHIFT              (0U)
#define SCT_CAPCTRLL_CAPCTRLL(x)                 (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLL_CAPCTRLL_SHIFT)) & SCT_CAPCTRLL_CAPCTRLL_MASK)
/*! @} */

/* The count of SCT_CAPCTRLL */
#define SCT_CAPCTRLL_COUNT                       (16U)

/*! @name CAPCTRLH - SCT_CAPCTRLH register */
/*! @{ */

#define SCT_CAPCTRLH_CAPCTRLH_MASK               (0xFFFFU)
#define SCT_CAPCTRLH_CAPCTRLH_SHIFT              (0U)
#define SCT_CAPCTRLH_CAPCTRLH(x)                 (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLH_CAPCTRLH_SHIFT)) & SCT_CAPCTRLH_CAPCTRLH_MASK)
/*! @} */

/* The count of SCT_CAPCTRLH */
#define SCT_CAPCTRLH_COUNT                       (16U)

/*! @name SCTCAPCTRL_CAPCTRL - Capture Control */
/*! @{ */

#define SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_L_MASK    (0xFFFFU)
#define SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_L_SHIFT   (0U)
/*! CAPCONn_L - Capture Control n Low
 */
#define SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_L(x)      (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_L_SHIFT)) & SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_L_MASK)

#define SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_H_MASK    (0xFFFF0000U)
#define SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_H_SHIFT   (16U)
/*! CAPCONn_H - Capture Control n High
 */
#define SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_H(x)      (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_H_SHIFT)) & SCT_SCTCAPCTRL_CAPCTRL_CAPCONn_H_MASK)
/*! @} */

/* The count of SCT_SCTCAPCTRL_CAPCTRL */
#define SCT_SCTCAPCTRL_CAPCTRL_COUNT             (16U)

/*! @name MATCHRELL - SCT_MATCHRELL register */
/*! @{ */

#define SCT_MATCHRELL_MATCHRELL_MASK             (0xFFFFU)
#define SCT_MATCHRELL_MATCHRELL_SHIFT            (0U)
#define SCT_MATCHRELL_MATCHRELL(x)               (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELL_MATCHRELL_SHIFT)) & SCT_MATCHRELL_MATCHRELL_MASK)
/*! @} */

/* The count of SCT_MATCHRELL */
#define SCT_MATCHRELL_COUNT                      (16U)

/*! @name MATCHRELH - SCT_MATCHRELH register */
/*! @{ */

#define SCT_MATCHRELH_MATCHRELH_MASK             (0xFFFFU)
#define SCT_MATCHRELH_MATCHRELH_SHIFT            (0U)
#define SCT_MATCHRELH_MATCHRELH(x)               (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELH_MATCHRELH_SHIFT)) & SCT_MATCHRELH_MATCHRELH_MASK)
/*! @} */

/* The count of SCT_MATCHRELH */
#define SCT_MATCHRELH_COUNT                      (16U)

/*! @name MATCHREL - Match Reload Value */
/*! @{ */

#define SCT_MATCHREL_RELOADn_L_MASK              (0xFFFFU)
#define SCT_MATCHREL_RELOADn_L_SHIFT             (0U)
/*! RELOADn_L - Reload n Low
 */
#define SCT_MATCHREL_RELOADn_L(x)                (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_L_SHIFT)) & SCT_MATCHREL_RELOADn_L_MASK)

#define SCT_MATCHREL_RELOADn_H_MASK              (0xFFFF0000U)
#define SCT_MATCHREL_RELOADn_H_SHIFT             (16U)
/*! RELOADn_H - Reload n High
 */
#define SCT_MATCHREL_RELOADn_H(x)                (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_H_SHIFT)) & SCT_MATCHREL_RELOADn_H_MASK)
/*! @} */

/* The count of SCT_MATCHREL */
#define SCT_MATCHREL_COUNT                       (16U)

/*! @name FRACMATREL - Fractional Match Reload */
/*! @{ */

#define SCT_FRACMATREL_FRACMAT_L_MASK            (0xFU)
#define SCT_FRACMATREL_FRACMAT_L_SHIFT           (0U)
/*! FRACMAT_L - Reload Fractional Match Low
 */
#define SCT_FRACMATREL_FRACMAT_L(x)              (((uint32_t)(((uint32_t)(x)) << SCT_FRACMATREL_FRACMAT_L_SHIFT)) & SCT_FRACMATREL_FRACMAT_L_MASK)

#define SCT_FRACMATREL_RELFRAC_H_MASK            (0xF0000U)
#define SCT_FRACMATREL_RELFRAC_H_SHIFT           (16U)
/*! RELFRAC_H - Reload Fractional Match High
 */
#define SCT_FRACMATREL_RELFRAC_H(x)              (((uint32_t)(((uint32_t)(x)) << SCT_FRACMATREL_RELFRAC_H_SHIFT)) & SCT_FRACMATREL_RELFRAC_H_MASK)
/*! @} */

/* The count of SCT_FRACMATREL */
#define SCT_FRACMATREL_COUNT                     (6U)

/*! @name EV_STATE - Event n State */
/*! @{ */

#define SCT_EV_STATE_STATEMSKn_MASK              (0xFFFFFFFFU)
#define SCT_EV_STATE_STATEMSKn_SHIFT             (0U)
/*! STATEMSKn - Event State Mask n
 */
#define SCT_EV_STATE_STATEMSKn(x)                (((uint32_t)(((uint32_t)(x)) << SCT_EV_STATE_STATEMSKn_SHIFT)) & SCT_EV_STATE_STATEMSKn_MASK)
/*! @} */

/* The count of SCT_EV_STATE */
#define SCT_EV_STATE_COUNT                       (16U)

/*! @name EV_CTRL - Event n Control */
/*! @{ */

#define SCT_EV_CTRL_MATCHSEL_MASK                (0xFU)
#define SCT_EV_CTRL_MATCHSEL_SHIFT               (0U)
/*! MATCHSEL - Match Select
 */
#define SCT_EV_CTRL_MATCHSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHSEL_SHIFT)) & SCT_EV_CTRL_MATCHSEL_MASK)

#define SCT_EV_CTRL_HEVENT_MASK                  (0x10U)
#define SCT_EV_CTRL_HEVENT_SHIFT                 (4U)
/*! HEVENT - High Event
 *  0b0..Low Counter
 *  0b1..High Counter
 */
#define SCT_EV_CTRL_HEVENT(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_HEVENT_SHIFT)) & SCT_EV_CTRL_HEVENT_MASK)

#define SCT_EV_CTRL_OUTSEL_MASK                  (0x20U)
#define SCT_EV_CTRL_OUTSEL_SHIFT                 (5U)
/*! OUTSEL - Input/Output Select
 *  0b0..Selects the inputs selected by IOSEL.
 *  0b1..Selects the outputs selected by IOSEL.
 */
#define SCT_EV_CTRL_OUTSEL(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_OUTSEL_SHIFT)) & SCT_EV_CTRL_OUTSEL_MASK)

#define SCT_EV_CTRL_IOSEL_MASK                   (0x3C0U)
#define SCT_EV_CTRL_IOSEL_SHIFT                  (6U)
/*! IOSEL - Input/Output Signal Select
 */
#define SCT_EV_CTRL_IOSEL(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOSEL_SHIFT)) & SCT_EV_CTRL_IOSEL_MASK)

#define SCT_EV_CTRL_IOCOND_MASK                  (0xC00U)
#define SCT_EV_CTRL_IOCOND_SHIFT                 (10U)
/*! IOCOND - Input/Output Condition
 *  0b00..Low
 *  0b01..Rise
 *  0b10..Fall
 *  0b11..High
 */
#define SCT_EV_CTRL_IOCOND(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOCOND_SHIFT)) & SCT_EV_CTRL_IOCOND_MASK)

#define SCT_EV_CTRL_COMBMODE_MASK                (0x3000U)
#define SCT_EV_CTRL_COMBMODE_SHIFT               (12U)
/*! COMBMODE - Combination Mode
 *  0b00..OR. The event occurs when either the specified match or I/O condition occurs.
 *  0b01..MATCH. Uses the specified match only.
 *  0b10..IO. Uses the specified I/O condition only.
 *  0b11..AND. The event occurs when the specified match and I/O condition occur simultaneously.
 */
#define SCT_EV_CTRL_COMBMODE(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_COMBMODE_SHIFT)) & SCT_EV_CTRL_COMBMODE_MASK)

#define SCT_EV_CTRL_STATELD_MASK                 (0x4000U)
#define SCT_EV_CTRL_STATELD_SHIFT                (14U)
/*! STATELD - State Load
 *  0b0..Add. STATEV value is added into STATE (the carry-out is ignored).
 *  0b1..Load. STATEV value is loaded into STATE.
 */
#define SCT_EV_CTRL_STATELD(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATELD_SHIFT)) & SCT_EV_CTRL_STATELD_MASK)

#define SCT_EV_CTRL_STATEV_MASK                  (0xF8000U)
#define SCT_EV_CTRL_STATEV_SHIFT                 (15U)
/*! STATEV - State Value
 */
#define SCT_EV_CTRL_STATEV(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATEV_SHIFT)) & SCT_EV_CTRL_STATEV_MASK)

#define SCT_EV_CTRL_MATCHMEM_MASK                (0x100000U)
#define SCT_EV_CTRL_MATCHMEM_SHIFT               (20U)
/*! MATCHMEM - Match Mem
 */
#define SCT_EV_CTRL_MATCHMEM(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHMEM_SHIFT)) & SCT_EV_CTRL_MATCHMEM_MASK)

#define SCT_EV_CTRL_DIRECTION_MASK               (0x600000U)
#define SCT_EV_CTRL_DIRECTION_SHIFT              (21U)
/*! DIRECTION - Direction
 *  0b00..Direction independent. This event is triggered regardless of the count direction.
 *  0b01..Counting up. This event is triggered only during up-counting when BIDIR = 1.
 *  0b10..Counting down. This event is triggered only during down-counting when BIDIR = 1.
 *  0b11..Reserved
 */
#define SCT_EV_CTRL_DIRECTION(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_DIRECTION_SHIFT)) & SCT_EV_CTRL_DIRECTION_MASK)
/*! @} */

/* The count of SCT_EV_CTRL */
#define SCT_EV_CTRL_COUNT                        (16U)

/*! @name OUT_SET - Output n Set */
/*! @{ */

#define SCT_OUT_SET_SET_MASK                     (0xFFFFU)
#define SCT_OUT_SET_SET_SHIFT                    (0U)
/*! SET - Set
 */
#define SCT_OUT_SET_SET(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK)
/*! @} */

/* The count of SCT_OUT_SET */
#define SCT_OUT_SET_COUNT                        (10U)

/*! @name OUT_CLR - Output n Clear */
/*! @{ */

#define SCT_OUT_CLR_CLR_MASK                     (0xFFFFU)
#define SCT_OUT_CLR_CLR_SHIFT                    (0U)
/*! CLR - Clear
 */
#define SCT_OUT_CLR_CLR(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK)
/*! @} */

/* The count of SCT_OUT_CLR */
#define SCT_OUT_CLR_COUNT                        (10U)


/*!
 * @}
 */ /* end of group SCT_Register_Masks */


/* SCT - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral SCT0 base address */
  #define SCT0_BASE                                (0x50085000u)
  /** Peripheral SCT0 base address */
  #define SCT0_BASE_NS                             (0x40085000u)
  /** Peripheral SCT0 base pointer */
  #define SCT0                                     ((SCT_Type *)SCT0_BASE)
  /** Peripheral SCT0 base pointer */
  #define SCT0_NS                                  ((SCT_Type *)SCT0_BASE_NS)
  /** Array initializer of SCT peripheral base addresses */
  #define SCT_BASE_ADDRS                           { SCT0_BASE }
  /** Array initializer of SCT peripheral base pointers */
  #define SCT_BASE_PTRS                            { SCT0 }
  /** Array initializer of SCT peripheral base addresses */
  #define SCT_BASE_ADDRS_NS                        { SCT0_BASE_NS }
  /** Array initializer of SCT peripheral base pointers */
  #define SCT_BASE_PTRS_NS                         { SCT0_NS }
#else
  /** Peripheral SCT0 base address */
  #define SCT0_BASE                                (0x40085000u)
  /** Peripheral SCT0 base pointer */
  #define SCT0                                     ((SCT_Type *)SCT0_BASE)
  /** Array initializer of SCT peripheral base addresses */
  #define SCT_BASE_ADDRS                           { SCT0_BASE }
  /** Array initializer of SCT peripheral base pointers */
  #define SCT_BASE_PTRS                            { SCT0 }
#endif
/** Interrupt vectors for the SCT peripheral type */
#define SCT_IRQS                                 { SCT0_IRQn }

/*!
 * @}
 */ /* end of group SCT_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- SECTRL Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SECTRL_Peripheral_Access_Layer SECTRL Peripheral Access Layer
 * @{
 */

/** SECTRL - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[16];
  __IO uint32_t FLASH_MEM_RULE;                    /**< Flash Memory Rule, offset: 0x10 */
       uint8_t RESERVED_1[12];
  __IO uint32_t ROM_MEM_RULE[4];                   /**< ROM Memory Rule, array offset: 0x20, array step: 0x4 */
       uint8_t RESERVED_2[16];
  __IO uint32_t RAMX_MEM_RULE0;                    /**< RAMX Memory Rule 0, offset: 0x40 */
       uint8_t RESERVED_3[28];
  __IO uint32_t FLEXSPI0_REGION0_MEM_RULE[4];      /**< FLEXSPI0 Region 0 Memory Rule, array offset: 0x60, array step: 0x4 */
  struct {                                         /* offset: 0x70, array step: 0x10 */
    __IO uint32_t FLEXSPI0_REGION_MEM_RULE0;         /**< FLEXSPI0 Region 1 Memory Rule 0..FLEXSPI0 Region 4 Memory Rule 0, array offset: 0x70, array step: 0x10 */
         uint8_t RESERVED_0[12];
  } FLEXSPI0_REGION1_4_MEM_RULE[4];
       uint8_t RESERVED_4[16];
  __IO uint32_t RAM00_MEM_RULE0;                   /**< SRAM0 Partition 0 Memory Rule, offset: 0xC0 */
       uint8_t RESERVED_5[28];
  __IO uint32_t RAM10_MEM_RULE0;                   /**< SRAM1 Partition 0 Memory Rule, offset: 0xE0 */
       uint8_t RESERVED_6[28];
  __IO uint32_t RAM20_MEM_RULE0;                   /**< SRAM2 Partition 0 Memory Rule, offset: 0x100 */
       uint8_t RESERVED_7[28];
  __IO uint32_t RAM30_MEM_RULE0;                   /**< SRAM Partition 0 Memory Rule, offset: 0x120 */
       uint8_t RESERVED_8[28];
  __IO uint32_t RAM40_MEM_RULE0;                   /**< SRAM4 Partition 0 Memory Rule, offset: 0x140 */
       uint8_t RESERVED_9[28];
  __IO uint32_t APB_PERIPHERAL_GROUP0_MEM_RULE0;   /**< APB Bridge Group 0 Memory Rule 0, offset: 0x160 */
  __IO uint32_t APB_PERIPHERAL_GROUP0_MEM_RULE1;   /**< APB Bridge Group 0 Memory Rule 1, offset: 0x164 */
  __IO uint32_t APB_PERIPHERAL_GROUP0_MEM_RULE2;   /**< APB Bridge Group 0 Rule 2, offset: 0x168 */
  __IO uint32_t APB_PERIPHERAL_GROUP0_MEM_RULE3;   /**< APB Bridge Group 0 Memory Rule 3, offset: 0x16C */
  __IO uint32_t APB_PERIPHERAL_GROUP1_MEM_RULE0;   /**< APB Bridge Group 1 Memory Rule 0, offset: 0x170 */
  __IO uint32_t APB_PERIPHERAL_GROUP1_MEM_RULE1;   /**< APB Bridge Group 1 Memory Rule 1, offset: 0x174 */
  __IO uint32_t APB_PERIPHERAL_GROUP1_MEM_RULE2;   /**< APB Bridge Group 1 Memory Rule 2, offset: 0x178 */
  __IO uint32_t APB_PERIPHERAL_GROUP1_MEM_RULE3;   /**< APB Bridge Group 1 Memory Rule 3, offset: 0x17C */
       uint8_t RESERVED_10[16];
  __IO uint32_t AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0; /**< AHB Peripheral 0 Slave Port9 Rule 0, offset: 0x190 */
  __IO uint32_t AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE1; /**< AHB Peripheral 0 Slave Port 9 Rule 1, offset: 0x194 */
       uint8_t RESERVED_11[8];
  __IO uint32_t AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0; /**< AHB Peripheral 1 Slave Port 10 Slave Rule 0, offset: 0x1A0 */
       uint8_t RESERVED_12[12];
  __IO uint32_t AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0; /**< AHB Peripheral 2 Slave Port 11 Slave Rule 0, offset: 0x1B0 */
       uint8_t RESERVED_13[12];
  __IO uint32_t AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0; /**< AHB Secure Control Peripheral Memory Rule 0, offset: 0x1C0 */
       uint8_t RESERVED_14[28];
  __IO uint32_t AIPS_BRIDGE_GROUP0_RULE0;          /**< AIPS Bridge Group 0 Rule 0, offset: 0x1E0 */
  __IO uint32_t AIPS_BRIDGE_GROUP0_RULE1;          /**< AIPS Bridge Group 0 Rule 1, offset: 0x1E4 */
       uint8_t RESERVED_15[24];
  __IO uint32_t AIPS_BRIDGE_GROUP1_RULE0;          /**< AIPS Bridge Group 1 Rule 0, offset: 0x200 */
  __IO uint32_t AIPS_BRIDGE_GROUP1_RULE1;          /**< AIPS Bridge Group 1 Rule 1, offset: 0x204 */
       uint8_t RESERVED_16[3064];
  __I  uint32_t SEC_VIO_ADDR[32];                  /**< Security Violation Address, array offset: 0xE00, array step: 0x4 */
  __I  uint32_t SEC_VIO_MISC_INFO[32];             /**< Security Violation Miscellaneous Information at Address, array offset: 0xE80, array step: 0x4 */
  __IO uint32_t SEC_VIO_INFO_VALID;                /**< Security Violation Info Validity for Address, offset: 0xF00 */
       uint8_t RESERVED_17[124];
  __IO uint32_t SEC_GPIO_MASK[3];                  /**< GPIO Mask for Port 0..GPIO Mask for Port 2, array offset: 0xF80, array step: 0x4 */
  __IO uint32_t SEC_GPIO_MASK3;                    /**< GPIO Mask for Port 3, offset: 0xF8C */
       uint8_t RESERVED_18[44];
  __IO uint32_t SEC_GP_REG_LOCK;                   /**< Secure Mask Lock, offset: 0xFBC */
       uint8_t RESERVED_19[16];
  __IO uint32_t MASTER_SEC_LEVEL;                  /**< Master Secure Level, offset: 0xFD0 */
  __IO uint32_t MASTER_SEC_ANTI_POL_REG;           /**< Master Secure Level, offset: 0xFD4 */
       uint8_t RESERVED_20[20];
  __IO uint32_t CM33_LOCK_REG[3];                  /**< Miscellaneous CPU0 Control Signals, array offset: 0xFEC, array step: 0x4 */
  __IO uint32_t MISC_CTRL_DP_REG;                  /**< Secure Control Duplicate, offset: 0xFF8 */
  __IO uint32_t MISC_CTRL_REG;                     /**< Secure Control, offset: 0xFFC */
} SECTRL_Type;

/* ----------------------------------------------------------------------------
   -- SECTRL Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SECTRL_Register_Masks SECTRL Register Masks
 * @{
 */

/*! @name FLASH_MEM_RULE - Flash Memory Rule */
/*! @{ */

#define SECTRL_FLASH_MEM_RULE_RULE0_MASK         (0x3U)
#define SECTRL_FLASH_MEM_RULE_RULE0_SHIFT        (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_FLASH_MEM_RULE_RULE0(x)           (((uint32_t)(((uint32_t)(x)) << SECTRL_FLASH_MEM_RULE_RULE0_SHIFT)) & SECTRL_FLASH_MEM_RULE_RULE0_MASK)

#define SECTRL_FLASH_MEM_RULE_RULE1_MASK         (0x30U)
#define SECTRL_FLASH_MEM_RULE_RULE1_SHIFT        (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_FLASH_MEM_RULE_RULE1(x)           (((uint32_t)(((uint32_t)(x)) << SECTRL_FLASH_MEM_RULE_RULE1_SHIFT)) & SECTRL_FLASH_MEM_RULE_RULE1_MASK)

#define SECTRL_FLASH_MEM_RULE_RULE2_MASK         (0x300U)
#define SECTRL_FLASH_MEM_RULE_RULE2_SHIFT        (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_FLASH_MEM_RULE_RULE2(x)           (((uint32_t)(((uint32_t)(x)) << SECTRL_FLASH_MEM_RULE_RULE2_SHIFT)) & SECTRL_FLASH_MEM_RULE_RULE2_MASK)

#define SECTRL_FLASH_MEM_RULE_RULE3_MASK         (0x3000U)
#define SECTRL_FLASH_MEM_RULE_RULE3_SHIFT        (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_FLASH_MEM_RULE_RULE3(x)           (((uint32_t)(((uint32_t)(x)) << SECTRL_FLASH_MEM_RULE_RULE3_SHIFT)) & SECTRL_FLASH_MEM_RULE_RULE3_MASK)

#define SECTRL_FLASH_MEM_RULE_RULE4_MASK         (0x30000U)
#define SECTRL_FLASH_MEM_RULE_RULE4_SHIFT        (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_FLASH_MEM_RULE_RULE4(x)           (((uint32_t)(((uint32_t)(x)) << SECTRL_FLASH_MEM_RULE_RULE4_SHIFT)) & SECTRL_FLASH_MEM_RULE_RULE4_MASK)

#define SECTRL_FLASH_MEM_RULE_RULE5_MASK         (0x300000U)
#define SECTRL_FLASH_MEM_RULE_RULE5_SHIFT        (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_FLASH_MEM_RULE_RULE5(x)           (((uint32_t)(((uint32_t)(x)) << SECTRL_FLASH_MEM_RULE_RULE5_SHIFT)) & SECTRL_FLASH_MEM_RULE_RULE5_MASK)

#define SECTRL_FLASH_MEM_RULE_RULE6_MASK         (0x3000000U)
#define SECTRL_FLASH_MEM_RULE_RULE6_SHIFT        (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_FLASH_MEM_RULE_RULE6(x)           (((uint32_t)(((uint32_t)(x)) << SECTRL_FLASH_MEM_RULE_RULE6_SHIFT)) & SECTRL_FLASH_MEM_RULE_RULE6_MASK)

#define SECTRL_FLASH_MEM_RULE_RULE7_MASK         (0x30000000U)
#define SECTRL_FLASH_MEM_RULE_RULE7_SHIFT        (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_FLASH_MEM_RULE_RULE7(x)           (((uint32_t)(((uint32_t)(x)) << SECTRL_FLASH_MEM_RULE_RULE7_SHIFT)) & SECTRL_FLASH_MEM_RULE_RULE7_MASK)
/*! @} */

/*! @name ROM_MEM_RULE - ROM Memory Rule */
/*! @{ */

#define SECTRL_ROM_MEM_RULE_RULE0_MASK           (0x3U)
#define SECTRL_ROM_MEM_RULE_RULE0_SHIFT          (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_ROM_MEM_RULE_RULE0(x)             (((uint32_t)(((uint32_t)(x)) << SECTRL_ROM_MEM_RULE_RULE0_SHIFT)) & SECTRL_ROM_MEM_RULE_RULE0_MASK)

#define SECTRL_ROM_MEM_RULE_RULE1_MASK           (0x30U)
#define SECTRL_ROM_MEM_RULE_RULE1_SHIFT          (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_ROM_MEM_RULE_RULE1(x)             (((uint32_t)(((uint32_t)(x)) << SECTRL_ROM_MEM_RULE_RULE1_SHIFT)) & SECTRL_ROM_MEM_RULE_RULE1_MASK)

#define SECTRL_ROM_MEM_RULE_RULE2_MASK           (0x300U)
#define SECTRL_ROM_MEM_RULE_RULE2_SHIFT          (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_ROM_MEM_RULE_RULE2(x)             (((uint32_t)(((uint32_t)(x)) << SECTRL_ROM_MEM_RULE_RULE2_SHIFT)) & SECTRL_ROM_MEM_RULE_RULE2_MASK)

#define SECTRL_ROM_MEM_RULE_RULE3_MASK           (0x3000U)
#define SECTRL_ROM_MEM_RULE_RULE3_SHIFT          (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_ROM_MEM_RULE_RULE3(x)             (((uint32_t)(((uint32_t)(x)) << SECTRL_ROM_MEM_RULE_RULE3_SHIFT)) & SECTRL_ROM_MEM_RULE_RULE3_MASK)

#define SECTRL_ROM_MEM_RULE_RULE4_MASK           (0x30000U)
#define SECTRL_ROM_MEM_RULE_RULE4_SHIFT          (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_ROM_MEM_RULE_RULE4(x)             (((uint32_t)(((uint32_t)(x)) << SECTRL_ROM_MEM_RULE_RULE4_SHIFT)) & SECTRL_ROM_MEM_RULE_RULE4_MASK)

#define SECTRL_ROM_MEM_RULE_RULE5_MASK           (0x300000U)
#define SECTRL_ROM_MEM_RULE_RULE5_SHIFT          (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_ROM_MEM_RULE_RULE5(x)             (((uint32_t)(((uint32_t)(x)) << SECTRL_ROM_MEM_RULE_RULE5_SHIFT)) & SECTRL_ROM_MEM_RULE_RULE5_MASK)

#define SECTRL_ROM_MEM_RULE_RULE6_MASK           (0x3000000U)
#define SECTRL_ROM_MEM_RULE_RULE6_SHIFT          (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_ROM_MEM_RULE_RULE6(x)             (((uint32_t)(((uint32_t)(x)) << SECTRL_ROM_MEM_RULE_RULE6_SHIFT)) & SECTRL_ROM_MEM_RULE_RULE6_MASK)

#define SECTRL_ROM_MEM_RULE_RULE7_MASK           (0x30000000U)
#define SECTRL_ROM_MEM_RULE_RULE7_SHIFT          (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_ROM_MEM_RULE_RULE7(x)             (((uint32_t)(((uint32_t)(x)) << SECTRL_ROM_MEM_RULE_RULE7_SHIFT)) & SECTRL_ROM_MEM_RULE_RULE7_MASK)
/*! @} */

/* The count of SECTRL_ROM_MEM_RULE */
#define SECTRL_ROM_MEM_RULE_COUNT                (4U)

/*! @name RAMX_MEM_RULE0 - RAMX Memory Rule 0 */
/*! @{ */

#define SECTRL_RAMX_MEM_RULE0_RULE0_MASK         (0x3U)
#define SECTRL_RAMX_MEM_RULE0_RULE0_SHIFT        (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_RAMX_MEM_RULE0_RULE0(x)           (((uint32_t)(((uint32_t)(x)) << SECTRL_RAMX_MEM_RULE0_RULE0_SHIFT)) & SECTRL_RAMX_MEM_RULE0_RULE0_MASK)

#define SECTRL_RAMX_MEM_RULE0_RULE1_MASK         (0x30U)
#define SECTRL_RAMX_MEM_RULE0_RULE1_SHIFT        (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_RAMX_MEM_RULE0_RULE1(x)           (((uint32_t)(((uint32_t)(x)) << SECTRL_RAMX_MEM_RULE0_RULE1_SHIFT)) & SECTRL_RAMX_MEM_RULE0_RULE1_MASK)

#define SECTRL_RAMX_MEM_RULE0_RULE2_MASK         (0x300U)
#define SECTRL_RAMX_MEM_RULE0_RULE2_SHIFT        (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_RAMX_MEM_RULE0_RULE2(x)           (((uint32_t)(((uint32_t)(x)) << SECTRL_RAMX_MEM_RULE0_RULE2_SHIFT)) & SECTRL_RAMX_MEM_RULE0_RULE2_MASK)

#define SECTRL_RAMX_MEM_RULE0_RULE3_MASK         (0x3000U)
#define SECTRL_RAMX_MEM_RULE0_RULE3_SHIFT        (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_RAMX_MEM_RULE0_RULE3(x)           (((uint32_t)(((uint32_t)(x)) << SECTRL_RAMX_MEM_RULE0_RULE3_SHIFT)) & SECTRL_RAMX_MEM_RULE0_RULE3_MASK)
/*! @} */

/*! @name FLEXSPI0_REGION0_MEM_RULE - FLEXSPI0 Region 0 Memory Rule */
/*! @{ */

#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE0_MASK (0x3U)
#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE0_SHIFT (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE0_SHIFT)) & SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE0_MASK)

#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE1_MASK (0x30U)
#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE1_SHIFT (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE1_SHIFT)) & SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE1_MASK)

#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE2_MASK (0x300U)
#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE2_SHIFT (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE2_SHIFT)) & SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE2_MASK)

#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE3_MASK (0x3000U)
#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE3_SHIFT (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE3_SHIFT)) & SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE3_MASK)

#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE4_MASK (0x30000U)
#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE4_SHIFT (16U)
/*! RULE4 - Rule 4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE4_SHIFT)) & SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE4_MASK)

#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE5_MASK (0x300000U)
#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE5_SHIFT (20U)
/*! RULE5 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE5_SHIFT)) & SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE5_MASK)

#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE6_MASK (0x3000000U)
#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE6_SHIFT (24U)
/*! RULE6 - Rule 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE6_SHIFT)) & SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE6_MASK)

#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE7_MASK (0x30000000U)
#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE7_SHIFT (28U)
/*! RULE7 - Rule 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE7_SHIFT)) & SECTRL_FLEXSPI0_REGION0_MEM_RULE_RULE7_MASK)
/*! @} */

/* The count of SECTRL_FLEXSPI0_REGION0_MEM_RULE */
#define SECTRL_FLEXSPI0_REGION0_MEM_RULE_COUNT   (4U)

/*! @name FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0 - FLEXSPI0 Region 1 Memory Rule 0..FLEXSPI0 Region 4 Memory Rule 0 */
/*! @{ */

#define SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE0_MASK (0x3U)
#define SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE0_SHIFT (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE0_SHIFT)) & SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE0_MASK)

#define SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE1_MASK (0x30U)
#define SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE1_SHIFT (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE1_SHIFT)) & SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE1_MASK)

#define SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE2_MASK (0x300U)
#define SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE2_SHIFT (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE2(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE2_SHIFT)) & SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE2_MASK)

#define SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE3_MASK (0x3000U)
#define SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE3_SHIFT (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE3(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE3_SHIFT)) & SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_RULE3_MASK)
/*! @} */

/* The count of SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0 */
#define SECTRL_FLEXSPI0_REGION1_4_MEM_RULE_FLEXSPI0_REGION_MEM_RULE0_COUNT (4U)

/*! @name RAM00_MEM_RULE0 - SRAM0 Partition 0 Memory Rule */
/*! @{ */

#define SECTRL_RAM00_MEM_RULE0_RULE0_MASK        (0x3U)
#define SECTRL_RAM00_MEM_RULE0_RULE0_SHIFT       (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_RAM00_MEM_RULE0_RULE0(x)          (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM00_MEM_RULE0_RULE0_SHIFT)) & SECTRL_RAM00_MEM_RULE0_RULE0_MASK)

#define SECTRL_RAM00_MEM_RULE0_RULE1_MASK        (0x30U)
#define SECTRL_RAM00_MEM_RULE0_RULE1_SHIFT       (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_RAM00_MEM_RULE0_RULE1(x)          (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM00_MEM_RULE0_RULE1_SHIFT)) & SECTRL_RAM00_MEM_RULE0_RULE1_MASK)

#define SECTRL_RAM00_MEM_RULE0_RULE2_MASK        (0x300U)
#define SECTRL_RAM00_MEM_RULE0_RULE2_SHIFT       (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_RAM00_MEM_RULE0_RULE2(x)          (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM00_MEM_RULE0_RULE2_SHIFT)) & SECTRL_RAM00_MEM_RULE0_RULE2_MASK)

#define SECTRL_RAM00_MEM_RULE0_RULE3_MASK        (0x3000U)
#define SECTRL_RAM00_MEM_RULE0_RULE3_SHIFT       (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_RAM00_MEM_RULE0_RULE3(x)          (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM00_MEM_RULE0_RULE3_SHIFT)) & SECTRL_RAM00_MEM_RULE0_RULE3_MASK)
/*! @} */

/*! @name RAM10_MEM_RULE0 - SRAM1 Partition 0 Memory Rule */
/*! @{ */

#define SECTRL_RAM10_MEM_RULE0_RULE0_MASK        (0x3U)
#define SECTRL_RAM10_MEM_RULE0_RULE0_SHIFT       (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_RAM10_MEM_RULE0_RULE0(x)          (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM10_MEM_RULE0_RULE0_SHIFT)) & SECTRL_RAM10_MEM_RULE0_RULE0_MASK)

#define SECTRL_RAM10_MEM_RULE0_RULE1_MASK        (0x30U)
#define SECTRL_RAM10_MEM_RULE0_RULE1_SHIFT       (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_RAM10_MEM_RULE0_RULE1(x)          (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM10_MEM_RULE0_RULE1_SHIFT)) & SECTRL_RAM10_MEM_RULE0_RULE1_MASK)

#define SECTRL_RAM10_MEM_RULE0_RULE2_MASK        (0x300U)
#define SECTRL_RAM10_MEM_RULE0_RULE2_SHIFT       (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_RAM10_MEM_RULE0_RULE2(x)          (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM10_MEM_RULE0_RULE2_SHIFT)) & SECTRL_RAM10_MEM_RULE0_RULE2_MASK)

#define SECTRL_RAM10_MEM_RULE0_RULE3_MASK        (0x3000U)
#define SECTRL_RAM10_MEM_RULE0_RULE3_SHIFT       (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_RAM10_MEM_RULE0_RULE3(x)          (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM10_MEM_RULE0_RULE3_SHIFT)) & SECTRL_RAM10_MEM_RULE0_RULE3_MASK)
/*! @} */

/*! @name RAM20_MEM_RULE0 - SRAM2 Partition 0 Memory Rule */
/*! @{ */

#define SECTRL_RAM20_MEM_RULE0_RULE0_MASK        (0x3U)
#define SECTRL_RAM20_MEM_RULE0_RULE0_SHIFT       (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_RAM20_MEM_RULE0_RULE0(x)          (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM20_MEM_RULE0_RULE0_SHIFT)) & SECTRL_RAM20_MEM_RULE0_RULE0_MASK)

#define SECTRL_RAM20_MEM_RULE0_RULE1_MASK        (0x30U)
#define SECTRL_RAM20_MEM_RULE0_RULE1_SHIFT       (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_RAM20_MEM_RULE0_RULE1(x)          (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM20_MEM_RULE0_RULE1_SHIFT)) & SECTRL_RAM20_MEM_RULE0_RULE1_MASK)

#define SECTRL_RAM20_MEM_RULE0_RULE2_MASK        (0x300U)
#define SECTRL_RAM20_MEM_RULE0_RULE2_SHIFT       (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_RAM20_MEM_RULE0_RULE2(x)          (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM20_MEM_RULE0_RULE2_SHIFT)) & SECTRL_RAM20_MEM_RULE0_RULE2_MASK)

#define SECTRL_RAM20_MEM_RULE0_RULE3_MASK        (0x3000U)
#define SECTRL_RAM20_MEM_RULE0_RULE3_SHIFT       (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_RAM20_MEM_RULE0_RULE3(x)          (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM20_MEM_RULE0_RULE3_SHIFT)) & SECTRL_RAM20_MEM_RULE0_RULE3_MASK)
/*! @} */

/*! @name RAM30_MEM_RULE0 - SRAM Partition 0 Memory Rule */
/*! @{ */

#define SECTRL_RAM30_MEM_RULE0_RULE0_MASK        (0x3U)
#define SECTRL_RAM30_MEM_RULE0_RULE0_SHIFT       (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_RAM30_MEM_RULE0_RULE0(x)          (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM30_MEM_RULE0_RULE0_SHIFT)) & SECTRL_RAM30_MEM_RULE0_RULE0_MASK)

#define SECTRL_RAM30_MEM_RULE0_RULE1_MASK        (0x30U)
#define SECTRL_RAM30_MEM_RULE0_RULE1_SHIFT       (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_RAM30_MEM_RULE0_RULE1(x)          (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM30_MEM_RULE0_RULE1_SHIFT)) & SECTRL_RAM30_MEM_RULE0_RULE1_MASK)

#define SECTRL_RAM30_MEM_RULE0_RULE2_MASK        (0x300U)
#define SECTRL_RAM30_MEM_RULE0_RULE2_SHIFT       (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_RAM30_MEM_RULE0_RULE2(x)          (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM30_MEM_RULE0_RULE2_SHIFT)) & SECTRL_RAM30_MEM_RULE0_RULE2_MASK)

#define SECTRL_RAM30_MEM_RULE0_RULE3_MASK        (0x3000U)
#define SECTRL_RAM30_MEM_RULE0_RULE3_SHIFT       (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_RAM30_MEM_RULE0_RULE3(x)          (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM30_MEM_RULE0_RULE3_SHIFT)) & SECTRL_RAM30_MEM_RULE0_RULE3_MASK)
/*! @} */

/*! @name RAM40_MEM_RULE0 - SRAM4 Partition 0 Memory Rule */
/*! @{ */

#define SECTRL_RAM40_MEM_RULE0_RULE0_MASK        (0x3U)
#define SECTRL_RAM40_MEM_RULE0_RULE0_SHIFT       (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_RAM40_MEM_RULE0_RULE0(x)          (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM40_MEM_RULE0_RULE0_SHIFT)) & SECTRL_RAM40_MEM_RULE0_RULE0_MASK)

#define SECTRL_RAM40_MEM_RULE0_RULE1_MASK        (0x30U)
#define SECTRL_RAM40_MEM_RULE0_RULE1_SHIFT       (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_RAM40_MEM_RULE0_RULE1(x)          (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM40_MEM_RULE0_RULE1_SHIFT)) & SECTRL_RAM40_MEM_RULE0_RULE1_MASK)

#define SECTRL_RAM40_MEM_RULE0_RULE2_MASK        (0x300U)
#define SECTRL_RAM40_MEM_RULE0_RULE2_SHIFT       (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_RAM40_MEM_RULE0_RULE2(x)          (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM40_MEM_RULE0_RULE2_SHIFT)) & SECTRL_RAM40_MEM_RULE0_RULE2_MASK)

#define SECTRL_RAM40_MEM_RULE0_RULE3_MASK        (0x3000U)
#define SECTRL_RAM40_MEM_RULE0_RULE3_SHIFT       (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_RAM40_MEM_RULE0_RULE3(x)          (((uint32_t)(((uint32_t)(x)) << SECTRL_RAM40_MEM_RULE0_RULE3_SHIFT)) & SECTRL_RAM40_MEM_RULE0_RULE3_MASK)
/*! @} */

/*! @name APB_PERIPHERAL_GROUP0_MEM_RULE0 - APB Bridge Group 0 Memory Rule 0 */
/*! @{ */

#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_SYSCON_MASK (0x3U)
#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_SYSCON_SHIFT (0U)
/*! SYSCON - SYSCON
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_SYSCON(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_SYSCON_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_SYSCON_MASK)

#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_IOCON_MASK (0x30U)
#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_IOCON_SHIFT (4U)
/*! IOCON - IOCON
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_IOCON(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_IOCON_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_IOCON_MASK)

#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_GPIO0_MASK (0x300U)
#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_GPIO0_SHIFT (8U)
/*! GPIO0 - GPIO0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_GPIO0_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_GPIO0_MASK)

#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_GPIO1_MASK (0x3000U)
#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_GPIO1_SHIFT (12U)
/*! GPIO1 - GPIO1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_GPIO1_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_GPIO1_MASK)

#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT0_MASK (0x30000U)
#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT0_SHIFT (16U)
/*! PINT0 - PINT0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT0_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT0_MASK)

#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT1_MASK (0x300000U)
#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT1_SHIFT (20U)
/*! PINT1 - Rule 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT1_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT1_MASK)

#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_GINT1_MASK (0x3000000U)
#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_GINT1_SHIFT (24U)
/*! GINT1 - GINT1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_GINT1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_GINT1_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE0_GINT1_MASK)
/*! @} */

/*! @name APB_PERIPHERAL_GROUP0_MEM_RULE1 - APB Bridge Group 0 Memory Rule 1 */
/*! @{ */

#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER0_MASK (0x3U)
#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER0_SHIFT (0U)
/*! CTIMER0 - CTIMER0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER0_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER0_MASK)

#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER1_MASK (0x30U)
#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER1_SHIFT (4U)
/*! CTIMER1 - CTIMER 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER1_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER1_MASK)

#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_WWDT0_MASK (0x30000U)
#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_WWDT0_SHIFT (16U)
/*! WWDT0 - WWDT0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_WWDT0_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_WWDT0_MASK)

#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_MRT_MASK (0x300000U)
#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_MRT_SHIFT (20U)
/*! MRT - MRT0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_MRT(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_MRT_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_MRT_MASK)

#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_MICRO_TICK_MASK (0x3000000U)
#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_MICRO_TICK_SHIFT (24U)
/*! MICRO_TICK - MICRO_TICK
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_MICRO_TICK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_MICRO_TICK_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_MICRO_TICK_MASK)

#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_ITRC_MASK (0x30000000U)
#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_ITRC_SHIFT (28U)
/*! ITRC - ITRC
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_ITRC(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_ITRC_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE1_ITRC_MASK)
/*! @} */

/*! @name APB_PERIPHERAL_GROUP0_MEM_RULE2 - APB Bridge Group 0 Rule 2 */
/*! @{ */

#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE2_ANALOG_CTRL_MASK (0x3000U)
#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE2_ANALOG_CTRL_SHIFT (12U)
/*! ANALOG_CTRL - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE2_ANALOG_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE2_ANALOG_CTRL_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE2_ANALOG_CTRL_MASK)

#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE2_eFUSE_MASK (0x300000U)
#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE2_eFUSE_SHIFT (20U)
/*! eFUSE - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE2_eFUSE(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE2_eFUSE_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE2_eFUSE_MASK)

#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE2_I3C0_MASK (0x3000000U)
#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE2_I3C0_SHIFT (24U)
/*! I3C0 - I3C0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE2_I3C0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE2_I3C0_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE2_I3C0_MASK)
/*! @} */

/*! @name APB_PERIPHERAL_GROUP0_MEM_RULE3 - APB Bridge Group 0 Memory Rule 3 */
/*! @{ */

#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE3_EZH_MASK (0x300000U)
#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE3_EZH_SHIFT (20U)
/*! EZH - EZH
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE3_EZH(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE3_EZH_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP0_MEM_RULE3_EZH_MASK)
/*! @} */

/*! @name APB_PERIPHERAL_GROUP1_MEM_RULE0 - APB Bridge Group 1 Memory Rule 0 */
/*! @{ */

#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE0_PMC_MASK (0x3U)
#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE0_PMC_SHIFT (0U)
/*! PMC - PMC
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE0_PMC(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE0_PMC_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE0_PMC_MASK)

#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE0_SYSCTL_I2S_MASK (0x3000U)
#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE0_SYSCTL_I2S_SHIFT (12U)
/*! SYSCTL_I2S - SYSCTL(I2S Pin Sharing)
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE0_SYSCTL_I2S(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE0_SYSCTL_I2S_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE0_SYSCTL_I2S_MASK)

#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE0_SPI_MSFT_MASK (0x30000U)
#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE0_SPI_MSFT_SHIFT (16U)
/*! SPI_MSFT - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE0_SPI_MSFT(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE0_SPI_MSFT_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE0_SPI_MSFT_MASK)
/*! @} */

/*! @name APB_PERIPHERAL_GROUP1_MEM_RULE1 - APB Bridge Group 1 Memory Rule 1 */
/*! @{ */

#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CTIMER2_MASK (0x3U)
#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CTIMER2_SHIFT (0U)
/*! CTIMER2 - CTIMER2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CTIMER2_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CTIMER2_MASK)

#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CTIMER3_MASK (0x30U)
#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CTIMER3_SHIFT (4U)
/*! CTIMER3 - CTIMER3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CTIMER3_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CTIMER3_MASK)

#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CTIMER4_MASK (0x300U)
#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CTIMER4_SHIFT (8U)
/*! CTIMER4 - CTIMER4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CTIMER4_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CTIMER4_MASK)

#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_RTC_MASK (0x30000U)
#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_RTC_SHIFT (16U)
/*! RTC - RTC
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_RTC(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_RTC_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_RTC_MASK)

#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_OS_EVENT_TIMER_MASK (0x300000U)
#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_OS_EVENT_TIMER_SHIFT (20U)
/*! OS_EVENT_TIMER - OS_EVENT_TIMER
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_OS_EVENT_TIMER(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_OS_EVENT_TIMER_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_OS_EVENT_TIMER_MASK)

#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CACHE64_POLSEL_MASK (0x3000000U)
#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CACHE64_POLSEL_SHIFT (24U)
/*! CACHE64_POLSEL - CACHE64_POLSEL
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CACHE64_POLSEL(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CACHE64_POLSEL_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_CACHE64_POLSEL_MASK)

#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_PKC_MASK (0x30000000U)
#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_PKC_SHIFT (28U)
/*! PKC - PKC
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_PKC(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_PKC_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE1_PKC_MASK)
/*! @} */

/*! @name APB_PERIPHERAL_GROUP1_MEM_RULE2 - APB Bridge Group 1 Memory Rule 2 */
/*! @{ */

#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS0_MASK (0x3U)
#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS0_SHIFT (0U)
/*! CSSV2MINI_ALIAS0 - CSSV2MINI ALIAS0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS0_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS0_MASK)

#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS1_MASK (0x30U)
#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS1_SHIFT (4U)
/*! CSSV2MINI_ALIAS1 - CSSV2MINI ALIAS1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS1_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS1_MASK)

#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS2_MASK (0x300U)
#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS2_SHIFT (8U)
/*! CSSV2MINI_ALIAS2 - CSSV2MINI ALIAS2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS2(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS2_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS2_MASK)

#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS3_MASK (0x3000U)
#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS3_SHIFT (12U)
/*! CSSV2MINI_ALIAS3 - CSSV2MINI ALIAS3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS3(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS3_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_CSSV2MINI_ALIAS3_MASK)

#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_FLASH_CONTROLLER_MASK (0x30000U)
#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_FLASH_CONTROLLER_SHIFT (16U)
/*! FLASH_CONTROLLER - Flash controller
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_FLASH_CONTROLLER(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_FLASH_CONTROLLER_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_FLASH_CONTROLLER_MASK)

#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_PRINCE0_MASK (0x300000U)
#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_PRINCE0_SHIFT (20U)
/*! PRINCE0 - PRINCE0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_PRINCE0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_PRINCE0_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE2_PRINCE0_MASK)
/*! @} */

/*! @name APB_PERIPHERAL_GROUP1_MEM_RULE3 - APB Bridge Group 1 Memory Rule 3 */
/*! @{ */

#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS0_MASK (0x300U)
#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS0_SHIFT (8U)
/*! PUF_ALIAS0 - PUF_ALIAS0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS0_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS0_MASK)

#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS1_MASK (0x3000U)
#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS1_SHIFT (12U)
/*! PUF_ALIAS1 - PUF_ALIAS0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS1_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS1_MASK)

#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS2_MASK (0x30000U)
#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS2_SHIFT (16U)
/*! PUF_ALIAS2 - PUF_ALIAS2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS2(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS2_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS2_MASK)

#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS3_MASK (0x300000U)
#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS3_SHIFT (20U)
/*! PUF_ALIAS3 - PUF_ALIAS3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS3(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS3_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_PUF_ALIAS3_MASK)

#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_ROM_MASK (0x3000000U)
#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_ROM_SHIFT (24U)
/*! ROM - ROM
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_ROM(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_ROM_SHIFT)) & SECTRL_APB_PERIPHERAL_GROUP1_MEM_RULE3_ROM_MASK)
/*! @} */

/*! @name AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0 - AHB Peripheral 0 Slave Port9 Rule 0 */
/*! @{ */

#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_DMA0_MASK (0x3U)
#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_DMA0_SHIFT (0U)
/*! DMA0 - DMA0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_DMA0_SHIFT)) & SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_DMA0_MASK)

#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_USB_FSD_MASK (0x30U)
#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_USB_FSD_SHIFT (4U)
/*! USB_FSD - USB FSD
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_USB_FSD(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_USB_FSD_SHIFT)) & SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_USB_FSD_MASK)

#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_SCTIMER_MASK (0x300U)
#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_SCTIMER_SHIFT (8U)
/*! SCTIMER - SCTIMER
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_SCTIMER(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_SCTIMER_SHIFT)) & SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_SCTIMER_MASK)

#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM0_MASK (0x3000U)
#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM0_SHIFT (12U)
/*! FLEXCOMM0 - FLEXCOMM 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM0_SHIFT)) & SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM0_MASK)

#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM1_MASK (0x30000U)
#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM1_SHIFT (16U)
/*! FLEXCOMM1 - FLEXCOMM 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM1_SHIFT)) & SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM1_MASK)

#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM2_MASK (0x300000U)
#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM2_SHIFT (20U)
/*! FLEXCOMM2 - FLEXCOMM 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM2(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM2_SHIFT)) & SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM2_MASK)

#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM3_MASK (0x3000000U)
#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM3_SHIFT (24U)
/*! FLEXCOMM3 - FLEXCOMM 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM3(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM3_SHIFT)) & SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM3_MASK)

#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM4_MASK (0x30000000U)
#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM4_SHIFT (28U)
/*! FLEXCOMM4 - FLEXCOMM4
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM4(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM4_SHIFT)) & SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE0_FLEXCOMM4_MASK)
/*! @} */

/*! @name AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE1 - AHB Peripheral 0 Slave Port 9 Rule 1 */
/*! @{ */

#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE1_MAILBOX_MASK (0x3U)
#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE1_MAILBOX_SHIFT (0U)
/*! MAILBOX - MAILBOX
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE1_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE1_MAILBOX_SHIFT)) & SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE1_MAILBOX_MASK)

#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE1_GPIO_MASK (0x30U)
#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE1_GPIO_SHIFT (4U)
/*! GPIO - GPIO
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE1_GPIO(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE1_GPIO_SHIFT)) & SECTRL_AHB_PERIPHERAL0_SLAVE_PORT_P9_SLAVE_RULE1_GPIO_MASK)
/*! @} */

/*! @name AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0 - AHB Peripheral 1 Slave Port 10 Slave Rule 0 */
/*! @{ */

#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_DMIC0_MASK (0x3U)
#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_DMIC0_SHIFT (0U)
/*! DMIC0 - DMIC0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_DMIC0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_DMIC0_SHIFT)) & SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_DMIC0_MASK)

#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_CRC_MASK (0x30U)
#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_CRC_SHIFT (4U)
/*! CRC - CRC
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_CRC(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_CRC_SHIFT)) & SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_CRC_MASK)

#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_FLEXCOMM5_MASK (0x300U)
#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_FLEXCOMM5_SHIFT (8U)
/*! FLEXCOMM5 - FLEXCOMM 5
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_FLEXCOMM5(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_FLEXCOMM5_SHIFT)) & SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_FLEXCOMM5_MASK)

#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_FLEXCOMM6_MASK (0x3000U)
#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_FLEXCOMM6_SHIFT (12U)
/*! FLEXCOMM6 - FLEXCOMM 6
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_FLEXCOMM6(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_FLEXCOMM6_SHIFT)) & SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_FLEXCOMM6_MASK)

#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_FLEXCOMM7_MASK (0x30000U)
#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_FLEXCOMM7_SHIFT (16U)
/*! FLEXCOMM7 - FLEXCOMM 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_FLEXCOMM7(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_FLEXCOMM7_SHIFT)) & SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_FLEXCOMM7_MASK)

#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_DEBUG_MAILBOX_MASK (0x300000U)
#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_DEBUG_MAILBOX_SHIFT (20U)
/*! DEBUG_MAILBOX - FLEXCOMM 7
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_DEBUG_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_DEBUG_MAILBOX_SHIFT)) & SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_DEBUG_MAILBOX_MASK)

#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_MCAN_MASK (0x3000000U)
#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_MCAN_SHIFT (24U)
/*! MCAN - FLEXCOMM 14
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_MCAN(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_MCAN_SHIFT)) & SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_MCAN_MASK)

#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_HS_LSPI_MASK (0x30000000U)
#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_HS_LSPI_SHIFT (28U)
/*! HS_LSPI - FLEXCOMM 15
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_HS_LSPI(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_HS_LSPI_SHIFT)) & SECTRL_AHB_PERIPHERAL1_SLAVE_PORT_P10_SLAVE_0_HS_LSPI_MASK)
/*! @} */

/*! @name AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0 - AHB Peripheral 2 Slave Port 11 Slave Rule 0 */
/*! @{ */

#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_ADC_MASK (0x3U)
#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_ADC_SHIFT (0U)
/*! ADC - ADC
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_ADC(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_ADC_SHIFT)) & SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_ADC_MASK)

#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_CDOG_MASK (0x30U)
#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_CDOG_SHIFT (4U)
/*! CDOG - Code Watch Dog timer
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_CDOG(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_CDOG_SHIFT)) & SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_CDOG_MASK)

#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_USB_FS_HOST_MASK (0x300U)
#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_USB_FS_HOST_SHIFT (8U)
/*! USB_FS_HOST - USB FS HOST
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_USB_FS_HOST(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_USB_FS_HOST_SHIFT)) & SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_USB_FS_HOST_MASK)

#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_POWERQUAD_MASK (0x3000U)
#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_POWERQUAD_SHIFT (12U)
/*! POWERQUAD - POWERQUAD
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_POWERQUAD(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_POWERQUAD_SHIFT)) & SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_POWERQUAD_MASK)

#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_DMA1_MASK (0x30000U)
#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_DMA1_SHIFT (16U)
/*! DMA1 - DMA1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_DMA1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_DMA1_SHIFT)) & SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_DMA1_MASK)

#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_SECGPIO_MASK (0x300000U)
#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_SECGPIO_SHIFT (20U)
/*! SECGPIO - SECGPIO
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_SECGPIO(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_SECGPIO_SHIFT)) & SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_SECGPIO_MASK)

#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_AHB_SECURE_MASK (0x3000000U)
#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_AHB_SECURE_SHIFT (24U)
/*! AHB_SECURE - AHB_SECURE
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_AHB_SECURE(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_AHB_SECURE_SHIFT)) & SECTRL_AHB_PERIPHERAL2_SLAVE_PORT_P11_SLAVE_RULE0_AHB_SECURE_MASK)
/*! @} */

/*! @name AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0 - AHB Secure Control Peripheral Memory Rule 0 */
/*! @{ */

#define SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE0_MASK (0x3U)
#define SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE0_SHIFT (0U)
/*! RULE0 - Rule 0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE0_SHIFT)) & SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE0_MASK)

#define SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE1_MASK (0x30U)
#define SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE1_SHIFT (4U)
/*! RULE1 - Rule 1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE1_SHIFT)) & SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE1_MASK)

#define SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE2_MASK (0x300U)
#define SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE2_SHIFT (8U)
/*! RULE2 - Rule 2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE2(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE2_SHIFT)) & SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE2_MASK)

#define SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE3_MASK (0x3000U)
#define SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE3_SHIFT (12U)
/*! RULE3 - Rule 3
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE3(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE3_SHIFT)) & SECTRL_AHB_SECURE_CTRL_PERIPHERAL_MEM_RULE0_RULE3_MASK)
/*! @} */

/*! @name AIPS_BRIDGE_GROUP0_RULE0 - AIPS Bridge Group 0 Rule 0 */
/*! @{ */

#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_ADC1_MASK (0x30U)
#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_ADC1_SHIFT (4U)
/*! ADC1 - ADC1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_ADC1(x)  (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP0_RULE0_ADC1_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP0_RULE0_ADC1_MASK)

#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_DAC0_MASK (0x300U)
#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_DAC0_SHIFT (8U)
/*! DAC0 - DAC0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_DAC0(x)  (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP0_RULE0_DAC0_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP0_RULE0_DAC0_MASK)

#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_HSCOMP0_MASK (0x3000U)
#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_HSCOMP0_SHIFT (12U)
/*! HSCOMP0 - HSCOMP0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_HSCOMP0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP0_RULE0_HSCOMP0_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP0_RULE0_HSCOMP0_MASK)

#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_OPAMP0_MASK (0x30000U)
#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_OPAMP0_SHIFT (16U)
/*! OPAMP0 - OPAMP0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_OPAMP0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP0_RULE0_OPAMP0_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP0_RULE0_OPAMP0_MASK)

#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_VREF_MASK (0x300000U)
#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_VREF_SHIFT (20U)
/*! VREF - VREF
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_VREF(x)  (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP0_RULE0_VREF_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP0_RULE0_VREF_MASK)

#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_DAC1_MASK (0x3000000U)
#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_DAC1_SHIFT (24U)
/*! DAC1 - DAC1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_DAC1(x)  (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP0_RULE0_DAC1_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP0_RULE0_DAC1_MASK)

#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_HSCOMP1_MASK (0x30000000U)
#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_HSCOMP1_SHIFT (28U)
/*! HSCOMP1 - HSCOMP1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_AIPS_BRIDGE_GROUP0_RULE0_HSCOMP1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP0_RULE0_HSCOMP1_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP0_RULE0_HSCOMP1_MASK)
/*! @} */

/*! @name AIPS_BRIDGE_GROUP0_RULE1 - AIPS Bridge Group 0 Rule 1 */
/*! @{ */

#define SECTRL_AIPS_BRIDGE_GROUP0_RULE1_OPAMP1_MASK (0x3U)
#define SECTRL_AIPS_BRIDGE_GROUP0_RULE1_OPAMP1_SHIFT (0U)
/*! OPAMP1 - OPAMP1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_AIPS_BRIDGE_GROUP0_RULE1_OPAMP1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP0_RULE1_OPAMP1_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP0_RULE1_OPAMP1_MASK)

#define SECTRL_AIPS_BRIDGE_GROUP0_RULE1_DAC2_MASK (0x30U)
#define SECTRL_AIPS_BRIDGE_GROUP0_RULE1_DAC2_SHIFT (4U)
/*! DAC2 - DAC2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_AIPS_BRIDGE_GROUP0_RULE1_DAC2(x)  (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP0_RULE1_DAC2_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP0_RULE1_DAC2_MASK)

#define SECTRL_AIPS_BRIDGE_GROUP0_RULE1_HSCOMP2_MASK (0x300U)
#define SECTRL_AIPS_BRIDGE_GROUP0_RULE1_HSCOMP2_SHIFT (8U)
/*! HSCOMP2 - HSCOMP2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_AIPS_BRIDGE_GROUP0_RULE1_HSCOMP2(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP0_RULE1_HSCOMP2_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP0_RULE1_HSCOMP2_MASK)

#define SECTRL_AIPS_BRIDGE_GROUP0_RULE1_OPAMP2_MASK (0x3000U)
#define SECTRL_AIPS_BRIDGE_GROUP0_RULE1_OPAMP2_SHIFT (12U)
/*! OPAMP2 - OPAMP2
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_AIPS_BRIDGE_GROUP0_RULE1_OPAMP2(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP0_RULE1_OPAMP2_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP0_RULE1_OPAMP2_MASK)
/*! @} */

/*! @name AIPS_BRIDGE_GROUP1_RULE0 - AIPS Bridge Group 1 Rule 0 */
/*! @{ */

#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXSPI0_MASK (0x3U)
#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXSPI0_SHIFT (0U)
/*! FLEXSPI0 - FLEXSPI0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXSPI0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXSPI0_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXSPI0_MASK)

#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXSPI_CMX_MASK (0x30U)
#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXSPI_CMX_SHIFT (4U)
/*! FLEXSPI_CMX - FLEXSPI_CMX
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXSPI_CMX(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXSPI_CMX_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXSPI_CMX_MASK)

#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_LPCAC_MASK (0x300U)
#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_LPCAC_SHIFT (8U)
/*! LPCAC - LPCAC
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_LPCAC(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP1_RULE0_LPCAC_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP1_RULE0_LPCAC_MASK)

#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXPWM0_MASK (0x3000U)
#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXPWM0_SHIFT (12U)
/*! FLEXPWM0 - FLEXPWM0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXPWM0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXPWM0_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXPWM0_MASK)

#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_ENC0_MASK (0x30000U)
#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_ENC0_SHIFT (16U)
/*! ENC0 - FLEXSPI0 Registers
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_ENC0(x)  (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP1_RULE0_ENC0_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP1_RULE0_ENC0_MASK)

#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXSPI_PWM1_MASK (0x300000U)
#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXSPI_PWM1_SHIFT (20U)
/*! FLEXSPI_PWM1 - FLEXSPI_PWM1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXSPI_PWM1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXSPI_PWM1_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP1_RULE0_FLEXSPI_PWM1_MASK)

#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_ENC1_MASK (0x3000000U)
#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_ENC1_SHIFT (24U)
/*! ENC1 - ENC1
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_ENC1(x)  (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP1_RULE0_ENC1_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP1_RULE0_ENC1_MASK)

#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_AOI0_MASK (0x30000000U)
#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_AOI0_SHIFT (28U)
/*! AOI0 - AOI0
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_AIPS_BRIDGE_GROUP1_RULE0_AOI0(x)  (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP1_RULE0_AOI0_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP1_RULE0_AOI0_MASK)
/*! @} */

/*! @name AIPS_BRIDGE_GROUP1_RULE1 - AIPS Bridge Group 1 Rule 1 */
/*! @{ */

#define SECTRL_AIPS_BRIDGE_GROUP1_RULE1_AOI1_MASK (0x3U)
#define SECTRL_AIPS_BRIDGE_GROUP1_RULE1_AOI1_SHIFT (0U)
/*! AOI1 - RNG (Random Number Generator)
 *  0b00..Non-secure and non-privilege user access allowed
 *  0b01..Non-secure and privilege access allowed
 *  0b10..Secure and non-privilege user access allowed
 *  0b11..Secure and privilege user access allowed
 */
#define SECTRL_AIPS_BRIDGE_GROUP1_RULE1_AOI1(x)  (((uint32_t)(((uint32_t)(x)) << SECTRL_AIPS_BRIDGE_GROUP1_RULE1_AOI1_SHIFT)) & SECTRL_AIPS_BRIDGE_GROUP1_RULE1_AOI1_MASK)
/*! @} */

/*! @name SEC_VIO_ADDRN_SEC_VIO_ADDR - Security Violation Address */
/*! @{ */

#define SECTRL_SEC_VIO_ADDRN_SEC_VIO_ADDR_SEC_VIO_INFO_WRITE_MASK (0xFFFFFFFFU)
#define SECTRL_SEC_VIO_ADDRN_SEC_VIO_ADDR_SEC_VIO_INFO_WRITE_SHIFT (0U)
/*! SEC_VIO_INFO_WRITE - Security violation access read/write indicator
 */
#define SECTRL_SEC_VIO_ADDRN_SEC_VIO_ADDR_SEC_VIO_INFO_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_ADDRN_SEC_VIO_ADDR_SEC_VIO_INFO_WRITE_SHIFT)) & SECTRL_SEC_VIO_ADDRN_SEC_VIO_ADDR_SEC_VIO_INFO_WRITE_MASK)
/*! @} */

/* The count of SECTRL_SEC_VIO_ADDRN_SEC_VIO_ADDR */
#define SECTRL_SEC_VIO_ADDRN_SEC_VIO_ADDR_COUNT  (32U)

/*! @name SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO - Security Violation Miscellaneous Information at Address */
/*! @{ */

#define SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK (0x1U)
#define SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT (0U)
/*! SEC_VIO_INFO_WRITE - Security violation access read/write indicator
 *  0b0..Read access
 *  0b1..Write access
 */
#define SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT)) & SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK)

#define SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK (0x2U)
#define SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT (1U)
/*! SEC_VIO_INFO_DATA_ACCESS - Security Violation Info Data Access
 *  0b0..Code
 *  0b1..Data
 */
#define SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT)) & SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK)

#define SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK (0xF0U)
#define SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT (4U)
/*! SEC_VIO_INFO_MASTER_SEC_LEVEL - Security Violation Info Master Security Level
 */
#define SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT)) & SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK)

#define SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK (0xF00U)
#define SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT (8U)
/*! SEC_VIO_INFO_MASTER - Security violation master number
 *  0b0000..M33 Code
 *  0b0001..M33 System
 *  0b0010..DMA0
 *  0b0011..DMA1
 *  0b0100..USBFS Device
 *  0b0101..USBFS Host
 *  0b0110..EZH Instruction
 *  0b0111..EZH Data
 *  0b1000..CSSV2
 *  0b1001..MCAN
 *  0b1010..PKC M0
 *  0b1011..GPU
 *  0b1100..DSP Data
 *  0b1101..DSP Instruction
 *  0b1110..Reserved
 *  0b1111..Reserved
 */
#define SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT)) & SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK)
/*! @} */

/* The count of SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO */
#define SECTRL_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_COUNT (32U)

/*! @name SEC_VIO_INFO_VALID - Security Violation Info Validity for Address */
/*! @{ */

#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK (0x1U)
#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT (0U)
/*! VIO_INFO_VALID0 - Violation information valid flag for AHB port 0
 *  0b0..Not valid
 *  0b1..Valid
 */
#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK)

#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK (0x2U)
#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT (1U)
/*! VIO_INFO_VALID1 - Violation information valid flag for AHB port 1
 *  0b0..Not valid
 *  0b1..Valid
 */
#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK)

#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK (0x4U)
#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT (2U)
/*! VIO_INFO_VALID2 - Violation information valid flag for AHB port 2
 *  0b0..Not valid
 *  0b1..Valid
 */
#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK)

#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK (0x8U)
#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT (3U)
/*! VIO_INFO_VALID3 - Violation information valid flag for AHB port 3
 *  0b0..Not valid
 *  0b1..Valid
 */
#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK)

#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK (0x10U)
#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT (4U)
/*! VIO_INFO_VALID4 - Violation information valid flag for AHB port 4
 *  0b0..Not valid
 *  0b1..Valid
 */
#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK)

#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK (0x20U)
#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT (5U)
/*! VIO_INFO_VALID5 - Violation information valid flag for AHB port 5
 *  0b0..Not valid
 *  0b1..Valid
 */
#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK)

#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK (0x40U)
#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT (6U)
/*! VIO_INFO_VALID6 - Violation information valid flag for AHB port 6
 *  0b0..Not valid
 *  0b1..Valid
 */
#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK)

#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK (0x80U)
#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT (7U)
/*! VIO_INFO_VALID7 - Violation information valid flag for AHB port 7
 *  0b0..Not valid
 *  0b1..Valid
 */
#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK)

#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK (0x100U)
#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT (8U)
/*! VIO_INFO_VALID8 - Violation information valid flag for AHB port 8
 *  0b0..Not valid
 *  0b1..Valid
 */
#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK)

#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK (0x200U)
#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT (9U)
/*! VIO_INFO_VALID9 - Violation information valid flag for AHB port 9
 *  0b0..Not valid
 *  0b1..Valid
 */
#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK)

#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK (0x400U)
#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT (10U)
/*! VIO_INFO_VALID10 - Violation information valid flag for AHB port 10
 *  0b0..Not valid
 *  0b1..Valid
 */
#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK)

#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK (0x800U)
#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT (11U)
/*! VIO_INFO_VALID11 - Violation information valid flag for AHB port 11
 *  0b0..Not valid
 *  0b1..Valid
 */
#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK)

#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_MASK (0x1000U)
#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_SHIFT (12U)
/*! VIO_INFO_VALID12 - Violation information valid flag for AHB port 12
 *  0b0..Not valid
 *  0b1..Valid
 */
#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID12(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_MASK)

#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_MASK (0x2000U)
#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_SHIFT (13U)
/*! VIO_INFO_VALID13 - Violation information valid flag for AHB port 13
 *  0b0..Not valid
 *  0b1..Valid
 */
#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID13(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_MASK)

#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_MASK (0x4000U)
#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_SHIFT (14U)
/*! VIO_INFO_VALID14 - Violation information valid flag for AHB port 14
 *  0b0..Not valid
 *  0b1..Valid
 */
#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID14(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_MASK)

#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_MASK (0x8000U)
#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_SHIFT (15U)
/*! VIO_INFO_VALID15 - Violation information valid flag for AHB port 15
 *  0b0..Not valid
 *  0b1..Valid
 */
#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID15(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_MASK)

#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_MASK (0x10000U)
#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_SHIFT (16U)
/*! VIO_INFO_VALID16 - Violation information valid flag for AHB port 16
 *  0b0..Not valid
 *  0b1..Valid
 */
#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID16(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_MASK)

#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_MASK (0x20000U)
#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_SHIFT (17U)
/*! VIO_INFO_VALID17 - Violation information valid flag for AHB port 17
 *  0b0..Not valid
 *  0b1..Valid
 */
#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID17(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_MASK)

#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID18_MASK (0x40000U)
#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID18_SHIFT (18U)
/*! VIO_INFO_VALID18 - Violation information valid flag for AHB port 18
 *  0b0..Not valid
 *  0b1..Valid
 */
#define SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID18(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID18_SHIFT)) & SECTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID18_MASK)
/*! @} */

/*! @name SEC_GPIO_MASKN_SEC_GPIO_MASK - GPIO Mask for Port 0..GPIO Mask for Port 2 */
/*! @{ */

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN0_SEC_MASK_MASK (0x1U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN0_SEC_MASK_SHIFT (0U)
/*! PIO0_PIN0_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN0_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN0_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN0_SEC_MASK_MASK (0x1U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN0_SEC_MASK_SHIFT (0U)
/*! PIO1_PIN0_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN0_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN0_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN0_SEC_MASK_MASK (0x1U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN0_SEC_MASK_SHIFT (0U)
/*! PIO2_PIN0_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN0_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN0_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN1_SEC_MASK_MASK (0x2U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN1_SEC_MASK_SHIFT (1U)
/*! PIO0_PIN1_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN1_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN1_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN1_SEC_MASK_MASK (0x2U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN1_SEC_MASK_SHIFT (1U)
/*! PIO1_PIN1_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN1_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN1_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN1_SEC_MASK_MASK (0x2U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN1_SEC_MASK_SHIFT (1U)
/*! PIO2_PIN1_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN1_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN1_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN2_SEC_MASK_MASK (0x4U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN2_SEC_MASK_SHIFT (2U)
/*! PIO0_PIN2_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN2_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN2_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN2_SEC_MASK_MASK (0x4U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN2_SEC_MASK_SHIFT (2U)
/*! PIO1_PIN2_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN2_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN2_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN2_SEC_MASK_MASK (0x4U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN2_SEC_MASK_SHIFT (2U)
/*! PIO2_PIN2_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN2_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN2_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN3_SEC_MASK_MASK (0x8U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN3_SEC_MASK_SHIFT (3U)
/*! PIO0_PIN3_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN3_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN3_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN3_SEC_MASK_MASK (0x8U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN3_SEC_MASK_SHIFT (3U)
/*! PIO1_PIN3_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN3_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN3_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN3_SEC_MASK_MASK (0x8U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN3_SEC_MASK_SHIFT (3U)
/*! PIO2_PIN3_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN3_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN3_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN4_SEC_MASK_MASK (0x10U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN4_SEC_MASK_SHIFT (4U)
/*! PIO0_PIN4_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN4_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN4_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN4_SEC_MASK_MASK (0x10U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN4_SEC_MASK_SHIFT (4U)
/*! PIO1_PIN4_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN4_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN4_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN4_SEC_MASK_MASK (0x10U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN4_SEC_MASK_SHIFT (4U)
/*! PIO2_PIN4_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN4_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN4_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN5_SEC_MASK_MASK (0x20U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN5_SEC_MASK_SHIFT (5U)
/*! PIO0_PIN5_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN5_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN5_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN5_SEC_MASK_MASK (0x20U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN5_SEC_MASK_SHIFT (5U)
/*! PIO1_PIN5_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN5_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN5_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN5_SEC_MASK_MASK (0x20U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN5_SEC_MASK_SHIFT (5U)
/*! PIO2_PIN5_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN5_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN5_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN6_SEC_MASK_MASK (0x40U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN6_SEC_MASK_SHIFT (6U)
/*! PIO0_PIN6_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN6_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN6_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN6_SEC_MASK_MASK (0x40U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN6_SEC_MASK_SHIFT (6U)
/*! PIO1_PIN6_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN6_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN6_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN6_SEC_MASK_MASK (0x40U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN6_SEC_MASK_SHIFT (6U)
/*! PIO2_PIN6_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN6_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN6_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN7_SEC_MASK_MASK (0x80U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN7_SEC_MASK_SHIFT (7U)
/*! PIO0_PIN7_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN7_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN7_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN7_SEC_MASK_MASK (0x80U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN7_SEC_MASK_SHIFT (7U)
/*! PIO1_PIN7_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN7_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN7_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN7_SEC_MASK_MASK (0x80U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN7_SEC_MASK_SHIFT (7U)
/*! PIO2_PIN7_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN7_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN7_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN8_SEC_MASK_MASK (0x100U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN8_SEC_MASK_SHIFT (8U)
/*! PIO0_PIN8_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN8_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN8_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN8_SEC_MASK_MASK (0x100U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN8_SEC_MASK_SHIFT (8U)
/*! PIO1_PIN8_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN8_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN8_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN8_SEC_MASK_MASK (0x100U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN8_SEC_MASK_SHIFT (8U)
/*! PIO2_PIN8_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN8_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN8_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN9_SEC_MASK_MASK (0x200U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN9_SEC_MASK_SHIFT (9U)
/*! PIO0_PIN9_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN9_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN9_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN9_SEC_MASK_MASK (0x200U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN9_SEC_MASK_SHIFT (9U)
/*! PIO1_PIN9_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN9_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN9_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN9_SEC_MASK_MASK (0x200U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN9_SEC_MASK_SHIFT (9U)
/*! PIO2_PIN9_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN9_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN9_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN10_SEC_MASK_MASK (0x400U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN10_SEC_MASK_SHIFT (10U)
/*! PIO0_PIN10_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN10_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN10_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN10_SEC_MASK_MASK (0x400U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN10_SEC_MASK_SHIFT (10U)
/*! PIO1_PIN10_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN10_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN10_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN10_SEC_MASK_MASK (0x400U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN10_SEC_MASK_SHIFT (10U)
/*! PIO2_PIN10_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN10_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN10_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN11_SEC_MASK_MASK (0x800U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN11_SEC_MASK_SHIFT (11U)
/*! PIO0_PIN11_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN11_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN11_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN11_SEC_MASK_MASK (0x800U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN11_SEC_MASK_SHIFT (11U)
/*! PIO1_PIN11_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN11_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN11_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN11_SEC_MASK_MASK (0x800U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN11_SEC_MASK_SHIFT (11U)
/*! PIO2_PIN11_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN11_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN11_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN12_SEC_MASK_MASK (0x1000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN12_SEC_MASK_SHIFT (12U)
/*! PIO0_PIN12_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN12_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN12_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN12_SEC_MASK_MASK (0x1000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN12_SEC_MASK_SHIFT (12U)
/*! PIO1_PIN12_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN12_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN12_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN12_SEC_MASK_MASK (0x1000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN12_SEC_MASK_SHIFT (12U)
/*! PIO2_PIN12_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN12_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN12_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN13_SEC_MASK_MASK (0x2000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN13_SEC_MASK_SHIFT (13U)
/*! PIO0_PIN13_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN13_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN13_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN13_SEC_MASK_MASK (0x2000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN13_SEC_MASK_SHIFT (13U)
/*! PIO1_PIN13_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN13_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN13_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN13_SEC_MASK_MASK (0x2000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN13_SEC_MASK_SHIFT (13U)
/*! PIO2_PIN13_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN13_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN13_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN14_SEC_MASK_MASK (0x4000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN14_SEC_MASK_SHIFT (14U)
/*! PIO0_PIN14_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN14_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN14_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN14_SEC_MASK_MASK (0x4000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN14_SEC_MASK_SHIFT (14U)
/*! PIO1_PIN14_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN14_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN14_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN14_SEC_MASK_MASK (0x4000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN14_SEC_MASK_SHIFT (14U)
/*! PIO2_PIN14_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN14_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN14_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN15_SEC_MASK_MASK (0x8000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN15_SEC_MASK_SHIFT (15U)
/*! PIO0_PIN15_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN15_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN15_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN15_SEC_MASK_MASK (0x8000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN15_SEC_MASK_SHIFT (15U)
/*! PIO1_PIN15_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN15_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN15_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN15_SEC_MASK_MASK (0x8000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN15_SEC_MASK_SHIFT (15U)
/*! PIO2_PIN15_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN15_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN15_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN16_SEC_MASK_MASK (0x10000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN16_SEC_MASK_SHIFT (16U)
/*! PIO0_PIN16_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN16_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN16_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN16_SEC_MASK_MASK (0x10000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN16_SEC_MASK_SHIFT (16U)
/*! PIO1_PIN16_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN16_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN16_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN16_SEC_MASK_MASK (0x10000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN16_SEC_MASK_SHIFT (16U)
/*! PIO2_PIN16_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN16_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN16_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN17_SEC_MASK_MASK (0x20000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN17_SEC_MASK_SHIFT (17U)
/*! PIO0_PIN17_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN17_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN17_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN17_SEC_MASK_MASK (0x20000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN17_SEC_MASK_SHIFT (17U)
/*! PIO1_PIN17_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN17_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN17_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN17_SEC_MASK_MASK (0x20000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN17_SEC_MASK_SHIFT (17U)
/*! PIO2_PIN17_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN17_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN17_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN18_SEC_MASK_MASK (0x40000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN18_SEC_MASK_SHIFT (18U)
/*! PIO0_PIN18_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN18_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN18_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN18_SEC_MASK_MASK (0x40000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN18_SEC_MASK_SHIFT (18U)
/*! PIO1_PIN18_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN18_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN18_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN18_SEC_MASK_MASK (0x40000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN18_SEC_MASK_SHIFT (18U)
/*! PIO2_PIN18_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN18_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN18_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN19_SEC_MASK_MASK (0x80000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN19_SEC_MASK_SHIFT (19U)
/*! PIO0_PIN19_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN19_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN19_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN19_SEC_MASK_MASK (0x80000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN19_SEC_MASK_SHIFT (19U)
/*! PIO1_PIN19_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN19_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN19_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN19_SEC_MASK_MASK (0x80000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN19_SEC_MASK_SHIFT (19U)
/*! PIO2_PIN19_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN19_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN19_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN20_SEC_MASK_MASK (0x100000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN20_SEC_MASK_SHIFT (20U)
/*! PIO0_PIN20_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN20_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN20_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN20_SEC_MASK_MASK (0x100000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN20_SEC_MASK_SHIFT (20U)
/*! PIO1_PIN20_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN20_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN20_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN20_SEC_MASK_MASK (0x100000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN20_SEC_MASK_SHIFT (20U)
/*! PIO2_PIN20_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN20_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN20_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN21_SEC_MASK_MASK (0x200000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN21_SEC_MASK_SHIFT (21U)
/*! PIO0_PIN21_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN21_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN21_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN21_SEC_MASK_MASK (0x200000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN21_SEC_MASK_SHIFT (21U)
/*! PIO1_PIN21_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN21_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN21_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN21_SEC_MASK_MASK (0x200000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN21_SEC_MASK_SHIFT (21U)
/*! PIO2_PIN21_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN21_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN21_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN22_SEC_MASK_MASK (0x400000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN22_SEC_MASK_SHIFT (22U)
/*! PIO0_PIN22_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN22_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN22_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN22_SEC_MASK_MASK (0x400000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN22_SEC_MASK_SHIFT (22U)
/*! PIO1_PIN22_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN22_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN22_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN22_SEC_MASK_MASK (0x400000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN22_SEC_MASK_SHIFT (22U)
/*! PIO2_PIN22_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN22_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN22_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN23_SEC_MASK_MASK (0x800000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN23_SEC_MASK_SHIFT (23U)
/*! PIO0_PIN23_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN23_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN23_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN23_SEC_MASK_MASK (0x800000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN23_SEC_MASK_SHIFT (23U)
/*! PIO1_PIN23_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN23_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN23_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN23_SEC_MASK_MASK (0x800000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN23_SEC_MASK_SHIFT (23U)
/*! PIO2_PIN23_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN23_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN23_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN24_SEC_MASK_MASK (0x1000000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN24_SEC_MASK_SHIFT (24U)
/*! PIO0_PIN24_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN24_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN24_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN24_SEC_MASK_MASK (0x1000000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN24_SEC_MASK_SHIFT (24U)
/*! PIO1_PIN24_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN24_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN24_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN24_SEC_MASK_MASK (0x1000000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN24_SEC_MASK_SHIFT (24U)
/*! PIO2_PIN24_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN24_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN24_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN25_SEC_MASK_MASK (0x2000000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN25_SEC_MASK_SHIFT (25U)
/*! PIO0_PIN25_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN25_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN25_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN25_SEC_MASK_MASK (0x2000000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN25_SEC_MASK_SHIFT (25U)
/*! PIO1_PIN25_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN25_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN25_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN25_SEC_MASK_MASK (0x2000000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN25_SEC_MASK_SHIFT (25U)
/*! PIO2_PIN25_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN25_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN25_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN26_SEC_MASK_MASK (0x4000000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN26_SEC_MASK_SHIFT (26U)
/*! PIO0_PIN26_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN26_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN26_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN26_SEC_MASK_MASK (0x4000000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN26_SEC_MASK_SHIFT (26U)
/*! PIO1_PIN26_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN26_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN26_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN26_SEC_MASK_MASK (0x4000000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN26_SEC_MASK_SHIFT (26U)
/*! PIO2_PIN26_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN26_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN26_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN27_SEC_MASK_MASK (0x8000000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN27_SEC_MASK_SHIFT (27U)
/*! PIO0_PIN27_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN27_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN27_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN27_SEC_MASK_MASK (0x8000000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN27_SEC_MASK_SHIFT (27U)
/*! PIO1_PIN27_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN27_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN27_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN27_SEC_MASK_MASK (0x8000000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN27_SEC_MASK_SHIFT (27U)
/*! PIO2_PIN27_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN27_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN27_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN28_SEC_MASK_MASK (0x10000000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN28_SEC_MASK_SHIFT (28U)
/*! PIO0_PIN28_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN28_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN28_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN28_SEC_MASK_MASK (0x10000000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN28_SEC_MASK_SHIFT (28U)
/*! PIO1_PIN28_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN28_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN28_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN28_SEC_MASK_MASK (0x10000000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN28_SEC_MASK_SHIFT (28U)
/*! PIO2_PIN28_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN28_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN28_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN29_SEC_MASK_MASK (0x20000000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN29_SEC_MASK_SHIFT (29U)
/*! PIO0_PIN29_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN29_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN29_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN29_SEC_MASK_MASK (0x20000000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN29_SEC_MASK_SHIFT (29U)
/*! PIO1_PIN29_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN29_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN29_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN29_SEC_MASK_MASK (0x20000000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN29_SEC_MASK_SHIFT (29U)
/*! PIO2_PIN29_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN29_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN29_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN30_SEC_MASK_MASK (0x40000000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN30_SEC_MASK_SHIFT (30U)
/*! PIO0_PIN30_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN30_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN30_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN30_SEC_MASK_MASK (0x40000000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN30_SEC_MASK_SHIFT (30U)
/*! PIO1_PIN30_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN30_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN30_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN30_SEC_MASK_MASK (0x40000000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN30_SEC_MASK_SHIFT (30U)
/*! PIO2_PIN30_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN30_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN30_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN31_SEC_MASK_MASK (0x80000000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN31_SEC_MASK_SHIFT (31U)
/*! PIO0_PIN31_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN31_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN31_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN31_SEC_MASK_MASK (0x80000000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN31_SEC_MASK_SHIFT (31U)
/*! PIO1_PIN31_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN31_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN31_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN31_SEC_MASK_MASK (0x80000000U)
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN31_SEC_MASK_SHIFT (31U)
/*! PIO2_PIN31_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN31_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO2_PIN31_SEC_MASK_MASK)
/*! @} */

/* The count of SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK */
#define SECTRL_SEC_GPIO_MASKN_SEC_GPIO_MASK_COUNT (3U)

/*! @name SEC_GPIO_MASK3 - GPIO Mask for Port 3 */
/*! @{ */

#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN0_SEC_MASK_MASK (0x1U)
#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN0_SEC_MASK_SHIFT (0U)
/*! PIO3_PIN0_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASK3_PIO3_PIN0_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASK3_PIO3_PIN0_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN1_SEC_MASK_MASK (0x2U)
#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN1_SEC_MASK_SHIFT (1U)
/*! PIO3_PIN1_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASK3_PIO3_PIN1_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASK3_PIO3_PIN1_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN2_SEC_MASK_MASK (0x4U)
#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN2_SEC_MASK_SHIFT (2U)
/*! PIO3_PIN2_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASK3_PIO3_PIN2_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASK3_PIO3_PIN2_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN3_SEC_MASK_MASK (0x8U)
#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN3_SEC_MASK_SHIFT (3U)
/*! PIO3_PIN3_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASK3_PIO3_PIN3_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASK3_PIO3_PIN3_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN4_SEC_MASK_MASK (0x10U)
#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN4_SEC_MASK_SHIFT (4U)
/*! PIO3_PIN4_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASK3_PIO3_PIN4_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASK3_PIO3_PIN4_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN5_SEC_MASK_MASK (0x20U)
#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN5_SEC_MASK_SHIFT (5U)
/*! PIO3_PIN5_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASK3_PIO3_PIN5_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASK3_PIO3_PIN5_SEC_MASK_MASK)

#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN6_SEC_MASK_MASK (0x40U)
#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN6_SEC_MASK_SHIFT (6U)
/*! PIO3_PIN6_SEC_MASK - Mask bit
 *  0b0..Masked
 *  0b1..Not masked
 */
#define SECTRL_SEC_GPIO_MASK3_PIO3_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GPIO_MASK3_PIO3_PIN6_SEC_MASK_SHIFT)) & SECTRL_SEC_GPIO_MASK3_PIO3_PIN6_SEC_MASK_MASK)
/*! @} */

/*! @name SEC_GP_REG_LOCK - Secure Mask Lock */
/*! @{ */

#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK0_LOCK_MASK (0x3U)
#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT (0U)
/*! SEC_GPIO_MASK0_LOCK - Secure GPIO _MASK0 Lock
 *  0b00..Reserved
 *  0b01..SEC_GPIO_MASK0 cannot be written
 *  0b10..SEC_GPIO_MASK0 can be written
 *  0b11..Reserved
 */
#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT)) & SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK0_LOCK_MASK)

#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK1_LOCK_MASK (0xCU)
#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT (2U)
/*! SEC_GPIO_MASK1_LOCK - Secure GPIO _MASK1 Lock
 *  0b00..Reserved
 *  0b01..SEC_GPIO_MASK1 cannot be written
 *  0b10..SEC_GPIO_MASK1 can be written
 *  0b11..Reserved
 */
#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT)) & SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK1_LOCK_MASK)

#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK2_LOCK_MASK (0x30U)
#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK2_LOCK_SHIFT (4U)
/*! SEC_GPIO_MASK2_LOCK - Secure GPIO _MASK2 Lock
 *  0b00..Reserved
 *  0b01..SEC_GPIO_MASK2 cannot be written
 *  0b10..SEC_GPIO_MASK2 can be written
 *  0b11..Reserved
 */
#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK2_LOCK_SHIFT)) & SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK2_LOCK_MASK)

#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK3_LOCK_MASK (0xC0U)
#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK3_LOCK_SHIFT (6U)
/*! SEC_GPIO_MASK3_LOCK - Secure GPIO _MASK3 Lock
 *  0b00..Reserved
 *  0b01..SEC_GPIO_MASK3 cannot be written
 *  0b10..SEC_GPIO_MASK3 can be written
 *  0b11..Reserved
 */
#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK3_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK3_LOCK_SHIFT)) & SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK3_LOCK_MASK)

#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK4_LOCK_MASK (0x300U)
#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK4_LOCK_SHIFT (8U)
/*! SEC_GPIO_MASK4_LOCK - SEC_GPIO_MASK4 Lock
 *  0b00..Reserved
 *  0b01..SEC_GPIO_MASK4_LOCK cannot be written
 *  0b10..SEC_GPIO_MASK4_LOCK can be written
 *  0b11..Reserved
 */
#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK4_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK4_LOCK_SHIFT)) & SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK4_LOCK_MASK)

#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK5_LOCK_MASK (0xC00U)
#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK5_LOCK_SHIFT (10U)
/*! SEC_GPIO_MASK5_LOCK - SEC_GPIO_MASK5 Lock
 *  0b00..Reserved
 *  0b01..SEC_GPIO_MASK5 cannot be written
 *  0b10..SEC_GPIO_MASK5 can be written
 *  0b11..Reserved
 */
#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK5_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK5_LOCK_SHIFT)) & SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK5_LOCK_MASK)

#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK6_LOCK_MASK (0x3000U)
#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK6_LOCK_SHIFT (12U)
/*! SEC_GPIO_MASK6_LOCK - SEC_GPIO_MASK6 Lock
 *  0b00..Reserved
 *  0b01..SEC_GPIO_MASK6 cannot be written
 *  0b10..SEC_GPIO_MASK6 can be written
 *  0b11..Reserved
 */
#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK6_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK6_LOCK_SHIFT)) & SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK6_LOCK_MASK)

#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK7_LOCK_MASK (0xC000U)
#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK7_LOCK_SHIFT (14U)
/*! SEC_GPIO_MASK7_LOCK - SEC_GPIO_MASK7 Lock
 *  0b00..Reserved
 *  0b01..SEC_GPIO_MASK7 cannot be written
 *  0b10..SEC_GPIO_MASK7 can be written
 *  0b11..Reserved
 */
#define SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK7_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK7_LOCK_SHIFT)) & SECTRL_SEC_GP_REG_LOCK_SEC_GPIO_MASK7_LOCK_MASK)

#define SECTRL_SEC_GP_REG_LOCK_SEC_DSP_INT_MASK_LOCK_MASK (0x30000U)
#define SECTRL_SEC_GP_REG_LOCK_SEC_DSP_INT_MASK_LOCK_SHIFT (16U)
/*! SEC_DSP_INT_MASK_LOCK - SEC_DSP_INT_MASK Lock
 *  0b00..Reserved
 *  0b01..SEC_DSP_INT_MASK cannot be written
 *  0b10..SEC_DSP_INT_MASK can be written
 *  0b11..Reserved
 */
#define SECTRL_SEC_GP_REG_LOCK_SEC_DSP_INT_MASK_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_SEC_GP_REG_LOCK_SEC_DSP_INT_MASK_LOCK_SHIFT)) & SECTRL_SEC_GP_REG_LOCK_SEC_DSP_INT_MASK_LOCK_MASK)
/*! @} */

/*! @name MASTER_SEC_LEVEL - Master Secure Level */
/*! @{ */

#define SECTRL_MASTER_SEC_LEVEL_DMA0_MASK        (0x30U)
#define SECTRL_MASTER_SEC_LEVEL_DMA0_SHIFT       (4U)
/*! DMA0 - DMA0
 *  0b00..Non-secure and non-privileged Master
 *  0b01..Non-secure and privileged Master
 *  0b10..Secure and non-privileged Master
 *  0b11..Secure and privileged Master
 */
#define SECTRL_MASTER_SEC_LEVEL_DMA0(x)          (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_LEVEL_DMA0_SHIFT)) & SECTRL_MASTER_SEC_LEVEL_DMA0_MASK)

#define SECTRL_MASTER_SEC_LEVEL_DMA1_MASK        (0xC0U)
#define SECTRL_MASTER_SEC_LEVEL_DMA1_SHIFT       (6U)
/*! DMA1 - DMA1
 *  0b00..Non-secure and non-privileged Master
 *  0b01..Non-secure and privileged Master
 *  0b10..Secure and non-privileged Master
 *  0b11..Secure and privileged Master
 */
#define SECTRL_MASTER_SEC_LEVEL_DMA1(x)          (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_LEVEL_DMA1_SHIFT)) & SECTRL_MASTER_SEC_LEVEL_DMA1_MASK)

#define SECTRL_MASTER_SEC_LEVEL_USBFSD_MASK      (0x300U)
#define SECTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT     (8U)
/*! USBFSD - USBFS Device
 *  0b00..Non-secure and non-privileged Master
 *  0b01..Non-secure and privileged Master
 *  0b10..Secure and non-privileged Master
 *  0b11..Secure and privileged Master
 */
#define SECTRL_MASTER_SEC_LEVEL_USBFSD(x)        (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT)) & SECTRL_MASTER_SEC_LEVEL_USBFSD_MASK)

#define SECTRL_MASTER_SEC_LEVEL_USBFSH_MASK      (0xC00U)
#define SECTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT     (10U)
/*! USBFSH - USBFS Host
 *  0b00..Non-secure and non-privileged Master
 *  0b01..Non-secure and privileged Master
 *  0b10..Secure and non-privileged Master
 *  0b11..Secure and privileged Master
 */
#define SECTRL_MASTER_SEC_LEVEL_USBFSH(x)        (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT)) & SECTRL_MASTER_SEC_LEVEL_USBFSH_MASK)

#define SECTRL_MASTER_SEC_LEVEL_EZH_D_MASK       (0x3000U)
#define SECTRL_MASTER_SEC_LEVEL_EZH_D_SHIFT      (12U)
/*! EZH_D - EZH Data
 *  0b00..Non-secure and non-privileged Master
 *  0b01..Non-secure and privileged Master
 *  0b10..Secure and non-privileged Master
 *  0b11..Secure and privileged Master
 */
#define SECTRL_MASTER_SEC_LEVEL_EZH_D(x)         (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_LEVEL_EZH_D_SHIFT)) & SECTRL_MASTER_SEC_LEVEL_EZH_D_MASK)

#define SECTRL_MASTER_SEC_LEVEL_EZH_I_MASK       (0xC000U)
#define SECTRL_MASTER_SEC_LEVEL_EZH_I_SHIFT      (14U)
/*! EZH_I - EZH Instruction
 *  0b00..Non-secure and non-privileged Master
 *  0b01..Non-secure and privileged Master
 *  0b10..Secure and non-privileged Master
 *  0b11..Secure and privileged Master
 */
#define SECTRL_MASTER_SEC_LEVEL_EZH_I(x)         (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_LEVEL_EZH_I_SHIFT)) & SECTRL_MASTER_SEC_LEVEL_EZH_I_MASK)

#define SECTRL_MASTER_SEC_LEVEL_MCAN_MASK        (0xC0000U)
#define SECTRL_MASTER_SEC_LEVEL_MCAN_SHIFT       (18U)
/*! MCAN - MCAN
 *  0b00..Non-secure and non-privileged Master
 *  0b01..Non-secure and privileged Master
 *  0b10..Secure and non-privileged Master
 *  0b11..Secure and privileged Master
 */
#define SECTRL_MASTER_SEC_LEVEL_MCAN(x)          (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_LEVEL_MCAN_SHIFT)) & SECTRL_MASTER_SEC_LEVEL_MCAN_MASK)

#define SECTRL_MASTER_SEC_LEVEL_POWERQUAD_MASK   (0x300000U)
#define SECTRL_MASTER_SEC_LEVEL_POWERQUAD_SHIFT  (20U)
/*! POWERQUAD - POWERQUAD
 *  0b00..Non-secure and non-privileged Master
 *  0b01..Non-secure and privileged Master
 *  0b10..Secure and non-privileged Master
 *  0b11..Secure and privileged Master
 */
#define SECTRL_MASTER_SEC_LEVEL_POWERQUAD(x)     (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_LEVEL_POWERQUAD_SHIFT)) & SECTRL_MASTER_SEC_LEVEL_POWERQUAD_MASK)

#define SECTRL_MASTER_SEC_LEVEL_PKC_MASK         (0xC00000U)
#define SECTRL_MASTER_SEC_LEVEL_PKC_SHIFT        (22U)
/*! PKC - PKC
 *  0b00..Non-secure and non-privileged Master
 *  0b01..Non-secure and privileged Master
 *  0b10..Secure and non-privileged Master
 *  0b11..Secure and privileged Master
 */
#define SECTRL_MASTER_SEC_LEVEL_PKC(x)           (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_LEVEL_PKC_SHIFT)) & SECTRL_MASTER_SEC_LEVEL_PKC_MASK)

#define SECTRL_MASTER_SEC_LEVEL_DSP_D_MASK       (0x3000000U)
#define SECTRL_MASTER_SEC_LEVEL_DSP_D_SHIFT      (24U)
/*! DSP_D - DSP Data
 *  0b00..Non-secure and non-privileged Master
 *  0b01..Non-secure and privileged Master
 *  0b10..Secure and non-privileged Master
 *  0b11..Secure and privileged Master
 */
#define SECTRL_MASTER_SEC_LEVEL_DSP_D(x)         (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_LEVEL_DSP_D_SHIFT)) & SECTRL_MASTER_SEC_LEVEL_DSP_D_MASK)

#define SECTRL_MASTER_SEC_LEVEL_DSP_I_MASK       (0xC000000U)
#define SECTRL_MASTER_SEC_LEVEL_DSP_I_SHIFT      (26U)
/*! DSP_I - DSP Instruction
 *  0b00..Non-secure and non-privileged Master
 *  0b01..Non-secure and privileged Master
 *  0b10..Secure and non-privileged Master
 *  0b11..Secure and privileged Master
 */
#define SECTRL_MASTER_SEC_LEVEL_DSP_I(x)         (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_LEVEL_DSP_I_SHIFT)) & SECTRL_MASTER_SEC_LEVEL_DSP_I_MASK)

#define SECTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK (0xC0000000U)
#define SECTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT (30U)
/*! MASTER_SEC_LEVEL_LOCK - Master Security Level Lock
 *  0b00..Reserved
 *  0b01..Lock writing to this register, including these (MASTER_SEC_LEVEL_LOCK) bits
 *  0b10..This register can be written
 *  0b11..Reserved
 */
#define SECTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT)) & SECTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK)
/*! @} */

/*! @name MASTER_SEC_ANTI_POL_REG - Master Secure Level */
/*! @{ */

#define SECTRL_MASTER_SEC_ANTI_POL_REG_DMA0_MASK (0x30U)
#define SECTRL_MASTER_SEC_ANTI_POL_REG_DMA0_SHIFT (4U)
/*! DMA0 - DMA0
 *  0b00..Non-secure and non-privileged Master
 *  0b01..Non-secure and privileged Master
 *  0b10..Secure and non-privileged Master
 *  0b11..Secure and privileged Master
 */
#define SECTRL_MASTER_SEC_ANTI_POL_REG_DMA0(x)   (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_ANTI_POL_REG_DMA0_SHIFT)) & SECTRL_MASTER_SEC_ANTI_POL_REG_DMA0_MASK)

#define SECTRL_MASTER_SEC_ANTI_POL_REG_DMA1_MASK (0xC0U)
#define SECTRL_MASTER_SEC_ANTI_POL_REG_DMA1_SHIFT (6U)
/*! DMA1 - DMA1
 *  0b00..Non-secure and non-privileged Master
 *  0b01..Non-secure and privileged Master
 *  0b10..Secure and non-privileged Master
 *  0b11..Secure and privileged Master
 */
#define SECTRL_MASTER_SEC_ANTI_POL_REG_DMA1(x)   (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_ANTI_POL_REG_DMA1_SHIFT)) & SECTRL_MASTER_SEC_ANTI_POL_REG_DMA1_MASK)

#define SECTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK (0x300U)
#define SECTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT (8U)
/*! USBFSD - USBFS Device
 *  0b00..Non-secure and non-privileged Master
 *  0b01..Non-secure and privileged Master
 *  0b10..Secure and non-privileged Master
 *  0b11..Secure and privileged Master
 */
#define SECTRL_MASTER_SEC_ANTI_POL_REG_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT)) & SECTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK)

#define SECTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK (0xC00U)
#define SECTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT (10U)
/*! USBFSH - USBFS Host
 *  0b00..Non-secure and non-privileged Master
 *  0b01..Non-secure and privileged Master
 *  0b10..Secure and non-privileged Master
 *  0b11..Secure and privileged Master
 */
#define SECTRL_MASTER_SEC_ANTI_POL_REG_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT)) & SECTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK)

#define SECTRL_MASTER_SEC_ANTI_POL_REG_EZH_D_MASK (0x3000U)
#define SECTRL_MASTER_SEC_ANTI_POL_REG_EZH_D_SHIFT (12U)
/*! EZH_D - EZH Data
 *  0b00..Non-secure and non-privileged Master
 *  0b01..Non-secure and privileged Master
 *  0b10..Secure and non-privileged Master
 *  0b11..Secure and privileged Master
 */
#define SECTRL_MASTER_SEC_ANTI_POL_REG_EZH_D(x)  (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_ANTI_POL_REG_EZH_D_SHIFT)) & SECTRL_MASTER_SEC_ANTI_POL_REG_EZH_D_MASK)

#define SECTRL_MASTER_SEC_ANTI_POL_REG_EZH_I_MASK (0xC000U)
#define SECTRL_MASTER_SEC_ANTI_POL_REG_EZH_I_SHIFT (14U)
/*! EZH_I - EZH Instruction
 *  0b00..Non-secure and non-privileged Master
 *  0b01..Non-secure and privileged Master
 *  0b10..Secure and non-privileged Master
 *  0b11..Secure and privileged Master
 */
#define SECTRL_MASTER_SEC_ANTI_POL_REG_EZH_I(x)  (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_ANTI_POL_REG_EZH_I_SHIFT)) & SECTRL_MASTER_SEC_ANTI_POL_REG_EZH_I_MASK)

#define SECTRL_MASTER_SEC_ANTI_POL_REG_MCAN_MASK (0xC0000U)
#define SECTRL_MASTER_SEC_ANTI_POL_REG_MCAN_SHIFT (18U)
/*! MCAN - MCAN
 *  0b00..Non-secure and non-privileged Master
 *  0b01..Non-secure and privileged Master
 *  0b10..Secure and non-privileged Master
 *  0b11..Secure and privileged Master
 */
#define SECTRL_MASTER_SEC_ANTI_POL_REG_MCAN(x)   (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_ANTI_POL_REG_MCAN_SHIFT)) & SECTRL_MASTER_SEC_ANTI_POL_REG_MCAN_MASK)

#define SECTRL_MASTER_SEC_ANTI_POL_REG_POWERQUAD_MASK (0x300000U)
#define SECTRL_MASTER_SEC_ANTI_POL_REG_POWERQUAD_SHIFT (20U)
/*! POWERQUAD - POWERQUAD
 *  0b00..Non-secure and non-privileged Master
 *  0b01..Non-secure and privileged Master
 *  0b10..Secure and non-privileged Master
 *  0b11..Secure and privileged Master
 */
#define SECTRL_MASTER_SEC_ANTI_POL_REG_POWERQUAD(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_ANTI_POL_REG_POWERQUAD_SHIFT)) & SECTRL_MASTER_SEC_ANTI_POL_REG_POWERQUAD_MASK)

#define SECTRL_MASTER_SEC_ANTI_POL_REG_PKC_MASK  (0xC00000U)
#define SECTRL_MASTER_SEC_ANTI_POL_REG_PKC_SHIFT (22U)
/*! PKC - PKC
 *  0b00..Non-secure and non-privileged Master
 *  0b01..Non-secure and privileged Master
 *  0b10..Secure and non-privileged Master
 *  0b11..Secure and privileged Master
 */
#define SECTRL_MASTER_SEC_ANTI_POL_REG_PKC(x)    (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_ANTI_POL_REG_PKC_SHIFT)) & SECTRL_MASTER_SEC_ANTI_POL_REG_PKC_MASK)

#define SECTRL_MASTER_SEC_ANTI_POL_REG_DSP_D_MASK (0x3000000U)
#define SECTRL_MASTER_SEC_ANTI_POL_REG_DSP_D_SHIFT (24U)
/*! DSP_D - DSP Data
 *  0b00..Non-secure and non-privileged Master
 *  0b01..Non-secure and privileged Master
 *  0b10..Secure and non-privileged Master
 *  0b11..Secure and privileged Master
 */
#define SECTRL_MASTER_SEC_ANTI_POL_REG_DSP_D(x)  (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_ANTI_POL_REG_DSP_D_SHIFT)) & SECTRL_MASTER_SEC_ANTI_POL_REG_DSP_D_MASK)

#define SECTRL_MASTER_SEC_ANTI_POL_REG_DSP_I_MASK (0xC000000U)
#define SECTRL_MASTER_SEC_ANTI_POL_REG_DSP_I_SHIFT (26U)
/*! DSP_I - DSP Instruction
 *  0b00..Non-secure and non-privileged Master
 *  0b01..Non-secure and privileged Master
 *  0b10..Secure and non-privileged Master
 *  0b11..Secure and privileged Master
 */
#define SECTRL_MASTER_SEC_ANTI_POL_REG_DSP_I(x)  (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_ANTI_POL_REG_DSP_I_SHIFT)) & SECTRL_MASTER_SEC_ANTI_POL_REG_DSP_I_MASK)

#define SECTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK (0xC0000000U)
#define SECTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT (30U)
/*! MASTER_SEC_LEVEL_ANTIPOL_LOCK - Master Security Level Antipole Lock
 *  0b00..Reserved
 *  0b01..Lock writing to this register, including these (MASTER_SEC_LEVEL_ANTIPOL_LOCK) bits
 *  0b10..This register can be written
 *  0b11..Reserved
 */
#define SECTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT)) & SECTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK)
/*! @} */

/*! @name CM33_LOCK_REGN_CM33_LOCK_REG - Miscellaneous CPU0 Control Signals */
/*! @{ */

#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U)
#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U)
/*! LOCK_NS_VTOR - LOCK_NS_VTOR
 *  0b00..Reserved
 *  0b01..CM33 (CPU0) LOCKNSVTOR is 1
 *  0b10..CM33 (CPU0) LOCKNSVTOR is 0
 *  0b11..Reserved
 */
#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_NS_VTOR_MASK)

#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_NS_MPU_MASK (0xCU)
#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_NS_MPU_SHIFT (2U)
/*! LOCK_NS_MPU - LOCK_NS_MPU
 *  0b00..Reserved
 *  0b01..CM33 (CPU0) LOCK_NS_MPU is 1
 *  0b10..CM33 (CPU0) LOCK_NS_MPU is 0
 *  0b11..Reserved
 */
#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_NS_MPU_SHIFT)) & SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_NS_MPU_MASK)

#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_S_VTAIRCR_MASK (0x30U)
#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_S_VTAIRCR_SHIFT (4U)
/*! LOCK_S_VTAIRCR - LOCK_S_VTAIRCR
 *  0b00..Reserved
 *  0b01..CM33 (CPU0) LOCK_S_VTAIRCR is 1
 *  0b10..CM33 (CPU0) LOCK_S_VTAIRCR is 0
 *  0b11..Reserved
 */
#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_S_VTAIRCR(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_S_VTAIRCR_SHIFT)) & SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_S_VTAIRCR_MASK)

#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_S_MPU_MASK (0xC0U)
#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_S_MPU_SHIFT (6U)
/*! LOCK_S_MPU - LOCK_S_MPU
 *  0b00..Reserved
 *  0b01..CM33 (CPU0) LOCK_S_MPU is 1
 *  0b10..CM33 (CPU0) LOCK_S_MPU is 0
 *  0b11..Reserved
 */
#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_S_MPU(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_S_MPU_SHIFT)) & SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_S_MPU_MASK)

#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_SAU_MASK (0x300U)
#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_SAU_SHIFT (8U)
/*! LOCK_SAU - LOCK_SAU
 *  0b00..Reserved
 *  0b01..CM33 (CPU0) LOCK_SAU is 1
 *  0b10..CM33 (CPU0) LOCK_SAU is 0
 *  0b11..Reserved
 */
#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_SAU(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_SAU_SHIFT)) & SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_LOCK_SAU_MASK)

#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_CM33_LOCK_REG_LOCK_MASK (0xC0000000U)
#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_CM33_LOCK_REG_LOCK_SHIFT (30U)
/*! CM33_LOCK_REG_LOCK - CM33_LOCK_REG_LOCK
 *  0b00..Reserved
 *  0b01..CM33_LOCK_REG_LOCK is 1
 *  0b10..CM33_LOCK_REG_LOCK is 0
 *  0b11..Reserved
 */
#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_CM33_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_CM33_LOCK_REG_LOCK_SHIFT)) & SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_CM33_LOCK_REG_LOCK_MASK)
/*! @} */

/* The count of SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG */
#define SECTRL_CM33_LOCK_REGN_CM33_LOCK_REG_COUNT (3U)

/*! @name MISC_CTRL_DP_REG - Secure Control Duplicate */
/*! @{ */

#define SECTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK  (0x3U)
#define SECTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT (0U)
/*! WRITE_LOCK - Write Lock
 *  0b00..Reserved
 *  0b01..Writes to this register and to the Memory and Peripheral RULE registers are not allowed
 *  0b10..Writes to this register and to the Memory and Peripheral RULE registers are allowed
 *  0b11..Reserved
 */
#define SECTRL_MISC_CTRL_DP_REG_WRITE_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << SECTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT)) & SECTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK)

#define SECTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK (0xCU)
#define SECTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT (2U)
/*! ENABLE_SECURE_CHECKING - Enable Secure Checking
 *  0b00..Reserved
 *  0b01..Enabled (restrictive mode)
 *  0b10..Disabled
 *  0b11..Reserved
 */
#define SECTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT)) & SECTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK)

#define SECTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U)
#define SECTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U)
/*! ENABLE_S_PRIV_CHECK - Enable Secure Privilege Checking
 *  0b00..Reserved
 *  0b01..Enabled (restrictive mode)
 *  0b10..Disabled
 *  0b11..Reserved
 */
#define SECTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & SECTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK)

#define SECTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U)
#define SECTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U)
/*! ENABLE_NS_PRIV_CHECK - Enable Non-Secure Privilege Checking
 *  0b00..Reserved
 *  0b01..Enabled (restrictive mode)
 *  0b10..Disabled
 *  0b11..Reserved
 */
#define SECTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & SECTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK)

#define SECTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U)
#define SECTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U)
/*! DISABLE_VIOLATION_ABORT - Disable Violation Abort
 *  0b00..Reserved
 *  0b01..The violation detected by the secure checker will not cause an abort, but a secure_violation_irq
 *        (interrupt request) will still be asserted and serviced by ISR.
 *  0b10..The violation detected by the secure checker will cause an abort.
 *  0b11..Reserved
 */
#define SECTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & SECTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK)

#define SECTRL_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_MASK (0xC00U)
#define SECTRL_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_SHIFT (10U)
/*! DISABLE_STRICT_MODE - Disable Strict Mode
 *  0b00..AHB master in strict mode
 *  0b01..AHB master in tier mode. Can read and write to memories at same or below level.
 *  0b10..AHB master in strict mode
 *  0b11..AHB master in strict mode
 */
#define SECTRL_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_SHIFT)) & SECTRL_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_MASK)

#define SECTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK (0xC000U)
#define SECTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT (14U)
/*! IDAU_ALL_NS - IDAU All Non-Secure
 *  0b00..Reserved
 *  0b01..IDAU is disabled, which means that all memories are attributed as non-secure memory.
 *  0b10..IDAU is enabled (restrictive mode)
 *  0b11..Reserved
 */
#define SECTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS(x)   (((uint32_t)(((uint32_t)(x)) << SECTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT)) & SECTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK)
/*! @} */

/*! @name MISC_CTRL_REG - Secure Control */
/*! @{ */

#define SECTRL_MISC_CTRL_REG_WRITE_LOCK_MASK     (0x3U)
#define SECTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT    (0U)
/*! WRITE_LOCK - Write Lock
 *  0b00..Reserved
 *  0b01..Writes to this register and to the Memory and Peripheral RULE registers are not allowed
 *  0b10..Writes to this register and to the Memory and Peripheral RULE registers are allowed
 *  0b11..Reserved
 */
#define SECTRL_MISC_CTRL_REG_WRITE_LOCK(x)       (((uint32_t)(((uint32_t)(x)) << SECTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT)) & SECTRL_MISC_CTRL_REG_WRITE_LOCK_MASK)

#define SECTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK (0xCU)
#define SECTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT (2U)
/*! ENABLE_SECURE_CHECKING - Enable Secure Checking
 *  0b00..Reserved
 *  0b01..Enabled (restrictive mode)
 *  0b10..Disabled
 *  0b11..Reserved
 */
#define SECTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT)) & SECTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK)

#define SECTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U)
#define SECTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U)
/*! ENABLE_S_PRIV_CHECK - Enable Secure Privilege Checking
 *  0b00..Reserved
 *  0b01..Enabled (restrictive mode)
 *  0b10..Disabled
 *  0b11..Reserved
 */
#define SECTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & SECTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK)

#define SECTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U)
#define SECTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U)
/*! ENABLE_NS_PRIV_CHECK - Enable Non-Secure Privilege Checking
 *  0b00..Reserved
 *  0b01..Enabled (restrictive mode)
 *  0b10..Disabled
 *  0b11..Reserved
 */
#define SECTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & SECTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK)

#define SECTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U)
#define SECTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U)
/*! DISABLE_VIOLATION_ABORT - Disable Violation Abort
 *  0b00..Reserved
 *  0b01..The violation detected by the secure checker will not cause an abort, but a secure_violation_irq
 *        (interrupt request) will still be asserted and serviced by ISR.
 *  0b10..The violation detected by the secure checker will cause an abort.
 *  0b11..Reserved
 */
#define SECTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & SECTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK)

#define SECTRL_MISC_CTRL_REG_DISABLE_STRICT_MODE_MASK (0xC00U)
#define SECTRL_MISC_CTRL_REG_DISABLE_STRICT_MODE_SHIFT (10U)
/*! DISABLE_STRICT_MODE - Disable Strict Mode
 *  0b00..AHB master in strict mode
 *  0b01..AHB master in tier mode. Can read and write to memories at same or below level.
 *  0b10..AHB master in strict mode
 *  0b11..AHB master in strict mode
 */
#define SECTRL_MISC_CTRL_REG_DISABLE_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SECTRL_MISC_CTRL_REG_DISABLE_STRICT_MODE_SHIFT)) & SECTRL_MISC_CTRL_REG_DISABLE_STRICT_MODE_MASK)

#define SECTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK    (0xC000U)
#define SECTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT   (14U)
/*! IDAU_ALL_NS - IDAU All Non-Secure
 *  0b00..Reserved
 *  0b01..IDAU is disabled, which means that all memories are attributed as non-secure memory.
 *  0b10..IDAU is enabled (restrictive mode)
 *  0b11..Reserved
 */
#define SECTRL_MISC_CTRL_REG_IDAU_ALL_NS(x)      (((uint32_t)(((uint32_t)(x)) << SECTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT)) & SECTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group SECTRL_Register_Masks */


/* SECTRL - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral SECTRL0 base address */
  #define SECTRL0_BASE                             (0x500AC000u)
  /** Peripheral SECTRL0 base address */
  #define SECTRL0_BASE_NS                          (0x400AC000u)
  /** Peripheral SECTRL0 base pointer */
  #define SECTRL0                                  ((SECTRL_Type *)SECTRL0_BASE)
  /** Peripheral SECTRL0 base pointer */
  #define SECTRL0_NS                               ((SECTRL_Type *)SECTRL0_BASE_NS)
  /** Array initializer of SECTRL peripheral base addresses */
  #define SECTRL_BASE_ADDRS                        { SECTRL0_BASE }
  /** Array initializer of SECTRL peripheral base pointers */
  #define SECTRL_BASE_PTRS                         { SECTRL0 }
  /** Array initializer of SECTRL peripheral base addresses */
  #define SECTRL_BASE_ADDRS_NS                     { SECTRL0_BASE_NS }
  /** Array initializer of SECTRL peripheral base pointers */
  #define SECTRL_BASE_PTRS_NS                      { SECTRL0_NS }
#else
  /** Peripheral SECTRL0 base address */
  #define SECTRL0_BASE                             (0x400AC000u)
  /** Peripheral SECTRL0 base pointer */
  #define SECTRL0                                  ((SECTRL_Type *)SECTRL0_BASE)
  /** Array initializer of SECTRL peripheral base addresses */
  #define SECTRL_BASE_ADDRS                        { SECTRL0_BASE }
  /** Array initializer of SECTRL peripheral base pointers */
  #define SECTRL_BASE_PTRS                         { SECTRL0 }
#endif

/*!
 * @}
 */ /* end of group SECTRL_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- SPI Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
 * @{
 */

/** SPI - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[1024];
  __IO uint32_t CFG;                               /**< Configuration Register, offset: 0x400 */
  __IO uint32_t DLY;                               /**< Delay Register, offset: 0x404 */
  __IO uint32_t STAT;                              /**< Status Register, offset: 0x408 */
  __IO uint32_t INTENSET;                          /**< Interrupt Enable Register, offset: 0x40C */
  __O  uint32_t INTENCLR;                          /**< Interrupt Enable Clear Register, offset: 0x410 */
       uint8_t RESERVED_1[16];
  __IO uint32_t DIV;                               /**< Clock Divider Register, offset: 0x424 */
  __I  uint32_t INTSTAT;                           /**< Interrupt Status Register, offset: 0x428 */
       uint8_t RESERVED_2[2516];
  __IO uint32_t FIFOCFG;                           /**< FIFO Configuration Register, offset: 0xE00 */
  __IO uint32_t FIFOSTAT;                          /**< FIFO Status Register, offset: 0xE04 */
  __IO uint32_t FIFOTRIG;                          /**< FIFO Trigger Register, offset: 0xE08 */
       uint8_t RESERVED_3[4];
  __IO uint32_t FIFOINTENSET;                      /**< FIFO Interrupt Enable Register, offset: 0xE10 */
  __IO uint32_t FIFOINTENCLR;                      /**< FIFO Interrupt Enable Clear Register, offset: 0xE14 */
  __I  uint32_t FIFOINTSTAT;                       /**< FIFO Interrupt Status Register, offset: 0xE18 */
       uint8_t RESERVED_4[4];
  __O  uint32_t FIFOWR;                            /**< FIFO Write Data Register, offset: 0xE20 */
       uint8_t RESERVED_5[12];
  __I  uint32_t FIFORD;                            /**< FIFO Read Data Register, offset: 0xE30 */
       uint8_t RESERVED_6[12];
  __I  uint32_t FIFORDNOPOP;                       /**< FIFO Data Read with no FIFO Pop Register, offset: 0xE40 */
       uint8_t RESERVED_7[4];
  __I  uint32_t FIFOSIZE;                          /**< FIFO Size Register, offset: 0xE48 */
  __IO uint32_t FIFORXTIMEOUTCFG;                  /**< FIFO Receive Timeout Configuration, offset: 0xE4C */
  __I  uint32_t FIFORXTIMEOUTCNT;                  /**< FIFO Receive Timeout Counter, offset: 0xE50 */
       uint8_t RESERVED_8[424];
  __I  uint32_t ID;                                /**< Peripheral Identification Register, offset: 0xFFC */
} SPI_Type;

/* ----------------------------------------------------------------------------
   -- SPI Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SPI_Register_Masks SPI Register Masks
 * @{
 */

/*! @name CFG - Configuration Register */
/*! @{ */

#define SPI_CFG_ENABLE_MASK                      (0x1U)
#define SPI_CFG_ENABLE_SHIFT                     (0U)
/*! ENABLE - SPI Enable
 *  0b0..Disabled. The SPI is disabled and the internal state machine and counters are reset.
 *  0b1..Enabled. The SPI is enabled for operation.
 */
#define SPI_CFG_ENABLE(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK)

#define SPI_CFG_MASTER_MASK                      (0x4U)
#define SPI_CFG_MASTER_SHIFT                     (2U)
/*! MASTER - Master Mode Select
 *  0b0..Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs; MISO is an output.
 *  0b1..Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs; MISO is an input.
 */
#define SPI_CFG_MASTER(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK)

#define SPI_CFG_LSBF_MASK                        (0x8U)
#define SPI_CFG_LSBF_SHIFT                       (3U)
/*! LSBF - LSB First Mode Enable
 *  0b0..Standard. Data is transmitted and received in standard MSB-first order.
 *  0b1..Reverse. Data is transmitted and received in reverse order (LSB first).
 */
#define SPI_CFG_LSBF(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK)

#define SPI_CFG_CPHA_MASK                        (0x10U)
#define SPI_CFG_CPHA_SHIFT                       (4U)
/*! CPHA - Clock Phase Select
 *  0b0..Change
 *  0b1..Capture
 */
#define SPI_CFG_CPHA(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK)

#define SPI_CFG_CPOL_MASK                        (0x20U)
#define SPI_CFG_CPOL_SHIFT                       (5U)
/*! CPOL - Clock Polarity Select
 *  0b0..Low. The rest state of the clock (between transfers) is low.
 *  0b1..High. The rest state of the clock (between transfers) is high.
 */
#define SPI_CFG_CPOL(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK)

#define SPI_CFG_LOOP_MASK                        (0x80U)
#define SPI_CFG_LOOP_SHIFT                       (7U)
/*! LOOP - Loopback Mode Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SPI_CFG_LOOP(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK)

#define SPI_CFG_SPOL0_MASK                       (0x100U)
#define SPI_CFG_SPOL0_SHIFT                      (8U)
/*! SPOL0 - SSEL0 Polarity Select
 *  0b0..Low. The SSEL0 pin is active low.
 *  0b1..High. The SSEL0 pin is active high.
 */
#define SPI_CFG_SPOL0(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK)

#define SPI_CFG_SPOL1_MASK                       (0x200U)
#define SPI_CFG_SPOL1_SHIFT                      (9U)
/*! SPOL1 - SSEL1 Polarity Select
 *  0b0..Low. The SSEL1 pin is active low.
 *  0b1..High. The SSEL1 pin is active high.
 */
#define SPI_CFG_SPOL1(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK)

#define SPI_CFG_SPOL2_MASK                       (0x400U)
#define SPI_CFG_SPOL2_SHIFT                      (10U)
/*! SPOL2 - SSEL2 Polarity Select
 *  0b0..Low. The SSEL2 pin is active low.
 *  0b1..High. The SSEL2 pin is active high.
 */
#define SPI_CFG_SPOL2(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK)

#define SPI_CFG_SPOL3_MASK                       (0x800U)
#define SPI_CFG_SPOL3_SHIFT                      (11U)
/*! SPOL3 - SSEL3 Polarity Select
 *  0b0..Low. The SSEL3 pin is active low.
 *  0b1..High. The SSEL3 pin is active high.
 */
#define SPI_CFG_SPOL3(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK)
/*! @} */

/*! @name DLY - Delay Register */
/*! @{ */

#define SPI_DLY_PRE_DELAY_MASK                   (0xFU)
#define SPI_DLY_PRE_DELAY_SHIFT                  (0U)
/*! PRE_DELAY - Pre-Delay
 *  0b0000..No additional time is inserted
 *  0b0001..1 SPI clock time is inserted
 *  0b0010..2 SPI clock times are inserted
 *  0b1111..15 SPI clock times are inserted
 */
#define SPI_DLY_PRE_DELAY(x)                     (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK)

#define SPI_DLY_POST_DELAY_MASK                  (0xF0U)
#define SPI_DLY_POST_DELAY_SHIFT                 (4U)
/*! POST_DELAY - Post-Delay
 *  0b0000..No additional time is inserted
 *  0b0001..1 SPI clock time is inserted
 *  0b0010..2 SPI clock times are inserted
 *  0b1111..15 SPI clock times are inserted
 */
#define SPI_DLY_POST_DELAY(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK)

#define SPI_DLY_FRAME_DELAY_MASK                 (0xF00U)
#define SPI_DLY_FRAME_DELAY_SHIFT                (8U)
/*! FRAME_DELAY - Frame Delay
 *  0b0000..No additional time is inserted
 *  0b0001..1 SPI clock time is inserted
 *  0b0010..2 SPI clock times are inserted
 *  0b1111..15 SPI clock times are inserted
 */
#define SPI_DLY_FRAME_DELAY(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK)

#define SPI_DLY_TRANSFER_DELAY_MASK              (0xF000U)
#define SPI_DLY_TRANSFER_DELAY_SHIFT             (12U)
/*! TRANSFER_DELAY - Transfer Delay
 *  0b0000..The minimum time that SSEL is deasserted is 1 SPI clock time (zero-added time)
 *  0b0001..The minimum time that SSEL is deasserted is 2 SPI clock times
 *  0b0010..The minimum time that SSEL is deasserted is 3 SPI clock times
 *  0b1111..The minimum time that SSEL is deasserted is 16 SPI clock times
 */
#define SPI_DLY_TRANSFER_DELAY(x)                (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK)
/*! @} */

/*! @name STAT - Status Register */
/*! @{ */

#define SPI_STAT_SSA_MASK                        (0x10U)
#define SPI_STAT_SSA_SHIFT                       (4U)
/*! SSA - Slave Select Assert
 */
#define SPI_STAT_SSA(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK)

#define SPI_STAT_SSD_MASK                        (0x20U)
#define SPI_STAT_SSD_SHIFT                       (5U)
/*! SSD - Slave Select Deassert
 */
#define SPI_STAT_SSD(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK)

#define SPI_STAT_STALLED_MASK                    (0x40U)
#define SPI_STAT_STALLED_SHIFT                   (6U)
/*! STALLED - Stalled Status Flag
 */
#define SPI_STAT_STALLED(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK)

#define SPI_STAT_ENDTRANSFER_MASK                (0x80U)
#define SPI_STAT_ENDTRANSFER_SHIFT               (7U)
/*! ENDTRANSFER - End Transfer Control
 */
#define SPI_STAT_ENDTRANSFER(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK)

#define SPI_STAT_MSTIDLE_MASK                    (0x100U)
#define SPI_STAT_MSTIDLE_SHIFT                   (8U)
/*! MSTIDLE - Master Idle Status Flag
 */
#define SPI_STAT_MSTIDLE(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK)
/*! @} */

/*! @name INTENSET - Interrupt Enable Register */
/*! @{ */

#define SPI_INTENSET_SSAEN_MASK                  (0x10U)
#define SPI_INTENSET_SSAEN_SHIFT                 (4U)
/*! SSAEN - Slave Select Assert Interrupt Enable
 *  0b0..Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted.
 *  0b1..Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted.
 */
#define SPI_INTENSET_SSAEN(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK)

#define SPI_INTENSET_SSDEN_MASK                  (0x20U)
#define SPI_INTENSET_SSDEN_SHIFT                 (5U)
/*! SSDEN - Slave Select Deassert Interrupt Enable
 *  0b0..Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted.
 *  0b1..Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted.
 */
#define SPI_INTENSET_SSDEN(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK)

#define SPI_INTENSET_MSTIDLEEN_MASK              (0x100U)
#define SPI_INTENSET_MSTIDLEEN_SHIFT             (8U)
/*! MSTIDLEEN - Master Idle Interrupt Enable
 *  0b0..No interrupt will be generated when the SPI master function is idle.
 *  0b1..An interrupt will be generated when the SPI master function is fully idle.
 */
#define SPI_INTENSET_MSTIDLEEN(x)                (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK)
/*! @} */

/*! @name INTENCLR - Interrupt Enable Clear Register */
/*! @{ */

#define SPI_INTENCLR_SSAEN_MASK                  (0x10U)
#define SPI_INTENCLR_SSAEN_SHIFT                 (4U)
/*! SSAEN - Slave Select Assert Interrupt Enable
 *  0b0..No effect
 *  0b1..Clear the Slave Select Assert Interrupt Enable bit (INTENSET[SSAEN])
 */
#define SPI_INTENCLR_SSAEN(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK)

#define SPI_INTENCLR_SSDEN_MASK                  (0x20U)
#define SPI_INTENCLR_SSDEN_SHIFT                 (5U)
/*! SSDEN - Slave Select Deassert Interrupt Enable
 *  0b0..No effect
 *  0b1..Clear the Slave Select Deassert Interrupt Enable bit (INTENSET[SSDEN])
 */
#define SPI_INTENCLR_SSDEN(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK)

#define SPI_INTENCLR_MSTIDLE_MASK                (0x100U)
#define SPI_INTENCLR_MSTIDLE_SHIFT               (8U)
/*! MSTIDLE - Master Idle Interrupt Enable
 *  0b0..No effect
 *  0b1..Clear the Master Idle Interrupt Enable bit (INTENSET[MSTIDLE])
 */
#define SPI_INTENCLR_MSTIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK)
/*! @} */

/*! @name DIV - Clock Divider Register */
/*! @{ */

#define SPI_DIV_DIVVAL_MASK                      (0xFFFFU)
#define SPI_DIV_DIVVAL_SHIFT                     (0U)
/*! DIVVAL - Rate Divider Value
 */
#define SPI_DIV_DIVVAL(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK)
/*! @} */

/*! @name INTSTAT - Interrupt Status Register */
/*! @{ */

#define SPI_INTSTAT_SSA_MASK                     (0x10U)
#define SPI_INTSTAT_SSA_SHIFT                    (4U)
/*! SSA - Slave Select Assert Interrupt
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SPI_INTSTAT_SSA(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK)

#define SPI_INTSTAT_SSD_MASK                     (0x20U)
#define SPI_INTSTAT_SSD_SHIFT                    (5U)
/*! SSD - Slave Select Deassert Interrupt
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SPI_INTSTAT_SSD(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK)

#define SPI_INTSTAT_MSTIDLE_MASK                 (0x100U)
#define SPI_INTSTAT_MSTIDLE_SHIFT                (8U)
/*! MSTIDLE - Master Idle Status Flag Interrupt
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SPI_INTSTAT_MSTIDLE(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK)
/*! @} */

/*! @name FIFOCFG - FIFO Configuration Register */
/*! @{ */

#define SPI_FIFOCFG_ENABLETX_MASK                (0x1U)
#define SPI_FIFOCFG_ENABLETX_SHIFT               (0U)
/*! ENABLETX - Enable the Transmit FIFO
 *  0b0..The transmit FIFO is not enabled
 *  0b1..The transmit FIFO is enabled
 */
#define SPI_FIFOCFG_ENABLETX(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK)

#define SPI_FIFOCFG_ENABLERX_MASK                (0x2U)
#define SPI_FIFOCFG_ENABLERX_SHIFT               (1U)
/*! ENABLERX - Enable the Receive FIFO
 *  0b0..The receive FIFO is not enabled
 *  0b1..The receive FIFO is enabled
 */
#define SPI_FIFOCFG_ENABLERX(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLERX_SHIFT)) & SPI_FIFOCFG_ENABLERX_MASK)

#define SPI_FIFOCFG_SIZE_MASK                    (0x30U)
#define SPI_FIFOCFG_SIZE_SHIFT                   (4U)
/*! SIZE - FIFO Size Configuration
 *  0b00..FIFO is configured as 16 entries of 8 bits.
 *  0b01..FIFO is configured as 8 entries of 16 bits.
 *  0b10..Not used
 *  0b11..Not used
 */
#define SPI_FIFOCFG_SIZE(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_SIZE_SHIFT)) & SPI_FIFOCFG_SIZE_MASK)

#define SPI_FIFOCFG_DMATX_MASK                   (0x1000U)
#define SPI_FIFOCFG_DMATX_SHIFT                  (12U)
/*! DMATX - DMA Configuration for Transmit
 *  0b0..DMA is not used for the transmit function
 *  0b1..Issues DMA request for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled.
 */
#define SPI_FIFOCFG_DMATX(x)                     (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMATX_SHIFT)) & SPI_FIFOCFG_DMATX_MASK)

#define SPI_FIFOCFG_DMARX_MASK                   (0x2000U)
#define SPI_FIFOCFG_DMARX_SHIFT                  (13U)
/*! DMARX - DMA Configuration for Receive
 *  0b0..DMA is not used for the receive function.
 *  0b1..Issues a DMA request for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled.
 */
#define SPI_FIFOCFG_DMARX(x)                     (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK)

#define SPI_FIFOCFG_WAKETX_MASK                  (0x4000U)
#define SPI_FIFOCFG_WAKETX_SHIFT                 (14U)
/*! WAKETX - Wake-up for Transmit FIFO Level
 *  0b0..Only enabled interrupts will wake up the device form reduced power modes
 *  0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in
 *       FIFOTRIG, even when the TXLVL interrupt is not enabled.
 */
#define SPI_FIFOCFG_WAKETX(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKETX_SHIFT)) & SPI_FIFOCFG_WAKETX_MASK)

#define SPI_FIFOCFG_WAKERX_MASK                  (0x8000U)
#define SPI_FIFOCFG_WAKERX_SHIFT                 (15U)
/*! WAKERX - Wake-up for Receive FIFO Level
 *  0b0..Only enabled interrupts will wake up the device form reduced power modes.
 *  0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by
 *       FIFOTRIG[RXLVL], even when the RXLVL interrupt is not enabled.
 */
#define SPI_FIFOCFG_WAKERX(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKERX_SHIFT)) & SPI_FIFOCFG_WAKERX_MASK)

#define SPI_FIFOCFG_EMPTYTX_MASK                 (0x10000U)
#define SPI_FIFOCFG_EMPTYTX_SHIFT                (16U)
/*! EMPTYTX - Empty Command for the Transmit FIFO
 *  0b0..No effect
 *  0b1..The TX FIFO is emptied
 */
#define SPI_FIFOCFG_EMPTYTX(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYTX_SHIFT)) & SPI_FIFOCFG_EMPTYTX_MASK)

#define SPI_FIFOCFG_EMPTYRX_MASK                 (0x20000U)
#define SPI_FIFOCFG_EMPTYRX_SHIFT                (17U)
/*! EMPTYRX - Empty Command for the Receive FIFO
 *  0b0..No effect
 *  0b1..The RX FIFO is emptied
 */
#define SPI_FIFOCFG_EMPTYRX(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK)

#define SPI_FIFOCFG_POPDBG_MASK                  (0x40000U)
#define SPI_FIFOCFG_POPDBG_SHIFT                 (18U)
/*! POPDBG - Pop FIFO for Debug Reads
 *  0b0..Debug reads of the FIFO do not pop the FIFO
 *  0b1..A debug read will cause the FIFO to pop
 */
#define SPI_FIFOCFG_POPDBG(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_POPDBG_SHIFT)) & SPI_FIFOCFG_POPDBG_MASK)
/*! @} */

/*! @name FIFOSTAT - FIFO Status Register */
/*! @{ */

#define SPI_FIFOSTAT_TXERR_MASK                  (0x1U)
#define SPI_FIFOSTAT_TXERR_SHIFT                 (0U)
/*! TXERR - TX FIFO Error
 *  0b0..A transmit FIFO error has not occurred.
 *  0b1..A transmit FIFO error has occurred. This error could be an overflow caused by pushing data into a full
 *       FIFO, or by an underflow if the FIFO is empty when data is needed.
 */
#define SPI_FIFOSTAT_TXERR(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK)

#define SPI_FIFOSTAT_RXERR_MASK                  (0x2U)
#define SPI_FIFOSTAT_RXERR_SHIFT                 (1U)
/*! RXERR - RX FIFO Error
 *  0b0..A receive FIFO overflow has not occurred
 *  0b1..A receive FIFO overflow has occurred, caused by software or DMA not emptying the FIFO fast enough
 */
#define SPI_FIFOSTAT_RXERR(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXERR_SHIFT)) & SPI_FIFOSTAT_RXERR_MASK)

#define SPI_FIFOSTAT_PERINT_MASK                 (0x8U)
#define SPI_FIFOSTAT_PERINT_SHIFT                (3U)
/*! PERINT - Peripheral Interrupt
 *  0b0..The peripheral function has not asserted an interrupt
 *  0b1..Indicates that the peripheral function has asserted an interrupt. More information can be found by
 *       reading the peripheral's status register (STAT).
 */
#define SPI_FIFOSTAT_PERINT(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_PERINT_SHIFT)) & SPI_FIFOSTAT_PERINT_MASK)

#define SPI_FIFOSTAT_TXEMPTY_MASK                (0x10U)
#define SPI_FIFOSTAT_TXEMPTY_SHIFT               (4U)
/*! TXEMPTY - Transmit FIFO Empty
 *  0b0..The transmit FIFO is not empty
 *  0b1..The transmit FIFO is empty, although the peripheral may still be processing the last piece of data.
 */
#define SPI_FIFOSTAT_TXEMPTY(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXEMPTY_SHIFT)) & SPI_FIFOSTAT_TXEMPTY_MASK)

#define SPI_FIFOSTAT_TXNOTFULL_MASK              (0x20U)
#define SPI_FIFOSTAT_TXNOTFULL_SHIFT             (5U)
/*! TXNOTFULL - Transmit FIFO is Not Full
 *  0b0..The transmit FIFO is full and another write would cause it to overflow
 *  0b1..The transmit FIFO is not full, so more data can be written
 */
#define SPI_FIFOSTAT_TXNOTFULL(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXNOTFULL_SHIFT)) & SPI_FIFOSTAT_TXNOTFULL_MASK)

#define SPI_FIFOSTAT_RXNOTEMPTY_MASK             (0x40U)
#define SPI_FIFOSTAT_RXNOTEMPTY_SHIFT            (6U)
/*! RXNOTEMPTY - Receive FIFO is Not Empty
 *  0b0..When 0, the receive FIFO is empty
 *  0b1..When 1, the receive FIFO is not empty, so data can be read
 */
#define SPI_FIFOSTAT_RXNOTEMPTY(x)               (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXNOTEMPTY_SHIFT)) & SPI_FIFOSTAT_RXNOTEMPTY_MASK)

#define SPI_FIFOSTAT_RXFULL_MASK                 (0x80U)
#define SPI_FIFOSTAT_RXFULL_SHIFT                (7U)
/*! RXFULL - Receive FIFO is Full
 *  0b0..The receive FIFO is not full
 *  0b1..The receive FIFO is full. To prevent the peripheral from causing an overflow, data should be read out.
 */
#define SPI_FIFOSTAT_RXFULL(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXFULL_SHIFT)) & SPI_FIFOSTAT_RXFULL_MASK)

#define SPI_FIFOSTAT_TXLVL_MASK                  (0x1F00U)
#define SPI_FIFOSTAT_TXLVL_SHIFT                 (8U)
/*! TXLVL - Transmit FIFO Current Level
 */
#define SPI_FIFOSTAT_TXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXLVL_SHIFT)) & SPI_FIFOSTAT_TXLVL_MASK)

#define SPI_FIFOSTAT_RXLVL_MASK                  (0x1F0000U)
#define SPI_FIFOSTAT_RXLVL_SHIFT                 (16U)
/*! RXLVL - Receive FIFO Current Level
 */
#define SPI_FIFOSTAT_RXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK)

#define SPI_FIFOSTAT_RXTIMEOUT_MASK              (0x1000000U)
#define SPI_FIFOSTAT_RXTIMEOUT_SHIFT             (24U)
/*! RXTIMEOUT - Receive FIFO Timeout
 *  0b0..RX FIFO on
 *  0b1..RX FIFO has timed out, based on the timeout configuration in the FIFORXTIMEOUTCFG register.
 */
#define SPI_FIFOSTAT_RXTIMEOUT(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXTIMEOUT_SHIFT)) & SPI_FIFOSTAT_RXTIMEOUT_MASK)
/*! @} */

/*! @name FIFOTRIG - FIFO Trigger Register */
/*! @{ */

#define SPI_FIFOTRIG_TXLVLENA_MASK               (0x1U)
#define SPI_FIFOTRIG_TXLVLENA_SHIFT              (0U)
/*! TXLVLENA - Transmit FIFO Level Trigger Enable
 *  0b0..Transmit FIFO level does not generate a FIFO level trigger
 *  0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the FIFOTRIG[TXLVL] field.
 */
#define SPI_FIFOTRIG_TXLVLENA(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK)

#define SPI_FIFOTRIG_RXLVLENA_MASK               (0x2U)
#define SPI_FIFOTRIG_RXLVLENA_SHIFT              (1U)
/*! RXLVLENA - Receive FIFO Level Trigger Enable
 *  0b0..Receive FIFO level does not generate a FIFO level trigger
 *  0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the FIFOTRIG[RXLVL] field.
 */
#define SPI_FIFOTRIG_RXLVLENA(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVLENA_SHIFT)) & SPI_FIFOTRIG_RXLVLENA_MASK)

#define SPI_FIFOTRIG_TXLVL_MASK                  (0xF00U)
#define SPI_FIFOTRIG_TXLVL_SHIFT                 (8U)
/*! TXLVL - Transmit FIFO Level Trigger Point
 *  0b0000..Trigger when the TX FIFO becomes empty
 *  0b0001..Trigger when the TX FIFO level decreases to 1 entry
 *  0b1111..Trigger when the TX FIFO level decreases to 15 entries (is no longer full)
 */
#define SPI_FIFOTRIG_TXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVL_SHIFT)) & SPI_FIFOTRIG_TXLVL_MASK)

#define SPI_FIFOTRIG_RXLVL_MASK                  (0xF0000U)
#define SPI_FIFOTRIG_RXLVL_SHIFT                 (16U)
/*! RXLVL - Receive FIFO Level Trigger Point
 *  0b0000..Trigger when the RX FIFO has received 1 entry (is no longer empty)
 *  0b0001..Trigger when the RX FIFO has received 2 entries
 *  0b1111..Trigger when the RX FIFO has received 16 entries (has become full)
 */
#define SPI_FIFOTRIG_RXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK)
/*! @} */

/*! @name FIFOINTENSET - FIFO Interrupt Enable Register */
/*! @{ */

#define SPI_FIFOINTENSET_TXERR_MASK              (0x1U)
#define SPI_FIFOINTENSET_TXERR_SHIFT             (0U)
/*! TXERR - TX Error Interrupt Enable
 *  0b0..No interrupt will be generated for a transmit error
 *  0b1..An interrupt will be generated when a transmit error occurs
 */
#define SPI_FIFOINTENSET_TXERR(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK)

#define SPI_FIFOINTENSET_RXERR_MASK              (0x2U)
#define SPI_FIFOINTENSET_RXERR_SHIFT             (1U)
/*! RXERR - Receive Error Interrupt Enable
 *  0b0..No interrupt will be generated for a receive error
 *  0b1..An interrupt will be generated when a receive error occurs
 */
#define SPI_FIFOINTENSET_RXERR(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXERR_SHIFT)) & SPI_FIFOINTENSET_RXERR_MASK)

#define SPI_FIFOINTENSET_TXLVL_MASK              (0x4U)
#define SPI_FIFOINTENSET_TXLVL_SHIFT             (2U)
/*! TXLVL - Transmit FIFO Level Interrupt Enable
 *  0b0..No interrupt will be generated based on the TX FIFO level
 *  0b1..If FIFOTRIG[TXLVLENA]=1, then an interrupt will be generated when the TX FIFO level decreases to the level specified by FIFOTRIG[TXLVL]
 */
#define SPI_FIFOINTENSET_TXLVL(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXLVL_SHIFT)) & SPI_FIFOINTENSET_TXLVL_MASK)

#define SPI_FIFOINTENSET_RXLVL_MASK              (0x8U)
#define SPI_FIFOINTENSET_RXLVL_SHIFT             (3U)
/*! RXLVL - Receive FIFO Level Interrupt Enable
 *  0b0..No interrupt will be generated based on the RX FIFO level
 *  0b1..If FIFOTRIG[RXLVLENA]=1, then an interrupt will be generated when the RX FIFO level increases to the level specified by FIFOTRIG[RXLVL]
 */
#define SPI_FIFOINTENSET_RXLVL(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXLVL_SHIFT)) & SPI_FIFOINTENSET_RXLVL_MASK)

#define SPI_FIFOINTENSET_RXTIMEOUT_MASK          (0x1000000U)
#define SPI_FIFOINTENSET_RXTIMEOUT_SHIFT         (24U)
/*! RXTIMEOUT - Receive Timeout
 *  0b0..No RX interrupt will be generated.
 *  0b1..Asserts RX interrupt if RX FIFO Timeout event occurs.
 */
#define SPI_FIFOINTENSET_RXTIMEOUT(x)            (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXTIMEOUT_SHIFT)) & SPI_FIFOINTENSET_RXTIMEOUT_MASK)
/*! @} */

/*! @name FIFOINTENCLR - FIFO Interrupt Enable Clear Register */
/*! @{ */

#define SPI_FIFOINTENCLR_TXERR_MASK              (0x1U)
#define SPI_FIFOINTENCLR_TXERR_SHIFT             (0U)
/*! TXERR - TX Error Interrupt Enable
 *  0b0..No effect
 *  0b1..Clear the TX Error Interrupt Enable bit FIFOINTENSET[TXERR]
 */
#define SPI_FIFOINTENCLR_TXERR(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK)

#define SPI_FIFOINTENCLR_RXERR_MASK              (0x2U)
#define SPI_FIFOINTENCLR_RXERR_SHIFT             (1U)
/*! RXERR - Receive Error Interrupt Enable
 *  0b0..No effect
 *  0b1..Clear the Receive Error Interrupt Enable bit FIFOINTENSET[RXERR]
 */
#define SPI_FIFOINTENCLR_RXERR(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXERR_SHIFT)) & SPI_FIFOINTENCLR_RXERR_MASK)

#define SPI_FIFOINTENCLR_TXLVL_MASK              (0x4U)
#define SPI_FIFOINTENCLR_TXLVL_SHIFT             (2U)
/*! TXLVL - Transmit FIFO Level Interrupt Enable
 *  0b0..No effect
 *  0b1..Clear the Transmit FIFO Level Interrupt Enable bit FIFOINTENSET[TXLVL]
 */
#define SPI_FIFOINTENCLR_TXLVL(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXLVL_SHIFT)) & SPI_FIFOINTENCLR_TXLVL_MASK)

#define SPI_FIFOINTENCLR_RXLVL_MASK              (0x8U)
#define SPI_FIFOINTENCLR_RXLVL_SHIFT             (3U)
/*! RXLVL - Receive FIFO Level Interrupt Enable
 *  0b0..No effect
 *  0b1..Clear the Receive FIFO Level Interrupt Enable bit FIFOINTENSET[RXLVL]
 */
#define SPI_FIFOINTENCLR_RXLVL(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK)

#define SPI_FIFOINTENCLR_RXTIMEOUT_MASK          (0x1000000U)
#define SPI_FIFOINTENCLR_RXTIMEOUT_SHIFT         (24U)
/*! RXTIMEOUT - Receive Timeout
 *  0b0..No effect
 *  0b1..Clear the interrupt
 */
#define SPI_FIFOINTENCLR_RXTIMEOUT(x)            (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXTIMEOUT_SHIFT)) & SPI_FIFOINTENCLR_RXTIMEOUT_MASK)
/*! @} */

/*! @name FIFOINTSTAT - FIFO Interrupt Status Register */
/*! @{ */

#define SPI_FIFOINTSTAT_TXERR_MASK               (0x1U)
#define SPI_FIFOINTSTAT_TXERR_SHIFT              (0U)
/*! TXERR - TX FIFO Error Interrupt Status
 *  0b0..Not pending
 *  0b1..Pending
 */
#define SPI_FIFOINTSTAT_TXERR(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK)

#define SPI_FIFOINTSTAT_RXERR_MASK               (0x2U)
#define SPI_FIFOINTSTAT_RXERR_SHIFT              (1U)
/*! RXERR - RX FIFO Error Interrupt Status
 *  0b0..Not pending
 *  0b1..Pending
 */
#define SPI_FIFOINTSTAT_RXERR(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXERR_SHIFT)) & SPI_FIFOINTSTAT_RXERR_MASK)

#define SPI_FIFOINTSTAT_TXLVL_MASK               (0x4U)
#define SPI_FIFOINTSTAT_TXLVL_SHIFT              (2U)
/*! TXLVL - Transmit FIFO Level Interrupt Status
 *  0b0..Not pending
 *  0b1..Pending
 */
#define SPI_FIFOINTSTAT_TXLVL(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXLVL_SHIFT)) & SPI_FIFOINTSTAT_TXLVL_MASK)

#define SPI_FIFOINTSTAT_RXLVL_MASK               (0x8U)
#define SPI_FIFOINTSTAT_RXLVL_SHIFT              (3U)
/*! RXLVL - Receive FIFO Level Interrupt Status
 *  0b0..Not pending
 *  0b1..Pending
 */
#define SPI_FIFOINTSTAT_RXLVL(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXLVL_SHIFT)) & SPI_FIFOINTSTAT_RXLVL_MASK)

#define SPI_FIFOINTSTAT_PERINT_MASK              (0x10U)
#define SPI_FIFOINTSTAT_PERINT_SHIFT             (4U)
/*! PERINT - Peripheral Interrupt Status
 *  0b0..Not pending
 *  0b1..Pending
 */
#define SPI_FIFOINTSTAT_PERINT(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK)

#define SPI_FIFOINTSTAT_RXTIMEOUT_MASK           (0x1000000U)
#define SPI_FIFOINTSTAT_RXTIMEOUT_SHIFT          (24U)
/*! RXTIMEOUT - Receive Timeout Status
 *  0b0..Not pending
 *  0b1..Pending
 */
#define SPI_FIFOINTSTAT_RXTIMEOUT(x)             (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXTIMEOUT_SHIFT)) & SPI_FIFOINTSTAT_RXTIMEOUT_MASK)
/*! @} */

/*! @name FIFOWR - FIFO Write Data Register */
/*! @{ */

#define SPI_FIFOWR_TXDATA_MASK                   (0xFFFFU)
#define SPI_FIFOWR_TXDATA_SHIFT                  (0U)
/*! TXDATA - Transmit Data to the FIFO
 */
#define SPI_FIFOWR_TXDATA(x)                     (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK)

#define SPI_FIFOWR_TXSSEL0_N_MASK                (0x10000U)
#define SPI_FIFOWR_TXSSEL0_N_SHIFT               (16U)
/*! TXSSEL0_N - Transmit Slave Select 0
 *  0b0..SSEL0 is asserted
 *  0b1..SSEL0 is not asserted
 */
#define SPI_FIFOWR_TXSSEL0_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL0_N_SHIFT)) & SPI_FIFOWR_TXSSEL0_N_MASK)

#define SPI_FIFOWR_TXSSEL1_N_MASK                (0x20000U)
#define SPI_FIFOWR_TXSSEL1_N_SHIFT               (17U)
/*! TXSSEL1_N - Transmit Slave Select 1
 *  0b0..SSEL1 is asserted
 *  0b1..SSEL1 is not asserted
 */
#define SPI_FIFOWR_TXSSEL1_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL1_N_SHIFT)) & SPI_FIFOWR_TXSSEL1_N_MASK)

#define SPI_FIFOWR_TXSSEL2_N_MASK                (0x40000U)
#define SPI_FIFOWR_TXSSEL2_N_SHIFT               (18U)
/*! TXSSEL2_N - Transmit Slave Select 2
 *  0b0..SSEL2 is asserted
 *  0b1..SSEL2 is not asserted
 */
#define SPI_FIFOWR_TXSSEL2_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK)

#define SPI_FIFOWR_TXSSEL3_N_MASK                (0x80000U)
#define SPI_FIFOWR_TXSSEL3_N_SHIFT               (19U)
/*! TXSSEL3_N - Transmit Slave Select 3
 *  0b0..SSEL3 is asserted
 *  0b1..SSEL3 is not asserted
 */
#define SPI_FIFOWR_TXSSEL3_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK)

#define SPI_FIFOWR_EOT_MASK                      (0x100000U)
#define SPI_FIFOWR_EOT_SHIFT                     (20U)
/*! EOT - End of Transfer
 *  0b0..SSEL is not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data.
 *  0b1..SSEL is deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data.
 */
#define SPI_FIFOWR_EOT(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOT_SHIFT)) & SPI_FIFOWR_EOT_MASK)

#define SPI_FIFOWR_EOF_MASK                      (0x200000U)
#define SPI_FIFOWR_EOF_SHIFT                     (21U)
/*! EOF - End of Frame
 *  0b0..Data not EOF. This piece of data transmitted is not treated as the end of a frame.
 *  0b1..Data EOF. This piece of data is treated as the end of a frame, causing the Frame_delay time to be
 *       inserted before subsequent data is transmitted.
 */
#define SPI_FIFOWR_EOF(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOF_SHIFT)) & SPI_FIFOWR_EOF_MASK)

#define SPI_FIFOWR_RXIGNORE_MASK                 (0x400000U)
#define SPI_FIFOWR_RXIGNORE_SHIFT                (22U)
/*! RXIGNORE - Receive Ignore
 *  0b0..Read received data. Received data must be read, to allow transmission to proceed. SPI transmit will halt
 *       when the receive data FIFO is full. In slave mode, an overrun error will occur if received data is not
 *       read before new data is received.
 *  0b1..Ignore received data. Received data is ignored, allowing transmission without reading unneeded received
 *       data. No receiver flags are generated.
 */
#define SPI_FIFOWR_RXIGNORE(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_RXIGNORE_SHIFT)) & SPI_FIFOWR_RXIGNORE_MASK)

#define SPI_FIFOWR_TXIGNORE_MASK                 (0x800000U)
#define SPI_FIFOWR_TXIGNORE_SHIFT                (23U)
/*! TXIGNORE - Transmit Ignore
 *  0b0..Write transmit data
 *  0b1..Ignore transmit data
 */
#define SPI_FIFOWR_TXIGNORE(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXIGNORE_SHIFT)) & SPI_FIFOWR_TXIGNORE_MASK)

#define SPI_FIFOWR_LEN_MASK                      (0xF000000U)
#define SPI_FIFOWR_LEN_SHIFT                     (24U)
/*! LEN - Data Length
 *  0b0000..Reserved
 *  0b0001..Reserved
 *  0b0010..Reserved
 *  0b0011..Data transfer is 4 bits in length
 *  0b0100..Data transfer is 5 bits in length
 *  0b1111..Data transfer is 16 bits in length
 */
#define SPI_FIFOWR_LEN(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK)
/*! @} */

/*! @name FIFORD - FIFO Read Data Register */
/*! @{ */

#define SPI_FIFORD_RXDATA_MASK                   (0xFFFFU)
#define SPI_FIFORD_RXDATA_SHIFT                  (0U)
/*! RXDATA - Received Data from the FIFO
 */
#define SPI_FIFORD_RXDATA(x)                     (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK)

#define SPI_FIFORD_RXSSEL0_N_MASK                (0x10000U)
#define SPI_FIFORD_RXSSEL0_N_SHIFT               (16U)
/*! RXSSEL0_N - Slave Select 0 for Receive
 *  0b0..Slave Select 0 is active
 *  0b1..Slave Select 0 is not active
 */
#define SPI_FIFORD_RXSSEL0_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL0_N_SHIFT)) & SPI_FIFORD_RXSSEL0_N_MASK)

#define SPI_FIFORD_RXSSEL1_N_MASK                (0x20000U)
#define SPI_FIFORD_RXSSEL1_N_SHIFT               (17U)
/*! RXSSEL1_N - Slave Select 1 for Receive
 *  0b0..Slave Select 1 is active
 *  0b1..Slave Select 1 is not active
 */
#define SPI_FIFORD_RXSSEL1_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL1_N_SHIFT)) & SPI_FIFORD_RXSSEL1_N_MASK)

#define SPI_FIFORD_RXSSEL2_N_MASK                (0x40000U)
#define SPI_FIFORD_RXSSEL2_N_SHIFT               (18U)
/*! RXSSEL2_N - Slave Select 2 for Receive
 *  0b0..Slave Select 2 is active
 *  0b1..Slave Select 2 is not active
 */
#define SPI_FIFORD_RXSSEL2_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK)

#define SPI_FIFORD_RXSSEL3_N_MASK                (0x80000U)
#define SPI_FIFORD_RXSSEL3_N_SHIFT               (19U)
/*! RXSSEL3_N - Slave Select 3 for Receive
 *  0b0..Slave Select 3 is active
 *  0b1..Slave Select 3 is not active
 */
#define SPI_FIFORD_RXSSEL3_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK)

#define SPI_FIFORD_SOT_MASK                      (0x100000U)
#define SPI_FIFORD_SOT_SHIFT                     (20U)
/*! SOT - Start of Transfer Flag
 *  0b0..This is not the 1st data after the SSELs went from deasserted to asserted
 *  0b1..This is the 1st data after the SSELs went from deasserted to asserted (i.e., any previous transfer has
 *       ended). This information can be used to identify the 1st piece of data in cases where the transfer length is
 *       greater than 16 bits.
 */
#define SPI_FIFORD_SOT(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK)
/*! @} */

/*! @name FIFORDNOPOP - FIFO Data Read with no FIFO Pop Register */
/*! @{ */

#define SPI_FIFORDNOPOP_RXDATA_MASK              (0xFFFFU)
#define SPI_FIFORDNOPOP_RXDATA_SHIFT             (0U)
/*! RXDATA - Received Data from the FIFO
 */
#define SPI_FIFORDNOPOP_RXDATA(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK)

#define SPI_FIFORDNOPOP_RXSSEL0_N_MASK           (0x10000U)
#define SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT          (16U)
/*! RXSSEL0_N - Slave Select 0 for Receive
 *  0b0..Not selected
 *  0b1..Selected
 */
#define SPI_FIFORDNOPOP_RXSSEL0_N(x)             (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL0_N_MASK)

#define SPI_FIFORDNOPOP_RXSSEL1_N_MASK           (0x20000U)
#define SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT          (17U)
/*! RXSSEL1_N - Slave Select 1 for Receive
 *  0b0..Not selected
 *  0b1..Selected
 */
#define SPI_FIFORDNOPOP_RXSSEL1_N(x)             (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL1_N_MASK)

#define SPI_FIFORDNOPOP_RXSSEL2_N_MASK           (0x40000U)
#define SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT          (18U)
/*! RXSSEL2_N - Slave Select 2 for Receive
 *  0b0..Not selected
 *  0b1..Selected
 */
#define SPI_FIFORDNOPOP_RXSSEL2_N(x)             (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK)

#define SPI_FIFORDNOPOP_RXSSEL3_N_MASK           (0x80000U)
#define SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT          (19U)
/*! RXSSEL3_N - Slave Select 3 for Receive
 *  0b0..Not selected
 *  0b1..Selected
 */
#define SPI_FIFORDNOPOP_RXSSEL3_N(x)             (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK)

#define SPI_FIFORDNOPOP_SOT_MASK                 (0x100000U)
#define SPI_FIFORDNOPOP_SOT_SHIFT                (20U)
/*! SOT - Start of Transfer Flag
 *  0b0..Not active
 *  0b1..Active
 */
#define SPI_FIFORDNOPOP_SOT(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK)
/*! @} */

/*! @name FIFOSIZE - FIFO Size Register */
/*! @{ */

#define SPI_FIFOSIZE_FIFOSIZE_MASK               (0x1FU)
#define SPI_FIFOSIZE_FIFOSIZE_SHIFT              (0U)
/*! FIFOSIZE - FIFO Size
 */
#define SPI_FIFOSIZE_FIFOSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSIZE_FIFOSIZE_SHIFT)) & SPI_FIFOSIZE_FIFOSIZE_MASK)
/*! @} */

/*! @name FIFORXTIMEOUTCFG - FIFO Receive Timeout Configuration */
/*! @{ */

#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER_MASK (0xFFU)
#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER_SHIFT (0U)
/*! RXTIMEOUT_PRESCALER - Receive Timeout Counter Clock Prescaler
 */
#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER_SHIFT)) & SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER_MASK)

#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE_MASK (0xFFFF00U)
#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE_SHIFT (8U)
/*! RXTIMEOUT_VALUE - Receive Timeout Value
 */
#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE(x)  (((uint32_t)(((uint32_t)(x)) << SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE_SHIFT)) & SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE_MASK)

#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_EN_MASK   (0x1000000U)
#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_EN_SHIFT  (24U)
/*! RXTIMEOUT_EN - Receive Timeout Enable
 *  0b0..Disable RX FIFO timeout
 *  0b1..Enable RX FIFO timeout
 */
#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_EN(x)     (((uint32_t)(((uint32_t)(x)) << SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_EN_SHIFT)) & SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_EN_MASK)

#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_COW_MASK  (0x2000000U)
#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_COW_SHIFT (25U)
/*! RXTIMEOUT_COW - Receive Timeout Continue On Write
 *  0b0..RX FIFO timeout counter is reset every time data is transferred from the peripheral into the RX FIFO.
 *  0b1..RX FIFO timeout counter is not reset every time data is transferred from the peripheral into the RX FIFO.
 */
#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_COW(x)    (((uint32_t)(((uint32_t)(x)) << SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_COW_SHIFT)) & SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_COW_MASK)

#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_COE_MASK  (0x4000000U)
#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_COE_SHIFT (26U)
/*! RXTIMEOUT_COE - Receive Timeout Continue On Empty
 *  0b0..RX FIFO timeout counter is reset when the RX FIFO becomes empty.
 *  0b1..RX FIFO timeout counter is not reset when the RX FIFO becomes empty.
 */
#define SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_COE(x)    (((uint32_t)(((uint32_t)(x)) << SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_COE_SHIFT)) & SPI_FIFORXTIMEOUTCFG_RXTIMEOUT_COE_MASK)
/*! @} */

/*! @name FIFORXTIMEOUTCNT - FIFO Receive Timeout Counter */
/*! @{ */

#define SPI_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT_MASK  (0xFFFFU)
#define SPI_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT_SHIFT (0U)
/*! RXTIMEOUT_CNT - Current RX FIFO timeout counter value
 */
#define SPI_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT(x)    (((uint32_t)(((uint32_t)(x)) << SPI_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT_SHIFT)) & SPI_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT_MASK)
/*! @} */

/*! @name ID - Peripheral Identification Register */
/*! @{ */

#define SPI_ID_APERTURE_MASK                     (0xFFU)
#define SPI_ID_APERTURE_SHIFT                    (0U)
/*! APERTURE - Aperture
 */
#define SPI_ID_APERTURE(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_ID_APERTURE_SHIFT)) & SPI_ID_APERTURE_MASK)

#define SPI_ID_MINOR_REV_MASK                    (0xF00U)
#define SPI_ID_MINOR_REV_SHIFT                   (8U)
/*! MINOR_REV - Minor revision of module implementation
 */
#define SPI_ID_MINOR_REV(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_ID_MINOR_REV_SHIFT)) & SPI_ID_MINOR_REV_MASK)

#define SPI_ID_MAJOR_REV_MASK                    (0xF000U)
#define SPI_ID_MAJOR_REV_SHIFT                   (12U)
/*! MAJOR_REV - Major revision of module implementation
 */
#define SPI_ID_MAJOR_REV(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_ID_MAJOR_REV_SHIFT)) & SPI_ID_MAJOR_REV_MASK)

#define SPI_ID_ID_MASK                           (0xFFFF0000U)
#define SPI_ID_ID_SHIFT                          (16U)
/*! ID - Module identifier for the selected function
 */
#define SPI_ID_ID(x)                             (((uint32_t)(((uint32_t)(x)) << SPI_ID_ID_SHIFT)) & SPI_ID_ID_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group SPI_Register_Masks */


/* SPI - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral SPI0 base address */
  #define SPI0_BASE                                (0x50086000u)
  /** Peripheral SPI0 base address */
  #define SPI0_BASE_NS                             (0x40086000u)
  /** Peripheral SPI0 base pointer */
  #define SPI0                                     ((SPI_Type *)SPI0_BASE)
  /** Peripheral SPI0 base pointer */
  #define SPI0_NS                                  ((SPI_Type *)SPI0_BASE_NS)
  /** Peripheral SPI1 base address */
  #define SPI1_BASE                                (0x50087000u)
  /** Peripheral SPI1 base address */
  #define SPI1_BASE_NS                             (0x40087000u)
  /** Peripheral SPI1 base pointer */
  #define SPI1                                     ((SPI_Type *)SPI1_BASE)
  /** Peripheral SPI1 base pointer */
  #define SPI1_NS                                  ((SPI_Type *)SPI1_BASE_NS)
  /** Peripheral SPI2 base address */
  #define SPI2_BASE                                (0x50088000u)
  /** Peripheral SPI2 base address */
  #define SPI2_BASE_NS                             (0x40088000u)
  /** Peripheral SPI2 base pointer */
  #define SPI2                                     ((SPI_Type *)SPI2_BASE)
  /** Peripheral SPI2 base pointer */
  #define SPI2_NS                                  ((SPI_Type *)SPI2_BASE_NS)
  /** Peripheral SPI3 base address */
  #define SPI3_BASE                                (0x50089000u)
  /** Peripheral SPI3 base address */
  #define SPI3_BASE_NS                             (0x40089000u)
  /** Peripheral SPI3 base pointer */
  #define SPI3                                     ((SPI_Type *)SPI3_BASE)
  /** Peripheral SPI3 base pointer */
  #define SPI3_NS                                  ((SPI_Type *)SPI3_BASE_NS)
  /** Peripheral SPI4 base address */
  #define SPI4_BASE                                (0x5008A000u)
  /** Peripheral SPI4 base address */
  #define SPI4_BASE_NS                             (0x4008A000u)
  /** Peripheral SPI4 base pointer */
  #define SPI4                                     ((SPI_Type *)SPI4_BASE)
  /** Peripheral SPI4 base pointer */
  #define SPI4_NS                                  ((SPI_Type *)SPI4_BASE_NS)
  /** Peripheral SPI5 base address */
  #define SPI5_BASE                                (0x50096000u)
  /** Peripheral SPI5 base address */
  #define SPI5_BASE_NS                             (0x40096000u)
  /** Peripheral SPI5 base pointer */
  #define SPI5                                     ((SPI_Type *)SPI5_BASE)
  /** Peripheral SPI5 base pointer */
  #define SPI5_NS                                  ((SPI_Type *)SPI5_BASE_NS)
  /** Peripheral SPI6 base address */
  #define SPI6_BASE                                (0x50097000u)
  /** Peripheral SPI6 base address */
  #define SPI6_BASE_NS                             (0x40097000u)
  /** Peripheral SPI6 base pointer */
  #define SPI6                                     ((SPI_Type *)SPI6_BASE)
  /** Peripheral SPI6 base pointer */
  #define SPI6_NS                                  ((SPI_Type *)SPI6_BASE_NS)
  /** Peripheral SPI7 base address */
  #define SPI7_BASE                                (0x50098000u)
  /** Peripheral SPI7 base address */
  #define SPI7_BASE_NS                             (0x40098000u)
  /** Peripheral SPI7 base pointer */
  #define SPI7                                     ((SPI_Type *)SPI7_BASE)
  /** Peripheral SPI7 base pointer */
  #define SPI7_NS                                  ((SPI_Type *)SPI7_BASE_NS)
  /** Peripheral SPI8 base address */
  #define SPI8_BASE                                (0x5009F000u)
  /** Peripheral SPI8 base address */
  #define SPI8_BASE_NS                             (0x4009F000u)
  /** Peripheral SPI8 base pointer */
  #define SPI8                                     ((SPI_Type *)SPI8_BASE)
  /** Peripheral SPI8 base pointer */
  #define SPI8_NS                                  ((SPI_Type *)SPI8_BASE_NS)
  /** Array initializer of SPI peripheral base addresses */
  #define SPI_BASE_ADDRS                           { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE }
  /** Array initializer of SPI peripheral base pointers */
  #define SPI_BASE_PTRS                            { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8 }
  /** Array initializer of SPI peripheral base addresses */
  #define SPI_BASE_ADDRS_NS                        { SPI0_BASE_NS, SPI1_BASE_NS, SPI2_BASE_NS, SPI3_BASE_NS, SPI4_BASE_NS, SPI5_BASE_NS, SPI6_BASE_NS, SPI7_BASE_NS, SPI8_BASE_NS }
  /** Array initializer of SPI peripheral base pointers */
  #define SPI_BASE_PTRS_NS                         { SPI0_NS, SPI1_NS, SPI2_NS, SPI3_NS, SPI4_NS, SPI5_NS, SPI6_NS, SPI7_NS, SPI8_NS }
#else
  /** Peripheral SPI0 base address */
  #define SPI0_BASE                                (0x40086000u)
  /** Peripheral SPI0 base pointer */
  #define SPI0                                     ((SPI_Type *)SPI0_BASE)
  /** Peripheral SPI1 base address */
  #define SPI1_BASE                                (0x40087000u)
  /** Peripheral SPI1 base pointer */
  #define SPI1                                     ((SPI_Type *)SPI1_BASE)
  /** Peripheral SPI2 base address */
  #define SPI2_BASE                                (0x40088000u)
  /** Peripheral SPI2 base pointer */
  #define SPI2                                     ((SPI_Type *)SPI2_BASE)
  /** Peripheral SPI3 base address */
  #define SPI3_BASE                                (0x40089000u)
  /** Peripheral SPI3 base pointer */
  #define SPI3                                     ((SPI_Type *)SPI3_BASE)
  /** Peripheral SPI4 base address */
  #define SPI4_BASE                                (0x4008A000u)
  /** Peripheral SPI4 base pointer */
  #define SPI4                                     ((SPI_Type *)SPI4_BASE)
  /** Peripheral SPI5 base address */
  #define SPI5_BASE                                (0x40096000u)
  /** Peripheral SPI5 base pointer */
  #define SPI5                                     ((SPI_Type *)SPI5_BASE)
  /** Peripheral SPI6 base address */
  #define SPI6_BASE                                (0x40097000u)
  /** Peripheral SPI6 base pointer */
  #define SPI6                                     ((SPI_Type *)SPI6_BASE)
  /** Peripheral SPI7 base address */
  #define SPI7_BASE                                (0x40098000u)
  /** Peripheral SPI7 base pointer */
  #define SPI7                                     ((SPI_Type *)SPI7_BASE)
  /** Peripheral SPI8 base address */
  #define SPI8_BASE                                (0x4009F000u)
  /** Peripheral SPI8 base pointer */
  #define SPI8                                     ((SPI_Type *)SPI8_BASE)
  /** Array initializer of SPI peripheral base addresses */
  #define SPI_BASE_ADDRS                           { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE }
  /** Array initializer of SPI peripheral base pointers */
  #define SPI_BASE_PTRS                            { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8 }
#endif
/** Interrupt vectors for the SPI peripheral type */
#define SPI_IRQS                                 { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn }

/*!
 * @}
 */ /* end of group SPI_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- SPI_FILTER Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SPI_FILTER_Peripheral_Access_Layer SPI_FILTER Peripheral Access Layer
 * @{
 */

/** SPI_FILTER - Register Layout Typedef */
typedef struct {
  __IO uint32_t CR;                                /**< Control, offset: 0x0 */
  __I  uint32_t ISR;                               /**< Interrupt Register, offset: 0x4 */
  __IO uint32_t IMR;                               /**< Interrupt Mask Register, offset: 0x8 */
  __I  uint32_t SR;                                /**< Status Register, offset: 0xC */
  __IO uint32_t TCR;                               /**< Test Control Register, offset: 0x10 */
  __IO uint32_t P0FAR1;                            /**< Port 0 filter address region 1, offset: 0x14 */
  __IO uint32_t P0FAR2;                            /**< Port 0 filter address region 2, offset: 0x18 */
  __IO uint32_t P0FAR3;                            /**< Port 0 filter address region 3, offset: 0x1C */
  __IO uint32_t P1FAR1;                            /**< Port 1 filter address region 1, offset: 0x20 */
  __IO uint32_t P1FAR2;                            /**< Port 1 filter address region 2, offset: 0x24 */
  __IO uint32_t P1FAR3;                            /**< Port 1 filter address region 3, offset: 0x28 */
       uint8_t RESERVED_0[4];
  __I  uint32_t VER;                               /**< Version, offset: 0x30 */
       uint8_t RESERVED_1[12];
  __IO uint32_t POPCODE0;                          /**< Programmable OP-Code0, offset: 0x40 */
  __IO uint32_t POPCODE1;                          /**< Programmable OP-Code1, offset: 0x44 */
  __IO uint32_t POPCODE2;                          /**< Programmable OP-Code2, offset: 0x48 */
  __IO uint32_t POPCODE3;                          /**< Programmable OP-Code3, offset: 0x4C */
  __IO uint32_t POPCODE4;                          /**< Programmable OP-Code4, offset: 0x50 */
  __I  uint32_t P0BOC;                             /**< P0 Blocked Op Code, offset: 0x54 */
  __I  uint32_t P1BOC;                             /**< P1 Blocked Op Code, offset: 0x58 */
  __IO uint32_t P0MAM;                             /**< Port 0 Max Address Mask, offset: 0x5C */
  __IO uint32_t P1MAM;                             /**< Port 1 Max Address Mask, offset: 0x60 */
} SPI_FILTER_Type;

/* ----------------------------------------------------------------------------
   -- SPI_FILTER Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SPI_FILTER_Register_Masks SPI_FILTER Register Masks
 * @{
 */

/*! @name CR - Control */
/*! @{ */

#define SPI_FILTER_CR_P1_ACT_SEL_MASK            (0x10000U)
#define SPI_FILTER_CR_P1_ACT_SEL_SHIFT           (16U)
/*! P1_ACT_SEL - Active Chip Select for P1 filter
 *  0b0..Sets CS0 as the read location for the firmware image and sets CS1 as the write location for the FW image.
 *  0b1..Sets CS1 as the read location for the firmware image and sets CS0 as the write location for the FW image.
 */
#define SPI_FILTER_CR_P1_ACT_SEL(x)              (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_CR_P1_ACT_SEL_SHIFT)) & SPI_FILTER_CR_P1_ACT_SEL_MASK)

#define SPI_FILTER_CR_P1_BYTE_SEL_MASK           (0x20000U)
#define SPI_FILTER_CR_P1_BYTE_SEL_SHIFT          (17U)
/*! P1_BYTE_SEL - Address Byte Select Mode for P1
 *  0b0..Sets the filter to 4-byte address mode
 *  0b1..Sets the filter to 3-byte address mode
 */
#define SPI_FILTER_CR_P1_BYTE_SEL(x)             (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_CR_P1_BYTE_SEL_SHIFT)) & SPI_FILTER_CR_P1_BYTE_SEL_MASK)

#define SPI_FILTER_CR_P1_BYTE_SEL_MD_MASK        (0x40000U)
#define SPI_FILTER_CR_P1_BYTE_SEL_MD_SHIFT       (18U)
/*! P1_BYTE_SEL_MD - Address Byte Select Mode for P1
 *  0b0..Normal Operation. The Address byte mode is determined by the Op Code Command
 *  0b1..Sets the Byte Mode to 3-byte and gives control of the function to the P1_BYTE_SEL in the P1 Filter
 *       Control Register. In this mode, any changes to P1_BYTE_SEL are latched and the internal state of P1_BYTE_SEL
 *       will retain this value when P1_BYTE_SEL_MD is cleared
 */
#define SPI_FILTER_CR_P1_BYTE_SEL_MD(x)          (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_CR_P1_BYTE_SEL_MD_SHIFT)) & SPI_FILTER_CR_P1_BYTE_SEL_MD_MASK)

#define SPI_FILTER_CR_P1_DIRTY_CLR_MASK          (0x80000U)
#define SPI_FILTER_CR_P1_DIRTY_CLR_SHIFT         (19U)
/*! P1_DIRTY_CLR - Clear dirty state for P1
 */
#define SPI_FILTER_CR_P1_DIRTY_CLR(x)            (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_CR_P1_DIRTY_CLR_SHIFT)) & SPI_FILTER_CR_P1_DIRTY_CLR_MASK)

#define SPI_FILTER_CR_P1_FLT_EN_MASK             (0x100000U)
#define SPI_FILTER_CR_P1_FLT_EN_SHIFT            (20U)
/*! P1_FLT_EN - Filter Enable bit for P1 filter
 *  0b0..Filter Disabled. All CS Disable outputs are asserted so that host access to the flash devices is
 *       disabled. CS# inputs to the filter are disabled so that the filter state machine is locked in its current state.
 *       All register controls remain functional.
 *  0b1..Filter Enabled. CS# inputs to the filter are enabled and the filter state machine controls the CS disable
 *       outputs. This bit takes priority over the P1_BYP_EN bit in the Test Control Register. Setting this bit
 *       will enable filtering and will enable communication to flash devices regardless of the state of P1_BYP_EN.
 *       All other register controls remain functional while filtering is enabled.
 */
#define SPI_FILTER_CR_P1_FLT_EN(x)               (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_CR_P1_FLT_EN_SHIFT)) & SPI_FILTER_CR_P1_FLT_EN_MASK)

#define SPI_FILTER_CR_P1_FLASH_MD_MASK           (0x200000U)
#define SPI_FILTER_CR_P1_FLASH_MD_SHIFT          (21U)
/*! P1_FLASH_MD - Flash Mode Select for P1
 *  0b0..Dual Flash Mode. Supports two separate physical flash devices as described in Section 3.1
 *  0b1..Single Flash Mode. Supports a single physical flash device as described in Section 3.2. Note that all
 *       Chip Erase Op Codes are blocked when in this mode.
 */
#define SPI_FILTER_CR_P1_FLASH_MD(x)             (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_CR_P1_FLASH_MD_SHIFT)) & SPI_FILTER_CR_P1_FLASH_MD_MASK)

#define SPI_FILTER_CR_P0_ACT_SEL_MASK            (0x1000000U)
#define SPI_FILTER_CR_P0_ACT_SEL_SHIFT           (24U)
/*! P0_ACT_SEL - Active Chip Select for P0 filter
 *  0b0..Sets CS0 as the read location for the firmware image and sets CS1 as the write location for the FW image.
 *  0b1..Sets CS1 as the read location for the firmware image and sets CS0 as the write location for the FW image.
 */
#define SPI_FILTER_CR_P0_ACT_SEL(x)              (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_CR_P0_ACT_SEL_SHIFT)) & SPI_FILTER_CR_P0_ACT_SEL_MASK)

#define SPI_FILTER_CR_P0_BYTE_SEL_MASK           (0x2000000U)
#define SPI_FILTER_CR_P0_BYTE_SEL_SHIFT          (25U)
/*! P0_BYTE_SEL - Address Byte Select for P0 filter
 *  0b0..Sets the filter to 3-byte address mode
 *  0b1..Sets the filter to 4-byte address mode
 */
#define SPI_FILTER_CR_P0_BYTE_SEL(x)             (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_CR_P0_BYTE_SEL_SHIFT)) & SPI_FILTER_CR_P0_BYTE_SEL_MASK)

#define SPI_FILTER_CR_P0_BYTE_SEL_MD_MASK        (0x4000000U)
#define SPI_FILTER_CR_P0_BYTE_SEL_MD_SHIFT       (26U)
/*! P0_BYTE_SEL_MD - Address Byte Select Mode for P0 filter
 *  0b0..Normal Operation. The Address byte mode is determined by the Op Code Command
 *  0b1..Sets the Byte Mode to 3-byte and gives control of the function to the P0_BYTE_SEL in the P0 Filter
 *       Control Register. In this mode, any changes to P0_BYTE_SEL are latched and the internal state of BYTE_SEL will
 *       retain this value when P0_BYTE_SEL_MD is cleared.
 */
#define SPI_FILTER_CR_P0_BYTE_SEL_MD(x)          (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_CR_P0_BYTE_SEL_MD_SHIFT)) & SPI_FILTER_CR_P0_BYTE_SEL_MD_MASK)

#define SPI_FILTER_CR_P0_DIRTY_CLR_MASK          (0x8000000U)
#define SPI_FILTER_CR_P0_DIRTY_CLR_SHIFT         (27U)
/*! P0_DIRTY_CLR - Clear dirty state for P0
 */
#define SPI_FILTER_CR_P0_DIRTY_CLR(x)            (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_CR_P0_DIRTY_CLR_SHIFT)) & SPI_FILTER_CR_P0_DIRTY_CLR_MASK)

#define SPI_FILTER_CR_P0_FLT_EN_MASK             (0x10000000U)
#define SPI_FILTER_CR_P0_FLT_EN_SHIFT            (28U)
/*! P0_FLT_EN - Filter Enable bit for P0
 *  0b0..Filter Enabled. CS# inputs to the filter are enabled and the filter state machine controls the CS disable
 *       outputs. CS# inputs to the filter are enabled so that the filter state machine is active. All other
 *       register controls are functional.
 *  0b1..Filter Disabled. All CS Disable outputs are asserted so that host access to the flash devices is
 *       disabled. CS# inputs to the filter are disabled so that the filter state machine is locked in its current state.
 *       All other register controls can be accessed, but have no impact on the functionality of the filter while
 *       the filter is disabled.
 */
#define SPI_FILTER_CR_P0_FLT_EN(x)               (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_CR_P0_FLT_EN_SHIFT)) & SPI_FILTER_CR_P0_FLT_EN_MASK)

#define SPI_FILTER_CR_P0_FLASH_MD_MASK           (0x20000000U)
#define SPI_FILTER_CR_P0_FLASH_MD_SHIFT          (29U)
/*! P0_FLASH_MD - Flash Mode Select for P0
 *  0b0..Dual Flash Mode. Supports two separate physical flash devices as described in Section 3.1
 *  0b1..Single Flash Mode. Supports a single physical flash device as described in Section 3.2. Note that all
 *       Chip Erase Op Codes are blocked when in this mode.
 */
#define SPI_FILTER_CR_P0_FLASH_MD(x)             (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_CR_P0_FLASH_MD_SHIFT)) & SPI_FILTER_CR_P0_FLASH_MD_MASK)
/*! @} */

/*! @name ISR - Interrupt Register */
/*! @{ */

#define SPI_FILTER_ISR_P0_DIRTY_INT_MASK         (0x1000000U)
#define SPI_FILTER_ISR_P0_DIRTY_INT_SHIFT        (24U)
/*! P0_DIRTY_INT
 *  0b0..Indicates that a write has occurred to the FW Code region of the inactive Flash and that flash is now considered corrupt
 *  0b1..Indicates normal operation
 */
#define SPI_FILTER_ISR_P0_DIRTY_INT(x)           (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_ISR_P0_DIRTY_INT_SHIFT)) & SPI_FILTER_ISR_P0_DIRTY_INT_MASK)

#define SPI_FILTER_ISR_P1_DIRTY_INT_MASK         (0x2000000U)
#define SPI_FILTER_ISR_P1_DIRTY_INT_SHIFT        (25U)
/*! P1_DIRTY_INT
 *  0b0..Indicates normal operation
 *  0b1..indicates that a write has occurred to the FW Code region of the inactive Flash and that flash is now considered corrupt
 */
#define SPI_FILTER_ISR_P1_DIRTY_INT(x)           (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_ISR_P1_DIRTY_INT_SHIFT)) & SPI_FILTER_ISR_P1_DIRTY_INT_MASK)

#define SPI_FILTER_ISR_P0_BLK_INT_MASK           (0x4000000U)
#define SPI_FILTER_ISR_P0_BLK_INT_SHIFT          (26U)
/*! P0_BLK_INT
 *  0b0..Indicates normal operation
 *  0b1..Indicates that a blocked opcode has been detected
 */
#define SPI_FILTER_ISR_P0_BLK_INT(x)             (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_ISR_P0_BLK_INT_SHIFT)) & SPI_FILTER_ISR_P0_BLK_INT_MASK)

#define SPI_FILTER_ISR_P1_BLK_INT_MASK           (0x8000000U)
#define SPI_FILTER_ISR_P1_BLK_INT_SHIFT          (27U)
/*! P1_BLK_INT
 *  0b0..Indicates normal operation
 *  0b1..Indicates that a blocked opcode has been detected
 */
#define SPI_FILTER_ISR_P1_BLK_INT(x)             (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_ISR_P1_BLK_INT_SHIFT)) & SPI_FILTER_ISR_P1_BLK_INT_MASK)

#define SPI_FILTER_ISR_P0_BYTEMODE_INT_MASK      (0x10000000U)
#define SPI_FILTER_ISR_P0_BYTEMODE_INT_SHIFT     (28U)
/*! P0_BYTEMODE_INT
 *  0b0..Indicates normal operation
 *  0b1..Indicates that a Bytemode change has been detected (OpCode E9 or B7)
 */
#define SPI_FILTER_ISR_P0_BYTEMODE_INT(x)        (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_ISR_P0_BYTEMODE_INT_SHIFT)) & SPI_FILTER_ISR_P0_BYTEMODE_INT_MASK)

#define SPI_FILTER_ISR_P1_BYTEMODE_INT_MASK      (0x20000000U)
#define SPI_FILTER_ISR_P1_BYTEMODE_INT_SHIFT     (29U)
/*! P1_BYTEMODE_INT
 *  0b0..Indicates normal operation
 *  0b1..Indicates that a Bytemode change has been detected (OpCode E9 or B7)
 */
#define SPI_FILTER_ISR_P1_BYTEMODE_INT(x)        (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_ISR_P1_BYTEMODE_INT_SHIFT)) & SPI_FILTER_ISR_P1_BYTEMODE_INT_MASK)

#define SPI_FILTER_ISR_P0_F8_INT_MASK            (0x40000000U)
#define SPI_FILTER_ISR_P0_F8_INT_SHIFT           (30U)
/*! P0_F8_INT
 *  0b0..Indicates normal operation
 *  0b1..Indicates an F8 command has been detected
 */
#define SPI_FILTER_ISR_P0_F8_INT(x)              (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_ISR_P0_F8_INT_SHIFT)) & SPI_FILTER_ISR_P0_F8_INT_MASK)

#define SPI_FILTER_ISR_P1_F8_INT_MASK            (0x80000000U)
#define SPI_FILTER_ISR_P1_F8_INT_SHIFT           (31U)
/*! P1_F8_INT
 *  0b0..Indicates normal operation
 *  0b1..Indicates an F8 command has been detected
 */
#define SPI_FILTER_ISR_P1_F8_INT(x)              (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_ISR_P1_F8_INT_SHIFT)) & SPI_FILTER_ISR_P1_F8_INT_MASK)
/*! @} */

/*! @name IMR - Interrupt Mask Register */
/*! @{ */

#define SPI_FILTER_IMR_P0_DIRTY_MASK_MASK        (0x1000000U)
#define SPI_FILTER_IMR_P0_DIRTY_MASK_SHIFT       (24U)
/*! P0_DIRTY_MASK - Mask bit for P0_DIRTY_INT
 *  0b0..Indicates P0_DIRTY_INT interrupt is disabled.
 *  0b1..Indicates P0_DIRTY_INT interrupt is enabled.
 */
#define SPI_FILTER_IMR_P0_DIRTY_MASK(x)          (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_IMR_P0_DIRTY_MASK_SHIFT)) & SPI_FILTER_IMR_P0_DIRTY_MASK_MASK)

#define SPI_FILTER_IMR_P1_DIRTY_MASK_MASK        (0x2000000U)
#define SPI_FILTER_IMR_P1_DIRTY_MASK_SHIFT       (25U)
/*! P1_DIRTY_MASK - Mask bit for P1_DIRTY_INT
 *  0b0..Indicates normal operation. P1_DIRTY_INT interrupt is enabled.
 *  0b1..Indicates P1_DIRTY_INT interrupt is disabled.
 */
#define SPI_FILTER_IMR_P1_DIRTY_MASK(x)          (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_IMR_P1_DIRTY_MASK_SHIFT)) & SPI_FILTER_IMR_P1_DIRTY_MASK_MASK)

#define SPI_FILTER_IMR_P0_BLK_MASK_MASK          (0x4000000U)
#define SPI_FILTER_IMR_P0_BLK_MASK_SHIFT         (26U)
/*! P0_BLK_MASK - Mask bit for P0_BLK_MASK
 *  0b0..Indicates P0_BLK_MASK is enabled.
 *  0b1..Indicates P0_BLK_MASK is disabled.
 */
#define SPI_FILTER_IMR_P0_BLK_MASK(x)            (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_IMR_P0_BLK_MASK_SHIFT)) & SPI_FILTER_IMR_P0_BLK_MASK_MASK)

#define SPI_FILTER_IMR_P1_BLK_MASK_MASK          (0x8000000U)
#define SPI_FILTER_IMR_P1_BLK_MASK_SHIFT         (27U)
/*! P1_BLK_MASK - Mask bit for P1_BLK_MASK
 *  0b0..Indicates P1_BLK_MASK is enabled.
 *  0b1..Indicates P1_BLK_MASK is disabled.
 */
#define SPI_FILTER_IMR_P1_BLK_MASK(x)            (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_IMR_P1_BLK_MASK_SHIFT)) & SPI_FILTER_IMR_P1_BLK_MASK_MASK)

#define SPI_FILTER_IMR_P0_BYTEMODE_MASK_MASK     (0x10000000U)
#define SPI_FILTER_IMR_P0_BYTEMODE_MASK_SHIFT    (28U)
/*! P0_BYTEMODE_MASK - Mask bit for P0_BYTEMODE_MASK
 *  0b0..Indicates P0_BYTEMODE_MASK is enabled.
 *  0b1..Indicates P0_BYTEMODE_MASK is disabled.
 */
#define SPI_FILTER_IMR_P0_BYTEMODE_MASK(x)       (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_IMR_P0_BYTEMODE_MASK_SHIFT)) & SPI_FILTER_IMR_P0_BYTEMODE_MASK_MASK)

#define SPI_FILTER_IMR_P1_BYTEMODE_MASK_MASK     (0x20000000U)
#define SPI_FILTER_IMR_P1_BYTEMODE_MASK_SHIFT    (29U)
/*! P1_BYTEMODE_MASK - Mask bit for P1_BYTEMODE_MASK
 *  0b0..Indicates P1_BYTEMODE_MASK is enabled.
 *  0b1..Indicates P1_BYTEMODE_MASK is disabled.
 */
#define SPI_FILTER_IMR_P1_BYTEMODE_MASK(x)       (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_IMR_P1_BYTEMODE_MASK_SHIFT)) & SPI_FILTER_IMR_P1_BYTEMODE_MASK_MASK)

#define SPI_FILTER_IMR_P0_F8_MASK_MASK           (0x40000000U)
#define SPI_FILTER_IMR_P0_F8_MASK_SHIFT          (30U)
/*! P0_F8_MASK - Mask bit for P0_F8_MASK
 *  0b0..Indicates P0_F8_MASK is enabled.
 *  0b1..Indicates P0_F8_MASK is disabled.
 */
#define SPI_FILTER_IMR_P0_F8_MASK(x)             (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_IMR_P0_F8_MASK_SHIFT)) & SPI_FILTER_IMR_P0_F8_MASK_MASK)

#define SPI_FILTER_IMR_P1_F8_MASK_MASK           (0x80000000U)
#define SPI_FILTER_IMR_P1_F8_MASK_SHIFT          (31U)
/*! P1_F8_MASK - Mask bit for P1_F8_MASK
 *  0b0..Indicates P1_F8_MASK is enabled.
 *  0b1..Indicates P1_F8_MASK is disabled.
 */
#define SPI_FILTER_IMR_P1_F8_MASK(x)             (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_IMR_P1_F8_MASK_SHIFT)) & SPI_FILTER_IMR_P1_F8_MASK_MASK)
/*! @} */

/*! @name SR - Status Register */
/*! @{ */

#define SPI_FILTER_SR_P1_DIRTY_MASK              (0x10000U)
#define SPI_FILTER_SR_P1_DIRTY_SHIFT             (16U)
/*! P1_DIRTY
 *  0b1..Indicates that a write to the inactive Flash has been detected and the state of the flash should be considered "dirty".
 *  0b1..Indicates normal operation. No Writes have been directed to the inactive Flash
 */
#define SPI_FILTER_SR_P1_DIRTY(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_SR_P1_DIRTY_SHIFT)) & SPI_FILTER_SR_P1_DIRTY_MASK)

#define SPI_FILTER_SR_P1_BYTE_MODE_MASK          (0x20000U)
#define SPI_FILTER_SR_P1_BYTE_MODE_SHIFT         (17U)
/*! P1_BYTE_MODE
 *  0b0..3-Byte Address Mode
 *  0b1..4-Byte Address Mode
 */
#define SPI_FILTER_SR_P1_BYTE_MODE(x)            (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_SR_P1_BYTE_MODE_SHIFT)) & SPI_FILTER_SR_P1_BYTE_MODE_MASK)

#define SPI_FILTER_SR_P0_DIRTY_MASK              (0x1000000U)
#define SPI_FILTER_SR_P0_DIRTY_SHIFT             (24U)
/*! P0_DIRTY
 *  0b0..Indicates normal operation. No Writes have been directed to the inactive Flash
 *  0b1..Indicates that a write to the inactive Flash has been detected and the state of the flash should be considered "dirty".
 */
#define SPI_FILTER_SR_P0_DIRTY(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_SR_P0_DIRTY_SHIFT)) & SPI_FILTER_SR_P0_DIRTY_MASK)

#define SPI_FILTER_SR_P0_BYTE_MODE_MASK          (0x2000000U)
#define SPI_FILTER_SR_P0_BYTE_MODE_SHIFT         (25U)
/*! P0_BYTE_MODE
 *  0b0..3-Byte Address Mode
 *  0b1..4-Byte Address Mode
 */
#define SPI_FILTER_SR_P0_BYTE_MODE(x)            (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_SR_P0_BYTE_MODE_SHIFT)) & SPI_FILTER_SR_P0_BYTE_MODE_MASK)
/*! @} */

/*! @name TCR - Test Control Register */
/*! @{ */

#define SPI_FILTER_TCR_P0_BYP_SEL_MASK           (0x10000U)
#define SPI_FILTER_TCR_P0_BYP_SEL_SHIFT          (16U)
/*! P0_BYP_SEL
 *  0b0..CS0
 *  0b1..CS1
 */
#define SPI_FILTER_TCR_P0_BYP_SEL(x)             (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_TCR_P0_BYP_SEL_SHIFT)) & SPI_FILTER_TCR_P0_BYP_SEL_MASK)

#define SPI_FILTER_TCR_P0_BYP_EN_MASK            (0x20000U)
#define SPI_FILTER_TCR_P0_BYP_EN_SHIFT           (17U)
/*! P0_BYP_EN
 *  0b0..Filter Bypass Disabled
 *  0b1..Filter Bypass Enabled
 */
#define SPI_FILTER_TCR_P0_BYP_EN(x)              (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_TCR_P0_BYP_EN_SHIFT)) & SPI_FILTER_TCR_P0_BYP_EN_MASK)

#define SPI_FILTER_TCR_P1_BYP_SEL_MASK           (0x40000U)
#define SPI_FILTER_TCR_P1_BYP_SEL_SHIFT          (18U)
/*! P1_BYP_SEL
 *  0b0..CS0
 *  0b1..CS1
 */
#define SPI_FILTER_TCR_P1_BYP_SEL(x)             (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_TCR_P1_BYP_SEL_SHIFT)) & SPI_FILTER_TCR_P1_BYP_SEL_MASK)

#define SPI_FILTER_TCR_P1_BYP_EN_MASK            (0x80000U)
#define SPI_FILTER_TCR_P1_BYP_EN_SHIFT           (19U)
/*! P1_BYP_EN
 *  0b0..Filter Bypass Disabled
 *  0b1..Filter Bypass Enabled
 */
#define SPI_FILTER_TCR_P1_BYP_EN(x)              (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_TCR_P1_BYP_EN_SHIFT)) & SPI_FILTER_TCR_P1_BYP_EN_MASK)

#define SPI_FILTER_TCR_P0_MFG_ID_MASK            (0xF000000U)
#define SPI_FILTER_TCR_P0_MFG_ID_SHIFT           (24U)
/*! P0_MFG_ID - Sets the Flash memory manufacturer
 *  0b0010..Micron
 *  0b0001..Windbond
 *  0b0000..Macronix
 */
#define SPI_FILTER_TCR_P0_MFG_ID(x)              (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_TCR_P0_MFG_ID_SHIFT)) & SPI_FILTER_TCR_P0_MFG_ID_MASK)

#define SPI_FILTER_TCR_P1_MFG_ID_MASK            (0xF0000000U)
#define SPI_FILTER_TCR_P1_MFG_ID_SHIFT           (28U)
/*! P1_MFG_ID - Sets the Flash memory manufacturer
 *  0b0010..Micron
 *  0b0001..Windbond
 *  0b0000..Macronix
 */
#define SPI_FILTER_TCR_P1_MFG_ID(x)              (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_TCR_P1_MFG_ID_SHIFT)) & SPI_FILTER_TCR_P1_MFG_ID_MASK)
/*! @} */

/*! @name P0FAR1 - Port 0 filter address region 1 */
/*! @{ */

#define SPI_FILTER_P0FAR1_ADDRESS_LOWER_LSBS_MASK (0xFFU)
#define SPI_FILTER_P0FAR1_ADDRESS_LOWER_LSBS_SHIFT (0U)
/*! ADDRESS_LOWER_LSBS - Address Lower LSBs
 */
#define SPI_FILTER_P0FAR1_ADDRESS_LOWER_LSBS(x)  (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P0FAR1_ADDRESS_LOWER_LSBS_SHIFT)) & SPI_FILTER_P0FAR1_ADDRESS_LOWER_LSBS_MASK)

#define SPI_FILTER_P0FAR1_ADDRESS_LOWER_MSBS_MASK (0xFF00U)
#define SPI_FILTER_P0FAR1_ADDRESS_LOWER_MSBS_SHIFT (8U)
/*! ADDRESS_LOWER_MSBS - Address Lower MSBs
 */
#define SPI_FILTER_P0FAR1_ADDRESS_LOWER_MSBS(x)  (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P0FAR1_ADDRESS_LOWER_MSBS_SHIFT)) & SPI_FILTER_P0FAR1_ADDRESS_LOWER_MSBS_MASK)

#define SPI_FILTER_P0FAR1_ADDRESS_UPPER_LSBS_MASK (0xFF0000U)
#define SPI_FILTER_P0FAR1_ADDRESS_UPPER_LSBS_SHIFT (16U)
/*! ADDRESS_UPPER_LSBS - Address Upper LSBs
 */
#define SPI_FILTER_P0FAR1_ADDRESS_UPPER_LSBS(x)  (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P0FAR1_ADDRESS_UPPER_LSBS_SHIFT)) & SPI_FILTER_P0FAR1_ADDRESS_UPPER_LSBS_MASK)

#define SPI_FILTER_P0FAR1_ADDRESS_UPPER_MSBS_MASK (0xFF000000U)
#define SPI_FILTER_P0FAR1_ADDRESS_UPPER_MSBS_SHIFT (24U)
/*! ADDRESS_UPPER_MSBS - Address Upper MSBs
 */
#define SPI_FILTER_P0FAR1_ADDRESS_UPPER_MSBS(x)  (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P0FAR1_ADDRESS_UPPER_MSBS_SHIFT)) & SPI_FILTER_P0FAR1_ADDRESS_UPPER_MSBS_MASK)
/*! @} */

/*! @name P0FAR2 - Port 0 filter address region 2 */
/*! @{ */

#define SPI_FILTER_P0FAR2_ADDRESS_LOWER_LSBS_MASK (0xFFU)
#define SPI_FILTER_P0FAR2_ADDRESS_LOWER_LSBS_SHIFT (0U)
/*! ADDRESS_LOWER_LSBS - Address Lower LSBs
 */
#define SPI_FILTER_P0FAR2_ADDRESS_LOWER_LSBS(x)  (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P0FAR2_ADDRESS_LOWER_LSBS_SHIFT)) & SPI_FILTER_P0FAR2_ADDRESS_LOWER_LSBS_MASK)

#define SPI_FILTER_P0FAR2_ADDRESS_LOWER_MSBS_MASK (0xFF00U)
#define SPI_FILTER_P0FAR2_ADDRESS_LOWER_MSBS_SHIFT (8U)
/*! ADDRESS_LOWER_MSBS - Address Lower MSBs
 */
#define SPI_FILTER_P0FAR2_ADDRESS_LOWER_MSBS(x)  (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P0FAR2_ADDRESS_LOWER_MSBS_SHIFT)) & SPI_FILTER_P0FAR2_ADDRESS_LOWER_MSBS_MASK)

#define SPI_FILTER_P0FAR2_ADDRESS_UPPER_LSBS_MASK (0xFF0000U)
#define SPI_FILTER_P0FAR2_ADDRESS_UPPER_LSBS_SHIFT (16U)
/*! ADDRESS_UPPER_LSBS - Address Upper LSBs
 */
#define SPI_FILTER_P0FAR2_ADDRESS_UPPER_LSBS(x)  (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P0FAR2_ADDRESS_UPPER_LSBS_SHIFT)) & SPI_FILTER_P0FAR2_ADDRESS_UPPER_LSBS_MASK)

#define SPI_FILTER_P0FAR2_ADDRESS_UPPER_MSBS_MASK (0xFF000000U)
#define SPI_FILTER_P0FAR2_ADDRESS_UPPER_MSBS_SHIFT (24U)
/*! ADDRESS_UPPER_MSBS - Address Upper MSBs
 */
#define SPI_FILTER_P0FAR2_ADDRESS_UPPER_MSBS(x)  (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P0FAR2_ADDRESS_UPPER_MSBS_SHIFT)) & SPI_FILTER_P0FAR2_ADDRESS_UPPER_MSBS_MASK)
/*! @} */

/*! @name P0FAR3 - Port 0 filter address region 3 */
/*! @{ */

#define SPI_FILTER_P0FAR3_ADDRESS_LOWER_LSBS_MASK (0xFFU)
#define SPI_FILTER_P0FAR3_ADDRESS_LOWER_LSBS_SHIFT (0U)
/*! ADDRESS_LOWER_LSBS - Address Lower LSBs
 */
#define SPI_FILTER_P0FAR3_ADDRESS_LOWER_LSBS(x)  (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P0FAR3_ADDRESS_LOWER_LSBS_SHIFT)) & SPI_FILTER_P0FAR3_ADDRESS_LOWER_LSBS_MASK)

#define SPI_FILTER_P0FAR3_ADDRESS_LOWER_MSBS_MASK (0xFF00U)
#define SPI_FILTER_P0FAR3_ADDRESS_LOWER_MSBS_SHIFT (8U)
/*! ADDRESS_LOWER_MSBS - Address Lower MSBs
 */
#define SPI_FILTER_P0FAR3_ADDRESS_LOWER_MSBS(x)  (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P0FAR3_ADDRESS_LOWER_MSBS_SHIFT)) & SPI_FILTER_P0FAR3_ADDRESS_LOWER_MSBS_MASK)

#define SPI_FILTER_P0FAR3_ADDRESS_UPPER_LSBS_MASK (0xFF0000U)
#define SPI_FILTER_P0FAR3_ADDRESS_UPPER_LSBS_SHIFT (16U)
/*! ADDRESS_UPPER_LSBS - Address Upper LSBs
 */
#define SPI_FILTER_P0FAR3_ADDRESS_UPPER_LSBS(x)  (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P0FAR3_ADDRESS_UPPER_LSBS_SHIFT)) & SPI_FILTER_P0FAR3_ADDRESS_UPPER_LSBS_MASK)

#define SPI_FILTER_P0FAR3_ADDRESS_UPPER_MSBS_MASK (0xFF000000U)
#define SPI_FILTER_P0FAR3_ADDRESS_UPPER_MSBS_SHIFT (24U)
/*! ADDRESS_UPPER_MSBS - Address Upper MSBs
 */
#define SPI_FILTER_P0FAR3_ADDRESS_UPPER_MSBS(x)  (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P0FAR3_ADDRESS_UPPER_MSBS_SHIFT)) & SPI_FILTER_P0FAR3_ADDRESS_UPPER_MSBS_MASK)
/*! @} */

/*! @name P1FAR1 - Port 1 filter address region 1 */
/*! @{ */

#define SPI_FILTER_P1FAR1_ADDRESS_LOWER_LSBS_MASK (0xFFU)
#define SPI_FILTER_P1FAR1_ADDRESS_LOWER_LSBS_SHIFT (0U)
/*! ADDRESS_LOWER_LSBS - Address Lower LSBs
 */
#define SPI_FILTER_P1FAR1_ADDRESS_LOWER_LSBS(x)  (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P1FAR1_ADDRESS_LOWER_LSBS_SHIFT)) & SPI_FILTER_P1FAR1_ADDRESS_LOWER_LSBS_MASK)

#define SPI_FILTER_P1FAR1_ADDRESS_LOWER_MSBS_MASK (0xFF00U)
#define SPI_FILTER_P1FAR1_ADDRESS_LOWER_MSBS_SHIFT (8U)
/*! ADDRESS_LOWER_MSBS - Address Lower MSBs
 */
#define SPI_FILTER_P1FAR1_ADDRESS_LOWER_MSBS(x)  (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P1FAR1_ADDRESS_LOWER_MSBS_SHIFT)) & SPI_FILTER_P1FAR1_ADDRESS_LOWER_MSBS_MASK)

#define SPI_FILTER_P1FAR1_ADDRESS_UPPER_LSBS_MASK (0xFF0000U)
#define SPI_FILTER_P1FAR1_ADDRESS_UPPER_LSBS_SHIFT (16U)
/*! ADDRESS_UPPER_LSBS - Address Upper LSBs
 */
#define SPI_FILTER_P1FAR1_ADDRESS_UPPER_LSBS(x)  (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P1FAR1_ADDRESS_UPPER_LSBS_SHIFT)) & SPI_FILTER_P1FAR1_ADDRESS_UPPER_LSBS_MASK)

#define SPI_FILTER_P1FAR1_ADDRESS_UPPER_MSBS_MASK (0xFF000000U)
#define SPI_FILTER_P1FAR1_ADDRESS_UPPER_MSBS_SHIFT (24U)
/*! ADDRESS_UPPER_MSBS - Address Upper MSBs
 */
#define SPI_FILTER_P1FAR1_ADDRESS_UPPER_MSBS(x)  (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P1FAR1_ADDRESS_UPPER_MSBS_SHIFT)) & SPI_FILTER_P1FAR1_ADDRESS_UPPER_MSBS_MASK)
/*! @} */

/*! @name P1FAR2 - Port 1 filter address region 2 */
/*! @{ */

#define SPI_FILTER_P1FAR2_ADDRESS_LOWER_LSBS_MASK (0xFFU)
#define SPI_FILTER_P1FAR2_ADDRESS_LOWER_LSBS_SHIFT (0U)
/*! ADDRESS_LOWER_LSBS - Address Lower LSBs
 */
#define SPI_FILTER_P1FAR2_ADDRESS_LOWER_LSBS(x)  (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P1FAR2_ADDRESS_LOWER_LSBS_SHIFT)) & SPI_FILTER_P1FAR2_ADDRESS_LOWER_LSBS_MASK)

#define SPI_FILTER_P1FAR2_ADDRESS_LOWER_MSBS_MASK (0xFF00U)
#define SPI_FILTER_P1FAR2_ADDRESS_LOWER_MSBS_SHIFT (8U)
/*! ADDRESS_LOWER_MSBS - Address Lower MSBs
 */
#define SPI_FILTER_P1FAR2_ADDRESS_LOWER_MSBS(x)  (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P1FAR2_ADDRESS_LOWER_MSBS_SHIFT)) & SPI_FILTER_P1FAR2_ADDRESS_LOWER_MSBS_MASK)

#define SPI_FILTER_P1FAR2_ADDRESS_UPPER_LSBS_MASK (0xFF0000U)
#define SPI_FILTER_P1FAR2_ADDRESS_UPPER_LSBS_SHIFT (16U)
/*! ADDRESS_UPPER_LSBS - Address Upper LSBs
 */
#define SPI_FILTER_P1FAR2_ADDRESS_UPPER_LSBS(x)  (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P1FAR2_ADDRESS_UPPER_LSBS_SHIFT)) & SPI_FILTER_P1FAR2_ADDRESS_UPPER_LSBS_MASK)

#define SPI_FILTER_P1FAR2_ADDRESS_UPPER_MSBS_MASK (0xFF000000U)
#define SPI_FILTER_P1FAR2_ADDRESS_UPPER_MSBS_SHIFT (24U)
/*! ADDRESS_UPPER_MSBS - Address Upper MSBs
 */
#define SPI_FILTER_P1FAR2_ADDRESS_UPPER_MSBS(x)  (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P1FAR2_ADDRESS_UPPER_MSBS_SHIFT)) & SPI_FILTER_P1FAR2_ADDRESS_UPPER_MSBS_MASK)
/*! @} */

/*! @name P1FAR3 - Port 1 filter address region 3 */
/*! @{ */

#define SPI_FILTER_P1FAR3_ADDRESS_LOWER_LSBS_MASK (0xFFU)
#define SPI_FILTER_P1FAR3_ADDRESS_LOWER_LSBS_SHIFT (0U)
/*! ADDRESS_LOWER_LSBS - Address Lower LSBs
 */
#define SPI_FILTER_P1FAR3_ADDRESS_LOWER_LSBS(x)  (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P1FAR3_ADDRESS_LOWER_LSBS_SHIFT)) & SPI_FILTER_P1FAR3_ADDRESS_LOWER_LSBS_MASK)

#define SPI_FILTER_P1FAR3_ADDRESS_LOWER_MSBS_MASK (0xFF00U)
#define SPI_FILTER_P1FAR3_ADDRESS_LOWER_MSBS_SHIFT (8U)
/*! ADDRESS_LOWER_MSBS - Address Lower MSBs
 */
#define SPI_FILTER_P1FAR3_ADDRESS_LOWER_MSBS(x)  (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P1FAR3_ADDRESS_LOWER_MSBS_SHIFT)) & SPI_FILTER_P1FAR3_ADDRESS_LOWER_MSBS_MASK)

#define SPI_FILTER_P1FAR3_ADDRESS_UPPER_LSBS_MASK (0xFF0000U)
#define SPI_FILTER_P1FAR3_ADDRESS_UPPER_LSBS_SHIFT (16U)
/*! ADDRESS_UPPER_LSBS - Address Upper LSBs
 */
#define SPI_FILTER_P1FAR3_ADDRESS_UPPER_LSBS(x)  (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P1FAR3_ADDRESS_UPPER_LSBS_SHIFT)) & SPI_FILTER_P1FAR3_ADDRESS_UPPER_LSBS_MASK)

#define SPI_FILTER_P1FAR3_ADDRESS_UPPER_MSBS_MASK (0xFF000000U)
#define SPI_FILTER_P1FAR3_ADDRESS_UPPER_MSBS_SHIFT (24U)
/*! ADDRESS_UPPER_MSBS - Address Upper MSBs
 */
#define SPI_FILTER_P1FAR3_ADDRESS_UPPER_MSBS(x)  (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P1FAR3_ADDRESS_UPPER_MSBS_SHIFT)) & SPI_FILTER_P1FAR3_ADDRESS_UPPER_MSBS_MASK)
/*! @} */

/*! @name VER - Version */
/*! @{ */

#define SPI_FILTER_VER_MINOR_REVISION_MASK       (0xF000000U)
#define SPI_FILTER_VER_MINOR_REVISION_SHIFT      (24U)
/*! MINOR_REVISION - Minor revision
 */
#define SPI_FILTER_VER_MINOR_REVISION(x)         (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_VER_MINOR_REVISION_SHIFT)) & SPI_FILTER_VER_MINOR_REVISION_MASK)

#define SPI_FILTER_VER_MAJOR_REVISION_MASK       (0xF0000000U)
#define SPI_FILTER_VER_MAJOR_REVISION_SHIFT      (28U)
/*! MAJOR_REVISION - Major Revision
 */
#define SPI_FILTER_VER_MAJOR_REVISION(x)         (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_VER_MAJOR_REVISION_SHIFT)) & SPI_FILTER_VER_MAJOR_REVISION_MASK)
/*! @} */

/*! @name POPCODE0 - Programmable OP-Code0 */
/*! @{ */

#define SPI_FILTER_POPCODE0_FILTER_STATE0_MASK   (0x1F0000U)
#define SPI_FILTER_POPCODE0_FILTER_STATE0_SHIFT  (16U)
/*! FILTER_STATE0 - Programmable Filter state 0
 */
#define SPI_FILTER_POPCODE0_FILTER_STATE0(x)     (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_POPCODE0_FILTER_STATE0_SHIFT)) & SPI_FILTER_POPCODE0_FILTER_STATE0_MASK)

#define SPI_FILTER_POPCODE0_FILTER_BIT0_MASK     (0x200000U)
#define SPI_FILTER_POPCODE0_FILTER_BIT0_SHIFT    (21U)
/*! FILTER_BIT0
 *  0b0..Filter after 7th bit for all Commands Op Codes that need to be filtered.
 *  0b1..Filter after 8th bit for all Read/Write Op Codes that are filtered based on the address.
 */
#define SPI_FILTER_POPCODE0_FILTER_BIT0(x)       (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_POPCODE0_FILTER_BIT0_SHIFT)) & SPI_FILTER_POPCODE0_FILTER_BIT0_MASK)

#define SPI_FILTER_POPCODE0_PRG_OPCODE0_MASK     (0xFF000000U)
#define SPI_FILTER_POPCODE0_PRG_OPCODE0_SHIFT    (24U)
/*! PRG_OPCODE0 - Programmable OP Code 0
 */
#define SPI_FILTER_POPCODE0_PRG_OPCODE0(x)       (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_POPCODE0_PRG_OPCODE0_SHIFT)) & SPI_FILTER_POPCODE0_PRG_OPCODE0_MASK)
/*! @} */

/*! @name POPCODE1 - Programmable OP-Code1 */
/*! @{ */

#define SPI_FILTER_POPCODE1_FILTER_STATE1_MASK   (0x1F0000U)
#define SPI_FILTER_POPCODE1_FILTER_STATE1_SHIFT  (16U)
/*! FILTER_STATE1 - Programmable Filter state 1
 */
#define SPI_FILTER_POPCODE1_FILTER_STATE1(x)     (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_POPCODE1_FILTER_STATE1_SHIFT)) & SPI_FILTER_POPCODE1_FILTER_STATE1_MASK)

#define SPI_FILTER_POPCODE1_FILTER_BIT1_MASK     (0x200000U)
#define SPI_FILTER_POPCODE1_FILTER_BIT1_SHIFT    (21U)
/*! FILTER_BIT1
 *  0b0..Filter after 7th bit for all Commands Op Codes that need to be filtered.
 *  0b1..Filter after 8th bit for all Read/Write Op Codes that are filtered based on the address.
 */
#define SPI_FILTER_POPCODE1_FILTER_BIT1(x)       (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_POPCODE1_FILTER_BIT1_SHIFT)) & SPI_FILTER_POPCODE1_FILTER_BIT1_MASK)

#define SPI_FILTER_POPCODE1_PRG_OPCODE1_MASK     (0xFF000000U)
#define SPI_FILTER_POPCODE1_PRG_OPCODE1_SHIFT    (24U)
/*! PRG_OPCODE1 - Programmable OP Code 1
 */
#define SPI_FILTER_POPCODE1_PRG_OPCODE1(x)       (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_POPCODE1_PRG_OPCODE1_SHIFT)) & SPI_FILTER_POPCODE1_PRG_OPCODE1_MASK)
/*! @} */

/*! @name POPCODE2 - Programmable OP-Code2 */
/*! @{ */

#define SPI_FILTER_POPCODE2_FILTER_STATE2_MASK   (0x1F0000U)
#define SPI_FILTER_POPCODE2_FILTER_STATE2_SHIFT  (16U)
/*! FILTER_STATE2 - Programmable Filter state 2
 */
#define SPI_FILTER_POPCODE2_FILTER_STATE2(x)     (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_POPCODE2_FILTER_STATE2_SHIFT)) & SPI_FILTER_POPCODE2_FILTER_STATE2_MASK)

#define SPI_FILTER_POPCODE2_FILTER_BIT2_MASK     (0x200000U)
#define SPI_FILTER_POPCODE2_FILTER_BIT2_SHIFT    (21U)
/*! FILTER_BIT2
 *  0b0..Filter after 7th bit for all Commands Op Codes that need to be filtered.
 *  0b1..Filter after 8th bit for all Read/Write Op Codes that are filtered based on the address.
 */
#define SPI_FILTER_POPCODE2_FILTER_BIT2(x)       (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_POPCODE2_FILTER_BIT2_SHIFT)) & SPI_FILTER_POPCODE2_FILTER_BIT2_MASK)

#define SPI_FILTER_POPCODE2_PRG_OPCODE2_MASK     (0xFF000000U)
#define SPI_FILTER_POPCODE2_PRG_OPCODE2_SHIFT    (24U)
/*! PRG_OPCODE2 - Programmable OP Code 0
 */
#define SPI_FILTER_POPCODE2_PRG_OPCODE2(x)       (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_POPCODE2_PRG_OPCODE2_SHIFT)) & SPI_FILTER_POPCODE2_PRG_OPCODE2_MASK)
/*! @} */

/*! @name POPCODE3 - Programmable OP-Code3 */
/*! @{ */

#define SPI_FILTER_POPCODE3_FILTER_STATE3_MASK   (0x1F0000U)
#define SPI_FILTER_POPCODE3_FILTER_STATE3_SHIFT  (16U)
/*! FILTER_STATE3 - Programmable Filter state 3
 */
#define SPI_FILTER_POPCODE3_FILTER_STATE3(x)     (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_POPCODE3_FILTER_STATE3_SHIFT)) & SPI_FILTER_POPCODE3_FILTER_STATE3_MASK)

#define SPI_FILTER_POPCODE3_FILTER_BIT3_MASK     (0x200000U)
#define SPI_FILTER_POPCODE3_FILTER_BIT3_SHIFT    (21U)
/*! FILTER_BIT3
 *  0b0..Filter after 7th bit for all Commands Op Codes that need to be filtered.
 *  0b1..Filter after 8th bit for all Read/Write Op Codes that are filtered based on the address.
 */
#define SPI_FILTER_POPCODE3_FILTER_BIT3(x)       (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_POPCODE3_FILTER_BIT3_SHIFT)) & SPI_FILTER_POPCODE3_FILTER_BIT3_MASK)

#define SPI_FILTER_POPCODE3_PRG_OPCODE3_MASK     (0xFF000000U)
#define SPI_FILTER_POPCODE3_PRG_OPCODE3_SHIFT    (24U)
/*! PRG_OPCODE3 - Programmable OP Code 3
 */
#define SPI_FILTER_POPCODE3_PRG_OPCODE3(x)       (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_POPCODE3_PRG_OPCODE3_SHIFT)) & SPI_FILTER_POPCODE3_PRG_OPCODE3_MASK)
/*! @} */

/*! @name POPCODE4 - Programmable OP-Code4 */
/*! @{ */

#define SPI_FILTER_POPCODE4_FILTER_STATE4_MASK   (0x1F0000U)
#define SPI_FILTER_POPCODE4_FILTER_STATE4_SHIFT  (16U)
/*! FILTER_STATE4 - Programmable Filter state 4
 */
#define SPI_FILTER_POPCODE4_FILTER_STATE4(x)     (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_POPCODE4_FILTER_STATE4_SHIFT)) & SPI_FILTER_POPCODE4_FILTER_STATE4_MASK)

#define SPI_FILTER_POPCODE4_FILTER_BIT4_MASK     (0x200000U)
#define SPI_FILTER_POPCODE4_FILTER_BIT4_SHIFT    (21U)
/*! FILTER_BIT4
 *  0b0..Filter after 7th bit for all Commands Op Codes that need to be filtered.
 *  0b1..Filter after 8th bit for all Read/Write Op Codes that are filtered based on the address.
 */
#define SPI_FILTER_POPCODE4_FILTER_BIT4(x)       (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_POPCODE4_FILTER_BIT4_SHIFT)) & SPI_FILTER_POPCODE4_FILTER_BIT4_MASK)

#define SPI_FILTER_POPCODE4_PRG_OPCODE4_MASK     (0xFF000000U)
#define SPI_FILTER_POPCODE4_PRG_OPCODE4_SHIFT    (24U)
/*! PRG_OPCODE4 - Programmable OP Code 4
 */
#define SPI_FILTER_POPCODE4_PRG_OPCODE4(x)       (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_POPCODE4_PRG_OPCODE4_SHIFT)) & SPI_FILTER_POPCODE4_PRG_OPCODE4_MASK)
/*! @} */

/*! @name P0BOC - P0 Blocked Op Code */
/*! @{ */

#define SPI_FILTER_P0BOC_P0BOC_MASK              (0xFF000000U)
#define SPI_FILTER_P0BOC_P0BOC_SHIFT             (24U)
/*! P0BOC - Port 0 Blocked Op Code
 */
#define SPI_FILTER_P0BOC_P0BOC(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P0BOC_P0BOC_SHIFT)) & SPI_FILTER_P0BOC_P0BOC_MASK)
/*! @} */

/*! @name P1BOC - P1 Blocked Op Code */
/*! @{ */

#define SPI_FILTER_P1BOC_P1BOC_MASK              (0xFF000000U)
#define SPI_FILTER_P1BOC_P1BOC_SHIFT             (24U)
/*! P1BOC - Port 1 Blocked Op Code
 */
#define SPI_FILTER_P1BOC_P1BOC(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P1BOC_P1BOC_SHIFT)) & SPI_FILTER_P1BOC_P1BOC_MASK)
/*! @} */

/*! @name P0MAM - Port 0 Max Address Mask */
/*! @{ */

#define SPI_FILTER_P0MAM_P0MAML_MASK             (0xFF0000U)
#define SPI_FILTER_P0MAM_P0MAML_SHIFT            (16U)
/*! P0MAML - Port 0 Max Address Mask LSB
 */
#define SPI_FILTER_P0MAM_P0MAML(x)               (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P0MAM_P0MAML_SHIFT)) & SPI_FILTER_P0MAM_P0MAML_MASK)

#define SPI_FILTER_P0MAM_P0MAMM_MASK             (0xFF000000U)
#define SPI_FILTER_P0MAM_P0MAMM_SHIFT            (24U)
/*! P0MAMM - Port 0 Max Address Mask MSB
 */
#define SPI_FILTER_P0MAM_P0MAMM(x)               (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P0MAM_P0MAMM_SHIFT)) & SPI_FILTER_P0MAM_P0MAMM_MASK)
/*! @} */

/*! @name P1MAM - Port 1 Max Address Mask */
/*! @{ */

#define SPI_FILTER_P1MAM_P1MAML_MASK             (0xFF0000U)
#define SPI_FILTER_P1MAM_P1MAML_SHIFT            (16U)
/*! P1MAML - Port 1 Max Address Mask LSB
 */
#define SPI_FILTER_P1MAM_P1MAML(x)               (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P1MAM_P1MAML_SHIFT)) & SPI_FILTER_P1MAM_P1MAML_MASK)

#define SPI_FILTER_P1MAM_P1MAMM_MASK             (0xFF000000U)
#define SPI_FILTER_P1MAM_P1MAMM_SHIFT            (24U)
/*! P1MAMM - Port 1 Max Address Mask MSB
 */
#define SPI_FILTER_P1MAM_P1MAMM(x)               (((uint32_t)(((uint32_t)(x)) << SPI_FILTER_P1MAM_P1MAMM_SHIFT)) & SPI_FILTER_P1MAM_P1MAMM_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group SPI_FILTER_Register_Masks */


/* SPI_FILTER - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral SPI_FILTER base address */
  #define SPI_FILTER_BASE                          (0x50024000u)
  /** Peripheral SPI_FILTER base address */
  #define SPI_FILTER_BASE_NS                       (0x40024000u)
  /** Peripheral SPI_FILTER base pointer */
  #define SPI_FILTER                               ((SPI_FILTER_Type *)SPI_FILTER_BASE)
  /** Peripheral SPI_FILTER base pointer */
  #define SPI_FILTER_NS                            ((SPI_FILTER_Type *)SPI_FILTER_BASE_NS)
  /** Array initializer of SPI_FILTER peripheral base addresses */
  #define SPI_FILTER_BASE_ADDRS                    { SPI_FILTER_BASE }
  /** Array initializer of SPI_FILTER peripheral base pointers */
  #define SPI_FILTER_BASE_PTRS                     { SPI_FILTER }
  /** Array initializer of SPI_FILTER peripheral base addresses */
  #define SPI_FILTER_BASE_ADDRS_NS                 { SPI_FILTER_BASE_NS }
  /** Array initializer of SPI_FILTER peripheral base pointers */
  #define SPI_FILTER_BASE_PTRS_NS                  { SPI_FILTER_NS }
#else
  /** Peripheral SPI_FILTER base address */
  #define SPI_FILTER_BASE                          (0x40024000u)
  /** Peripheral SPI_FILTER base pointer */
  #define SPI_FILTER                               ((SPI_FILTER_Type *)SPI_FILTER_BASE)
  /** Array initializer of SPI_FILTER peripheral base addresses */
  #define SPI_FILTER_BASE_ADDRS                    { SPI_FILTER_BASE }
  /** Array initializer of SPI_FILTER peripheral base pointers */
  #define SPI_FILTER_BASE_PTRS                     { SPI_FILTER }
#endif

/*!
 * @}
 */ /* end of group SPI_FILTER_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- SYSCON Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer
 * @{
 */

/** SYSCON - Register Layout Typedef */
typedef struct {
  __IO uint32_t MEMORYREMAP;                       /**< Memory Remap Control, offset: 0x0 */
       uint8_t RESERVED_0[12];
  __IO uint32_t AHBMATPRIO;                        /**< AHB Matrix priority control, offset: 0x10 */
  __IO uint32_t AHBMATPRIO1;                       /**< AHB Matrix priority control, offset: 0x14 */
       uint8_t RESERVED_1[32];
  __IO uint32_t CPU0STCKCAL;                       /**< System tick calibration for secure part of CPU0, offset: 0x38 */
  __IO uint32_t CPU0NSTCKCAL;                      /**< System tick calibration for non-secure part of CPU0, offset: 0x3C */
       uint8_t RESERVED_2[8];
  __IO uint32_t NMISRC;                            /**< NMI Source Select, offset: 0x48 */
       uint8_t RESERVED_3[180];
  __IO uint32_t PRESETCTRL0;                       /**< Peripheral reset control 0, offset: 0x100 */
  __IO uint32_t PRESETCTRL1;                       /**< Peripheral reset control 1, offset: 0x104 */
  __IO uint32_t PRESETCTRL2;                       /**< Peripheral reset control 2, offset: 0x108 */
  __IO uint32_t PRESETCTRL3;                       /**< Peripheral reset control 3, offset: 0x10C */
       uint8_t RESERVED_4[16];
  __O  uint32_t PRESETCTRLSET[4];                  /**< Peripheral reset control set n, array offset: 0x120, array step: 0x4 */
       uint8_t RESERVED_5[16];
  __O  uint32_t PRESETCTRLCLR[4];                  /**< Peripheral reset control clear n, array offset: 0x140, array step: 0x4 */
       uint8_t RESERVED_6[16];
  __O  uint32_t SWR_RESET;                         /**< Software Reset, offset: 0x160 */
       uint8_t RESERVED_7[156];
  __IO uint32_t AHBCLKCTRL0;                       /**< AHB Clock control 0, offset: 0x200 */
  __IO uint32_t AHBCLKCTRL1;                       /**< AHB Clock control 1, offset: 0x204 */
  __IO uint32_t AHBCLKCTRL2;                       /**< AHB Clock control 2, offset: 0x208 */
  __IO uint32_t AHBCLKCTRL3;                       /**< AHB Clock Control 3, offset: 0x20C */
       uint8_t RESERVED_8[16];
  __IO uint32_t AHBCLKCTRLSET[4];                  /**< AHB Clock Control Set, array offset: 0x220, array step: 0x4 */
       uint8_t RESERVED_9[16];
  __IO uint32_t AHBCLKCTRLCLR[4];                  /**< AHB Clock Control Clear, array offset: 0x240, array step: 0x4 */
       uint8_t RESERVED_10[16];
  __IO uint32_t SYSTICKCLKSEL0;                    /**< System Tick Timer for CPU0 source select, offset: 0x260 */
       uint8_t RESERVED_11[4];
  __IO uint32_t TRACECLKSEL;                       /**< Trace clock source select, offset: 0x268 */
  __IO uint32_t CTIMERCLKSEL[5];                   /**< CTimer 0 clock source select..CTimer 4 clock source select, array offset: 0x26C, array step: 0x4 */
  __IO uint32_t MAINCLKSELA;                       /**< Main clock source select A, offset: 0x280 */
  __IO uint32_t MAINCLKSELB;                       /**< Main clock source select B, offset: 0x284 */
  __IO uint32_t CLKOUTSEL;                         /**< CLKOUT clock source select, offset: 0x288 */
       uint8_t RESERVED_12[4];
  __IO uint32_t PLL0CLKSEL;                        /**< PLL0 clock source select, offset: 0x290 */
  __IO uint32_t PLL1CLKSEL;                        /**< PLL1 clock source select, offset: 0x294 */
       uint8_t RESERVED_13[8];
  __IO uint32_t CANCLKSEL;                         /**< CAN clock source select, offset: 0x2A0 */
  __IO uint32_t ADC0CLKSEL;                        /**< ADC0 clock source select, offset: 0x2A4 */
  __IO uint32_t USB0CLKSEL;                        /**< FS USB clock source select, offset: 0x2A8 */
       uint8_t RESERVED_14[4];
  __IO uint32_t FCCLKSEL[8];                       /**< Flexcomm 0 clock source select for Fractional Rate Divider..Flexcomm 7 clock source select for Fractional Rate Divider, array offset: 0x2B0, array step: 0x4 */
  __IO uint32_t HSSPICLKSEL;                       /**< HS SPI clock source select, offset: 0x2D0 */
       uint8_t RESERVED_15[12];
  __IO uint32_t MCLKCLKSEL;                        /**< MCLK clock source select, offset: 0x2E0 */
       uint8_t RESERVED_16[12];
  __IO uint32_t SCTCLKSEL;                         /**< SCTimer/PWM clock source select, offset: 0x2F0 */
       uint8_t RESERVED_17[12];
  __IO uint32_t SYSTICKCLKDIV[1];                  /**< System Tick Timer divider for CPU0, array offset: 0x300, array step: 0x4 */
       uint8_t RESERVED_18[4];
  __IO uint32_t TRACECLKDIV;                       /**< TRACE clock divider, offset: 0x308 */
  __IO uint32_t CANCLKDIV;                         /**< CAN clock divider, offset: 0x30C */
       uint8_t RESERVED_19[16];
  __IO uint32_t FRGCTRL[8];                        /**< Fractional rate divider for flexcomm 0..Fractional rate divider for flexcomm 7, array offset: 0x320, array step: 0x4 */
       uint8_t RESERVED_20[64];
  __IO uint32_t AHBCLKDIV;                         /**< System clock divider, offset: 0x380 */
  __IO uint32_t CLKOUTDIV;                         /**< CLKOUT clock divider, offset: 0x384 */
  __IO uint32_t FROHFDIV;                          /**< FRO_HF (96MHz) clock divider, offset: 0x388 */
  __IO uint32_t WDTCLKDIV;                         /**< WDT clock divider, offset: 0x38C */
       uint8_t RESERVED_21[4];
  __IO uint32_t ADC0CLKDIV;                        /**< ADC0 clock divider, offset: 0x394 */
  __IO uint32_t USB0CLKDIV;                        /**< USB0-FS Clock divider, offset: 0x398 */
       uint8_t RESERVED_22[16];
  __IO uint32_t MCLKDIV;                           /**< I2S MCLK clock divider, offset: 0x3AC */
       uint8_t RESERVED_23[4];
  __IO uint32_t SCTCLKDIV;                         /**< SCT/PWM clock divider, offset: 0x3B4 */
       uint8_t RESERVED_24[12];
  __IO uint32_t PLLCLKDIV;                         /**< PLL clock divider, offset: 0x3C4 */
       uint8_t RESERVED_25[8];
  __IO uint32_t CTIMERCLKDIV[5];                   /**< CTimer 0 clock divider..CTimer 4 clock divider, array offset: 0x3D0, array step: 0x4 */
       uint8_t RESERVED_26[24];
  __IO uint32_t CLKUNLOCK;                         /**< Clock configuration unlock, offset: 0x3FC */
  __IO uint32_t FMCCR;                             /**< FMC configuration, offset: 0x400 */
  __IO uint32_t ROMCR;                             /**< ROM wait state, offset: 0x404 */
       uint8_t RESERVED_27[4];
  __IO uint32_t USB0NEEDCLKCTRL;                   /**< USB0-FS need clock control, offset: 0x40C */
  __I  uint32_t USB0NEEDCLKSTAT;                   /**< USB0-FS need clock status, offset: 0x410 */
  __IO uint32_t EZHINT;                            /**< EZH interrupt hijack, offset: 0x414 */
       uint8_t RESERVED_28[4];
  __O  uint32_t FMCFLUSH;                          /**< FMC flush control, offset: 0x41C */
  __IO uint32_t MCLKIO;                            /**< MCLK control, offset: 0x420 */
       uint8_t RESERVED_29[64];
  __IO uint32_t ADC1CLKSEL;                        /**< ADC1 clock source select, offset: 0x464 */
  __IO uint32_t ADC1CLKDIV;                        /**< ADC1 clock divider, offset: 0x468 */
       uint8_t RESERVED_30[4];
  __IO uint32_t RAM_INTERLEAVE;                    /**< Control RAM interleave integration, offset: 0x470 */
       uint8_t RESERVED_31[28];
  struct {                                         /* offset: 0x490, array step: 0x8 */
    __IO uint32_t CLKSEL;                            /**< DAC0 functional clock selection..DAC2 functional clock selection, array offset: 0x490, array step: 0x8 */
    __IO uint32_t CLKDIV;                            /**< DAC0 functional clock divider..DAC2 functional clock divider, array offset: 0x494, array step: 0x8 */
  } DAC[3];
  __IO uint32_t FLEXSPICLKSEL;                     /**< FLEXSPI clock selection, offset: 0x4A8 */
  __IO uint32_t FLEXSPICLKDIV;                     /**< FLEXSPI clock divider, offset: 0x4AC */
  __IO uint32_t CDPA_ENABLE;                       /**< Enable protection, offset: 0x4B0 */
  __IO uint32_t CDPA_ENABLE_DP;                    /**< Enable protection duplicate, offset: 0x4B4 */
  __IO uint32_t CDPA_CONFIG;                       /**< CDPA base address, offset: 0x4B8 */
       uint8_t RESERVED_32[20];
  __IO uint32_t FLASH_HIDING_LOCKOUT_ADDR;         /**< Flash hiding lockout address, offset: 0x4D0 */
  __IO uint32_t FLASH_HIDING_BASE_ADDR;            /**< Flash hiding base address, offset: 0x4D4 */
  __IO uint32_t FLASH_HIDING_BASE_DP_ADDR;         /**< Flash hiding base DP address, offset: 0x4D8 */
  __IO uint32_t FLASH_HIDING_SIZE_ADDR;            /**< Hiding size address, offset: 0x4DC */
  __IO uint32_t FLASH_HIDING_SIZE_DP_ADDR;         /**< Hiding size DP address, offset: 0x4E0 */
       uint8_t RESERVED_33[72];
  __IO uint32_t PLLCLKDIVSEL;                      /**< PLL clock divider clock selection, offset: 0x52C */
  __IO uint32_t I3CFCLKSEL;                        /**< I3C functional clock selection, offset: 0x530 */
  __IO uint32_t I3CFCLKSTCSEL;                     /**< I3C FCLK_STC clock selection, offset: 0x534 */
  __IO uint32_t I3CFCLKSTCDIV;                     /**< I3C FCLK_STC clock divider, offset: 0x538 */
  __IO uint32_t I3CFCLKSDIV;                       /**< I3C FCLKS clock divider, offset: 0x53C */
  __IO uint32_t I3CFCLKDIV;                        /**< I3C FCLK divider, offset: 0x540 */
  __IO uint32_t I3CFCLKSSEL;                       /**< I3C FCLK_S selection, offset: 0x544 */
  __IO uint32_t DMICFCLKSEL;                       /**< DMIC clock selection, offset: 0x548 */
  __IO uint32_t DMICFCLKDIV;                       /**< DMIC clock division, offset: 0x54C */
       uint8_t RESERVED_34[16];
  __IO uint32_t PLL1CTRL;                          /**< PLL1 550m control, offset: 0x560 */
  __I  uint32_t PLL1STAT;                          /**< PLL1 550m status, offset: 0x564 */
  __IO uint32_t PLL1NDEC;                          /**< PLL1 550m N divider, offset: 0x568 */
  __IO uint32_t PLL1MDEC;                          /**< PLL1 550m M divider, offset: 0x56C */
  __IO uint32_t PLL1PDEC;                          /**< PLL1 550m P divider, offset: 0x570 */
       uint8_t RESERVED_35[12];
  __IO uint32_t PLL0CTRL;                          /**< PLL0 550m control, offset: 0x580 */
  __I  uint32_t PLL0STAT;                          /**< PLL0 550m status, offset: 0x584 */
  __IO uint32_t PLL0NDEC;                          /**< PLL0 550m N divider, offset: 0x588 */
  __IO uint32_t PLL0PDEC;                          /**< PLL0 550m P divider, offset: 0x58C */
  __IO uint32_t PLL0SSCG0;                         /**< PLL0 Spread Spectrum control 0, offset: 0x590 */
  __IO uint32_t PLL0SSCG1;                         /**< PLL0 Spread Spectrum control 1, offset: 0x594 */
       uint8_t RESERVED_36[56];
  __IO uint32_t DAC_ISO_CTRL;                      /**< DAC Isolation Control, offset: 0x5D0 */
       uint8_t RESERVED_37[172];
  __IO uint32_t STARTER[4];                        /**< Start logic wake-up enable, array offset: 0x680, array step: 0x4 */
       uint8_t RESERVED_38[16];
  __IO uint32_t STARTERSET[4];                     /**< Set bits in STARTER, array offset: 0x6A0, array step: 0x4 */
       uint8_t RESERVED_39[16];
  __O  uint32_t STARTERCLR[2];                     /**< Clear bits in STARTER, array offset: 0x6C0, array step: 0x4 */
       uint8_t RESERVED_40[60];
  __IO uint32_t FUNCRETENTIONCTRL;                 /**< Functional retention control, offset: 0x704 */
       uint8_t RESERVED_41[120];
  __IO uint32_t HARDWARESLEEP;                     /**< Hardware Sleep control, offset: 0x780 */
       uint8_t RESERVED_42[136];
  __I  uint32_t CPUSTAT;                           /**< CPU Status, offset: 0x80C */
       uint8_t RESERVED_43[20];
  __IO uint32_t LPCAC_CTRL;                        /**< LPCAC control, offset: 0x824 */
       uint8_t RESERVED_44[4];
  __IO uint32_t FC32KCLKSEL;                       /**< Flexcomm 32K clock select, offset: 0x82C */
  __IO uint32_t FRGCLKSEL[8];                      /**< FRG Clock Source Select, array offset: 0x830, array step: 0x4 */
  __IO uint32_t FLEXCOMMCLKDIV[8];                 /**< Flexcomm clock divider, array offset: 0x850, array step: 0x4 */
       uint8_t RESERVED_45[280];
  __IO uint32_t CSS_TEMPORAL_STATE;                /**< CSS temporal state, offset: 0x988 */
  __IO uint32_t CSS_KDF_MASK;                      /**< Key derivation function mask, offset: 0x98C */
  __IO uint32_t CSS_FEATURE0;                      /**< CSS command feature, offset: 0x990 */
  __IO uint32_t CSS_FEATURE1;                      /**< CSS command feature, offset: 0x994 */
  __IO uint32_t CSS_FEATURE0_DP;                   /**< CSS command feature - duplicate version, offset: 0x998 */
  __IO uint32_t CSS_FEATURE1_DP;                   /**< CSS command feature - duplicate version, offset: 0x99C */
       uint8_t RESERVED_46[4];
  __IO uint32_t CSS_BOOT_RETRY_CNT;                /**< CSS boot retry counter, offset: 0x9A4 */
       uint8_t RESERVED_47[8];
  __IO uint32_t CSS_CLK_CTRL;                      /**< CSS clock control, offset: 0x9B0 */
  __O  uint32_t CSS_CLK_CTRL_SET;                  /**< CSS clock control set, offset: 0x9B4 */
  __O  uint32_t CSS_CLK_CTRL_CLR;                  /**< CSS clock control clear, offset: 0x9B8 */
  __IO uint32_t CSS_CLK_SEL;                       /**< CSS clock select, offset: 0x9BC */
       uint8_t RESERVED_48[16];
  __I  uint32_t CSS_AS_CFG0;                       /**< CSS AS configuration, offset: 0x9D0 */
  __I  uint32_t CSS_AS_CFG1;                       /**< CSS AS configuration1, offset: 0x9D4 */
  __I  uint32_t CSS_AS_CFG2;                       /**< CSS AS configuration2, offset: 0x9D8 */
       uint8_t RESERVED_49[4];
  __I  uint32_t CSS_AS_ST0;                        /**< CSS AS state register, offset: 0x9E0 */
  __I  uint32_t CSS_AS_ST1;                        /**< CSS AS state1, offset: 0x9E4 */
  __I  uint32_t CSS_AS_ST2;                        /**< CSS AS state2, offset: 0x9E8 */
       uint8_t RESERVED_50[4];
  __I  uint32_t CSS_AS_FLAG0;                      /**< CSS AS flag0, offset: 0x9F0 */
       uint8_t RESERVED_51[36];
  __IO uint32_t CLOCK_CTRL;                        /**< Clock Control, offset: 0xA18 */
       uint8_t RESERVED_52[244];
  __IO uint32_t COMP_INT_CTRL;                     /**< Comparator Interrupt control, offset: 0xB10 */
  __I  uint32_t COMP_INT_STATUS;                   /**< Comparator Interrupt status, offset: 0xB14 */
       uint8_t RESERVED_53[748];
  __IO uint32_t AUTOCLKGATEOVERRIDE;               /**< Control automatic clock gating, offset: 0xE04 */
  __IO uint32_t GPIOPSYNC;                         /**< GPIO Synchronization, offset: 0xE08 */
       uint8_t RESERVED_54[24];
  __IO uint32_t AUTOCLKGATEOVERRIDE1;              /**< Control automatic clock gating, offset: 0xE24 */
       uint8_t RESERVED_55[8];
  __IO uint32_t ENABLE_MEM_PARITY_ECC_CHECK;       /**< Memory parity ECC enable, offset: 0xE30 */
  __I  uint32_t MEM_PARITY_ECC_ERROR_FLAG;         /**< Memory parity ECC error flag, offset: 0xE34 */
  __IO uint32_t PWM0SUBCTL;                        /**< PWM0 submodule control, offset: 0xE38 */
  __IO uint32_t PWM1SUBCTL;                        /**< PWM1 submodule control, offset: 0xE3C */
  __IO uint32_t CTIMERGLOBALSTARTEN;               /**< CTIMER global start enable, offset: 0xE40 */
       uint8_t RESERVED_56[348];
  __IO uint32_t DEBUG_LOCK_EN;                     /**< Control write access to security, offset: 0xFA0 */
  __IO uint32_t DEBUG_FEATURES;                    /**< Cortex debug features control, offset: 0xFA4 */
  __IO uint32_t DEBUG_FEATURES_DP;                 /**< Cortex debug features control (duplicate), offset: 0xFA8 */
       uint8_t RESERVED_57[8];
  __IO uint32_t SWD_ACCESS_CPU[1];                 /**< CPU0 Software Debug Access, array offset: 0xFB4, array step: 0x4 */
       uint8_t RESERVED_58[8];
  __IO uint32_t DEBUG_AUTH_BEACON;                 /**< Debug authentication BEACON, offset: 0xFC0 */
  __IO uint32_t SWD_ACCESS_DSP;                    /**< DSP Software Debug Access, offset: 0xFC4 */
       uint8_t RESERVED_59[44];
       uint32_t DEVICE_TYPE;                       /**< Device type, offset: 0xFF4 */
  __I  uint32_t DEVICE_ID0;                        /**< Device ID, offset: 0xFF8 */
  __I  uint32_t DIEID;                             /**< Chip revision ID and Number, offset: 0xFFC */
} SYSCON_Type;

/* ----------------------------------------------------------------------------
   -- SYSCON Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SYSCON_Register_Masks SYSCON Register Masks
 * @{
 */

/*! @name MEMORYREMAP - Memory Remap Control */
/*! @{ */

#define SYSCON_MEMORYREMAP_MAP_MASK              (0x3U)
#define SYSCON_MEMORYREMAP_MAP_SHIFT             (0U)
/*! MAP - Select the location of the vector table:
 *  0b00..Vector Table in ROM.
 *  0b01..Vector Table in RAM.
 *  0b1x..Vector Table in Flash.
 */
#define SYSCON_MEMORYREMAP_MAP(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_MEMORYREMAP_MAP_SHIFT)) & SYSCON_MEMORYREMAP_MAP_MASK)
/*! @} */

/*! @name AHBMATPRIO - AHB Matrix priority control */
/*! @{ */

#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_MASK     (0x3U)
#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_SHIFT    (0U)
/*! PRI_CPU0_CBUS - CPU0 C-AHB bus.
 */
#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_MASK)

#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_MASK     (0xCU)
#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_SHIFT    (2U)
/*! PRI_CPU0_SBUS - CPU0 S-AHB bus.
 */
#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_MASK)

#define SYSCON_AHBMATPRIO_PRI_USB_FSD_MASK       (0x300U)
#define SYSCON_AHBMATPRIO_PRI_USB_FSD_SHIFT      (8U)
/*! PRI_USB_FSD - USB0-FS Device.(USB0)
 */
#define SYSCON_AHBMATPRIO_PRI_USB_FSD(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_FSD_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_FSD_MASK)

#define SYSCON_AHBMATPRIO_PRI_SDMA0_MASK         (0xC00U)
#define SYSCON_AHBMATPRIO_PRI_SDMA0_SHIFT        (10U)
/*! PRI_SDMA0 - DMA0 controller priority.
 */
#define SYSCON_AHBMATPRIO_PRI_SDMA0(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDMA0_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDMA0_MASK)

#define SYSCON_AHBMATPRIO_PRI_EZH_B_D_MASK       (0x3000U)
#define SYSCON_AHBMATPRIO_PRI_EZH_B_D_SHIFT      (12U)
/*! PRI_EZH_B_D - EZH B data bus.
 */
#define SYSCON_AHBMATPRIO_PRI_EZH_B_D(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_EZH_B_D_SHIFT)) & SYSCON_AHBMATPRIO_PRI_EZH_B_D_MASK)

#define SYSCON_AHBMATPRIO_PRI_EZH_B_I_MASK       (0xC000U)
#define SYSCON_AHBMATPRIO_PRI_EZH_B_I_SHIFT      (14U)
/*! PRI_EZH_B_I - EZH B instruction bus.
 */
#define SYSCON_AHBMATPRIO_PRI_EZH_B_I(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_EZH_B_I_SHIFT)) & SYSCON_AHBMATPRIO_PRI_EZH_B_I_MASK)

#define SYSCON_AHBMATPRIO_PRI_PQ_MASK            (0xC0000U)
#define SYSCON_AHBMATPRIO_PRI_PQ_SHIFT           (18U)
/*! PRI_PQ - PQ (HW Accelerator).
 */
#define SYSCON_AHBMATPRIO_PRI_PQ(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_PQ_SHIFT)) & SYSCON_AHBMATPRIO_PRI_PQ_MASK)

#define SYSCON_AHBMATPRIO_PRI_CSSV2_MASK         (0x300000U)
#define SYSCON_AHBMATPRIO_PRI_CSSV2_SHIFT        (20U)
/*! PRI_CSSV2 - CSSV2
 */
#define SYSCON_AHBMATPRIO_PRI_CSSV2(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CSSV2_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CSSV2_MASK)

#define SYSCON_AHBMATPRIO_PRI_USB_FS_MASK        (0xC00000U)
#define SYSCON_AHBMATPRIO_PRI_USB_FS_SHIFT       (22U)
/*! PRI_USB_FS - USB-FS host
 */
#define SYSCON_AHBMATPRIO_PRI_USB_FS(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_FS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_FS_MASK)

#define SYSCON_AHBMATPRIO_PRI_SDMA1_MASK         (0x3000000U)
#define SYSCON_AHBMATPRIO_PRI_SDMA1_SHIFT        (24U)
/*! PRI_SDMA1 - DMA1 controller priority.
 */
#define SYSCON_AHBMATPRIO_PRI_SDMA1(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDMA1_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDMA1_MASK)

#define SYSCON_AHBMATPRIO_PRI_MCAN_MASK          (0xC000000U)
#define SYSCON_AHBMATPRIO_PRI_MCAN_SHIFT         (26U)
/*! PRI_MCAN - MCAN
 */
#define SYSCON_AHBMATPRIO_PRI_MCAN(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_MCAN_SHIFT)) & SYSCON_AHBMATPRIO_PRI_MCAN_MASK)

#define SYSCON_AHBMATPRIO_PKC_MASK               (0xC0000000U)
#define SYSCON_AHBMATPRIO_PKC_SHIFT              (30U)
/*! PKC - PKC
 */
#define SYSCON_AHBMATPRIO_PKC(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PKC_SHIFT)) & SYSCON_AHBMATPRIO_PKC_MASK)
/*! @} */

/*! @name AHBMATPRIO1 - AHB Matrix priority control */
/*! @{ */

#define SYSCON_AHBMATPRIO1_DSP_D_MASK            (0xCU)
#define SYSCON_AHBMATPRIO1_DSP_D_SHIFT           (2U)
/*! DSP_D - DSP D bus
 */
#define SYSCON_AHBMATPRIO1_DSP_D(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO1_DSP_D_SHIFT)) & SYSCON_AHBMATPRIO1_DSP_D_MASK)

#define SYSCON_AHBMATPRIO1_DSP_I_MASK            (0x30U)
#define SYSCON_AHBMATPRIO1_DSP_I_SHIFT           (4U)
/*! DSP_I - DSP I bus
 */
#define SYSCON_AHBMATPRIO1_DSP_I(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO1_DSP_I_SHIFT)) & SYSCON_AHBMATPRIO1_DSP_I_MASK)
/*! @} */

/*! @name CPU0STCKCAL - System tick calibration for secure part of CPU0 */
/*! @{ */

#define SYSCON_CPU0STCKCAL_TENMS_MASK            (0xFFFFFFU)
#define SYSCON_CPU0STCKCAL_TENMS_SHIFT           (0U)
/*! TENMS - Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If the value
 *    reads as zero, the calibration value is not known.
 */
#define SYSCON_CPU0STCKCAL_TENMS(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_TENMS_SHIFT)) & SYSCON_CPU0STCKCAL_TENMS_MASK)

#define SYSCON_CPU0STCKCAL_SKEW_MASK             (0x1000000U)
#define SYSCON_CPU0STCKCAL_SKEW_SHIFT            (24U)
/*! SKEW - Indicates whether the TENMS value is exact:
 *  0b0..TENMS value is exact
 *  0b1..TENMS value is inexact, or not given
 */
#define SYSCON_CPU0STCKCAL_SKEW(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_SKEW_SHIFT)) & SYSCON_CPU0STCKCAL_SKEW_MASK)

#define SYSCON_CPU0STCKCAL_NOREF_MASK            (0x2000000U)
#define SYSCON_CPU0STCKCAL_NOREF_SHIFT           (25U)
/*! NOREF - Indicates whether the device provides a reference clock to the processor
 *  0b0..Reference clock provided
 *  0b1..No reference clock provided
 */
#define SYSCON_CPU0STCKCAL_NOREF(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_NOREF_SHIFT)) & SYSCON_CPU0STCKCAL_NOREF_MASK)
/*! @} */

/*! @name CPU0NSTCKCAL - System tick calibration for non-secure part of CPU0 */
/*! @{ */

#define SYSCON_CPU0NSTCKCAL_TENMS_MASK           (0xFFFFFFU)
#define SYSCON_CPU0NSTCKCAL_TENMS_SHIFT          (0U)
/*! TENMS - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the
 *    value reads as zero, the calibration value is not known.
 */
#define SYSCON_CPU0NSTCKCAL_TENMS(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_TENMS_SHIFT)) & SYSCON_CPU0NSTCKCAL_TENMS_MASK)

#define SYSCON_CPU0NSTCKCAL_SKEW_MASK            (0x1000000U)
#define SYSCON_CPU0NSTCKCAL_SKEW_SHIFT           (24U)
/*! SKEW - Indicates whether the TENMS value is exact:
 *  0b0..TENMS value is exact
 *  0b1..TENMS value is inexact, or not given
 */
#define SYSCON_CPU0NSTCKCAL_SKEW(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_SKEW_SHIFT)) & SYSCON_CPU0NSTCKCAL_SKEW_MASK)

#define SYSCON_CPU0NSTCKCAL_NOREF_MASK           (0x2000000U)
#define SYSCON_CPU0NSTCKCAL_NOREF_SHIFT          (25U)
/*! NOREF - Indicates whether the device provides a reference clock to the processor:
 *  0b0..Reference clock provided
 *  0b1..No reference clock provided
 */
#define SYSCON_CPU0NSTCKCAL_NOREF(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_NOREF_SHIFT)) & SYSCON_CPU0NSTCKCAL_NOREF_MASK)
/*! @} */

/*! @name NMISRC - NMI Source Select */
/*! @{ */

#define SYSCON_NMISRC_IRQCPU0_MASK               (0x3FU)
#define SYSCON_NMISRC_IRQCPU0_SHIFT              (0U)
/*! IRQCPU0 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the CPU0, if enabled by NMIENCPU0.
 */
#define SYSCON_NMISRC_IRQCPU0(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU0_SHIFT)) & SYSCON_NMISRC_IRQCPU0_MASK)

#define SYSCON_NMISRC_NMIENCPU0_MASK             (0x80000000U)
#define SYSCON_NMISRC_NMIENCPU0_SHIFT            (31U)
/*! NMIENCPU0 - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQCPU0.
 */
#define SYSCON_NMISRC_NMIENCPU0(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU0_SHIFT)) & SYSCON_NMISRC_NMIENCPU0_MASK)
/*! @} */

/*! @name PRESETCTRL0 - Peripheral reset control 0 */
/*! @{ */

#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_MASK   (0x8U)
#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_SHIFT  (3U)
/*! SRAM_CTRL1_RST - SRAM Controller 1 reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_MASK)

#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_MASK   (0x10U)
#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_SHIFT  (4U)
/*! SRAM_CTRL2_RST - SRAM Controller 2 reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_MASK)

#define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_MASK   (0x20U)
#define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_SHIFT  (5U)
/*! SRAM_CTRL3_RST - SRAM Controller 3 reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_MASK)

#define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_MASK   (0x40U)
#define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_SHIFT  (6U)
/*! SRAM_CTRL4_RST - SRAM Controller 4 reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_MASK)

#define SYSCON_PRESETCTRL0_FLASH_RST_MASK        (0x80U)
#define SYSCON_PRESETCTRL0_FLASH_RST_SHIFT       (7U)
/*! FLASH_RST - Flash controller reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL0_FLASH_RST(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FLASH_RST_SHIFT)) & SYSCON_PRESETCTRL0_FLASH_RST_MASK)

#define SYSCON_PRESETCTRL0_FMC_RST_MASK          (0x100U)
#define SYSCON_PRESETCTRL0_FMC_RST_SHIFT         (8U)
/*! FMC_RST - FMC controller reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL0_FMC_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FMC_RST_SHIFT)) & SYSCON_PRESETCTRL0_FMC_RST_MASK)

#define SYSCON_PRESETCTRL0_FLEXSPI_RST_MASK      (0x400U)
#define SYSCON_PRESETCTRL0_FLEXSPI_RST_SHIFT     (10U)
/*! FLEXSPI_RST - FLEXSPI reset control
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL0_FLEXSPI_RST(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FLEXSPI_RST_SHIFT)) & SYSCON_PRESETCTRL0_FLEXSPI_RST_MASK)

#define SYSCON_PRESETCTRL0_IOCON_RST_MASK        (0x2000U)
#define SYSCON_PRESETCTRL0_IOCON_RST_SHIFT       (13U)
/*! IOCON_RST - I/O controller reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL0_IOCON_RST(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_IOCON_RST_SHIFT)) & SYSCON_PRESETCTRL0_IOCON_RST_MASK)

#define SYSCON_PRESETCTRL0_GPIO0_RST_MASK        (0x4000U)
#define SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT       (14U)
/*! GPIO0_RST - GPIO0 reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL0_GPIO0_RST(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO0_RST_MASK)

#define SYSCON_PRESETCTRL0_GPIO1_RST_MASK        (0x8000U)
#define SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT       (15U)
/*! GPIO1_RST - GPIO1 reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL0_GPIO1_RST(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO1_RST_MASK)

#define SYSCON_PRESETCTRL0_GPIO2_RST_MASK        (0x10000U)
#define SYSCON_PRESETCTRL0_GPIO2_RST_SHIFT       (16U)
/*! GPIO2_RST - GPIO2 reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL0_GPIO2_RST(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO2_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO2_RST_MASK)

#define SYSCON_PRESETCTRL0_GPIO3_RST_MASK        (0x20000U)
#define SYSCON_PRESETCTRL0_GPIO3_RST_SHIFT       (17U)
/*! GPIO3_RST - GPIO3 reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL0_GPIO3_RST(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO3_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO3_RST_MASK)

#define SYSCON_PRESETCTRL0_PINT_RST_MASK         (0x40000U)
#define SYSCON_PRESETCTRL0_PINT_RST_SHIFT        (18U)
/*! PINT_RST - Pin interrupt (PINT) reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL0_PINT_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_PINT_RST_MASK)

#define SYSCON_PRESETCTRL0_GINT_RST_MASK         (0x80000U)
#define SYSCON_PRESETCTRL0_GINT_RST_SHIFT        (19U)
/*! GINT_RST - Group interrupt (GINT) reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL0_GINT_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_GINT_RST_MASK)

#define SYSCON_PRESETCTRL0_DMA0_RST_MASK         (0x100000U)
#define SYSCON_PRESETCTRL0_DMA0_RST_SHIFT        (20U)
/*! DMA0_RST - DMA0 reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL0_DMA0_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_DMA0_RST_SHIFT)) & SYSCON_PRESETCTRL0_DMA0_RST_MASK)

#define SYSCON_PRESETCTRL0_CRCGEN_RST_MASK       (0x200000U)
#define SYSCON_PRESETCTRL0_CRCGEN_RST_SHIFT      (21U)
/*! CRCGEN_RST - CRCGEN reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL0_CRCGEN_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_CRCGEN_RST_SHIFT)) & SYSCON_PRESETCTRL0_CRCGEN_RST_MASK)

#define SYSCON_PRESETCTRL0_WWDT_RST_MASK         (0x400000U)
#define SYSCON_PRESETCTRL0_WWDT_RST_SHIFT        (22U)
/*! WWDT_RST - Watchdog Timer reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL0_WWDT_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_WWDT_RST_SHIFT)) & SYSCON_PRESETCTRL0_WWDT_RST_MASK)

#define SYSCON_PRESETCTRL0_RTC_RST_MASK          (0x800000U)
#define SYSCON_PRESETCTRL0_RTC_RST_SHIFT         (23U)
/*! RTC_RST - Real Time Clock (RTC) reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL0_RTC_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_RTC_RST_SHIFT)) & SYSCON_PRESETCTRL0_RTC_RST_MASK)

#define SYSCON_PRESETCTRL0_MAILBOX_RST_MASK      (0x4000000U)
#define SYSCON_PRESETCTRL0_MAILBOX_RST_SHIFT     (26U)
/*! MAILBOX_RST - Inter CPU communication Mailbox reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL0_MAILBOX_RST(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MAILBOX_RST_SHIFT)) & SYSCON_PRESETCTRL0_MAILBOX_RST_MASK)

#define SYSCON_PRESETCTRL0_ADC0_RST_MASK         (0x8000000U)
#define SYSCON_PRESETCTRL0_ADC0_RST_SHIFT        (27U)
/*! ADC0_RST - ADC0 reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL0_ADC0_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_ADC0_RST_SHIFT)) & SYSCON_PRESETCTRL0_ADC0_RST_MASK)

#define SYSCON_PRESETCTRL0_ADC1_RST_MASK         (0x10000000U)
#define SYSCON_PRESETCTRL0_ADC1_RST_SHIFT        (28U)
/*! ADC1_RST - ADC1 reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL0_ADC1_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_ADC1_RST_SHIFT)) & SYSCON_PRESETCTRL0_ADC1_RST_MASK)

#define SYSCON_PRESETCTRL0_DAC0_RST_MASK         (0x20000000U)
#define SYSCON_PRESETCTRL0_DAC0_RST_SHIFT        (29U)
/*! DAC0_RST - DAC0 reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL0_DAC0_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_DAC0_RST_SHIFT)) & SYSCON_PRESETCTRL0_DAC0_RST_MASK)
/*! @} */

/*! @name PRESETCTRL1 - Peripheral reset control 1 */
/*! @{ */

#define SYSCON_PRESETCTRL1_MRT_RST_MASK          (0x1U)
#define SYSCON_PRESETCTRL1_MRT_RST_SHIFT         (0U)
/*! MRT_RST - MRT reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL1_MRT_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_MRT_RST_SHIFT)) & SYSCON_PRESETCTRL1_MRT_RST_MASK)

#define SYSCON_PRESETCTRL1_OSTIMER_RST_MASK      (0x2U)
#define SYSCON_PRESETCTRL1_OSTIMER_RST_SHIFT     (1U)
/*! OSTIMER_RST - OS Event Timer reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL1_OSTIMER_RST(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_OSTIMER_RST_SHIFT)) & SYSCON_PRESETCTRL1_OSTIMER_RST_MASK)

#define SYSCON_PRESETCTRL1_SCT_RST_MASK          (0x4U)
#define SYSCON_PRESETCTRL1_SCT_RST_SHIFT         (2U)
/*! SCT_RST - SCT reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL1_SCT_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_SCT_RST_SHIFT)) & SYSCON_PRESETCTRL1_SCT_RST_MASK)

#define SYSCON_PRESETCTRL1_CAN_RST_MASK          (0x80U)
#define SYSCON_PRESETCTRL1_CAN_RST_SHIFT         (7U)
/*! CAN_RST - CAN reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL1_CAN_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_CAN_RST_SHIFT)) & SYSCON_PRESETCTRL1_CAN_RST_MASK)

#define SYSCON_PRESETCTRL1_UTICK_RST_MASK        (0x400U)
#define SYSCON_PRESETCTRL1_UTICK_RST_SHIFT       (10U)
/*! UTICK_RST - UTICK reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL1_UTICK_RST(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_UTICK_RST_SHIFT)) & SYSCON_PRESETCTRL1_UTICK_RST_MASK)

#define SYSCON_PRESETCTRL1_FC0_RST_MASK          (0x800U)
#define SYSCON_PRESETCTRL1_FC0_RST_SHIFT         (11U)
/*! FC0_RST - FC0 reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL1_FC0_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC0_RST_MASK)

#define SYSCON_PRESETCTRL1_FC1_RST_MASK          (0x1000U)
#define SYSCON_PRESETCTRL1_FC1_RST_SHIFT         (12U)
/*! FC1_RST - FC1 reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL1_FC1_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC1_RST_MASK)

#define SYSCON_PRESETCTRL1_FC2_RST_MASK          (0x2000U)
#define SYSCON_PRESETCTRL1_FC2_RST_SHIFT         (13U)
/*! FC2_RST - FC2 reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL1_FC2_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC2_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC2_RST_MASK)

#define SYSCON_PRESETCTRL1_FC3_RST_MASK          (0x4000U)
#define SYSCON_PRESETCTRL1_FC3_RST_SHIFT         (14U)
/*! FC3_RST - FC3 reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL1_FC3_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC3_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC3_RST_MASK)

#define SYSCON_PRESETCTRL1_FC4_RST_MASK          (0x8000U)
#define SYSCON_PRESETCTRL1_FC4_RST_SHIFT         (15U)
/*! FC4_RST - FC4 reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL1_FC4_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC4_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC4_RST_MASK)

#define SYSCON_PRESETCTRL1_FC5_RST_MASK          (0x10000U)
#define SYSCON_PRESETCTRL1_FC5_RST_SHIFT         (16U)
/*! FC5_RST - FC5 reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL1_FC5_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC5_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC5_RST_MASK)

#define SYSCON_PRESETCTRL1_FC6_RST_MASK          (0x20000U)
#define SYSCON_PRESETCTRL1_FC6_RST_SHIFT         (17U)
/*! FC6_RST - FC6 reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL1_FC6_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC6_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC6_RST_MASK)

#define SYSCON_PRESETCTRL1_FC7_RST_MASK          (0x40000U)
#define SYSCON_PRESETCTRL1_FC7_RST_SHIFT         (18U)
/*! FC7_RST - FC7 reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL1_FC7_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC7_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC7_RST_MASK)

#define SYSCON_PRESETCTRL1_DMIC_RST_MASK         (0x80000U)
#define SYSCON_PRESETCTRL1_DMIC_RST_SHIFT        (19U)
/*! DMIC_RST - DMIC reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL1_DMIC_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_DMIC_RST_SHIFT)) & SYSCON_PRESETCTRL1_DMIC_RST_MASK)

#define SYSCON_PRESETCTRL1_TIMER2_RST_MASK       (0x400000U)
#define SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT      (22U)
/*! TIMER2_RST - Timer 2 reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL1_TIMER2_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER2_RST_MASK)

#define SYSCON_PRESETCTRL1_USB0_DEV_RST_MASK     (0x2000000U)
#define SYSCON_PRESETCTRL1_USB0_DEV_RST_SHIFT    (25U)
/*! USB0_DEV_RST - USB0-FS DEV reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL1_USB0_DEV_RST(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_USB0_DEV_RST_SHIFT)) & SYSCON_PRESETCTRL1_USB0_DEV_RST_MASK)

#define SYSCON_PRESETCTRL1_TIMER0_RST_MASK       (0x4000000U)
#define SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT      (26U)
/*! TIMER0_RST - Timer 0 reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL1_TIMER0_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER0_RST_MASK)

#define SYSCON_PRESETCTRL1_TIMER1_RST_MASK       (0x8000000U)
#define SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT      (27U)
/*! TIMER1_RST - Timer 1 reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL1_TIMER1_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER1_RST_MASK)

#define SYSCON_PRESETCTRL1_EZHA_RST_MASK         (0x40000000U)
#define SYSCON_PRESETCTRL1_EZHA_RST_SHIFT        (30U)
/*! EZHA_RST - EZH a reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL1_EZHA_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_EZHA_RST_SHIFT)) & SYSCON_PRESETCTRL1_EZHA_RST_MASK)

#define SYSCON_PRESETCTRL1_EZHB_RST_MASK         (0x80000000U)
#define SYSCON_PRESETCTRL1_EZHB_RST_SHIFT        (31U)
/*! EZHB_RST - EZH b reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL1_EZHB_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_EZHB_RST_SHIFT)) & SYSCON_PRESETCTRL1_EZHB_RST_MASK)
/*! @} */

/*! @name PRESETCTRL2 - Peripheral reset control 2 */
/*! @{ */

#define SYSCON_PRESETCTRL2_DMA1_RST_MASK         (0x2U)
#define SYSCON_PRESETCTRL2_DMA1_RST_SHIFT        (1U)
/*! DMA1_RST - DMA1 reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL2_DMA1_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_DMA1_RST_SHIFT)) & SYSCON_PRESETCTRL2_DMA1_RST_MASK)

#define SYSCON_PRESETCTRL2_COMP_RST_MASK         (0x4U)
#define SYSCON_PRESETCTRL2_COMP_RST_SHIFT        (2U)
/*! COMP_RST - Analog comparator reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL2_COMP_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_COMP_RST_SHIFT)) & SYSCON_PRESETCTRL2_COMP_RST_MASK)

#define SYSCON_PRESETCTRL2_FREQME_RST_MASK       (0x100U)
#define SYSCON_PRESETCTRL2_FREQME_RST_SHIFT      (8U)
/*! FREQME_RST - Frequency meter reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL2_FREQME_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_FREQME_RST_SHIFT)) & SYSCON_PRESETCTRL2_FREQME_RST_MASK)

#define SYSCON_PRESETCTRL2_RNG_RST_MASK          (0x2000U)
#define SYSCON_PRESETCTRL2_RNG_RST_SHIFT         (13U)
/*! RNG_RST - RNG reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL2_RNG_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_RNG_RST_SHIFT)) & SYSCON_PRESETCTRL2_RNG_RST_MASK)

#define SYSCON_PRESETCTRL2_SYSCTL_RST_MASK       (0x8000U)
#define SYSCON_PRESETCTRL2_SYSCTL_RST_SHIFT      (15U)
/*! SYSCTL_RST - SYSCTL Block reset.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL2_SYSCTL_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_SYSCTL_RST_SHIFT)) & SYSCON_PRESETCTRL2_SYSCTL_RST_MASK)

#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST_MASK   (0x10000U)
#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST_SHIFT  (16U)
/*! USB0_HOSTM_RST - USB0-FS Host Master reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB0_HOSTM_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB0_HOSTM_RST_MASK)

#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST_MASK   (0x20000U)
#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST_SHIFT  (17U)
/*! USB0_HOSTS_RST - USB0-FS Host Slave reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB0_HOSTS_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB0_HOSTS_RST_MASK)

#define SYSCON_PRESETCTRL2_CSS_RST_MASK          (0x40000U)
#define SYSCON_PRESETCTRL2_CSS_RST_SHIFT         (18U)
/*! CSS_RST - CSS reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL2_CSS_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_CSS_RST_SHIFT)) & SYSCON_PRESETCTRL2_CSS_RST_MASK)

#define SYSCON_PRESETCTRL2_PQ_RST_MASK           (0x80000U)
#define SYSCON_PRESETCTRL2_PQ_RST_SHIFT          (19U)
/*! PQ_RST - Power Quad reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL2_PQ_RST(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PQ_RST_SHIFT)) & SYSCON_PRESETCTRL2_PQ_RST_MASK)

#define SYSCON_PRESETCTRL2_TIMER3_RST_MASK       (0x200000U)
#define SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT      (21U)
/*! TIMER3_RST - Timer 3 reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL2_TIMER3_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER3_RST_MASK)

#define SYSCON_PRESETCTRL2_TIMER4_RST_MASK       (0x400000U)
#define SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT      (22U)
/*! TIMER4_RST - Timer 4 reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL2_TIMER4_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER4_RST_MASK)

#define SYSCON_PRESETCTRL2_PUF_RST_MASK          (0x800000U)
#define SYSCON_PRESETCTRL2_PUF_RST_SHIFT         (23U)
/*! PUF_RST - PUF reset control reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL2_PUF_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PUF_RST_SHIFT)) & SYSCON_PRESETCTRL2_PUF_RST_MASK)

#define SYSCON_PRESETCTRL2_PKC_RST_MASK          (0x1000000U)
#define SYSCON_PRESETCTRL2_PKC_RST_SHIFT         (24U)
/*! PKC_RST - PKC reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.g
 */
#define SYSCON_PRESETCTRL2_PKC_RST(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PKC_RST_SHIFT)) & SYSCON_PRESETCTRL2_PKC_RST_MASK)

#define SYSCON_PRESETCTRL2_ANACTRL_RST_MASK      (0x8000000U)
#define SYSCON_PRESETCTRL2_ANACTRL_RST_SHIFT     (27U)
/*! ANACTRL_RST - Analog control reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL2_ANACTRL_RST(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_ANACTRL_RST_SHIFT)) & SYSCON_PRESETCTRL2_ANACTRL_RST_MASK)

#define SYSCON_PRESETCTRL2_HS_SPI_RST_MASK       (0x10000000U)
#define SYSCON_PRESETCTRL2_HS_SPI_RST_SHIFT      (28U)
/*! HS_SPI_RST - HS SPI reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL2_HS_SPI_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_HS_SPI_RST_SHIFT)) & SYSCON_PRESETCTRL2_HS_SPI_RST_MASK)

#define SYSCON_PRESETCTRL2_GPIO_SEC_RST_MASK     (0x20000000U)
#define SYSCON_PRESETCTRL2_GPIO_SEC_RST_SHIFT    (29U)
/*! GPIO_SEC_RST - GPIO secure reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL2_GPIO_SEC_RST(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO_SEC_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO_SEC_RST_MASK)

#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_MASK (0x40000000U)
#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_SHIFT (30U)
/*! GPIO_SEC_INT_RST - GPIO secure int reset control.
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_MASK)
/*! @} */

/*! @name PRESETCTRL3 - Peripheral reset control 3 */
/*! @{ */

#define SYSCON_PRESETCTRL3_I3C0_RST_MASK         (0x1U)
#define SYSCON_PRESETCTRL3_I3C0_RST_SHIFT        (0U)
/*! I3C0_RST - I3C reset control
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL3_I3C0_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_I3C0_RST_SHIFT)) & SYSCON_PRESETCTRL3_I3C0_RST_MASK)

#define SYSCON_PRESETCTRL3_ENC0_RST_MASK         (0x8U)
#define SYSCON_PRESETCTRL3_ENC0_RST_SHIFT        (3U)
/*! ENC0_RST - ENC0 reset control
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL3_ENC0_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_ENC0_RST_SHIFT)) & SYSCON_PRESETCTRL3_ENC0_RST_MASK)

#define SYSCON_PRESETCTRL3_ENC1_RST_MASK         (0x10U)
#define SYSCON_PRESETCTRL3_ENC1_RST_SHIFT        (4U)
/*! ENC1_RST - ENC1 reset control
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL3_ENC1_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_ENC1_RST_SHIFT)) & SYSCON_PRESETCTRL3_ENC1_RST_MASK)

#define SYSCON_PRESETCTRL3_PWM0_RST_MASK         (0x20U)
#define SYSCON_PRESETCTRL3_PWM0_RST_SHIFT        (5U)
/*! PWM0_RST - PWM0 reset control
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL3_PWM0_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_PWM0_RST_SHIFT)) & SYSCON_PRESETCTRL3_PWM0_RST_MASK)

#define SYSCON_PRESETCTRL3_PWM1_RST_MASK         (0x40U)
#define SYSCON_PRESETCTRL3_PWM1_RST_SHIFT        (6U)
/*! PWM1_RST - PWM1 reset control
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL3_PWM1_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_PWM1_RST_SHIFT)) & SYSCON_PRESETCTRL3_PWM1_RST_MASK)

#define SYSCON_PRESETCTRL3_AOI0_RST_MASK         (0x80U)
#define SYSCON_PRESETCTRL3_AOI0_RST_SHIFT        (7U)
/*! AOI0_RST - AOI0 reset control
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL3_AOI0_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_AOI0_RST_SHIFT)) & SYSCON_PRESETCTRL3_AOI0_RST_MASK)

#define SYSCON_PRESETCTRL3_AOI1_RST_MASK         (0x100U)
#define SYSCON_PRESETCTRL3_AOI1_RST_SHIFT        (8U)
/*! AOI1_RST - AOI1 reset control
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL3_AOI1_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_AOI1_RST_SHIFT)) & SYSCON_PRESETCTRL3_AOI1_RST_MASK)

#define SYSCON_PRESETCTRL3_FTM0_RST_MASK         (0x200U)
#define SYSCON_PRESETCTRL3_FTM0_RST_SHIFT        (9U)
/*! FTM0_RST - FTM0 reset control
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL3_FTM0_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_FTM0_RST_SHIFT)) & SYSCON_PRESETCTRL3_FTM0_RST_MASK)

#define SYSCON_PRESETCTRL3_DAC1_RST_MASK         (0x400U)
#define SYSCON_PRESETCTRL3_DAC1_RST_SHIFT        (10U)
/*! DAC1_RST - DAC1 reset control
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL3_DAC1_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_DAC1_RST_SHIFT)) & SYSCON_PRESETCTRL3_DAC1_RST_MASK)

#define SYSCON_PRESETCTRL3_DAC2_RST_MASK         (0x800U)
#define SYSCON_PRESETCTRL3_DAC2_RST_SHIFT        (11U)
/*! DAC2_RST - DAC2 reset control
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL3_DAC2_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_DAC2_RST_SHIFT)) & SYSCON_PRESETCTRL3_DAC2_RST_MASK)

#define SYSCON_PRESETCTRL3_OPAMP0_RST_MASK       (0x1000U)
#define SYSCON_PRESETCTRL3_OPAMP0_RST_SHIFT      (12U)
/*! OPAMP0_RST - OPAMP0 reset control
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL3_OPAMP0_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_OPAMP0_RST_SHIFT)) & SYSCON_PRESETCTRL3_OPAMP0_RST_MASK)

#define SYSCON_PRESETCTRL3_OPAMP1_RST_MASK       (0x2000U)
#define SYSCON_PRESETCTRL3_OPAMP1_RST_SHIFT      (13U)
/*! OPAMP1_RST - OPAMP1 reset control
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL3_OPAMP1_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_OPAMP1_RST_SHIFT)) & SYSCON_PRESETCTRL3_OPAMP1_RST_MASK)

#define SYSCON_PRESETCTRL3_OPAMP2_RST_MASK       (0x4000U)
#define SYSCON_PRESETCTRL3_OPAMP2_RST_SHIFT      (14U)
/*! OPAMP2_RST - OPAMP2 reset control
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL3_OPAMP2_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_OPAMP2_RST_SHIFT)) & SYSCON_PRESETCTRL3_OPAMP2_RST_MASK)

#define SYSCON_PRESETCTRL3_HSCMP0_RST_MASK       (0x8000U)
#define SYSCON_PRESETCTRL3_HSCMP0_RST_SHIFT      (15U)
/*! HSCMP0_RST - HSCMP0 reset control
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL3_HSCMP0_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_HSCMP0_RST_SHIFT)) & SYSCON_PRESETCTRL3_HSCMP0_RST_MASK)

#define SYSCON_PRESETCTRL3_HSCMP1_RST_MASK       (0x10000U)
#define SYSCON_PRESETCTRL3_HSCMP1_RST_SHIFT      (16U)
/*! HSCMP1_RST - HSCMP1 reset control
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL3_HSCMP1_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_HSCMP1_RST_SHIFT)) & SYSCON_PRESETCTRL3_HSCMP1_RST_MASK)

#define SYSCON_PRESETCTRL3_HSCMP2_RST_MASK       (0x20000U)
#define SYSCON_PRESETCTRL3_HSCMP2_RST_SHIFT      (17U)
/*! HSCMP2_RST - HSCMP2 reset control
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL3_HSCMP2_RST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_HSCMP2_RST_SHIFT)) & SYSCON_PRESETCTRL3_HSCMP2_RST_MASK)

#define SYSCON_PRESETCTRL3_VREF_RST_MASK         (0x40000U)
#define SYSCON_PRESETCTRL3_VREF_RST_SHIFT        (18U)
/*! VREF_RST - VREF reset control
 *  0b1..Block is reset.
 *  0b0..Block is not reset.
 */
#define SYSCON_PRESETCTRL3_VREF_RST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_VREF_RST_SHIFT)) & SYSCON_PRESETCTRL3_VREF_RST_MASK)
/*! @} */

/*! @name PRESETCTRLSET - Peripheral reset control set n */
/*! @{ */

#define SYSCON_PRESETCTRLSET_DATA_MASK           (0xFFFFFFFFU)
#define SYSCON_PRESETCTRLSET_DATA_SHIFT          (0U)
/*! DATA - Data array value
 */
#define SYSCON_PRESETCTRLSET_DATA(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_DATA_SHIFT)) & SYSCON_PRESETCTRLSET_DATA_MASK)

#define SYSCON_PRESETCTRLSET_DATA_L_MASK         (0x7FFU)
#define SYSCON_PRESETCTRLSET_DATA_L_SHIFT        (0U)
/*! DATA_L - Data array value
 */
#define SYSCON_PRESETCTRLSET_DATA_L(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_DATA_L_SHIFT)) & SYSCON_PRESETCTRLSET_DATA_L_MASK)

#define SYSCON_PRESETCTRLSET_DATA_U_MASK         (0xFFFFF000U)
#define SYSCON_PRESETCTRLSET_DATA_U_SHIFT        (12U)
/*! DATA_U - Data array value
 */
#define SYSCON_PRESETCTRLSET_DATA_U(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_DATA_U_SHIFT)) & SYSCON_PRESETCTRLSET_DATA_U_MASK)
/*! @} */

/* The count of SYSCON_PRESETCTRLSET */
#define SYSCON_PRESETCTRLSET_COUNT               (4U)

/*! @name PRESETCTRLCLR - Peripheral reset control clear n */
/*! @{ */

#define SYSCON_PRESETCTRLCLR_DATA_MASK           (0xFFFFFFFFU)
#define SYSCON_PRESETCTRLCLR_DATA_SHIFT          (0U)
/*! DATA - Data array value
 */
#define SYSCON_PRESETCTRLCLR_DATA(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_DATA_SHIFT)) & SYSCON_PRESETCTRLCLR_DATA_MASK)

#define SYSCON_PRESETCTRLCLR_DATA_L_MASK         (0x7FFU)
#define SYSCON_PRESETCTRLCLR_DATA_L_SHIFT        (0U)
/*! DATA_L - Data array value
 */
#define SYSCON_PRESETCTRLCLR_DATA_L(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_DATA_L_SHIFT)) & SYSCON_PRESETCTRLCLR_DATA_L_MASK)

#define SYSCON_PRESETCTRLCLR_DATA_U_MASK         (0xFFFFF000U)
#define SYSCON_PRESETCTRLCLR_DATA_U_SHIFT        (12U)
/*! DATA_U - Data array value
 */
#define SYSCON_PRESETCTRLCLR_DATA_U(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_DATA_U_SHIFT)) & SYSCON_PRESETCTRLCLR_DATA_U_MASK)
/*! @} */

/* The count of SYSCON_PRESETCTRLCLR */
#define SYSCON_PRESETCTRLCLR_COUNT               (4U)

/*! @name SWR_RESET - Software Reset */
/*! @{ */

#define SYSCON_SWR_RESET_SWR_RESET_MASK          (0xFFFFFFFFU)
#define SYSCON_SWR_RESET_SWR_RESET_SHIFT         (0U)
/*! SWR_RESET - Write 0x5A00_0001 to generate a software_reset.
 */
#define SYSCON_SWR_RESET_SWR_RESET(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_SWR_RESET_SWR_RESET_SHIFT)) & SYSCON_SWR_RESET_SWR_RESET_MASK)
/*! @} */

/*! @name AHBCLKCTRL0 - AHB Clock control 0 */
/*! @{ */

#define SYSCON_AHBCLKCTRL0_ROM_MASK              (0x2U)
#define SYSCON_AHBCLKCTRL0_ROM_SHIFT             (1U)
/*! ROM - Enables the clock for the ROM.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL0_ROM(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ROM_SHIFT)) & SYSCON_AHBCLKCTRL0_ROM_MASK)

#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK       (0x8U)
#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT      (3U)
/*! SRAM_CTRL1 - Enables the clock for the SRAM Controller 1.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK)

#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK       (0x10U)
#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2_SHIFT      (4U)
/*! SRAM_CTRL2 - Enables the clock for the SRAM Controller 2.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL2_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK)

#define SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK       (0x20U)
#define SYSCON_AHBCLKCTRL0_SRAM_CTRL3_SHIFT      (5U)
/*! SRAM_CTRL3 - Enables the clock for the SRAM Controller 3.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL0_SRAM_CTRL3(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL3_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK)

#define SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK       (0x40U)
#define SYSCON_AHBCLKCTRL0_SRAM_CTRL4_SHIFT      (6U)
/*! SRAM_CTRL4 - Enables the clock for the SRAM Controller 4.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL0_SRAM_CTRL4(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL4_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK)

#define SYSCON_AHBCLKCTRL0_FLASH_MASK            (0x80U)
#define SYSCON_AHBCLKCTRL0_FLASH_SHIFT           (7U)
/*! FLASH - Enables the clock for the Flash controller.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL0_FLASH(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FLASH_SHIFT)) & SYSCON_AHBCLKCTRL0_FLASH_MASK)

#define SYSCON_AHBCLKCTRL0_FMC_MASK              (0x100U)
#define SYSCON_AHBCLKCTRL0_FMC_SHIFT             (8U)
/*! FMC - Enables the clock for the FMC controller.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL0_FMC(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FMC_SHIFT)) & SYSCON_AHBCLKCTRL0_FMC_MASK)

#define SYSCON_AHBCLKCTRL0_FLEXSPI_MASK          (0x400U)
#define SYSCON_AHBCLKCTRL0_FLEXSPI_SHIFT         (10U)
/*! FLEXSPI - Enables the clock for the Flexspi.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL0_FLEXSPI(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FLEXSPI_SHIFT)) & SYSCON_AHBCLKCTRL0_FLEXSPI_MASK)

#define SYSCON_AHBCLKCTRL0_MUX_MASK              (0x800U)
#define SYSCON_AHBCLKCTRL0_MUX_SHIFT             (11U)
/*! MUX - Enables the clock for the Input Mux.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL0_MUX(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MUX_SHIFT)) & SYSCON_AHBCLKCTRL0_MUX_MASK)

#define SYSCON_AHBCLKCTRL0_IOCON_MASK            (0x2000U)
#define SYSCON_AHBCLKCTRL0_IOCON_SHIFT           (13U)
/*! IOCON - Enables the clock for the I/O controller.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL0_IOCON(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_IOCON_SHIFT)) & SYSCON_AHBCLKCTRL0_IOCON_MASK)

#define SYSCON_AHBCLKCTRL0_GPIO0_MASK            (0x4000U)
#define SYSCON_AHBCLKCTRL0_GPIO0_SHIFT           (14U)
/*! GPIO0 - Enables the clock for the GPIO0.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL0_GPIO0(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO0_MASK)

#define SYSCON_AHBCLKCTRL0_GPIO1_MASK            (0x8000U)
#define SYSCON_AHBCLKCTRL0_GPIO1_SHIFT           (15U)
/*! GPIO1 - Enables the clock for the GPIO1.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL0_GPIO1(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO1_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO1_MASK)

#define SYSCON_AHBCLKCTRL0_GPIO2_MASK            (0x10000U)
#define SYSCON_AHBCLKCTRL0_GPIO2_SHIFT           (16U)
/*! GPIO2 - Enables the clock for the GPIO2.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL0_GPIO2(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO2_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO2_MASK)

#define SYSCON_AHBCLKCTRL0_GPIO3_MASK            (0x20000U)
#define SYSCON_AHBCLKCTRL0_GPIO3_SHIFT           (17U)
/*! GPIO3 - Enables the clock for the GPIO3.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL0_GPIO3(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO3_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO3_MASK)

#define SYSCON_AHBCLKCTRL0_PINT_MASK             (0x40000U)
#define SYSCON_AHBCLKCTRL0_PINT_SHIFT            (18U)
/*! PINT - Enables the clock for the Pin interrupt (PINT).
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL0_PINT(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PINT_SHIFT)) & SYSCON_AHBCLKCTRL0_PINT_MASK)

#define SYSCON_AHBCLKCTRL0_GINT_MASK             (0x80000U)
#define SYSCON_AHBCLKCTRL0_GINT_SHIFT            (19U)
/*! GINT - Enables the clock for the Group interrupt (GINT).
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL0_GINT(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GINT_SHIFT)) & SYSCON_AHBCLKCTRL0_GINT_MASK)

#define SYSCON_AHBCLKCTRL0_DMA0_MASK             (0x100000U)
#define SYSCON_AHBCLKCTRL0_DMA0_SHIFT            (20U)
/*! DMA0 - Enables the clock for the DMA0.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL0_DMA0(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_DMA0_SHIFT)) & SYSCON_AHBCLKCTRL0_DMA0_MASK)

#define SYSCON_AHBCLKCTRL0_CRCGEN_MASK           (0x200000U)
#define SYSCON_AHBCLKCTRL0_CRCGEN_SHIFT          (21U)
/*! CRCGEN - Enables the clock for the CRCGEN.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL0_CRCGEN(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_CRCGEN_SHIFT)) & SYSCON_AHBCLKCTRL0_CRCGEN_MASK)

#define SYSCON_AHBCLKCTRL0_WWDT_MASK             (0x400000U)
#define SYSCON_AHBCLKCTRL0_WWDT_SHIFT            (22U)
/*! WWDT - Enables the clock for the Watchdog Timer.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL0_WWDT(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_WWDT_SHIFT)) & SYSCON_AHBCLKCTRL0_WWDT_MASK)

#define SYSCON_AHBCLKCTRL0_RTC_MASK              (0x800000U)
#define SYSCON_AHBCLKCTRL0_RTC_SHIFT             (23U)
/*! RTC - Enables the clock for the Real Time Clock (RTC).
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL0_RTC(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RTC_SHIFT)) & SYSCON_AHBCLKCTRL0_RTC_MASK)

#define SYSCON_AHBCLKCTRL0_MAILBOX_MASK          (0x4000000U)
#define SYSCON_AHBCLKCTRL0_MAILBOX_SHIFT         (26U)
/*! MAILBOX - Enables the clock for the Inter CPU communication Mailbox.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL0_MAILBOX(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MAILBOX_SHIFT)) & SYSCON_AHBCLKCTRL0_MAILBOX_MASK)

#define SYSCON_AHBCLKCTRL0_ADC0_MASK             (0x8000000U)
#define SYSCON_AHBCLKCTRL0_ADC0_SHIFT            (27U)
/*! ADC0 - Enables the clock for ADC0.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL0_ADC0(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ADC0_SHIFT)) & SYSCON_AHBCLKCTRL0_ADC0_MASK)

#define SYSCON_AHBCLKCTRL0_ADC1_MASK             (0x10000000U)
#define SYSCON_AHBCLKCTRL0_ADC1_SHIFT            (28U)
/*! ADC1 - Enables the clock for ADC1.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL0_ADC1(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ADC1_SHIFT)) & SYSCON_AHBCLKCTRL0_ADC1_MASK)

#define SYSCON_AHBCLKCTRL0_DAC0_MASK             (0x20000000U)
#define SYSCON_AHBCLKCTRL0_DAC0_SHIFT            (29U)
/*! DAC0 - Enables the clock for DAC0.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL0_DAC0(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_DAC0_SHIFT)) & SYSCON_AHBCLKCTRL0_DAC0_MASK)
/*! @} */

/*! @name AHBCLKCTRL1 - AHB Clock control 1 */
/*! @{ */

#define SYSCON_AHBCLKCTRL1_MRT_MASK              (0x1U)
#define SYSCON_AHBCLKCTRL1_MRT_SHIFT             (0U)
/*! MRT - Enables the clock for the MRT.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL1_MRT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_MRT_SHIFT)) & SYSCON_AHBCLKCTRL1_MRT_MASK)

#define SYSCON_AHBCLKCTRL1_OSTIMER_MASK          (0x2U)
#define SYSCON_AHBCLKCTRL1_OSTIMER_SHIFT         (1U)
/*! OSTIMER - Enables the clock for the OS Event Timer.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL1_OSTIMER(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_OSTIMER_SHIFT)) & SYSCON_AHBCLKCTRL1_OSTIMER_MASK)

#define SYSCON_AHBCLKCTRL1_SCT_MASK              (0x4U)
#define SYSCON_AHBCLKCTRL1_SCT_SHIFT             (2U)
/*! SCT - Enables the clock for the SCT.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL1_SCT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_SCT_SHIFT)) & SYSCON_AHBCLKCTRL1_SCT_MASK)

#define SYSCON_AHBCLKCTRL1_CAN_MASK              (0x80U)
#define SYSCON_AHBCLKCTRL1_CAN_SHIFT             (7U)
/*! CAN - Enables the clock for the CAN.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL1_CAN(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_CAN_SHIFT)) & SYSCON_AHBCLKCTRL1_CAN_MASK)

#define SYSCON_AHBCLKCTRL1_UTICK_MASK            (0x400U)
#define SYSCON_AHBCLKCTRL1_UTICK_SHIFT           (10U)
/*! UTICK - Enables the clock for the UTICK.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL1_UTICK(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_UTICK_SHIFT)) & SYSCON_AHBCLKCTRL1_UTICK_MASK)

#define SYSCON_AHBCLKCTRL1_FC0_MASK              (0x800U)
#define SYSCON_AHBCLKCTRL1_FC0_SHIFT             (11U)
/*! FC0 - Enables the clock for the FC0.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL1_FC0(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC0_SHIFT)) & SYSCON_AHBCLKCTRL1_FC0_MASK)

#define SYSCON_AHBCLKCTRL1_FC1_MASK              (0x1000U)
#define SYSCON_AHBCLKCTRL1_FC1_SHIFT             (12U)
/*! FC1 - Enables the clock for the FC1.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL1_FC1(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC1_SHIFT)) & SYSCON_AHBCLKCTRL1_FC1_MASK)

#define SYSCON_AHBCLKCTRL1_FC2_MASK              (0x2000U)
#define SYSCON_AHBCLKCTRL1_FC2_SHIFT             (13U)
/*! FC2 - Enables the clock for the FC2.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL1_FC2(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC2_SHIFT)) & SYSCON_AHBCLKCTRL1_FC2_MASK)

#define SYSCON_AHBCLKCTRL1_FC3_MASK              (0x4000U)
#define SYSCON_AHBCLKCTRL1_FC3_SHIFT             (14U)
/*! FC3 - Enables the clock for the FC3.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL1_FC3(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC3_SHIFT)) & SYSCON_AHBCLKCTRL1_FC3_MASK)

#define SYSCON_AHBCLKCTRL1_FC4_MASK              (0x8000U)
#define SYSCON_AHBCLKCTRL1_FC4_SHIFT             (15U)
/*! FC4 - Enables the clock for the FC4.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL1_FC4(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC4_SHIFT)) & SYSCON_AHBCLKCTRL1_FC4_MASK)

#define SYSCON_AHBCLKCTRL1_FC5_MASK              (0x10000U)
#define SYSCON_AHBCLKCTRL1_FC5_SHIFT             (16U)
/*! FC5 - Enables the clock for the FC5.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL1_FC5(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC5_SHIFT)) & SYSCON_AHBCLKCTRL1_FC5_MASK)

#define SYSCON_AHBCLKCTRL1_FC6_MASK              (0x20000U)
#define SYSCON_AHBCLKCTRL1_FC6_SHIFT             (17U)
/*! FC6 - Enables the clock for the FC6.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL1_FC6(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC6_SHIFT)) & SYSCON_AHBCLKCTRL1_FC6_MASK)

#define SYSCON_AHBCLKCTRL1_FC7_MASK              (0x40000U)
#define SYSCON_AHBCLKCTRL1_FC7_SHIFT             (18U)
/*! FC7 - Enables the clock for the FC7.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL1_FC7(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC7_SHIFT)) & SYSCON_AHBCLKCTRL1_FC7_MASK)

#define SYSCON_AHBCLKCTRL1_DMIC_MASK             (0x80000U)
#define SYSCON_AHBCLKCTRL1_DMIC_SHIFT            (19U)
/*! DMIC - Enables the clock for DMIC.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL1_DMIC(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_DMIC_SHIFT)) & SYSCON_AHBCLKCTRL1_DMIC_MASK)

#define SYSCON_AHBCLKCTRL1_TIMER2_MASK           (0x400000U)
#define SYSCON_AHBCLKCTRL1_TIMER2_SHIFT          (22U)
/*! TIMER2 - Enables the clock for the Timer 2.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL1_TIMER2(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER2_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER2_MASK)

#define SYSCON_AHBCLKCTRL1_USB0_DEV_MASK         (0x2000000U)
#define SYSCON_AHBCLKCTRL1_USB0_DEV_SHIFT        (25U)
/*! USB0_DEV - Enables the clock for the USB0-FS device.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL1_USB0_DEV(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_USB0_DEV_SHIFT)) & SYSCON_AHBCLKCTRL1_USB0_DEV_MASK)

#define SYSCON_AHBCLKCTRL1_TIMER0_MASK           (0x4000000U)
#define SYSCON_AHBCLKCTRL1_TIMER0_SHIFT          (26U)
/*! TIMER0 - Enables the clock for the Timer 0.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL1_TIMER0(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER0_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER0_MASK)

#define SYSCON_AHBCLKCTRL1_TIMER1_MASK           (0x8000000U)
#define SYSCON_AHBCLKCTRL1_TIMER1_SHIFT          (27U)
/*! TIMER1 - Enables the clock for the Timer 1.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL1_TIMER1(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER1_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER1_MASK)

#define SYSCON_AHBCLKCTRL1_EZHA_MASK             (0x40000000U)
#define SYSCON_AHBCLKCTRL1_EZHA_SHIFT            (30U)
/*! EZHA - Enables the clock for the EZH a.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL1_EZHA(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_EZHA_SHIFT)) & SYSCON_AHBCLKCTRL1_EZHA_MASK)

#define SYSCON_AHBCLKCTRL1_EZHB_MASK             (0x80000000U)
#define SYSCON_AHBCLKCTRL1_EZHB_SHIFT            (31U)
/*! EZHB - Enables the clock for the EZH b.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL1_EZHB(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_EZHB_SHIFT)) & SYSCON_AHBCLKCTRL1_EZHB_MASK)
/*! @} */

/*! @name AHBCLKCTRL2 - AHB Clock control 2 */
/*! @{ */

#define SYSCON_AHBCLKCTRL2_DMA1_MASK             (0x2U)
#define SYSCON_AHBCLKCTRL2_DMA1_SHIFT            (1U)
/*! DMA1 - Enables the clock for the DMA1.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL2_DMA1(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_DMA1_SHIFT)) & SYSCON_AHBCLKCTRL2_DMA1_MASK)

#define SYSCON_AHBCLKCTRL2_COMP_MASK             (0x4U)
#define SYSCON_AHBCLKCTRL2_COMP_SHIFT            (2U)
/*! COMP - Enables the clock for the Analog comparator.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL2_COMP(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_COMP_SHIFT)) & SYSCON_AHBCLKCTRL2_COMP_MASK)

#define SYSCON_AHBCLKCTRL2_FREQME_MASK           (0x100U)
#define SYSCON_AHBCLKCTRL2_FREQME_SHIFT          (8U)
/*! FREQME - Enables the clock for the Frequency meter.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL2_FREQME(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_FREQME_SHIFT)) & SYSCON_AHBCLKCTRL2_FREQME_MASK)

#define SYSCON_AHBCLKCTRL2_RNG_MASK              (0x2000U)
#define SYSCON_AHBCLKCTRL2_RNG_SHIFT             (13U)
/*! RNG - Enables the clock for the RNG.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL2_RNG(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_RNG_SHIFT)) & SYSCON_AHBCLKCTRL2_RNG_MASK)

#define SYSCON_AHBCLKCTRL2_PMUX1_MASK            (0x4000U)
#define SYSCON_AHBCLKCTRL2_PMUX1_SHIFT           (14U)
/*! PMUX1 - Enables the clock for Peripheral Input Mux 1.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL2_PMUX1(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PMUX1_SHIFT)) & SYSCON_AHBCLKCTRL2_PMUX1_MASK)

#define SYSCON_AHBCLKCTRL2_SYSCTL_MASK           (0x8000U)
#define SYSCON_AHBCLKCTRL2_SYSCTL_SHIFT          (15U)
/*! SYSCTL - SYSCTL block clock.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL2_SYSCTL(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SYSCTL_SHIFT)) & SYSCON_AHBCLKCTRL2_SYSCTL_MASK)

#define SYSCON_AHBCLKCTRL2_USB0_HOSTM_MASK       (0x10000U)
#define SYSCON_AHBCLKCTRL2_USB0_HOSTM_SHIFT      (16U)
/*! USB0_HOSTM - Enables the clock for the USB0-FS Host Master.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL2_USB0_HOSTM(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB0_HOSTM_SHIFT)) & SYSCON_AHBCLKCTRL2_USB0_HOSTM_MASK)

#define SYSCON_AHBCLKCTRL2_USB0_HOSTS_MASK       (0x20000U)
#define SYSCON_AHBCLKCTRL2_USB0_HOSTS_SHIFT      (17U)
/*! USB0_HOSTS - Enables the clock for the USB0-FS Host Slave.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL2_USB0_HOSTS(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB0_HOSTS_SHIFT)) & SYSCON_AHBCLKCTRL2_USB0_HOSTS_MASK)

#define SYSCON_AHBCLKCTRL2_CSS_MASK              (0x40000U)
#define SYSCON_AHBCLKCTRL2_CSS_SHIFT             (18U)
/*! CSS - Enables the clock for CSS.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL2_CSS(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_CSS_SHIFT)) & SYSCON_AHBCLKCTRL2_CSS_MASK)

#define SYSCON_AHBCLKCTRL2_PQ_MASK               (0x80000U)
#define SYSCON_AHBCLKCTRL2_PQ_SHIFT              (19U)
/*! PQ - Enables the clock for the Power Quad.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL2_PQ(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PQ_SHIFT)) & SYSCON_AHBCLKCTRL2_PQ_MASK)

#define SYSCON_AHBCLKCTRL2_TIMER3_MASK           (0x200000U)
#define SYSCON_AHBCLKCTRL2_TIMER3_SHIFT          (21U)
/*! TIMER3 - Enables the clock for the Timer 3.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL2_TIMER3(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER3_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER3_MASK)

#define SYSCON_AHBCLKCTRL2_TIMER4_MASK           (0x400000U)
#define SYSCON_AHBCLKCTRL2_TIMER4_SHIFT          (22U)
/*! TIMER4 - Enables the clock for the Timer 4.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL2_TIMER4(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER4_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER4_MASK)

#define SYSCON_AHBCLKCTRL2_PUF_MASK              (0x800000U)
#define SYSCON_AHBCLKCTRL2_PUF_SHIFT             (23U)
/*! PUF - Enables the clock for the PUF reset control.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL2_PUF(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PUF_SHIFT)) & SYSCON_AHBCLKCTRL2_PUF_MASK)

#define SYSCON_AHBCLKCTRL2_PKC_MASK              (0x1000000U)
#define SYSCON_AHBCLKCTRL2_PKC_SHIFT             (24U)
/*! PKC - Enables the clock for the PKC.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL2_PKC(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PKC_SHIFT)) & SYSCON_AHBCLKCTRL2_PKC_MASK)

#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK      (0x8000000U)
#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL_SHIFT     (27U)
/*! ANALOG_CTRL - Enables the clock for the Analog Controller block.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_ANALOG_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK)

#define SYSCON_AHBCLKCTRL2_HS_SPI_MASK           (0x10000000U)
#define SYSCON_AHBCLKCTRL2_HS_SPI_SHIFT          (28U)
/*! HS_SPI - Enables the clock for the HS SPI.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL2_HS_SPI(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_HS_SPI_SHIFT)) & SYSCON_AHBCLKCTRL2_HS_SPI_MASK)

#define SYSCON_AHBCLKCTRL2_GPIO_SEC_MASK         (0x20000000U)
#define SYSCON_AHBCLKCTRL2_GPIO_SEC_SHIFT        (29U)
/*! GPIO_SEC - Enables the clock for the GPIO secure.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL2_GPIO_SEC(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO_SEC_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO_SEC_MASK)

#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_MASK     (0x40000000U)
#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_SHIFT    (30U)
/*! GPIO_SEC_INT - Enables the clock for the GPIO secure int.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_MASK)
/*! @} */

/*! @name AHBCLKCTRL3 - AHB Clock Control 3 */
/*! @{ */

#define SYSCON_AHBCLKCTRL3_I3C0_MASK             (0x1U)
#define SYSCON_AHBCLKCTRL3_I3C0_SHIFT            (0U)
/*! I3C0 - Enables the clock for I3C0.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL3_I3C0(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_I3C0_SHIFT)) & SYSCON_AHBCLKCTRL3_I3C0_MASK)

#define SYSCON_AHBCLKCTRL3_ENC0_MASK             (0x8U)
#define SYSCON_AHBCLKCTRL3_ENC0_SHIFT            (3U)
/*! ENC0 - Enables the clock for ENC0.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL3_ENC0(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_ENC0_SHIFT)) & SYSCON_AHBCLKCTRL3_ENC0_MASK)

#define SYSCON_AHBCLKCTRL3_ENC1_MASK             (0x10U)
#define SYSCON_AHBCLKCTRL3_ENC1_SHIFT            (4U)
/*! ENC1 - Enables the clock for ENC1.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL3_ENC1(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_ENC1_SHIFT)) & SYSCON_AHBCLKCTRL3_ENC1_MASK)

#define SYSCON_AHBCLKCTRL3_PWM0_MASK             (0x20U)
#define SYSCON_AHBCLKCTRL3_PWM0_SHIFT            (5U)
/*! PWM0 - Enables the clock for PWM0.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL3_PWM0(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_PWM0_SHIFT)) & SYSCON_AHBCLKCTRL3_PWM0_MASK)

#define SYSCON_AHBCLKCTRL3_PWM1_MASK             (0x40U)
#define SYSCON_AHBCLKCTRL3_PWM1_SHIFT            (6U)
/*! PWM1 - Enables the clock for PWM1.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL3_PWM1(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_PWM1_SHIFT)) & SYSCON_AHBCLKCTRL3_PWM1_MASK)

#define SYSCON_AHBCLKCTRL3_AOI0_MASK             (0x80U)
#define SYSCON_AHBCLKCTRL3_AOI0_SHIFT            (7U)
/*! AOI0 - Enables the clock for AOI0.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL3_AOI0(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_AOI0_SHIFT)) & SYSCON_AHBCLKCTRL3_AOI0_MASK)

#define SYSCON_AHBCLKCTRL3_AOI1_MASK             (0x100U)
#define SYSCON_AHBCLKCTRL3_AOI1_SHIFT            (8U)
/*! AOI1 - Enables the clock for AOI1.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL3_AOI1(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_AOI1_SHIFT)) & SYSCON_AHBCLKCTRL3_AOI1_MASK)

#define SYSCON_AHBCLKCTRL3_FTM0_MASK             (0x200U)
#define SYSCON_AHBCLKCTRL3_FTM0_SHIFT            (9U)
/*! FTM0 - Enables the clock for FTM0.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL3_FTM0(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_FTM0_SHIFT)) & SYSCON_AHBCLKCTRL3_FTM0_MASK)

#define SYSCON_AHBCLKCTRL3_DAC1_MASK             (0x400U)
#define SYSCON_AHBCLKCTRL3_DAC1_SHIFT            (10U)
/*! DAC1 - Enables the clock for DAC1.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL3_DAC1(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_DAC1_SHIFT)) & SYSCON_AHBCLKCTRL3_DAC1_MASK)

#define SYSCON_AHBCLKCTRL3_DAC2_MASK             (0x800U)
#define SYSCON_AHBCLKCTRL3_DAC2_SHIFT            (11U)
/*! DAC2 - Enables the clock for DAC2.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL3_DAC2(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_DAC2_SHIFT)) & SYSCON_AHBCLKCTRL3_DAC2_MASK)

#define SYSCON_AHBCLKCTRL3_OPAMP0_MASK           (0x1000U)
#define SYSCON_AHBCLKCTRL3_OPAMP0_SHIFT          (12U)
/*! OPAMP0 - Enables the clock for OPAMP0.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL3_OPAMP0(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_OPAMP0_SHIFT)) & SYSCON_AHBCLKCTRL3_OPAMP0_MASK)

#define SYSCON_AHBCLKCTRL3_OPAMP1_MASK           (0x2000U)
#define SYSCON_AHBCLKCTRL3_OPAMP1_SHIFT          (13U)
/*! OPAMP1 - Enables the clock for OPAMP1.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL3_OPAMP1(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_OPAMP1_SHIFT)) & SYSCON_AHBCLKCTRL3_OPAMP1_MASK)

#define SYSCON_AHBCLKCTRL3_OPAMP2_MASK           (0x4000U)
#define SYSCON_AHBCLKCTRL3_OPAMP2_SHIFT          (14U)
/*! OPAMP2 - Enables the clock for OPAMP2.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL3_OPAMP2(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_OPAMP2_SHIFT)) & SYSCON_AHBCLKCTRL3_OPAMP2_MASK)

#define SYSCON_AHBCLKCTRL3_HSCMP0_MASK           (0x8000U)
#define SYSCON_AHBCLKCTRL3_HSCMP0_SHIFT          (15U)
/*! HSCMP0 - Enables the clock for HSCMP0.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL3_HSCMP0(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_HSCMP0_SHIFT)) & SYSCON_AHBCLKCTRL3_HSCMP0_MASK)

#define SYSCON_AHBCLKCTRL3_HSCMP1_MASK           (0x10000U)
#define SYSCON_AHBCLKCTRL3_HSCMP1_SHIFT          (16U)
/*! HSCMP1 - Enables the clock for HSCMP1.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL3_HSCMP1(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_HSCMP1_SHIFT)) & SYSCON_AHBCLKCTRL3_HSCMP1_MASK)

#define SYSCON_AHBCLKCTRL3_HSCMP2_MASK           (0x20000U)
#define SYSCON_AHBCLKCTRL3_HSCMP2_SHIFT          (17U)
/*! HSCMP2 - Enables the clock for HSCMP2.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL3_HSCMP2(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_HSCMP2_SHIFT)) & SYSCON_AHBCLKCTRL3_HSCMP2_MASK)

#define SYSCON_AHBCLKCTRL3_VREF_MASK             (0x40000U)
#define SYSCON_AHBCLKCTRL3_VREF_SHIFT            (18U)
/*! VREF - Enables the clock for VREF.
 *  0b1..Enable Clock.
 *  0b0..Disable Clock.
 */
#define SYSCON_AHBCLKCTRL3_VREF(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_VREF_SHIFT)) & SYSCON_AHBCLKCTRL3_VREF_MASK)
/*! @} */

/*! @name AHBCLKCTRLSET - AHB Clock Control Set */
/*! @{ */

#define SYSCON_AHBCLKCTRLSET_DATA_MASK           (0xFFFFFFFFU)
#define SYSCON_AHBCLKCTRLSET_DATA_SHIFT          (0U)
/*! DATA - Data array value
 */
#define SYSCON_AHBCLKCTRLSET_DATA(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_DATA_SHIFT)) & SYSCON_AHBCLKCTRLSET_DATA_MASK)
/*! @} */

/* The count of SYSCON_AHBCLKCTRLSET */
#define SYSCON_AHBCLKCTRLSET_COUNT               (4U)

/*! @name AHBCLKCTRLCLR - AHB Clock Control Clear */
/*! @{ */

#define SYSCON_AHBCLKCTRLCLR_DATA_MASK           (0xFFFFFFFFU)
#define SYSCON_AHBCLKCTRLCLR_DATA_SHIFT          (0U)
/*! DATA - Data array value
 */
#define SYSCON_AHBCLKCTRLCLR_DATA(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_DATA_SHIFT)) & SYSCON_AHBCLKCTRLCLR_DATA_MASK)
/*! @} */

/* The count of SYSCON_AHBCLKCTRLCLR */
#define SYSCON_AHBCLKCTRLCLR_COUNT               (4U)

/*! @name SYSTICKCLKSEL0 - System Tick Timer for CPU0 source select */
/*! @{ */

#define SYSCON_SYSTICKCLKSEL0_SEL_MASK           (0x7U)
#define SYSCON_SYSTICKCLKSEL0_SEL_SHIFT          (0U)
/*! SEL - System Tick Timer for CPU0 source select.
 *  0b000..System Tick 0 divided clock.
 *  0b001..FRO 1MHz clock.
 *  0b010..Oscillator 32 kHz clock.
 *  0b011..No clock.
 *  0b100..No clock.
 *  0b101..No clock.
 *  0b110..No clock.
 *  0b111..No clock.
 */
#define SYSCON_SYSTICKCLKSEL0_SEL(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSEL0_SEL_SHIFT)) & SYSCON_SYSTICKCLKSEL0_SEL_MASK)
/*! @} */

/*! @name TRACECLKSEL - Trace clock source select */
/*! @{ */

#define SYSCON_TRACECLKSEL_SEL_MASK              (0x7U)
#define SYSCON_TRACECLKSEL_SEL_SHIFT             (0U)
/*! SEL - Trace clock source select.
 *  0b000..Trace divided clock.
 *  0b001..FRO 1MHz clock.
 *  0b010..Oscillator 32 kHz clock.
 *  0b011..No clock.
 *  0b100..No clock.
 *  0b101..No clock.
 *  0b110..No clock.
 *  0b111..No clock.
 */
#define SYSCON_TRACECLKSEL_SEL(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKSEL_SEL_SHIFT)) & SYSCON_TRACECLKSEL_SEL_MASK)
/*! @} */

/*! @name CTIMERCLKSEL - CTimer 0 clock source select..CTimer 4 clock source select */
/*! @{ */

#define SYSCON_CTIMERCLKSEL_SEL_MASK             (0x7U)
#define SYSCON_CTIMERCLKSEL_SEL_SHIFT            (0U)
/*! SEL - CTimer 4 clock source select.
 *  0b000..Main clock.
 *  0b001..PLL0 clock.
 *  0b010..PLL1 clock.
 *  0b011..FRO 96 MHz clock.
 *  0b100..FRO 1MHz clock.
 *  0b101..MCLK clock.
 *  0b110..Oscillator 32kHz clock.
 *  0b111..No clock.
 */
#define SYSCON_CTIMERCLKSEL_SEL(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL_SEL_MASK)
/*! @} */

/* The count of SYSCON_CTIMERCLKSEL */
#define SYSCON_CTIMERCLKSEL_COUNT                (5U)

/*! @name MAINCLKSELA - Main clock source select A */
/*! @{ */

#define SYSCON_MAINCLKSELA_SEL_MASK              (0x7U)
#define SYSCON_MAINCLKSELA_SEL_SHIFT             (0U)
/*! SEL - Main clock source select A
 *  0b000..FRO 12 MHz clock.
 *  0b001..CLKIN clock.
 *  0b010..FRO 1MHz clock.
 *  0b011..FRO 96 MHz clock.
 *  0b100..Reserved.
 *  0b101..Reserved.
 *  0b110..Reserved.
 *  0b111..Reserved.
 */
#define SYSCON_MAINCLKSELA_SEL(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELA_SEL_SHIFT)) & SYSCON_MAINCLKSELA_SEL_MASK)
/*! @} */

/*! @name MAINCLKSELB - Main clock source select B */
/*! @{ */

#define SYSCON_MAINCLKSELB_SEL_MASK              (0x7U)
#define SYSCON_MAINCLKSELB_SEL_SHIFT             (0U)
/*! SEL - Main clock source select B
 *  0b000..Use the source selected in MAINCLKSELA.
 *  0b001..PLL0 clock.
 *  0b010..PLL1 clock.
 *  0b011..Oscillator 32 kHz clock.
 *  0b100..Reserved.
 *  0b101..Reserved.
 *  0b110..Reserved.
 *  0b111..Reserved.
 */
#define SYSCON_MAINCLKSELB_SEL(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELB_SEL_SHIFT)) & SYSCON_MAINCLKSELB_SEL_MASK)
/*! @} */

/*! @name CLKOUTSEL - CLKOUT clock source select */
/*! @{ */

#define SYSCON_CLKOUTSEL_SEL_MASK                (0xFU)
#define SYSCON_CLKOUTSEL_SEL_SHIFT               (0U)
/*! SEL - CLKOUT clock source select.
 *  0b0000..Main clock.
 *  0b0001..PLL0 clock.
 *  0b0010..CLKIN clock.
 *  0b0011..FRO 96 MHz clock.
 *  0b0100..FRO 1MHz clock.
 *  0b0101..PLL1 clock.
 *  0b0110..Oscillator 32kHz clock.
 *  0b0111..No clock.
 *  0b1000..Reserved.
 *  0b1001..Reserved.
 *  0b1010..Reserved.
 *  0b1011..Reserved.
 *  0b1100..No clock.
 *  0b1101..No clock.
 *  0b1110..No clock.
 *  0b1111..No clock.
 */
#define SYSCON_CLKOUTSEL_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSEL_SEL_SHIFT)) & SYSCON_CLKOUTSEL_SEL_MASK)
/*! @} */

/*! @name PLL0CLKSEL - PLL0 clock source select */
/*! @{ */

#define SYSCON_PLL0CLKSEL_SEL_MASK               (0x7U)
#define SYSCON_PLL0CLKSEL_SEL_SHIFT              (0U)
/*! SEL - PLL0 clock source select.
 *  0b000..FRO 12 MHz clock.
 *  0b001..CLKIN clock.
 *  0b010..FRO 1MHz clock.
 *  0b011..Oscillator 32kHz clock.
 *  0b100..No clock.
 *  0b101..No clock.
 *  0b110..No clock.
 *  0b111..No clock.
 */
#define SYSCON_PLL0CLKSEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKSEL_SEL_SHIFT)) & SYSCON_PLL0CLKSEL_SEL_MASK)
/*! @} */

/*! @name PLL1CLKSEL - PLL1 clock source select */
/*! @{ */

#define SYSCON_PLL1CLKSEL_SEL_MASK               (0x7U)
#define SYSCON_PLL1CLKSEL_SEL_SHIFT              (0U)
/*! SEL - PLL1 clock source select.
 *  0b000..FRO 12 MHz clock.
 *  0b001..CLKIN clock.
 *  0b010..FRO 1MHz clock.
 *  0b011..Oscillator 32kHz clock.
 *  0b100..No clock.
 *  0b101..No clock.
 *  0b110..No clock.
 *  0b111..No clock.
 */
#define SYSCON_PLL1CLKSEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLKSEL_SEL_SHIFT)) & SYSCON_PLL1CLKSEL_SEL_MASK)
/*! @} */

/*! @name CANCLKSEL - CAN clock source select */
/*! @{ */

#define SYSCON_CANCLKSEL_SEL_MASK                (0x7U)
#define SYSCON_CANCLKSEL_SEL_SHIFT               (0U)
/*! SEL - CAN clock source select.
 *  0b000..CAN divided clock.
 *  0b001..FRO 1MHz clock.
 *  0b010..Oscillator 32 kHz clock.
 *  0b011..No clock.
 *  0b100..No clock.
 *  0b101..No clock.
 *  0b110..No clock.
 *  0b111..No clock.
 */
#define SYSCON_CANCLKSEL_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_CANCLKSEL_SEL_SHIFT)) & SYSCON_CANCLKSEL_SEL_MASK)
/*! @} */

/*! @name ADC0CLKSEL - ADC0 clock source select */
/*! @{ */

#define SYSCON_ADC0CLKSEL_SEL_MASK               (0x7U)
#define SYSCON_ADC0CLKSEL_SEL_SHIFT              (0U)
/*! SEL - ADC clock source select.
 *  0b000..Main clock.
 *  0b001..PLL0 clock.
 *  0b010..FRO 96 MHz clock.
 *  0b011..Reserved.
 *  0b100..XO to ADC Clock.
 *  0b101..No clock.
 *  0b110..No clock.
 *  0b111..No clock.
 */
#define SYSCON_ADC0CLKSEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC0CLKSEL_SEL_SHIFT)) & SYSCON_ADC0CLKSEL_SEL_MASK)
/*! @} */

/*! @name USB0CLKSEL - FS USB clock source select */
/*! @{ */

#define SYSCON_USB0CLKSEL_SEL_MASK               (0x7U)
#define SYSCON_USB0CLKSEL_SEL_SHIFT              (0U)
/*! SEL - FS USB clock source select.
 *  0b000..Main clock.
 *  0b001..PLL0 clock.
 *  0b010..No clock.
 *  0b011..FRO 96 MHz clock.
 *  0b100..No clock.
 *  0b101..PLL1 clock.
 *  0b110..No clock.
 *  0b111..No clock.
 */
#define SYSCON_USB0CLKSEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSEL_SEL_SHIFT)) & SYSCON_USB0CLKSEL_SEL_MASK)
/*! @} */

/*! @name FCCLKSEL - Flexcomm 0 clock source select for Fractional Rate Divider..Flexcomm 7 clock source select for Fractional Rate Divider */
/*! @{ */

#define SYSCON_FCCLKSEL_SEL_MASK                 (0x7U)
#define SYSCON_FCCLKSEL_SEL_SHIFT                (0U)
/*! SEL - Flexcomm 7 clock source select for Fractional Rate Divider.
 *  0b000..Main clock.
 *  0b001..system PLL divided clock.
 *  0b010..FRO 12 MHz clock.
 *  0b011..FRO 96 MHz clock.
 *  0b100..FRO 1MHz clock.
 *  0b101..MCLK clock.
 *  0b110..Oscillator 32 kHz clock.
 *  0b111..No clock.
 */
#define SYSCON_FCCLKSEL_SEL(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL_SEL_SHIFT)) & SYSCON_FCCLKSEL_SEL_MASK)
/*! @} */

/* The count of SYSCON_FCCLKSEL */
#define SYSCON_FCCLKSEL_COUNT                    (8U)

/*! @name HSSPICLKSEL - HS SPI clock source select */
/*! @{ */

#define SYSCON_HSSPICLKSEL_SEL_MASK              (0x7U)
#define SYSCON_HSSPICLKSEL_SEL_SHIFT             (0U)
/*! SEL - HS SPI clock source select.
 *  0b000..Main clock.
 *  0b001..system PLL divided clock.
 *  0b010..FRO 12 MHz clock.
 *  0b011..FRO 96 MHz clock.
 *  0b100..FRO 1MHz clock.
 *  0b101..No clock.
 *  0b110..Oscillator 32 kHz clock.
 *  0b111..No clock.
 */
#define SYSCON_HSSPICLKSEL_SEL(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_HSSPICLKSEL_SEL_SHIFT)) & SYSCON_HSSPICLKSEL_SEL_MASK)
/*! @} */

/*! @name MCLKCLKSEL - MCLK clock source select */
/*! @{ */

#define SYSCON_MCLKCLKSEL_SEL_MASK               (0x7U)
#define SYSCON_MCLKCLKSEL_SEL_SHIFT              (0U)
/*! SEL - MCLK clock source select.
 *  0b000..FRO 96 MHz clock.
 *  0b001..PLL0 clock.
 *  0b010..Reserved.
 *  0b011..Reserved.
 *  0b100..No clock.
 *  0b101..No clock.
 *  0b110..No clock.
 *  0b111..No clock.
 */
#define SYSCON_MCLKCLKSEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKCLKSEL_SEL_SHIFT)) & SYSCON_MCLKCLKSEL_SEL_MASK)
/*! @} */

/*! @name SCTCLKSEL - SCTimer/PWM clock source select */
/*! @{ */

#define SYSCON_SCTCLKSEL_SEL_MASK                (0x7U)
#define SYSCON_SCTCLKSEL_SEL_SHIFT               (0U)
/*! SEL - SCTimer/PWM clock source select.
 *  0b000..Main clock.
 *  0b001..PLL0 clock.
 *  0b010..CLKIN clock.
 *  0b011..FRO 96 MHz clock.
 *  0b100..PLL1 clock.
 *  0b101..MCLK clock.
 *  0b110..No clock.
 *  0b111..No clock.
 */
#define SYSCON_SCTCLKSEL_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKSEL_SEL_SHIFT)) & SYSCON_SCTCLKSEL_SEL_MASK)
/*! @} */

/*! @name SYSTICKCLKDIV - System Tick Timer divider for CPU0 */
/*! @{ */

#define SYSCON_SYSTICKCLKDIV_DIV_MASK            (0xFFU)
#define SYSCON_SYSTICKCLKDIV_DIV_SHIFT           (0U)
/*! DIV - Clock divider value.
 */
#define SYSCON_SYSTICKCLKDIV_DIV(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV_DIV_MASK)

#define SYSCON_SYSTICKCLKDIV_RESET_MASK          (0x20000000U)
#define SYSCON_SYSTICKCLKDIV_RESET_SHIFT         (29U)
/*! RESET - Resets the divider counter.
 *  0b1..Divider is reset.
 *  0b0..Divider is not reset.
 */
#define SYSCON_SYSTICKCLKDIV_RESET(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV_RESET_MASK)

#define SYSCON_SYSTICKCLKDIV_HALT_MASK           (0x40000000U)
#define SYSCON_SYSTICKCLKDIV_HALT_SHIFT          (30U)
/*! HALT - Halts the divider counter.
 *  0b1..Divider clock is stopped.
 *  0b0..Divider clock is running.
 */
#define SYSCON_SYSTICKCLKDIV_HALT(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV_HALT_MASK)

#define SYSCON_SYSTICKCLKDIV_UNSTAB_MASK         (0x80000000U)
#define SYSCON_SYSTICKCLKDIV_UNSTAB_SHIFT        (31U)
/*! UNSTAB - Divider status flag.
 *  0b1..Clock frequency is not stable.
 *  0b0..Divider clock is stable.
 */
#define SYSCON_SYSTICKCLKDIV_UNSTAB(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_UNSTAB_SHIFT)) & SYSCON_SYSTICKCLKDIV_UNSTAB_MASK)
/*! @} */

/* The count of SYSCON_SYSTICKCLKDIV */
#define SYSCON_SYSTICKCLKDIV_COUNT               (1U)

/*! @name TRACECLKDIV - TRACE clock divider */
/*! @{ */

#define SYSCON_TRACECLKDIV_DIV_MASK              (0xFFU)
#define SYSCON_TRACECLKDIV_DIV_SHIFT             (0U)
/*! DIV - Clock divider value.
 */
#define SYSCON_TRACECLKDIV_DIV(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_DIV_SHIFT)) & SYSCON_TRACECLKDIV_DIV_MASK)

#define SYSCON_TRACECLKDIV_RESET_MASK            (0x20000000U)
#define SYSCON_TRACECLKDIV_RESET_SHIFT           (29U)
/*! RESET - Resets the divider counter.
 *  0b1..Divider is reset.
 *  0b0..Divider is not reset.
 */
#define SYSCON_TRACECLKDIV_RESET(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_RESET_SHIFT)) & SYSCON_TRACECLKDIV_RESET_MASK)

#define SYSCON_TRACECLKDIV_HALT_MASK             (0x40000000U)
#define SYSCON_TRACECLKDIV_HALT_SHIFT            (30U)
/*! HALT - Halts the divider counter.
 *  0b1..Divider clock is stopped.
 *  0b0..Divider clock is running.
 */
#define SYSCON_TRACECLKDIV_HALT(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_HALT_SHIFT)) & SYSCON_TRACECLKDIV_HALT_MASK)

#define SYSCON_TRACECLKDIV_UNSTAB_MASK           (0x80000000U)
#define SYSCON_TRACECLKDIV_UNSTAB_SHIFT          (31U)
/*! UNSTAB - Divider status flag.
 *  0b1..Clock frequency is not stable.
 *  0b0..Divider clock is stable.
 */
#define SYSCON_TRACECLKDIV_UNSTAB(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_UNSTAB_SHIFT)) & SYSCON_TRACECLKDIV_UNSTAB_MASK)
/*! @} */

/*! @name CANCLKDIV - CAN clock divider */
/*! @{ */

#define SYSCON_CANCLKDIV_DIV_MASK                (0xFFU)
#define SYSCON_CANCLKDIV_DIV_SHIFT               (0U)
/*! DIV - Clock divider value.
 */
#define SYSCON_CANCLKDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_CANCLKDIV_DIV_SHIFT)) & SYSCON_CANCLKDIV_DIV_MASK)

#define SYSCON_CANCLKDIV_RESET_MASK              (0x20000000U)
#define SYSCON_CANCLKDIV_RESET_SHIFT             (29U)
/*! RESET - Resets the divider counter.
 *  0b1..Divider is reset.
 *  0b0..Divider is not reset.
 */
#define SYSCON_CANCLKDIV_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_CANCLKDIV_RESET_SHIFT)) & SYSCON_CANCLKDIV_RESET_MASK)

#define SYSCON_CANCLKDIV_HALT_MASK               (0x40000000U)
#define SYSCON_CANCLKDIV_HALT_SHIFT              (30U)
/*! HALT - Halts the divider counter.
 *  0b1..Divider clock is stopped.
 *  0b0..Divider clock is running.
 */
#define SYSCON_CANCLKDIV_HALT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_CANCLKDIV_HALT_SHIFT)) & SYSCON_CANCLKDIV_HALT_MASK)

#define SYSCON_CANCLKDIV_UNSTAB_MASK             (0x80000000U)
#define SYSCON_CANCLKDIV_UNSTAB_SHIFT            (31U)
/*! UNSTAB - Divider status flag.
 *  0b1..Clock frequency is not stable.
 *  0b0..Divider clock is stable.
 */
#define SYSCON_CANCLKDIV_UNSTAB(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_CANCLKDIV_UNSTAB_SHIFT)) & SYSCON_CANCLKDIV_UNSTAB_MASK)
/*! @} */

/*! @name FRGCTRL - Fractional rate divider for flexcomm 0..Fractional rate divider for flexcomm 7 */
/*! @{ */

#define SYSCON_FRGCTRL_DIV_MASK                  (0xFFU)
#define SYSCON_FRGCTRL_DIV_SHIFT                 (0U)
/*! DIV - Denominator of the fractional rate divider.
 */
#define SYSCON_FRGCTRL_DIV(x)                    (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_DIV_SHIFT)) & SYSCON_FRGCTRL_DIV_MASK)

#define SYSCON_FRGCTRL_MULT_MASK                 (0xFF00U)
#define SYSCON_FRGCTRL_MULT_SHIFT                (8U)
/*! MULT - Numerator of the fractional rate divider.
 */
#define SYSCON_FRGCTRL_MULT(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_MULT_SHIFT)) & SYSCON_FRGCTRL_MULT_MASK)
/*! @} */

/* The count of SYSCON_FRGCTRL */
#define SYSCON_FRGCTRL_COUNT                     (8U)

/*! @name AHBCLKDIV - System clock divider */
/*! @{ */

#define SYSCON_AHBCLKDIV_DIV_MASK                (0xFFU)
#define SYSCON_AHBCLKDIV_DIV_SHIFT               (0U)
/*! DIV - Clock divider value.
 */
#define SYSCON_AHBCLKDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK)

#define SYSCON_AHBCLKDIV_RESET_MASK              (0x20000000U)
#define SYSCON_AHBCLKDIV_RESET_SHIFT             (29U)
/*! RESET - Resets the divider counter.
 *  0b1..Divider is reset.
 *  0b0..Divider is not reset.
 */
#define SYSCON_AHBCLKDIV_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_RESET_SHIFT)) & SYSCON_AHBCLKDIV_RESET_MASK)

#define SYSCON_AHBCLKDIV_HALT_MASK               (0x40000000U)
#define SYSCON_AHBCLKDIV_HALT_SHIFT              (30U)
/*! HALT - Halts the divider counter.
 *  0b1..Divider clock is stopped.
 *  0b0..Divider clock is running.
 */
#define SYSCON_AHBCLKDIV_HALT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_HALT_SHIFT)) & SYSCON_AHBCLKDIV_HALT_MASK)

#define SYSCON_AHBCLKDIV_UNSTAB_MASK             (0x80000000U)
#define SYSCON_AHBCLKDIV_UNSTAB_SHIFT            (31U)
/*! UNSTAB - Divider status flag.
 *  0b1..Clock frequency is not stable.
 *  0b0..Divider clock is stable.
 */
#define SYSCON_AHBCLKDIV_UNSTAB(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_UNSTAB_SHIFT)) & SYSCON_AHBCLKDIV_UNSTAB_MASK)
/*! @} */

/*! @name CLKOUTDIV - CLKOUT clock divider */
/*! @{ */

#define SYSCON_CLKOUTDIV_DIV_MASK                (0xFFU)
#define SYSCON_CLKOUTDIV_DIV_SHIFT               (0U)
/*! DIV - Clock divider value.
 */
#define SYSCON_CLKOUTDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK)

#define SYSCON_CLKOUTDIV_RESET_MASK              (0x20000000U)
#define SYSCON_CLKOUTDIV_RESET_SHIFT             (29U)
/*! RESET - Resets the divider counter.
 *  0b1..Divider is reset.
 *  0b0..Divider is not reset.
 */
#define SYSCON_CLKOUTDIV_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_RESET_SHIFT)) & SYSCON_CLKOUTDIV_RESET_MASK)

#define SYSCON_CLKOUTDIV_HALT_MASK               (0x40000000U)
#define SYSCON_CLKOUTDIV_HALT_SHIFT              (30U)
/*! HALT - Halts the divider counter.
 *  0b1..Divider clock is stopped.
 *  0b0..Divider clock is running.
 */
#define SYSCON_CLKOUTDIV_HALT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_HALT_SHIFT)) & SYSCON_CLKOUTDIV_HALT_MASK)

#define SYSCON_CLKOUTDIV_UNSTAB_MASK             (0x80000000U)
#define SYSCON_CLKOUTDIV_UNSTAB_SHIFT            (31U)
/*! UNSTAB - Divider status flag.
 *  0b1..Clock frequency is not stable.
 *  0b0..Divider clock is stable.
 */
#define SYSCON_CLKOUTDIV_UNSTAB(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_UNSTAB_SHIFT)) & SYSCON_CLKOUTDIV_UNSTAB_MASK)
/*! @} */

/*! @name FROHFDIV - FRO_HF (96MHz) clock divider */
/*! @{ */

#define SYSCON_FROHFDIV_DIV_MASK                 (0xFFU)
#define SYSCON_FROHFDIV_DIV_SHIFT                (0U)
/*! DIV - Clock divider value.
 */
#define SYSCON_FROHFDIV_DIV(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_DIV_SHIFT)) & SYSCON_FROHFDIV_DIV_MASK)

#define SYSCON_FROHFDIV_RESET_MASK               (0x20000000U)
#define SYSCON_FROHFDIV_RESET_SHIFT              (29U)
/*! RESET - Resets the divider counter.
 *  0b1..Divider is reset.
 *  0b0..Divider is not reset.
 */
#define SYSCON_FROHFDIV_RESET(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_RESET_SHIFT)) & SYSCON_FROHFDIV_RESET_MASK)

#define SYSCON_FROHFDIV_HALT_MASK                (0x40000000U)
#define SYSCON_FROHFDIV_HALT_SHIFT               (30U)
/*! HALT - Halts the divider counter.
 *  0b1..Divider clock is stopped.
 *  0b0..Divider clock is running.
 */
#define SYSCON_FROHFDIV_HALT(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_HALT_SHIFT)) & SYSCON_FROHFDIV_HALT_MASK)

#define SYSCON_FROHFDIV_UNSTAB_MASK              (0x80000000U)
#define SYSCON_FROHFDIV_UNSTAB_SHIFT             (31U)
/*! UNSTAB - Divider status flag.
 *  0b1..Clock frequency is not stable.
 *  0b0..Divider clock is stable.
 */
#define SYSCON_FROHFDIV_UNSTAB(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_UNSTAB_SHIFT)) & SYSCON_FROHFDIV_UNSTAB_MASK)
/*! @} */

/*! @name WDTCLKDIV - WDT clock divider */
/*! @{ */

#define SYSCON_WDTCLKDIV_DIV_MASK                (0x3FU)
#define SYSCON_WDTCLKDIV_DIV_SHIFT               (0U)
/*! DIV - Clock divider value.
 */
#define SYSCON_WDTCLKDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_DIV_SHIFT)) & SYSCON_WDTCLKDIV_DIV_MASK)

#define SYSCON_WDTCLKDIV_RESET_MASK              (0x20000000U)
#define SYSCON_WDTCLKDIV_RESET_SHIFT             (29U)
/*! RESET - Resets the divider counter.
 *  0b1..Divider is reset.
 *  0b0..Divider is not reset.
 */
#define SYSCON_WDTCLKDIV_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_RESET_SHIFT)) & SYSCON_WDTCLKDIV_RESET_MASK)

#define SYSCON_WDTCLKDIV_HALT_MASK               (0x40000000U)
#define SYSCON_WDTCLKDIV_HALT_SHIFT              (30U)
/*! HALT - Halts the divider counter.
 *  0b1..Divider clock is stopped.
 *  0b0..Divider clock is running.
 */
#define SYSCON_WDTCLKDIV_HALT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_HALT_SHIFT)) & SYSCON_WDTCLKDIV_HALT_MASK)

#define SYSCON_WDTCLKDIV_UNSTAB_MASK             (0x80000000U)
#define SYSCON_WDTCLKDIV_UNSTAB_SHIFT            (31U)
/*! UNSTAB - Divider status flag.
 *  0b1..Clock frequency is not stable.
 *  0b0..Divider clock is stable.
 */
#define SYSCON_WDTCLKDIV_UNSTAB(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_UNSTAB_SHIFT)) & SYSCON_WDTCLKDIV_UNSTAB_MASK)
/*! @} */

/*! @name ADC0CLKDIV - ADC0 clock divider */
/*! @{ */

#define SYSCON_ADC0CLKDIV_DIV_MASK               (0x7U)
#define SYSCON_ADC0CLKDIV_DIV_SHIFT              (0U)
/*! DIV - Clock divider value.
 */
#define SYSCON_ADC0CLKDIV_DIV(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC0CLKDIV_DIV_SHIFT)) & SYSCON_ADC0CLKDIV_DIV_MASK)

#define SYSCON_ADC0CLKDIV_RESET_MASK             (0x20000000U)
#define SYSCON_ADC0CLKDIV_RESET_SHIFT            (29U)
/*! RESET - Resets the divider counter.
 *  0b1..Divider is reset.
 *  0b0..Divider is not reset.
 */
#define SYSCON_ADC0CLKDIV_RESET(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC0CLKDIV_RESET_SHIFT)) & SYSCON_ADC0CLKDIV_RESET_MASK)

#define SYSCON_ADC0CLKDIV_HALT_MASK              (0x40000000U)
#define SYSCON_ADC0CLKDIV_HALT_SHIFT             (30U)
/*! HALT - Halts the divider counter.
 *  0b1..Divider clock is stopped.
 *  0b0..Divider clock is running.
 */
#define SYSCON_ADC0CLKDIV_HALT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC0CLKDIV_HALT_SHIFT)) & SYSCON_ADC0CLKDIV_HALT_MASK)

#define SYSCON_ADC0CLKDIV_UNSTAB_MASK            (0x80000000U)
#define SYSCON_ADC0CLKDIV_UNSTAB_SHIFT           (31U)
/*! UNSTAB - Divider status flag.
 *  0b1..Clock frequency is not stable.
 *  0b0..Divider clock is stable.
 */
#define SYSCON_ADC0CLKDIV_UNSTAB(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC0CLKDIV_UNSTAB_SHIFT)) & SYSCON_ADC0CLKDIV_UNSTAB_MASK)
/*! @} */

/*! @name USB0CLKDIV - USB0-FS Clock divider */
/*! @{ */

#define SYSCON_USB0CLKDIV_DIV_MASK               (0xFFU)
#define SYSCON_USB0CLKDIV_DIV_SHIFT              (0U)
/*! DIV - Clock divider value.
 */
#define SYSCON_USB0CLKDIV_DIV(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_DIV_SHIFT)) & SYSCON_USB0CLKDIV_DIV_MASK)

#define SYSCON_USB0CLKDIV_RESET_MASK             (0x20000000U)
#define SYSCON_USB0CLKDIV_RESET_SHIFT            (29U)
/*! RESET - Resets the divider counter.
 *  0b1..Divider is reset.
 *  0b0..Divider is not reset.
 */
#define SYSCON_USB0CLKDIV_RESET(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_RESET_SHIFT)) & SYSCON_USB0CLKDIV_RESET_MASK)

#define SYSCON_USB0CLKDIV_HALT_MASK              (0x40000000U)
#define SYSCON_USB0CLKDIV_HALT_SHIFT             (30U)
/*! HALT - Halts the divider counter.
 *  0b1..Divider clock is stopped.
 *  0b0..Divider clock is running.
 */
#define SYSCON_USB0CLKDIV_HALT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_HALT_SHIFT)) & SYSCON_USB0CLKDIV_HALT_MASK)

#define SYSCON_USB0CLKDIV_UNSTAB_MASK            (0x80000000U)
#define SYSCON_USB0CLKDIV_UNSTAB_SHIFT           (31U)
/*! UNSTAB - Divider status flag.
 *  0b1..Clock frequency is not stable.
 *  0b0..Divider clock is stable.
 */
#define SYSCON_USB0CLKDIV_UNSTAB(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_UNSTAB_SHIFT)) & SYSCON_USB0CLKDIV_UNSTAB_MASK)
/*! @} */

/*! @name MCLKDIV - I2S MCLK clock divider */
/*! @{ */

#define SYSCON_MCLKDIV_DIV_MASK                  (0xFFU)
#define SYSCON_MCLKDIV_DIV_SHIFT                 (0U)
/*! DIV - Clock divider value.
 */
#define SYSCON_MCLKDIV_DIV(x)                    (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_DIV_SHIFT)) & SYSCON_MCLKDIV_DIV_MASK)

#define SYSCON_MCLKDIV_RESET_MASK                (0x20000000U)
#define SYSCON_MCLKDIV_RESET_SHIFT               (29U)
/*! RESET - Resets the divider counter.
 *  0b1..Divider is reset.
 *  0b0..Divider is not reset.
 */
#define SYSCON_MCLKDIV_RESET(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_RESET_SHIFT)) & SYSCON_MCLKDIV_RESET_MASK)

#define SYSCON_MCLKDIV_HALT_MASK                 (0x40000000U)
#define SYSCON_MCLKDIV_HALT_SHIFT                (30U)
/*! HALT - Halts the divider counter.
 *  0b1..Divider clock is stopped.
 *  0b0..Divider clock is running.
 */
#define SYSCON_MCLKDIV_HALT(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_HALT_SHIFT)) & SYSCON_MCLKDIV_HALT_MASK)

#define SYSCON_MCLKDIV_UNSTAB_MASK               (0x80000000U)
#define SYSCON_MCLKDIV_UNSTAB_SHIFT              (31U)
/*! UNSTAB - Divider status flag.
 *  0b1..Clock frequency is not stable.
 *  0b0..Divider clock is stable.
 */
#define SYSCON_MCLKDIV_UNSTAB(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_UNSTAB_SHIFT)) & SYSCON_MCLKDIV_UNSTAB_MASK)
/*! @} */

/*! @name SCTCLKDIV - SCT/PWM clock divider */
/*! @{ */

#define SYSCON_SCTCLKDIV_DIV_MASK                (0xFFU)
#define SYSCON_SCTCLKDIV_DIV_SHIFT               (0U)
/*! DIV - Clock divider value.
 */
#define SYSCON_SCTCLKDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_DIV_SHIFT)) & SYSCON_SCTCLKDIV_DIV_MASK)

#define SYSCON_SCTCLKDIV_RESET_MASK              (0x20000000U)
#define SYSCON_SCTCLKDIV_RESET_SHIFT             (29U)
/*! RESET - Resets the divider counter.
 *  0b1..Divider is reset.
 *  0b0..Divider is not reset.
 */
#define SYSCON_SCTCLKDIV_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_RESET_SHIFT)) & SYSCON_SCTCLKDIV_RESET_MASK)

#define SYSCON_SCTCLKDIV_HALT_MASK               (0x40000000U)
#define SYSCON_SCTCLKDIV_HALT_SHIFT              (30U)
/*! HALT - Halts the divider counter.
 *  0b1..Divider clock is stopped.
 *  0b0..Divider clock is running.
 */
#define SYSCON_SCTCLKDIV_HALT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_HALT_SHIFT)) & SYSCON_SCTCLKDIV_HALT_MASK)

#define SYSCON_SCTCLKDIV_UNSTAB_MASK             (0x80000000U)
#define SYSCON_SCTCLKDIV_UNSTAB_SHIFT            (31U)
/*! UNSTAB - Divider status flag.
 *  0b1..Clock frequency is not stable.
 *  0b0..Divider clock is stable.
 */
#define SYSCON_SCTCLKDIV_UNSTAB(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_UNSTAB_SHIFT)) & SYSCON_SCTCLKDIV_UNSTAB_MASK)
/*! @} */

/*! @name PLLCLKDIV - PLL clock divider */
/*! @{ */

#define SYSCON_PLLCLKDIV_DIV_MASK                (0xFFU)
#define SYSCON_PLLCLKDIV_DIV_SHIFT               (0U)
/*! DIV - Clock divider value.
 */
#define SYSCON_PLLCLKDIV_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_PLLCLKDIV_DIV_SHIFT)) & SYSCON_PLLCLKDIV_DIV_MASK)

#define SYSCON_PLLCLKDIV_RESET_MASK              (0x20000000U)
#define SYSCON_PLLCLKDIV_RESET_SHIFT             (29U)
/*! RESET - Resets the divider counter.
 *  0b1..Divider is reset.
 *  0b0..Divider is not reset.
 */
#define SYSCON_PLLCLKDIV_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_PLLCLKDIV_RESET_SHIFT)) & SYSCON_PLLCLKDIV_RESET_MASK)

#define SYSCON_PLLCLKDIV_HALT_MASK               (0x40000000U)
#define SYSCON_PLLCLKDIV_HALT_SHIFT              (30U)
/*! HALT - Halts the divider counter.
 *  0b1..Divider clock is stopped.
 *  0b0..Divider clock is running.
 */
#define SYSCON_PLLCLKDIV_HALT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_PLLCLKDIV_HALT_SHIFT)) & SYSCON_PLLCLKDIV_HALT_MASK)

#define SYSCON_PLLCLKDIV_UNSTAB_MASK             (0x80000000U)
#define SYSCON_PLLCLKDIV_UNSTAB_SHIFT            (31U)
/*! UNSTAB - Divider status flag.
 *  0b1..Clock frequency is not stable.
 *  0b0..Divider clock is stable.
 */
#define SYSCON_PLLCLKDIV_UNSTAB(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_PLLCLKDIV_UNSTAB_SHIFT)) & SYSCON_PLLCLKDIV_UNSTAB_MASK)
/*! @} */

/*! @name CTIMERXCLKDIV_CTIMERCLKDIV - CTimer 0 clock divider..CTimer 4 clock divider */
/*! @{ */

#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_DIV_MASK (0xFFU)
#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_DIV_SHIFT (0U)
/*! DIV - Clock divider value
 */
#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_DIV_SHIFT)) & SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_DIV_MASK)

#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_RESET_MASK (0x20000000U)
#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_RESET_SHIFT (29U)
/*! RESET - Resets the divider counter
 *  0b0..Divider is not reset
 *  0b1..Divider is reset
 */
#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_RESET_SHIFT)) & SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_RESET_MASK)

#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_HALT_MASK (0x40000000U)
#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_HALT_SHIFT (30U)
/*! HALT - Halts the divider counter
 *  0b0..Divider clock is running.
 *  0b1..Divider clock has stopped.
 */
#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_HALT_SHIFT)) & SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_HALT_MASK)

#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_UNSTAB_MASK (0x80000000U)
#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_UNSTAB_SHIFT (31U)
/*! UNSTAB - Divider status flag
 *  0b0..Stable divider clock.
 *  0b1..Unstable clock frequency.
 */
#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_UNSTAB_SHIFT)) & SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_UNSTAB_MASK)
/*! @} */

/* The count of SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV */
#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_COUNT  (5U)

/*! @name CLKUNLOCK - Clock configuration unlock */
/*! @{ */

#define SYSCON_CLKUNLOCK_UNLOCK_MASK             (0xFFFFFFFFU)
#define SYSCON_CLKUNLOCK_UNLOCK_SHIFT            (0U)
/*! UNLOCK - Control clock configuration registers access (for example, xxxDIV, xxxSEL).
 *  0b00000000000000000000000000000001..Update all clock configuration.
 *  0b00000000000000000000000000000000..All hardware clock configruration are freeze.
 */
#define SYSCON_CLKUNLOCK_UNLOCK(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKUNLOCK_UNLOCK_SHIFT)) & SYSCON_CLKUNLOCK_UNLOCK_MASK)
/*! @} */

/*! @name FMCCR - FMC configuration */
/*! @{ */

#define SYSCON_FMCCR_FETCHCFG_MASK               (0x3U)
#define SYSCON_FMCCR_FETCHCFG_SHIFT              (0U)
/*! FETCHCFG - Instruction fetch configuration.
 *  0b00..Instruction fetches from flash are not buffered.
 *  0b01..One buffer is used for all instruction fetches.
 *  0b10..All buffers may be used for instruction fetches.
 */
#define SYSCON_FMCCR_FETCHCFG(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_FETCHCFG_SHIFT)) & SYSCON_FMCCR_FETCHCFG_MASK)

#define SYSCON_FMCCR_DATACFG_MASK                (0xCU)
#define SYSCON_FMCCR_DATACFG_SHIFT               (2U)
/*! DATACFG - Data read configuration.
 *  0b00..Data accesses from flash are not buffered.
 *  0b01..One buffer is used for all data accesses.
 *  0b10..All buffers can be used for data accesses.
 */
#define SYSCON_FMCCR_DATACFG(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_DATACFG_SHIFT)) & SYSCON_FMCCR_DATACFG_MASK)

#define SYSCON_FMCCR_ACCEL_MASK                  (0x10U)
#define SYSCON_FMCCR_ACCEL_SHIFT                 (4U)
/*! ACCEL - Acceleration enable.
 *  0b0..Flash acceleration is disabled.
 *  0b1..Flash acceleration is enabled.
 */
#define SYSCON_FMCCR_ACCEL(x)                    (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_ACCEL_SHIFT)) & SYSCON_FMCCR_ACCEL_MASK)

#define SYSCON_FMCCR_PREFEN_MASK                 (0x20U)
#define SYSCON_FMCCR_PREFEN_SHIFT                (5U)
/*! PREFEN - Prefetch enable.
 *  0b0..No instruction prefetch is performed.
 *  0b1..Instruction prefetch is enabled.
 */
#define SYSCON_FMCCR_PREFEN(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PREFEN_SHIFT)) & SYSCON_FMCCR_PREFEN_MASK)

#define SYSCON_FMCCR_PREFOVR_MASK                (0x40U)
#define SYSCON_FMCCR_PREFOVR_SHIFT               (6U)
/*! PREFOVR - Prefetch override.
 *  0b0..Any previously initiated prefetch will be completed.
 *  0b1..Any previously initiated prefetch will be aborted, and the next flash line following the current
 *       execution address will be prefetched if not already buffered.
 */
#define SYSCON_FMCCR_PREFOVR(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PREFOVR_SHIFT)) & SYSCON_FMCCR_PREFOVR_MASK)

#define SYSCON_FMCCR_FLASHTIM_MASK               (0xF000U)
#define SYSCON_FMCCR_FLASHTIM_SHIFT              (12U)
/*! FLASHTIM - Flash memory access time.
 *  0b0000..1 system clock flash access time (for system clock rates up to 11 MHz).
 *  0b0001..2 system clocks flash access time (for system clock rates up to 22 MHz).
 *  0b0010..3 system clocks flash access time (for system clock rates up to 33 MHz).
 *  0b0011..4 system clocks flash access time (for system clock rates up to 44 MHz).
 *  0b0100..5 system clocks flash access time (for system clock rates up to 55 MHz).
 *  0b0101..6 system clocks flash access time (for system clock rates up to 66 MHz).
 *  0b0110..7 system clocks flash access time (for system clock rates up to 77 MHz).
 *  0b0111..8 system clocks flash access time (for system clock rates up to 88 MHz).
 *  0b1000..9 system clocks flash access time (for system clock rates up to 100 MHz).
 *  0b1001..10 system clocks flash access time (for system clock rates up to 115 MHz).
 *  0b1010..11 system clocks flash access time (for system clock rates up to 130 MHz).
 *  0b1011..12 system clocks flash access time (for system clock rates up to 150 MHz).
 */
#define SYSCON_FMCCR_FLASHTIM(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_FLASHTIM_SHIFT)) & SYSCON_FMCCR_FLASHTIM_MASK)

#define SYSCON_FMCCR_ECCABORTEN_MASK             (0x300000U)
#define SYSCON_FMCCR_ECCABORTEN_SHIFT            (20U)
/*! ECCABORTEN - ECC error abort enable
 */
#define SYSCON_FMCCR_ECCABORTEN(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_ECCABORTEN_SHIFT)) & SYSCON_FMCCR_ECCABORTEN_MASK)

#define SYSCON_FMCCR_CLKDIV_MASK                 (0xC000000U)
#define SYSCON_FMCCR_CLKDIV_SHIFT                (26U)
/*! CLKDIV - CLKDIV; default value is 00.
 *  0b00..1 division
 *  0b01..2 division
 *  0b10..3 division
 *  0b11..4 division
 */
#define SYSCON_FMCCR_CLKDIV(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_CLKDIV_SHIFT)) & SYSCON_FMCCR_CLKDIV_MASK)
/*! @} */

/*! @name ROMCR - ROM wait state */
/*! @{ */

#define SYSCON_ROMCR_ROM_WAIT_MASK               (0x1U)
#define SYSCON_ROMCR_ROM_WAIT_SHIFT              (0U)
/*! ROM_WAIT - ROM waiting Arm core and other masters.
 */
#define SYSCON_ROMCR_ROM_WAIT(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_ROMCR_ROM_WAIT_SHIFT)) & SYSCON_ROMCR_ROM_WAIT_MASK)
/*! @} */

/*! @name USB0NEEDCLKCTRL - USB0-FS need clock control */
/*! @{ */

#define SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_MASK (0x1U)
#define SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_SHIFT (0U)
/*! AP_FS_DEV_NEEDCLK - USB0-FS Device USB0_NEEDCLK signal control:.
 *  0b0..Under hardware control.
 *  0b1..Forced high.
 */
#define SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_MASK)

#define SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_MASK (0x2U)
#define SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_SHIFT (1U)
/*! POL_FS_DEV_NEEDCLK - USB0-FS Device USB0_NEEDCLK polarity for triggering the USB0-FS wake-up interrupt:.
 *  0b0..Falling edge of device USB0_NEEDCLK triggers wake-up.
 *  0b1..Rising edge of device USB0_NEEDCLK triggers wake-up.
 */
#define SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_MASK)

#define SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_MASK (0x4U)
#define SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_SHIFT (2U)
/*! AP_FS_HOST_NEEDCLK - USB0-FS Host USB0_NEEDCLK signal control:.
 *  0b0..Under hardware control.
 *  0b1..Forced high.
 */
#define SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_MASK)

#define SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_MASK (0x8U)
#define SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_SHIFT (3U)
/*! POL_FS_HOST_NEEDCLK - USB0-FS Host USB0_NEEDCLK polarity for triggering the USB0-FS wake-up interrupt:.
 *  0b0..Falling edge of device USB0_NEEDCLK triggers wake-up.
 *  0b1..Rising edge of device USB0_NEEDCLK triggers wake-up.
 */
#define SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_MASK)
/*! @} */

/*! @name USB0NEEDCLKSTAT - USB0-FS need clock status */
/*! @{ */

#define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_MASK  (0x1U)
#define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_SHIFT (0U)
/*! DEV_NEEDCLK - USB0-FS Device USB0_NEEDCLK signal status:.
 *  0b1..USB0-FS Device clock is high.
 *  0b0..USB0-FS Device clock is low.
 */
#define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_MASK)

#define SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_MASK (0x2U)
#define SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_SHIFT (1U)
/*! HOST_NEEDCLK - USB0-FS Host USB0_NEEDCLK signal status:.
 *  0b1..USB0-FS Host clock is high.
 *  0b0..USB0-FS Host clock is low.
 */
#define SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_MASK)
/*! @} */

/*! @name EZHINT - EZH interrupt hijack */
/*! @{ */

#define SYSCON_EZHINT_EZHINT_MASK                (0xFFFFFFFFU)
#define SYSCON_EZHINT_EZHINT_SHIFT               (0U)
/*! EZHINT - EZH interrupt hijack.
 */
#define SYSCON_EZHINT_EZHINT(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_EZHINT_EZHINT_SHIFT)) & SYSCON_EZHINT_EZHINT_MASK)
/*! @} */

/*! @name FMCFLUSH - FMC flush control */
/*! @{ */

#define SYSCON_FMCFLUSH_FLUSH_MASK               (0x1U)
#define SYSCON_FMCFLUSH_FLUSH_SHIFT              (0U)
/*! FLUSH - Flush control
 *  0b1..Flush the FMC buffer contents.
 *  0b0..No action.
 */
#define SYSCON_FMCFLUSH_FLUSH(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCFLUSH_FLUSH_SHIFT)) & SYSCON_FMCFLUSH_FLUSH_MASK)
/*! @} */

/*! @name MCLKIO - MCLK control */
/*! @{ */

#define SYSCON_MCLKIO_MCLKIO_MASK                (0x1U)
#define SYSCON_MCLKIO_MCLKIO_SHIFT               (0U)
/*! MCLKIO - MCLK control.
 *  0b0..input mode.
 *  0b1..output mode.
 */
#define SYSCON_MCLKIO_MCLKIO(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKIO_MCLKIO_SHIFT)) & SYSCON_MCLKIO_MCLKIO_MASK)
/*! @} */

/*! @name ADC1CLKSEL - ADC1 clock source select */
/*! @{ */

#define SYSCON_ADC1CLKSEL_SEL_MASK               (0x7U)
#define SYSCON_ADC1CLKSEL_SEL_SHIFT              (0U)
/*! SEL - ADC clock source select.
 *  0b000..Main clock.
 *  0b001..PLL0 clock.
 *  0b010..FRO 96 MHz clock.
 *  0b011..Reserved.
 *  0b100..XO to ADC clock.
 *  0b101..No clock.
 *  0b110..No clock.
 *  0b111..No clock.
 */
#define SYSCON_ADC1CLKSEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC1CLKSEL_SEL_SHIFT)) & SYSCON_ADC1CLKSEL_SEL_MASK)
/*! @} */

/*! @name ADC1CLKDIV - ADC1 clock divider */
/*! @{ */

#define SYSCON_ADC1CLKDIV_DIV_MASK               (0x7U)
#define SYSCON_ADC1CLKDIV_DIV_SHIFT              (0U)
/*! DIV - Clock divider value.
 */
#define SYSCON_ADC1CLKDIV_DIV(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC1CLKDIV_DIV_SHIFT)) & SYSCON_ADC1CLKDIV_DIV_MASK)

#define SYSCON_ADC1CLKDIV_RESET_MASK             (0x20000000U)
#define SYSCON_ADC1CLKDIV_RESET_SHIFT            (29U)
/*! RESET - Resets the divider counter.
 *  0b1..Divider is reset.
 *  0b0..Divider is not reset.
 */
#define SYSCON_ADC1CLKDIV_RESET(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC1CLKDIV_RESET_SHIFT)) & SYSCON_ADC1CLKDIV_RESET_MASK)

#define SYSCON_ADC1CLKDIV_HALT_MASK              (0x40000000U)
#define SYSCON_ADC1CLKDIV_HALT_SHIFT             (30U)
/*! HALT - Halts the divider counter.
 *  0b1..Divider clock is stopped.
 *  0b0..Divider clock is running.
 */
#define SYSCON_ADC1CLKDIV_HALT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC1CLKDIV_HALT_SHIFT)) & SYSCON_ADC1CLKDIV_HALT_MASK)

#define SYSCON_ADC1CLKDIV_UNSTAB_MASK            (0x80000000U)
#define SYSCON_ADC1CLKDIV_UNSTAB_SHIFT           (31U)
/*! UNSTAB - Divider status flag.
 *  0b1..Clock frequency is not stable.
 *  0b0..Divider clock is stable.
 */
#define SYSCON_ADC1CLKDIV_UNSTAB(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC1CLKDIV_UNSTAB_SHIFT)) & SYSCON_ADC1CLKDIV_UNSTAB_MASK)
/*! @} */

/*! @name RAM_INTERLEAVE - Control RAM interleave integration */
/*! @{ */

#define SYSCON_RAM_INTERLEAVE_INTERLEAVE_MASK    (0x1U)
#define SYSCON_RAM_INTERLEAVE_INTERLEAVE_SHIFT   (0U)
/*! INTERLEAVE - Control RAM access for RAM_02 and RAM_03.
 *  0b1..RAM access to RAM_02 and RAM_03 is interleaved. This setting is need for PKC L0 memory access.
 *  0b0..RAM access to RAM_02 and RAM_03 is consecutive.
 */
#define SYSCON_RAM_INTERLEAVE_INTERLEAVE(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_RAM_INTERLEAVE_INTERLEAVE_SHIFT)) & SYSCON_RAM_INTERLEAVE_INTERLEAVE_MASK)
/*! @} */

/*! @name DAC_CLKSEL - DAC0 functional clock selection..DAC2 functional clock selection */
/*! @{ */

#define SYSCON_DAC_CLKSEL_SEL_MASK               (0x7U)
#define SYSCON_DAC_CLKSEL_SEL_SHIFT              (0U)
/*! SEL - DAC clock source select.
 *  0b000..Main clock.
 *  0b001..PLL0 clock.
 *  0b010..No clock.
 *  0b011..FRO_HF.
 *  0b100..FRO_12M.
 *  0b101..PLL1 clock.
 *  0b110..FRO_1M.
 *  0b111..No clock.
 */
#define SYSCON_DAC_CLKSEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_DAC_CLKSEL_SEL_SHIFT)) & SYSCON_DAC_CLKSEL_SEL_MASK)
/*! @} */

/* The count of SYSCON_DAC_CLKSEL */
#define SYSCON_DAC_CLKSEL_COUNT                  (3U)

/*! @name DAC_CLKDIV - DAC0 functional clock divider..DAC2 functional clock divider */
/*! @{ */

#define SYSCON_DAC_CLKDIV_DIV_MASK               (0x7U)
#define SYSCON_DAC_CLKDIV_DIV_SHIFT              (0U)
/*! DIV - Clock divider value.
 */
#define SYSCON_DAC_CLKDIV_DIV(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_DAC_CLKDIV_DIV_SHIFT)) & SYSCON_DAC_CLKDIV_DIV_MASK)

#define SYSCON_DAC_CLKDIV_RESET_MASK             (0x20000000U)
#define SYSCON_DAC_CLKDIV_RESET_SHIFT            (29U)
/*! RESET - Resets the divider counter.
 *  0b1..Divider is reset.
 *  0b0..Divider is not reset.
 */
#define SYSCON_DAC_CLKDIV_RESET(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_DAC_CLKDIV_RESET_SHIFT)) & SYSCON_DAC_CLKDIV_RESET_MASK)

#define SYSCON_DAC_CLKDIV_HALT_MASK              (0x40000000U)
#define SYSCON_DAC_CLKDIV_HALT_SHIFT             (30U)
/*! HALT - Halts the divider counter.
 *  0b1..Divider clock is stopped.
 *  0b0..Divider clock is running.
 */
#define SYSCON_DAC_CLKDIV_HALT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_DAC_CLKDIV_HALT_SHIFT)) & SYSCON_DAC_CLKDIV_HALT_MASK)

#define SYSCON_DAC_CLKDIV_UNSTAB_MASK            (0x80000000U)
#define SYSCON_DAC_CLKDIV_UNSTAB_SHIFT           (31U)
/*! UNSTAB - Divider status flag.
 *  0b1..Clock frequency is not stable.
 *  0b0..Divider clock is stable.
 */
#define SYSCON_DAC_CLKDIV_UNSTAB(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_DAC_CLKDIV_UNSTAB_SHIFT)) & SYSCON_DAC_CLKDIV_UNSTAB_MASK)
/*! @} */

/* The count of SYSCON_DAC_CLKDIV */
#define SYSCON_DAC_CLKDIV_COUNT                  (3U)

/*! @name FLEXSPICLKSEL - FLEXSPI clock selection */
/*! @{ */

#define SYSCON_FLEXSPICLKSEL_SEL_MASK            (0xFU)
#define SYSCON_FLEXSPICLKSEL_SEL_SHIFT           (0U)
/*! SEL - Flexspi clock select
 *  0b0000..Main clock
 *  0b0001..PLL0 clock
 *  0b0010..No clock
 *  0b0011..FRO_HF
 *  0b0100..No clock
 *  0b0101..PLL1 clock
 *  0b0110..No clock
 *  0b0111..No clock
 *  0b1000..No clock
 *  0b1001..No clock
 *  0b1010..No clock
 *  0b1011..No clock
 *  0b1100..No clock
 *  0b1101..No clock
 *  0b1110..No clock
 *  0b1111..No clock
 */
#define SYSCON_FLEXSPICLKSEL_SEL(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXSPICLKSEL_SEL_SHIFT)) & SYSCON_FLEXSPICLKSEL_SEL_MASK)
/*! @} */

/*! @name FLEXSPICLKDIV - FLEXSPI clock divider */
/*! @{ */

#define SYSCON_FLEXSPICLKDIV_DIV_MASK            (0x7U)
#define SYSCON_FLEXSPICLKDIV_DIV_SHIFT           (0U)
/*! DIV - Clock divider value.
 */
#define SYSCON_FLEXSPICLKDIV_DIV(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXSPICLKDIV_DIV_SHIFT)) & SYSCON_FLEXSPICLKDIV_DIV_MASK)

#define SYSCON_FLEXSPICLKDIV_RESET_MASK          (0x20000000U)
#define SYSCON_FLEXSPICLKDIV_RESET_SHIFT         (29U)
/*! RESET - Resets the divider counter.
 *  0b1..Divider is reset.
 *  0b0..Divider is not reset.
 */
#define SYSCON_FLEXSPICLKDIV_RESET(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXSPICLKDIV_RESET_SHIFT)) & SYSCON_FLEXSPICLKDIV_RESET_MASK)

#define SYSCON_FLEXSPICLKDIV_HALT_MASK           (0x40000000U)
#define SYSCON_FLEXSPICLKDIV_HALT_SHIFT          (30U)
/*! HALT - Halts the divider counter.
 *  0b1..Divider clock is stopped.
 *  0b0..Divider clock is running.
 */
#define SYSCON_FLEXSPICLKDIV_HALT(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXSPICLKDIV_HALT_SHIFT)) & SYSCON_FLEXSPICLKDIV_HALT_MASK)

#define SYSCON_FLEXSPICLKDIV_UNSTAB_MASK         (0x80000000U)
#define SYSCON_FLEXSPICLKDIV_UNSTAB_SHIFT        (31U)
/*! UNSTAB - Divider status flag.
 *  0b1..Clock frequency is not stable.
 *  0b0..Divider clock is stable.
 */
#define SYSCON_FLEXSPICLKDIV_UNSTAB(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXSPICLKDIV_UNSTAB_SHIFT)) & SYSCON_FLEXSPICLKDIV_UNSTAB_MASK)
/*! @} */

/*! @name CDPA_ENABLE - Enable protection */
/*! @{ */

#define SYSCON_CDPA_ENABLE_CDPA_ENABLE_MASK      (0x3U)
#define SYSCON_CDPA_ENABLE_CDPA_ENABLE_SHIFT     (0U)
/*! CDPA_ENABLE - Enable control
 */
#define SYSCON_CDPA_ENABLE_CDPA_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_CDPA_ENABLE_CDPA_ENABLE_SHIFT)) & SYSCON_CDPA_ENABLE_CDPA_ENABLE_MASK)
/*! @} */

/*! @name CDPA_ENABLE_DP - Enable protection duplicate */
/*! @{ */

#define SYSCON_CDPA_ENABLE_DP_CDPA_ENABLE_DP_MASK (0x3U)
#define SYSCON_CDPA_ENABLE_DP_CDPA_ENABLE_DP_SHIFT (0U)
/*! CDPA_ENABLE_DP - Enable control
 */
#define SYSCON_CDPA_ENABLE_DP_CDPA_ENABLE_DP(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_CDPA_ENABLE_DP_CDPA_ENABLE_DP_SHIFT)) & SYSCON_CDPA_ENABLE_DP_CDPA_ENABLE_DP_MASK)
/*! @} */

/*! @name CDPA_CONFIG - CDPA base address */
/*! @{ */

#define SYSCON_CDPA_CONFIG_CDPA_START_PAGE_MASK  (0x1FFU)
#define SYSCON_CDPA_CONFIG_CDPA_START_PAGE_SHIFT (0U)
/*! CDPA_START_PAGE - Specifies the size of CDPA in number of pages.
 */
#define SYSCON_CDPA_CONFIG_CDPA_START_PAGE(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_CDPA_CONFIG_CDPA_START_PAGE_SHIFT)) & SYSCON_CDPA_CONFIG_CDPA_START_PAGE_MASK)
/*! @} */

/*! @name FLASH_HIDING_LOCKOUT_ADDR - Flash hiding lockout address */
/*! @{ */

#define SYSCON_FLASH_HIDING_LOCKOUT_ADDR_flash_hiding_lockout_addr_MASK (0xFFFFFFFFU)
#define SYSCON_FLASH_HIDING_LOCKOUT_ADDR_flash_hiding_lockout_addr_SHIFT (0U)
/*! flash_hiding_lockout_addr - while flash hiding is disabled, register write is locked.
 */
#define SYSCON_FLASH_HIDING_LOCKOUT_ADDR_flash_hiding_lockout_addr(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASH_HIDING_LOCKOUT_ADDR_flash_hiding_lockout_addr_SHIFT)) & SYSCON_FLASH_HIDING_LOCKOUT_ADDR_flash_hiding_lockout_addr_MASK)
/*! @} */

/*! @name FLASH_HIDING_BASE_ADDR - Flash hiding base address */
/*! @{ */

#define SYSCON_FLASH_HIDING_BASE_ADDR_flash_hiding_base_addr_MASK (0x3FFFFU)
#define SYSCON_FLASH_HIDING_BASE_ADDR_flash_hiding_base_addr_SHIFT (0U)
/*! flash_hiding_base_addr - Base address for flash hiding
 */
#define SYSCON_FLASH_HIDING_BASE_ADDR_flash_hiding_base_addr(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASH_HIDING_BASE_ADDR_flash_hiding_base_addr_SHIFT)) & SYSCON_FLASH_HIDING_BASE_ADDR_flash_hiding_base_addr_MASK)
/*! @} */

/*! @name FLASH_HIDING_BASE_DP_ADDR - Flash hiding base DP address */
/*! @{ */

#define SYSCON_FLASH_HIDING_BASE_DP_ADDR_flash_hiding_base_addr_MASK (0x3FFFFU)
#define SYSCON_FLASH_HIDING_BASE_DP_ADDR_flash_hiding_base_addr_SHIFT (0U)
/*! flash_hiding_base_addr - Base address for flash hiding
 */
#define SYSCON_FLASH_HIDING_BASE_DP_ADDR_flash_hiding_base_addr(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASH_HIDING_BASE_DP_ADDR_flash_hiding_base_addr_SHIFT)) & SYSCON_FLASH_HIDING_BASE_DP_ADDR_flash_hiding_base_addr_MASK)
/*! @} */

/*! @name FLASH_HIDING_SIZE_ADDR - Hiding size address */
/*! @{ */

#define SYSCON_FLASH_HIDING_SIZE_ADDR_flash_hiding_size_addr_MASK (0x3FFFFU)
#define SYSCON_FLASH_HIDING_SIZE_ADDR_flash_hiding_size_addr_SHIFT (0U)
/*! flash_hiding_size_addr - Size address for flash hiding
 */
#define SYSCON_FLASH_HIDING_SIZE_ADDR_flash_hiding_size_addr(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASH_HIDING_SIZE_ADDR_flash_hiding_size_addr_SHIFT)) & SYSCON_FLASH_HIDING_SIZE_ADDR_flash_hiding_size_addr_MASK)
/*! @} */

/*! @name FLASH_HIDING_SIZE_DP_ADDR - Hiding size DP address */
/*! @{ */

#define SYSCON_FLASH_HIDING_SIZE_DP_ADDR_flash_hiding_size_dp_addr_MASK (0x3FFFFU)
#define SYSCON_FLASH_HIDING_SIZE_DP_ADDR_flash_hiding_size_dp_addr_SHIFT (0U)
/*! flash_hiding_size_dp_addr - Size address for flash hiding
 */
#define SYSCON_FLASH_HIDING_SIZE_DP_ADDR_flash_hiding_size_dp_addr(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASH_HIDING_SIZE_DP_ADDR_flash_hiding_size_dp_addr_SHIFT)) & SYSCON_FLASH_HIDING_SIZE_DP_ADDR_flash_hiding_size_dp_addr_MASK)
/*! @} */

/*! @name PLLCLKDIVSEL - PLL clock divider clock selection */
/*! @{ */

#define SYSCON_PLLCLKDIVSEL_SEL_MASK             (0x7U)
#define SYSCON_PLLCLKDIVSEL_SEL_SHIFT            (0U)
/*! SEL - Flexspi clock select
 *  0b000..PLL0 clock
 *  0b001..PLL1 clock
 *  0b010..No clock
 *  0b011..No clock
 *  0b100..No clock
 *  0b101..No clock
 *  0b110..No clock
 *  0b111..No clock
 */
#define SYSCON_PLLCLKDIVSEL_SEL(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_PLLCLKDIVSEL_SEL_SHIFT)) & SYSCON_PLLCLKDIVSEL_SEL_MASK)
/*! @} */

/*! @name I3CFCLKSEL - I3C functional clock selection */
/*! @{ */

#define SYSCON_I3CFCLKSEL_SEL_MASK               (0x7U)
#define SYSCON_I3CFCLKSEL_SEL_SHIFT              (0U)
/*! SEL - I3C clock select
 *  0b000..Main clock
 *  0b001..FRO_HF_DIV
 *  0b010..No clock
 *  0b011..No clock
 *  0b100..No clock
 *  0b101..No clock
 *  0b110..No clock
 *  0b111..No clock
 */
#define SYSCON_I3CFCLKSEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_I3CFCLKSEL_SEL_SHIFT)) & SYSCON_I3CFCLKSEL_SEL_MASK)
/*! @} */

/*! @name I3CFCLKSTCSEL - I3C FCLK_STC clock selection */
/*! @{ */

#define SYSCON_I3CFCLKSTCSEL_SEL_MASK            (0x7U)
#define SYSCON_I3CFCLKSTCSEL_SEL_SHIFT           (0U)
/*! SEL - I3C FCLK_STC clock select
 *  0b000..I3CFCLK
 *  0b001..FRO_1M
 *  0b010..No clock
 *  0b011..No clock
 *  0b100..No clock
 *  0b101..No clock
 *  0b110..No clock
 *  0b111..No clock
 */
#define SYSCON_I3CFCLKSTCSEL_SEL(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_I3CFCLKSTCSEL_SEL_SHIFT)) & SYSCON_I3CFCLKSTCSEL_SEL_MASK)
/*! @} */

/*! @name I3CFCLKSTCDIV - I3C FCLK_STC clock divider */
/*! @{ */

#define SYSCON_I3CFCLKSTCDIV_DIV_MASK            (0x7U)
#define SYSCON_I3CFCLKSTCDIV_DIV_SHIFT           (0U)
/*! DIV - Clock divider value.
 */
#define SYSCON_I3CFCLKSTCDIV_DIV(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_I3CFCLKSTCDIV_DIV_SHIFT)) & SYSCON_I3CFCLKSTCDIV_DIV_MASK)

#define SYSCON_I3CFCLKSTCDIV_RESET_MASK          (0x20000000U)
#define SYSCON_I3CFCLKSTCDIV_RESET_SHIFT         (29U)
/*! RESET - Resets the divider counter.
 *  0b1..Divider is reset.
 *  0b0..Divider is not reset.
 */
#define SYSCON_I3CFCLKSTCDIV_RESET(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_I3CFCLKSTCDIV_RESET_SHIFT)) & SYSCON_I3CFCLKSTCDIV_RESET_MASK)

#define SYSCON_I3CFCLKSTCDIV_HALT_MASK           (0x40000000U)
#define SYSCON_I3CFCLKSTCDIV_HALT_SHIFT          (30U)
/*! HALT - Halts the divider counter.
 *  0b1..Divider clock is stopped.
 *  0b0..Divider clock is running.
 */
#define SYSCON_I3CFCLKSTCDIV_HALT(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_I3CFCLKSTCDIV_HALT_SHIFT)) & SYSCON_I3CFCLKSTCDIV_HALT_MASK)

#define SYSCON_I3CFCLKSTCDIV_UNSTAB_MASK         (0x80000000U)
#define SYSCON_I3CFCLKSTCDIV_UNSTAB_SHIFT        (31U)
/*! UNSTAB - Divider status flag.
 *  0b1..Clock frequency is not stable.
 *  0b0..Divider clock is stable.
 */
#define SYSCON_I3CFCLKSTCDIV_UNSTAB(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_I3CFCLKSTCDIV_UNSTAB_SHIFT)) & SYSCON_I3CFCLKSTCDIV_UNSTAB_MASK)
/*! @} */

/*! @name I3CFCLKSDIV - I3C FCLKS clock divider */
/*! @{ */

#define SYSCON_I3CFCLKSDIV_DIV_MASK              (0x7U)
#define SYSCON_I3CFCLKSDIV_DIV_SHIFT             (0U)
/*! DIV - Clock divider value.
 */
#define SYSCON_I3CFCLKSDIV_DIV(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_I3CFCLKSDIV_DIV_SHIFT)) & SYSCON_I3CFCLKSDIV_DIV_MASK)

#define SYSCON_I3CFCLKSDIV_RESET_MASK            (0x20000000U)
#define SYSCON_I3CFCLKSDIV_RESET_SHIFT           (29U)
/*! RESET - Resets the divider counter.
 *  0b1..Divider is reset.
 *  0b0..Divider is not reset.
 */
#define SYSCON_I3CFCLKSDIV_RESET(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_I3CFCLKSDIV_RESET_SHIFT)) & SYSCON_I3CFCLKSDIV_RESET_MASK)

#define SYSCON_I3CFCLKSDIV_HALT_MASK             (0x40000000U)
#define SYSCON_I3CFCLKSDIV_HALT_SHIFT            (30U)
/*! HALT - Halts the divider counter.
 *  0b1..Divider clock is stopped.
 *  0b0..Divider clock is running.
 */
#define SYSCON_I3CFCLKSDIV_HALT(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_I3CFCLKSDIV_HALT_SHIFT)) & SYSCON_I3CFCLKSDIV_HALT_MASK)

#define SYSCON_I3CFCLKSDIV_UNSTAB_MASK           (0x80000000U)
#define SYSCON_I3CFCLKSDIV_UNSTAB_SHIFT          (31U)
/*! UNSTAB - Divider status flag.
 *  0b1..Clock frequency is not stable.
 *  0b0..Divider clock is stable.
 */
#define SYSCON_I3CFCLKSDIV_UNSTAB(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_I3CFCLKSDIV_UNSTAB_SHIFT)) & SYSCON_I3CFCLKSDIV_UNSTAB_MASK)
/*! @} */

/*! @name I3CFCLKDIV - I3C FCLK divider */
/*! @{ */

#define SYSCON_I3CFCLKDIV_DIV_MASK               (0x7U)
#define SYSCON_I3CFCLKDIV_DIV_SHIFT              (0U)
/*! DIV - Clock divider value.
 */
#define SYSCON_I3CFCLKDIV_DIV(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_I3CFCLKDIV_DIV_SHIFT)) & SYSCON_I3CFCLKDIV_DIV_MASK)

#define SYSCON_I3CFCLKDIV_RESET_MASK             (0x20000000U)
#define SYSCON_I3CFCLKDIV_RESET_SHIFT            (29U)
/*! RESET - Resets the divider counter.
 *  0b1..Divider is reset.
 *  0b0..Divider is not reset.
 */
#define SYSCON_I3CFCLKDIV_RESET(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_I3CFCLKDIV_RESET_SHIFT)) & SYSCON_I3CFCLKDIV_RESET_MASK)

#define SYSCON_I3CFCLKDIV_HALT_MASK              (0x40000000U)
#define SYSCON_I3CFCLKDIV_HALT_SHIFT             (30U)
/*! HALT - Halts the divider counter.
 *  0b1..Divider clock is stopped.
 *  0b0..Divider clock is running.
 */
#define SYSCON_I3CFCLKDIV_HALT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_I3CFCLKDIV_HALT_SHIFT)) & SYSCON_I3CFCLKDIV_HALT_MASK)

#define SYSCON_I3CFCLKDIV_UNSTAB_MASK            (0x80000000U)
#define SYSCON_I3CFCLKDIV_UNSTAB_SHIFT           (31U)
/*! UNSTAB - Divider status flag.
 *  0b1..Clock frequency is not stable.
 *  0b0..Divider clock is stable.
 */
#define SYSCON_I3CFCLKDIV_UNSTAB(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_I3CFCLKDIV_UNSTAB_SHIFT)) & SYSCON_I3CFCLKDIV_UNSTAB_MASK)
/*! @} */

/*! @name I3CFCLKSSEL - I3C FCLK_S selection */
/*! @{ */

#define SYSCON_I3CFCLKSSEL_SEL_MASK              (0x7U)
#define SYSCON_I3CFCLKSSEL_SEL_SHIFT             (0U)
/*! SEL - I3C FCLK_S clock select
 *  0b000..FRO_1M
 *  0b001..No clock
 *  0b010..No clock
 *  0b011..No clock
 *  0b100..No clock
 *  0b101..No clock
 *  0b110..No clock
 *  0b111..No clock
 */
#define SYSCON_I3CFCLKSSEL_SEL(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_I3CFCLKSSEL_SEL_SHIFT)) & SYSCON_I3CFCLKSSEL_SEL_MASK)
/*! @} */

/*! @name DMICFCLKSEL - DMIC clock selection */
/*! @{ */

#define SYSCON_DMICFCLKSEL_SEL_MASK              (0x7U)
#define SYSCON_DMICFCLKSEL_SEL_SHIFT             (0U)
/*! SEL - DMIC clock select
 *  0b000..Main clock
 *  0b001..PLL0 clock
 *  0b010..Clock in
 *  0b011..FRO_HF
 *  0b100..PLL1 clock
 *  0b101..MCLK in
 *  0b110..No clock
 *  0b111..No clock
 */
#define SYSCON_DMICFCLKSEL_SEL(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICFCLKSEL_SEL_SHIFT)) & SYSCON_DMICFCLKSEL_SEL_MASK)
/*! @} */

/*! @name DMICFCLKDIV - DMIC clock division */
/*! @{ */

#define SYSCON_DMICFCLKDIV_DIV_MASK              (0xFFU)
#define SYSCON_DMICFCLKDIV_DIV_SHIFT             (0U)
/*! DIV - Clock divider value.
 */
#define SYSCON_DMICFCLKDIV_DIV(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICFCLKDIV_DIV_SHIFT)) & SYSCON_DMICFCLKDIV_DIV_MASK)

#define SYSCON_DMICFCLKDIV_RESET_MASK            (0x20000000U)
#define SYSCON_DMICFCLKDIV_RESET_SHIFT           (29U)
/*! RESET - Resets the divider counter.
 *  0b1..Divider is reset.
 *  0b0..Divider is not reset.
 */
#define SYSCON_DMICFCLKDIV_RESET(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICFCLKDIV_RESET_SHIFT)) & SYSCON_DMICFCLKDIV_RESET_MASK)

#define SYSCON_DMICFCLKDIV_HALT_MASK             (0x40000000U)
#define SYSCON_DMICFCLKDIV_HALT_SHIFT            (30U)
/*! HALT - Halts the divider counter.
 *  0b1..Divider clock is stopped.
 *  0b0..Divider clock is running.
 */
#define SYSCON_DMICFCLKDIV_HALT(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICFCLKDIV_HALT_SHIFT)) & SYSCON_DMICFCLKDIV_HALT_MASK)

#define SYSCON_DMICFCLKDIV_UNSTAB_MASK           (0x80000000U)
#define SYSCON_DMICFCLKDIV_UNSTAB_SHIFT          (31U)
/*! UNSTAB - Divider status flag.
 *  0b1..Clock frequency is not stable.
 *  0b0..Divider clock is stable.
 */
#define SYSCON_DMICFCLKDIV_UNSTAB(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICFCLKDIV_UNSTAB_SHIFT)) & SYSCON_DMICFCLKDIV_UNSTAB_MASK)
/*! @} */

/*! @name PLL1CTRL - PLL1 550m control */
/*! @{ */

#define SYSCON_PLL1CTRL_SELR_MASK                (0xFU)
#define SYSCON_PLL1CTRL_SELR_SHIFT               (0U)
/*! SELR - Bandwidth select R value.
 */
#define SYSCON_PLL1CTRL_SELR(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELR_SHIFT)) & SYSCON_PLL1CTRL_SELR_MASK)

#define SYSCON_PLL1CTRL_SELI_MASK                (0x3F0U)
#define SYSCON_PLL1CTRL_SELI_SHIFT               (4U)
/*! SELI - Bandwidth select I value.
 */
#define SYSCON_PLL1CTRL_SELI(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELI_SHIFT)) & SYSCON_PLL1CTRL_SELI_MASK)

#define SYSCON_PLL1CTRL_SELP_MASK                (0x7C00U)
#define SYSCON_PLL1CTRL_SELP_SHIFT               (10U)
/*! SELP - Bandwidth select P value.
 */
#define SYSCON_PLL1CTRL_SELP(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELP_SHIFT)) & SYSCON_PLL1CTRL_SELP_MASK)

#define SYSCON_PLL1CTRL_BYPASSPLL_MASK           (0x8000U)
#define SYSCON_PLL1CTRL_BYPASSPLL_SHIFT          (15U)
/*! BYPASSPLL - Bypass PLL input clock is sent directly to the PLL output (default).
 *  0b1..PLL input clock is sent directly to the PLL output.
 *  0b0..use PLL.
 */
#define SYSCON_PLL1CTRL_BYPASSPLL(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPLL_MASK)

#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK      (0x10000U)
#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2_SHIFT     (16U)
/*! BYPASSPOSTDIV2 - bypass of the divide-by-2 divider in the post-divider.
 *  0b1..bypass of the divide-by-2 divider in the post-divider.
 *  0b0..use the divide-by-2 divider in the post-divider.
 */
#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPOSTDIV2_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK)

#define SYSCON_PLL1CTRL_LIMUPOFF_MASK            (0x20000U)
#define SYSCON_PLL1CTRL_LIMUPOFF_SHIFT           (17U)
/*! LIMUPOFF - limup_off = 1 in spread spectrum and fractional PLL applications.
 */
#define SYSCON_PLL1CTRL_LIMUPOFF(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_LIMUPOFF_SHIFT)) & SYSCON_PLL1CTRL_LIMUPOFF_MASK)

#define SYSCON_PLL1CTRL_BWDIRECT_MASK            (0x40000U)
#define SYSCON_PLL1CTRL_BWDIRECT_SHIFT           (18U)
/*! BWDIRECT - control of the bandwidth of the PLL.
 *  0b1..modify the bandwidth of the PLL directly.
 *  0b0..the bandwidth is changed synchronously with the feedback-divider.
 */
#define SYSCON_PLL1CTRL_BWDIRECT(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BWDIRECT_SHIFT)) & SYSCON_PLL1CTRL_BWDIRECT_MASK)

#define SYSCON_PLL1CTRL_BYPASSPREDIV_MASK        (0x80000U)
#define SYSCON_PLL1CTRL_BYPASSPREDIV_SHIFT       (19U)
/*! BYPASSPREDIV - bypass of the pre-divider.
 *  0b1..bypass of the pre-divider.
 *  0b0..use the pre-divider.
 */
#define SYSCON_PLL1CTRL_BYPASSPREDIV(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPREDIV_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK)

#define SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK       (0x100000U)
#define SYSCON_PLL1CTRL_BYPASSPOSTDIV_SHIFT      (20U)
/*! BYPASSPOSTDIV - bypass of the post-divider.
 *  0b1..bypass of the post-divider.
 *  0b0..use the post-divider.
 */
#define SYSCON_PLL1CTRL_BYPASSPOSTDIV(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPOSTDIV_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK)

#define SYSCON_PLL1CTRL_CLKEN_MASK               (0x200000U)
#define SYSCON_PLL1CTRL_CLKEN_SHIFT              (21U)
/*! CLKEN - enable the output clock.
 *  0b1..Enable the output clock.
 *  0b0..Disable the output clock.
 */
#define SYSCON_PLL1CTRL_CLKEN(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_CLKEN_SHIFT)) & SYSCON_PLL1CTRL_CLKEN_MASK)

#define SYSCON_PLL1CTRL_FRMEN_MASK               (0x400000U)
#define SYSCON_PLL1CTRL_FRMEN_SHIFT              (22U)
/*! FRMEN - 1: free running mode.
 */
#define SYSCON_PLL1CTRL_FRMEN(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_FRMEN_SHIFT)) & SYSCON_PLL1CTRL_FRMEN_MASK)

#define SYSCON_PLL1CTRL_FRMCLKSTABLE_MASK        (0x800000U)
#define SYSCON_PLL1CTRL_FRMCLKSTABLE_SHIFT       (23U)
/*! FRMCLKSTABLE - free running mode clockstable: Warning: Only make frm_clockstable = 1 after the PLL output frequency is stable.
 */
#define SYSCON_PLL1CTRL_FRMCLKSTABLE(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_FRMCLKSTABLE_SHIFT)) & SYSCON_PLL1CTRL_FRMCLKSTABLE_MASK)

#define SYSCON_PLL1CTRL_SKEWEN_MASK              (0x1000000U)
#define SYSCON_PLL1CTRL_SKEWEN_SHIFT             (24U)
/*! SKEWEN - Skew mode.
 *  0b1..skewmode is enable.
 *  0b0..skewmode is disable.
 */
#define SYSCON_PLL1CTRL_SKEWEN(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SKEWEN_SHIFT)) & SYSCON_PLL1CTRL_SKEWEN_MASK)
/*! @} */

/*! @name PLL1STAT - PLL1 550m status */
/*! @{ */

#define SYSCON_PLL1STAT_LOCK_MASK                (0x1U)
#define SYSCON_PLL1STAT_LOCK_SHIFT               (0U)
/*! LOCK - lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz.
 */
#define SYSCON_PLL1STAT_LOCK(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_LOCK_SHIFT)) & SYSCON_PLL1STAT_LOCK_MASK)

#define SYSCON_PLL1STAT_PREDIVACK_MASK           (0x2U)
#define SYSCON_PLL1STAT_PREDIVACK_SHIFT          (1U)
/*! PREDIVACK - pre-divider ratio change acknowledge.
 */
#define SYSCON_PLL1STAT_PREDIVACK(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_PREDIVACK_SHIFT)) & SYSCON_PLL1STAT_PREDIVACK_MASK)

#define SYSCON_PLL1STAT_FEEDDIVACK_MASK          (0x4U)
#define SYSCON_PLL1STAT_FEEDDIVACK_SHIFT         (2U)
/*! FEEDDIVACK - feedback divider ratio change acknowledge.
 */
#define SYSCON_PLL1STAT_FEEDDIVACK(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_FEEDDIVACK_SHIFT)) & SYSCON_PLL1STAT_FEEDDIVACK_MASK)

#define SYSCON_PLL1STAT_POSTDIVACK_MASK          (0x8U)
#define SYSCON_PLL1STAT_POSTDIVACK_SHIFT         (3U)
/*! POSTDIVACK - post-divider ratio change acknowledge.
 */
#define SYSCON_PLL1STAT_POSTDIVACK(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_POSTDIVACK_SHIFT)) & SYSCON_PLL1STAT_POSTDIVACK_MASK)

#define SYSCON_PLL1STAT_FRMDET_MASK              (0x10U)
#define SYSCON_PLL1STAT_FRMDET_SHIFT             (4U)
/*! FRMDET - free running detector output (active high).
 */
#define SYSCON_PLL1STAT_FRMDET(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_FRMDET_SHIFT)) & SYSCON_PLL1STAT_FRMDET_MASK)
/*! @} */

/*! @name PLL1NDEC - PLL1 550m N divider */
/*! @{ */

#define SYSCON_PLL1NDEC_NDIV_MASK                (0xFFU)
#define SYSCON_PLL1NDEC_NDIV_SHIFT               (0U)
/*! NDIV - pre-divider divider ratio (N-divider).
 */
#define SYSCON_PLL1NDEC_NDIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1NDEC_NDIV_SHIFT)) & SYSCON_PLL1NDEC_NDIV_MASK)

#define SYSCON_PLL1NDEC_NREQ_MASK                (0x100U)
#define SYSCON_PLL1NDEC_NREQ_SHIFT               (8U)
/*! NREQ - pre-divider ratio change request.
 */
#define SYSCON_PLL1NDEC_NREQ(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1NDEC_NREQ_SHIFT)) & SYSCON_PLL1NDEC_NREQ_MASK)
/*! @} */

/*! @name PLL1MDEC - PLL1 550m M divider */
/*! @{ */

#define SYSCON_PLL1MDEC_MDIV_MASK                (0xFFFFU)
#define SYSCON_PLL1MDEC_MDIV_SHIFT               (0U)
/*! MDIV - feedback divider divider ratio (M-divider).
 */
#define SYSCON_PLL1MDEC_MDIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1MDEC_MDIV_SHIFT)) & SYSCON_PLL1MDEC_MDIV_MASK)

#define SYSCON_PLL1MDEC_MREQ_MASK                (0x10000U)
#define SYSCON_PLL1MDEC_MREQ_SHIFT               (16U)
/*! MREQ - feedback ratio change request.
 */
#define SYSCON_PLL1MDEC_MREQ(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1MDEC_MREQ_SHIFT)) & SYSCON_PLL1MDEC_MREQ_MASK)
/*! @} */

/*! @name PLL1PDEC - PLL1 550m P divider */
/*! @{ */

#define SYSCON_PLL1PDEC_PDIV_MASK                (0x1FU)
#define SYSCON_PLL1PDEC_PDIV_SHIFT               (0U)
/*! PDIV - post-divider divider ratio (P-divider)
 */
#define SYSCON_PLL1PDEC_PDIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1PDEC_PDIV_SHIFT)) & SYSCON_PLL1PDEC_PDIV_MASK)

#define SYSCON_PLL1PDEC_PREQ_MASK                (0x20U)
#define SYSCON_PLL1PDEC_PREQ_SHIFT               (5U)
/*! PREQ - feedback ratio change request.
 */
#define SYSCON_PLL1PDEC_PREQ(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1PDEC_PREQ_SHIFT)) & SYSCON_PLL1PDEC_PREQ_MASK)
/*! @} */

/*! @name PLL0CTRL - PLL0 550m control */
/*! @{ */

#define SYSCON_PLL0CTRL_SELR_MASK                (0xFU)
#define SYSCON_PLL0CTRL_SELR_SHIFT               (0U)
/*! SELR - Bandwidth select R value.
 */
#define SYSCON_PLL0CTRL_SELR(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELR_SHIFT)) & SYSCON_PLL0CTRL_SELR_MASK)

#define SYSCON_PLL0CTRL_SELI_MASK                (0x3F0U)
#define SYSCON_PLL0CTRL_SELI_SHIFT               (4U)
/*! SELI - Bandwidth select I value.
 */
#define SYSCON_PLL0CTRL_SELI(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELI_SHIFT)) & SYSCON_PLL0CTRL_SELI_MASK)

#define SYSCON_PLL0CTRL_SELP_MASK                (0x7C00U)
#define SYSCON_PLL0CTRL_SELP_SHIFT               (10U)
/*! SELP - Bandwidth select P value.
 */
#define SYSCON_PLL0CTRL_SELP(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELP_SHIFT)) & SYSCON_PLL0CTRL_SELP_MASK)

#define SYSCON_PLL0CTRL_BYPASSPLL_MASK           (0x8000U)
#define SYSCON_PLL0CTRL_BYPASSPLL_SHIFT          (15U)
/*! BYPASSPLL - Bypass PLL input clock is sent directly to the PLL output (default).
 *  0b1..Bypass PLL input clock is sent directly to the PLL output.
 *  0b0..use PLL.
 */
#define SYSCON_PLL0CTRL_BYPASSPLL(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPLL_MASK)

#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK      (0x10000U)
#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2_SHIFT     (16U)
/*! BYPASSPOSTDIV2 - bypass of the divide-by-2 divider in the post-divider.
 *  0b1..bypass of the divide-by-2 divider in the post-divider.
 *  0b0..use the divide-by-2 divider in the post-divider.
 */
#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPOSTDIV2_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK)

#define SYSCON_PLL0CTRL_LIMUPOFF_MASK            (0x20000U)
#define SYSCON_PLL0CTRL_LIMUPOFF_SHIFT           (17U)
/*! LIMUPOFF - limup_off = 1 in spread spectrum and fractional PLL applications.
 */
#define SYSCON_PLL0CTRL_LIMUPOFF(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_LIMUPOFF_SHIFT)) & SYSCON_PLL0CTRL_LIMUPOFF_MASK)

#define SYSCON_PLL0CTRL_BWDIRECT_MASK            (0x40000U)
#define SYSCON_PLL0CTRL_BWDIRECT_SHIFT           (18U)
/*! BWDIRECT - Control of the bandwidth of the PLL.
 *  0b1..modify the bandwidth of the PLL directly.
 *  0b0..the bandwidth is changed synchronously with the feedback-divider.
 */
#define SYSCON_PLL0CTRL_BWDIRECT(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BWDIRECT_SHIFT)) & SYSCON_PLL0CTRL_BWDIRECT_MASK)

#define SYSCON_PLL0CTRL_BYPASSPREDIV_MASK        (0x80000U)
#define SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT       (19U)
/*! BYPASSPREDIV - bypass of the pre-divider.
 *  0b1..bypass of the pre-divider.
 *  0b0..use the pre-divider.
 */
#define SYSCON_PLL0CTRL_BYPASSPREDIV(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK)

#define SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK       (0x100000U)
#define SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT      (20U)
/*! BYPASSPOSTDIV - bypass of the post-divider.
 *  0b1..bypass of the post-divider.
 *  0b0..use the post-divider.
 */
#define SYSCON_PLL0CTRL_BYPASSPOSTDIV(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK)

#define SYSCON_PLL0CTRL_CLKEN_MASK               (0x200000U)
#define SYSCON_PLL0CTRL_CLKEN_SHIFT              (21U)
/*! CLKEN - enable the output clock.
 *  0b1..enable the output clock.
 *  0b0..disable the output clock.
 */
#define SYSCON_PLL0CTRL_CLKEN(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_CLKEN_SHIFT)) & SYSCON_PLL0CTRL_CLKEN_MASK)

#define SYSCON_PLL0CTRL_FRMEN_MASK               (0x400000U)
#define SYSCON_PLL0CTRL_FRMEN_SHIFT              (22U)
/*! FRMEN - free running mode.
 *  0b1..free running mode is enable.
 *  0b0..free running mode is disable.
 */
#define SYSCON_PLL0CTRL_FRMEN(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_FRMEN_SHIFT)) & SYSCON_PLL0CTRL_FRMEN_MASK)

#define SYSCON_PLL0CTRL_FRMCLKSTABLE_MASK        (0x800000U)
#define SYSCON_PLL0CTRL_FRMCLKSTABLE_SHIFT       (23U)
/*! FRMCLKSTABLE - free running mode clockstable: Warning: Only make frm_clockstable =1 after the PLL output frequency is stable.
 */
#define SYSCON_PLL0CTRL_FRMCLKSTABLE(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_FRMCLKSTABLE_SHIFT)) & SYSCON_PLL0CTRL_FRMCLKSTABLE_MASK)

#define SYSCON_PLL0CTRL_SKEWEN_MASK              (0x1000000U)
#define SYSCON_PLL0CTRL_SKEWEN_SHIFT             (24U)
/*! SKEWEN - skew mode.
 *  0b1..skew mode is enable.
 *  0b0..skew mode is disable.
 */
#define SYSCON_PLL0CTRL_SKEWEN(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SKEWEN_SHIFT)) & SYSCON_PLL0CTRL_SKEWEN_MASK)
/*! @} */

/*! @name PLL0STAT - PLL0 550m status */
/*! @{ */

#define SYSCON_PLL0STAT_LOCK_MASK                (0x1U)
#define SYSCON_PLL0STAT_LOCK_SHIFT               (0U)
/*! LOCK - lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz.
 */
#define SYSCON_PLL0STAT_LOCK(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_LOCK_SHIFT)) & SYSCON_PLL0STAT_LOCK_MASK)

#define SYSCON_PLL0STAT_PREDIVACK_MASK           (0x2U)
#define SYSCON_PLL0STAT_PREDIVACK_SHIFT          (1U)
/*! PREDIVACK - pre-divider ratio change acknowledge.
 */
#define SYSCON_PLL0STAT_PREDIVACK(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_PREDIVACK_SHIFT)) & SYSCON_PLL0STAT_PREDIVACK_MASK)

#define SYSCON_PLL0STAT_FEEDDIVACK_MASK          (0x4U)
#define SYSCON_PLL0STAT_FEEDDIVACK_SHIFT         (2U)
/*! FEEDDIVACK - feedback divider ratio change acknowledge.
 */
#define SYSCON_PLL0STAT_FEEDDIVACK(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_FEEDDIVACK_SHIFT)) & SYSCON_PLL0STAT_FEEDDIVACK_MASK)

#define SYSCON_PLL0STAT_POSTDIVACK_MASK          (0x8U)
#define SYSCON_PLL0STAT_POSTDIVACK_SHIFT         (3U)
/*! POSTDIVACK - post-divider ratio change acknowledge.
 */
#define SYSCON_PLL0STAT_POSTDIVACK(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_POSTDIVACK_SHIFT)) & SYSCON_PLL0STAT_POSTDIVACK_MASK)

#define SYSCON_PLL0STAT_FRMDET_MASK              (0x10U)
#define SYSCON_PLL0STAT_FRMDET_SHIFT             (4U)
/*! FRMDET - free running detector output (active high).
 */
#define SYSCON_PLL0STAT_FRMDET(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_FRMDET_SHIFT)) & SYSCON_PLL0STAT_FRMDET_MASK)
/*! @} */

/*! @name PLL0NDEC - PLL0 550m N divider */
/*! @{ */

#define SYSCON_PLL0NDEC_NDIV_MASK                (0xFFU)
#define SYSCON_PLL0NDEC_NDIV_SHIFT               (0U)
/*! NDIV - pre-divider divider ratio (N-divider).
 */
#define SYSCON_PLL0NDEC_NDIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0NDEC_NDIV_SHIFT)) & SYSCON_PLL0NDEC_NDIV_MASK)

#define SYSCON_PLL0NDEC_NREQ_MASK                (0x100U)
#define SYSCON_PLL0NDEC_NREQ_SHIFT               (8U)
/*! NREQ - pre-divider ratio change request.
 */
#define SYSCON_PLL0NDEC_NREQ(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0NDEC_NREQ_SHIFT)) & SYSCON_PLL0NDEC_NREQ_MASK)
/*! @} */

/*! @name PLL0PDEC - PLL0 550m P divider */
/*! @{ */

#define SYSCON_PLL0PDEC_PDIV_MASK                (0x1FU)
#define SYSCON_PLL0PDEC_PDIV_SHIFT               (0U)
/*! PDIV - post-divider divider ratio (P-divider)
 */
#define SYSCON_PLL0PDEC_PDIV(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0PDEC_PDIV_SHIFT)) & SYSCON_PLL0PDEC_PDIV_MASK)

#define SYSCON_PLL0PDEC_PREQ_MASK                (0x20U)
#define SYSCON_PLL0PDEC_PREQ_SHIFT               (5U)
/*! PREQ - feedback ratio change request.
 */
#define SYSCON_PLL0PDEC_PREQ(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0PDEC_PREQ_SHIFT)) & SYSCON_PLL0PDEC_PREQ_MASK)
/*! @} */

/*! @name PLL0SSCG0 - PLL0 Spread Spectrum control 0 */
/*! @{ */

#define SYSCON_PLL0SSCG0_MD_LBS_MASK             (0xFFFFFFFFU)
#define SYSCON_PLL0SSCG0_MD_LBS_SHIFT            (0U)
/*! MD_LBS - input word of the wrapper bit 31 to 0.
 */
#define SYSCON_PLL0SSCG0_MD_LBS(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG0_MD_LBS_SHIFT)) & SYSCON_PLL0SSCG0_MD_LBS_MASK)
/*! @} */

/*! @name PLL0SSCG1 - PLL0 Spread Spectrum control 1 */
/*! @{ */

#define SYSCON_PLL0SSCG1_MD_MBS_MASK             (0x1U)
#define SYSCON_PLL0SSCG1_MD_MBS_SHIFT            (0U)
/*! MD_MBS - input word of the wrapper bit 32.
 */
#define SYSCON_PLL0SSCG1_MD_MBS(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MD_MBS_SHIFT)) & SYSCON_PLL0SSCG1_MD_MBS_MASK)

#define SYSCON_PLL0SSCG1_MD_REQ_MASK             (0x2U)
#define SYSCON_PLL0SSCG1_MD_REQ_SHIFT            (1U)
/*! MD_REQ - md change request.
 */
#define SYSCON_PLL0SSCG1_MD_REQ(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MD_REQ_SHIFT)) & SYSCON_PLL0SSCG1_MD_REQ_MASK)

#define SYSCON_PLL0SSCG1_MF_MASK                 (0x1CU)
#define SYSCON_PLL0SSCG1_MF_SHIFT                (2U)
/*! MF - programmable modulation frequency fm = Fref/Nss mf[2:0] = 000 => Nss=512 (fm ~ 3.
 */
#define SYSCON_PLL0SSCG1_MF(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MF_SHIFT)) & SYSCON_PLL0SSCG1_MF_MASK)

#define SYSCON_PLL0SSCG1_MR_MASK                 (0xE0U)
#define SYSCON_PLL0SSCG1_MR_SHIFT                (5U)
/*! MR - programmable frequency modulation depth Dfmodpk-pk = Fref*kss/Fcco = kss/(2*md[32:25]dec)
 *    mr[2:0] = 000 => kss = 0 (no spread spectrum) mr[2:0] = 001 => kss ~ 1 mr[2:0] = 010 => kss ~ 1.
 */
#define SYSCON_PLL0SSCG1_MR(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MR_SHIFT)) & SYSCON_PLL0SSCG1_MR_MASK)

#define SYSCON_PLL0SSCG1_MC_MASK                 (0x300U)
#define SYSCON_PLL0SSCG1_MC_SHIFT                (8U)
/*! MC - modulation waveform control Compensation for low pass filtering of the PLL to get a
 *    triangular modulation at the output of the PLL, giving a flat frequency spectrum.
 */
#define SYSCON_PLL0SSCG1_MC(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MC_SHIFT)) & SYSCON_PLL0SSCG1_MC_MASK)

#define SYSCON_PLL0SSCG1_MDIV_EXT_MASK           (0x3FFFC00U)
#define SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT          (10U)
/*! MDIV_EXT - to select an external mdiv value.
 */
#define SYSCON_PLL0SSCG1_MDIV_EXT(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT)) & SYSCON_PLL0SSCG1_MDIV_EXT_MASK)

#define SYSCON_PLL0SSCG1_MREQ_MASK               (0x4000000U)
#define SYSCON_PLL0SSCG1_MREQ_SHIFT              (26U)
/*! MREQ - to select an external mreq value.
 */
#define SYSCON_PLL0SSCG1_MREQ(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MREQ_SHIFT)) & SYSCON_PLL0SSCG1_MREQ_MASK)

#define SYSCON_PLL0SSCG1_DITHER_MASK             (0x8000000U)
#define SYSCON_PLL0SSCG1_DITHER_SHIFT            (27U)
/*! DITHER - dithering between two modulation frequencies in a random way or in a pseudo random way
 *    (white noise), in order to decrease the probability that the modulated waveform will occur
 *    with the same phase on a particular point on the screen.
 */
#define SYSCON_PLL0SSCG1_DITHER(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_DITHER_SHIFT)) & SYSCON_PLL0SSCG1_DITHER_MASK)

#define SYSCON_PLL0SSCG1_SEL_EXT_MASK            (0x10000000U)
#define SYSCON_PLL0SSCG1_SEL_EXT_SHIFT           (28U)
/*! SEL_EXT - to select mdiv_ext and mreq_ext sel_ext = 0: mdiv ~ md[32:0], mreq = 1 sel_ext = 1 : mdiv = mdiv_ext, mreq = mreq_ext.
 */
#define SYSCON_PLL0SSCG1_SEL_EXT(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_SEL_EXT_SHIFT)) & SYSCON_PLL0SSCG1_SEL_EXT_MASK)
/*! @} */

/*! @name DAC_ISO_CTRL - DAC Isolation Control */
/*! @{ */

#define SYSCON_DAC_ISO_CTRL_DAC0_ISO_MASK        (0x1U)
#define SYSCON_DAC_ISO_CTRL_DAC0_ISO_SHIFT       (0U)
/*! DAC0_ISO - DAC0 Isolation
 *  0b0..DAC0 isolation disabled
 *  0b1..DAC0 isolation enabled
 */
#define SYSCON_DAC_ISO_CTRL_DAC0_ISO(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_DAC_ISO_CTRL_DAC0_ISO_SHIFT)) & SYSCON_DAC_ISO_CTRL_DAC0_ISO_MASK)

#define SYSCON_DAC_ISO_CTRL_DAC1_ISO_MASK        (0x2U)
#define SYSCON_DAC_ISO_CTRL_DAC1_ISO_SHIFT       (1U)
/*! DAC1_ISO - DAC1 Isolation
 *  0b0..DAC1 isolation disabled
 *  0b1..DAC1 isolation enabled
 */
#define SYSCON_DAC_ISO_CTRL_DAC1_ISO(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_DAC_ISO_CTRL_DAC1_ISO_SHIFT)) & SYSCON_DAC_ISO_CTRL_DAC1_ISO_MASK)

#define SYSCON_DAC_ISO_CTRL_DAC2_ISO_MASK        (0x4U)
#define SYSCON_DAC_ISO_CTRL_DAC2_ISO_SHIFT       (2U)
/*! DAC2_ISO - DAC2 Isolation
 *  0b0..DAC2 isolation disabled
 *  0b1..DAC2 isolation enabled
 */
#define SYSCON_DAC_ISO_CTRL_DAC2_ISO(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_DAC_ISO_CTRL_DAC2_ISO_SHIFT)) & SYSCON_DAC_ISO_CTRL_DAC2_ISO_MASK)
/*! @} */

/*! @name STARTER - Start logic wake-up enable */
/*! @{ */

#define SYSCON_STARTER_FLEXPWM1_COMPARE1_IRQ_MASK (0x1U)
#define SYSCON_STARTER_FLEXPWM1_COMPARE1_IRQ_SHIFT (0U)
/*! FLEXPWM1_COMPARE1_IRQ - FlexPWM1 compare interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_FLEXPWM1_COMPARE1_IRQ(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM1_COMPARE1_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM1_COMPARE1_IRQ_MASK)

#define SYSCON_STARTER_GPIO_INT04_MASK           (0x1U)
#define SYSCON_STARTER_GPIO_INT04_SHIFT          (0U)
/*! GPIO_INT04 - GPIO_INT04 interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_GPIO_INT04(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GPIO_INT04_SHIFT)) & SYSCON_STARTER_GPIO_INT04_MASK)

#define SYSCON_STARTER_SYS_MASK                  (0x1U)
#define SYSCON_STARTER_SYS_SHIFT                 (0U)
/*! SYS - SYS interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_SYS(x)                    (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SYS_SHIFT)) & SYSCON_STARTER_SYS_MASK)

#define SYSCON_STARTER_CSS_IRQ1_MASK             (0x2U)
#define SYSCON_STARTER_CSS_IRQ1_SHIFT            (1U)
/*! CSS_IRQ1 - CSS_IRQ1 (Digital Glitch Detect)
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_CSS_IRQ1(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CSS_IRQ1_SHIFT)) & SYSCON_STARTER_CSS_IRQ1_MASK)

#define SYSCON_STARTER_FLEXPWM1_RELOAD1_IRQ_MASK (0x2U)
#define SYSCON_STARTER_FLEXPWM1_RELOAD1_IRQ_SHIFT (1U)
/*! FLEXPWM1_RELOAD1_IRQ - FlexPWM1 reload interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_FLEXPWM1_RELOAD1_IRQ(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM1_RELOAD1_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM1_RELOAD1_IRQ_MASK)

#define SYSCON_STARTER_GPIO_INT05_MASK           (0x2U)
#define SYSCON_STARTER_GPIO_INT05_SHIFT          (1U)
/*! GPIO_INT05 - GPIO_INT05 interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_GPIO_INT05(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GPIO_INT05_SHIFT)) & SYSCON_STARTER_GPIO_INT05_MASK)

#define SYSCON_STARTER_SDMA0_MASK                (0x2U)
#define SYSCON_STARTER_SDMA0_SHIFT               (1U)
/*! SDMA0 - SDMA0 interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_SDMA0(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SDMA0_SHIFT)) & SYSCON_STARTER_SDMA0_MASK)

#define SYSCON_STARTER_FLEXPWM1_COMPARE2_IRQ_MASK (0x4U)
#define SYSCON_STARTER_FLEXPWM1_COMPARE2_IRQ_SHIFT (2U)
/*! FLEXPWM1_COMPARE2_IRQ - FlexPWM1 compare interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_FLEXPWM1_COMPARE2_IRQ(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM1_COMPARE2_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM1_COMPARE2_IRQ_MASK)

#define SYSCON_STARTER_GINT0_MASK                (0x4U)
#define SYSCON_STARTER_GINT0_SHIFT               (2U)
/*! GINT0 - GINT0 interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_GINT0(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GINT0_SHIFT)) & SYSCON_STARTER_GINT0_MASK)

#define SYSCON_STARTER_GPIO_INT06_MASK           (0x4U)
#define SYSCON_STARTER_GPIO_INT06_SHIFT          (2U)
/*! GPIO_INT06 - GPIO_INT06 interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_GPIO_INT06(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GPIO_INT06_SHIFT)) & SYSCON_STARTER_GPIO_INT06_MASK)

#define SYSCON_STARTER_TAMPER_IRQ_MASK           (0x4U)
#define SYSCON_STARTER_TAMPER_IRQ_SHIFT          (2U)
/*! TAMPER_IRQ - Tamper interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_TAMPER_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_TAMPER_IRQ_SHIFT)) & SYSCON_STARTER_TAMPER_IRQ_MASK)

#define SYSCON_STARTER_FLEXPWM1_RELOAD2_IRQ_MASK (0x8U)
#define SYSCON_STARTER_FLEXPWM1_RELOAD2_IRQ_SHIFT (3U)
/*! FLEXPWM1_RELOAD2_IRQ - FlexPWM1 reload interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_FLEXPWM1_RELOAD2_IRQ(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM1_RELOAD2_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM1_RELOAD2_IRQ_MASK)

#define SYSCON_STARTER_GINT1_MASK                (0x8U)
#define SYSCON_STARTER_GINT1_SHIFT               (3U)
/*! GINT1 - GINT1 interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_GINT1(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GINT1_SHIFT)) & SYSCON_STARTER_GINT1_MASK)

#define SYSCON_STARTER_GPIO_INT07_MASK           (0x8U)
#define SYSCON_STARTER_GPIO_INT07_SHIFT          (3U)
/*! GPIO_INT07 - GPIO_INT07 interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_GPIO_INT07(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GPIO_INT07_SHIFT)) & SYSCON_STARTER_GPIO_INT07_MASK)

#define SYSCON_STARTER_CTIMER2_MASK              (0x10U)
#define SYSCON_STARTER_CTIMER2_SHIFT             (4U)
/*! CTIMER2 - CTIMER2 interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_CTIMER2(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER2_SHIFT)) & SYSCON_STARTER_CTIMER2_MASK)

#define SYSCON_STARTER_FLEXPWM1_COMPARE3_IRQ_MASK (0x10U)
#define SYSCON_STARTER_FLEXPWM1_COMPARE3_IRQ_SHIFT (4U)
/*! FLEXPWM1_COMPARE3_IRQ - FlexPWM1 compare interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_FLEXPWM1_COMPARE3_IRQ(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM1_COMPARE3_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM1_COMPARE3_IRQ_MASK)

#define SYSCON_STARTER_PIO_INT0_MASK             (0x10U)
#define SYSCON_STARTER_PIO_INT0_SHIFT            (4U)
/*! PIO_INT0 - PIO_INT0 interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_PIO_INT0(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIO_INT0_SHIFT)) & SYSCON_STARTER_PIO_INT0_MASK)

#define SYSCON_STARTER_CTIMER4_MASK              (0x20U)
#define SYSCON_STARTER_CTIMER4_SHIFT             (5U)
/*! CTIMER4 - CTIMER4 interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_CTIMER4(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER4_SHIFT)) & SYSCON_STARTER_CTIMER4_MASK)

#define SYSCON_STARTER_FLEXPWM1_RELOAD3_IRQ_MASK (0x20U)
#define SYSCON_STARTER_FLEXPWM1_RELOAD3_IRQ_SHIFT (5U)
/*! FLEXPWM1_RELOAD3_IRQ - FlexPWM1 reload interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_FLEXPWM1_RELOAD3_IRQ(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM1_RELOAD3_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM1_RELOAD3_IRQ_MASK)

#define SYSCON_STARTER_PIO_INT1_MASK             (0x20U)
#define SYSCON_STARTER_PIO_INT1_SHIFT            (5U)
/*! PIO_INT1 - PIO_INT1 interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_PIO_INT1(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIO_INT1_SHIFT)) & SYSCON_STARTER_PIO_INT1_MASK)

#define SYSCON_STARTER_ENCO_COMPARE_IRQ_MASK     (0x40U)
#define SYSCON_STARTER_ENCO_COMPARE_IRQ_SHIFT    (6U)
/*! ENCO_COMPARE_IRQ - ENC0 compare interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_ENCO_COMPARE_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ENCO_COMPARE_IRQ_SHIFT)) & SYSCON_STARTER_ENCO_COMPARE_IRQ_MASK)

#define SYSCON_STARTER_OS_EVENT_MASK             (0x40U)
#define SYSCON_STARTER_OS_EVENT_SHIFT            (6U)
/*! OS_EVENT - OS_EVENT interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_OS_EVENT(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_OS_EVENT_SHIFT)) & SYSCON_STARTER_OS_EVENT_MASK)

#define SYSCON_STARTER_PIO_INT2_MASK             (0x40U)
#define SYSCON_STARTER_PIO_INT2_SHIFT            (6U)
/*! PIO_INT2 - PIO_INT2 interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_PIO_INT2(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIO_INT2_SHIFT)) & SYSCON_STARTER_PIO_INT2_MASK)

#define SYSCON_STARTER_ENCO_HOME_IRQ_MASK        (0x80U)
#define SYSCON_STARTER_ENCO_HOME_IRQ_SHIFT       (7U)
/*! ENCO_HOME_IRQ - ENC0 home interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_ENCO_HOME_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ENCO_HOME_IRQ_SHIFT)) & SYSCON_STARTER_ENCO_HOME_IRQ_MASK)

#define SYSCON_STARTER_FLEXSPI_MASK              (0x80U)
#define SYSCON_STARTER_FLEXSPI_SHIFT             (7U)
/*! FLEXSPI - FLEXSPI interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_FLEXSPI(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXSPI_SHIFT)) & SYSCON_STARTER_FLEXSPI_MASK)

#define SYSCON_STARTER_PIO_INT3_MASK             (0x80U)
#define SYSCON_STARTER_PIO_INT3_SHIFT            (7U)
/*! PIO_INT3 - PIO_INT3 interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_PIO_INT3(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIO_INT3_SHIFT)) & SYSCON_STARTER_PIO_INT3_MASK)

#define SYSCON_STARTER_ENCO_WDG_IRQ_MASK         (0x100U)
#define SYSCON_STARTER_ENCO_WDG_IRQ_SHIFT        (8U)
/*! ENCO_WDG_IRQ - ENC0 WDOG interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_ENCO_WDG_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ENCO_WDG_IRQ_SHIFT)) & SYSCON_STARTER_ENCO_WDG_IRQ_MASK)

#define SYSCON_STARTER_UTICK0_MASK               (0x100U)
#define SYSCON_STARTER_UTICK0_SHIFT              (8U)
/*! UTICK0 - UTICK0 interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_UTICK0(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_UTICK0_SHIFT)) & SYSCON_STARTER_UTICK0_MASK)

#define SYSCON_STARTER_ENCO_IDX_IRQ_MASK         (0x200U)
#define SYSCON_STARTER_ENCO_IDX_IRQ_SHIFT        (9U)
/*! ENCO_IDX_IRQ - ENC0 IDX interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_ENCO_IDX_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ENCO_IDX_IRQ_SHIFT)) & SYSCON_STARTER_ENCO_IDX_IRQ_MASK)

#define SYSCON_STARTER_MRT0_MASK                 (0x200U)
#define SYSCON_STARTER_MRT0_SHIFT                (9U)
/*! MRT0 - MRT0 interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_MRT0(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_MRT0_SHIFT)) & SYSCON_STARTER_MRT0_MASK)

#define SYSCON_STARTER_CTIMER0_MASK              (0x400U)
#define SYSCON_STARTER_CTIMER0_SHIFT             (10U)
/*! CTIMER0 - CTIMER0 interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_CTIMER0(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER0_SHIFT)) & SYSCON_STARTER_CTIMER0_MASK)

#define SYSCON_STARTER_DAC0_IRQ_MASK             (0x400U)
#define SYSCON_STARTER_DAC0_IRQ_SHIFT            (10U)
/*! DAC0_IRQ - DAC0 interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_DAC0_IRQ(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_DAC0_IRQ_SHIFT)) & SYSCON_STARTER_DAC0_IRQ_MASK)

#define SYSCON_STARTER_ENC1_COMPARE_IRQ_MASK     (0x400U)
#define SYSCON_STARTER_ENC1_COMPARE_IRQ_SHIFT    (10U)
/*! ENC1_COMPARE_IRQ - ENC1 compare interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_ENC1_COMPARE_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ENC1_COMPARE_IRQ_SHIFT)) & SYSCON_STARTER_ENC1_COMPARE_IRQ_MASK)

#define SYSCON_STARTER_CAN0_IRQ0_MASK            (0x800U)
#define SYSCON_STARTER_CAN0_IRQ0_SHIFT           (11U)
/*! CAN0_IRQ0 - CAN0_IRQ0 interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_CAN0_IRQ0(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CAN0_IRQ0_SHIFT)) & SYSCON_STARTER_CAN0_IRQ0_MASK)

#define SYSCON_STARTER_CTIMER1_MASK              (0x800U)
#define SYSCON_STARTER_CTIMER1_SHIFT             (11U)
/*! CTIMER1 - CTIMER1 interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_CTIMER1(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER1_SHIFT)) & SYSCON_STARTER_CTIMER1_MASK)

#define SYSCON_STARTER_DAC1_IRQ_MASK             (0x800U)
#define SYSCON_STARTER_DAC1_IRQ_SHIFT            (11U)
/*! DAC1_IRQ - DAC1 interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_DAC1_IRQ(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_DAC1_IRQ_SHIFT)) & SYSCON_STARTER_DAC1_IRQ_MASK)

#define SYSCON_STARTER_ENC1_HOME_IRQ_MASK        (0x800U)
#define SYSCON_STARTER_ENC1_HOME_IRQ_SHIFT       (11U)
/*! ENC1_HOME_IRQ - ENC1 home interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_ENC1_HOME_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ENC1_HOME_IRQ_SHIFT)) & SYSCON_STARTER_ENC1_HOME_IRQ_MASK)

#define SYSCON_STARTER_CAN0_IRQ1_MASK            (0x1000U)
#define SYSCON_STARTER_CAN0_IRQ1_SHIFT           (12U)
/*! CAN0_IRQ1 - CAN0_IRQ0 interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_CAN0_IRQ1(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CAN0_IRQ1_SHIFT)) & SYSCON_STARTER_CAN0_IRQ1_MASK)

#define SYSCON_STARTER_DAC2_IRQ_MASK             (0x1000U)
#define SYSCON_STARTER_DAC2_IRQ_SHIFT            (12U)
/*! DAC2_IRQ - DAC2 interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_DAC2_IRQ(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_DAC2_IRQ_SHIFT)) & SYSCON_STARTER_DAC2_IRQ_MASK)

#define SYSCON_STARTER_ENC1_WDG_IRQ_MASK         (0x1000U)
#define SYSCON_STARTER_ENC1_WDG_IRQ_SHIFT        (12U)
/*! ENC1_WDG_IRQ - ENC1 WDOG interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_ENC1_WDG_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ENC1_WDG_IRQ_SHIFT)) & SYSCON_STARTER_ENC1_WDG_IRQ_MASK)

#define SYSCON_STARTER_SCT0_MASK                 (0x1000U)
#define SYSCON_STARTER_SCT0_SHIFT                (12U)
/*! SCT0 - SCT0 interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_SCT0(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SCT0_SHIFT)) & SYSCON_STARTER_SCT0_MASK)

#define SYSCON_STARTER_CTIMER3_MASK              (0x2000U)
#define SYSCON_STARTER_CTIMER3_SHIFT             (13U)
/*! CTIMER3 - CTIMER3 interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_CTIMER3(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER3_SHIFT)) & SYSCON_STARTER_CTIMER3_MASK)

#define SYSCON_STARTER_ENC1_IDX_IRQ_MASK         (0x2000U)
#define SYSCON_STARTER_ENC1_IDX_IRQ_SHIFT        (13U)
/*! ENC1_IDX_IRQ - ENC1 IDX interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_ENC1_IDX_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ENC1_IDX_IRQ_SHIFT)) & SYSCON_STARTER_ENC1_IDX_IRQ_MASK)

#define SYSCON_STARTER_HS_CMP0_IRQ_MASK          (0x2000U)
#define SYSCON_STARTER_HS_CMP0_IRQ_SHIFT         (13U)
/*! HS_CMP0_IRQ - HS_CMP0 interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_HS_CMP0_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_HS_CMP0_IRQ_SHIFT)) & SYSCON_STARTER_HS_CMP0_IRQ_MASK)

#define SYSCON_STARTER_SPI_FILTER_MASK           (0x2000U)
#define SYSCON_STARTER_SPI_FILTER_SHIFT          (13U)
/*! SPI_FILTER - SPI_FILTER interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_SPI_FILTER(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SPI_FILTER_SHIFT)) & SYSCON_STARTER_SPI_FILTER_MASK)

#define SYSCON_STARTER_FLEXINT0_MASK             (0x4000U)
#define SYSCON_STARTER_FLEXINT0_SHIFT            (14U)
/*! FLEXINT0 - FLEXINT0 interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_FLEXINT0(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT0_SHIFT)) & SYSCON_STARTER_FLEXINT0_MASK)

#define SYSCON_STARTER_HS_CMP1_IRQ_MASK          (0x4000U)
#define SYSCON_STARTER_HS_CMP1_IRQ_SHIFT         (14U)
/*! HS_CMP1_IRQ - HS_CMP1 interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_HS_CMP1_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_HS_CMP1_IRQ_SHIFT)) & SYSCON_STARTER_HS_CMP1_IRQ_MASK)

#define SYSCON_STARTER_ITRC_IRQ_MASK             (0x4000U)
#define SYSCON_STARTER_ITRC_IRQ_SHIFT            (14U)
/*! ITRC_IRQ - ITRC interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_ITRC_IRQ(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ITRC_IRQ_SHIFT)) & SYSCON_STARTER_ITRC_IRQ_MASK)

#define SYSCON_STARTER_FLEXINT1_MASK             (0x8000U)
#define SYSCON_STARTER_FLEXINT1_SHIFT            (15U)
/*! FLEXINT1 - FLEXINT1 interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_FLEXINT1(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT1_SHIFT)) & SYSCON_STARTER_FLEXINT1_MASK)

#define SYSCON_STARTER_HS_CMP2_IRQ_MASK          (0x8000U)
#define SYSCON_STARTER_HS_CMP2_IRQ_SHIFT         (15U)
/*! HS_CMP2_IRQ - HS_CMP2 interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_HS_CMP2_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_HS_CMP2_IRQ_SHIFT)) & SYSCON_STARTER_HS_CMP2_IRQ_MASK)

#define SYSCON_STARTER_CSSV2_ERR_MASK            (0x10000U)
#define SYSCON_STARTER_CSSV2_ERR_SHIFT           (16U)
/*! CSSV2_ERR - CSSv2 error interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_CSSV2_ERR(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CSSV2_ERR_SHIFT)) & SYSCON_STARTER_CSSV2_ERR_MASK)

#define SYSCON_STARTER_FLEXINT2_MASK             (0x10000U)
#define SYSCON_STARTER_FLEXINT2_SHIFT            (16U)
/*! FLEXINT2 - FLEXINT2 interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_FLEXINT2(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT2_SHIFT)) & SYSCON_STARTER_FLEXINT2_MASK)

#define SYSCON_STARTER_FLEXPWM0_CAPTURE_IRQ_MASK (0x10000U)
#define SYSCON_STARTER_FLEXPWM0_CAPTURE_IRQ_SHIFT (16U)
/*! FLEXPWM0_CAPTURE_IRQ - FlexPWM0 capture interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_FLEXPWM0_CAPTURE_IRQ(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM0_CAPTURE_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM0_CAPTURE_IRQ_MASK)

#define SYSCON_STARTER_FLEXINT3_MASK             (0x20000U)
#define SYSCON_STARTER_FLEXINT3_SHIFT            (17U)
/*! FLEXINT3 - FLEXINT3 interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_FLEXINT3(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT3_SHIFT)) & SYSCON_STARTER_FLEXINT3_MASK)

#define SYSCON_STARTER_FLEXPWM0_FAULT_IRQ_MASK   (0x20000U)
#define SYSCON_STARTER_FLEXPWM0_FAULT_IRQ_SHIFT  (17U)
/*! FLEXPWM0_FAULT_IRQ - FlexPWM0 fault interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_FLEXPWM0_FAULT_IRQ(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM0_FAULT_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM0_FAULT_IRQ_MASK)

#define SYSCON_STARTER_PKC_ERR_IRQ_MASK          (0x20000U)
#define SYSCON_STARTER_PKC_ERR_IRQ_SHIFT         (17U)
/*! PKC_ERR_IRQ - PKC error interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_PKC_ERR_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PKC_ERR_IRQ_SHIFT)) & SYSCON_STARTER_PKC_ERR_IRQ_MASK)

#define SYSCON_STARTER_SEC_HYPERVISOR_CALL_MASK  (0x20000U)
#define SYSCON_STARTER_SEC_HYPERVISOR_CALL_SHIFT (17U)
/*! SEC_HYPERVISOR_CALL - SEC_HYPERVISOR_CALL interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_SEC_HYPERVISOR_CALL(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SEC_HYPERVISOR_CALL_SHIFT)) & SYSCON_STARTER_SEC_HYPERVISOR_CALL_MASK)

#define SYSCON_STARTER_FLEXINT4_MASK             (0x40000U)
#define SYSCON_STARTER_FLEXINT4_SHIFT            (18U)
/*! FLEXINT4 - FLEXINT4 interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_FLEXINT4(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT4_SHIFT)) & SYSCON_STARTER_FLEXINT4_MASK)

#define SYSCON_STARTER_FLEXPWM0_RELOAD_ERR_IRQ_MASK (0x40000U)
#define SYSCON_STARTER_FLEXPWM0_RELOAD_ERR_IRQ_SHIFT (18U)
/*! FLEXPWM0_RELOAD_ERR_IRQ - FlexPWM0 reload error interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_FLEXPWM0_RELOAD_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM0_RELOAD_ERR_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM0_RELOAD_ERR_IRQ_MASK)

#define SYSCON_STARTER_PVTVF0_AMBER_IRQ_MASK     (0x40000U)
#define SYSCON_STARTER_PVTVF0_AMBER_IRQ_SHIFT    (18U)
/*! PVTVF0_AMBER_IRQ - PVTVF0 amber interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_PVTVF0_AMBER_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PVTVF0_AMBER_IRQ_SHIFT)) & SYSCON_STARTER_PVTVF0_AMBER_IRQ_MASK)

#define SYSCON_STARTER_SEC_GPIO_INT00_MASK       (0x40000U)
#define SYSCON_STARTER_SEC_GPIO_INT00_SHIFT      (18U)
/*! SEC_GPIO_INT00 - SEC_GPIO_INT00 interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_SEC_GPIO_INT00(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SEC_GPIO_INT00_SHIFT)) & SYSCON_STARTER_SEC_GPIO_INT00_MASK)

#define SYSCON_STARTER_FLEXINT5_MASK             (0x80000U)
#define SYSCON_STARTER_FLEXINT5_SHIFT            (19U)
/*! FLEXINT5 - FLEXINT5 interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_FLEXINT5(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT5_SHIFT)) & SYSCON_STARTER_FLEXINT5_MASK)

#define SYSCON_STARTER_FLEXPWM0_COMPARE0_IRQ_MASK (0x80000U)
#define SYSCON_STARTER_FLEXPWM0_COMPARE0_IRQ_SHIFT (19U)
/*! FLEXPWM0_COMPARE0_IRQ - FlexPWM0 compare interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_FLEXPWM0_COMPARE0_IRQ(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM0_COMPARE0_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM0_COMPARE0_IRQ_MASK)

#define SYSCON_STARTER_PVTVF0_RED_IRQ_MASK       (0x80000U)
#define SYSCON_STARTER_PVTVF0_RED_IRQ_SHIFT      (19U)
/*! PVTVF0_RED_IRQ - PVTVF0 red interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_PVTVF0_RED_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PVTVF0_RED_IRQ_SHIFT)) & SYSCON_STARTER_PVTVF0_RED_IRQ_MASK)

#define SYSCON_STARTER_SEC_GPIO_INT01_MASK       (0x80000U)
#define SYSCON_STARTER_SEC_GPIO_INT01_SHIFT      (19U)
/*! SEC_GPIO_INT01 - SEC_GPIO_INT01 interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_SEC_GPIO_INT01(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SEC_GPIO_INT01_SHIFT)) & SYSCON_STARTER_SEC_GPIO_INT01_MASK)

#define SYSCON_STARTER_FLEXINT6_MASK             (0x100000U)
#define SYSCON_STARTER_FLEXINT6_SHIFT            (20U)
/*! FLEXINT6 - FLEXINT6 interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_FLEXINT6(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT6_SHIFT)) & SYSCON_STARTER_FLEXINT6_MASK)

#define SYSCON_STARTER_FLEXPWM0_RELOAD0_IRQ_MASK (0x100000U)
#define SYSCON_STARTER_FLEXPWM0_RELOAD0_IRQ_SHIFT (20U)
/*! FLEXPWM0_RELOAD0_IRQ - FlexPWM0 reload interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_FLEXPWM0_RELOAD0_IRQ(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM0_RELOAD0_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM0_RELOAD0_IRQ_MASK)

#define SYSCON_STARTER_FREQ_ME_PLUS_MASK         (0x100000U)
#define SYSCON_STARTER_FREQ_ME_PLUS_SHIFT        (20U)
/*! FREQ_ME_PLUS - FREQME interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_FREQ_ME_PLUS(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FREQ_ME_PLUS_SHIFT)) & SYSCON_STARTER_FREQ_ME_PLUS_MASK)

#define SYSCON_STARTER_PVTVF1_AMBER_IRQ_MASK     (0x100000U)
#define SYSCON_STARTER_PVTVF1_AMBER_IRQ_SHIFT    (20U)
/*! PVTVF1_AMBER_IRQ - PVTVF1 amber interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_PVTVF1_AMBER_IRQ(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PVTVF1_AMBER_IRQ_SHIFT)) & SYSCON_STARTER_PVTVF1_AMBER_IRQ_MASK)

#define SYSCON_STARTER_FLEXINT7_MASK             (0x200000U)
#define SYSCON_STARTER_FLEXINT7_SHIFT            (21U)
/*! FLEXINT7 - FLEXINT7 interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_FLEXINT7(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT7_SHIFT)) & SYSCON_STARTER_FLEXINT7_MASK)

#define SYSCON_STARTER_FLEXPWM0_COMPARE1_IRQ_MASK (0x200000U)
#define SYSCON_STARTER_FLEXPWM0_COMPARE1_IRQ_SHIFT (21U)
/*! FLEXPWM0_COMPARE1_IRQ - FlexPWM0 compare interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_FLEXPWM0_COMPARE1_IRQ(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM0_COMPARE1_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM0_COMPARE1_IRQ_MASK)

#define SYSCON_STARTER_PVTVF1_RED_IRQ_MASK       (0x200000U)
#define SYSCON_STARTER_PVTVF1_RED_IRQ_SHIFT      (21U)
/*! PVTVF1_RED_IRQ - PVTVF1 red interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_PVTVF1_RED_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PVTVF1_RED_IRQ_SHIFT)) & SYSCON_STARTER_PVTVF1_RED_IRQ_MASK)

#define SYSCON_STARTER_SEC_VIO_MASK              (0x200000U)
#define SYSCON_STARTER_SEC_VIO_SHIFT             (21U)
/*! SEC_VIO - SEC_VIO interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_SEC_VIO(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SEC_VIO_SHIFT)) & SYSCON_STARTER_SEC_VIO_MASK)

#define SYSCON_STARTER_ADC0_MASK                 (0x400000U)
#define SYSCON_STARTER_ADC0_SHIFT                (22U)
/*! ADC0 - ADC0 interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_ADC0(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ADC0_SHIFT)) & SYSCON_STARTER_ADC0_MASK)

#define SYSCON_STARTER_FLEXPWM0_RELOAD1_IRQ_MASK (0x400000U)
#define SYSCON_STARTER_FLEXPWM0_RELOAD1_IRQ_SHIFT (22U)
/*! FLEXPWM0_RELOAD1_IRQ - FlexPWM0 reload interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_FLEXPWM0_RELOAD1_IRQ(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM0_RELOAD1_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM0_RELOAD1_IRQ_MASK)

#define SYSCON_STARTER_SHA_MASK                  (0x400000U)
#define SYSCON_STARTER_SHA_SHIFT                 (22U)
/*! SHA - SHA interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_SHA(x)                    (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SHA_SHIFT)) & SYSCON_STARTER_SHA_MASK)

#define SYSCON_STARTER_ADC1_MASK                 (0x800000U)
#define SYSCON_STARTER_ADC1_SHIFT                (23U)
/*! ADC1 - ADC1 interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_ADC1(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ADC1_SHIFT)) & SYSCON_STARTER_ADC1_MASK)

#define SYSCON_STARTER_FLEXPWM0_COMPARE2_IRQ_MASK (0x800000U)
#define SYSCON_STARTER_FLEXPWM0_COMPARE2_IRQ_SHIFT (23U)
/*! FLEXPWM0_COMPARE2_IRQ - FlexPWM0 compare interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_FLEXPWM0_COMPARE2_IRQ(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM0_COMPARE2_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM0_COMPARE2_IRQ_MASK)

#define SYSCON_STARTER_PKC_MASK                  (0x800000U)
#define SYSCON_STARTER_PKC_SHIFT                 (23U)
/*! PKC - PKC interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_PKC(x)                    (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PKC_SHIFT)) & SYSCON_STARTER_PKC_MASK)

#define SYSCON_STARTER_ACMP_OVR_MASK             (0x1000000U)
#define SYSCON_STARTER_ACMP_OVR_SHIFT            (24U)
/*! ACMP_OVR - ACMP_OVR interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_ACMP_OVR(x)               (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ACMP_OVR_SHIFT)) & SYSCON_STARTER_ACMP_OVR_MASK)

#define SYSCON_STARTER_FLEXPWM0_RELOAD2_IRQ_MASK (0x1000000U)
#define SYSCON_STARTER_FLEXPWM0_RELOAD2_IRQ_SHIFT (24U)
/*! FLEXPWM0_RELOAD2_IRQ - FlexPWM0 reload interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_FLEXPWM0_RELOAD2_IRQ(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM0_RELOAD2_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM0_RELOAD2_IRQ_MASK)

#define SYSCON_STARTER_QDDKEY_MASK               (0x1000000U)
#define SYSCON_STARTER_QDDKEY_SHIFT              (24U)
/*! QDDKEY - QDDKEY interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_QDDKEY(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_QDDKEY_SHIFT)) & SYSCON_STARTER_QDDKEY_MASK)

#define SYSCON_STARTER_DMIC_MASK                 (0x2000000U)
#define SYSCON_STARTER_DMIC_SHIFT                (25U)
/*! DMIC - DMIC interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_DMIC(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_DMIC_SHIFT)) & SYSCON_STARTER_DMIC_MASK)

#define SYSCON_STARTER_FLEXPWM0_COMPARE3_IRQ_MASK (0x2000000U)
#define SYSCON_STARTER_FLEXPWM0_COMPARE3_IRQ_SHIFT (25U)
/*! FLEXPWM0_COMPARE3_IRQ - FlexPWM0 compare interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_FLEXPWM0_COMPARE3_IRQ(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM0_COMPARE3_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM0_COMPARE3_IRQ_MASK)

#define SYSCON_STARTER_PQ_MASK                   (0x2000000U)
#define SYSCON_STARTER_PQ_SHIFT                  (25U)
/*! PQ - PQ interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_PQ(x)                     (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PQ_SHIFT)) & SYSCON_STARTER_PQ_MASK)

#define SYSCON_STARTER_FLEXPWM0_RELOAD3_IRQ_MASK (0x4000000U)
#define SYSCON_STARTER_FLEXPWM0_RELOAD3_IRQ_SHIFT (26U)
/*! FLEXPWM0_RELOAD3_IRQ - FlexPWM0 reload interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_FLEXPWM0_RELOAD3_IRQ(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM0_RELOAD3_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM0_RELOAD3_IRQ_MASK)

#define SYSCON_STARTER_SDMA1_MASK                (0x4000000U)
#define SYSCON_STARTER_SDMA1_SHIFT               (26U)
/*! SDMA1 - SDMA1 interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_SDMA1(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SDMA1_SHIFT)) & SYSCON_STARTER_SDMA1_MASK)

#define SYSCON_STARTER_FLEXPWM1_CAPTURE_IRQ_MASK (0x8000000U)
#define SYSCON_STARTER_FLEXPWM1_CAPTURE_IRQ_SHIFT (27U)
/*! FLEXPWM1_CAPTURE_IRQ - FlexPWM1 capture interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_FLEXPWM1_CAPTURE_IRQ(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM1_CAPTURE_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM1_CAPTURE_IRQ_MASK)

#define SYSCON_STARTER_SPI_HS_MASK               (0x8000000U)
#define SYSCON_STARTER_SPI_HS_SHIFT              (27U)
/*! SPI_HS - SPI_HS interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_SPI_HS(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SPI_HS_SHIFT)) & SYSCON_STARTER_SPI_HS_MASK)

#define SYSCON_STARTER_USB0_NEEDCLK_MASK         (0x8000000U)
#define SYSCON_STARTER_USB0_NEEDCLK_SHIFT        (27U)
/*! USB0_NEEDCLK - USB0_NEEDCLK interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_USB0_NEEDCLK(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB0_NEEDCLK_SHIFT)) & SYSCON_STARTER_USB0_NEEDCLK_MASK)

#define SYSCON_STARTER_CODE_WDG0_MASK            (0x10000000U)
#define SYSCON_STARTER_CODE_WDG0_SHIFT           (28U)
/*! CODE_WDG0 - CODE WDG0 interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_CODE_WDG0(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CODE_WDG0_SHIFT)) & SYSCON_STARTER_CODE_WDG0_MASK)

#define SYSCON_STARTER_FLEXPWM1_FAULT_IRQ_MASK   (0x10000000U)
#define SYSCON_STARTER_FLEXPWM1_FAULT_IRQ_SHIFT  (28U)
/*! FLEXPWM1_FAULT_IRQ - FlexPWM1 fault interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_FLEXPWM1_FAULT_IRQ(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM1_FAULT_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM1_FAULT_IRQ_MASK)

#define SYSCON_STARTER_USB0_MASK                 (0x10000000U)
#define SYSCON_STARTER_USB0_SHIFT                (28U)
/*! USB0 - USB0-FS interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_USB0(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB0_SHIFT)) & SYSCON_STARTER_USB0_MASK)

#define SYSCON_STARTER_FLEXPWM1_RELOAD_ERR_IRQ_MASK (0x20000000U)
#define SYSCON_STARTER_FLEXPWM1_RELOAD_ERR_IRQ_SHIFT (29U)
/*! FLEXPWM1_RELOAD_ERR_IRQ - FlexPWM1 reload error interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_FLEXPWM1_RELOAD_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM1_RELOAD_ERR_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM1_RELOAD_ERR_IRQ_MASK)

#define SYSCON_STARTER_RTC_LITE0_MASK            (0x20000000U)
#define SYSCON_STARTER_RTC_LITE0_SHIFT           (29U)
/*! RTC_LITE0 - RTC_LITE0 interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_RTC_LITE0(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_RTC_LITE0_SHIFT)) & SYSCON_STARTER_RTC_LITE0_MASK)

#define SYSCON_STARTER_EZH_ARCH_B0_MASK          (0x40000000U)
#define SYSCON_STARTER_EZH_ARCH_B0_SHIFT         (30U)
/*! EZH_ARCH_B0 - EZH_ARCH_B0 interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_EZH_ARCH_B0(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_EZH_ARCH_B0_SHIFT)) & SYSCON_STARTER_EZH_ARCH_B0_MASK)

#define SYSCON_STARTER_FLEXPWM1_COMPARE0_IRQ_MASK (0x40000000U)
#define SYSCON_STARTER_FLEXPWM1_COMPARE0_IRQ_SHIFT (30U)
/*! FLEXPWM1_COMPARE0_IRQ - FlexPWM1 compare interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_FLEXPWM1_COMPARE0_IRQ(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM1_COMPARE0_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM1_COMPARE0_IRQ_MASK)

#define SYSCON_STARTER_I3C0_MASK                 (0x40000000U)
#define SYSCON_STARTER_I3C0_SHIFT                (30U)
/*! I3C0 - I3C0 interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_I3C0(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_I3C0_SHIFT)) & SYSCON_STARTER_I3C0_MASK)

#define SYSCON_STARTER_FLEXPWM1_RELOAD0_IRQ_MASK (0x80000000U)
#define SYSCON_STARTER_FLEXPWM1_RELOAD0_IRQ_SHIFT (31U)
/*! FLEXPWM1_RELOAD0_IRQ - FlexPWM1 reload interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_FLEXPWM1_RELOAD0_IRQ(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXPWM1_RELOAD0_IRQ_SHIFT)) & SYSCON_STARTER_FLEXPWM1_RELOAD0_IRQ_MASK)

#define SYSCON_STARTER_WAKEUP_MAILBOX0_MASK      (0x80000000U)
#define SYSCON_STARTER_WAKEUP_MAILBOX0_SHIFT     (31U)
/*! WAKEUP_MAILBOX0 - WAKEUP_MAILBOX0 interrupt wake-up.
 *  0b0..Wake-up disabled.
 *  0b1..Wake-up enabled.
 */
#define SYSCON_STARTER_WAKEUP_MAILBOX0(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_WAKEUP_MAILBOX0_SHIFT)) & SYSCON_STARTER_WAKEUP_MAILBOX0_MASK)
/*! @} */

/* The count of SYSCON_STARTER */
#define SYSCON_STARTER_COUNT                     (4U)

/*! @name STARTERSET - Set bits in STARTER */
/*! @{ */

#define SYSCON_STARTERSET_FLEXPWM1_COMPARE1_SET_MASK (0x1U)
#define SYSCON_STARTERSET_FLEXPWM1_COMPARE1_SET_SHIFT (0U)
/*! FLEXPWM1_COMPARE1_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register.
 */
#define SYSCON_STARTERSET_FLEXPWM1_COMPARE1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM1_COMPARE1_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM1_COMPARE1_SET_MASK)

#define SYSCON_STARTERSET_GPIO_INT04_SET_MASK    (0x1U)
#define SYSCON_STARTERSET_GPIO_INT04_SET_SHIFT   (0U)
/*! GPIO_INT04_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register.
 */
#define SYSCON_STARTERSET_GPIO_INT04_SET(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT04_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT04_SET_MASK)

#define SYSCON_STARTERSET_SYS_SET_MASK           (0x1U)
#define SYSCON_STARTERSET_SYS_SET_SHIFT          (0U)
/*! SYS_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERSET_SYS_SET(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SYS_SET_SHIFT)) & SYSCON_STARTERSET_SYS_SET_MASK)

#define SYSCON_STARTERSET_CSS_SET_MASK           (0x2U)
#define SYSCON_STARTERSET_CSS_SET_SHIFT          (1U)
/*! CSS_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register.
 */
#define SYSCON_STARTERSET_CSS_SET(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CSS_SET_SHIFT)) & SYSCON_STARTERSET_CSS_SET_MASK)

#define SYSCON_STARTERSET_FLEXPWM1_RELOAD1_SET_MASK (0x2U)
#define SYSCON_STARTERSET_FLEXPWM1_RELOAD1_SET_SHIFT (1U)
/*! FLEXPWM1_RELOAD1_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register.
 */
#define SYSCON_STARTERSET_FLEXPWM1_RELOAD1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM1_RELOAD1_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM1_RELOAD1_SET_MASK)

#define SYSCON_STARTERSET_GPIO_INT05_SET_MASK    (0x2U)
#define SYSCON_STARTERSET_GPIO_INT05_SET_SHIFT   (1U)
/*! GPIO_INT05_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register.
 */
#define SYSCON_STARTERSET_GPIO_INT05_SET(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT05_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT05_SET_MASK)

#define SYSCON_STARTERSET_SDMA0_SET_MASK         (0x2U)
#define SYSCON_STARTERSET_SDMA0_SET_SHIFT        (1U)
/*! SDMA0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERSET_SDMA0_SET(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SDMA0_SET_SHIFT)) & SYSCON_STARTERSET_SDMA0_SET_MASK)

#define SYSCON_STARTERSET_FLEXPWM1_COMPARE2_SET_MASK (0x4U)
#define SYSCON_STARTERSET_FLEXPWM1_COMPARE2_SET_SHIFT (2U)
/*! FLEXPWM1_COMPARE2_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register.
 */
#define SYSCON_STARTERSET_FLEXPWM1_COMPARE2_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM1_COMPARE2_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM1_COMPARE2_SET_MASK)

#define SYSCON_STARTERSET_GPIO_GLOBALINT0_SET_MASK (0x4U)
#define SYSCON_STARTERSET_GPIO_GLOBALINT0_SET_SHIFT (2U)
/*! GPIO_GLOBALINT0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERSET_GPIO_GLOBALINT0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_GLOBALINT0_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_GLOBALINT0_SET_MASK)

#define SYSCON_STARTERSET_GPIO_INT06_SET_MASK    (0x4U)
#define SYSCON_STARTERSET_GPIO_INT06_SET_SHIFT   (2U)
/*! GPIO_INT06_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register.
 */
#define SYSCON_STARTERSET_GPIO_INT06_SET(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT06_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT06_SET_MASK)

#define SYSCON_STARTERSET_TAMPER_SET_MASK        (0x4U)
#define SYSCON_STARTERSET_TAMPER_SET_SHIFT       (2U)
/*! TAMPER_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register.
 */
#define SYSCON_STARTERSET_TAMPER_SET(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_TAMPER_SET_SHIFT)) & SYSCON_STARTERSET_TAMPER_SET_MASK)

#define SYSCON_STARTERSET_FLEXPWM1_RELOAD2_SET_MASK (0x8U)
#define SYSCON_STARTERSET_FLEXPWM1_RELOAD2_SET_SHIFT (3U)
/*! FLEXPWM1_RELOAD2_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register.
 */
#define SYSCON_STARTERSET_FLEXPWM1_RELOAD2_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM1_RELOAD2_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM1_RELOAD2_SET_MASK)

#define SYSCON_STARTERSET_GPIO_GLOBALINT1_SET_MASK (0x8U)
#define SYSCON_STARTERSET_GPIO_GLOBALINT1_SET_SHIFT (3U)
/*! GPIO_GLOBALINT1_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERSET_GPIO_GLOBALINT1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_GLOBALINT1_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_GLOBALINT1_SET_MASK)

#define SYSCON_STARTERSET_GPIO_INT07_SET_MASK    (0x8U)
#define SYSCON_STARTERSET_GPIO_INT07_SET_SHIFT   (3U)
/*! GPIO_INT07_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register.
 */
#define SYSCON_STARTERSET_GPIO_INT07_SET(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT07_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT07_SET_MASK)

#define SYSCON_STARTERSET_CTIMER2_SET_MASK       (0x10U)
#define SYSCON_STARTERSET_CTIMER2_SET_SHIFT      (4U)
/*! CTIMER2_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register.
 */
#define SYSCON_STARTERSET_CTIMER2_SET(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER2_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER2_SET_MASK)

#define SYSCON_STARTERSET_FLEXPWM1_COMPARE3_SET_MASK (0x10U)
#define SYSCON_STARTERSET_FLEXPWM1_COMPARE3_SET_SHIFT (4U)
/*! FLEXPWM1_COMPARE3_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register.
 */
#define SYSCON_STARTERSET_FLEXPWM1_COMPARE3_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM1_COMPARE3_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM1_COMPARE3_SET_MASK)

#define SYSCON_STARTERSET_GPIO_INT00_SET_MASK    (0x10U)
#define SYSCON_STARTERSET_GPIO_INT00_SET_SHIFT   (4U)
/*! GPIO_INT00_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERSET_GPIO_INT00_SET(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT00_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT00_SET_MASK)

#define SYSCON_STARTERSET_CTIMER4_SET_MASK       (0x20U)
#define SYSCON_STARTERSET_CTIMER4_SET_SHIFT      (5U)
/*! CTIMER4_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register.
 */
#define SYSCON_STARTERSET_CTIMER4_SET(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER4_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER4_SET_MASK)

#define SYSCON_STARTERSET_FLEXPWM1_RELOAD3_SET_MASK (0x20U)
#define SYSCON_STARTERSET_FLEXPWM1_RELOAD3_SET_SHIFT (5U)
/*! FLEXPWM1_RELOAD3_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register.
 */
#define SYSCON_STARTERSET_FLEXPWM1_RELOAD3_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM1_RELOAD3_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM1_RELOAD3_SET_MASK)

#define SYSCON_STARTERSET_GPIO_INT01_SET_MASK    (0x20U)
#define SYSCON_STARTERSET_GPIO_INT01_SET_SHIFT   (5U)
/*! GPIO_INT01_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERSET_GPIO_INT01_SET(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT01_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT01_SET_MASK)

#define SYSCON_STARTERSET_ENC0_COMPARE_SET_MASK  (0x40U)
#define SYSCON_STARTERSET_ENC0_COMPARE_SET_SHIFT (6U)
/*! ENC0_COMPARE_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register.
 */
#define SYSCON_STARTERSET_ENC0_COMPARE_SET(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_ENC0_COMPARE_SET_SHIFT)) & SYSCON_STARTERSET_ENC0_COMPARE_SET_MASK)

#define SYSCON_STARTERSET_GPIO_INT02_SET_MASK    (0x40U)
#define SYSCON_STARTERSET_GPIO_INT02_SET_SHIFT   (6U)
/*! GPIO_INT02_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERSET_GPIO_INT02_SET(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT02_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT02_SET_MASK)

#define SYSCON_STARTERSET_OS_EVENT_SET_MASK      (0x40U)
#define SYSCON_STARTERSET_OS_EVENT_SET_SHIFT     (6U)
/*! OS_EVENT_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register.
 */
#define SYSCON_STARTERSET_OS_EVENT_SET(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_OS_EVENT_SET_SHIFT)) & SYSCON_STARTERSET_OS_EVENT_SET_MASK)

#define SYSCON_STARTERSET_ENC0_HOME_SET_MASK     (0x80U)
#define SYSCON_STARTERSET_ENC0_HOME_SET_SHIFT    (7U)
/*! ENC0_HOME_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register.
 */
#define SYSCON_STARTERSET_ENC0_HOME_SET(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_ENC0_HOME_SET_SHIFT)) & SYSCON_STARTERSET_ENC0_HOME_SET_MASK)

#define SYSCON_STARTERSET_GPIO_INT03_SET_MASK    (0x80U)
#define SYSCON_STARTERSET_GPIO_INT03_SET_SHIFT   (7U)
/*! GPIO_INT03_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERSET_GPIO_INT03_SET(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT03_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT03_SET_MASK)

#define SYSCON_STARTERSET_ENC0_WDG_SET_MASK      (0x100U)
#define SYSCON_STARTERSET_ENC0_WDG_SET_SHIFT     (8U)
/*! ENC0_WDG_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register.
 */
#define SYSCON_STARTERSET_ENC0_WDG_SET(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_ENC0_WDG_SET_SHIFT)) & SYSCON_STARTERSET_ENC0_WDG_SET_MASK)

#define SYSCON_STARTERSET_UTICK0_SET_MASK        (0x100U)
#define SYSCON_STARTERSET_UTICK0_SET_SHIFT       (8U)
/*! UTICK0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERSET_UTICK0_SET(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_UTICK0_SET_SHIFT)) & SYSCON_STARTERSET_UTICK0_SET_MASK)

#define SYSCON_STARTERSET_ENC0_IDX_SET_MASK      (0x200U)
#define SYSCON_STARTERSET_ENC0_IDX_SET_SHIFT     (9U)
/*! ENC0_IDX_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register.
 */
#define SYSCON_STARTERSET_ENC0_IDX_SET(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_ENC0_IDX_SET_SHIFT)) & SYSCON_STARTERSET_ENC0_IDX_SET_MASK)

#define SYSCON_STARTERSET_MRT0_SET_MASK          (0x200U)
#define SYSCON_STARTERSET_MRT0_SET_SHIFT         (9U)
/*! MRT0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERSET_MRT0_SET(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_MRT0_SET_SHIFT)) & SYSCON_STARTERSET_MRT0_SET_MASK)

#define SYSCON_STARTERSET_CTIMER0_SET_MASK       (0x400U)
#define SYSCON_STARTERSET_CTIMER0_SET_SHIFT      (10U)
/*! CTIMER0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERSET_CTIMER0_SET(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER0_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER0_SET_MASK)

#define SYSCON_STARTERSET_DAC0_SET_MASK          (0x400U)
#define SYSCON_STARTERSET_DAC0_SET_SHIFT         (10U)
/*! DAC0_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register.
 */
#define SYSCON_STARTERSET_DAC0_SET(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_DAC0_SET_SHIFT)) & SYSCON_STARTERSET_DAC0_SET_MASK)

#define SYSCON_STARTERSET_ENC1_COMPARE_SET_MASK  (0x400U)
#define SYSCON_STARTERSET_ENC1_COMPARE_SET_SHIFT (10U)
/*! ENC1_COMPARE_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register.
 */
#define SYSCON_STARTERSET_ENC1_COMPARE_SET(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_ENC1_COMPARE_SET_SHIFT)) & SYSCON_STARTERSET_ENC1_COMPARE_SET_MASK)

#define SYSCON_STARTERSET_CTIMER1_SET_MASK       (0x800U)
#define SYSCON_STARTERSET_CTIMER1_SET_SHIFT      (11U)
/*! CTIMER1_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERSET_CTIMER1_SET(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER1_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER1_SET_MASK)

#define SYSCON_STARTERSET_DAC1_SET_MASK          (0x800U)
#define SYSCON_STARTERSET_DAC1_SET_SHIFT         (11U)
/*! DAC1_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register.
 */
#define SYSCON_STARTERSET_DAC1_SET(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_DAC1_SET_SHIFT)) & SYSCON_STARTERSET_DAC1_SET_MASK)

#define SYSCON_STARTERSET_ENC1_HOME_SET_MASK     (0x800U)
#define SYSCON_STARTERSET_ENC1_HOME_SET_SHIFT    (11U)
/*! ENC1_HOME_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register.
 */
#define SYSCON_STARTERSET_ENC1_HOME_SET(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_ENC1_HOME_SET_SHIFT)) & SYSCON_STARTERSET_ENC1_HOME_SET_MASK)

#define SYSCON_STARTERSET_DAC2_SET_MASK          (0x1000U)
#define SYSCON_STARTERSET_DAC2_SET_SHIFT         (12U)
/*! DAC2_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register.
 */
#define SYSCON_STARTERSET_DAC2_SET(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_DAC2_SET_SHIFT)) & SYSCON_STARTERSET_DAC2_SET_MASK)

#define SYSCON_STARTERSET_ENC1_WDG_SET_MASK      (0x1000U)
#define SYSCON_STARTERSET_ENC1_WDG_SET_SHIFT     (12U)
/*! ENC1_WDG_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register.
 */
#define SYSCON_STARTERSET_ENC1_WDG_SET(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_ENC1_WDG_SET_SHIFT)) & SYSCON_STARTERSET_ENC1_WDG_SET_MASK)

#define SYSCON_STARTERSET_SCT0_SET_MASK          (0x1000U)
#define SYSCON_STARTERSET_SCT0_SET_SHIFT         (12U)
/*! SCT0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERSET_SCT0_SET(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SCT0_SET_SHIFT)) & SYSCON_STARTERSET_SCT0_SET_MASK)

#define SYSCON_STARTERSET_CTIMER3_SET_MASK       (0x2000U)
#define SYSCON_STARTERSET_CTIMER3_SET_SHIFT      (13U)
/*! CTIMER3_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERSET_CTIMER3_SET(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER3_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER3_SET_MASK)

#define SYSCON_STARTERSET_ENC1_IDX_SET_MASK      (0x2000U)
#define SYSCON_STARTERSET_ENC1_IDX_SET_SHIFT     (13U)
/*! ENC1_IDX_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register.
 */
#define SYSCON_STARTERSET_ENC1_IDX_SET(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_ENC1_IDX_SET_SHIFT)) & SYSCON_STARTERSET_ENC1_IDX_SET_MASK)

#define SYSCON_STARTERSET_HS_CMP0_SET_MASK       (0x2000U)
#define SYSCON_STARTERSET_HS_CMP0_SET_SHIFT      (13U)
/*! HS_CMP0_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register.
 */
#define SYSCON_STARTERSET_HS_CMP0_SET(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_HS_CMP0_SET_SHIFT)) & SYSCON_STARTERSET_HS_CMP0_SET_MASK)

#define SYSCON_STARTERSET_FLEXINT0_SET_MASK      (0x4000U)
#define SYSCON_STARTERSET_FLEXINT0_SET_SHIFT     (14U)
/*! FLEXINT0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERSET_FLEXINT0_SET(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT0_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT0_SET_MASK)

#define SYSCON_STARTERSET_HS_CMP1_SET_MASK       (0x4000U)
#define SYSCON_STARTERSET_HS_CMP1_SET_SHIFT      (14U)
/*! HS_CMP1_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register.
 */
#define SYSCON_STARTERSET_HS_CMP1_SET(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_HS_CMP1_SET_SHIFT)) & SYSCON_STARTERSET_HS_CMP1_SET_MASK)

#define SYSCON_STARTERSET_ITRC_SET_MASK          (0x4000U)
#define SYSCON_STARTERSET_ITRC_SET_SHIFT         (14U)
/*! ITRC_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register.
 */
#define SYSCON_STARTERSET_ITRC_SET(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_ITRC_SET_SHIFT)) & SYSCON_STARTERSET_ITRC_SET_MASK)

#define SYSCON_STARTERSET_FLEXINT1_SET_MASK      (0x8000U)
#define SYSCON_STARTERSET_FLEXINT1_SET_SHIFT     (15U)
/*! FLEXINT1_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERSET_FLEXINT1_SET(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT1_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT1_SET_MASK)

#define SYSCON_STARTERSET_HS_CMP2_SET_MASK       (0x8000U)
#define SYSCON_STARTERSET_HS_CMP2_SET_SHIFT      (15U)
/*! HS_CMP2_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register.
 */
#define SYSCON_STARTERSET_HS_CMP2_SET(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_HS_CMP2_SET_SHIFT)) & SYSCON_STARTERSET_HS_CMP2_SET_MASK)

#define SYSCON_STARTERSET_CSSV2_ERR_SET_MASK     (0x10000U)
#define SYSCON_STARTERSET_CSSV2_ERR_SET_SHIFT    (16U)
/*! CSSV2_ERR_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register.
 */
#define SYSCON_STARTERSET_CSSV2_ERR_SET(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CSSV2_ERR_SET_SHIFT)) & SYSCON_STARTERSET_CSSV2_ERR_SET_MASK)

#define SYSCON_STARTERSET_FLEXINT2_SET_MASK      (0x10000U)
#define SYSCON_STARTERSET_FLEXINT2_SET_SHIFT     (16U)
/*! FLEXINT2_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERSET_FLEXINT2_SET(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT2_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT2_SET_MASK)

#define SYSCON_STARTERSET_FLEXPWM0_CAPTURE_SET_MASK (0x10000U)
#define SYSCON_STARTERSET_FLEXPWM0_CAPTURE_SET_SHIFT (16U)
/*! FLEXPWM0_CAPTURE_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register.
 */
#define SYSCON_STARTERSET_FLEXPWM0_CAPTURE_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM0_CAPTURE_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM0_CAPTURE_SET_MASK)

#define SYSCON_STARTERSET_FLEXINT3_SET_MASK      (0x20000U)
#define SYSCON_STARTERSET_FLEXINT3_SET_SHIFT     (17U)
/*! FLEXINT3_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERSET_FLEXINT3_SET(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT3_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT3_SET_MASK)

#define SYSCON_STARTERSET_FLEXPWM0_FAULT_SET_MASK (0x20000U)
#define SYSCON_STARTERSET_FLEXPWM0_FAULT_SET_SHIFT (17U)
/*! FLEXPWM0_FAULT_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register.
 */
#define SYSCON_STARTERSET_FLEXPWM0_FAULT_SET(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM0_FAULT_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM0_FAULT_SET_MASK)

#define SYSCON_STARTERSET_PKC_ERR_SET_MASK       (0x20000U)
#define SYSCON_STARTERSET_PKC_ERR_SET_SHIFT      (17U)
/*! PKC_ERR_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register.
 */
#define SYSCON_STARTERSET_PKC_ERR_SET(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_PKC_ERR_SET_SHIFT)) & SYSCON_STARTERSET_PKC_ERR_SET_MASK)

#define SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET_MASK (0x20000U)
#define SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET_SHIFT (17U)
/*! SEC_HYPERVISOR_CALL_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register.
 */
#define SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET_SHIFT)) & SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET_MASK)

#define SYSCON_STARTERSET_FLEXINT4_SET_MASK      (0x40000U)
#define SYSCON_STARTERSET_FLEXINT4_SET_SHIFT     (18U)
/*! FLEXINT4_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERSET_FLEXINT4_SET(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT4_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT4_SET_MASK)

#define SYSCON_STARTERSET_FLEXPWM0_RELOAD_ERROR_SET_MASK (0x40000U)
#define SYSCON_STARTERSET_FLEXPWM0_RELOAD_ERROR_SET_SHIFT (18U)
/*! FLEXPWM0_RELOAD_ERROR_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register.
 */
#define SYSCON_STARTERSET_FLEXPWM0_RELOAD_ERROR_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM0_RELOAD_ERROR_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM0_RELOAD_ERROR_SET_MASK)

#define SYSCON_STARTERSET_PVTVF0_AMBER_SET_MASK  (0x40000U)
#define SYSCON_STARTERSET_PVTVF0_AMBER_SET_SHIFT (18U)
/*! PVTVF0_AMBER_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register.
 */
#define SYSCON_STARTERSET_PVTVF0_AMBER_SET(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_PVTVF0_AMBER_SET_SHIFT)) & SYSCON_STARTERSET_PVTVF0_AMBER_SET_MASK)

#define SYSCON_STARTERSET_SEC_GPIO_INT00_SET_MASK (0x40000U)
#define SYSCON_STARTERSET_SEC_GPIO_INT00_SET_SHIFT (18U)
/*! SEC_GPIO_INT00_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register.
 */
#define SYSCON_STARTERSET_SEC_GPIO_INT00_SET(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SEC_GPIO_INT00_SET_SHIFT)) & SYSCON_STARTERSET_SEC_GPIO_INT00_SET_MASK)

#define SYSCON_STARTERSET_FLEXINT5_SET_MASK      (0x80000U)
#define SYSCON_STARTERSET_FLEXINT5_SET_SHIFT     (19U)
/*! FLEXINT5_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERSET_FLEXINT5_SET(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT5_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT5_SET_MASK)

#define SYSCON_STARTERSET_FLEXPWM0_COMPARE0_SET_MASK (0x80000U)
#define SYSCON_STARTERSET_FLEXPWM0_COMPARE0_SET_SHIFT (19U)
/*! FLEXPWM0_COMPARE0_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register.
 */
#define SYSCON_STARTERSET_FLEXPWM0_COMPARE0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM0_COMPARE0_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM0_COMPARE0_SET_MASK)

#define SYSCON_STARTERSET_PVTVF0_RED_SET_MASK    (0x80000U)
#define SYSCON_STARTERSET_PVTVF0_RED_SET_SHIFT   (19U)
/*! PVTVF0_RED_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register.
 */
#define SYSCON_STARTERSET_PVTVF0_RED_SET(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_PVTVF0_RED_SET_SHIFT)) & SYSCON_STARTERSET_PVTVF0_RED_SET_MASK)

#define SYSCON_STARTERSET_SEC_GPIO_INT01_SET_MASK (0x80000U)
#define SYSCON_STARTERSET_SEC_GPIO_INT01_SET_SHIFT (19U)
/*! SEC_GPIO_INT01_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register.
 */
#define SYSCON_STARTERSET_SEC_GPIO_INT01_SET(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SEC_GPIO_INT01_SET_SHIFT)) & SYSCON_STARTERSET_SEC_GPIO_INT01_SET_MASK)

#define SYSCON_STARTERSET_FLEXINT6_SET_MASK      (0x100000U)
#define SYSCON_STARTERSET_FLEXINT6_SET_SHIFT     (20U)
/*! FLEXINT6_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERSET_FLEXINT6_SET(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT6_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT6_SET_MASK)

#define SYSCON_STARTERSET_FLEXPWM0_RELOAD0_SET_MASK (0x100000U)
#define SYSCON_STARTERSET_FLEXPWM0_RELOAD0_SET_SHIFT (20U)
/*! FLEXPWM0_RELOAD0_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register.
 */
#define SYSCON_STARTERSET_FLEXPWM0_RELOAD0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM0_RELOAD0_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM0_RELOAD0_SET_MASK)

#define SYSCON_STARTERSET_PVTVF1_AMBER_SET_MASK  (0x100000U)
#define SYSCON_STARTERSET_PVTVF1_AMBER_SET_SHIFT (20U)
/*! PVTVF1_AMBER_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register.
 */
#define SYSCON_STARTERSET_PVTVF1_AMBER_SET(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_PVTVF1_AMBER_SET_SHIFT)) & SYSCON_STARTERSET_PVTVF1_AMBER_SET_MASK)

#define SYSCON_STARTERSET_FLEXINT7_SET_MASK      (0x200000U)
#define SYSCON_STARTERSET_FLEXINT7_SET_SHIFT     (21U)
/*! FLEXINT7_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERSET_FLEXINT7_SET(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT7_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT7_SET_MASK)

#define SYSCON_STARTERSET_FLEXPWM0_COMPARE1_SET_MASK (0x200000U)
#define SYSCON_STARTERSET_FLEXPWM0_COMPARE1_SET_SHIFT (21U)
/*! FLEXPWM0_COMPARE1_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register.
 */
#define SYSCON_STARTERSET_FLEXPWM0_COMPARE1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM0_COMPARE1_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM0_COMPARE1_SET_MASK)

#define SYSCON_STARTERSET_PVTVF1_RED_SET_MASK    (0x200000U)
#define SYSCON_STARTERSET_PVTVF1_RED_SET_SHIFT   (21U)
/*! PVTVF1_RED_SET - Writing ones to this register sets the corresponding bit in the STARTER3 register.
 */
#define SYSCON_STARTERSET_PVTVF1_RED_SET(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_PVTVF1_RED_SET_SHIFT)) & SYSCON_STARTERSET_PVTVF1_RED_SET_MASK)

#define SYSCON_STARTERSET_ADC0_SET_MASK          (0x400000U)
#define SYSCON_STARTERSET_ADC0_SET_SHIFT         (22U)
/*! ADC0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERSET_ADC0_SET(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_ADC0_SET_SHIFT)) & SYSCON_STARTERSET_ADC0_SET_MASK)

#define SYSCON_STARTERSET_FLEXPWM0_RELOAD1_SET_MASK (0x400000U)
#define SYSCON_STARTERSET_FLEXPWM0_RELOAD1_SET_SHIFT (22U)
/*! FLEXPWM0_RELOAD1_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register.
 */
#define SYSCON_STARTERSET_FLEXPWM0_RELOAD1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM0_RELOAD1_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM0_RELOAD1_SET_MASK)

#define SYSCON_STARTERSET_FLEXPWM0_COMPARE2_SET_MASK (0x800000U)
#define SYSCON_STARTERSET_FLEXPWM0_COMPARE2_SET_SHIFT (23U)
/*! FLEXPWM0_COMPARE2_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register.
 */
#define SYSCON_STARTERSET_FLEXPWM0_COMPARE2_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM0_COMPARE2_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM0_COMPARE2_SET_MASK)

#define SYSCON_STARTERSET_ADC0_THCMP_OVR_SET_MASK (0x1000000U)
#define SYSCON_STARTERSET_ADC0_THCMP_OVR_SET_SHIFT (24U)
/*! ADC0_THCMP_OVR_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERSET_ADC0_THCMP_OVR_SET(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_ADC0_THCMP_OVR_SET_SHIFT)) & SYSCON_STARTERSET_ADC0_THCMP_OVR_SET_MASK)

#define SYSCON_STARTERSET_FLEXPWM0_RELOAD2_SET_MASK (0x1000000U)
#define SYSCON_STARTERSET_FLEXPWM0_RELOAD2_SET_SHIFT (24U)
/*! FLEXPWM0_RELOAD2_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register.
 */
#define SYSCON_STARTERSET_FLEXPWM0_RELOAD2_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM0_RELOAD2_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM0_RELOAD2_SET_MASK)

#define SYSCON_STARTERSET_QDDKEY_SET_MASK        (0x1000000U)
#define SYSCON_STARTERSET_QDDKEY_SET_SHIFT       (24U)
/*! QDDKEY_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register.
 */
#define SYSCON_STARTERSET_QDDKEY_SET(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_QDDKEY_SET_SHIFT)) & SYSCON_STARTERSET_QDDKEY_SET_MASK)

#define SYSCON_STARTERSET_FLEXPWM0_COMPARE3_SET_MASK (0x2000000U)
#define SYSCON_STARTERSET_FLEXPWM0_COMPARE3_SET_SHIFT (25U)
/*! FLEXPWM0_COMPARE3_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register.
 */
#define SYSCON_STARTERSET_FLEXPWM0_COMPARE3_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM0_COMPARE3_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM0_COMPARE3_SET_MASK)

#define SYSCON_STARTERSET_PQ_SET_MASK            (0x2000000U)
#define SYSCON_STARTERSET_PQ_SET_SHIFT           (25U)
/*! PQ_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register.
 */
#define SYSCON_STARTERSET_PQ_SET(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_PQ_SET_SHIFT)) & SYSCON_STARTERSET_PQ_SET_MASK)

#define SYSCON_STARTERSET_FLEXPWM0_RELOAD3_SET_MASK (0x4000000U)
#define SYSCON_STARTERSET_FLEXPWM0_RELOAD3_SET_SHIFT (26U)
/*! FLEXPWM0_RELOAD3_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register.
 */
#define SYSCON_STARTERSET_FLEXPWM0_RELOAD3_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM0_RELOAD3_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM0_RELOAD3_SET_MASK)

#define SYSCON_STARTERSET_SDMA1_SET_MASK         (0x4000000U)
#define SYSCON_STARTERSET_SDMA1_SET_SHIFT        (26U)
/*! SDMA1_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register.
 */
#define SYSCON_STARTERSET_SDMA1_SET(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SDMA1_SET_SHIFT)) & SYSCON_STARTERSET_SDMA1_SET_MASK)

#define SYSCON_STARTERSET_FLEXPWM1_CAPTURE_SET_MASK (0x8000000U)
#define SYSCON_STARTERSET_FLEXPWM1_CAPTURE_SET_SHIFT (27U)
/*! FLEXPWM1_CAPTURE_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register.
 */
#define SYSCON_STARTERSET_FLEXPWM1_CAPTURE_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM1_CAPTURE_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM1_CAPTURE_SET_MASK)

#define SYSCON_STARTERSET_SPI_HS_SET_MASK        (0x8000000U)
#define SYSCON_STARTERSET_SPI_HS_SET_SHIFT       (27U)
/*! SPI_HS_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register.
 */
#define SYSCON_STARTERSET_SPI_HS_SET(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SPI_HS_SET_SHIFT)) & SYSCON_STARTERSET_SPI_HS_SET_MASK)

#define SYSCON_STARTERSET_USB0_NEEDCLK_SET_MASK  (0x8000000U)
#define SYSCON_STARTERSET_USB0_NEEDCLK_SET_SHIFT (27U)
/*! USB0_NEEDCLK_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERSET_USB0_NEEDCLK_SET(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_USB0_NEEDCLK_SET_SHIFT)) & SYSCON_STARTERSET_USB0_NEEDCLK_SET_MASK)

#define SYSCON_STARTERSET_FLEXPWM1_FAULT_SET_MASK (0x10000000U)
#define SYSCON_STARTERSET_FLEXPWM1_FAULT_SET_SHIFT (28U)
/*! FLEXPWM1_FAULT_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register.
 */
#define SYSCON_STARTERSET_FLEXPWM1_FAULT_SET(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM1_FAULT_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM1_FAULT_SET_MASK)

#define SYSCON_STARTERSET_USB0_SET_MASK          (0x10000000U)
#define SYSCON_STARTERSET_USB0_SET_SHIFT         (28U)
/*! USB0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERSET_USB0_SET(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_USB0_SET_SHIFT)) & SYSCON_STARTERSET_USB0_SET_MASK)

#define SYSCON_STARTERSET_FLEXPWM1_RELOAD_ERROR_SET_MASK (0x20000000U)
#define SYSCON_STARTERSET_FLEXPWM1_RELOAD_ERROR_SET_SHIFT (29U)
/*! FLEXPWM1_RELOAD_ERROR_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register.
 */
#define SYSCON_STARTERSET_FLEXPWM1_RELOAD_ERROR_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM1_RELOAD_ERROR_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM1_RELOAD_ERROR_SET_MASK)

#define SYSCON_STARTERSET_RTC_LITE0_SET_MASK     (0x20000000U)
#define SYSCON_STARTERSET_RTC_LITE0_SET_SHIFT    (29U)
/*! RTC_LITE0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERSET_RTC_LITE0_SET(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_RTC_LITE0_SET_SHIFT)) & SYSCON_STARTERSET_RTC_LITE0_SET_MASK)

#define SYSCON_STARTERSET_EZH_ARCH_B0_SET_MASK   (0x40000000U)
#define SYSCON_STARTERSET_EZH_ARCH_B0_SET_SHIFT  (30U)
/*! EZH_ARCH_B0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERSET_EZH_ARCH_B0_SET(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_EZH_ARCH_B0_SET_SHIFT)) & SYSCON_STARTERSET_EZH_ARCH_B0_SET_MASK)

#define SYSCON_STARTERSET_FLEXPWM1_COMPARE0_SET_MASK (0x40000000U)
#define SYSCON_STARTERSET_FLEXPWM1_COMPARE0_SET_SHIFT (30U)
/*! FLEXPWM1_COMPARE0_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register.
 */
#define SYSCON_STARTERSET_FLEXPWM1_COMPARE0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM1_COMPARE0_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM1_COMPARE0_SET_MASK)

#define SYSCON_STARTERSET_FLEXPWM1_RELOAD0_SET_MASK (0x80000000U)
#define SYSCON_STARTERSET_FLEXPWM1_RELOAD0_SET_SHIFT (31U)
/*! FLEXPWM1_RELOAD0_SET - Writing ones to this register sets the corresponding bit in the STARTER2 register.
 */
#define SYSCON_STARTERSET_FLEXPWM1_RELOAD0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXPWM1_RELOAD0_SET_SHIFT)) & SYSCON_STARTERSET_FLEXPWM1_RELOAD0_SET_MASK)

#define SYSCON_STARTERSET_WAKEUPPADS_SET_MASK    (0x80000000U)
#define SYSCON_STARTERSET_WAKEUPPADS_SET_SHIFT   (31U)
/*! WAKEUPPADS_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register.
 */
#define SYSCON_STARTERSET_WAKEUPPADS_SET(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_WAKEUPPADS_SET_SHIFT)) & SYSCON_STARTERSET_WAKEUPPADS_SET_MASK)

#define SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET_MASK (0x80000000U)
#define SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET_SHIFT (31U)
/*! WAKEUP_MAILBOX0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET_SHIFT)) & SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET_MASK)
/*! @} */

/* The count of SYSCON_STARTERSET */
#define SYSCON_STARTERSET_COUNT                  (4U)

/*! @name STARTERCLR - Clear bits in STARTER */
/*! @{ */

#define SYSCON_STARTERCLR_GPIO_INT04_CLR_MASK    (0x1U)
#define SYSCON_STARTERCLR_GPIO_INT04_CLR_SHIFT   (0U)
/*! GPIO_INT04_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register.
 */
#define SYSCON_STARTERCLR_GPIO_INT04_CLR(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT04_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT04_CLR_MASK)

#define SYSCON_STARTERCLR_SYS_CLR_MASK           (0x1U)
#define SYSCON_STARTERCLR_SYS_CLR_SHIFT          (0U)
/*! SYS_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERCLR_SYS_CLR(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SYS_CLR_SHIFT)) & SYSCON_STARTERCLR_SYS_CLR_MASK)

#define SYSCON_STARTERCLR_GPIO_INT05_CLR_MASK    (0x2U)
#define SYSCON_STARTERCLR_GPIO_INT05_CLR_SHIFT   (1U)
/*! GPIO_INT05_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register.
 */
#define SYSCON_STARTERCLR_GPIO_INT05_CLR(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT05_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT05_CLR_MASK)

#define SYSCON_STARTERCLR_SDMA0_CLR_MASK         (0x2U)
#define SYSCON_STARTERCLR_SDMA0_CLR_SHIFT        (1U)
/*! SDMA0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERCLR_SDMA0_CLR(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SDMA0_CLR_SHIFT)) & SYSCON_STARTERCLR_SDMA0_CLR_MASK)

#define SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR_MASK (0x4U)
#define SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR_SHIFT (2U)
/*! GPIO_GLOBALINT0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR_MASK)

#define SYSCON_STARTERCLR_GPIO_INT06_CLR_MASK    (0x4U)
#define SYSCON_STARTERCLR_GPIO_INT06_CLR_SHIFT   (2U)
/*! GPIO_INT06_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register.
 */
#define SYSCON_STARTERCLR_GPIO_INT06_CLR(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT06_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT06_CLR_MASK)

#define SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR_MASK (0x8U)
#define SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR_SHIFT (3U)
/*! GPIO_GLOBALINT1_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR_MASK)

#define SYSCON_STARTERCLR_GPIO_INT07_CLR_MASK    (0x8U)
#define SYSCON_STARTERCLR_GPIO_INT07_CLR_SHIFT   (3U)
/*! GPIO_INT07_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register.
 */
#define SYSCON_STARTERCLR_GPIO_INT07_CLR(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT07_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT07_CLR_MASK)

#define SYSCON_STARTERCLR_CTIMER2_CLR_MASK       (0x10U)
#define SYSCON_STARTERCLR_CTIMER2_CLR_SHIFT      (4U)
/*! CTIMER2_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register.
 */
#define SYSCON_STARTERCLR_CTIMER2_CLR(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER2_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER2_CLR_MASK)

#define SYSCON_STARTERCLR_GPIO_INT00_CLR_MASK    (0x10U)
#define SYSCON_STARTERCLR_GPIO_INT00_CLR_SHIFT   (4U)
/*! GPIO_INT00_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERCLR_GPIO_INT00_CLR(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT00_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT00_CLR_MASK)

#define SYSCON_STARTERCLR_CTIMER4_CLR_MASK       (0x20U)
#define SYSCON_STARTERCLR_CTIMER4_CLR_SHIFT      (5U)
/*! CTIMER4_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register.
 */
#define SYSCON_STARTERCLR_CTIMER4_CLR(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER4_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER4_CLR_MASK)

#define SYSCON_STARTERCLR_GPIO_INT01_CLR_MASK    (0x20U)
#define SYSCON_STARTERCLR_GPIO_INT01_CLR_SHIFT   (5U)
/*! GPIO_INT01_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERCLR_GPIO_INT01_CLR(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT01_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT01_CLR_MASK)

#define SYSCON_STARTERCLR_GPIO_INT02_CLR_MASK    (0x40U)
#define SYSCON_STARTERCLR_GPIO_INT02_CLR_SHIFT   (6U)
/*! GPIO_INT02_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERCLR_GPIO_INT02_CLR(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT02_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT02_CLR_MASK)

#define SYSCON_STARTERCLR_OS_EVENT_CLR_MASK      (0x40U)
#define SYSCON_STARTERCLR_OS_EVENT_CLR_SHIFT     (6U)
/*! OS_EVENT_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register.
 */
#define SYSCON_STARTERCLR_OS_EVENT_CLR(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_OS_EVENT_CLR_SHIFT)) & SYSCON_STARTERCLR_OS_EVENT_CLR_MASK)

#define SYSCON_STARTERCLR_GPIO_INT03_CLR_MASK    (0x80U)
#define SYSCON_STARTERCLR_GPIO_INT03_CLR_SHIFT   (7U)
/*! GPIO_INT03_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERCLR_GPIO_INT03_CLR(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT03_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT03_CLR_MASK)

#define SYSCON_STARTERCLR_UTICK0_CLR_MASK        (0x100U)
#define SYSCON_STARTERCLR_UTICK0_CLR_SHIFT       (8U)
/*! UTICK0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERCLR_UTICK0_CLR(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_UTICK0_CLR_SHIFT)) & SYSCON_STARTERCLR_UTICK0_CLR_MASK)

#define SYSCON_STARTERCLR_MRT0_CLR_MASK          (0x200U)
#define SYSCON_STARTERCLR_MRT0_CLR_SHIFT         (9U)
/*! MRT0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERCLR_MRT0_CLR(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_MRT0_CLR_SHIFT)) & SYSCON_STARTERCLR_MRT0_CLR_MASK)

#define SYSCON_STARTERCLR_CTIMER0_CLR_MASK       (0x400U)
#define SYSCON_STARTERCLR_CTIMER0_CLR_SHIFT      (10U)
/*! CTIMER0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERCLR_CTIMER0_CLR(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER0_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER0_CLR_MASK)

#define SYSCON_STARTERCLR_CTIMER1_CLR_MASK       (0x800U)
#define SYSCON_STARTERCLR_CTIMER1_CLR_SHIFT      (11U)
/*! CTIMER1_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERCLR_CTIMER1_CLR(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER1_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER1_CLR_MASK)

#define SYSCON_STARTERCLR_SCT0_CLR_MASK          (0x1000U)
#define SYSCON_STARTERCLR_SCT0_CLR_SHIFT         (12U)
/*! SCT0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERCLR_SCT0_CLR(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SCT0_CLR_SHIFT)) & SYSCON_STARTERCLR_SCT0_CLR_MASK)

#define SYSCON_STARTERCLR_CTIMER3_CLR_MASK       (0x2000U)
#define SYSCON_STARTERCLR_CTIMER3_CLR_SHIFT      (13U)
/*! CTIMER3_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERCLR_CTIMER3_CLR(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER3_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER3_CLR_MASK)

#define SYSCON_STARTERCLR_FLEXINT0_CLR_MASK      (0x4000U)
#define SYSCON_STARTERCLR_FLEXINT0_CLR_SHIFT     (14U)
/*! FLEXINT0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERCLR_FLEXINT0_CLR(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT0_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT0_CLR_MASK)

#define SYSCON_STARTERCLR_FLEXINT1_CLR_MASK      (0x8000U)
#define SYSCON_STARTERCLR_FLEXINT1_CLR_SHIFT     (15U)
/*! FLEXINT1_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERCLR_FLEXINT1_CLR(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT1_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT1_CLR_MASK)

#define SYSCON_STARTERCLR_FLEXINT2_CLR_MASK      (0x10000U)
#define SYSCON_STARTERCLR_FLEXINT2_CLR_SHIFT     (16U)
/*! FLEXINT2_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERCLR_FLEXINT2_CLR(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT2_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT2_CLR_MASK)

#define SYSCON_STARTERCLR_FLEXINT3_CLR_MASK      (0x20000U)
#define SYSCON_STARTERCLR_FLEXINT3_CLR_SHIFT     (17U)
/*! FLEXINT3_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERCLR_FLEXINT3_CLR(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT3_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT3_CLR_MASK)

#define SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR_MASK (0x20000U)
#define SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR_SHIFT (17U)
/*! SEC_HYPERVISOR_CALL_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register.
 */
#define SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR_SHIFT)) & SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR_MASK)

#define SYSCON_STARTERCLR_FLEXINT4_CLR_MASK      (0x40000U)
#define SYSCON_STARTERCLR_FLEXINT4_CLR_SHIFT     (18U)
/*! FLEXINT4_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERCLR_FLEXINT4_CLR(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT4_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT4_CLR_MASK)

#define SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR_MASK (0x40000U)
#define SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR_SHIFT (18U)
/*! SEC_GPIO_INT00_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register.
 */
#define SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR_SHIFT)) & SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR_MASK)

#define SYSCON_STARTERCLR_FLEXINT5_CLR_MASK      (0x80000U)
#define SYSCON_STARTERCLR_FLEXINT5_CLR_SHIFT     (19U)
/*! FLEXINT5_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERCLR_FLEXINT5_CLR(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT5_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT5_CLR_MASK)

#define SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR_MASK (0x80000U)
#define SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR_SHIFT (19U)
/*! SEC_GPIO_INT01_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register.
 */
#define SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR_SHIFT)) & SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR_MASK)

#define SYSCON_STARTERCLR_FLEXINT6_CLR_MASK      (0x100000U)
#define SYSCON_STARTERCLR_FLEXINT6_CLR_SHIFT     (20U)
/*! FLEXINT6_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERCLR_FLEXINT6_CLR(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT6_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT6_CLR_MASK)

#define SYSCON_STARTERCLR_FLEXINT7_CLR_MASK      (0x200000U)
#define SYSCON_STARTERCLR_FLEXINT7_CLR_SHIFT     (21U)
/*! FLEXINT7_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERCLR_FLEXINT7_CLR(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT7_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT7_CLR_MASK)

#define SYSCON_STARTERCLR_ADC0_CLR_MASK          (0x400000U)
#define SYSCON_STARTERCLR_ADC0_CLR_SHIFT         (22U)
/*! ADC0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERCLR_ADC0_CLR(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_ADC0_CLR_SHIFT)) & SYSCON_STARTERCLR_ADC0_CLR_MASK)

#define SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR_MASK (0x1000000U)
#define SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR_SHIFT (24U)
/*! ADC0_THCMP_OVR_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR_SHIFT)) & SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR_MASK)

#define SYSCON_STARTERCLR_QDDKEY_CLR_MASK        (0x1000000U)
#define SYSCON_STARTERCLR_QDDKEY_CLR_SHIFT       (24U)
/*! QDDKEY_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register.
 */
#define SYSCON_STARTERCLR_QDDKEY_CLR(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_QDDKEY_CLR_SHIFT)) & SYSCON_STARTERCLR_QDDKEY_CLR_MASK)

#define SYSCON_STARTERCLR_PQ_CLR_MASK            (0x2000000U)
#define SYSCON_STARTERCLR_PQ_CLR_SHIFT           (25U)
/*! PQ_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register.
 */
#define SYSCON_STARTERCLR_PQ_CLR(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_PQ_CLR_SHIFT)) & SYSCON_STARTERCLR_PQ_CLR_MASK)

#define SYSCON_STARTERCLR_SDMA1_CLR_MASK         (0x4000000U)
#define SYSCON_STARTERCLR_SDMA1_CLR_SHIFT        (26U)
/*! SDMA1_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register.
 */
#define SYSCON_STARTERCLR_SDMA1_CLR(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SDMA1_CLR_SHIFT)) & SYSCON_STARTERCLR_SDMA1_CLR_MASK)

#define SYSCON_STARTERCLR_SPI_HS_CLR_MASK        (0x8000000U)
#define SYSCON_STARTERCLR_SPI_HS_CLR_SHIFT       (27U)
/*! SPI_HS_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register.
 */
#define SYSCON_STARTERCLR_SPI_HS_CLR(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SPI_HS_CLR_SHIFT)) & SYSCON_STARTERCLR_SPI_HS_CLR_MASK)

#define SYSCON_STARTERCLR_USB0_NEEDCLK_CLR_MASK  (0x8000000U)
#define SYSCON_STARTERCLR_USB0_NEEDCLK_CLR_SHIFT (27U)
/*! USB0_NEEDCLK_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERCLR_USB0_NEEDCLK_CLR(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_USB0_NEEDCLK_CLR_SHIFT)) & SYSCON_STARTERCLR_USB0_NEEDCLK_CLR_MASK)

#define SYSCON_STARTERCLR_USB0_CLR_MASK          (0x10000000U)
#define SYSCON_STARTERCLR_USB0_CLR_SHIFT         (28U)
/*! USB0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERCLR_USB0_CLR(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_USB0_CLR_SHIFT)) & SYSCON_STARTERCLR_USB0_CLR_MASK)

#define SYSCON_STARTERCLR_RTC_LITE0_CLR_MASK     (0x20000000U)
#define SYSCON_STARTERCLR_RTC_LITE0_CLR_SHIFT    (29U)
/*! RTC_LITE0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERCLR_RTC_LITE0_CLR(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_RTC_LITE0_CLR_SHIFT)) & SYSCON_STARTERCLR_RTC_LITE0_CLR_MASK)

#define SYSCON_STARTERCLR_EZH_ARCH_B0_CLR_MASK   (0x40000000U)
#define SYSCON_STARTERCLR_EZH_ARCH_B0_CLR_SHIFT  (30U)
/*! EZH_ARCH_B0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERCLR_EZH_ARCH_B0_CLR(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_EZH_ARCH_B0_CLR_SHIFT)) & SYSCON_STARTERCLR_EZH_ARCH_B0_CLR_MASK)

#define SYSCON_STARTERCLR_WAKEUPPADS_CLR_MASK    (0x80000000U)
#define SYSCON_STARTERCLR_WAKEUPPADS_CLR_SHIFT   (31U)
/*! WAKEUPPADS_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register.
 */
#define SYSCON_STARTERCLR_WAKEUPPADS_CLR(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_WAKEUPPADS_CLR_SHIFT)) & SYSCON_STARTERCLR_WAKEUPPADS_CLR_MASK)

#define SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR_MASK (0x80000000U)
#define SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR_SHIFT (31U)
/*! WAKEUP_MAILBOX0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register.
 */
#define SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR_SHIFT)) & SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR_MASK)
/*! @} */

/* The count of SYSCON_STARTERCLR */
#define SYSCON_STARTERCLR_COUNT                  (2U)

/*! @name FUNCRETENTIONCTRL - Functional retention control */
/*! @{ */

#define SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_MASK (0x1U)
#define SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_SHIFT (0U)
/*! FUNCRETENA - functional retention in power down only.
 *  0b1..enable functional retention.
 *  0b0..disable functional retention.
 */
#define SYSCON_FUNCRETENTIONCTRL_FUNCRETENA(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_SHIFT)) & SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_MASK)

#define SYSCON_FUNCRETENTIONCTRL_RET_START_MASK  (0x3FFEU)
#define SYSCON_FUNCRETENTIONCTRL_RET_START_SHIFT (1U)
/*! RET_START - Start address divided by 4 inside SRAMX bank.
 */
#define SYSCON_FUNCRETENTIONCTRL_RET_START(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_FUNCRETENTIONCTRL_RET_START_SHIFT)) & SYSCON_FUNCRETENTIONCTRL_RET_START_MASK)

#define SYSCON_FUNCRETENTIONCTRL_RET_LENTH_MASK  (0xFFC000U)
#define SYSCON_FUNCRETENTIONCTRL_RET_LENTH_SHIFT (14U)
/*! RET_LENTH - lenth of Scan chains to save.
 */
#define SYSCON_FUNCRETENTIONCTRL_RET_LENTH(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_FUNCRETENTIONCTRL_RET_LENTH_SHIFT)) & SYSCON_FUNCRETENTIONCTRL_RET_LENTH_MASK)
/*! @} */

/*! @name HARDWARESLEEP - Hardware Sleep control */
/*! @{ */

#define SYSCON_HARDWARESLEEP_FORCED_MASK         (0x1U)
#define SYSCON_HARDWARESLEEP_FORCED_SHIFT        (0U)
/*! FORCED - Force peripheral clocking to stay on during Deep Sleep and Power-down modes.
 */
#define SYSCON_HARDWARESLEEP_FORCED(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_FORCED_SHIFT)) & SYSCON_HARDWARESLEEP_FORCED_MASK)

#define SYSCON_HARDWARESLEEP_PERIPHERALS_MASK    (0x2U)
#define SYSCON_HARDWARESLEEP_PERIPHERALS_SHIFT   (1U)
/*! PERIPHERALS - Wake for Flexcomms.
 */
#define SYSCON_HARDWARESLEEP_PERIPHERALS(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_PERIPHERALS_SHIFT)) & SYSCON_HARDWARESLEEP_PERIPHERALS_MASK)

#define SYSCON_HARDWARESLEEP_DMIC_MASK           (0x4U)
#define SYSCON_HARDWARESLEEP_DMIC_SHIFT          (2U)
/*! DMIC - Wake for DMIC.
 */
#define SYSCON_HARDWARESLEEP_DMIC(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_DMIC_SHIFT)) & SYSCON_HARDWARESLEEP_DMIC_MASK)

#define SYSCON_HARDWARESLEEP_SDMA0_MASK          (0x8U)
#define SYSCON_HARDWARESLEEP_SDMA0_SHIFT         (3U)
/*! SDMA0 - Wake for DMA0.
 */
#define SYSCON_HARDWARESLEEP_SDMA0(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_SDMA0_SHIFT)) & SYSCON_HARDWARESLEEP_SDMA0_MASK)

#define SYSCON_HARDWARESLEEP_SDMA1_MASK          (0x20U)
#define SYSCON_HARDWARESLEEP_SDMA1_SHIFT         (5U)
/*! SDMA1 - Wake for DMA1.
 */
#define SYSCON_HARDWARESLEEP_SDMA1(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_SDMA1_SHIFT)) & SYSCON_HARDWARESLEEP_SDMA1_MASK)

#define SYSCON_HARDWARESLEEP_DAC_MASK            (0x40U)
#define SYSCON_HARDWARESLEEP_DAC_SHIFT           (6U)
/*! DAC - Wake for DAC0/1/2.
 */
#define SYSCON_HARDWARESLEEP_DAC(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_DAC_SHIFT)) & SYSCON_HARDWARESLEEP_DAC_MASK)

#define SYSCON_HARDWARESLEEP_HW_ENABLE_FRO192M_MASK (0x80000000U)
#define SYSCON_HARDWARESLEEP_HW_ENABLE_FRO192M_SHIFT (31U)
/*! HW_ENABLE_FRO192M - Set this bit if FRO192M is diabled.
 */
#define SYSCON_HARDWARESLEEP_HW_ENABLE_FRO192M(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_HW_ENABLE_FRO192M_SHIFT)) & SYSCON_HARDWARESLEEP_HW_ENABLE_FRO192M_MASK)
/*! @} */

/*! @name CPUSTAT - CPU Status */
/*! @{ */

#define SYSCON_CPUSTAT_CPU0SLEEPING_MASK         (0x1U)
#define SYSCON_CPUSTAT_CPU0SLEEPING_SHIFT        (0U)
/*! CPU0SLEEPING - The CPU0 sleeping state.
 *  0b1..the CPU is sleeping.
 *  0b0..the CPU is not sleeping.
 */
#define SYSCON_CPUSTAT_CPU0SLEEPING(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUSTAT_CPU0SLEEPING_SHIFT)) & SYSCON_CPUSTAT_CPU0SLEEPING_MASK)

#define SYSCON_CPUSTAT_CPU0LOCKUP_MASK           (0x4U)
#define SYSCON_CPUSTAT_CPU0LOCKUP_SHIFT          (2U)
/*! CPU0LOCKUP - The CPU0 lockup state.
 *  0b1..the CPU is in lockup.
 *  0b0..the CPU is not in lockup.
 */
#define SYSCON_CPUSTAT_CPU0LOCKUP(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUSTAT_CPU0LOCKUP_SHIFT)) & SYSCON_CPUSTAT_CPU0LOCKUP_MASK)
/*! @} */

/*! @name LPCAC_CTRL - LPCAC control */
/*! @{ */

#define SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK         (0x1U)
#define SYSCON_LPCAC_CTRL_DIS_LPCAC_SHIFT        (0U)
/*! DIS_LPCAC - Disable/enable cache function. Default value is 1.
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCON_LPCAC_CTRL_DIS_LPCAC(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_DIS_LPCAC_SHIFT)) & SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK)

#define SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK         (0x2U)
#define SYSCON_LPCAC_CTRL_CLR_LPCAC_SHIFT        (1U)
/*! CLR_LPCAC - Clear cache function. Default value is 0.
 *  0b0..Unclear cache
 *  0b1..Clear cache
 */
#define SYSCON_LPCAC_CTRL_CLR_LPCAC(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_CLR_LPCAC_SHIFT)) & SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK)

#define SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_MASK      (0x4U)
#define SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_SHIFT     (2U)
/*! FRC_NO_ALLOC - Force no allocation. Default value is 0.
 *  0b0..Force allocation
 *  0b1..Force no allocation
 */
#define SYSCON_LPCAC_CTRL_FRC_NO_ALLOC(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_SHIFT)) & SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_MASK)

#define SYSCON_LPCAC_CTRL_PARITY_MISS_EN_MASK    (0x8U)
#define SYSCON_LPCAC_CTRL_PARITY_MISS_EN_SHIFT   (3U)
/*! PARITY_MISS_EN - Enable parity miss. Default value is 0.
 *  0b0..Disable
 *  0b1..Enable parity, miss on parity error
 */
#define SYSCON_LPCAC_CTRL_PARITY_MISS_EN(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_PARITY_MISS_EN_SHIFT)) & SYSCON_LPCAC_CTRL_PARITY_MISS_EN_MASK)
/*! @} */

/*! @name FC32KCLKSEL - Flexcomm 32K clock select */
/*! @{ */

#define SYSCON_FC32KCLKSEL_FC32KCLKSEL_MASK      (0x1U)
#define SYSCON_FC32KCLKSEL_FC32KCLKSEL_SHIFT     (0U)
/*! FC32KCLKSEL - Flexcomm 32K clock select
 *  0b0..FRO32K
 *  0b1..XTAL 32K
 */
#define SYSCON_FC32KCLKSEL_FC32KCLKSEL(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_FC32KCLKSEL_FC32KCLKSEL_SHIFT)) & SYSCON_FC32KCLKSEL_FC32KCLKSEL_MASK)
/*! @} */

/*! @name FRGCLKSEL - FRG Clock Source Select */
/*! @{ */

#define SYSCON_FRGCLKSEL_FRG_SRC_SEL_MASK        (0x7U)
#define SYSCON_FRGCLKSEL_FRG_SRC_SEL_SHIFT       (0U)
/*! FRG_SRC_SEL - FRG clock source select
 *  0b000..main clock
 *  0b001..PLL clock
 *  0b010..fro_div_hf
 *  0b011..None
 *  0b100..None
 *  0b101..None
 *  0b110..None
 *  0b111..None
 */
#define SYSCON_FRGCLKSEL_FRG_SRC_SEL(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCLKSEL_FRG_SRC_SEL_SHIFT)) & SYSCON_FRGCLKSEL_FRG_SRC_SEL_MASK)
/*! @} */

/* The count of SYSCON_FRGCLKSEL */
#define SYSCON_FRGCLKSEL_COUNT                   (8U)

/*! @name FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV - Flexcomm clock divider */
/*! @{ */

#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_DIV_MASK (0xFFU)
#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_DIV_SHIFT (0U)
/*! DIV - Clock divider value:
 */
#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_DIV_SHIFT)) & SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_DIV_MASK)

#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_RESET_MASK (0x20000000U)
#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_RESET_SHIFT (29U)
/*! RESET - Reset
 *  0b0..Divider is not reset
 *  0b1..Divider is reset
 */
#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_RESET_SHIFT)) & SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_RESET_MASK)

#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_HALT_MASK (0x40000000U)
#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_HALT_SHIFT (30U)
/*! HALT - Reset
 *  0b0..Divider clock is running
 *  0b1..Divider clock has stopped
 */
#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_HALT_SHIFT)) & SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_HALT_MASK)

#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_REQFLAG_MASK (0x80000000U)
#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_REQFLAG_SHIFT (31U)
/*! REQFLAG - Reset
 *  0b0..Divider clock is stable
 *  0b1..Clock frequency is not stable
 */
#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_REQFLAG_SHIFT)) & SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_REQFLAG_MASK)
/*! @} */

/* The count of SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV */
#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_COUNT (8U)

/*! @name CSS_TEMPORAL_STATE - CSS temporal state */
/*! @{ */

#define SYSCON_CSS_TEMPORAL_STATE_TEMPORAL_STATE_MASK (0xFU)
#define SYSCON_CSS_TEMPORAL_STATE_TEMPORAL_STATE_SHIFT (0U)
/*! TEMPORAL_STATE - Temporal state
 */
#define SYSCON_CSS_TEMPORAL_STATE_TEMPORAL_STATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_TEMPORAL_STATE_TEMPORAL_STATE_SHIFT)) & SYSCON_CSS_TEMPORAL_STATE_TEMPORAL_STATE_MASK)
/*! @} */

/*! @name CSS_KDF_MASK - Key derivation function mask */
/*! @{ */

#define SYSCON_CSS_KDF_MASK_KDF_MASK_MASK        (0xFFFFFFFFU)
#define SYSCON_CSS_KDF_MASK_KDF_MASK_SHIFT       (0U)
/*! KDF_MASK - Key derivation function mask.
 */
#define SYSCON_CSS_KDF_MASK_KDF_MASK(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_KDF_MASK_KDF_MASK_SHIFT)) & SYSCON_CSS_KDF_MASK_KDF_MASK_MASK)
/*! @} */

/*! @name CSS_FEATURE0 - CSS command feature */
/*! @{ */

#define SYSCON_CSS_FEATURE0_CIPHER_MASK          (0x3U)
#define SYSCON_CSS_FEATURE0_CIPHER_SHIFT         (0U)
/*! CIPHER - Enables CIPHER command.
 */
#define SYSCON_CSS_FEATURE0_CIPHER(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_CIPHER_SHIFT)) & SYSCON_CSS_FEATURE0_CIPHER_MASK)

#define SYSCON_CSS_FEATURE0_AUTH_CIPHER_MASK     (0xCU)
#define SYSCON_CSS_FEATURE0_AUTH_CIPHER_SHIFT    (2U)
/*! AUTH_CIPHER - Enables AUTH_CIPHER command.
 */
#define SYSCON_CSS_FEATURE0_AUTH_CIPHER(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_AUTH_CIPHER_SHIFT)) & SYSCON_CSS_FEATURE0_AUTH_CIPHER_MASK)

#define SYSCON_CSS_FEATURE0_ECSIGN_MASK          (0x300U)
#define SYSCON_CSS_FEATURE0_ECSIGN_SHIFT         (8U)
/*! ECSIGN - Enables ECSIGN command.
 */
#define SYSCON_CSS_FEATURE0_ECSIGN(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_ECSIGN_SHIFT)) & SYSCON_CSS_FEATURE0_ECSIGN_MASK)

#define SYSCON_CSS_FEATURE0_ECVFY_MASK           (0xC00U)
#define SYSCON_CSS_FEATURE0_ECVFY_SHIFT          (10U)
/*! ECVFY - Enables ECVFY command.
 */
#define SYSCON_CSS_FEATURE0_ECVFY(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_ECVFY_SHIFT)) & SYSCON_CSS_FEATURE0_ECVFY_MASK)

#define SYSCON_CSS_FEATURE0_ECKXCH_MASK          (0x3000U)
#define SYSCON_CSS_FEATURE0_ECKXCH_SHIFT         (12U)
/*! ECKXCH - Enables ECKXCH command.
 */
#define SYSCON_CSS_FEATURE0_ECKXCH(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_ECKXCH_SHIFT)) & SYSCON_CSS_FEATURE0_ECKXCH_MASK)

#define SYSCON_CSS_FEATURE0_KEYGEN_MASK          (0x30000U)
#define SYSCON_CSS_FEATURE0_KEYGEN_SHIFT         (16U)
/*! KEYGEN - Enables KEYGEN command.
 */
#define SYSCON_CSS_FEATURE0_KEYGEN(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_KEYGEN_SHIFT)) & SYSCON_CSS_FEATURE0_KEYGEN_MASK)

#define SYSCON_CSS_FEATURE0_KEYIN_MASK           (0xC0000U)
#define SYSCON_CSS_FEATURE0_KEYIN_SHIFT          (18U)
/*! KEYIN - Enables KEYIN command.
 */
#define SYSCON_CSS_FEATURE0_KEYIN(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_KEYIN_SHIFT)) & SYSCON_CSS_FEATURE0_KEYIN_MASK)

#define SYSCON_CSS_FEATURE0_KEYOUT_MASK          (0x300000U)
#define SYSCON_CSS_FEATURE0_KEYOUT_SHIFT         (20U)
/*! KEYOUT - Enables KEYOUT command.
 */
#define SYSCON_CSS_FEATURE0_KEYOUT(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_KEYOUT_SHIFT)) & SYSCON_CSS_FEATURE0_KEYOUT_MASK)

#define SYSCON_CSS_FEATURE0_KDELETE_MASK         (0xC00000U)
#define SYSCON_CSS_FEATURE0_KDELETE_SHIFT        (22U)
/*! KDELETE - Enables KDELETE command.
 */
#define SYSCON_CSS_FEATURE0_KDELETE(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_KDELETE_SHIFT)) & SYSCON_CSS_FEATURE0_KDELETE_MASK)
/*! @} */

/*! @name CSS_FEATURE1 - CSS command feature */
/*! @{ */

#define SYSCON_CSS_FEATURE1_CKDF_MASK            (0x3U)
#define SYSCON_CSS_FEATURE1_CKDF_SHIFT           (0U)
/*! CKDF - Enables CKDF command.
 */
#define SYSCON_CSS_FEATURE1_CKDF(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_CKDF_SHIFT)) & SYSCON_CSS_FEATURE1_CKDF_MASK)

#define SYSCON_CSS_FEATURE1_HKDF_MASK            (0xCU)
#define SYSCON_CSS_FEATURE1_HKDF_SHIFT           (2U)
/*! HKDF - Enables HKDF command.
 */
#define SYSCON_CSS_FEATURE1_HKDF(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_HKDF_SHIFT)) & SYSCON_CSS_FEATURE1_HKDF_MASK)

#define SYSCON_CSS_FEATURE1_TLS_INIT_MASK        (0x30U)
#define SYSCON_CSS_FEATURE1_TLS_INIT_SHIFT       (4U)
/*! TLS_INIT - Enables TLS_INIT command.
 */
#define SYSCON_CSS_FEATURE1_TLS_INIT(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_TLS_INIT_SHIFT)) & SYSCON_CSS_FEATURE1_TLS_INIT_MASK)

#define SYSCON_CSS_FEATURE1_HASH_MASK            (0x300U)
#define SYSCON_CSS_FEATURE1_HASH_SHIFT           (8U)
/*! HASH - Enables HASH command.
 */
#define SYSCON_CSS_FEATURE1_HASH(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_HASH_SHIFT)) & SYSCON_CSS_FEATURE1_HASH_MASK)

#define SYSCON_CSS_FEATURE1_HMAC_MASK            (0xC00U)
#define SYSCON_CSS_FEATURE1_HMAC_SHIFT           (10U)
/*! HMAC - Enables HMAC command.
 */
#define SYSCON_CSS_FEATURE1_HMAC(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_HMAC_SHIFT)) & SYSCON_CSS_FEATURE1_HMAC_MASK)

#define SYSCON_CSS_FEATURE1_CMAC_MASK            (0x3000U)
#define SYSCON_CSS_FEATURE1_CMAC_SHIFT           (12U)
/*! CMAC - Enables CMAC command.
 */
#define SYSCON_CSS_FEATURE1_CMAC(x)              (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_CMAC_SHIFT)) & SYSCON_CSS_FEATURE1_CMAC_MASK)

#define SYSCON_CSS_FEATURE1_DRBG_REQ_MASK        (0x30000U)
#define SYSCON_CSS_FEATURE1_DRBG_REQ_SHIFT       (16U)
/*! DRBG_REQ - Enables DRBG_REQ command.
 */
#define SYSCON_CSS_FEATURE1_DRBG_REQ(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_DRBG_REQ_SHIFT)) & SYSCON_CSS_FEATURE1_DRBG_REQ_MASK)

#define SYSCON_CSS_FEATURE1_DRBG_TEST_MASK       (0xC0000U)
#define SYSCON_CSS_FEATURE1_DRBG_TEST_SHIFT      (18U)
/*! DRBG_TEST - Enables DRBG_TEST command.
 */
#define SYSCON_CSS_FEATURE1_DRBG_TEST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_DRBG_TEST_SHIFT)) & SYSCON_CSS_FEATURE1_DRBG_TEST_MASK)

#define SYSCON_CSS_FEATURE1_DTRNG_CFG_LOAD_MASK  (0x3000000U)
#define SYSCON_CSS_FEATURE1_DTRNG_CFG_LOAD_SHIFT (24U)
/*! DTRNG_CFG_LOAD - Enables DTRNG_CFG_LOAD command.
 */
#define SYSCON_CSS_FEATURE1_DTRNG_CFG_LOAD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_DTRNG_CFG_LOAD_SHIFT)) & SYSCON_CSS_FEATURE1_DTRNG_CFG_LOAD_MASK)

#define SYSCON_CSS_FEATURE1_DTRNG_EVAL_MASK      (0xC000000U)
#define SYSCON_CSS_FEATURE1_DTRNG_EVAL_SHIFT     (26U)
/*! DTRNG_EVAL - Enables DTRNG_EVAL command.
 */
#define SYSCON_CSS_FEATURE1_DTRNG_EVAL(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_DTRNG_EVAL_SHIFT)) & SYSCON_CSS_FEATURE1_DTRNG_EVAL_MASK)

#define SYSCON_CSS_FEATURE1_GDET_CFG_LOAD_MASK   (0x30000000U)
#define SYSCON_CSS_FEATURE1_GDET_CFG_LOAD_SHIFT  (28U)
/*! GDET_CFG_LOAD - Enables GDET_CFG_LOAD command.
 */
#define SYSCON_CSS_FEATURE1_GDET_CFG_LOAD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_GDET_CFG_LOAD_SHIFT)) & SYSCON_CSS_FEATURE1_GDET_CFG_LOAD_MASK)
/*! @} */

/*! @name CSS_FEATURE0_DP - CSS command feature - duplicate version */
/*! @{ */

#define SYSCON_CSS_FEATURE0_DP_CIPHER_MASK       (0x3U)
#define SYSCON_CSS_FEATURE0_DP_CIPHER_SHIFT      (0U)
/*! CIPHER - Enables CIPHER command.
 */
#define SYSCON_CSS_FEATURE0_DP_CIPHER(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_DP_CIPHER_SHIFT)) & SYSCON_CSS_FEATURE0_DP_CIPHER_MASK)

#define SYSCON_CSS_FEATURE0_DP_AUTH_CIPHER_MASK  (0xCU)
#define SYSCON_CSS_FEATURE0_DP_AUTH_CIPHER_SHIFT (2U)
/*! AUTH_CIPHER - Enables AUTH_CIPHER command.
 */
#define SYSCON_CSS_FEATURE0_DP_AUTH_CIPHER(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_DP_AUTH_CIPHER_SHIFT)) & SYSCON_CSS_FEATURE0_DP_AUTH_CIPHER_MASK)

#define SYSCON_CSS_FEATURE0_DP_ECSIGN_MASK       (0x300U)
#define SYSCON_CSS_FEATURE0_DP_ECSIGN_SHIFT      (8U)
/*! ECSIGN - Enables ECSIGN command.
 */
#define SYSCON_CSS_FEATURE0_DP_ECSIGN(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_DP_ECSIGN_SHIFT)) & SYSCON_CSS_FEATURE0_DP_ECSIGN_MASK)

#define SYSCON_CSS_FEATURE0_DP_ECVFY_MASK        (0xC00U)
#define SYSCON_CSS_FEATURE0_DP_ECVFY_SHIFT       (10U)
/*! ECVFY - Enables ECSIGN command.
 */
#define SYSCON_CSS_FEATURE0_DP_ECVFY(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_DP_ECVFY_SHIFT)) & SYSCON_CSS_FEATURE0_DP_ECVFY_MASK)

#define SYSCON_CSS_FEATURE0_DP_ECKXCH_MASK       (0x3000U)
#define SYSCON_CSS_FEATURE0_DP_ECKXCH_SHIFT      (12U)
/*! ECKXCH - Enables ECSIGN command.
 */
#define SYSCON_CSS_FEATURE0_DP_ECKXCH(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_DP_ECKXCH_SHIFT)) & SYSCON_CSS_FEATURE0_DP_ECKXCH_MASK)

#define SYSCON_CSS_FEATURE0_DP_KEYGEN_MASK       (0x30000U)
#define SYSCON_CSS_FEATURE0_DP_KEYGEN_SHIFT      (16U)
/*! KEYGEN - Enables KEYGEN command.
 */
#define SYSCON_CSS_FEATURE0_DP_KEYGEN(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_DP_KEYGEN_SHIFT)) & SYSCON_CSS_FEATURE0_DP_KEYGEN_MASK)

#define SYSCON_CSS_FEATURE0_DP_KEYIN_MASK        (0xC0000U)
#define SYSCON_CSS_FEATURE0_DP_KEYIN_SHIFT       (18U)
/*! KEYIN - Enables KEYIN command.
 */
#define SYSCON_CSS_FEATURE0_DP_KEYIN(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_DP_KEYIN_SHIFT)) & SYSCON_CSS_FEATURE0_DP_KEYIN_MASK)

#define SYSCON_CSS_FEATURE0_DP_KEYOUT_MASK       (0x300000U)
#define SYSCON_CSS_FEATURE0_DP_KEYOUT_SHIFT      (20U)
/*! KEYOUT - Enables KEYOUT command.
 */
#define SYSCON_CSS_FEATURE0_DP_KEYOUT(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_DP_KEYOUT_SHIFT)) & SYSCON_CSS_FEATURE0_DP_KEYOUT_MASK)

#define SYSCON_CSS_FEATURE0_DP_KDELETE_MASK      (0xC00000U)
#define SYSCON_CSS_FEATURE0_DP_KDELETE_SHIFT     (22U)
/*! KDELETE - Enables KDELETE command.
 */
#define SYSCON_CSS_FEATURE0_DP_KDELETE(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE0_DP_KDELETE_SHIFT)) & SYSCON_CSS_FEATURE0_DP_KDELETE_MASK)
/*! @} */

/*! @name CSS_FEATURE1_DP - CSS command feature - duplicate version */
/*! @{ */

#define SYSCON_CSS_FEATURE1_DP_CKDF_MASK         (0x3U)
#define SYSCON_CSS_FEATURE1_DP_CKDF_SHIFT        (0U)
/*! CKDF - Enables CKDF command.
 */
#define SYSCON_CSS_FEATURE1_DP_CKDF(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_DP_CKDF_SHIFT)) & SYSCON_CSS_FEATURE1_DP_CKDF_MASK)

#define SYSCON_CSS_FEATURE1_DP_HKDF_MASK         (0xCU)
#define SYSCON_CSS_FEATURE1_DP_HKDF_SHIFT        (2U)
/*! HKDF - Enables HKDF command.
 */
#define SYSCON_CSS_FEATURE1_DP_HKDF(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_DP_HKDF_SHIFT)) & SYSCON_CSS_FEATURE1_DP_HKDF_MASK)

#define SYSCON_CSS_FEATURE1_DP_TLS_INIT_MASK     (0x30U)
#define SYSCON_CSS_FEATURE1_DP_TLS_INIT_SHIFT    (4U)
/*! TLS_INIT - Enables TLS_INIT command.
 */
#define SYSCON_CSS_FEATURE1_DP_TLS_INIT(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_DP_TLS_INIT_SHIFT)) & SYSCON_CSS_FEATURE1_DP_TLS_INIT_MASK)

#define SYSCON_CSS_FEATURE1_DP_HASH_MASK         (0x300U)
#define SYSCON_CSS_FEATURE1_DP_HASH_SHIFT        (8U)
/*! HASH - Enables HASH command.
 */
#define SYSCON_CSS_FEATURE1_DP_HASH(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_DP_HASH_SHIFT)) & SYSCON_CSS_FEATURE1_DP_HASH_MASK)

#define SYSCON_CSS_FEATURE1_DP_HMAC_MASK         (0xC00U)
#define SYSCON_CSS_FEATURE1_DP_HMAC_SHIFT        (10U)
/*! HMAC - Enables HMAC command.
 */
#define SYSCON_CSS_FEATURE1_DP_HMAC(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_DP_HMAC_SHIFT)) & SYSCON_CSS_FEATURE1_DP_HMAC_MASK)

#define SYSCON_CSS_FEATURE1_DP_CMAC_MASK         (0x3000U)
#define SYSCON_CSS_FEATURE1_DP_CMAC_SHIFT        (12U)
/*! CMAC - Enables CMAC command.
 */
#define SYSCON_CSS_FEATURE1_DP_CMAC(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_DP_CMAC_SHIFT)) & SYSCON_CSS_FEATURE1_DP_CMAC_MASK)

#define SYSCON_CSS_FEATURE1_DP_DRBG_REQ_MASK     (0x30000U)
#define SYSCON_CSS_FEATURE1_DP_DRBG_REQ_SHIFT    (16U)
/*! DRBG_REQ - Enables DRBG_REQ command.
 */
#define SYSCON_CSS_FEATURE1_DP_DRBG_REQ(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_DP_DRBG_REQ_SHIFT)) & SYSCON_CSS_FEATURE1_DP_DRBG_REQ_MASK)

#define SYSCON_CSS_FEATURE1_DP_DRBG_TEST_MASK    (0xC0000U)
#define SYSCON_CSS_FEATURE1_DP_DRBG_TEST_SHIFT   (18U)
/*! DRBG_TEST - Enables DRBG_TEST command.
 */
#define SYSCON_CSS_FEATURE1_DP_DRBG_TEST(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_DP_DRBG_TEST_SHIFT)) & SYSCON_CSS_FEATURE1_DP_DRBG_TEST_MASK)

#define SYSCON_CSS_FEATURE1_DP_DTRNG_CFG_LOAD_MASK (0x3000000U)
#define SYSCON_CSS_FEATURE1_DP_DTRNG_CFG_LOAD_SHIFT (24U)
/*! DTRNG_CFG_LOAD - Enables DTRNG_CFG_LOAD command.
 */
#define SYSCON_CSS_FEATURE1_DP_DTRNG_CFG_LOAD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_DP_DTRNG_CFG_LOAD_SHIFT)) & SYSCON_CSS_FEATURE1_DP_DTRNG_CFG_LOAD_MASK)

#define SYSCON_CSS_FEATURE1_DP_DTRNG_EVAL_MASK   (0xC000000U)
#define SYSCON_CSS_FEATURE1_DP_DTRNG_EVAL_SHIFT  (26U)
/*! DTRNG_EVAL - Enables DTRNG_EVAL command.
 */
#define SYSCON_CSS_FEATURE1_DP_DTRNG_EVAL(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_DP_DTRNG_EVAL_SHIFT)) & SYSCON_CSS_FEATURE1_DP_DTRNG_EVAL_MASK)

#define SYSCON_CSS_FEATURE1_DP_GDET_CFG_LOAD_MASK (0x30000000U)
#define SYSCON_CSS_FEATURE1_DP_GDET_CFG_LOAD_SHIFT (28U)
/*! GDET_CFG_LOAD - Enables GDET_CFG_LOAD command.
 */
#define SYSCON_CSS_FEATURE1_DP_GDET_CFG_LOAD(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_FEATURE1_DP_GDET_CFG_LOAD_SHIFT)) & SYSCON_CSS_FEATURE1_DP_GDET_CFG_LOAD_MASK)
/*! @} */

/*! @name CSS_BOOT_RETRY_CNT - CSS boot retry counter */
/*! @{ */

#define SYSCON_CSS_BOOT_RETRY_CNT_BOOT_RETRY_CNT_MASK (0xFFFFFFFFU)
#define SYSCON_CSS_BOOT_RETRY_CNT_BOOT_RETRY_CNT_SHIFT (0U)
/*! BOOT_RETRY_CNT - Boot retry counter bit.
 */
#define SYSCON_CSS_BOOT_RETRY_CNT_BOOT_RETRY_CNT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_BOOT_RETRY_CNT_BOOT_RETRY_CNT_SHIFT)) & SYSCON_CSS_BOOT_RETRY_CNT_BOOT_RETRY_CNT_MASK)
/*! @} */

/*! @name CSS_CLK_CTRL - CSS clock control */
/*! @{ */

#define SYSCON_CSS_CLK_CTRL_GDET_REFCLK_EN_MASK  (0x1U)
#define SYSCON_CSS_CLK_CTRL_GDET_REFCLK_EN_SHIFT (0U)
/*! GDET_REFCLK_EN - GDET reference clock enable bit.
 */
#define SYSCON_CSS_CLK_CTRL_GDET_REFCLK_EN(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_CLK_CTRL_GDET_REFCLK_EN_SHIFT)) & SYSCON_CSS_CLK_CTRL_GDET_REFCLK_EN_MASK)

#define SYSCON_CSS_CLK_CTRL_DTRNG_REFCLK_EN_MASK (0x2U)
#define SYSCON_CSS_CLK_CTRL_DTRNG_REFCLK_EN_SHIFT (1U)
/*! DTRNG_REFCLK_EN - DTRNG reference clock enable bit.
 */
#define SYSCON_CSS_CLK_CTRL_DTRNG_REFCLK_EN(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_CLK_CTRL_DTRNG_REFCLK_EN_SHIFT)) & SYSCON_CSS_CLK_CTRL_DTRNG_REFCLK_EN_MASK)
/*! @} */

/*! @name CSS_CLK_CTRL_SET - CSS clock control set */
/*! @{ */

#define SYSCON_CSS_CLK_CTRL_SET_GDET_REFCLK_EN_SET_MASK (0x1U)
#define SYSCON_CSS_CLK_CTRL_SET_GDET_REFCLK_EN_SET_SHIFT (0U)
/*! GDET_REFCLK_EN_SET - GDET reference clock enable set bit.
 */
#define SYSCON_CSS_CLK_CTRL_SET_GDET_REFCLK_EN_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_CLK_CTRL_SET_GDET_REFCLK_EN_SET_SHIFT)) & SYSCON_CSS_CLK_CTRL_SET_GDET_REFCLK_EN_SET_MASK)

#define SYSCON_CSS_CLK_CTRL_SET_DTRNG_REFCLK_EN_SET_MASK (0x2U)
#define SYSCON_CSS_CLK_CTRL_SET_DTRNG_REFCLK_EN_SET_SHIFT (1U)
/*! DTRNG_REFCLK_EN_SET - DTRNG reference clock enable set bit.
 */
#define SYSCON_CSS_CLK_CTRL_SET_DTRNG_REFCLK_EN_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_CLK_CTRL_SET_DTRNG_REFCLK_EN_SET_SHIFT)) & SYSCON_CSS_CLK_CTRL_SET_DTRNG_REFCLK_EN_SET_MASK)
/*! @} */

/*! @name CSS_CLK_CTRL_CLR - CSS clock control clear */
/*! @{ */

#define SYSCON_CSS_CLK_CTRL_CLR_GDET_REFCLK_EN_CLR_MASK (0x1U)
#define SYSCON_CSS_CLK_CTRL_CLR_GDET_REFCLK_EN_CLR_SHIFT (0U)
/*! GDET_REFCLK_EN_CLR - GDET reference clock enable clear bit.
 */
#define SYSCON_CSS_CLK_CTRL_CLR_GDET_REFCLK_EN_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_CLK_CTRL_CLR_GDET_REFCLK_EN_CLR_SHIFT)) & SYSCON_CSS_CLK_CTRL_CLR_GDET_REFCLK_EN_CLR_MASK)

#define SYSCON_CSS_CLK_CTRL_CLR_DTRNG_REFCLK_EN_CLR_MASK (0x2U)
#define SYSCON_CSS_CLK_CTRL_CLR_DTRNG_REFCLK_EN_CLR_SHIFT (1U)
/*! DTRNG_REFCLK_EN_CLR - DTRNG reference clock enable clear bit.
 */
#define SYSCON_CSS_CLK_CTRL_CLR_DTRNG_REFCLK_EN_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_CLK_CTRL_CLR_DTRNG_REFCLK_EN_CLR_SHIFT)) & SYSCON_CSS_CLK_CTRL_CLR_DTRNG_REFCLK_EN_CLR_MASK)
/*! @} */

/*! @name CSS_CLK_SEL - CSS clock select */
/*! @{ */

#define SYSCON_CSS_CLK_SEL_GDET_REFCLK_SEL_MASK  (0x3U)
#define SYSCON_CSS_CLK_SEL_GDET_REFCLK_SEL_SHIFT (0U)
/*! GDET_REFCLK_SEL - GDET reference clock select bit.
 */
#define SYSCON_CSS_CLK_SEL_GDET_REFCLK_SEL(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_CLK_SEL_GDET_REFCLK_SEL_SHIFT)) & SYSCON_CSS_CLK_SEL_GDET_REFCLK_SEL_MASK)
/*! @} */

/*! @name CSS_AS_CFG0 - CSS AS configuration */
/*! @{ */

#define SYSCON_CSS_AS_CFG0_CFG_LC_STATE_MASK     (0xFFU)
#define SYSCON_CSS_AS_CFG0_CFG_LC_STATE_SHIFT    (0U)
/*! CFG_LC_STATE - LC state configuration bit.
 */
#define SYSCON_CSS_AS_CFG0_CFG_LC_STATE(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG0_CFG_LC_STATE_SHIFT)) & SYSCON_CSS_AS_CFG0_CFG_LC_STATE_MASK)

#define SYSCON_CSS_AS_CFG0_CFG_BOD_VDDMAIN_RESET_ENABLED_MASK (0x100U)
#define SYSCON_CSS_AS_CFG0_CFG_BOD_VDDMAIN_RESET_ENABLED_SHIFT (8U)
/*! CFG_BOD_VDDMAIN_RESET_ENABLED - When BOD VDDMAIN analog detector is turned on and BOD VDDMAIN reset is enabled, this bit indicates state 1.
 */
#define SYSCON_CSS_AS_CFG0_CFG_BOD_VDDMAIN_RESET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG0_CFG_BOD_VDDMAIN_RESET_ENABLED_SHIFT)) & SYSCON_CSS_AS_CFG0_CFG_BOD_VDDMAIN_RESET_ENABLED_MASK)

#define SYSCON_CSS_AS_CFG0_CFG_BOD_CORE_RESET_ENABLED_MASK (0x200U)
#define SYSCON_CSS_AS_CFG0_CFG_BOD_CORE_RESET_ENABLED_SHIFT (9U)
/*! CFG_BOD_CORE_RESET_ENABLED - When BOD CORE analog detector is turned on and BOD CORE reset is enabled, this bit indicates state 1.
 */
#define SYSCON_CSS_AS_CFG0_CFG_BOD_CORE_RESET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG0_CFG_BOD_CORE_RESET_ENABLED_SHIFT)) & SYSCON_CSS_AS_CFG0_CFG_BOD_CORE_RESET_ENABLED_MASK)

#define SYSCON_CSS_AS_CFG0_CFG_BOD_VDDMAIN_IRQ_ENABLED_MASK (0x400U)
#define SYSCON_CSS_AS_CFG0_CFG_BOD_VDDMAIN_IRQ_ENABLED_SHIFT (10U)
/*! CFG_BOD_VDDMAIN_IRQ_ENABLED - When BOD VDDMAIN analog detector is turned on and BOD VDDMAIN IRQ is enabled, this bit indicates state 1.
 */
#define SYSCON_CSS_AS_CFG0_CFG_BOD_VDDMAIN_IRQ_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG0_CFG_BOD_VDDMAIN_IRQ_ENABLED_SHIFT)) & SYSCON_CSS_AS_CFG0_CFG_BOD_VDDMAIN_IRQ_ENABLED_MASK)

#define SYSCON_CSS_AS_CFG0_CFG_WDT_ENABLED_MASK  (0x1000U)
#define SYSCON_CSS_AS_CFG0_CFG_WDT_ENABLED_SHIFT (12U)
/*! CFG_WDT_ENABLED - When WatchDog Timer is activated, this bit indicates state 1.
 */
#define SYSCON_CSS_AS_CFG0_CFG_WDT_ENABLED(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG0_CFG_WDT_ENABLED_SHIFT)) & SYSCON_CSS_AS_CFG0_CFG_WDT_ENABLED_MASK)

#define SYSCON_CSS_AS_CFG0_CFG_CWDT_ENABLED_MASK (0x2000U)
#define SYSCON_CSS_AS_CFG0_CFG_CWDT_ENABLED_SHIFT (13U)
/*! CFG_CWDT_ENABLED - When Code WatchDog Timer is activated, this bit indicates state 1.
 */
#define SYSCON_CSS_AS_CFG0_CFG_CWDT_ENABLED(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG0_CFG_CWDT_ENABLED_SHIFT)) & SYSCON_CSS_AS_CFG0_CFG_CWDT_ENABLED_MASK)

#define SYSCON_CSS_AS_CFG0_CFG_CSS_GDET_ENABLED_MASK (0x8000U)
#define SYSCON_CSS_AS_CFG0_CFG_CSS_GDET_ENABLED_SHIFT (15U)
/*! CFG_CSS_GDET_ENABLED - When CSS GDET is enabled, this bit indicates state 1.
 */
#define SYSCON_CSS_AS_CFG0_CFG_CSS_GDET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG0_CFG_CSS_GDET_ENABLED_SHIFT)) & SYSCON_CSS_AS_CFG0_CFG_CSS_GDET_ENABLED_MASK)

#define SYSCON_CSS_AS_CFG0_CFG_ANA_GDET_ENABLED_MASK (0x10000U)
#define SYSCON_CSS_AS_CFG0_CFG_ANA_GDET_ENABLED_SHIFT (16U)
/*! CFG_ANA_GDET_ENABLED - When ANALOG GDET is enabled, this bit indicates state 1.
 */
#define SYSCON_CSS_AS_CFG0_CFG_ANA_GDET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG0_CFG_ANA_GDET_ENABLED_SHIFT)) & SYSCON_CSS_AS_CFG0_CFG_ANA_GDET_ENABLED_MASK)

#define SYSCON_CSS_AS_CFG0_CFG_TAMPER_DET_ENABLED_MASK (0x20000U)
#define SYSCON_CSS_AS_CFG0_CFG_TAMPER_DET_ENABLED_SHIFT (17U)
/*! CFG_TAMPER_DET_ENABLED - When tamper detector is enabled in RTC, this bit indicates state 1.
 */
#define SYSCON_CSS_AS_CFG0_CFG_TAMPER_DET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG0_CFG_TAMPER_DET_ENABLED_SHIFT)) & SYSCON_CSS_AS_CFG0_CFG_TAMPER_DET_ENABLED_MASK)

#define SYSCON_CSS_AS_CFG0_CFG_FLASH_IS_REMAPPED_MASK (0x40000U)
#define SYSCON_CSS_AS_CFG0_CFG_FLASH_IS_REMAPPED_SHIFT (18U)
/*! CFG_FLASH_IS_REMAPPED - When FLASHREMAP_OFFSET register (0x4000_0448) is not equal to 0x0000_0000, this bit indicates state 1.
 */
#define SYSCON_CSS_AS_CFG0_CFG_FLASH_IS_REMAPPED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG0_CFG_FLASH_IS_REMAPPED_SHIFT)) & SYSCON_CSS_AS_CFG0_CFG_FLASH_IS_REMAPPED_MASK)

#define SYSCON_CSS_AS_CFG0_CFG_FLASH_IS_REMAPPED_DP_MASK (0x80000U)
#define SYSCON_CSS_AS_CFG0_CFG_FLASH_IS_REMAPPED_DP_SHIFT (19U)
/*! CFG_FLASH_IS_REMAPPED_DP - When FLASHREMAP_OFFSET_DP register (0x4000_044C) is not equal to 0x0000_0000, this bit indicates state 1.
 */
#define SYSCON_CSS_AS_CFG0_CFG_FLASH_IS_REMAPPED_DP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG0_CFG_FLASH_IS_REMAPPED_DP_SHIFT)) & SYSCON_CSS_AS_CFG0_CFG_FLASH_IS_REMAPPED_DP_MASK)

#define SYSCON_CSS_AS_CFG0_CFG_FLASH_BANK0_ENABLE_MASK (0xF00000U)
#define SYSCON_CSS_AS_CFG0_CFG_FLASH_BANK0_ENABLE_SHIFT (20U)
/*! CFG_FLASH_BANK0_ENABLE - The state of FLASHBANK_ENABLE0 register (0x4000_0450) reflects to this register as below.
 */
#define SYSCON_CSS_AS_CFG0_CFG_FLASH_BANK0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG0_CFG_FLASH_BANK0_ENABLE_SHIFT)) & SYSCON_CSS_AS_CFG0_CFG_FLASH_BANK0_ENABLE_MASK)

#define SYSCON_CSS_AS_CFG0_CFG_FLASH_BANK1_ENABLE_MASK (0xF000000U)
#define SYSCON_CSS_AS_CFG0_CFG_FLASH_BANK1_ENABLE_SHIFT (24U)
/*! CFG_FLASH_BANK1_ENABLE - The state of FLASHBANK_ENABLE1 register (0x4000_0454) reflects to this register as below:
 */
#define SYSCON_CSS_AS_CFG0_CFG_FLASH_BANK1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG0_CFG_FLASH_BANK1_ENABLE_SHIFT)) & SYSCON_CSS_AS_CFG0_CFG_FLASH_BANK1_ENABLE_MASK)

#define SYSCON_CSS_AS_CFG0_CFG_QK_DISABLE_ENROLL_MASK (0x10000000U)
#define SYSCON_CSS_AS_CFG0_CFG_QK_DISABLE_ENROLL_SHIFT (28U)
/*! CFG_QK_DISABLE_ENROLL - When CONFIG[DIS_PUF_ENROLL] bit is set 1, this bit indicates state 1.
 */
#define SYSCON_CSS_AS_CFG0_CFG_QK_DISABLE_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG0_CFG_QK_DISABLE_ENROLL_SHIFT)) & SYSCON_CSS_AS_CFG0_CFG_QK_DISABLE_ENROLL_MASK)

#define SYSCON_CSS_AS_CFG0_CFG_QK_DISABLE_WRAP_MASK (0x20000000U)
#define SYSCON_CSS_AS_CFG0_CFG_QK_DISABLE_WRAP_SHIFT (29U)
/*! CFG_QK_DISABLE_WRAP - When CONFIG[DIS_PUF_WRAP_KEY] bit is set 1, this bit indicates state 1.
 */
#define SYSCON_CSS_AS_CFG0_CFG_QK_DISABLE_WRAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG0_CFG_QK_DISABLE_WRAP_SHIFT)) & SYSCON_CSS_AS_CFG0_CFG_QK_DISABLE_WRAP_MASK)
/*! @} */

/*! @name CSS_AS_CFG1 - CSS AS configuration1 */
/*! @{ */

#define SYSCON_CSS_AS_CFG1_CFG_SEC_DIS_STRICT_MODE_MASK (0x2U)
#define SYSCON_CSS_AS_CFG1_CFG_SEC_DIS_STRICT_MODE_SHIFT (1U)
/*! CFG_SEC_DIS_STRICT_MODE - When "CFG_SEC_ENA_SEC_CHK" indicates state 0 or when
 *    "DISABLE_STRICT_MODE" bits in "MISC_CTRL_REG" and "MISC_CTRL_DP_REG" on AHB secure controller, both bits are
 *    equal to 01, this bit indicates state 1.
 */
#define SYSCON_CSS_AS_CFG1_CFG_SEC_DIS_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG1_CFG_SEC_DIS_STRICT_MODE_SHIFT)) & SYSCON_CSS_AS_CFG1_CFG_SEC_DIS_STRICT_MODE_MASK)

#define SYSCON_CSS_AS_CFG1_CFG_SEC_DIS_VIOL_ABORT_MASK (0x4U)
#define SYSCON_CSS_AS_CFG1_CFG_SEC_DIS_VIOL_ABORT_SHIFT (2U)
/*! CFG_SEC_DIS_VIOL_ABORT - When "DISABLE_VIOLATION_ABORT" bits in "MISC_CTRL_REG" and
 *    "MISC_CTRL_DP_REG" on AHB secure controller, both bits are not equal to 10, this bit indicates state 1.
 */
#define SYSCON_CSS_AS_CFG1_CFG_SEC_DIS_VIOL_ABORT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG1_CFG_SEC_DIS_VIOL_ABORT_SHIFT)) & SYSCON_CSS_AS_CFG1_CFG_SEC_DIS_VIOL_ABORT_MASK)

#define SYSCON_CSS_AS_CFG1_CFG_SEC_ENA_NS_PRIV_CHK_MASK (0x8U)
#define SYSCON_CSS_AS_CFG1_CFG_SEC_ENA_NS_PRIV_CHK_SHIFT (3U)
/*! CFG_SEC_ENA_NS_PRIV_CHK - When "ENABLE_NS_PRIV_CHECK" bits in "MISC_CTRL_REG" and
 *    "MISC_CTRL_DP_REG" on AHB secure controller, both bits are not equal to 10, this bit indicates state 1.
 */
#define SYSCON_CSS_AS_CFG1_CFG_SEC_ENA_NS_PRIV_CHK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG1_CFG_SEC_ENA_NS_PRIV_CHK_SHIFT)) & SYSCON_CSS_AS_CFG1_CFG_SEC_ENA_NS_PRIV_CHK_MASK)

#define SYSCON_CSS_AS_CFG1_CFG_SEC_ENA_S_PRIV_CHK_MASK (0x10U)
#define SYSCON_CSS_AS_CFG1_CFG_SEC_ENA_S_PRIV_CHK_SHIFT (4U)
/*! CFG_SEC_ENA_S_PRIV_CHK - When "ENABLE_S_PRIV_CHECK" bits in "MISC_CTRL_REG" and
 *    "MISC_CTRL_DP_REG" on AHB secure controller, both bits are not equal to 10, this bit indicates state 1.
 */
#define SYSCON_CSS_AS_CFG1_CFG_SEC_ENA_S_PRIV_CHK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG1_CFG_SEC_ENA_S_PRIV_CHK_SHIFT)) & SYSCON_CSS_AS_CFG1_CFG_SEC_ENA_S_PRIV_CHK_MASK)

#define SYSCON_CSS_AS_CFG1_CFG_SEC_ENA_SEC_CHK_MASK (0x20U)
#define SYSCON_CSS_AS_CFG1_CFG_SEC_ENA_SEC_CHK_SHIFT (5U)
/*! CFG_SEC_ENA_SEC_CHK - When "ENABLE_SECURE_CHECKING" bits in "MISC_CTRL_REG" and
 *    "MISC_CTRL_DP_REG" on AHB secure controller, both bits are not equal to 10, this bit indicates state 1.
 */
#define SYSCON_CSS_AS_CFG1_CFG_SEC_ENA_SEC_CHK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG1_CFG_SEC_ENA_SEC_CHK_SHIFT)) & SYSCON_CSS_AS_CFG1_CFG_SEC_ENA_SEC_CHK_MASK)

#define SYSCON_CSS_AS_CFG1_CFG_SEC_IDAU_ALLNS_MASK (0x40U)
#define SYSCON_CSS_AS_CFG1_CFG_SEC_IDAU_ALLNS_SHIFT (6U)
/*! CFG_SEC_IDAU_ALLNS - When "IDAU_ALL_NS" bits in "MISC_CTRL_REG" and "MISC_CTRL_DP_REG" on AHB
 *    secure controller, both bits are equal to 01, this bit indicates state 1.
 */
#define SYSCON_CSS_AS_CFG1_CFG_SEC_IDAU_ALLNS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG1_CFG_SEC_IDAU_ALLNS_SHIFT)) & SYSCON_CSS_AS_CFG1_CFG_SEC_IDAU_ALLNS_MASK)

#define SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_NS_MPU_MASK (0x100U)
#define SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_NS_MPU_SHIFT (8U)
/*! CFG_SEC_LOCK_NS_MPU - When "LOCK_NS_MPU" bits in "CPU0_LOCK_REG" on AHB secure controller are not equal to 10, this bit indicates state 1.
 */
#define SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_NS_MPU_SHIFT)) & SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_NS_MPU_MASK)

#define SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_NS_VTOR_MASK (0x200U)
#define SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_NS_VTOR_SHIFT (9U)
/*! CFG_SEC_LOCK_NS_VTOR - When "LOCK_NS_VTOR" bits in "CPU0_LOCK_REG" on AHB secure controller are not equal to 10, this bit indicates state 1.
 */
#define SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_NS_VTOR_SHIFT)) & SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_NS_VTOR_MASK)

#define SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_S_MPU_MASK (0x400U)
#define SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_S_MPU_SHIFT (10U)
/*! CFG_SEC_LOCK_S_MPU - When "LOCK_S_MPU" bits in "CPU0_LOCK_REG" on AHB secure controller are not equal to 10, this bit indicates state 1.
 */
#define SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_S_MPU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_S_MPU_SHIFT)) & SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_S_MPU_MASK)

#define SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_S_VTAIRCR_MASK (0x800U)
#define SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_S_VTAIRCR_SHIFT (11U)
/*! CFG_SEC_LOCK_S_VTAIRCR - When "LOCK_S_VTAIRCR" bits in "CPU0_LOCK_REG" on AHB secure controller are not equal to 10, this bit indicates state 1.
 */
#define SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_S_VTAIRCR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_S_VTAIRCR_SHIFT)) & SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_S_VTAIRCR_MASK)

#define SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_SAU_MASK (0x1000U)
#define SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_SAU_SHIFT (12U)
/*! CFG_SEC_LOCK_SAU - When "LOCK_SAU" bits in "CPU0_LOCK_REG" on AHB secure controller are not equal to 10, this bit indicates state 1.
 */
#define SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_SAU(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_SAU_SHIFT)) & SYSCON_CSS_AS_CFG1_CFG_SEC_LOCK_SAU_MASK)
/*! @} */

/*! @name CSS_AS_CFG2 - CSS AS configuration2 */
/*! @{ */

#define SYSCON_CSS_AS_CFG2_CFG_CSS_CMD_EN_MASK   (0xFFFFFFFFU)
#define SYSCON_CSS_AS_CFG2_CFG_CSS_CMD_EN_SHIFT  (0U)
/*! CFG_CSS_CMD_EN - CSS configuration command enable bit.
 */
#define SYSCON_CSS_AS_CFG2_CFG_CSS_CMD_EN(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_CFG2_CFG_CSS_CMD_EN_SHIFT)) & SYSCON_CSS_AS_CFG2_CFG_CSS_CMD_EN_MASK)
/*! @} */

/*! @name CSS_AS_ST0 - CSS AS state register */
/*! @{ */

#define SYSCON_CSS_AS_ST0_ST_TEMPORAL_STATE_MASK (0xFU)
#define SYSCON_CSS_AS_ST0_ST_TEMPORAL_STATE_SHIFT (0U)
/*! ST_TEMPORAL_STATE - "TEMPORAL_STATE[3:0]" on "CSS_TEMPORAL_STATE" register reflects this register.
 */
#define SYSCON_CSS_AS_ST0_ST_TEMPORAL_STATE(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_ST0_ST_TEMPORAL_STATE_SHIFT)) & SYSCON_CSS_AS_ST0_ST_TEMPORAL_STATE_MASK)

#define SYSCON_CSS_AS_ST0_ST_CPU0_DBGEN_MASK     (0x10U)
#define SYSCON_CSS_AS_ST0_ST_CPU0_DBGEN_SHIFT    (4U)
/*! ST_CPU0_DBGEN - When CPU0 (CM33) "deben" input is state 1, this bit indicates state 1.
 */
#define SYSCON_CSS_AS_ST0_ST_CPU0_DBGEN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_ST0_ST_CPU0_DBGEN_SHIFT)) & SYSCON_CSS_AS_ST0_ST_CPU0_DBGEN_MASK)

#define SYSCON_CSS_AS_ST0_ST_CPU0_NIDEN_MASK     (0x20U)
#define SYSCON_CSS_AS_ST0_ST_CPU0_NIDEN_SHIFT    (5U)
/*! ST_CPU0_NIDEN - When CPU0 (CM33) "niden" input is state 1, this bit indicates state 1.
 */
#define SYSCON_CSS_AS_ST0_ST_CPU0_NIDEN(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_ST0_ST_CPU0_NIDEN_SHIFT)) & SYSCON_CSS_AS_ST0_ST_CPU0_NIDEN_MASK)

#define SYSCON_CSS_AS_ST0_ST_CPU0_SPIDEN_MASK    (0x40U)
#define SYSCON_CSS_AS_ST0_ST_CPU0_SPIDEN_SHIFT   (6U)
/*! ST_CPU0_SPIDEN - When CPU0 (CM33) "spiden" input is state 1, this bit indicates state 1.
 */
#define SYSCON_CSS_AS_ST0_ST_CPU0_SPIDEN(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_ST0_ST_CPU0_SPIDEN_SHIFT)) & SYSCON_CSS_AS_ST0_ST_CPU0_SPIDEN_MASK)

#define SYSCON_CSS_AS_ST0_ST_CPU0_SPNIDEN_MASK   (0x80U)
#define SYSCON_CSS_AS_ST0_ST_CPU0_SPNIDEN_SHIFT  (7U)
/*! ST_CPU0_SPNIDEN - When CPU0 (CM33) "spniden" input is state 1, this bit indicates state 1.
 */
#define SYSCON_CSS_AS_ST0_ST_CPU0_SPNIDEN(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_ST0_ST_CPU0_SPNIDEN_SHIFT)) & SYSCON_CSS_AS_ST0_ST_CPU0_SPNIDEN_MASK)

#define SYSCON_CSS_AS_ST0_ST_DAP_ENABLE_CPU0_MASK (0x400U)
#define SYSCON_CSS_AS_ST0_ST_DAP_ENABLE_CPU0_SHIFT (10U)
/*! ST_DAP_ENABLE_CPU0 - When DAP to AP0 for CPU0 (CM33) debug access is allowed, this bit indicates state 1.
 */
#define SYSCON_CSS_AS_ST0_ST_DAP_ENABLE_CPU0(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_ST0_ST_DAP_ENABLE_CPU0_SHIFT)) & SYSCON_CSS_AS_ST0_ST_DAP_ENABLE_CPU0_MASK)

#define SYSCON_CSS_AS_ST0_ST_CSS_DEBUG_EN_MASK   (0x2000U)
#define SYSCON_CSS_AS_ST0_ST_CSS_DEBUG_EN_SHIFT  (13U)
/*! ST_CSS_DEBUG_EN - When CSS uCode code fetch out of AHB for debug is enabled, this bit indicates state 1.
 */
#define SYSCON_CSS_AS_ST0_ST_CSS_DEBUG_EN(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_ST0_ST_CSS_DEBUG_EN_SHIFT)) & SYSCON_CSS_AS_ST0_ST_CSS_DEBUG_EN_MASK)

#define SYSCON_CSS_AS_ST0_ST_ALLOW_TEST_ACCESS_MASK (0x4000U)
#define SYSCON_CSS_AS_ST0_ST_ALLOW_TEST_ACCESS_SHIFT (14U)
/*! ST_ALLOW_TEST_ACCESS - When JTAG TAP access is allowed, this bit indicates state 1.
 */
#define SYSCON_CSS_AS_ST0_ST_ALLOW_TEST_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_ST0_ST_ALLOW_TEST_ACCESS_SHIFT)) & SYSCON_CSS_AS_ST0_ST_ALLOW_TEST_ACCESS_MASK)

#define SYSCON_CSS_AS_ST0_ST_XO32K_FAILED_MASK   (0x8000U)
#define SYSCON_CSS_AS_ST0_ST_XO32K_FAILED_SHIFT  (15U)
/*! ST_XO32K_FAILED - When XO32K oscillation fail flag is state 1 in PMC register block, this bit indicates state 1.
 */
#define SYSCON_CSS_AS_ST0_ST_XO32K_FAILED(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_ST0_ST_XO32K_FAILED_SHIFT)) & SYSCON_CSS_AS_ST0_ST_XO32K_FAILED_MASK)
/*! @} */

/*! @name CSS_AS_ST1 - CSS AS state1 */
/*! @{ */

#define SYSCON_CSS_AS_ST1_ST_QK_PUF_SCORE_MASK   (0xFU)
#define SYSCON_CSS_AS_ST1_ST_QK_PUF_SCORE_SHIFT  (0U)
/*! ST_QK_PUF_SCORE - These register bits indicate the state of "qk_puf_score[3:0]" outputs from QK PUF block.
 */
#define SYSCON_CSS_AS_ST1_ST_QK_PUF_SCORE(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_ST1_ST_QK_PUF_SCORE_SHIFT)) & SYSCON_CSS_AS_ST1_ST_QK_PUF_SCORE_MASK)

#define SYSCON_CSS_AS_ST1_ST_QK_ZEROIZED_MASK    (0x10U)
#define SYSCON_CSS_AS_ST1_ST_QK_ZEROIZED_SHIFT   (4U)
/*! ST_QK_ZEROIZED - This register bit indicates the state of "qk_zeroized" output from QK PUF block.
 */
#define SYSCON_CSS_AS_ST1_ST_QK_ZEROIZED(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_ST1_ST_QK_ZEROIZED_SHIFT)) & SYSCON_CSS_AS_ST1_ST_QK_ZEROIZED_MASK)

#define SYSCON_CSS_AS_ST1_ST_MAIN_CLK_IS_EXT_MASK (0x20U)
#define SYSCON_CSS_AS_ST1_ST_MAIN_CLK_IS_EXT_SHIFT (5U)
/*! ST_MAIN_CLK_IS_EXT - When MAIN_CLK is running from external clock source either XO32M, XO32K or GPIO CLKIN, this bit indicates state 1.
 */
#define SYSCON_CSS_AS_ST1_ST_MAIN_CLK_IS_EXT(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_ST1_ST_MAIN_CLK_IS_EXT_SHIFT)) & SYSCON_CSS_AS_ST1_ST_MAIN_CLK_IS_EXT_MASK)

#define SYSCON_CSS_AS_ST1_ST_DCDC_VOUT_MASK      (0x3C0U)
#define SYSCON_CSS_AS_ST1_ST_DCDC_VOUT_SHIFT     (6U)
/*! ST_DCDC_VOUT - VOUT[3:0] setting on DCDC0 register in PMC block will reflect to this register.
 */
#define SYSCON_CSS_AS_ST1_ST_DCDC_VOUT(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_ST1_ST_DCDC_VOUT_SHIFT)) & SYSCON_CSS_AS_ST1_ST_DCDC_VOUT_MASK)

#define SYSCON_CSS_AS_ST1_ST_BOOT_MODE_MASK      (0xC00U)
#define SYSCON_CSS_AS_ST1_ST_BOOT_MODE_SHIFT     (10U)
/*! ST_BOOT_MODE - BOOTMODE[1:0] status on STATUS register in PMC block will reflect to this register.
 */
#define SYSCON_CSS_AS_ST1_ST_BOOT_MODE(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_ST1_ST_BOOT_MODE_SHIFT)) & SYSCON_CSS_AS_ST1_ST_BOOT_MODE_MASK)

#define SYSCON_CSS_AS_ST1_ST_BOOT_RETRY_CNT_MASK (0xF000U)
#define SYSCON_CSS_AS_ST1_ST_BOOT_RETRY_CNT_SHIFT (12U)
/*! ST_BOOT_RETRY_CNT - "BOOT_RETRY_CNT[3:0]" on "CSS_BOOT_RETRY_CNT" register reflects this register.
 */
#define SYSCON_CSS_AS_ST1_ST_BOOT_RETRY_CNT(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_ST1_ST_BOOT_RETRY_CNT_SHIFT)) & SYSCON_CSS_AS_ST1_ST_BOOT_RETRY_CNT_MASK)
/*! @} */

/*! @name CSS_AS_ST2 - CSS AS state2 */
/*! @{ */

#define SYSCON_CSS_AS_ST2_CSS_AS_ST2_MASK        (0xFFFFFFFFU)
#define SYSCON_CSS_AS_ST2_CSS_AS_ST2_SHIFT       (0U)
/*! CSS_AS_ST2 - "BOOT_STATE[31:0]" on "CSS_BOOT_STATE" register reflects this register.
 */
#define SYSCON_CSS_AS_ST2_CSS_AS_ST2(x)          (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_ST2_CSS_AS_ST2_SHIFT)) & SYSCON_CSS_AS_ST2_CSS_AS_ST2_MASK)
/*! @} */

/*! @name CSS_AS_FLAG0 - CSS AS flag0 */
/*! @{ */

#define SYSCON_CSS_AS_FLAG0_FLAG_AP_ENABLE_CPU0_MASK (0x1U)
#define SYSCON_CSS_AS_FLAG0_FLAG_AP_ENABLE_CPU0_SHIFT (0U)
/*! FLAG_AP_ENABLE_CPU0 - This flag bit is set 1 when DAP enables AP0 for CPU0 (CM33) debug access. The register is cleared 0 by PMC reset event.
 */
#define SYSCON_CSS_AS_FLAG0_FLAG_AP_ENABLE_CPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_FLAG0_FLAG_AP_ENABLE_CPU0_SHIFT)) & SYSCON_CSS_AS_FLAG0_FLAG_AP_ENABLE_CPU0_MASK)

#define SYSCON_CSS_AS_FLAG0_FLAG_BOD_VDDMAIN_RESET_OCCURED_MASK (0x10U)
#define SYSCON_CSS_AS_FLAG0_FLAG_BOD_VDDMAIN_RESET_OCCURED_SHIFT (4U)
/*! FLAG_BOD_VDDMAIN_RESET_OCCURED - This flag bit is set 1 when BOD VDDMAIN reset is enabled and
 *    BOD VDDMAIN analog detector is tripped. This register is cleared 0 by AO domain POR.
 */
#define SYSCON_CSS_AS_FLAG0_FLAG_BOD_VDDMAIN_RESET_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_FLAG0_FLAG_BOD_VDDMAIN_RESET_OCCURED_SHIFT)) & SYSCON_CSS_AS_FLAG0_FLAG_BOD_VDDMAIN_RESET_OCCURED_MASK)

#define SYSCON_CSS_AS_FLAG0_FLAG_BOD_CORE_RESET_OCCURED_MASK (0x20U)
#define SYSCON_CSS_AS_FLAG0_FLAG_BOD_CORE_RESET_OCCURED_SHIFT (5U)
/*! FLAG_BOD_CORE_RESET_OCCURED - This flag bit is set 1 when BOD CORE reset is enabled and BOD CORE
 *    analog detector is tripped. This register is cleared 0 by AO domain POR.
 */
#define SYSCON_CSS_AS_FLAG0_FLAG_BOD_CORE_RESET_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_FLAG0_FLAG_BOD_CORE_RESET_OCCURED_SHIFT)) & SYSCON_CSS_AS_FLAG0_FLAG_BOD_CORE_RESET_OCCURED_MASK)

#define SYSCON_CSS_AS_FLAG0_FLAG_BOD_VDDMAIN_IRQ_OCCURED_MASK (0x40U)
#define SYSCON_CSS_AS_FLAG0_FLAG_BOD_VDDMAIN_IRQ_OCCURED_SHIFT (6U)
/*! FLAG_BOD_VDDMAIN_IRQ_OCCURED - This flag bit is set 1 when BOD VDDMAIN IRQ is enabled and BOD
 *    VDDMAIN analog detector is tripped. This register is cleared 0 by PMC reset event.
 */
#define SYSCON_CSS_AS_FLAG0_FLAG_BOD_VDDMAIN_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_FLAG0_FLAG_BOD_VDDMAIN_IRQ_OCCURED_SHIFT)) & SYSCON_CSS_AS_FLAG0_FLAG_BOD_VDDMAIN_IRQ_OCCURED_MASK)

#define SYSCON_CSS_AS_FLAG0_FLAG_BOD_CORE_IRQ_OCCURED_MASK (0x80U)
#define SYSCON_CSS_AS_FLAG0_FLAG_BOD_CORE_IRQ_OCCURED_SHIFT (7U)
/*! FLAG_BOD_CORE_IRQ_OCCURED - This flag bit is set 1 when BOD CORE IRQ is enabled and BOD CORE
 *    analog detector is tripped. This register is cleared 0 by PMC reset event.
 */
#define SYSCON_CSS_AS_FLAG0_FLAG_BOD_CORE_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_FLAG0_FLAG_BOD_CORE_IRQ_OCCURED_SHIFT)) & SYSCON_CSS_AS_FLAG0_FLAG_BOD_CORE_IRQ_OCCURED_MASK)

#define SYSCON_CSS_AS_FLAG0_FLAG_WDT_RESET_OCCURED_MASK (0x100U)
#define SYSCON_CSS_AS_FLAG0_FLAG_WDT_RESET_OCCURED_SHIFT (8U)
/*! FLAG_WDT_RESET_OCCURED - This flag bit is set 1 when WatchDog Timer reset is enabled and reset
 *    event is triggered. This register is cleared 0 by AO domain POR.
 */
#define SYSCON_CSS_AS_FLAG0_FLAG_WDT_RESET_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_FLAG0_FLAG_WDT_RESET_OCCURED_SHIFT)) & SYSCON_CSS_AS_FLAG0_FLAG_WDT_RESET_OCCURED_MASK)

#define SYSCON_CSS_AS_FLAG0_FLAG_CWDT_RESET_OCCURED_MASK (0x200U)
#define SYSCON_CSS_AS_FLAG0_FLAG_CWDT_RESET_OCCURED_SHIFT (9U)
/*! FLAG_CWDT_RESET_OCCURED - This flag bit is set 1 when Code WatchDog Timer reset is enabled and
 *    reset event is triggered. This register is cleared 0 by AO domain POR.
 */
#define SYSCON_CSS_AS_FLAG0_FLAG_CWDT_RESET_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_FLAG0_FLAG_CWDT_RESET_OCCURED_SHIFT)) & SYSCON_CSS_AS_FLAG0_FLAG_CWDT_RESET_OCCURED_MASK)

#define SYSCON_CSS_AS_FLAG0_FLAG_WDT_IRQ_OCCURED_MASK (0x400U)
#define SYSCON_CSS_AS_FLAG0_FLAG_WDT_IRQ_OCCURED_SHIFT (10U)
/*! FLAG_WDT_IRQ_OCCURED - This flag register is set 1 when WatchDog Timer IRQ is enabled and IRQ
 *    event is triggered. This register is cleared 0 by PMC reset event.
 */
#define SYSCON_CSS_AS_FLAG0_FLAG_WDT_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_FLAG0_FLAG_WDT_IRQ_OCCURED_SHIFT)) & SYSCON_CSS_AS_FLAG0_FLAG_WDT_IRQ_OCCURED_MASK)

#define SYSCON_CSS_AS_FLAG0_FLAG_CWDT_IRQ_OCCURED_MASK (0x800U)
#define SYSCON_CSS_AS_FLAG0_FLAG_CWDT_IRQ_OCCURED_SHIFT (11U)
/*! FLAG_CWDT_IRQ_OCCURED - This flag bit is set 1 when Code WatchDog Timer IRQ is enabled and IRQ
 *    event is triggered. This register is cleared 0 by PMC reset event.
 */
#define SYSCON_CSS_AS_FLAG0_FLAG_CWDT_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_FLAG0_FLAG_CWDT_IRQ_OCCURED_SHIFT)) & SYSCON_CSS_AS_FLAG0_FLAG_CWDT_IRQ_OCCURED_MASK)

#define SYSCON_CSS_AS_FLAG0_FLAG_QK_ERROR_MASK   (0x1000U)
#define SYSCON_CSS_AS_FLAG0_FLAG_QK_ERROR_SHIFT  (12U)
/*! FLAG_QK_ERROR - This flag bit is set 1 when QK_ERROR is flagged from QK PUF block. This register is cleared 0 by PMC reset event.
 */
#define SYSCON_CSS_AS_FLAG0_FLAG_QK_ERROR(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_FLAG0_FLAG_QK_ERROR_SHIFT)) & SYSCON_CSS_AS_FLAG0_FLAG_QK_ERROR_MASK)

#define SYSCON_CSS_AS_FLAG0_FLAG_CSS_GLITCH_DETECTED_MASK (0x2000U)
#define SYSCON_CSS_AS_FLAG0_FLAG_CSS_GLITCH_DETECTED_SHIFT (13U)
/*! FLAG_CSS_GLITCH_DETECTED - This flag bit is set 1 when GDET error is flagged from CSS. This register is cleared 0 by PMC reset event.
 */
#define SYSCON_CSS_AS_FLAG0_FLAG_CSS_GLITCH_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_FLAG0_FLAG_CSS_GLITCH_DETECTED_SHIFT)) & SYSCON_CSS_AS_FLAG0_FLAG_CSS_GLITCH_DETECTED_MASK)

#define SYSCON_CSS_AS_FLAG0_FLAG_ANA_GLITCH_DETECTED_MASK (0x4000U)
#define SYSCON_CSS_AS_FLAG0_FLAG_ANA_GLITCH_DETECTED_SHIFT (14U)
/*! FLAG_ANA_GLITCH_DETECTED - This flag bit is set 1 when ANALOG GDET error is flagged in SYSCON block. This register is cleared 0 by PMC reset event.
 */
#define SYSCON_CSS_AS_FLAG0_FLAG_ANA_GLITCH_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_FLAG0_FLAG_ANA_GLITCH_DETECTED_SHIFT)) & SYSCON_CSS_AS_FLAG0_FLAG_ANA_GLITCH_DETECTED_MASK)

#define SYSCON_CSS_AS_FLAG0_FLAG_TAMPER_EVENT_DETECTED_MASK (0x8000U)
#define SYSCON_CSS_AS_FLAG0_FLAG_TAMPER_EVENT_DETECTED_SHIFT (15U)
/*! FLAG_TAMPER_EVENT_DETECTED - This flag bit is set 1 when tamper event is flagged from RTC. This
 *    register is cleared 0 by AO domain POR or by PMC reset event, if ranmpr detection event is
 *    cleared by software.
 */
#define SYSCON_CSS_AS_FLAG0_FLAG_TAMPER_EVENT_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_FLAG0_FLAG_TAMPER_EVENT_DETECTED_SHIFT)) & SYSCON_CSS_AS_FLAG0_FLAG_TAMPER_EVENT_DETECTED_MASK)

#define SYSCON_CSS_AS_FLAG0_FLAG_FLASH_ECC_INVALID_MASK (0x10000U)
#define SYSCON_CSS_AS_FLAG0_FLAG_FLASH_ECC_INVALID_SHIFT (16U)
/*! FLAG_FLASH_ECC_INVALID - This flag bit is set 1 when FLASH controller indicates ECC error. This register is cleared 0 by PMC reset event.
 */
#define SYSCON_CSS_AS_FLAG0_FLAG_FLASH_ECC_INVALID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_FLAG0_FLAG_FLASH_ECC_INVALID_SHIFT)) & SYSCON_CSS_AS_FLAG0_FLAG_FLASH_ECC_INVALID_MASK)

#define SYSCON_CSS_AS_FLAG0_FLAG_SEC_VIOL_IRQ_OCURRED_MASK (0x20000U)
#define SYSCON_CSS_AS_FLAG0_FLAG_SEC_VIOL_IRQ_OCURRED_SHIFT (17U)
/*! FLAG_SEC_VIOL_IRQ_OCURRED - This flag bit is set 1 when security violation is indicated from FLASH sub-system or AHB bus matrix.
 */
#define SYSCON_CSS_AS_FLAG0_FLAG_SEC_VIOL_IRQ_OCURRED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_FLAG0_FLAG_SEC_VIOL_IRQ_OCURRED_SHIFT)) & SYSCON_CSS_AS_FLAG0_FLAG_SEC_VIOL_IRQ_OCURRED_MASK)

#define SYSCON_CSS_AS_FLAG0_FLAG_CPU0_NS_C_ACC_OCCURED_MASK (0x40000U)
#define SYSCON_CSS_AS_FLAG0_FLAG_CPU0_NS_C_ACC_OCCURED_SHIFT (18U)
/*! FLAG_CPU0_NS_C_ACC_OCCURED - This flag bit is set 1 when CPU0 (CM33) makes non-secure code
 *    transactions. This register is cleared 0 by PMC reset event.
 */
#define SYSCON_CSS_AS_FLAG0_FLAG_CPU0_NS_C_ACC_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_FLAG0_FLAG_CPU0_NS_C_ACC_OCCURED_SHIFT)) & SYSCON_CSS_AS_FLAG0_FLAG_CPU0_NS_C_ACC_OCCURED_MASK)

#define SYSCON_CSS_AS_FLAG0_FLAG_CPU0_NS_D_ACC_OCCURED_MASK (0x80000U)
#define SYSCON_CSS_AS_FLAG0_FLAG_CPU0_NS_D_ACC_OCCURED_SHIFT (19U)
/*! FLAG_CPU0_NS_D_ACC_OCCURED - This flag register is set 1 when CPU0 (CM33) makes non-secure data
 *    transactions. This register is cleared 0 by PMC reset event.
 */
#define SYSCON_CSS_AS_FLAG0_FLAG_CPU0_NS_D_ACC_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CSS_AS_FLAG0_FLAG_CPU0_NS_D_ACC_OCCURED_SHIFT)) & SYSCON_CSS_AS_FLAG0_FLAG_CPU0_NS_D_ACC_OCCURED_MASK)
/*! @} */

/*! @name CLOCK_CTRL - Clock Control */
/*! @{ */

#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_MASK (0x2U)
#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_SHIFT (1U)
/*! XTAL32MHZ_FREQM_ENA - Enable XTAL32MHz clock for Frequency Measure module.
 *  0b1..The clock is enabled.
 *  0b0..The clock is not enabled.
 */
#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_MASK)

#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_MASK (0x4U)
#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_SHIFT (2U)
/*! FRO1MHZ_UTICK_ENA - Enable FRO 1MHz clock for Frequency Measure module and for UTICK.
 *  0b1..The clock is enabled.
 *  0b0..The clock is not enabled.
 */
#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_MASK)

#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_MASK (0x8U)
#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_SHIFT (3U)
/*! FRO12MHZ_FREQM_ENA - Enable FRO 12MHz clock for Frequency Measure module.
 *  0b1..The clock is enabled.
 *  0b0..The clock is not enabled.
 */
#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_MASK)

#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_MASK  (0x10U)
#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_SHIFT (4U)
/*! FRO_HF_FREQM_ENA - Enable FRO 96MHz clock for Frequency Measure module.
 *  0b1..The clock is enabled.
 *  0b0..The clock is not enabled.
 */
#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_MASK)

#define SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK         (0x20U)
#define SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT        (5U)
/*! CLKIN_ENA - Enable clock_in clock for clock module.
 *  0b1..The clock is enabled.
 *  0b0..The clock is not enabled.
 */
#define SYSCON_CLOCK_CTRL_CLKIN_ENA(x)           (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK)

#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK   (0x40U)
#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT  (6U)
/*! FRO1MHZ_CLK_ENA - Enable FRO 1MHz clock for clock muxing in clock gen.
 *  0b1..The clock is enabled.
 *  0b0..The clock is not enabled.
 */
#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK)

#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_MASK (0x80U)
#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_SHIFT (7U)
/*! ANA_FRO12M_CLK_ENA - Enable FRO 12MHz clock for analog control of the FRO 192MHz.
 *  0b1..The clock is enabled.
 *  0b0..The clock is not enabled.
 */
#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_MASK)

#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_MASK    (0x100U)
#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_SHIFT   (8U)
/*! XO_CAL_CLK_ENA - Enable clock for crystal oscillator calibration
 *  0b1..The clock is enabled.
 *  0b0..The clock is not enabled.
 */
#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_MASK)
/*! @} */

/*! @name COMP_INT_CTRL - Comparator Interrupt control */
/*! @{ */

#define SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK     (0x1U)
#define SYSCON_COMP_INT_CTRL_INT_ENABLE_SHIFT    (0U)
/*! INT_ENABLE - Analog Comparator interrupt enable control:.
 *  0b1..interrupt enable.
 *  0b0..interrupt disable.
 */
#define SYSCON_COMP_INT_CTRL_INT_ENABLE(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_ENABLE_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK)

#define SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK      (0x2U)
#define SYSCON_COMP_INT_CTRL_INT_CLEAR_SHIFT     (1U)
/*! INT_CLEAR - Analog Comparator interrupt clear.
 *  0b0..No effect.
 *  0b1..Clear the interrupt. Self-cleared bit.
 */
#define SYSCON_COMP_INT_CTRL_INT_CLEAR(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_CLEAR_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK)

#define SYSCON_COMP_INT_CTRL_INT_CTRL_MASK       (0x1CU)
#define SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT      (2U)
/*! INT_CTRL - Comparator interrupt type selector:.
 *  0b000..The analog comparator interrupt edge sensitive is disabled.
 *  0b010..analog comparator interrupt is rising edge sensitive.
 *  0b100..analog comparator interrupt is falling edge sensitive.
 *  0b110..analog comparator interrupt is rising and falling edge sensitive.
 *  0b001..The analog comparator interrupt level sensitive is disabled.
 *  0b011..Analog Comparator interrupt is high level sensitive.
 *  0b101..Analog Comparator interrupt is low level sensitive.
 *  0b111..The analog comparator interrupt level sensitive is disabled.
 */
#define SYSCON_COMP_INT_CTRL_INT_CTRL(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_CTRL_MASK)

#define SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK     (0x20U)
#define SYSCON_COMP_INT_CTRL_INT_SOURCE_SHIFT    (5U)
/*! INT_SOURCE - Select which Analog comparator output (filtered our un-filtered) is used for interrupt detection.
 *  0b0..Select Analog Comparator filtered output as input for interrupt detection.
 *  0b1..Select Analog Comparator raw output (unfiltered) as input for interrupt detection. Must be used when
 *       Analog comparator is used as wake up source in Power down mode.
 */
#define SYSCON_COMP_INT_CTRL_INT_SOURCE(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_SOURCE_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK)
/*! @} */

/*! @name COMP_INT_STATUS - Comparator Interrupt status */
/*! @{ */

#define SYSCON_COMP_INT_STATUS_STATUS_MASK       (0x1U)
#define SYSCON_COMP_INT_STATUS_STATUS_SHIFT      (0U)
/*! STATUS - Interrupt status BEFORE Interrupt Enable.
 *  0b0..No interrupt pending.
 *  0b1..Interrupt pending.
 */
#define SYSCON_COMP_INT_STATUS_STATUS(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_STATUS_SHIFT)) & SYSCON_COMP_INT_STATUS_STATUS_MASK)

#define SYSCON_COMP_INT_STATUS_INT_STATUS_MASK   (0x2U)
#define SYSCON_COMP_INT_STATUS_INT_STATUS_SHIFT  (1U)
/*! INT_STATUS - Interrupt status AFTER Interrupt Enable.
 *  0b0..no interrupt pending.
 *  0b1..interrupt pending.
 */
#define SYSCON_COMP_INT_STATUS_INT_STATUS(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_INT_STATUS_SHIFT)) & SYSCON_COMP_INT_STATUS_INT_STATUS_MASK)

#define SYSCON_COMP_INT_STATUS_VAL_MASK          (0x4U)
#define SYSCON_COMP_INT_STATUS_VAL_SHIFT         (2U)
/*! VAL - comparator analog output.
 *  0b1..P+ is greater than P-.
 *  0b0..P+ is smaller than P-.
 */
#define SYSCON_COMP_INT_STATUS_VAL(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_VAL_SHIFT)) & SYSCON_COMP_INT_STATUS_VAL_MASK)
/*! @} */

/*! @name AUTOCLKGATEOVERRIDE - Control automatic clock gating */
/*! @{ */

#define SYSCON_AUTOCLKGATEOVERRIDE_ROM_MASK      (0x1U)
#define SYSCON_AUTOCLKGATEOVERRIDE_ROM_SHIFT     (0U)
/*! ROM - Control automatic clock gating of ROM controller.
 *  0b1..Automatic clock gating is overridden (Clock gating is disabled).
 *  0b0..Automatic clock gating is not overridden.
 */
#define SYSCON_AUTOCLKGATEOVERRIDE_ROM(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_ROM_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_ROM_MASK)

#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_MASK     (0x2U)
#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_SHIFT    (1U)
/*! RAMX - Control automatic clock gating of RAMX controller.
 *  0b1..Automatic clock gating is overridden (Clock gating is disabled).
 *  0b0..Automatic clock gating is not overridden.
 */
#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAMX_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAMX_MASK)

#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_MASK     (0x4U)
#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_SHIFT    (2U)
/*! RAM0 - Control automatic clock gating of RAM0 controller.
 *  0b1..Automatic clock gating is overridden (Clock gating is disabled).
 *  0b0..Automatic clock gating is not overridden.
 */
#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM0_MASK)

#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_MASK     (0x8U)
#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_SHIFT    (3U)
/*! RAM1 - Control automatic clock gating of RAM1 controller.
 *  0b1..Automatic clock gating is overridden (Clock gating is disabled).
 *  0b0..Automatic clock gating is not overridden.
 */
#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM1_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM1_MASK)

#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_MASK     (0x10U)
#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_SHIFT    (4U)
/*! RAM2 - Control automatic clock gating of RAM2 controller.
 *  0b1..Automatic clock gating is overridden (Clock gating is disabled).
 *  0b0..Automatic clock gating is not overridden.
 */
#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM2_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM2_MASK)

#define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_MASK     (0x20U)
#define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_SHIFT    (5U)
/*! RAM3 - Control automatic clock gating of RAM3 controller.
 *  0b1..Automatic clock gating is overridden (Clock gating is disabled).
 *  0b0..Automatic clock gating is not overridden.
 */
#define SYSCON_AUTOCLKGATEOVERRIDE_RAM3(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM3_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM3_MASK)

#define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_MASK     (0x40U)
#define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_SHIFT    (6U)
/*! RAM4 - Control automatic clock gating of RAM4 controller.
 *  0b1..Automatic clock gating is overridden (Clock gating is disabled).
 *  0b0..Automatic clock gating is not overridden.
 */
#define SYSCON_AUTOCLKGATEOVERRIDE_RAM4(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM4_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM4_MASK)

#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_MASK (0x80U)
#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_SHIFT (7U)
/*! SYNC0_APB - Control automatic clock gating of synchronous bridge controller 0.
 *  0b1..Automatic clock gating is overridden (Clock gating is disabled).
 *  0b0..Automatic clock gating is not overridden.
 */
#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_MASK)

#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_MASK (0x100U)
#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_SHIFT (8U)
/*! SYNC1_APB - Control automatic clock gating of synchronous bridge controller 1.
 *  0b1..Automatic clock gating is overridden (Clock gating is disabled).
 *  0b0..Automatic clock gating is not overridden.
 */
#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_MASK)

#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_MASK   (0x800U)
#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_SHIFT  (11U)
/*! CRCGEN - Control automatic clock gating of CRCGEN controller.
 *  0b1..Automatic clock gating is overridden (Clock gating is disabled).
 *  0b0..Automatic clock gating is not overridden.
 */
#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_MASK)

#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_MASK    (0x1000U)
#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_SHIFT   (12U)
/*! SDMA0 - Control automatic clock gating of DMA0 controller.
 *  0b1..Automatic clock gating is overridden (Clock gating is disabled).
 *  0b0..Automatic clock gating is not overridden.
 */
#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_MASK)

#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_MASK    (0x2000U)
#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_SHIFT   (13U)
/*! SDMA1 - Control automatic clock gating of DMA1 controller.
 *  0b1..Automatic clock gating is overridden (Clock gating is disabled).
 *  0b0..Automatic clock gating is not overridden.
 */
#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_MASK)

#define SYSCON_AUTOCLKGATEOVERRIDE_USB0_MASK     (0x4000U)
#define SYSCON_AUTOCLKGATEOVERRIDE_USB0_SHIFT    (14U)
/*! USB0 - Control automatic clock gating of USB controller.
 *  0b1..Automatic clock gating is overridden (Clock gating is disabled).
 *  0b0..Automatic clock gating is not overridden.
 */
#define SYSCON_AUTOCLKGATEOVERRIDE_USB0(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_USB0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_USB0_MASK)

#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_MASK   (0x8000U)
#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_SHIFT  (15U)
/*! SYSCON - Control automatic clock gating of synchronous system controller registers bank.
 *  0b1..Automatic clock gating is overridden (Clock gating is disabled).
 *  0b0..Automatic clock gating is not overridden.
 */
#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_MASK)

#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_MASK (0xFFFF0000U)
#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_SHIFT (16U)
/*! ENABLEUPDATE - The value 0xC0DE must be written for AUTOCLKGATEOVERRIDE registers fields updates to have effect.
 *  0b1100000011011110..Bit Fields 0 - 15 of this register are updated
 *  0b0000000000000000..Bit Fields 0 - 15 of this register are not updated
 */
#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_MASK)
/*! @} */

/*! @name GPIOPSYNC - GPIO Synchronization */
/*! @{ */

#define SYSCON_GPIOPSYNC_PSYNC_MASK              (0x1U)
#define SYSCON_GPIOPSYNC_PSYNC_SHIFT             (0U)
/*! PSYNC - Enable bypass of the first stage of synchronization inside GPIO_INT module.
 *  0b1..Bypass of the first stage of synchronization inside GPIO_INT module.
 *  0b0..Use the first stage of synchronization inside GPIO_INT module.
 */
#define SYSCON_GPIOPSYNC_PSYNC(x)                (((uint32_t)(((uint32_t)(x)) << SYSCON_GPIOPSYNC_PSYNC_SHIFT)) & SYSCON_GPIOPSYNC_PSYNC_MASK)
/*! @} */

/*! @name AUTOCLKGATEOVERRIDE1 - Control automatic clock gating */
/*! @{ */

#define SYSCON_AUTOCLKGATEOVERRIDE1_DAC0_MASK    (0x1U)
#define SYSCON_AUTOCLKGATEOVERRIDE1_DAC0_SHIFT   (0U)
/*! DAC0 - DAC0
 */
#define SYSCON_AUTOCLKGATEOVERRIDE1_DAC0(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE1_DAC0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE1_DAC0_MASK)

#define SYSCON_AUTOCLKGATEOVERRIDE1_DAC1_MASK    (0x2U)
#define SYSCON_AUTOCLKGATEOVERRIDE1_DAC1_SHIFT   (1U)
/*! DAC1 - DAC1
 */
#define SYSCON_AUTOCLKGATEOVERRIDE1_DAC1(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE1_DAC1_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE1_DAC1_MASK)

#define SYSCON_AUTOCLKGATEOVERRIDE1_DAC2_MASK    (0x4U)
#define SYSCON_AUTOCLKGATEOVERRIDE1_DAC2_SHIFT   (2U)
/*! DAC2 - DAC2
 */
#define SYSCON_AUTOCLKGATEOVERRIDE1_DAC2(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE1_DAC2_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE1_DAC2_MASK)

#define SYSCON_AUTOCLKGATEOVERRIDE1_OPAMP0_MASK  (0x8U)
#define SYSCON_AUTOCLKGATEOVERRIDE1_OPAMP0_SHIFT (3U)
/*! OPAMP0 - OPAMP0
 */
#define SYSCON_AUTOCLKGATEOVERRIDE1_OPAMP0(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE1_OPAMP0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE1_OPAMP0_MASK)

#define SYSCON_AUTOCLKGATEOVERRIDE1_OPAMP1_MASK  (0x10U)
#define SYSCON_AUTOCLKGATEOVERRIDE1_OPAMP1_SHIFT (4U)
/*! OPAMP1 - OPAMP1
 */
#define SYSCON_AUTOCLKGATEOVERRIDE1_OPAMP1(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE1_OPAMP1_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE1_OPAMP1_MASK)

#define SYSCON_AUTOCLKGATEOVERRIDE1_OPAMP2_MASK  (0x20U)
#define SYSCON_AUTOCLKGATEOVERRIDE1_OPAMP2_SHIFT (5U)
/*! OPAMP2 - OPAMP2
 */
#define SYSCON_AUTOCLKGATEOVERRIDE1_OPAMP2(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE1_OPAMP2_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE1_OPAMP2_MASK)

#define SYSCON_AUTOCLKGATEOVERRIDE1_HSCMP0_MASK  (0x40U)
#define SYSCON_AUTOCLKGATEOVERRIDE1_HSCMP0_SHIFT (6U)
/*! HSCMP0 - HSCMP0
 */
#define SYSCON_AUTOCLKGATEOVERRIDE1_HSCMP0(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE1_HSCMP0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE1_HSCMP0_MASK)

#define SYSCON_AUTOCLKGATEOVERRIDE1_HSCMP1_MASK  (0x80U)
#define SYSCON_AUTOCLKGATEOVERRIDE1_HSCMP1_SHIFT (7U)
/*! HSCMP1 - HSCMP0
 */
#define SYSCON_AUTOCLKGATEOVERRIDE1_HSCMP1(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE1_HSCMP1_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE1_HSCMP1_MASK)

#define SYSCON_AUTOCLKGATEOVERRIDE1_HSCMP2_MASK  (0x100U)
#define SYSCON_AUTOCLKGATEOVERRIDE1_HSCMP2_SHIFT (8U)
/*! HSCMP2 - HSCMP2
 */
#define SYSCON_AUTOCLKGATEOVERRIDE1_HSCMP2(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE1_HSCMP2_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE1_HSCMP2_MASK)

#define SYSCON_AUTOCLKGATEOVERRIDE1_VREF_MASK    (0x200U)
#define SYSCON_AUTOCLKGATEOVERRIDE1_VREF_SHIFT   (9U)
/*! VREF - VREF
 */
#define SYSCON_AUTOCLKGATEOVERRIDE1_VREF(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE1_VREF_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE1_VREF_MASK)

#define SYSCON_AUTOCLKGATEOVERRIDE1_PWM0_MASK    (0x400U)
#define SYSCON_AUTOCLKGATEOVERRIDE1_PWM0_SHIFT   (10U)
/*! PWM0 - PWM0
 */
#define SYSCON_AUTOCLKGATEOVERRIDE1_PWM0(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE1_PWM0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE1_PWM0_MASK)

#define SYSCON_AUTOCLKGATEOVERRIDE1_PWM1_MASK    (0x800U)
#define SYSCON_AUTOCLKGATEOVERRIDE1_PWM1_SHIFT   (11U)
/*! PWM1 - PWM1
 */
#define SYSCON_AUTOCLKGATEOVERRIDE1_PWM1(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE1_PWM1_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE1_PWM1_MASK)
/*! @} */

/*! @name ENABLE_MEM_PARITY_ECC_CHECK - Memory parity ECC enable */
/*! @{ */

#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAMx_MASK (0x1U)
#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAMx_SHIFT (0U)
/*! ENABLE_RAMx - Enable RAMx parity error check
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAMx(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAMx_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAMx_MASK)

#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM00_MASK (0x2U)
#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM00_SHIFT (1U)
/*! ENABLE_RAM00 - Enable RAM00 parity error check
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM00(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM00_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM00_MASK)

#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM01_MASK (0x4U)
#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM01_SHIFT (2U)
/*! ENABLE_RAM01 - Enable RAM01 parity error check
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM01(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM01_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM01_MASK)

#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAMx02_MASK (0x8U)
#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAMx02_SHIFT (3U)
/*! ENABLE_RAMx02 - Enable RAMx02 parity error check
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAMx02(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAMx02_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAMx02_MASK)

#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM03_MASK (0x10U)
#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM03_SHIFT (4U)
/*! ENABLE_RAM03 - Enable RAM03 parity error check
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM03(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM03_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM03_MASK)

#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM1_MBIT_MASK (0x20U)
#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM1_MBIT_SHIFT (5U)
/*! ENABLE_RAM1_MBIT - Enable RAM1 ECC mbit error check
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM1_MBIT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM1_MBIT_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM1_MBIT_MASK)

#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM1_SBIT_MASK (0x40U)
#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM1_SBIT_SHIFT (6U)
/*! ENABLE_RAM1_SBIT - Enable RAM1 ECC sbit error check
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM1_SBIT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM1_SBIT_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM1_SBIT_MASK)

#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM2_MASK (0x80U)
#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM2_SHIFT (7U)
/*! ENABLE_RAM2 - Enable RAM2 parity error check
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM2_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM2_MASK)

#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM3_MASK (0x100U)
#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM3_SHIFT (8U)
/*! ENABLE_RAM3 - Enable RAM3 parity error check
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM3_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM3_MASK)

#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM40_MASK (0x200U)
#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM40_SHIFT (9U)
/*! ENABLE_RAM40 - Enable RAM40 parity error check
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM40(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM40_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM40_MASK)

#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM41_MASK (0x400U)
#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM41_SHIFT (10U)
/*! ENABLE_RAM41 - Enable RAM41 parity error check
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM41(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM41_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM41_MASK)

#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM42_MASK (0x800U)
#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM42_SHIFT (11U)
/*! ENABLE_RAM42 - Enable RAM42 parity error check
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM42(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM42_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM42_MASK)

#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM43_MASK (0x1000U)
#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM43_SHIFT (12U)
/*! ENABLE_RAM43 - Enable RAM43 parity error check
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM43(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM43_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_ENABLE_RAM43_MASK)

#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMX_PARITY_ERROR_INTEN_MASK (0x100000U)
#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMX_PARITY_ERROR_INTEN_SHIFT (20U)
/*! RAMX_PARITY_ERROR_INTEN - Interrupt enable for RAMX parity error
 *  0b0..Disable.
 *  0b1..Enable RAM error interrupt when RAMX parity error status flag is set.
 */
#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMX_PARITY_ERROR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMX_PARITY_ERROR_INTEN_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMX_PARITY_ERROR_INTEN_MASK)

#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMA_PARITY_ERROR_INTEN_MASK (0x200000U)
#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMA_PARITY_ERROR_INTEN_SHIFT (21U)
/*! RAMA_PARITY_ERROR_INTEN - Interrupt enable for RAMA parity error
 *  0b0..Disable.
 *  0b1..Enable RAM error interrupt when RAMA parity error status flag is set.
 */
#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMA_PARITY_ERROR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMA_PARITY_ERROR_INTEN_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMA_PARITY_ERROR_INTEN_MASK)

#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMB_ECC_MBIT_ERROR_INTEN_MASK (0x400000U)
#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMB_ECC_MBIT_ERROR_INTEN_SHIFT (22U)
/*! RAMB_ECC_MBIT_ERROR_INTEN - Interrupt enable for RAMB ECC mbit_err
 *  0b0..Disable.
 *  0b1..Enable RAM error interrupt when RAMB ECC mbit_err status flag is set.
 */
#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMB_ECC_MBIT_ERROR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMB_ECC_MBIT_ERROR_INTEN_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMB_ECC_MBIT_ERROR_INTEN_MASK)

#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMB_ECC_SBIT_ERROR_INTEN_MASK (0x800000U)
#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMB_ECC_SBIT_ERROR_INTEN_SHIFT (23U)
/*! RAMB_ECC_SBIT_ERROR_INTEN - Interrupt enable for RAMB ECC sbit_err
 *  0b0..Disable.
 *  0b1..Enable RAM error interrupt when RAMB ECC sbit_err status flag is set.
 */
#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMB_ECC_SBIT_ERROR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMB_ECC_SBIT_ERROR_INTEN_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMB_ECC_SBIT_ERROR_INTEN_MASK)

#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMC_PARITY_ERROR_INTEN_MASK (0x1000000U)
#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMC_PARITY_ERROR_INTEN_SHIFT (24U)
/*! RAMC_PARITY_ERROR_INTEN - Interrupt enable for RAMC parity error
 *  0b0..Disable.
 *  0b1..Enable RAM error interrupt when RAMC parity error status flag is set.
 */
#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMC_PARITY_ERROR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMC_PARITY_ERROR_INTEN_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMC_PARITY_ERROR_INTEN_MASK)

#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMD_PARITY_ERROR_INTEN_MASK (0x2000000U)
#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMD_PARITY_ERROR_INTEN_SHIFT (25U)
/*! RAMD_PARITY_ERROR_INTEN - Interrupt enable for RAMD parity error
 *  0b0..Disable.
 *  0b1..Enable RAM error interrupt when RAMD parity error status flag is set.
 */
#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMD_PARITY_ERROR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMD_PARITY_ERROR_INTEN_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAMD_PARITY_ERROR_INTEN_MASK)

#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAME_PARITY_ERROR_INTEN_MASK (0x4000000U)
#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAME_PARITY_ERROR_INTEN_SHIFT (26U)
/*! RAME_PARITY_ERROR_INTEN - Interrupt enable for RAME parity error
 *  0b0..Disable.
 *  0b1..Enable RAM error interrupt when RAME parity error status flag is set.
 */
#define SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAME_PARITY_ERROR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAME_PARITY_ERROR_INTEN_SHIFT)) & SYSCON_ENABLE_MEM_PARITY_ECC_CHECK_RAME_PARITY_ERROR_INTEN_MASK)
/*! @} */

/*! @name MEM_PARITY_ECC_ERROR_FLAG - Memory parity ECC error flag */
/*! @{ */

#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAMX_PARITY_ERROR_MASK (0x1U)
#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAMX_PARITY_ERROR_SHIFT (0U)
/*! RAMX_PARITY_ERROR - RAMx parity error detected
 *  0b0..No error detected
 *  0b1..Error detected
 */
#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAMX_PARITY_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAMX_PARITY_ERROR_SHIFT)) & SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAMX_PARITY_ERROR_MASK)

#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM0_PARITY_ERROR_MASK (0x2U)
#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM0_PARITY_ERROR_SHIFT (1U)
/*! RAM0_PARITY_ERROR - RAM0 parity error detected
 *  0b0..No error detected
 *  0b1..Error detected
 */
#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM0_PARITY_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM0_PARITY_ERROR_SHIFT)) & SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM0_PARITY_ERROR_MASK)

#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM1_ECC_MBIT_ERROR_MASK (0x4U)
#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM1_ECC_MBIT_ERROR_SHIFT (2U)
/*! RAM1_ECC_MBIT_ERROR - RAM1 ECC mbit error detected
 *  0b0..No error detected
 *  0b1..Error detected
 */
#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM1_ECC_MBIT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM1_ECC_MBIT_ERROR_SHIFT)) & SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM1_ECC_MBIT_ERROR_MASK)

#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM1_ECC_SBIT_ERROR_MASK (0x8U)
#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM1_ECC_SBIT_ERROR_SHIFT (3U)
/*! RAM1_ECC_SBIT_ERROR - RAM1 ECC sbit error detected
 *  0b0..No error detected
 *  0b1..Error detected
 */
#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM1_ECC_SBIT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM1_ECC_SBIT_ERROR_SHIFT)) & SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM1_ECC_SBIT_ERROR_MASK)

#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM2_PARITY_ERROR_MASK (0x10U)
#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM2_PARITY_ERROR_SHIFT (4U)
/*! RAM2_PARITY_ERROR - RAM2 parity error detected
 *  0b0..No error detected
 *  0b1..Error detected
 */
#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM2_PARITY_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM2_PARITY_ERROR_SHIFT)) & SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM2_PARITY_ERROR_MASK)

#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM3_PARITY_ERROR_MASK (0x20U)
#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM3_PARITY_ERROR_SHIFT (5U)
/*! RAM3_PARITY_ERROR - RAM3 parity error detected
 *  0b0..No error detected
 *  0b1..Error detected
 */
#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM3_PARITY_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM3_PARITY_ERROR_SHIFT)) & SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM3_PARITY_ERROR_MASK)

#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM4_PARITY_ERROR_MASK (0x40U)
#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM4_PARITY_ERROR_SHIFT (6U)
/*! RAM4_PARITY_ERROR - RAM4 parity error detected
 *  0b0..No error detected
 *  0b1..Error detected
 */
#define SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM4_PARITY_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM4_PARITY_ERROR_SHIFT)) & SYSCON_MEM_PARITY_ECC_ERROR_FLAG_RAM4_PARITY_ERROR_MASK)
/*! @} */

/*! @name PWM0SUBCTL - PWM0 submodule control */
/*! @{ */

#define SYSCON_PWM0SUBCTL_CLK0_EN_MASK           (0x1U)
#define SYSCON_PWM0SUBCTL_CLK0_EN_SHIFT          (0U)
/*! CLK0_EN - PWM0 SUB Clock0 enable
 */
#define SYSCON_PWM0SUBCTL_CLK0_EN(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_CLK0_EN_SHIFT)) & SYSCON_PWM0SUBCTL_CLK0_EN_MASK)

#define SYSCON_PWM0SUBCTL_CLK1_EN_MASK           (0x2U)
#define SYSCON_PWM0SUBCTL_CLK1_EN_SHIFT          (1U)
/*! CLK1_EN - PWM0 SUB Clock1 enable
 */
#define SYSCON_PWM0SUBCTL_CLK1_EN(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_CLK1_EN_SHIFT)) & SYSCON_PWM0SUBCTL_CLK1_EN_MASK)

#define SYSCON_PWM0SUBCTL_CLK2_EN_MASK           (0x4U)
#define SYSCON_PWM0SUBCTL_CLK2_EN_SHIFT          (2U)
/*! CLK2_EN - PWM0 SUB Clock2 enable
 */
#define SYSCON_PWM0SUBCTL_CLK2_EN(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_CLK2_EN_SHIFT)) & SYSCON_PWM0SUBCTL_CLK2_EN_MASK)

#define SYSCON_PWM0SUBCTL_CLK3_EN_MASK           (0x8U)
#define SYSCON_PWM0SUBCTL_CLK3_EN_SHIFT          (3U)
/*! CLK3_EN - PWM0 SUB Clock3 enable
 */
#define SYSCON_PWM0SUBCTL_CLK3_EN(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_CLK3_EN_SHIFT)) & SYSCON_PWM0SUBCTL_CLK3_EN_MASK)

#define SYSCON_PWM0SUBCTL_DMAVALM0_MASK          (0x1000U)
#define SYSCON_PWM0SUBCTL_DMAVALM0_SHIFT         (12U)
/*! DMAVALM0 - PWM0 submodule 0 DMA Compare Value Done Mask
 */
#define SYSCON_PWM0SUBCTL_DMAVALM0(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_DMAVALM0_SHIFT)) & SYSCON_PWM0SUBCTL_DMAVALM0_MASK)

#define SYSCON_PWM0SUBCTL_DMAVALM1_MASK          (0x2000U)
#define SYSCON_PWM0SUBCTL_DMAVALM1_SHIFT         (13U)
/*! DMAVALM1 - PWM0 submodule 1 DMA Compare Value Done Mask
 */
#define SYSCON_PWM0SUBCTL_DMAVALM1(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_DMAVALM1_SHIFT)) & SYSCON_PWM0SUBCTL_DMAVALM1_MASK)

#define SYSCON_PWM0SUBCTL_DMAVALM2_MASK          (0x4000U)
#define SYSCON_PWM0SUBCTL_DMAVALM2_SHIFT         (14U)
/*! DMAVALM2 - PWM0 submodule 2 DMA Compare Value Done Mask
 */
#define SYSCON_PWM0SUBCTL_DMAVALM2(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_DMAVALM2_SHIFT)) & SYSCON_PWM0SUBCTL_DMAVALM2_MASK)

#define SYSCON_PWM0SUBCTL_DMAVALM3_MASK          (0x8000U)
#define SYSCON_PWM0SUBCTL_DMAVALM3_SHIFT         (15U)
/*! DMAVALM3 - PWM0 submodule 3 DMA Compare Value Done Mask
 */
#define SYSCON_PWM0SUBCTL_DMAVALM3(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_DMAVALM3_SHIFT)) & SYSCON_PWM0SUBCTL_DMAVALM3_MASK)
/*! @} */

/*! @name PWM1SUBCTL - PWM1 submodule control */
/*! @{ */

#define SYSCON_PWM1SUBCTL_CLK0_EN_MASK           (0x1U)
#define SYSCON_PWM1SUBCTL_CLK0_EN_SHIFT          (0U)
/*! CLK0_EN - PWM1 SUB Clock0 enable
 */
#define SYSCON_PWM1SUBCTL_CLK0_EN(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_CLK0_EN_SHIFT)) & SYSCON_PWM1SUBCTL_CLK0_EN_MASK)

#define SYSCON_PWM1SUBCTL_CLK1_EN_MASK           (0x2U)
#define SYSCON_PWM1SUBCTL_CLK1_EN_SHIFT          (1U)
/*! CLK1_EN - PWM1 SUB Clock1 enable
 */
#define SYSCON_PWM1SUBCTL_CLK1_EN(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_CLK1_EN_SHIFT)) & SYSCON_PWM1SUBCTL_CLK1_EN_MASK)

#define SYSCON_PWM1SUBCTL_CLK2_EN_MASK           (0x4U)
#define SYSCON_PWM1SUBCTL_CLK2_EN_SHIFT          (2U)
/*! CLK2_EN - PWM1 SUB Clock2 enable
 */
#define SYSCON_PWM1SUBCTL_CLK2_EN(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_CLK2_EN_SHIFT)) & SYSCON_PWM1SUBCTL_CLK2_EN_MASK)

#define SYSCON_PWM1SUBCTL_CLK3_EN_MASK           (0x8U)
#define SYSCON_PWM1SUBCTL_CLK3_EN_SHIFT          (3U)
/*! CLK3_EN - PWM1 SUB Clock3 enable
 */
#define SYSCON_PWM1SUBCTL_CLK3_EN(x)             (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_CLK3_EN_SHIFT)) & SYSCON_PWM1SUBCTL_CLK3_EN_MASK)

#define SYSCON_PWM1SUBCTL_DMAVALM0_MASK          (0x1000U)
#define SYSCON_PWM1SUBCTL_DMAVALM0_SHIFT         (12U)
/*! DMAVALM0 - PWM1 submodule 0 DMA Compare Value Done Mask
 */
#define SYSCON_PWM1SUBCTL_DMAVALM0(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_DMAVALM0_SHIFT)) & SYSCON_PWM1SUBCTL_DMAVALM0_MASK)

#define SYSCON_PWM1SUBCTL_DMAVALM1_MASK          (0x2000U)
#define SYSCON_PWM1SUBCTL_DMAVALM1_SHIFT         (13U)
/*! DMAVALM1 - PWM1 submodule 1 DMA Compare Value Done Mask
 */
#define SYSCON_PWM1SUBCTL_DMAVALM1(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_DMAVALM1_SHIFT)) & SYSCON_PWM1SUBCTL_DMAVALM1_MASK)

#define SYSCON_PWM1SUBCTL_DMAVALM2_MASK          (0x4000U)
#define SYSCON_PWM1SUBCTL_DMAVALM2_SHIFT         (14U)
/*! DMAVALM2 - PWM1 submodule 2 DMA Compare Value Done Mask
 */
#define SYSCON_PWM1SUBCTL_DMAVALM2(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_DMAVALM2_SHIFT)) & SYSCON_PWM1SUBCTL_DMAVALM2_MASK)

#define SYSCON_PWM1SUBCTL_DMAVALM3_MASK          (0x8000U)
#define SYSCON_PWM1SUBCTL_DMAVALM3_SHIFT         (15U)
/*! DMAVALM3 - PWM1 submodule 3 DMA Compare Value Done Mask
 */
#define SYSCON_PWM1SUBCTL_DMAVALM3(x)            (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_DMAVALM3_SHIFT)) & SYSCON_PWM1SUBCTL_DMAVALM3_MASK)
/*! @} */

/*! @name CTIMERGLOBALSTARTEN - CTIMER global start enable */
/*! @{ */

#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_MASK (0x1U)
#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_SHIFT (0U)
/*! CTIMER0_CLK_EN - CTIMER0 function clock enable
 */
#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_MASK)

#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_MASK (0x2U)
#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_SHIFT (1U)
/*! CTIMER1_CLK_EN - CTIMER1 function clock enable
 */
#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_MASK)

#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_MASK (0x4U)
#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_SHIFT (2U)
/*! CTIMER2_CLK_EN - CTIMER2 function clock enable
 */
#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_MASK)

#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN_MASK (0x8U)
#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN_SHIFT (3U)
/*! CTIMER3_CLK_EN - CTIMER3 function clock enable
 */
#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN_MASK)

#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN_MASK (0x10U)
#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN_SHIFT (4U)
/*! CTIMER4_CLK_EN - CTIMER4 function clock enable
 */
#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN_MASK)
/*! @} */

/*! @name DEBUG_LOCK_EN - Control write access to security */
/*! @{ */

#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK       (0xFU)
#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT      (0U)
/*! LOCK_ALL - Control write access to security registers.
 *  0b1010..1010: Enable write access to all registers.
 *  0b0000..Any other value than b1010: disable write access to all registers.
 */
#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL(x)         (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT)) & SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK)
/*! @} */

/*! @name DEBUG_FEATURES - Cortex debug features control */
/*! @{ */

#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK    (0x3U)
#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT   (0U)
/*! CPU0_DBGEN - CPU0 Invasive Debug Control
 *  0b01..Disable debug
 *  0b10..Enable debug
 */
#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK)

#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK    (0xCU)
#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT   (2U)
/*! CPU0_NIDEN - CPU0 Non Invasive Debug Control
 *  0b01..Disable debug
 *  0b10..Enable debug
 */
#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN(x)      (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK)

#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_MASK   (0x30U)
#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_SHIFT  (4U)
/*! CPU0_SPIDEN - CPU0 Secure Privileged Invasive Debug Control
 *  0b01..Disable debug
 *  0b10..Enable debug
 */
#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN(x)     (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_MASK)

#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_MASK  (0xC0U)
#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_SHIFT (6U)
/*! CPU0_SPNIDEN - CPU0 Secure Privileged Non Invasive Debug Control
 *  0b01..Disable debug
 *  0b10..Enable debug
 */
#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN(x)    (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_MASK)
/*! @} */

/*! @name DEBUG_FEATURES_DP - Cortex debug features control (duplicate) */
/*! @{ */

#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK (0x3U)
#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT (0U)
/*! CPU0_DBGEN - CPU0 Invasive Debug Control
 *  0b01..Disable debug
 *  0b10..Enable debug
 */
#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK)

#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK (0xCU)
#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT (2U)
/*! CPU0_NIDEN - CPU0 Non Invasive Debug Control
 *  0b01..Disable debug
 *  0b10..Enable debug
 */
#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN(x)   (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK)

#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_MASK (0x30U)
#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_SHIFT (4U)
/*! CPU0_SPIDEN - CPU0 Secure Privileged Invasive Debug Control
 *  0b01..Disable debug
 *  0b10..Enable debug
 */
#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN(x)  (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_MASK)

#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_MASK (0xC0U)
#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_SHIFT (6U)
/*! CPU0_SPNIDEN - CPU0 Secure Privileged Non Invasive Debug Control
 *  0b01..Disable debug
 *  0b10..Enable debug
 */
#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_MASK)
/*! @} */

/*! @name SWD_ACCESS_CPU - CPU0 Software Debug Access */
/*! @{ */

#define SYSCON_SWD_ACCESS_CPU_SEC_CODE_MASK      (0xFFFFFFFFU)
#define SYSCON_SWD_ACCESS_CPU_SEC_CODE_SHIFT     (0U)
/*! SEC_CODE - CPU0 SWD-AP: 0x12345678.
 *  0b00010010001101000101011001111000..Value to write to enable CPU0 SWD access. Reading back register will be read as 0xA.
 *  0b00000000000000000000000000000000..CPU0 DAP is not allowed. Reading back register will be read as 0x5.
 */
#define SYSCON_SWD_ACCESS_CPU_SEC_CODE(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_SWD_ACCESS_CPU_SEC_CODE_SHIFT)) & SYSCON_SWD_ACCESS_CPU_SEC_CODE_MASK)
/*! @} */

/* The count of SYSCON_SWD_ACCESS_CPU */
#define SYSCON_SWD_ACCESS_CPU_COUNT              (1U)

/*! @name DEBUG_AUTH_BEACON - Debug authentication BEACON */
/*! @{ */

#define SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK     (0xFFFFFFFFU)
#define SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT    (0U)
/*! BEACON - Set by the debug authentication code in ROM to pass the debug beacons (Credential
 *    Beacon and Authentication Beacon) to application code.
 */
#define SYSCON_DEBUG_AUTH_BEACON_BEACON(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT)) & SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK)
/*! @} */

/*! @name SWD_ACCESS_DSP - DSP Software Debug Access */
/*! @{ */

#define SYSCON_SWD_ACCESS_DSP_SEC_CODE_MASK      (0xFFFFFFFFU)
#define SYSCON_SWD_ACCESS_DSP_SEC_CODE_SHIFT     (0U)
/*! SEC_CODE - DSP SWD-AP: 0x12345678.
 *  0b00010010001101000101011001111000..Value to write to enable DSP SWD access. Reading back register will be read as 0xA.
 *  0b00000000000000000000000000000000..DSP DAP is not allowed. Reading back register will be read as 0x5.
 */
#define SYSCON_SWD_ACCESS_DSP_SEC_CODE(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_SWD_ACCESS_DSP_SEC_CODE_SHIFT)) & SYSCON_SWD_ACCESS_DSP_SEC_CODE_MASK)
/*! @} */

/*! @name DEVICE_ID0 - Device ID */
/*! @{ */

#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK     (0xF00000U)
#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT    (20U)
/*! ROM_REV_MINOR - ROM revision.
 */
#define SYSCON_DEVICE_ID0_ROM_REV_MINOR(x)       (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT)) & SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK)
/*! @} */

/*! @name DIEID - Chip revision ID and Number */
/*! @{ */

#define SYSCON_DIEID_REV_ID_MASK                 (0xFU)
#define SYSCON_DIEID_REV_ID_SHIFT                (0U)
/*! REV_ID - Chip Metal Revision ID.
 */
#define SYSCON_DIEID_REV_ID(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_REV_ID_SHIFT)) & SYSCON_DIEID_REV_ID_MASK)

#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK      (0xFFFFF0U)
#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT     (4U)
/*! MCO_NUM_IN_DIE_ID - Chip Number 0x426B.
 */
#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID(x)        (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT)) & SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group SYSCON_Register_Masks */


/* SYSCON - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral SYSCON base address */
  #define SYSCON_BASE                              (0x50000000u)
  /** Peripheral SYSCON base address */
  #define SYSCON_BASE_NS                           (0x40000000u)
  /** Peripheral SYSCON base pointer */
  #define SYSCON                                   ((SYSCON_Type *)SYSCON_BASE)
  /** Peripheral SYSCON base pointer */
  #define SYSCON_NS                                ((SYSCON_Type *)SYSCON_BASE_NS)
  /** Array initializer of SYSCON peripheral base addresses */
  #define SYSCON_BASE_ADDRS                        { SYSCON_BASE }
  /** Array initializer of SYSCON peripheral base pointers */
  #define SYSCON_BASE_PTRS                         { SYSCON }
  /** Array initializer of SYSCON peripheral base addresses */
  #define SYSCON_BASE_ADDRS_NS                     { SYSCON_BASE_NS }
  /** Array initializer of SYSCON peripheral base pointers */
  #define SYSCON_BASE_PTRS_NS                      { SYSCON_NS }
#else
  /** Peripheral SYSCON base address */
  #define SYSCON_BASE                              (0x40000000u)
  /** Peripheral SYSCON base pointer */
  #define SYSCON                                   ((SYSCON_Type *)SYSCON_BASE)
  /** Array initializer of SYSCON peripheral base addresses */
  #define SYSCON_BASE_ADDRS                        { SYSCON_BASE }
  /** Array initializer of SYSCON peripheral base pointers */
  #define SYSCON_BASE_PTRS                         { SYSCON }
#endif

/*!
 * @}
 */ /* end of group SYSCON_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- SYSCTL Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SYSCTL_Peripheral_Access_Layer SYSCTL Peripheral Access Layer
 * @{
 */

/** SYSCTL - Register Layout Typedef */
typedef struct {
  __IO uint32_t UPDATELCKOUT;                      /**< Write Lock Out, offset: 0x0 */
       uint8_t RESERVED_0[60];
  __IO uint32_t FCCTRLSEL[8];                      /**< Shared Signal Select for Flexcomm 0..Shared Signal Select for Flexcomm 7, array offset: 0x40, array step: 0x4 */
       uint8_t RESERVED_1[32];
  __IO uint32_t SHAREDCTRLSET[2];                  /**< Shared Signal Set 0..Shared Signal Set 1, array offset: 0x80, array step: 0x4 */
       uint8_t RESERVED_2[248];
  __IO uint32_t CODE_GRAY_LSB;                     /**< Gray Code LSB Input, offset: 0x180 */
  __IO uint32_t CODE_GRAY_MSB;                     /**< Gray Code MSB Input, offset: 0x184 */
  __I  uint32_t CODE_BIN_LSB;                      /**< Binary Code LSB Input, offset: 0x188 */
  __I  uint32_t CODE_BIN_MSB;                      /**< Binary Code MSB Input, offset: 0x18C */
} SYSCTL_Type;

/* ----------------------------------------------------------------------------
   -- SYSCTL Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SYSCTL_Register_Masks SYSCTL Register Masks
 * @{
 */

/*! @name UPDATELCKOUT - Write Lock Out */
/*! @{ */

#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK    (0x1U)
#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT_SHIFT   (0U)
/*! UPDATELCKOUT - Lock Out
 *  0b0..Normal Mode: Allow writes to all registers.
 *  0b1..Protected Mode: Do not allow writes to all registers except UPDATELCKOUT.
 */
#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL_UPDATELCKOUT_UPDATELCKOUT_SHIFT)) & SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK)
/*! @} */

/*! @name FCCTRLSEL - Shared Signal Select for Flexcomm 0..Shared Signal Select for Flexcomm 7 */
/*! @{ */

#define SYSCTL_FCCTRLSEL_SCKINSEL_MASK           (0x3U)
#define SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT          (0U)
/*! SCKINSEL - SCK Input Select
 *  0b00..Selects the dedicated FCn_SCK signal
 *  0b01..Selects from shared signal set 0 (SHAREDCTRLSET0)
 *  0b10..Selects from shared signal set 1 (SHAREDCTRLSET1)
 *  0b11..Reserved
 */
#define SYSCTL_FCCTRLSEL_SCKINSEL(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_SCKINSEL_MASK)

#define SYSCTL_FCCTRLSEL_WSINSEL_MASK            (0x300U)
#define SYSCTL_FCCTRLSEL_WSINSEL_SHIFT           (8U)
/*! WSINSEL - WS Input Select
 *  0b00..Selects the dedicated FCn_TXD_SCL_MISO_WS signal
 *  0b01..Selects from shared signal set 0 (SHAREDCTRLSET0)
 *  0b10..Selects from shared signal set 1 (SHAREDCTRLSET1)
 *  0b11..Reserved
 */
#define SYSCTL_FCCTRLSEL_WSINSEL(x)              (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_WSINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_WSINSEL_MASK)

#define SYSCTL_FCCTRLSEL_DATAINSEL_MASK          (0x30000U)
#define SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT         (16U)
/*! DATAINSEL - DATA Input Select
 *  0b00..Selects the dedicated FCn_RXD_SDA_MOSI_DATA input
 *  0b01..Selects from shared signal set 0 (SHAREDCTRLSET0)
 *  0b10..Selects from shared signal set 1 (SHAREDCTRLSET1)
 *  0b11..Reserved
 */
#define SYSCTL_FCCTRLSEL_DATAINSEL(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_DATAINSEL_MASK)

#define SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK         (0x3000000U)
#define SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT        (24U)
/*! DATAOUTSEL - DATA Output Select
 *  0b00..Selects the dedicated FCn_RXD_SDA_MOSI_DATA output
 *  0b01..Selects from shared signal set 0 (SHAREDCTRLSET0)
 *  0b10..Selects from shared signal set 1 (SHAREDCTRLSET1)
 *  0b11..Reserved
 */
#define SYSCTL_FCCTRLSEL_DATAOUTSEL(x)           (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT)) & SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK)
/*! @} */

/* The count of SYSCTL_FCCTRLSEL */
#define SYSCTL_FCCTRLSEL_COUNT                   (8U)

/*! @name SHAREDCTRLSET - Shared Signal Set 0..Shared Signal Set 1 */
/*! @{ */

#define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK   (0x7U)
#define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT  (0U)
/*! SHAREDSCKSEL - SCK Source Select
 *  0b000..Flexcomm 0
 *  0b001..Flexcomm 1
 *  0b010..Flexcomm 2
 *  0b011..Reserved
 *  0b100..Flexcomm 4
 *  0b101..Flexcomm 5
 *  0b110..Flexcomm 6
 *  0b111..Flexcomm 7
 */
#define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK)

#define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_MASK    (0x70U)
#define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_SHIFT   (4U)
/*! SHAREDWSSEL - WS Source Select
 *  0b000..Flexcomm 0
 *  0b001..Flexcomm 1
 *  0b010..Flexcomm 2
 *  0b011..Reserved
 *  0b100..Flexcomm 4
 *  0b101..Flexcomm 5
 *  0b110..Flexcomm 6
 *  0b111..Flexcomm 7
 */
#define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_MASK)

#define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_MASK  (0x700U)
#define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_SHIFT (8U)
/*! SHAREDDATASEL - DATA Input Source Select
 *  0b000..Flexcomm 0
 *  0b001..Flexcomm 1
 *  0b010..Flexcomm 2
 *  0b011..Reserved
 *  0b100..Flexcomm 4
 *  0b101..Flexcomm 5
 *  0b110..Flexcomm 6
 *  0b111..Flexcomm 7
 */
#define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_MASK)

#define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK   (0x10000U)
#define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT  (16U)
/*! FC0DATAOUTEN - DATAOUT Enable for Flexcomm 0
 *  0b0..Does not contribute
 *  0b1..Contributes
 */
#define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK)

#define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK   (0x20000U)
#define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT  (17U)
/*! FC1DATAOUTEN - DATAOUT Enable for Flexcomm 1
 *  0b0..Does not contribute
 *  0b1..Contributes
 */
#define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK)

#define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK   (0x40000U)
#define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_SHIFT  (18U)
/*! FC2DATAOUTEN - DATAOUT Enable for Flexcomm 2
 *  0b0..Does not contribute
 *  0b1..Contributes
 */
#define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK)

#define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_MASK   (0x100000U)
#define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT  (20U)
/*! FC4DATAOUTEN - DATAOUT Enable for Flexcomm 4
 *  0b0..Does not contribute
 *  0b1..Contributes
 */
#define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_MASK)

#define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_MASK   (0x200000U)
#define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT  (21U)
/*! FC5DATAOUTEN - DATAOUT Enable for Flexcomm 5
 *  0b0..Does not contribute
 *  0b1..Contributes
 */
#define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_MASK)

#define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK   (0x400000U)
#define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT  (22U)
/*! FC6DATAOUTEN - DATAOUT Enable for Flexcomm 6
 *  0b0..Does not contribute
 *  0b1..Contributes
 */
#define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK)

#define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK   (0x800000U)
#define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT  (23U)
/*! FC7DATAOUTEN - DATAOUT Enable for Flexcomm 7
 *  0b0..Does not contribute
 *  0b1..Contributes
 */
#define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK)
/*! @} */

/* The count of SYSCTL_SHAREDCTRLSET */
#define SYSCTL_SHAREDCTRLSET_COUNT               (2U)

/*! @name CODE_GRAY_LSB - Gray Code LSB Input */
/*! @{ */

#define SYSCTL_CODE_GRAY_LSB_CODE_GRAY_LSB_MASK  (0xFFFFFFFFU)
#define SYSCTL_CODE_GRAY_LSB_CODE_GRAY_LSB_SHIFT (0U)
/*! CODE_GRAY_LSB - Gray code (least-significant)
 */
#define SYSCTL_CODE_GRAY_LSB_CODE_GRAY_LSB(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL_CODE_GRAY_LSB_CODE_GRAY_LSB_SHIFT)) & SYSCTL_CODE_GRAY_LSB_CODE_GRAY_LSB_MASK)
/*! @} */

/*! @name CODE_GRAY_MSB - Gray Code MSB Input */
/*! @{ */

#define SYSCTL_CODE_GRAY_MSB_CODE_GRAY_MSB_MASK  (0x3FFU)
#define SYSCTL_CODE_GRAY_MSB_CODE_GRAY_MSB_SHIFT (0U)
/*! CODE_GRAY_MSB - Gray code (most-significant)
 */
#define SYSCTL_CODE_GRAY_MSB_CODE_GRAY_MSB(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL_CODE_GRAY_MSB_CODE_GRAY_MSB_SHIFT)) & SYSCTL_CODE_GRAY_MSB_CODE_GRAY_MSB_MASK)
/*! @} */

/*! @name CODE_BIN_LSB - Binary Code LSB Input */
/*! @{ */

#define SYSCTL_CODE_BIN_LSB_CODE_BIN_LSB_MASK    (0xFFFFFFFFU)
#define SYSCTL_CODE_BIN_LSB_CODE_BIN_LSB_SHIFT   (0U)
/*! CODE_BIN_LSB - Binary converted code (least-significant)
 */
#define SYSCTL_CODE_BIN_LSB_CODE_BIN_LSB(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL_CODE_BIN_LSB_CODE_BIN_LSB_SHIFT)) & SYSCTL_CODE_BIN_LSB_CODE_BIN_LSB_MASK)
/*! @} */

/*! @name CODE_BIN_MSB - Binary Code MSB Input */
/*! @{ */

#define SYSCTL_CODE_BIN_MSB_CODE_BIN_MSB_MASK    (0x3FFU)
#define SYSCTL_CODE_BIN_MSB_CODE_BIN_MSB_SHIFT   (0U)
/*! CODE_BIN_MSB - Binary converted code (most-significant)
 */
#define SYSCTL_CODE_BIN_MSB_CODE_BIN_MSB(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL_CODE_BIN_MSB_CODE_BIN_MSB_SHIFT)) & SYSCTL_CODE_BIN_MSB_CODE_BIN_MSB_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group SYSCTL_Register_Masks */


/* SYSCTL - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral SYSCTL base address */
  #define SYSCTL_BASE                              (0x50023000u)
  /** Peripheral SYSCTL base address */
  #define SYSCTL_BASE_NS                           (0x40023000u)
  /** Peripheral SYSCTL base pointer */
  #define SYSCTL                                   ((SYSCTL_Type *)SYSCTL_BASE)
  /** Peripheral SYSCTL base pointer */
  #define SYSCTL_NS                                ((SYSCTL_Type *)SYSCTL_BASE_NS)
  /** Array initializer of SYSCTL peripheral base addresses */
  #define SYSCTL_BASE_ADDRS                        { SYSCTL_BASE }
  /** Array initializer of SYSCTL peripheral base pointers */
  #define SYSCTL_BASE_PTRS                         { SYSCTL }
  /** Array initializer of SYSCTL peripheral base addresses */
  #define SYSCTL_BASE_ADDRS_NS                     { SYSCTL_BASE_NS }
  /** Array initializer of SYSCTL peripheral base pointers */
  #define SYSCTL_BASE_PTRS_NS                      { SYSCTL_NS }
#else
  /** Peripheral SYSCTL base address */
  #define SYSCTL_BASE                              (0x40023000u)
  /** Peripheral SYSCTL base pointer */
  #define SYSCTL                                   ((SYSCTL_Type *)SYSCTL_BASE)
  /** Array initializer of SYSCTL peripheral base addresses */
  #define SYSCTL_BASE_ADDRS                        { SYSCTL_BASE }
  /** Array initializer of SYSCTL peripheral base pointers */
  #define SYSCTL_BASE_PTRS                         { SYSCTL }
#endif

/*!
 * @}
 */ /* end of group SYSCTL_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- USART Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup USART_Peripheral_Access_Layer USART Peripheral Access Layer
 * @{
 */

/** USART - Register Layout Typedef */
typedef struct {
  __IO uint32_t CFG;                               /**< USART Configuration, offset: 0x0 */
  __IO uint32_t CTL;                               /**< USART Control, offset: 0x4 */
  __IO uint32_t STAT;                              /**< USART Status, offset: 0x8 */
  __IO uint32_t INTENSET;                          /**< Interrupt Enable Read and Set for USART (not FIFO) Status, offset: 0xC */
  __O  uint32_t INTENCLR;                          /**< Interrupt Enable Clear, offset: 0x10 */
       uint8_t RESERVED_0[12];
  __IO uint32_t BRG;                               /**< Baud Rate Generator, offset: 0x20 */
  __I  uint32_t INTSTAT;                           /**< Interrupt Status, offset: 0x24 */
  __IO uint32_t OSR;                               /**< Oversample Selection Register for Asynchronous Communication, offset: 0x28 */
  __IO uint32_t ADDR;                              /**< Address Register for Automatic Address Matching, offset: 0x2C */
       uint8_t RESERVED_1[3536];
  __IO uint32_t FIFOCFG;                           /**< FIFO Configuration, offset: 0xE00 */
  __IO uint32_t FIFOSTAT;                          /**< FIFO Status, offset: 0xE04 */
  __IO uint32_t FIFOTRIG;                          /**< FIFO Trigger Settings for Interrupt and DMA Request, offset: 0xE08 */
       uint8_t RESERVED_2[4];
  __IO uint32_t FIFOINTENSET;                      /**< FIFO Interrupt Enable, offset: 0xE10 */
  __IO uint32_t FIFOINTENCLR;                      /**< FIFO Interrupt Enable Clear, offset: 0xE14 */
  __I  uint32_t FIFOINTSTAT;                       /**< FIFO Interrupt Status, offset: 0xE18 */
       uint8_t RESERVED_3[4];
  __O  uint32_t FIFOWR;                            /**< FIFO Write Data, offset: 0xE20 */
       uint8_t RESERVED_4[12];
  __I  uint32_t FIFORD;                            /**< FIFO Read Data, offset: 0xE30 */
       uint8_t RESERVED_5[12];
  __I  uint32_t FIFORDNOPOP;                       /**< FIFO Data Read with No FIFO Pop, offset: 0xE40 */
       uint8_t RESERVED_6[4];
  __I  uint32_t FIFOSIZE;                          /**< FIFO Size, offset: 0xE48 */
  __IO uint32_t FIFORXTIMEOUTCFG;                  /**< FIFO Receive Timeout Configuration, offset: 0xE4C */
  __I  uint32_t FIFORXTIMEOUTCNT;                  /**< FIFO Receive Timeout Counter, offset: 0xE50 */
       uint8_t RESERVED_7[424];
  __I  uint32_t ID;                                /**< Peripheral Identification, offset: 0xFFC */
} USART_Type;

/* ----------------------------------------------------------------------------
   -- USART Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup USART_Register_Masks USART Register Masks
 * @{
 */

/*! @name CFG - USART Configuration */
/*! @{ */

#define USART_CFG_ENABLE_MASK                    (0x1U)
#define USART_CFG_ENABLE_SHIFT                   (0U)
/*! ENABLE - USART Enable
 *  0b0..Disabled
 *  0b1..Enabled. The USART is enabled for operation.
 */
#define USART_CFG_ENABLE(x)                      (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK)

#define USART_CFG_DATALEN_MASK                   (0xCU)
#define USART_CFG_DATALEN_SHIFT                  (2U)
/*! DATALEN - Data Length. Selects the data size for the USART.
 *  0b00..7 bit data length
 *  0b01..8 bit data length
 *  0b10..9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET[CTL].
 *  0b11..Reserved
 */
#define USART_CFG_DATALEN(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK)

#define USART_CFG_PARITYSEL_MASK                 (0x30U)
#define USART_CFG_PARITYSEL_SHIFT                (4U)
/*! PARITYSEL - Parity Select. Selects what type of parity is used by the USART.
 *  0b00..No parity
 *  0b01..Reserved
 *  0b10..Even parity
 *  0b11..Odd parity
 */
#define USART_CFG_PARITYSEL(x)                   (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK)

#define USART_CFG_STOPLEN_MASK                   (0x40U)
#define USART_CFG_STOPLEN_SHIFT                  (6U)
/*! STOPLEN - Stop Length
 *  0b0..1 stop bit
 *  0b1..2 stop bits. This setting should be used only for asynchronous communication.
 */
#define USART_CFG_STOPLEN(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK)

#define USART_CFG_MODE32K_MASK                   (0x80U)
#define USART_CFG_MODE32K_SHIFT                  (7U)
/*! MODE32K - Mode 32 kHz
 *  0b0..Disabled. USART uses standard clocking.
 *  0b1..Enabled
 */
#define USART_CFG_MODE32K(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CFG_MODE32K_SHIFT)) & USART_CFG_MODE32K_MASK)

#define USART_CFG_LINMODE_MASK                   (0x100U)
#define USART_CFG_LINMODE_SHIFT                  (8U)
/*! LINMODE - LIN Break Mode Enable
 *  0b0..Disabled. Break detect and generate is configured for normal operation.
 *  0b1..Enabled. Break detect and generate is configured for LIN bus operation.
 */
#define USART_CFG_LINMODE(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CFG_LINMODE_SHIFT)) & USART_CFG_LINMODE_MASK)

#define USART_CFG_CTSEN_MASK                     (0x200U)
#define USART_CFG_CTSEN_SHIFT                    (9U)
/*! CTSEN - CTS Enable
 *  0b0..No flow control. The transmitter does not receive any automatic flow control signal.
 *  0b1..Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes.
 */
#define USART_CFG_CTSEN(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK)

#define USART_CFG_SYNCEN_MASK                    (0x800U)
#define USART_CFG_SYNCEN_SHIFT                   (11U)
/*! SYNCEN - Synchronous Enable. Selects synchronous or asynchronous operation.
 *  0b0..Asynchronous mode
 *  0b1..Synchronous mode
 */
#define USART_CFG_SYNCEN(x)                      (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK)

#define USART_CFG_CLKPOL_MASK                    (0x1000U)
#define USART_CFG_CLKPOL_SHIFT                   (12U)
/*! CLKPOL - Clock Polarity
 *  0b0..Falling edge. RXD is sampled on the falling edge of SCLK.
 *  0b1..Rising edge. RXD is sampled on the rising edge of SCLK.
 */
#define USART_CFG_CLKPOL(x)                      (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK)

#define USART_CFG_SYNCMST_MASK                   (0x4000U)
#define USART_CFG_SYNCMST_SHIFT                  (14U)
/*! SYNCMST - Synchronous mode Master Select
 *  0b0..Slave. When synchronous mode is enabled, the USART is a slave.
 *  0b1..Master. When synchronous mode is enabled, the USART is a master.
 */
#define USART_CFG_SYNCMST(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK)

#define USART_CFG_LOOP_MASK                      (0x8000U)
#define USART_CFG_LOOP_SHIFT                     (15U)
/*! LOOP - Loopback Mode
 *  0b0..Normal operation
 *  0b1..Loopback mode
 */
#define USART_CFG_LOOP(x)                        (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK)

#define USART_CFG_OETA_MASK                      (0x40000U)
#define USART_CFG_OETA_SHIFT                     (18U)
/*! OETA - Output Enable Turnaround Time Enable for RS-485 Operation.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define USART_CFG_OETA(x)                        (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK)

#define USART_CFG_AUTOADDR_MASK                  (0x80000U)
#define USART_CFG_AUTOADDR_SHIFT                 (19U)
/*! AUTOADDR - Automatic Address Matching Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define USART_CFG_AUTOADDR(x)                    (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK)

#define USART_CFG_OESEL_MASK                     (0x100000U)
#define USART_CFG_OESEL_SHIFT                    (20U)
/*! OESEL - Output Enable Select
 *  0b0..Standard. The RTS signal is used as the standard flow control function.
 *  0b1..RS-485. The RTS signal is configured to provide an output enable signal to control an RS-485 transceiver.
 */
#define USART_CFG_OESEL(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK)

#define USART_CFG_OEPOL_MASK                     (0x200000U)
#define USART_CFG_OEPOL_SHIFT                    (21U)
/*! OEPOL - Output Enable Polarity
 *  0b0..Low. If selected by OESEL, the output enable is active low.
 *  0b1..High. If selected by OESEL, the output enable is active high.
 */
#define USART_CFG_OEPOL(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK)

#define USART_CFG_RXPOL_MASK                     (0x400000U)
#define USART_CFG_RXPOL_SHIFT                    (22U)
/*! RXPOL - Receive Data Polarity
 *  0b0..Standard
 *  0b1..Inverted
 */
#define USART_CFG_RXPOL(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK)

#define USART_CFG_TXPOL_MASK                     (0x800000U)
#define USART_CFG_TXPOL_SHIFT                    (23U)
/*! TXPOL - Transmit data polarity
 *  0b0..Standard
 *  0b1..Inverted
 */
#define USART_CFG_TXPOL(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK)
/*! @} */

/*! @name CTL - USART Control */
/*! @{ */

#define USART_CTL_TXBRKEN_MASK                   (0x2U)
#define USART_CTL_TXBRKEN_SHIFT                  (1U)
/*! TXBRKEN - Break Enable
 *  0b0..Normal operation
 *  0b1..Continuous break
 */
#define USART_CTL_TXBRKEN(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK)

#define USART_CTL_ADDRDET_MASK                   (0x4U)
#define USART_CTL_ADDRDET_SHIFT                  (2U)
/*! ADDRDET - Enable Address Detect Mode
 *  0b0..Disabled. The USART presents all incoming data.
 *  0b1..Enabled
 */
#define USART_CTL_ADDRDET(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK)

#define USART_CTL_TXDIS_MASK                     (0x40U)
#define USART_CTL_TXDIS_SHIFT                    (6U)
/*! TXDIS - Transmit Disable
 *  0b0..Not disabled. USART transmitter is not disabled.
 *  0b1..Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This
 *       feature can be used to facilitate software flow control.
 */
#define USART_CTL_TXDIS(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK)

#define USART_CTL_CC_MASK                        (0x100U)
#define USART_CTL_CC_SHIFT                       (8U)
/*! CC - Continuous Clock Generation
 *  0b0..Clock on character
 *  0b1..Continuous clock
 */
#define USART_CTL_CC(x)                          (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK)

#define USART_CTL_CLRCCONRX_MASK                 (0x200U)
#define USART_CTL_CLRCCONRX_SHIFT                (9U)
/*! CLRCCONRX - Clear Continuous Clock
 *  0b0..No effect. No effect on the CC bit.
 *  0b1..Auto-clear
 */
#define USART_CTL_CLRCCONRX(x)                   (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK)

#define USART_CTL_AUTOBAUD_MASK                  (0x10000U)
#define USART_CTL_AUTOBAUD_SHIFT                 (16U)
/*! AUTOBAUD - Autobaud Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define USART_CTL_AUTOBAUD(x)                    (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK)
/*! @} */

/*! @name STAT - USART Status */
/*! @{ */

#define USART_STAT_RXIDLE_MASK                   (0x2U)
#define USART_STAT_RXIDLE_SHIFT                  (1U)
/*! RXIDLE - Receiver Idle
 *  0b0..The receiver is currently receiving data.
 *  0b1..The receiver is not currently receiving data.
 */
#define USART_STAT_RXIDLE(x)                     (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK)

#define USART_STAT_TXIDLE_MASK                   (0x8U)
#define USART_STAT_TXIDLE_SHIFT                  (3U)
/*! TXIDLE - Transmitter Idle
 *  0b0..The transmitter is currently sending data.
 *  0b1..The transmitter is not currently sending data.
 */
#define USART_STAT_TXIDLE(x)                     (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK)

#define USART_STAT_CTS_MASK                      (0x10U)
#define USART_STAT_CTS_SHIFT                     (4U)
/*! CTS - CTS value
 */
#define USART_STAT_CTS(x)                        (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK)

#define USART_STAT_DELTACTS_MASK                 (0x20U)
#define USART_STAT_DELTACTS_SHIFT                (5U)
/*! DELTACTS - Delta CTS
 */
#define USART_STAT_DELTACTS(x)                   (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK)

#define USART_STAT_TXDISSTAT_MASK                (0x40U)
#define USART_STAT_TXDISSTAT_SHIFT               (6U)
/*! TXDISSTAT - Transmitter Disabled Status Flag
 *  0b0..Not Idle. Indicates that the USART transmitter is NOT fully idle after being disabled.
 *  0b1..Idle. Indicates that the USART transmitter is fully idle after being disabled (CTL[TXDIS] = 1).
 */
#define USART_STAT_TXDISSTAT(x)                  (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK)

#define USART_STAT_RXBRK_MASK                    (0x400U)
#define USART_STAT_RXBRK_SHIFT                   (10U)
/*! RXBRK - Received Break
 */
#define USART_STAT_RXBRK(x)                      (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK)

#define USART_STAT_DELTARXBRK_MASK               (0x800U)
#define USART_STAT_DELTARXBRK_SHIFT              (11U)
/*! DELTARXBRK - Delta Received Break
 */
#define USART_STAT_DELTARXBRK(x)                 (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK)

#define USART_STAT_START_MASK                    (0x1000U)
#define USART_STAT_START_SHIFT                   (12U)
/*! START - Start
 */
#define USART_STAT_START(x)                      (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK)

#define USART_STAT_FRAMERRINT_MASK               (0x2000U)
#define USART_STAT_FRAMERRINT_SHIFT              (13U)
/*! FRAMERRINT - Framing Error Interrupt Flag
 */
#define USART_STAT_FRAMERRINT(x)                 (((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK)

#define USART_STAT_PARITYERRINT_MASK             (0x4000U)
#define USART_STAT_PARITYERRINT_SHIFT            (14U)
/*! PARITYERRINT - Parity Error Interrupt Flag
 */
#define USART_STAT_PARITYERRINT(x)               (((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK)

#define USART_STAT_RXNOISEINT_MASK               (0x8000U)
#define USART_STAT_RXNOISEINT_SHIFT              (15U)
/*! RXNOISEINT - Received Noise Interrupt Flag
 */
#define USART_STAT_RXNOISEINT(x)                 (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK)

#define USART_STAT_ABERR_MASK                    (0x10000U)
#define USART_STAT_ABERR_SHIFT                   (16U)
/*! ABERR - Auto Baud Error
 */
#define USART_STAT_ABERR(x)                      (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK)
/*! @} */

/*! @name INTENSET - Interrupt Enable Read and Set for USART (not FIFO) Status */
/*! @{ */

#define USART_INTENSET_TXIDLEEN_MASK             (0x8U)
#define USART_INTENSET_TXIDLEEN_SHIFT            (3U)
/*! TXIDLEEN - Transmit Idle Flag
 *  0b1..Enables an interrupt when the transmitter becomes idle (STAT[TXIDLE] = 1).
 */
#define USART_INTENSET_TXIDLEEN(x)               (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK)

#define USART_INTENSET_DELTACTSEN_MASK           (0x20U)
#define USART_INTENSET_DELTACTSEN_SHIFT          (5U)
/*! DELTACTSEN - Delta CTS Input Flag
 *  0b1..Enables an interrupt when there is a change in the state of the CTS input.
 */
#define USART_INTENSET_DELTACTSEN(x)             (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK)

#define USART_INTENSET_TXDISEN_MASK              (0x40U)
#define USART_INTENSET_TXDISEN_SHIFT             (6U)
/*! TXDISEN - Transmit Disabled Flag
 *  0b1..Enables an interrupt when the transmitter is fully disabled as indicated by the STAT[TXDISINT] flag. See
 *       the description of the STAT[TXDISINT] flag.
 */
#define USART_INTENSET_TXDISEN(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK)

#define USART_INTENSET_DELTARXBRKEN_MASK         (0x800U)
#define USART_INTENSET_DELTARXBRKEN_SHIFT        (11U)
/*! DELTARXBRKEN - Delta Receive Break Enable
 *  0b1..Enable
 */
#define USART_INTENSET_DELTARXBRKEN(x)           (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK)

#define USART_INTENSET_STARTEN_MASK              (0x1000U)
#define USART_INTENSET_STARTEN_SHIFT             (12U)
/*! STARTEN - Start Enable
 *  0b1..Enables an interrupt when a received start bit has been detected.
 */
#define USART_INTENSET_STARTEN(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK)

#define USART_INTENSET_FRAMERREN_MASK            (0x2000U)
#define USART_INTENSET_FRAMERREN_SHIFT           (13U)
/*! FRAMERREN - Frame Error Enable
 *  0b1..Enables an interrupt when a framing error has been detected.
 */
#define USART_INTENSET_FRAMERREN(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK)

#define USART_INTENSET_PARITYERREN_MASK          (0x4000U)
#define USART_INTENSET_PARITYERREN_SHIFT         (14U)
/*! PARITYERREN - Parity Error Enble
 *  0b1..Enables an interrupt when a parity error has been detected.
 */
#define USART_INTENSET_PARITYERREN(x)            (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK)

#define USART_INTENSET_RXNOISEEN_MASK            (0x8000U)
#define USART_INTENSET_RXNOISEEN_SHIFT           (15U)
/*! RXNOISEEN - Receive Noise Enable
 *  0b1..Enables an interrupt when noise is detected. See the description of the CTL[RXNOISEINT] bit.
 */
#define USART_INTENSET_RXNOISEEN(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK)

#define USART_INTENSET_ABERREN_MASK              (0x10000U)
#define USART_INTENSET_ABERREN_SHIFT             (16U)
/*! ABERREN - Auto Baud Error Enable
 *  0b1..Enables an interrupt when an auto baud error occurs.
 */
#define USART_INTENSET_ABERREN(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK)
/*! @} */

/*! @name INTENCLR - Interrupt Enable Clear */
/*! @{ */

#define USART_INTENCLR_TXIDLECLR_MASK            (0x8U)
#define USART_INTENCLR_TXIDLECLR_SHIFT           (3U)
/*! TXIDLECLR - Transmit Idle Clear
 */
#define USART_INTENCLR_TXIDLECLR(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK)

#define USART_INTENCLR_DELTACTSCLR_MASK          (0x20U)
#define USART_INTENCLR_DELTACTSCLR_SHIFT         (5U)
/*! DELTACTSCLR - Delta CTS Clear
 */
#define USART_INTENCLR_DELTACTSCLR(x)            (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK)

#define USART_INTENCLR_TXDISCLR_MASK             (0x40U)
#define USART_INTENCLR_TXDISCLR_SHIFT            (6U)
/*! TXDISCLR - Transmit Disable Clear
 */
#define USART_INTENCLR_TXDISCLR(x)               (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISCLR_SHIFT)) & USART_INTENCLR_TXDISCLR_MASK)

#define USART_INTENCLR_DELTARXBRKCLR_MASK        (0x800U)
#define USART_INTENCLR_DELTARXBRKCLR_SHIFT       (11U)
/*! DELTARXBRKCLR - Delta Receive Break Clear
 */
#define USART_INTENCLR_DELTARXBRKCLR(x)          (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK)

#define USART_INTENCLR_STARTCLR_MASK             (0x1000U)
#define USART_INTENCLR_STARTCLR_SHIFT            (12U)
/*! STARTCLR - Start Clear
 */
#define USART_INTENCLR_STARTCLR(x)               (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK)

#define USART_INTENCLR_FRAMERRCLR_MASK           (0x2000U)
#define USART_INTENCLR_FRAMERRCLR_SHIFT          (13U)
/*! FRAMERRCLR - Frame Error Clear
 */
#define USART_INTENCLR_FRAMERRCLR(x)             (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK)

#define USART_INTENCLR_PARITYERRCLR_MASK         (0x4000U)
#define USART_INTENCLR_PARITYERRCLR_SHIFT        (14U)
/*! PARITYERRCLR - Parity Error Clear
 */
#define USART_INTENCLR_PARITYERRCLR(x)           (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK)

#define USART_INTENCLR_RXNOISECLR_MASK           (0x8000U)
#define USART_INTENCLR_RXNOISECLR_SHIFT          (15U)
/*! RXNOISECLR - Receive Noise Clear
 */
#define USART_INTENCLR_RXNOISECLR(x)             (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK)

#define USART_INTENCLR_ABERRCLR_MASK             (0x10000U)
#define USART_INTENCLR_ABERRCLR_SHIFT            (16U)
/*! ABERRCLR - Auto Baud Error Clear
 */
#define USART_INTENCLR_ABERRCLR(x)               (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK)
/*! @} */

/*! @name BRG - Baud Rate Generator */
/*! @{ */

#define USART_BRG_BRGVAL_MASK                    (0xFFFFU)
#define USART_BRG_BRGVAL_SHIFT                   (0U)
/*! BRGVAL - Baud Rate Generator Value
 *  0b0000000000000000..FCLK is used directly by the USART function.
 *  0b0000000000000001..FCLK is divided by 2 before use by the USART function.
 *  0b0000000000000010..FCLK is divided by 3 before use by the USART function.
 *  0b1111111111111111..FCLK is divided by 65,536 before use by the USART function.
 */
#define USART_BRG_BRGVAL(x)                      (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK)
/*! @} */

/*! @name INTSTAT - Interrupt Status */
/*! @{ */

#define USART_INTSTAT_TXIDLE_MASK                (0x8U)
#define USART_INTSTAT_TXIDLE_SHIFT               (3U)
/*! TXIDLE - Transmitter Idle Flag
 */
#define USART_INTSTAT_TXIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK)

#define USART_INTSTAT_DELTACTS_MASK              (0x20U)
#define USART_INTSTAT_DELTACTS_SHIFT             (5U)
/*! DELTACTS - Delta CTS Change Flag
 */
#define USART_INTSTAT_DELTACTS(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK)

#define USART_INTSTAT_TXDISINT_MASK              (0x40U)
#define USART_INTSTAT_TXDISINT_SHIFT             (6U)
/*! TXDISINT - Transmitter Disabled Interrupt Flag
 */
#define USART_INTSTAT_TXDISINT(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK)

#define USART_INTSTAT_DELTARXBRK_MASK            (0x800U)
#define USART_INTSTAT_DELTARXBRK_SHIFT           (11U)
/*! DELTARXBRK - Delta Receiver Break Change Flag
 */
#define USART_INTSTAT_DELTARXBRK(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK)

#define USART_INTSTAT_START_MASK                 (0x1000U)
#define USART_INTSTAT_START_SHIFT                (12U)
/*! START - Start Detected on Receiver Flag
 */
#define USART_INTSTAT_START(x)                   (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK)

#define USART_INTSTAT_FRAMERRINT_MASK            (0x2000U)
#define USART_INTSTAT_FRAMERRINT_SHIFT           (13U)
/*! FRAMERRINT - Framing Error Interrupt Flag
 */
#define USART_INTSTAT_FRAMERRINT(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK)

#define USART_INTSTAT_PARITYERRINT_MASK          (0x4000U)
#define USART_INTSTAT_PARITYERRINT_SHIFT         (14U)
/*! PARITYERRINT - Parity Error Interrupt Flag
 */
#define USART_INTSTAT_PARITYERRINT(x)            (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK)

#define USART_INTSTAT_RXNOISEINT_MASK            (0x8000U)
#define USART_INTSTAT_RXNOISEINT_SHIFT           (15U)
/*! RXNOISEINT - Received Noise Interrupt Flag
 */
#define USART_INTSTAT_RXNOISEINT(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK)

#define USART_INTSTAT_ABERRINT_MASK              (0x10000U)
#define USART_INTSTAT_ABERRINT_SHIFT             (16U)
/*! ABERRINT - Auto Baud Error Interrupt Flag
 */
#define USART_INTSTAT_ABERRINT(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK)
/*! @} */

/*! @name OSR - Oversample Selection Register for Asynchronous Communication */
/*! @{ */

#define USART_OSR_OSRVAL_MASK                    (0xFU)
#define USART_OSR_OSRVAL_SHIFT                   (0U)
/*! OSRVAL - Oversample Selection Value
 *  0b0000..Not supported
 *  0b0001..Not supported
 *  0b0010..Not supported
 *  0b0011..Not supported
 *  0b0100..5 function clocks are used to transmit and receive each data bit.
 *  0b0101..6 function clocks are used to transmit and receive each data bit.
 *  0b1111..16 function clocks are used to transmit and receive each data bit.
 */
#define USART_OSR_OSRVAL(x)                      (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK)
/*! @} */

/*! @name ADDR - Address Register for Automatic Address Matching */
/*! @{ */

#define USART_ADDR_ADDRESS_MASK                  (0xFFU)
#define USART_ADDR_ADDRESS_SHIFT                 (0U)
/*! ADDRESS - Address
 */
#define USART_ADDR_ADDRESS(x)                    (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK)
/*! @} */

/*! @name FIFOCFG - FIFO Configuration */
/*! @{ */

#define USART_FIFOCFG_ENABLETX_MASK              (0x1U)
#define USART_FIFOCFG_ENABLETX_SHIFT             (0U)
/*! ENABLETX - Enable the Transmit FIFO.
 *  0b0..The transmit FIFO is not enabled.
 *  0b1..The transmit FIFO is enabled.
 */
#define USART_FIFOCFG_ENABLETX(x)                (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK)

#define USART_FIFOCFG_ENABLERX_MASK              (0x2U)
#define USART_FIFOCFG_ENABLERX_SHIFT             (1U)
/*! ENABLERX - Enable the Receive FIFO
 *  0b0..The receive FIFO is not enabled.
 *  0b1..The receive FIFO is enabled.
 */
#define USART_FIFOCFG_ENABLERX(x)                (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLERX_SHIFT)) & USART_FIFOCFG_ENABLERX_MASK)

#define USART_FIFOCFG_SIZE_MASK                  (0x30U)
#define USART_FIFOCFG_SIZE_SHIFT                 (4U)
/*! SIZE - FIFO Size Configuration
 *  0b00..FIFO is configured as 16 entries of 8 bits.
 *  0b01..Not used
 *  0b10..Not used
 *  0b11..Not used
 */
#define USART_FIFOCFG_SIZE(x)                    (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_SIZE_SHIFT)) & USART_FIFOCFG_SIZE_MASK)

#define USART_FIFOCFG_DMATX_MASK                 (0x1000U)
#define USART_FIFOCFG_DMATX_SHIFT                (12U)
/*! DMATX - DMA Configuration for Transmit
 *  0b0..DMA is not used for the transmit function.
 *  0b1..Triggers DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled.
 */
#define USART_FIFOCFG_DMATX(x)                   (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMATX_SHIFT)) & USART_FIFOCFG_DMATX_MASK)

#define USART_FIFOCFG_DMARX_MASK                 (0x2000U)
#define USART_FIFOCFG_DMARX_SHIFT                (13U)
/*! DMARX - DMA Configuration for Receive
 *  0b0..DMA is not used for the receive function.
 *  0b1..Triggers DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled.
 */
#define USART_FIFOCFG_DMARX(x)                   (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMARX_SHIFT)) & USART_FIFOCFG_DMARX_MASK)

#define USART_FIFOCFG_WAKETX_MASK                (0x4000U)
#define USART_FIFOCFG_WAKETX_SHIFT               (14U)
/*! WAKETX - Wake-up for Transmit FIFO Level
 *  0b0..Only enabled interrupts will wake up the device from low power modes.
 *  0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by
 *       FIFOTRIG[TXLVL], even when the TXLVL interrupt is not enabled.
 */
#define USART_FIFOCFG_WAKETX(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKETX_SHIFT)) & USART_FIFOCFG_WAKETX_MASK)

#define USART_FIFOCFG_WAKERX_MASK                (0x8000U)
#define USART_FIFOCFG_WAKERX_SHIFT               (15U)
/*! WAKERX - Wake-up for Receive FIFO Level
 *  0b0..Only enabled interrupts will wake up the device from low power modes.
 *  0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by
 *       FIFOTRIG[RXLVL], even when the RXLVL interrupt is not enabled.
 */
#define USART_FIFOCFG_WAKERX(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKERX_SHIFT)) & USART_FIFOCFG_WAKERX_MASK)

#define USART_FIFOCFG_EMPTYTX_MASK               (0x10000U)
#define USART_FIFOCFG_EMPTYTX_SHIFT              (16U)
/*! EMPTYTX - Empty Command for the Transmit FIFO
 *  0b0..No effect
 *  0b1..The TX FIFO is emptied.
 */
#define USART_FIFOCFG_EMPTYTX(x)                 (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYTX_SHIFT)) & USART_FIFOCFG_EMPTYTX_MASK)

#define USART_FIFOCFG_EMPTYRX_MASK               (0x20000U)
#define USART_FIFOCFG_EMPTYRX_SHIFT              (17U)
/*! EMPTYRX - Empty Command for the Receive FIFO
 *  0b0..No effect
 *  0b1..The RX FIFO is emptied.
 */
#define USART_FIFOCFG_EMPTYRX(x)                 (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK)

#define USART_FIFOCFG_POPDBG_MASK                (0x40000U)
#define USART_FIFOCFG_POPDBG_SHIFT               (18U)
/*! POPDBG - Pop FIFO for Debug Reads
 *  0b0..Debug reads of the FIFO do not pop the FIFO.
 *  0b1..A debug read will cause the FIFO to pop.
 */
#define USART_FIFOCFG_POPDBG(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_POPDBG_SHIFT)) & USART_FIFOCFG_POPDBG_MASK)
/*! @} */

/*! @name FIFOSTAT - FIFO Status */
/*! @{ */

#define USART_FIFOSTAT_TXERR_MASK                (0x1U)
#define USART_FIFOSTAT_TXERR_SHIFT               (0U)
/*! TXERR - TX FIFO Error
 *  0b0..A transmit FIFO error has not occurred.
 *  0b1..A transmit FIFO error has occurred. This error could be an overflow caused by pushing data into a full
 *       FIFO, or by an underflow if the FIFO is empty when data is needed.
 */
#define USART_FIFOSTAT_TXERR(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK)

#define USART_FIFOSTAT_RXERR_MASK                (0x2U)
#define USART_FIFOSTAT_RXERR_SHIFT               (1U)
/*! RXERR - RX FIFO Error
 *  0b0..A receive FIFO overflow has not occurred
 *  0b1..A receive FIFO overflow has occurred, caused by software or DMA not emptying the FIFO fast enough
 */
#define USART_FIFOSTAT_RXERR(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXERR_SHIFT)) & USART_FIFOSTAT_RXERR_MASK)

#define USART_FIFOSTAT_PERINT_MASK               (0x8U)
#define USART_FIFOSTAT_PERINT_SHIFT              (3U)
/*! PERINT - Peripheral Interrupt
 *  0b0..No Peripheral Interrupt
 *  0b1..Peripheral Interrupt
 */
#define USART_FIFOSTAT_PERINT(x)                 (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_PERINT_SHIFT)) & USART_FIFOSTAT_PERINT_MASK)

#define USART_FIFOSTAT_TXEMPTY_MASK              (0x10U)
#define USART_FIFOSTAT_TXEMPTY_SHIFT             (4U)
/*! TXEMPTY - Transmit FIFO Empty
 *  0b0..The transmit FIFO is not empty.
 *  0b1..The transmit FIFO is empty, although the peripheral may still be processing the last piece of data.
 */
#define USART_FIFOSTAT_TXEMPTY(x)                (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXEMPTY_SHIFT)) & USART_FIFOSTAT_TXEMPTY_MASK)

#define USART_FIFOSTAT_TXNOTFULL_MASK            (0x20U)
#define USART_FIFOSTAT_TXNOTFULL_SHIFT           (5U)
/*! TXNOTFULL - Transmit FIFO is Not Full
 *  0b0..The transmit FIFO is full and another write would cause it to overflow.
 *  0b1..The transmit FIFO is not full, so more data can be written.
 */
#define USART_FIFOSTAT_TXNOTFULL(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXNOTFULL_SHIFT)) & USART_FIFOSTAT_TXNOTFULL_MASK)

#define USART_FIFOSTAT_RXNOTEMPTY_MASK           (0x40U)
#define USART_FIFOSTAT_RXNOTEMPTY_SHIFT          (6U)
/*! RXNOTEMPTY - Receive FIFO is Not Empty
 *  0b0..The receive FIFO is empty.
 *  0b1..The receive FIFO is not empty, so data can be read.
 */
#define USART_FIFOSTAT_RXNOTEMPTY(x)             (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXNOTEMPTY_SHIFT)) & USART_FIFOSTAT_RXNOTEMPTY_MASK)

#define USART_FIFOSTAT_RXFULL_MASK               (0x80U)
#define USART_FIFOSTAT_RXFULL_SHIFT              (7U)
/*! RXFULL - Receive FIFO is Full
 *  0b0..The receive FIFO is not full.
 *  0b1..The receive FIFO is full.
 */
#define USART_FIFOSTAT_RXFULL(x)                 (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXFULL_SHIFT)) & USART_FIFOSTAT_RXFULL_MASK)

#define USART_FIFOSTAT_TXLVL_MASK                (0x1F00U)
#define USART_FIFOSTAT_TXLVL_SHIFT               (8U)
/*! TXLVL - Transmit FIFO Current Level
 */
#define USART_FIFOSTAT_TXLVL(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXLVL_SHIFT)) & USART_FIFOSTAT_TXLVL_MASK)

#define USART_FIFOSTAT_RXLVL_MASK                (0x1F0000U)
#define USART_FIFOSTAT_RXLVL_SHIFT               (16U)
/*! RXLVL - Receive FIFO Current Level
 */
#define USART_FIFOSTAT_RXLVL(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK)

#define USART_FIFOSTAT_RXTIMEOUT_MASK            (0x1000000U)
#define USART_FIFOSTAT_RXTIMEOUT_SHIFT           (24U)
/*! RXTIMEOUT - Receive FIFO Timeout
 *  0b0..RX FIFO on
 *  0b1..RX FIFO has timed out, based on the timeout configuration in the FIFORXTIMEOUTCFG register.
 */
#define USART_FIFOSTAT_RXTIMEOUT(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXTIMEOUT_SHIFT)) & USART_FIFOSTAT_RXTIMEOUT_MASK)
/*! @} */

/*! @name FIFOTRIG - FIFO Trigger Settings for Interrupt and DMA Request */
/*! @{ */

#define USART_FIFOTRIG_TXLVLENA_MASK             (0x1U)
#define USART_FIFOTRIG_TXLVLENA_SHIFT            (0U)
/*! TXLVLENA - Transmit FIFO Level Trigger Enable.
 *  0b0..Transmit FIFO level does not generate a FIFO level trigger.
 *  0b1..A trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field.
 */
#define USART_FIFOTRIG_TXLVLENA(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK)

#define USART_FIFOTRIG_RXLVLENA_MASK             (0x2U)
#define USART_FIFOTRIG_RXLVLENA_SHIFT            (1U)
/*! RXLVLENA - Receive FIFO Level Trigger Enable
 *  0b0..Receive FIFO level does not generate a FIFO level trigger.
 *  0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field.
 */
#define USART_FIFOTRIG_RXLVLENA(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVLENA_SHIFT)) & USART_FIFOTRIG_RXLVLENA_MASK)

#define USART_FIFOTRIG_TXLVL_MASK                (0xF00U)
#define USART_FIFOTRIG_TXLVL_SHIFT               (8U)
/*! TXLVL - Transmit FIFO Level Trigger Point
 *  0b0000..Trigger when the TX FIFO becomes empty
 *  0b0001..Trigger when the TX FIFO level decreases to 1 entry
 *  0b1111..Trigger when the TX FIFO level decreases to 15 entries (is no longer full)
 */
#define USART_FIFOTRIG_TXLVL(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVL_SHIFT)) & USART_FIFOTRIG_TXLVL_MASK)

#define USART_FIFOTRIG_RXLVL_MASK                (0xF0000U)
#define USART_FIFOTRIG_RXLVL_SHIFT               (16U)
/*! RXLVL - Receive FIFO Level Trigger Point
 *  0b0000..Trigger when the RX FIFO has received 1 entry (is no longer empty)
 *  0b0001..Trigger when the RX FIFO has received 2 entries
 *  0b1111..Trigger when the RX FIFO has received 16 entries (has become full)
 */
#define USART_FIFOTRIG_RXLVL(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK)
/*! @} */

/*! @name FIFOINTENSET - FIFO Interrupt Enable */
/*! @{ */

#define USART_FIFOINTENSET_TXERR_MASK            (0x1U)
#define USART_FIFOINTENSET_TXERR_SHIFT           (0U)
/*! TXERR - Transmit Error Interrupt Enable
 *  0b0..No interrupt will be generated for a transmit error.
 *  0b1..An interrupt will be generated when a transmit error occurs.
 */
#define USART_FIFOINTENSET_TXERR(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK)

#define USART_FIFOINTENSET_RXERR_MASK            (0x2U)
#define USART_FIFOINTENSET_RXERR_SHIFT           (1U)
/*! RXERR - Receive Error Interrupt Enable
 *  0b0..No interrupt will be generated for a receive error.
 *  0b1..An interrupt will be generated when a receive error occurs.
 */
#define USART_FIFOINTENSET_RXERR(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXERR_SHIFT)) & USART_FIFOINTENSET_RXERR_MASK)

#define USART_FIFOINTENSET_TXLVL_MASK            (0x4U)
#define USART_FIFOINTENSET_TXLVL_SHIFT           (2U)
/*! TXLVL - Transmit FIFO Level Interrupt Enable
 *  0b0..No interrupt will be generated based on the TX FIFO level.
 *  0b1..If FIFOTRIG[TXLVLENA] = 1, then an interrupt will be generated when the TX FIFO level decreases to the level specified by FIFOTRIG[TXLVL]
 */
#define USART_FIFOINTENSET_TXLVL(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXLVL_SHIFT)) & USART_FIFOINTENSET_TXLVL_MASK)

#define USART_FIFOINTENSET_RXLVL_MASK            (0x8U)
#define USART_FIFOINTENSET_RXLVL_SHIFT           (3U)
/*! RXLVL - Receive FIFO Level Interrupt Enable
 *  0b0..No interrupt will be generated based on the RX FIFO level.
 *  0b1..If FIFOTRIG[RXLVLENA] = 1, an interrupt will be generated when the when the RX FIFO level increases to
 *       the level specified by FIFOTRIG[RXLVL].
 */
#define USART_FIFOINTENSET_RXLVL(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXLVL_SHIFT)) & USART_FIFOINTENSET_RXLVL_MASK)

#define USART_FIFOINTENSET_RXTIMEOUT_MASK        (0x1000000U)
#define USART_FIFOINTENSET_RXTIMEOUT_SHIFT       (24U)
/*! RXTIMEOUT - Receive Timeout
 *  0b0..No RX interrupt will be generated.
 *  0b1..Asserts RX interrupt if RX FIFO Timeout event occurs.
 */
#define USART_FIFOINTENSET_RXTIMEOUT(x)          (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXTIMEOUT_SHIFT)) & USART_FIFOINTENSET_RXTIMEOUT_MASK)
/*! @} */

/*! @name FIFOINTENCLR - FIFO Interrupt Enable Clear */
/*! @{ */

#define USART_FIFOINTENCLR_TXERR_MASK            (0x1U)
#define USART_FIFOINTENCLR_TXERR_SHIFT           (0U)
/*! TXERR - Transmit Error Interrupt Enable
 *  0b0..No effect
 *  0b1..Clear the interrupt
 */
#define USART_FIFOINTENCLR_TXERR(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK)

#define USART_FIFOINTENCLR_RXERR_MASK            (0x2U)
#define USART_FIFOINTENCLR_RXERR_SHIFT           (1U)
/*! RXERR - Receive Error Interrupt Enable
 *  0b0..No effect
 *  0b1..Clear the interrupt
 */
#define USART_FIFOINTENCLR_RXERR(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXERR_SHIFT)) & USART_FIFOINTENCLR_RXERR_MASK)

#define USART_FIFOINTENCLR_TXLVL_MASK            (0x4U)
#define USART_FIFOINTENCLR_TXLVL_SHIFT           (2U)
/*! TXLVL - Transmit FIFO Level Interrupt Enable
 *  0b0..No effect
 *  0b1..Clear the interrupt
 */
#define USART_FIFOINTENCLR_TXLVL(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXLVL_SHIFT)) & USART_FIFOINTENCLR_TXLVL_MASK)

#define USART_FIFOINTENCLR_RXLVL_MASK            (0x8U)
#define USART_FIFOINTENCLR_RXLVL_SHIFT           (3U)
/*! RXLVL - Receive FIFO Level Interrupt Enable
 *  0b0..No effect
 *  0b1..Clear the interrupt
 */
#define USART_FIFOINTENCLR_RXLVL(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK)

#define USART_FIFOINTENCLR_RXTIMEOUT_MASK        (0x1000000U)
#define USART_FIFOINTENCLR_RXTIMEOUT_SHIFT       (24U)
/*! RXTIMEOUT - Receive Timeout
 *  0b0..No effect
 *  0b1..Clear the interrupt
 */
#define USART_FIFOINTENCLR_RXTIMEOUT(x)          (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXTIMEOUT_SHIFT)) & USART_FIFOINTENCLR_RXTIMEOUT_MASK)
/*! @} */

/*! @name FIFOINTSTAT - FIFO Interrupt Status */
/*! @{ */

#define USART_FIFOINTSTAT_TXERR_MASK             (0x1U)
#define USART_FIFOINTSTAT_TXERR_SHIFT            (0U)
/*! TXERR - TX FIFO Error Interrupt Status
 *  0b0..Not pending
 *  0b1..Pending
 */
#define USART_FIFOINTSTAT_TXERR(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK)

#define USART_FIFOINTSTAT_RXERR_MASK             (0x2U)
#define USART_FIFOINTSTAT_RXERR_SHIFT            (1U)
/*! RXERR - RX FIFO Error Interrupt Status
 *  0b0..Not pending
 *  0b1..Pending
 */
#define USART_FIFOINTSTAT_RXERR(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXERR_SHIFT)) & USART_FIFOINTSTAT_RXERR_MASK)

#define USART_FIFOINTSTAT_TXLVL_MASK             (0x4U)
#define USART_FIFOINTSTAT_TXLVL_SHIFT            (2U)
/*! TXLVL - Transmit FIFO Level Interrupt Status
 *  0b0..Not pending
 *  0b1..Pending
 */
#define USART_FIFOINTSTAT_TXLVL(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXLVL_SHIFT)) & USART_FIFOINTSTAT_TXLVL_MASK)

#define USART_FIFOINTSTAT_RXLVL_MASK             (0x8U)
#define USART_FIFOINTSTAT_RXLVL_SHIFT            (3U)
/*! RXLVL - Receive FIFO Level Interrupt Status
 *  0b0..Not pending
 *  0b1..Pending
 */
#define USART_FIFOINTSTAT_RXLVL(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXLVL_SHIFT)) & USART_FIFOINTSTAT_RXLVL_MASK)

#define USART_FIFOINTSTAT_PERINT_MASK            (0x10U)
#define USART_FIFOINTSTAT_PERINT_SHIFT           (4U)
/*! PERINT - Peripheral Interrupt Status
 *  0b0..Not pending
 *  0b1..Pending
 */
#define USART_FIFOINTSTAT_PERINT(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK)

#define USART_FIFOINTSTAT_RXTIMEOUT_MASK         (0x1000000U)
#define USART_FIFOINTSTAT_RXTIMEOUT_SHIFT        (24U)
/*! RXTIMEOUT - Receive Timeout Status
 *  0b0..Not pending
 *  0b1..Pending
 */
#define USART_FIFOINTSTAT_RXTIMEOUT(x)           (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXTIMEOUT_SHIFT)) & USART_FIFOINTSTAT_RXTIMEOUT_MASK)
/*! @} */

/*! @name FIFOWR - FIFO Write Data */
/*! @{ */

#define USART_FIFOWR_TXDATA_MASK                 (0x1FFU)
#define USART_FIFOWR_TXDATA_SHIFT                (0U)
/*! TXDATA - Transmit data to the FIFO
 */
#define USART_FIFOWR_TXDATA(x)                   (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK)
/*! @} */

/*! @name FIFORD - FIFO Read Data */
/*! @{ */

#define USART_FIFORD_RXDATA_MASK                 (0x1FFU)
#define USART_FIFORD_RXDATA_SHIFT                (0U)
/*! RXDATA - Received Data from the FIFO
 */
#define USART_FIFORD_RXDATA(x)                   (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK)

#define USART_FIFORD_FRAMERR_MASK                (0x2000U)
#define USART_FIFORD_FRAMERR_SHIFT               (13U)
/*! FRAMERR - Framing Error Status Flag
 */
#define USART_FIFORD_FRAMERR(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_FRAMERR_SHIFT)) & USART_FIFORD_FRAMERR_MASK)

#define USART_FIFORD_PARITYERR_MASK              (0x4000U)
#define USART_FIFORD_PARITYERR_SHIFT             (14U)
/*! PARITYERR - Parity Error Status Flag
 */
#define USART_FIFORD_PARITYERR(x)                (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_PARITYERR_SHIFT)) & USART_FIFORD_PARITYERR_MASK)

#define USART_FIFORD_RXNOISE_MASK                (0x8000U)
#define USART_FIFORD_RXNOISE_SHIFT               (15U)
/*! RXNOISE - Received Noise Flag
 */
#define USART_FIFORD_RXNOISE(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK)
/*! @} */

/*! @name FIFORDNOPOP - FIFO Data Read with No FIFO Pop */
/*! @{ */

#define USART_FIFORDNOPOP_RXDATA_MASK            (0x1FFU)
#define USART_FIFORDNOPOP_RXDATA_SHIFT           (0U)
/*! RXDATA - Received Data from the FIFO
 */
#define USART_FIFORDNOPOP_RXDATA(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK)

#define USART_FIFORDNOPOP_FRAMERR_MASK           (0x2000U)
#define USART_FIFORDNOPOP_FRAMERR_SHIFT          (13U)
/*! FRAMERR - Framing Error Status Flag
 */
#define USART_FIFORDNOPOP_FRAMERR(x)             (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_FRAMERR_SHIFT)) & USART_FIFORDNOPOP_FRAMERR_MASK)

#define USART_FIFORDNOPOP_PARITYERR_MASK         (0x4000U)
#define USART_FIFORDNOPOP_PARITYERR_SHIFT        (14U)
/*! PARITYERR - Parity Error Status Flag
 */
#define USART_FIFORDNOPOP_PARITYERR(x)           (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_PARITYERR_SHIFT)) & USART_FIFORDNOPOP_PARITYERR_MASK)

#define USART_FIFORDNOPOP_RXNOISE_MASK           (0x8000U)
#define USART_FIFORDNOPOP_RXNOISE_SHIFT          (15U)
/*! RXNOISE - Received Noise Flag
 */
#define USART_FIFORDNOPOP_RXNOISE(x)             (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK)
/*! @} */

/*! @name FIFOSIZE - FIFO Size */
/*! @{ */

#define USART_FIFOSIZE_FIFOSIZE_MASK             (0x1FU)
#define USART_FIFOSIZE_FIFOSIZE_SHIFT            (0U)
/*! FIFOSIZE - FIFO Size
 */
#define USART_FIFOSIZE_FIFOSIZE(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOSIZE_FIFOSIZE_SHIFT)) & USART_FIFOSIZE_FIFOSIZE_MASK)
/*! @} */

/*! @name FIFORXTIMEOUTCFG - FIFO Receive Timeout Configuration */
/*! @{ */

#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER_MASK (0xFFU)
#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER_SHIFT (0U)
/*! RXTIMEOUT_PRESCALER - Receive Timeout Counter Clock Prescaler
 */
#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER_SHIFT)) & USART_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER_MASK)

#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE_MASK (0xFFFF00U)
#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE_SHIFT (8U)
/*! RXTIMEOUT_VALUE - Receive Timeout Value
 */
#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE_SHIFT)) & USART_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE_MASK)

#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_EN_MASK (0x1000000U)
#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_EN_SHIFT (24U)
/*! RXTIMEOUT_EN - Receive Timeout Enable
 *  0b0..Disable RX FIFO timeout
 *  0b1..Enable RX FIFO timeout
 */
#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_EN(x)   (((uint32_t)(((uint32_t)(x)) << USART_FIFORXTIMEOUTCFG_RXTIMEOUT_EN_SHIFT)) & USART_FIFORXTIMEOUTCFG_RXTIMEOUT_EN_MASK)

#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_COW_MASK (0x2000000U)
#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_COW_SHIFT (25U)
/*! RXTIMEOUT_COW - Receive Timeout Continue On Write
 *  0b0..RX FIFO timeout counter is reset every time data is transferred from the peripheral into the RX FIFO.
 *  0b1..RX FIFO timeout counter is not reset every time data is transferred from the peripheral into the RX FIFO.
 */
#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_COW(x)  (((uint32_t)(((uint32_t)(x)) << USART_FIFORXTIMEOUTCFG_RXTIMEOUT_COW_SHIFT)) & USART_FIFORXTIMEOUTCFG_RXTIMEOUT_COW_MASK)

#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_COE_MASK (0x4000000U)
#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_COE_SHIFT (26U)
/*! RXTIMEOUT_COE - Receive Timeout Continue On Empty
 *  0b0..RX FIFO timeout counter is reset when the RX FIFO becomes empty.
 *  0b1..RX FIFO timeout counter is not reset when the RX FIFO becomes empty.
 */
#define USART_FIFORXTIMEOUTCFG_RXTIMEOUT_COE(x)  (((uint32_t)(((uint32_t)(x)) << USART_FIFORXTIMEOUTCFG_RXTIMEOUT_COE_SHIFT)) & USART_FIFORXTIMEOUTCFG_RXTIMEOUT_COE_MASK)
/*! @} */

/*! @name FIFORXTIMEOUTCNT - FIFO Receive Timeout Counter */
/*! @{ */

#define USART_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT_MASK (0xFFFFU)
#define USART_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT_SHIFT (0U)
/*! RXTIMEOUT_CNT - Current RX FIFO timeout counter value
 */
#define USART_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT(x)  (((uint32_t)(((uint32_t)(x)) << USART_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT_SHIFT)) & USART_FIFORXTIMEOUTCNT_RXTIMEOUT_CNT_MASK)
/*! @} */

/*! @name ID - Peripheral Identification */
/*! @{ */

#define USART_ID_APERTURE_MASK                   (0xFFU)
#define USART_ID_APERTURE_SHIFT                  (0U)
/*! APERTURE - Aperture
 */
#define USART_ID_APERTURE(x)                     (((uint32_t)(((uint32_t)(x)) << USART_ID_APERTURE_SHIFT)) & USART_ID_APERTURE_MASK)

#define USART_ID_MINOR_REV_MASK                  (0xF00U)
#define USART_ID_MINOR_REV_SHIFT                 (8U)
/*! MINOR_REV - Minor revision of module implementation
 */
#define USART_ID_MINOR_REV(x)                    (((uint32_t)(((uint32_t)(x)) << USART_ID_MINOR_REV_SHIFT)) & USART_ID_MINOR_REV_MASK)

#define USART_ID_MAJOR_REV_MASK                  (0xF000U)
#define USART_ID_MAJOR_REV_SHIFT                 (12U)
/*! MAJOR_REV - Major revision of module implementation
 */
#define USART_ID_MAJOR_REV(x)                    (((uint32_t)(((uint32_t)(x)) << USART_ID_MAJOR_REV_SHIFT)) & USART_ID_MAJOR_REV_MASK)

#define USART_ID_ID_MASK                         (0xFFFF0000U)
#define USART_ID_ID_SHIFT                        (16U)
/*! ID - Module identifier for the selected function
 */
#define USART_ID_ID(x)                           (((uint32_t)(((uint32_t)(x)) << USART_ID_ID_SHIFT)) & USART_ID_ID_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group USART_Register_Masks */


/* USART - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral USART0 base address */
  #define USART0_BASE                              (0x50086000u)
  /** Peripheral USART0 base address */
  #define USART0_BASE_NS                           (0x40086000u)
  /** Peripheral USART0 base pointer */
  #define USART0                                   ((USART_Type *)USART0_BASE)
  /** Peripheral USART0 base pointer */
  #define USART0_NS                                ((USART_Type *)USART0_BASE_NS)
  /** Peripheral USART1 base address */
  #define USART1_BASE                              (0x50087000u)
  /** Peripheral USART1 base address */
  #define USART1_BASE_NS                           (0x40087000u)
  /** Peripheral USART1 base pointer */
  #define USART1                                   ((USART_Type *)USART1_BASE)
  /** Peripheral USART1 base pointer */
  #define USART1_NS                                ((USART_Type *)USART1_BASE_NS)
  /** Peripheral USART2 base address */
  #define USART2_BASE                              (0x50088000u)
  /** Peripheral USART2 base address */
  #define USART2_BASE_NS                           (0x40088000u)
  /** Peripheral USART2 base pointer */
  #define USART2                                   ((USART_Type *)USART2_BASE)
  /** Peripheral USART2 base pointer */
  #define USART2_NS                                ((USART_Type *)USART2_BASE_NS)
  /** Peripheral USART3 base address */
  #define USART3_BASE                              (0x50089000u)
  /** Peripheral USART3 base address */
  #define USART3_BASE_NS                           (0x40089000u)
  /** Peripheral USART3 base pointer */
  #define USART3                                   ((USART_Type *)USART3_BASE)
  /** Peripheral USART3 base pointer */
  #define USART3_NS                                ((USART_Type *)USART3_BASE_NS)
  /** Peripheral USART4 base address */
  #define USART4_BASE                              (0x5008A000u)
  /** Peripheral USART4 base address */
  #define USART4_BASE_NS                           (0x4008A000u)
  /** Peripheral USART4 base pointer */
  #define USART4                                   ((USART_Type *)USART4_BASE)
  /** Peripheral USART4 base pointer */
  #define USART4_NS                                ((USART_Type *)USART4_BASE_NS)
  /** Peripheral USART5 base address */
  #define USART5_BASE                              (0x50096000u)
  /** Peripheral USART5 base address */
  #define USART5_BASE_NS                           (0x40096000u)
  /** Peripheral USART5 base pointer */
  #define USART5                                   ((USART_Type *)USART5_BASE)
  /** Peripheral USART5 base pointer */
  #define USART5_NS                                ((USART_Type *)USART5_BASE_NS)
  /** Peripheral USART6 base address */
  #define USART6_BASE                              (0x50097000u)
  /** Peripheral USART6 base address */
  #define USART6_BASE_NS                           (0x40097000u)
  /** Peripheral USART6 base pointer */
  #define USART6                                   ((USART_Type *)USART6_BASE)
  /** Peripheral USART6 base pointer */
  #define USART6_NS                                ((USART_Type *)USART6_BASE_NS)
  /** Peripheral USART7 base address */
  #define USART7_BASE                              (0x50098000u)
  /** Peripheral USART7 base address */
  #define USART7_BASE_NS                           (0x40098000u)
  /** Peripheral USART7 base pointer */
  #define USART7                                   ((USART_Type *)USART7_BASE)
  /** Peripheral USART7 base pointer */
  #define USART7_NS                                ((USART_Type *)USART7_BASE_NS)
  /** Array initializer of USART peripheral base addresses */
  #define USART_BASE_ADDRS                         { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE }
  /** Array initializer of USART peripheral base pointers */
  #define USART_BASE_PTRS                          { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 }
  /** Array initializer of USART peripheral base addresses */
  #define USART_BASE_ADDRS_NS                      { USART0_BASE_NS, USART1_BASE_NS, USART2_BASE_NS, USART3_BASE_NS, USART4_BASE_NS, USART5_BASE_NS, USART6_BASE_NS, USART7_BASE_NS }
  /** Array initializer of USART peripheral base pointers */
  #define USART_BASE_PTRS_NS                       { USART0_NS, USART1_NS, USART2_NS, USART3_NS, USART4_NS, USART5_NS, USART6_NS, USART7_NS }
#else
  /** Peripheral USART0 base address */
  #define USART0_BASE                              (0x40086000u)
  /** Peripheral USART0 base pointer */
  #define USART0                                   ((USART_Type *)USART0_BASE)
  /** Peripheral USART1 base address */
  #define USART1_BASE                              (0x40087000u)
  /** Peripheral USART1 base pointer */
  #define USART1                                   ((USART_Type *)USART1_BASE)
  /** Peripheral USART2 base address */
  #define USART2_BASE                              (0x40088000u)
  /** Peripheral USART2 base pointer */
  #define USART2                                   ((USART_Type *)USART2_BASE)
  /** Peripheral USART3 base address */
  #define USART3_BASE                              (0x40089000u)
  /** Peripheral USART3 base pointer */
  #define USART3                                   ((USART_Type *)USART3_BASE)
  /** Peripheral USART4 base address */
  #define USART4_BASE                              (0x4008A000u)
  /** Peripheral USART4 base pointer */
  #define USART4                                   ((USART_Type *)USART4_BASE)
  /** Peripheral USART5 base address */
  #define USART5_BASE                              (0x40096000u)
  /** Peripheral USART5 base pointer */
  #define USART5                                   ((USART_Type *)USART5_BASE)
  /** Peripheral USART6 base address */
  #define USART6_BASE                              (0x40097000u)
  /** Peripheral USART6 base pointer */
  #define USART6                                   ((USART_Type *)USART6_BASE)
  /** Peripheral USART7 base address */
  #define USART7_BASE                              (0x40098000u)
  /** Peripheral USART7 base pointer */
  #define USART7                                   ((USART_Type *)USART7_BASE)
  /** Array initializer of USART peripheral base addresses */
  #define USART_BASE_ADDRS                         { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE }
  /** Array initializer of USART peripheral base pointers */
  #define USART_BASE_PTRS                          { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 }
#endif
/** Interrupt vectors for the USART peripheral type */
#define USART_IRQS                               { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn }

/*!
 * @}
 */ /* end of group USART_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- USB Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
 * @{
 */

/** USB - Register Layout Typedef */
typedef struct {
  __IO uint32_t DEVCMDSTAT;                        /**< USB Device Command/Status, offset: 0x0 */
  __IO uint32_t INFO;                              /**< USB Info, offset: 0x4 */
  __IO uint32_t EPLISTSTART;                       /**< USB EP Command/Status List start address, offset: 0x8 */
  __IO uint32_t DATABUFSTART;                      /**< USB Data buffer start address, offset: 0xC */
  __IO uint32_t LPM;                               /**< USB Link Power Management, offset: 0x10 */
  __IO uint32_t EPSKIP;                            /**< USB Endpoint skip, offset: 0x14 */
  __IO uint32_t EPINUSE;                           /**< USB Endpoint Buffer in use, offset: 0x18 */
  __IO uint32_t EPBUFCFG;                          /**< USB Endpoint Buffer Configuration, offset: 0x1C */
  __IO uint32_t INTSTAT;                           /**< USB interrupt status, offset: 0x20 */
  __IO uint32_t INTEN;                             /**< USB interrupt enable, offset: 0x24 */
  __IO uint32_t INTSETSTAT;                        /**< USB set interrupt status, offset: 0x28 */
       uint8_t RESERVED_0[8];
  __IO uint32_t EPTOGGLE;                          /**< USB Endpoint toggle, offset: 0x34 */
} USB_Type;

/* ----------------------------------------------------------------------------
   -- USB Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup USB_Register_Masks USB Register Masks
 * @{
 */

/*! @name DEVCMDSTAT - USB Device Command/Status */
/*! @{ */

#define USB_DEVCMDSTAT_DEV_ADDR_MASK             (0x7FU)
#define USB_DEVCMDSTAT_DEV_ADDR_SHIFT            (0U)
/*! DEV_ADDR - USB device address
 */
#define USB_DEVCMDSTAT_DEV_ADDR(x)               (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USB_DEVCMDSTAT_DEV_ADDR_MASK)

#define USB_DEVCMDSTAT_DEV_EN_MASK               (0x80U)
#define USB_DEVCMDSTAT_DEV_EN_SHIFT              (7U)
/*! DEV_EN - USB device enable
 */
#define USB_DEVCMDSTAT_DEV_EN(x)                 (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_EN_SHIFT)) & USB_DEVCMDSTAT_DEV_EN_MASK)

#define USB_DEVCMDSTAT_SETUP_MASK                (0x100U)
#define USB_DEVCMDSTAT_SETUP_SHIFT               (8U)
/*! SETUP - SETUP token received
 */
#define USB_DEVCMDSTAT_SETUP(x)                  (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_SETUP_SHIFT)) & USB_DEVCMDSTAT_SETUP_MASK)

#define USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK        (0x200U)
#define USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT       (9U)
/*! FORCE_NEEDCLK - Forces the NEEDCLK output to always be on:
 *  0b0..USB_NEEDCLK has normal function.
 *  0b1..USB_NEEDCLK always 1. Clock will not be stopped in case of suspend.
 */
#define USB_DEVCMDSTAT_FORCE_NEEDCLK(x)          (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK)

#define USB_DEVCMDSTAT_LPM_SUP_MASK              (0x800U)
#define USB_DEVCMDSTAT_LPM_SUP_SHIFT             (11U)
/*! LPM_SUP - LPM Support
 *  0b0..LPM not supported.
 *  0b1..LPM supported.
 */
#define USB_DEVCMDSTAT_LPM_SUP(x)                (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUP_SHIFT)) & USB_DEVCMDSTAT_LPM_SUP_MASK)

#define USB_DEVCMDSTAT_INTONNAK_AO_MASK          (0x1000U)
#define USB_DEVCMDSTAT_INTONNAK_AO_SHIFT         (12U)
/*! INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP
 *  0b0..Only acknowledged packets generate an interrupt
 *  0b1..Both acknowledged and NAKed packets generate interrupts.
 */
#define USB_DEVCMDSTAT_INTONNAK_AO(x)            (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AO_MASK)

#define USB_DEVCMDSTAT_INTONNAK_AI_MASK          (0x2000U)
#define USB_DEVCMDSTAT_INTONNAK_AI_SHIFT         (13U)
/*! INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP
 *  0b0..Only acknowledged packets generate an interrupt
 *  0b1..Both acknowledged and NAKed packets generate interrupts.
 */
#define USB_DEVCMDSTAT_INTONNAK_AI(x)            (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AI_MASK)

#define USB_DEVCMDSTAT_INTONNAK_CO_MASK          (0x4000U)
#define USB_DEVCMDSTAT_INTONNAK_CO_SHIFT         (14U)
/*! INTONNAK_CO - Interrupt on NAK for control OUT EP
 *  0b0..Only acknowledged packets generate an interrupt
 *  0b1..Both acknowledged and NAKed packets generate interrupts.
 */
#define USB_DEVCMDSTAT_INTONNAK_CO(x)            (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CO_MASK)

#define USB_DEVCMDSTAT_INTONNAK_CI_MASK          (0x8000U)
#define USB_DEVCMDSTAT_INTONNAK_CI_SHIFT         (15U)
/*! INTONNAK_CI - Interrupt on NAK for control IN EP
 *  0b0..Only acknowledged packets generate an interrupt
 *  0b1..Both acknowledged and NAKed packets generate interrupts.
 */
#define USB_DEVCMDSTAT_INTONNAK_CI(x)            (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CI_MASK)

#define USB_DEVCMDSTAT_DCON_MASK                 (0x10000U)
#define USB_DEVCMDSTAT_DCON_SHIFT                (16U)
/*! DCON - Device status - connect
 */
#define USB_DEVCMDSTAT_DCON(x)                   (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_SHIFT)) & USB_DEVCMDSTAT_DCON_MASK)

#define USB_DEVCMDSTAT_DSUS_MASK                 (0x20000U)
#define USB_DEVCMDSTAT_DSUS_SHIFT                (17U)
/*! DSUS - Device status - suspend
 */
#define USB_DEVCMDSTAT_DSUS(x)                   (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_SHIFT)) & USB_DEVCMDSTAT_DSUS_MASK)

#define USB_DEVCMDSTAT_LPM_SUS_MASK              (0x80000U)
#define USB_DEVCMDSTAT_LPM_SUS_SHIFT             (19U)
/*! LPM_SUS - Device status - LPM Suspend
 */
#define USB_DEVCMDSTAT_LPM_SUS(x)                (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUS_SHIFT)) & USB_DEVCMDSTAT_LPM_SUS_MASK)

#define USB_DEVCMDSTAT_LPM_REWP_MASK             (0x100000U)
#define USB_DEVCMDSTAT_LPM_REWP_SHIFT            (20U)
/*! LPM_REWP - LPM Remote Wake-up Enabled by USB host
 */
#define USB_DEVCMDSTAT_LPM_REWP(x)               (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_REWP_SHIFT)) & USB_DEVCMDSTAT_LPM_REWP_MASK)

#define USB_DEVCMDSTAT_DCON_C_MASK               (0x1000000U)
#define USB_DEVCMDSTAT_DCON_C_SHIFT              (24U)
/*! DCON_C - Device status - connect change
 */
#define USB_DEVCMDSTAT_DCON_C(x)                 (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_C_SHIFT)) & USB_DEVCMDSTAT_DCON_C_MASK)

#define USB_DEVCMDSTAT_DSUS_C_MASK               (0x2000000U)
#define USB_DEVCMDSTAT_DSUS_C_SHIFT              (25U)
/*! DSUS_C - Device status - suspend change
 */
#define USB_DEVCMDSTAT_DSUS_C(x)                 (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_C_SHIFT)) & USB_DEVCMDSTAT_DSUS_C_MASK)

#define USB_DEVCMDSTAT_DRES_C_MASK               (0x4000000U)
#define USB_DEVCMDSTAT_DRES_C_SHIFT              (26U)
/*! DRES_C - Device status - reset change
 */
#define USB_DEVCMDSTAT_DRES_C(x)                 (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DRES_C_SHIFT)) & USB_DEVCMDSTAT_DRES_C_MASK)

#define USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK        (0x10000000U)
#define USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT       (28U)
#define USB_DEVCMDSTAT_VBUSDEBOUNCED(x)          (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT)) & USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK)
/*! @} */

/*! @name INFO - USB Info */
/*! @{ */

#define USB_INFO_FRAME_NR_MASK                   (0x7FFU)
#define USB_INFO_FRAME_NR_SHIFT                  (0U)
/*! FRAME_NR - Frame number
 */
#define USB_INFO_FRAME_NR(x)                     (((uint32_t)(((uint32_t)(x)) << USB_INFO_FRAME_NR_SHIFT)) & USB_INFO_FRAME_NR_MASK)

#define USB_INFO_ERR_CODE_MASK                   (0x7800U)
#define USB_INFO_ERR_CODE_SHIFT                  (11U)
/*! ERR_CODE - The error code which last occurred:
 *  0b0000..No error
 *  0b0001..PID encoding error
 *  0b0010..PID unknown
 *  0b0011..Packet unexpected
 *  0b0100..Token CRC error
 *  0b0101..Data CRC error
 *  0b0110..Time out
 *  0b0111..Babble
 *  0b1000..Truncated EOP
 *  0b1001..Sent/Received NAK
 *  0b1010..Sent Stall
 *  0b1011..Overrun
 *  0b1100..Sent empty packet
 *  0b1101..Bitstuff error
 *  0b1110..Sync error
 *  0b1111..Wrong data toggle
 */
#define USB_INFO_ERR_CODE(x)                     (((uint32_t)(((uint32_t)(x)) << USB_INFO_ERR_CODE_SHIFT)) & USB_INFO_ERR_CODE_MASK)

#define USB_INFO_MINREV_MASK                     (0xFF0000U)
#define USB_INFO_MINREV_SHIFT                    (16U)
/*! MINREV - Minor Revision.
 */
#define USB_INFO_MINREV(x)                       (((uint32_t)(((uint32_t)(x)) << USB_INFO_MINREV_SHIFT)) & USB_INFO_MINREV_MASK)

#define USB_INFO_MAJREV_MASK                     (0xFF000000U)
#define USB_INFO_MAJREV_SHIFT                    (24U)
/*! MAJREV - Major Revision.
 */
#define USB_INFO_MAJREV(x)                       (((uint32_t)(((uint32_t)(x)) << USB_INFO_MAJREV_SHIFT)) & USB_INFO_MAJREV_MASK)
/*! @} */

/*! @name EPLISTSTART - USB EP Command/Status List start address */
/*! @{ */

#define USB_EPLISTSTART_EP_LIST_MASK             (0xFFFFFF00U)
#define USB_EPLISTSTART_EP_LIST_SHIFT            (8U)
/*! EP_LIST - Start address of the USB EP Command/Status List.
 */
#define USB_EPLISTSTART_EP_LIST(x)               (((uint32_t)(((uint32_t)(x)) << USB_EPLISTSTART_EP_LIST_SHIFT)) & USB_EPLISTSTART_EP_LIST_MASK)
/*! @} */

/*! @name DATABUFSTART - USB Data buffer start address */
/*! @{ */

#define USB_DATABUFSTART_DA_BUF_MASK             (0xFFC00000U)
#define USB_DATABUFSTART_DA_BUF_SHIFT            (22U)
/*! DA_BUF - Start address of the buffer pointer page where all endpoint data buffers are located.
 */
#define USB_DATABUFSTART_DA_BUF(x)               (((uint32_t)(((uint32_t)(x)) << USB_DATABUFSTART_DA_BUF_SHIFT)) & USB_DATABUFSTART_DA_BUF_MASK)
/*! @} */

/*! @name LPM - USB Link Power Management */
/*! @{ */

#define USB_LPM_HIRD_HW_MASK                     (0xFU)
#define USB_LPM_HIRD_HW_SHIFT                    (0U)
/*! HIRD_HW - Host Initiated Resume Duration - hardware
 */
#define USB_LPM_HIRD_HW(x)                       (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_HW_SHIFT)) & USB_LPM_HIRD_HW_MASK)

#define USB_LPM_HIRD_SW_MASK                     (0xF0U)
#define USB_LPM_HIRD_SW_SHIFT                    (4U)
/*! HIRD_SW - Host Initiated Resume Duration - software
 */
#define USB_LPM_HIRD_SW(x)                       (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_SW_SHIFT)) & USB_LPM_HIRD_SW_MASK)

#define USB_LPM_DATA_PENDING_MASK                (0x100U)
#define USB_LPM_DATA_PENDING_SHIFT               (8U)
/*! DATA_PENDING - Data pending
 */
#define USB_LPM_DATA_PENDING(x)                  (((uint32_t)(((uint32_t)(x)) << USB_LPM_DATA_PENDING_SHIFT)) & USB_LPM_DATA_PENDING_MASK)
/*! @} */

/*! @name EPSKIP - USB Endpoint skip */
/*! @{ */

#define USB_EPSKIP_SKIP_MASK                     (0xFFFU)
#define USB_EPSKIP_SKIP_SHIFT                    (0U)
/*! SKIP - Endpoint skip
 */
#define USB_EPSKIP_SKIP(x)                       (((uint32_t)(((uint32_t)(x)) << USB_EPSKIP_SKIP_SHIFT)) & USB_EPSKIP_SKIP_MASK)
/*! @} */

/*! @name EPINUSE - USB Endpoint Buffer in use */
/*! @{ */

#define USB_EPINUSE_BUF_MASK                     (0xFFCU)
#define USB_EPINUSE_BUF_SHIFT                    (2U)
/*! BUF - Buffer in use
 *  0b0000000000..Hardware is accessing buffer 0
 *  0b0000000001..Hardware is accessing buffer 1
 */
#define USB_EPINUSE_BUF(x)                       (((uint32_t)(((uint32_t)(x)) << USB_EPINUSE_BUF_SHIFT)) & USB_EPINUSE_BUF_MASK)
/*! @} */

/*! @name EPBUFCFG - USB Endpoint Buffer Configuration */
/*! @{ */

#define USB_EPBUFCFG_BUF_SB_MASK                 (0xFFCU)
#define USB_EPBUFCFG_BUF_SB_SHIFT                (2U)
/*! BUF_SB - Buffer usage
 *  0b0000000000..Single-buffer
 *  0b0000000001..Double-buffer
 */
#define USB_EPBUFCFG_BUF_SB(x)                   (((uint32_t)(((uint32_t)(x)) << USB_EPBUFCFG_BUF_SB_SHIFT)) & USB_EPBUFCFG_BUF_SB_MASK)
/*! @} */

/*! @name INTSTAT - USB interrupt status */
/*! @{ */

#define USB_INTSTAT_EP0OUT_MASK                  (0x1U)
#define USB_INTSTAT_EP0OUT_SHIFT                 (0U)
/*! EP0OUT - Control EP0 OUT direction
 */
#define USB_INTSTAT_EP0OUT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0OUT_SHIFT)) & USB_INTSTAT_EP0OUT_MASK)

#define USB_INTSTAT_EP0IN_MASK                   (0x2U)
#define USB_INTSTAT_EP0IN_SHIFT                  (1U)
/*! EP0IN - Control EP0 IN direction
 */
#define USB_INTSTAT_EP0IN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0IN_SHIFT)) & USB_INTSTAT_EP0IN_MASK)

#define USB_INTSTAT_EP1OUT_MASK                  (0x4U)
#define USB_INTSTAT_EP1OUT_SHIFT                 (2U)
/*! EP1OUT - EP1 OUT direction
 */
#define USB_INTSTAT_EP1OUT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1OUT_SHIFT)) & USB_INTSTAT_EP1OUT_MASK)

#define USB_INTSTAT_EP1IN_MASK                   (0x8U)
#define USB_INTSTAT_EP1IN_SHIFT                  (3U)
/*! EP1IN - EP1 IN direction
 */
#define USB_INTSTAT_EP1IN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1IN_SHIFT)) & USB_INTSTAT_EP1IN_MASK)

#define USB_INTSTAT_EP2OUT_MASK                  (0x10U)
#define USB_INTSTAT_EP2OUT_SHIFT                 (4U)
/*! EP2OUT - EP2 OUT direction
 */
#define USB_INTSTAT_EP2OUT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2OUT_SHIFT)) & USB_INTSTAT_EP2OUT_MASK)

#define USB_INTSTAT_EP2IN_MASK                   (0x20U)
#define USB_INTSTAT_EP2IN_SHIFT                  (5U)
/*! EP2IN - EP2 IN direction
 */
#define USB_INTSTAT_EP2IN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2IN_SHIFT)) & USB_INTSTAT_EP2IN_MASK)

#define USB_INTSTAT_EP3OUT_MASK                  (0x40U)
#define USB_INTSTAT_EP3OUT_SHIFT                 (6U)
/*! EP3OUT - EP3 OUT direction
 */
#define USB_INTSTAT_EP3OUT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3OUT_SHIFT)) & USB_INTSTAT_EP3OUT_MASK)

#define USB_INTSTAT_EP3IN_MASK                   (0x80U)
#define USB_INTSTAT_EP3IN_SHIFT                  (7U)
/*! EP3IN - EP3 IN direction
 */
#define USB_INTSTAT_EP3IN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3IN_SHIFT)) & USB_INTSTAT_EP3IN_MASK)

#define USB_INTSTAT_EP4OUT_MASK                  (0x100U)
#define USB_INTSTAT_EP4OUT_SHIFT                 (8U)
/*! EP4OUT - EP4 OUT direction
 */
#define USB_INTSTAT_EP4OUT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4OUT_SHIFT)) & USB_INTSTAT_EP4OUT_MASK)

#define USB_INTSTAT_EP4IN_MASK                   (0x200U)
#define USB_INTSTAT_EP4IN_SHIFT                  (9U)
/*! EP4IN - EP4 IN direction
 */
#define USB_INTSTAT_EP4IN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4IN_SHIFT)) & USB_INTSTAT_EP4IN_MASK)

#define USB_INTSTAT_FRAME_INT_MASK               (0x40000000U)
#define USB_INTSTAT_FRAME_INT_SHIFT              (30U)
/*! FRAME_INT - Frame interrupt
 */
#define USB_INTSTAT_FRAME_INT(x)                 (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_FRAME_INT_SHIFT)) & USB_INTSTAT_FRAME_INT_MASK)

#define USB_INTSTAT_DEV_INT_MASK                 (0x80000000U)
#define USB_INTSTAT_DEV_INT_SHIFT                (31U)
/*! DEV_INT - Device status interrupt
 */
#define USB_INTSTAT_DEV_INT(x)                   (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_DEV_INT_SHIFT)) & USB_INTSTAT_DEV_INT_MASK)
/*! @} */

/*! @name INTEN - USB interrupt enable */
/*! @{ */

#define USB_INTEN_EP_INT_EN_MASK                 (0x3FFU)
#define USB_INTEN_EP_INT_EN_SHIFT                (0U)
/*! EP_INT_EN - End point interrupt enable
 */
#define USB_INTEN_EP_INT_EN(x)                   (((uint32_t)(((uint32_t)(x)) << USB_INTEN_EP_INT_EN_SHIFT)) & USB_INTEN_EP_INT_EN_MASK)

#define USB_INTEN_FRAME_INT_EN_MASK              (0x40000000U)
#define USB_INTEN_FRAME_INT_EN_SHIFT             (30U)
/*! FRAME_INT_EN - Frame interrupt enable
 */
#define USB_INTEN_FRAME_INT_EN(x)                (((uint32_t)(((uint32_t)(x)) << USB_INTEN_FRAME_INT_EN_SHIFT)) & USB_INTEN_FRAME_INT_EN_MASK)

#define USB_INTEN_DEV_INT_EN_MASK                (0x80000000U)
#define USB_INTEN_DEV_INT_EN_SHIFT               (31U)
/*! DEV_INT_EN - Device interrupt enable
 */
#define USB_INTEN_DEV_INT_EN(x)                  (((uint32_t)(((uint32_t)(x)) << USB_INTEN_DEV_INT_EN_SHIFT)) & USB_INTEN_DEV_INT_EN_MASK)
/*! @} */

/*! @name INTSETSTAT - USB set interrupt status */
/*! @{ */

#define USB_INTSETSTAT_EP_SET_INT_MASK           (0x3FFU)
#define USB_INTSETSTAT_EP_SET_INT_SHIFT          (0U)
/*! EP_SET_INT - End point set interrupt
 */
#define USB_INTSETSTAT_EP_SET_INT(x)             (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_EP_SET_INT_SHIFT)) & USB_INTSETSTAT_EP_SET_INT_MASK)

#define USB_INTSETSTAT_FRAME_SET_INT_MASK        (0x40000000U)
#define USB_INTSETSTAT_FRAME_SET_INT_SHIFT       (30U)
/*! FRAME_SET_INT - Frame set interrupt
 */
#define USB_INTSETSTAT_FRAME_SET_INT(x)          (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USB_INTSETSTAT_FRAME_SET_INT_MASK)

#define USB_INTSETSTAT_DEV_SET_INT_MASK          (0x80000000U)
#define USB_INTSETSTAT_DEV_SET_INT_SHIFT         (31U)
/*! DEV_SET_INT - Device set interrupt
 */
#define USB_INTSETSTAT_DEV_SET_INT(x)            (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_DEV_SET_INT_SHIFT)) & USB_INTSETSTAT_DEV_SET_INT_MASK)
/*! @} */

/*! @name EPTOGGLE - USB Endpoint toggle */
/*! @{ */

#define USB_EPTOGGLE_TOGGLE_MASK                 (0x3FFU)
#define USB_EPTOGGLE_TOGGLE_SHIFT                (0U)
/*! TOGGLE - Endpoint data toggle
 */
#define USB_EPTOGGLE_TOGGLE(x)                   (((uint32_t)(((uint32_t)(x)) << USB_EPTOGGLE_TOGGLE_SHIFT)) & USB_EPTOGGLE_TOGGLE_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group USB_Register_Masks */


/* USB - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral USB0 base address */
  #define USB0_BASE                                (0x50084000u)
  /** Peripheral USB0 base address */
  #define USB0_BASE_NS                             (0x40084000u)
  /** Peripheral USB0 base pointer */
  #define USB0                                     ((USB_Type *)USB0_BASE)
  /** Peripheral USB0 base pointer */
  #define USB0_NS                                  ((USB_Type *)USB0_BASE_NS)
  /** Array initializer of USB peripheral base addresses */
  #define USB_BASE_ADDRS                           { USB0_BASE }
  /** Array initializer of USB peripheral base pointers */
  #define USB_BASE_PTRS                            { USB0 }
  /** Array initializer of USB peripheral base addresses */
  #define USB_BASE_ADDRS_NS                        { USB0_BASE_NS }
  /** Array initializer of USB peripheral base pointers */
  #define USB_BASE_PTRS_NS                         { USB0_NS }
#else
  /** Peripheral USB0 base address */
  #define USB0_BASE                                (0x40084000u)
  /** Peripheral USB0 base pointer */
  #define USB0                                     ((USB_Type *)USB0_BASE)
  /** Array initializer of USB peripheral base addresses */
  #define USB_BASE_ADDRS                           { USB0_BASE }
  /** Array initializer of USB peripheral base pointers */
  #define USB_BASE_PTRS                            { USB0 }
#endif
/** Interrupt vectors for the USB peripheral type */
#define USB_IRQS                                 { USB0_IRQn }
#define USB_NEEDCLK_IRQS                         { USB0_NEEDCLK_IRQn }

/*!
 * @}
 */ /* end of group USB_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- USBFSH Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup USBFSH_Peripheral_Access_Layer USBFSH Peripheral Access Layer
 * @{
 */

/** USBFSH - Register Layout Typedef */
typedef struct {
  __I  uint32_t HCREVISION;                        /**< Host controller revision, offset: 0x0 */
  __IO uint32_t HCCONTROL;                         /**< Host controller control, offset: 0x4 */
  __IO uint32_t HCCOMMANDSTATUS;                   /**< Host controller command status, offset: 0x8 */
  __IO uint32_t HCINTERRUPTSTATUS;                 /**< Host controller interrupt status, offset: 0xC */
  __IO uint32_t HCINTERRUPTENABLE;                 /**< Host Controller interrupt enable, offset: 0x10 */
  __IO uint32_t HCINTERRUPTDISABLE;                /**< The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt., offset: 0x14 */
  __IO uint32_t HCHCCA;                            /**< Host controller communication area, offset: 0x18 */
  __I  uint32_t HCPERIODCURRENTED;                 /**< Host controller period current endpoint descriptor, offset: 0x1C */
  __IO uint32_t HCCONTROLHEADED;                   /**< Host controller control head endpoint descriptor, offset: 0x20 */
  __IO uint32_t HCCONTROLCURRENTED;                /**< Host controller control current endpoint descriptor, offset: 0x24 */
  __IO uint32_t HCBULKHEADED;                      /**< Host controller bulk head endpoint descriptor, offset: 0x28 */
  __IO uint32_t HCBULKCURRENTED;                   /**< Host controller bulk current endpoint descriptor, offset: 0x2C */
  __I  uint32_t HCDONEHEAD;                        /**< Host controller done head, offset: 0x30 */
  __IO uint32_t HCFMINTERVAL;                      /**< Host controller frame interval, offset: 0x34 */
  __I  uint32_t HCFMREMAINING;                     /**< Host controller frame remaining, offset: 0x38 */
  __I  uint32_t HCFMNUMBER;                        /**< Host controller frame number, offset: 0x3C */
  __IO uint32_t HCPERIODICSTART;                   /**< Host controller periodic start, offset: 0x40 */
  __IO uint32_t HCLSTHRESHOLD;                     /**< Host controller low speed threshold, offset: 0x44 */
  __IO uint32_t HCRHDESCRIPTORA;                   /**< Host controller root hub descriptor A, offset: 0x48 */
  __IO uint32_t HCRHDESCRIPTORB;                   /**< Host controller root hub descriptor B, offset: 0x4C */
  __IO uint32_t HCRHSTATUS;                        /**< , offset: 0x50 */
  __IO uint32_t HCRHPORTSTATUS;                    /**< Host controller root hub port status, offset: 0x54 */
       uint8_t RESERVED_0[4];
  __IO uint32_t PORTMODE;                          /**< Port Mode, offset: 0x5C */
} USBFSH_Type;

/* ----------------------------------------------------------------------------
   -- USBFSH Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup USBFSH_Register_Masks USBFSH Register Masks
 * @{
 */

/*! @name HCREVISION - Host controller revision */
/*! @{ */

#define USBFSH_HCREVISION_REV_MASK               (0xFFU)
#define USBFSH_HCREVISION_REV_SHIFT              (0U)
/*! REV - Revision
 */
#define USBFSH_HCREVISION_REV(x)                 (((uint32_t)(((uint32_t)(x)) << USBFSH_HCREVISION_REV_SHIFT)) & USBFSH_HCREVISION_REV_MASK)
/*! @} */

/*! @name HCCONTROL - Host controller control */
/*! @{ */

#define USBFSH_HCCONTROL_CBSR_MASK               (0x3U)
#define USBFSH_HCCONTROL_CBSR_SHIFT              (0U)
/*! CBSR - ControlBulkServiceRatio.
 */
#define USBFSH_HCCONTROL_CBSR(x)                 (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CBSR_SHIFT)) & USBFSH_HCCONTROL_CBSR_MASK)

#define USBFSH_HCCONTROL_PLE_MASK                (0x4U)
#define USBFSH_HCCONTROL_PLE_SHIFT               (2U)
/*! PLE - PeriodicListEnable.
 */
#define USBFSH_HCCONTROL_PLE(x)                  (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_PLE_SHIFT)) & USBFSH_HCCONTROL_PLE_MASK)

#define USBFSH_HCCONTROL_IE_MASK                 (0x8U)
#define USBFSH_HCCONTROL_IE_SHIFT                (3U)
/*! IE - IsochronousEnable.
 */
#define USBFSH_HCCONTROL_IE(x)                   (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IE_SHIFT)) & USBFSH_HCCONTROL_IE_MASK)

#define USBFSH_HCCONTROL_CLE_MASK                (0x10U)
#define USBFSH_HCCONTROL_CLE_SHIFT               (4U)
/*! CLE - ControlListEnable.
 */
#define USBFSH_HCCONTROL_CLE(x)                  (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CLE_SHIFT)) & USBFSH_HCCONTROL_CLE_MASK)

#define USBFSH_HCCONTROL_BLE_MASK                (0x20U)
#define USBFSH_HCCONTROL_BLE_SHIFT               (5U)
/*! BLE - BulkListEnable This bit is set to enable the processing of the Bulk list in the next Frame.
 */
#define USBFSH_HCCONTROL_BLE(x)                  (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_BLE_SHIFT)) & USBFSH_HCCONTROL_BLE_MASK)

#define USBFSH_HCCONTROL_HCFS_MASK               (0xC0U)
#define USBFSH_HCCONTROL_HCFS_SHIFT              (6U)
/*! HCFS - HostControllerFunctionalState
 *  0b00..USBRESET
 *  0b01..USBRESUME
 *  0b10..USBOPERATIONAL
 *  0b11..USBSUSPEND
 */
#define USBFSH_HCCONTROL_HCFS(x)                 (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_HCFS_SHIFT)) & USBFSH_HCCONTROL_HCFS_MASK)

#define USBFSH_HCCONTROL_IR_MASK                 (0x100U)
#define USBFSH_HCCONTROL_IR_SHIFT                (8U)
/*! IR - InterruptRouting
 */
#define USBFSH_HCCONTROL_IR(x)                   (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IR_SHIFT)) & USBFSH_HCCONTROL_IR_MASK)

#define USBFSH_HCCONTROL_RWC_MASK                (0x200U)
#define USBFSH_HCCONTROL_RWC_SHIFT               (9U)
/*! RWC - RemoteWakeupConnected This bit indicates whether HC supports remote wake-up signaling.
 */
#define USBFSH_HCCONTROL_RWC(x)                  (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWC_SHIFT)) & USBFSH_HCCONTROL_RWC_MASK)

#define USBFSH_HCCONTROL_RWE_MASK                (0x400U)
#define USBFSH_HCCONTROL_RWE_SHIFT               (10U)
/*! RWE - RemoteWakeupEnable This bit is used by HCD to enable or disable the remote wake-up feature
 *    upon the detection of upstream resume signaling.
 */
#define USBFSH_HCCONTROL_RWE(x)                  (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWE_SHIFT)) & USBFSH_HCCONTROL_RWE_MASK)
/*! @} */

/*! @name HCCOMMANDSTATUS - Host controller command status */
/*! @{ */

#define USBFSH_HCCOMMANDSTATUS_HCR_MASK          (0x1U)
#define USBFSH_HCCOMMANDSTATUS_HCR_SHIFT         (0U)
/*! HCR - HostControllerReset
 */
#define USBFSH_HCCOMMANDSTATUS_HCR(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_HCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_HCR_MASK)

#define USBFSH_HCCOMMANDSTATUS_CLF_MASK          (0x2U)
#define USBFSH_HCCOMMANDSTATUS_CLF_SHIFT         (1U)
/*! CLF - ControlListFilled This bit is used to indicate whether there are any TDs on the Control list.
 */
#define USBFSH_HCCOMMANDSTATUS_CLF(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_CLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_CLF_MASK)

#define USBFSH_HCCOMMANDSTATUS_BLF_MASK          (0x4U)
#define USBFSH_HCCOMMANDSTATUS_BLF_SHIFT         (2U)
/*! BLF - BulkListFilled This bit is used to indicate whether there are any TDs on the Bulk list.
 */
#define USBFSH_HCCOMMANDSTATUS_BLF(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_BLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_BLF_MASK)

#define USBFSH_HCCOMMANDSTATUS_OCR_MASK          (0x8U)
#define USBFSH_HCCOMMANDSTATUS_OCR_SHIFT         (3U)
/*! OCR - OwnershipChangeRequest This bit is set by an OS HCD to request a change of control of the HC.
 */
#define USBFSH_HCCOMMANDSTATUS_OCR(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_OCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_OCR_MASK)

#define USBFSH_HCCOMMANDSTATUS_SOC_MASK          (0xC0U)
#define USBFSH_HCCOMMANDSTATUS_SOC_SHIFT         (6U)
/*! SOC - SchedulingOverrunCount These bits are incremented on each scheduling overrun error.
 */
#define USBFSH_HCCOMMANDSTATUS_SOC(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_SOC_SHIFT)) & USBFSH_HCCOMMANDSTATUS_SOC_MASK)
/*! @} */

/*! @name HCINTERRUPTSTATUS - Host controller interrupt status */
/*! @{ */

#define USBFSH_HCINTERRUPTSTATUS_SO_MASK         (0x1U)
#define USBFSH_HCINTERRUPTSTATUS_SO_SHIFT        (0U)
/*! SO - SchedulingOverrun
 */
#define USBFSH_HCINTERRUPTSTATUS_SO(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SO_MASK)

#define USBFSH_HCINTERRUPTSTATUS_WDH_MASK        (0x2U)
#define USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT       (1U)
/*! WDH - WritebackDoneHead
 */
#define USBFSH_HCINTERRUPTSTATUS_WDH(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_WDH_MASK)

#define USBFSH_HCINTERRUPTSTATUS_SF_MASK         (0x4U)
#define USBFSH_HCINTERRUPTSTATUS_SF_SHIFT        (2U)
/*! SF - StartofFrame
 */
#define USBFSH_HCINTERRUPTSTATUS_SF(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SF_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SF_MASK)

#define USBFSH_HCINTERRUPTSTATUS_RD_MASK         (0x8U)
#define USBFSH_HCINTERRUPTSTATUS_RD_SHIFT        (3U)
/*! RD - ResumeDetected
 */
#define USBFSH_HCINTERRUPTSTATUS_RD(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RD_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RD_MASK)

#define USBFSH_HCINTERRUPTSTATUS_UE_MASK         (0x10U)
#define USBFSH_HCINTERRUPTSTATUS_UE_SHIFT        (4U)
/*! UE - UnrecoverableError
 */
#define USBFSH_HCINTERRUPTSTATUS_UE(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_UE_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_UE_MASK)

#define USBFSH_HCINTERRUPTSTATUS_FNO_MASK        (0x20U)
#define USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT       (5U)
/*! FNO - FrameNumberOverflow
 */
#define USBFSH_HCINTERRUPTSTATUS_FNO(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_FNO_MASK)

#define USBFSH_HCINTERRUPTSTATUS_RHSC_MASK       (0x40U)
#define USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT      (6U)
/*! RHSC - RootHubStatusChange This bit is set when the content of HcRhStatus or the content of any
 *    of HcRhPortStatus[NumberofDownstreamPort] has changed.
 */
#define USBFSH_HCINTERRUPTSTATUS_RHSC(x)         (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RHSC_MASK)

#define USBFSH_HCINTERRUPTSTATUS_OC_MASK         (0xFFFFFC00U)
#define USBFSH_HCINTERRUPTSTATUS_OC_SHIFT        (10U)
/*! OC - OwnershipChange
 */
#define USBFSH_HCINTERRUPTSTATUS_OC(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_OC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_OC_MASK)
/*! @} */

/*! @name HCINTERRUPTENABLE - Host Controller interrupt enable */
/*! @{ */

#define USBFSH_HCINTERRUPTENABLE_SO_MASK         (0x1U)
#define USBFSH_HCINTERRUPTENABLE_SO_SHIFT        (0U)
/*! SO - Scheduling Overrun interrupt.
 *  0b0..No effect
 *  0b1..Enables interrupt
 */
#define USBFSH_HCINTERRUPTENABLE_SO(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SO_MASK)

#define USBFSH_HCINTERRUPTENABLE_WDH_MASK        (0x2U)
#define USBFSH_HCINTERRUPTENABLE_WDH_SHIFT       (1U)
/*! WDH - HcDoneHead Writeback interrupt.
 *  0b0..No effect
 *  0b1..Enables interrupt
 */
#define USBFSH_HCINTERRUPTENABLE_WDH(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTENABLE_WDH_MASK)

#define USBFSH_HCINTERRUPTENABLE_SF_MASK         (0x4U)
#define USBFSH_HCINTERRUPTENABLE_SF_SHIFT        (2U)
/*! SF - Start of Frame interrupt.
 *  0b0..No effect
 *  0b1..Enables interrupt
 */
#define USBFSH_HCINTERRUPTENABLE_SF(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SF_MASK)

#define USBFSH_HCINTERRUPTENABLE_RD_MASK         (0x8U)
#define USBFSH_HCINTERRUPTENABLE_RD_SHIFT        (3U)
/*! RD - Resume Detect interrupt.
 *  0b0..No effect
 *  0b1..Enables interrupt
 */
#define USBFSH_HCINTERRUPTENABLE_RD(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RD_MASK)

#define USBFSH_HCINTERRUPTENABLE_UE_MASK         (0x10U)
#define USBFSH_HCINTERRUPTENABLE_UE_SHIFT        (4U)
/*! UE - Unrecoverable Error interrupt.
 *  0b0..No effect
 *  0b1..Enables interrupt
 */
#define USBFSH_HCINTERRUPTENABLE_UE(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_UE_MASK)

#define USBFSH_HCINTERRUPTENABLE_FNO_MASK        (0x20U)
#define USBFSH_HCINTERRUPTENABLE_FNO_SHIFT       (5U)
/*! FNO - Frame Number Overflow interrupt.
 *  0b0..No effect
 *  0b1..Enables interrupt
 */
#define USBFSH_HCINTERRUPTENABLE_FNO(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_FNO_MASK)

#define USBFSH_HCINTERRUPTENABLE_RHSC_MASK       (0x40U)
#define USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT      (6U)
/*! RHSC - Root Hub Status Change interrupt.
 *  0b0..No effect
 *  0b1..Enables interrupt
 */
#define USBFSH_HCINTERRUPTENABLE_RHSC(x)         (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RHSC_MASK)

#define USBFSH_HCINTERRUPTENABLE_OC_MASK         (0x40000000U)
#define USBFSH_HCINTERRUPTENABLE_OC_SHIFT        (30U)
/*! OC - Ownership Change interrupt.
 *  0b0..No effect
 *  0b1..Enables interrupt
 */
#define USBFSH_HCINTERRUPTENABLE_OC(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_OC_MASK)

#define USBFSH_HCINTERRUPTENABLE_MIE_MASK        (0x80000000U)
#define USBFSH_HCINTERRUPTENABLE_MIE_SHIFT       (31U)
/*! MIE - Master Interrupt Enable.
 */
#define USBFSH_HCINTERRUPTENABLE_MIE(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_MIE_MASK)
/*! @} */

/*! @name HCINTERRUPTDISABLE - The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt. */
/*! @{ */

#define USBFSH_HCINTERRUPTDISABLE_SO_MASK        (0x1U)
#define USBFSH_HCINTERRUPTDISABLE_SO_SHIFT       (0U)
/*! SO - Scheduling Overrun interrupt.
 *  0b0..No effect
 *  0b1..Disables interrupt
 */
#define USBFSH_HCINTERRUPTDISABLE_SO(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SO_MASK)

#define USBFSH_HCINTERRUPTDISABLE_WDH_MASK       (0x2U)
#define USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT      (1U)
/*! WDH - HcDoneHead Writeback interrupt.
 *  0b0..No effect
 *  0b1..Disables interrupt
 */
#define USBFSH_HCINTERRUPTDISABLE_WDH(x)         (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_WDH_MASK)

#define USBFSH_HCINTERRUPTDISABLE_SF_MASK        (0x4U)
#define USBFSH_HCINTERRUPTDISABLE_SF_SHIFT       (2U)
/*! SF - Start of Frame interrupt.
 *  0b0..No effect
 *  0b1..Disables interrupt
 */
#define USBFSH_HCINTERRUPTDISABLE_SF(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SF_MASK)

#define USBFSH_HCINTERRUPTDISABLE_RD_MASK        (0x8U)
#define USBFSH_HCINTERRUPTDISABLE_RD_SHIFT       (3U)
/*! RD - Resume Detect interrupt.
 *  0b0..No effect
 *  0b1..Disables interrupt
 */
#define USBFSH_HCINTERRUPTDISABLE_RD(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RD_MASK)

#define USBFSH_HCINTERRUPTDISABLE_UE_MASK        (0x10U)
#define USBFSH_HCINTERRUPTDISABLE_UE_SHIFT       (4U)
/*! UE - Unrecoverable Error interrupt.
 *  0b0..No effect
 *  0b1..Disables interrupt
 */
#define USBFSH_HCINTERRUPTDISABLE_UE(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_UE_MASK)

#define USBFSH_HCINTERRUPTDISABLE_FNO_MASK       (0x20U)
#define USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT      (5U)
/*! FNO - Frame Number Overflow interrupt.
 *  0b0..No effect
 *  0b1..Disables interrupt
 */
#define USBFSH_HCINTERRUPTDISABLE_FNO(x)         (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_FNO_MASK)

#define USBFSH_HCINTERRUPTDISABLE_RHSC_MASK      (0x40U)
#define USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT     (6U)
/*! RHSC - Root Hub Status Change interrupt.
 *  0b0..No effect
 *  0b1..Disables interrupt
 */
#define USBFSH_HCINTERRUPTDISABLE_RHSC(x)        (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RHSC_MASK)

#define USBFSH_HCINTERRUPTDISABLE_OC_MASK        (0x40000000U)
#define USBFSH_HCINTERRUPTDISABLE_OC_SHIFT       (30U)
/*! OC - Ownership Change interrupt.
 *  0b0..No effect
 *  0b1..Disables interrupt
 */
#define USBFSH_HCINTERRUPTDISABLE_OC(x)          (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_OC_MASK)

#define USBFSH_HCINTERRUPTDISABLE_MIE_MASK       (0x80000000U)
#define USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT      (31U)
/*! MIE - A 0 written to this field is ignored by HC.
 *  0b0..No effect
 *  0b1..Disables interrupt
 */
#define USBFSH_HCINTERRUPTDISABLE_MIE(x)         (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_MIE_MASK)
/*! @} */

/*! @name HCHCCA - Host controller communication area */
/*! @{ */

#define USBFSH_HCHCCA_HCCA_MASK                  (0xFFFFFF00U)
#define USBFSH_HCHCCA_HCCA_SHIFT                 (8U)
/*! HCCA - Host Controller Communication Area
 */
#define USBFSH_HCHCCA_HCCA(x)                    (((uint32_t)(((uint32_t)(x)) << USBFSH_HCHCCA_HCCA_SHIFT)) & USBFSH_HCHCCA_HCCA_MASK)
/*! @} */

/*! @name HCPERIODCURRENTED - Host controller period current endpoint descriptor */
/*! @{ */

#define USBFSH_HCPERIODCURRENTED_PCED_MASK       (0xFFFFFFF0U)
#define USBFSH_HCPERIODCURRENTED_PCED_SHIFT      (4U)
/*! PCED - The content of this register is updated by HC after a periodic ED is processed.
 */
#define USBFSH_HCPERIODCURRENTED_PCED(x)         (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODCURRENTED_PCED_SHIFT)) & USBFSH_HCPERIODCURRENTED_PCED_MASK)
/*! @} */

/*! @name HCCONTROLHEADED - Host controller control head endpoint descriptor */
/*! @{ */

#define USBFSH_HCCONTROLHEADED_CHED_MASK         (0xFFFFFFF0U)
#define USBFSH_HCCONTROLHEADED_CHED_SHIFT        (4U)
/*! CHED - HC traverses the Control list starting with the HcControlHeadED pointer.
 */
#define USBFSH_HCCONTROLHEADED_CHED(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLHEADED_CHED_SHIFT)) & USBFSH_HCCONTROLHEADED_CHED_MASK)
/*! @} */

/*! @name HCCONTROLCURRENTED - Host controller control current endpoint descriptor */
/*! @{ */

#define USBFSH_HCCONTROLCURRENTED_CCED_MASK      (0xFFFFFFF0U)
#define USBFSH_HCCONTROLCURRENTED_CCED_SHIFT     (4U)
/*! CCED - ControlCurrentED
 */
#define USBFSH_HCCONTROLCURRENTED_CCED(x)        (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLCURRENTED_CCED_SHIFT)) & USBFSH_HCCONTROLCURRENTED_CCED_MASK)
/*! @} */

/*! @name HCBULKHEADED - Host controller bulk head endpoint descriptor */
/*! @{ */

#define USBFSH_HCBULKHEADED_BHED_MASK            (0xFFFFFFF0U)
#define USBFSH_HCBULKHEADED_BHED_SHIFT           (4U)
/*! BHED - BulkHeadED HC traverses the bulk list starting with the HcBulkHeadED pointer.
 */
#define USBFSH_HCBULKHEADED_BHED(x)              (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKHEADED_BHED_SHIFT)) & USBFSH_HCBULKHEADED_BHED_MASK)
/*! @} */

/*! @name HCBULKCURRENTED - Host controller bulk current endpoint descriptor */
/*! @{ */

#define USBFSH_HCBULKCURRENTED_BCED_MASK         (0xFFFFFFF0U)
#define USBFSH_HCBULKCURRENTED_BCED_SHIFT        (4U)
/*! BCED - BulkCurrentED
 */
#define USBFSH_HCBULKCURRENTED_BCED(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKCURRENTED_BCED_SHIFT)) & USBFSH_HCBULKCURRENTED_BCED_MASK)
/*! @} */

/*! @name HCDONEHEAD - Host controller done head */
/*! @{ */

#define USBFSH_HCDONEHEAD_DH_MASK                (0xFFFFFFF0U)
#define USBFSH_HCDONEHEAD_DH_SHIFT               (4U)
/*! DH - DoneHead When a TD is completed, HC writes the content of HcDoneHead to the NextTD field of the TD.
 */
#define USBFSH_HCDONEHEAD_DH(x)                  (((uint32_t)(((uint32_t)(x)) << USBFSH_HCDONEHEAD_DH_SHIFT)) & USBFSH_HCDONEHEAD_DH_MASK)
/*! @} */

/*! @name HCFMINTERVAL - Host controller frame interval */
/*! @{ */

#define USBFSH_HCFMINTERVAL_FI_MASK              (0x3FFFU)
#define USBFSH_HCFMINTERVAL_FI_SHIFT             (0U)
/*! FI - FrameInterval This specifies the interval between two consecutive SOFs in bit times.
 */
#define USBFSH_HCFMINTERVAL_FI(x)                (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FI_SHIFT)) & USBFSH_HCFMINTERVAL_FI_MASK)

#define USBFSH_HCFMINTERVAL_FSMPS_MASK           (0x7FFF0000U)
#define USBFSH_HCFMINTERVAL_FSMPS_SHIFT          (16U)
/*! FSMPS - FSLargestDataPacket This field specifies a value which is loaded into the Largest Data
 *    Packet Counter at the beginning of each frame.
 */
#define USBFSH_HCFMINTERVAL_FSMPS(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FSMPS_SHIFT)) & USBFSH_HCFMINTERVAL_FSMPS_MASK)

#define USBFSH_HCFMINTERVAL_FIT_MASK             (0x80000000U)
#define USBFSH_HCFMINTERVAL_FIT_SHIFT            (31U)
/*! FIT - FrameIntervalToggle
 */
#define USBFSH_HCFMINTERVAL_FIT(x)               (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FIT_SHIFT)) & USBFSH_HCFMINTERVAL_FIT_MASK)
/*! @} */

/*! @name HCFMREMAINING - Host controller frame remaining */
/*! @{ */

#define USBFSH_HCFMREMAINING_FR_MASK             (0x3FFFU)
#define USBFSH_HCFMREMAINING_FR_SHIFT            (0U)
/*! FR - FrameRemaining
 */
#define USBFSH_HCFMREMAINING_FR(x)               (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FR_SHIFT)) & USBFSH_HCFMREMAINING_FR_MASK)

#define USBFSH_HCFMREMAINING_FRT_MASK            (0x80000000U)
#define USBFSH_HCFMREMAINING_FRT_SHIFT           (31U)
/*! FRT - FrameRemainingToggle
 */
#define USBFSH_HCFMREMAINING_FRT(x)              (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FRT_SHIFT)) & USBFSH_HCFMREMAINING_FRT_MASK)
/*! @} */

/*! @name HCFMNUMBER - Host controller frame number */
/*! @{ */

#define USBFSH_HCFMNUMBER_FN_MASK                (0xFFFFU)
#define USBFSH_HCFMNUMBER_FN_SHIFT               (0U)
/*! FN - FrameNumber
 */
#define USBFSH_HCFMNUMBER_FN(x)                  (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMNUMBER_FN_SHIFT)) & USBFSH_HCFMNUMBER_FN_MASK)
/*! @} */

/*! @name HCPERIODICSTART - Host controller periodic start */
/*! @{ */

#define USBFSH_HCPERIODICSTART_PS_MASK           (0x3FFFU)
#define USBFSH_HCPERIODICSTART_PS_SHIFT          (0U)
/*! PS - PeriodicStart
 */
#define USBFSH_HCPERIODICSTART_PS(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODICSTART_PS_SHIFT)) & USBFSH_HCPERIODICSTART_PS_MASK)
/*! @} */

/*! @name HCLSTHRESHOLD - Host controller low speed threshold */
/*! @{ */

#define USBFSH_HCLSTHRESHOLD_LST_MASK            (0xFFFU)
#define USBFSH_HCLSTHRESHOLD_LST_SHIFT           (0U)
/*! LST - LSThreshold
 */
#define USBFSH_HCLSTHRESHOLD_LST(x)              (((uint32_t)(((uint32_t)(x)) << USBFSH_HCLSTHRESHOLD_LST_SHIFT)) & USBFSH_HCLSTHRESHOLD_LST_MASK)
/*! @} */

/*! @name HCRHDESCRIPTORA - Host controller root hub descriptor A */
/*! @{ */

#define USBFSH_HCRHDESCRIPTORA_NDP_MASK          (0xFFU)
#define USBFSH_HCRHDESCRIPTORA_NDP_SHIFT         (0U)
/*! NDP - NumberDownstreamPorts
 */
#define USBFSH_HCRHDESCRIPTORA_NDP(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NDP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NDP_MASK)

#define USBFSH_HCRHDESCRIPTORA_PSM_MASK          (0x100U)
#define USBFSH_HCRHDESCRIPTORA_PSM_SHIFT         (8U)
/*! PSM - PowerSwitchingMode
 *  0b0..All ports are powered at the same time
 *  0b1..Each port is powered individually.
 */
#define USBFSH_HCRHDESCRIPTORA_PSM(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_PSM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_PSM_MASK)

#define USBFSH_HCRHDESCRIPTORA_NPS_MASK          (0x200U)
#define USBFSH_HCRHDESCRIPTORA_NPS_SHIFT         (9U)
/*! NPS - NoPowerSwitching
 *  0b0..Ports are power switched
 *  0b1..Ports are always powered on when the host controller is powered on
 */
#define USBFSH_HCRHDESCRIPTORA_NPS(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NPS_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NPS_MASK)

#define USBFSH_HCRHDESCRIPTORA_DT_MASK           (0x400U)
#define USBFSH_HCRHDESCRIPTORA_DT_SHIFT          (10U)
/*! DT - DeviceType
 */
#define USBFSH_HCRHDESCRIPTORA_DT(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_DT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_DT_MASK)

#define USBFSH_HCRHDESCRIPTORA_OCPM_MASK         (0x800U)
#define USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT        (11U)
/*! OCPM - OverCurrentProtectionMode This bit describes how the overcurrent status for the root hub ports are reported.
 *  0b0..Over-current status is reported collectively for all downstream ports
 *  0b1..Over-current status is reported on a per-port basis
 */
#define USBFSH_HCRHDESCRIPTORA_OCPM(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_OCPM_MASK)

#define USBFSH_HCRHDESCRIPTORA_NOCP_MASK         (0x1000U)
#define USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT        (12U)
/*! NOCP - NoOverCurrentProtection This bit describes how the overcurrent status for the root hub ports are reported.
 *  0b0..Over-current status is reported collectively for all downstream ports
 *  0b1..No overcurrent protection supported
 */
#define USBFSH_HCRHDESCRIPTORA_NOCP(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NOCP_MASK)

#define USBFSH_HCRHDESCRIPTORA_POTPGT_MASK       (0xFF000000U)
#define USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT      (24U)
/*! POTPGT - PowerOnToPowerGoodTime
 */
#define USBFSH_HCRHDESCRIPTORA_POTPGT(x)         (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_POTPGT_MASK)
/*! @} */

/*! @name HCRHDESCRIPTORB - Host controller root hub descriptor B */
/*! @{ */

#define USBFSH_HCRHDESCRIPTORB_DR_MASK           (0xFFFFU)
#define USBFSH_HCRHDESCRIPTORB_DR_SHIFT          (0U)
/*! DR - DeviceRemovable
 */
#define USBFSH_HCRHDESCRIPTORB_DR(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_DR_SHIFT)) & USBFSH_HCRHDESCRIPTORB_DR_MASK)

#define USBFSH_HCRHDESCRIPTORB_PPCM_MASK         (0xFFFF0000U)
#define USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT        (16U)
/*! PPCM - PortPowerControlMask
 */
#define USBFSH_HCRHDESCRIPTORB_PPCM(x)           (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT)) & USBFSH_HCRHDESCRIPTORB_PPCM_MASK)
/*! @} */

/*! @name HCRHSTATUS -  */
/*! @{ */

#define USBFSH_HCRHSTATUS_LPS_MASK               (0x1U)
#define USBFSH_HCRHSTATUS_LPS_SHIFT              (0U)
/*! LPS - (read) LocalPowerStatus (write) ClearGlobalPower
 */
#define USBFSH_HCRHSTATUS_LPS(x)                 (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPS_SHIFT)) & USBFSH_HCRHSTATUS_LPS_MASK)

#define USBFSH_HCRHSTATUS_OCI_MASK               (0x2U)
#define USBFSH_HCRHSTATUS_OCI_SHIFT              (1U)
/*! OCI - OverCurrentIndicator
 */
#define USBFSH_HCRHSTATUS_OCI(x)                 (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCI_SHIFT)) & USBFSH_HCRHSTATUS_OCI_MASK)

#define USBFSH_HCRHSTATUS_DRWE_MASK              (0x8000U)
#define USBFSH_HCRHSTATUS_DRWE_SHIFT             (15U)
/*! DRWE - (read) DeviceRemoteWakeupEnable (Write) SetRemoteWakeupEnable
 *  0b0..ConnectStatusChange is not a remote wakeup event
 *  0b1..ConnectStatusChange is a remote wakeup event
 */
#define USBFSH_HCRHSTATUS_DRWE(x)                (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_DRWE_SHIFT)) & USBFSH_HCRHSTATUS_DRWE_MASK)

#define USBFSH_HCRHSTATUS_LPSC_MASK              (0x10000U)
#define USBFSH_HCRHSTATUS_LPSC_SHIFT             (16U)
/*! LPSC - (read) LocalPowerStatusChange(Write) SetGlobalPower .
 */
#define USBFSH_HCRHSTATUS_LPSC(x)                (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPSC_SHIFT)) & USBFSH_HCRHSTATUS_LPSC_MASK)

#define USBFSH_HCRHSTATUS_OCIC_MASK              (0x20000U)
#define USBFSH_HCRHSTATUS_OCIC_SHIFT             (17U)
/*! OCIC - OverCurrentIndicatorChange
 */
#define USBFSH_HCRHSTATUS_OCIC(x)                (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCIC_SHIFT)) & USBFSH_HCRHSTATUS_OCIC_MASK)

#define USBFSH_HCRHSTATUS_CRWE_MASK              (0x80000000U)
#define USBFSH_HCRHSTATUS_CRWE_SHIFT             (31U)
/*! CRWE - (write) ClearRemoteWakeupEnable .
 */
#define USBFSH_HCRHSTATUS_CRWE(x)                (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_CRWE_SHIFT)) & USBFSH_HCRHSTATUS_CRWE_MASK)
/*! @} */

/*! @name HCRHPORTSTATUS - Host controller root hub port status */
/*! @{ */

#define USBFSH_HCRHPORTSTATUS_CCS_MASK           (0x1U)
#define USBFSH_HCRHPORTSTATUS_CCS_SHIFT          (0U)
/*! CCS - CurrentConnectStatus
 *  0b0..Device is not connected
 *  0b1..Device is connected
 */
#define USBFSH_HCRHPORTSTATUS_CCS(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CCS_SHIFT)) & USBFSH_HCRHPORTSTATUS_CCS_MASK)

#define USBFSH_HCRHPORTSTATUS_PES_MASK           (0x2U)
#define USBFSH_HCRHPORTSTATUS_PES_SHIFT          (1U)
/*! PES - (Read)PortEnableStatus
 *  0b0..Port is disabled
 *  0b1..Port is enabled
 */
#define USBFSH_HCRHPORTSTATUS_PES(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PES_SHIFT)) & USBFSH_HCRHPORTSTATUS_PES_MASK)

#define USBFSH_HCRHPORTSTATUS_PSS_MASK           (0x4U)
#define USBFSH_HCRHPORTSTATUS_PSS_SHIFT          (2U)
/*! PSS - (Read) PortSuspendStatus
 *  0b0..Port is not suspended
 *  0b1..Port is suspended
 */
#define USBFSH_HCRHPORTSTATUS_PSS(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSS_MASK)

#define USBFSH_HCRHPORTSTATUS_POCI_MASK          (0x8U)
#define USBFSH_HCRHPORTSTATUS_POCI_SHIFT         (3U)
/*! POCI - (read) PortOverCurrentIndicator
 *  0b0..Overcurrent condition is not detected
 *  0b1..Overcurrent condition is detected
 */
#define USBFSH_HCRHPORTSTATUS_POCI(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_POCI_SHIFT)) & USBFSH_HCRHPORTSTATUS_POCI_MASK)

#define USBFSH_HCRHPORTSTATUS_PRS_MASK           (0x10U)
#define USBFSH_HCRHPORTSTATUS_PRS_SHIFT          (4U)
/*! PRS - (read) PortResetStatus When this bit is set by a write to SetPortReset, port reset signaling is asserted.
 *  0b0..Port reset signal is not active
 *  0b1..Port reset signal is active
 */
#define USBFSH_HCRHPORTSTATUS_PRS(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRS_MASK)

#define USBFSH_HCRHPORTSTATUS_PPS_MASK           (0x100U)
#define USBFSH_HCRHPORTSTATUS_PPS_SHIFT          (8U)
/*! PPS - (read) PortPowerStatus
 *  0b0..Port power is off
 *  0b1..Port power is on
 */
#define USBFSH_HCRHPORTSTATUS_PPS(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PPS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PPS_MASK)

#define USBFSH_HCRHPORTSTATUS_LSDA_MASK          (0x200U)
#define USBFSH_HCRHPORTSTATUS_LSDA_SHIFT         (9U)
/*! LSDA - (read) LowSpeedDeviceAttached
 *  0b0..Full speed device is attached
 *  0b1..Low speed device is attached
 */
#define USBFSH_HCRHPORTSTATUS_LSDA(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_LSDA_SHIFT)) & USBFSH_HCRHPORTSTATUS_LSDA_MASK)

#define USBFSH_HCRHPORTSTATUS_CSC_MASK           (0x10000U)
#define USBFSH_HCRHPORTSTATUS_CSC_SHIFT          (16U)
/*! CSC - ConnectStatusChange
 *  0b0..CurrentConnectStatus has not changed
 *  0b1..CurrentConnectStatus has changed
 */
#define USBFSH_HCRHPORTSTATUS_CSC(x)             (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_CSC_MASK)

#define USBFSH_HCRHPORTSTATUS_PESC_MASK          (0x20000U)
#define USBFSH_HCRHPORTSTATUS_PESC_SHIFT         (17U)
/*! PESC - PortEnableStatusChange
 *  0b0..PortEnableStatus has not changed
 *  0b1..PortEnableStatus has changed
 */
#define USBFSH_HCRHPORTSTATUS_PESC(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PESC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PESC_MASK)

#define USBFSH_HCRHPORTSTATUS_PSSC_MASK          (0x40000U)
#define USBFSH_HCRHPORTSTATUS_PSSC_SHIFT         (18U)
/*! PSSC - PortSuspendStatusChange
 *  0b0..Resume sequence is not complete
 *  0b1..Resume sequence is complete
 */
#define USBFSH_HCRHPORTSTATUS_PSSC(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSSC_MASK)

#define USBFSH_HCRHPORTSTATUS_OCIC_MASK          (0x80000U)
#define USBFSH_HCRHPORTSTATUS_OCIC_SHIFT         (19U)
/*! OCIC - PortOverCurrentIndicatorChange
 *  0b0..PortOverCurrentIndicator has not changed
 *  0b1..PortOverCurrentIndicator has changed
 */
#define USBFSH_HCRHPORTSTATUS_OCIC(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_OCIC_SHIFT)) & USBFSH_HCRHPORTSTATUS_OCIC_MASK)

#define USBFSH_HCRHPORTSTATUS_PRSC_MASK          (0x100000U)
#define USBFSH_HCRHPORTSTATUS_PRSC_SHIFT         (20U)
/*! PRSC - PortResetStatusChange
 *  0b0..Port reset is not complete
 *  0b1..Port reset is complete
 */
#define USBFSH_HCRHPORTSTATUS_PRSC(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRSC_MASK)
/*! @} */

/*! @name PORTMODE - Port Mode */
/*! @{ */

#define USBFSH_PORTMODE_ID_MASK                  (0x1U)
#define USBFSH_PORTMODE_ID_SHIFT                 (0U)
/*! ID - Port ID pin value.
 */
#define USBFSH_PORTMODE_ID(x)                    (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_SHIFT)) & USBFSH_PORTMODE_ID_MASK)

#define USBFSH_PORTMODE_ID_EN_MASK               (0x100U)
#define USBFSH_PORTMODE_ID_EN_SHIFT              (8U)
/*! ID_EN - Port ID pin pull-up enable.
 */
#define USBFSH_PORTMODE_ID_EN(x)                 (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_EN_SHIFT)) & USBFSH_PORTMODE_ID_EN_MASK)

#define USBFSH_PORTMODE_DEV_ENABLE_MASK          (0x10000U)
#define USBFSH_PORTMODE_DEV_ENABLE_SHIFT         (16U)
/*! DEV_ENABLE - Device Enable
 *  0b0..Device
 *  0b1..Host
 */
#define USBFSH_PORTMODE_DEV_ENABLE(x)            (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBFSH_PORTMODE_DEV_ENABLE_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group USBFSH_Register_Masks */


/* USBFSH - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral USBFSH base address */
  #define USBFSH_BASE                              (0x500A2000u)
  /** Peripheral USBFSH base address */
  #define USBFSH_BASE_NS                           (0x400A2000u)
  /** Peripheral USBFSH base pointer */
  #define USBFSH                                   ((USBFSH_Type *)USBFSH_BASE)
  /** Peripheral USBFSH base pointer */
  #define USBFSH_NS                                ((USBFSH_Type *)USBFSH_BASE_NS)
  /** Array initializer of USBFSH peripheral base addresses */
  #define USBFSH_BASE_ADDRS                        { USBFSH_BASE }
  /** Array initializer of USBFSH peripheral base pointers */
  #define USBFSH_BASE_PTRS                         { USBFSH }
  /** Array initializer of USBFSH peripheral base addresses */
  #define USBFSH_BASE_ADDRS_NS                     { USBFSH_BASE_NS }
  /** Array initializer of USBFSH peripheral base pointers */
  #define USBFSH_BASE_PTRS_NS                      { USBFSH_NS }
#else
  /** Peripheral USBFSH base address */
  #define USBFSH_BASE                              (0x400A2000u)
  /** Peripheral USBFSH base pointer */
  #define USBFSH                                   ((USBFSH_Type *)USBFSH_BASE)
  /** Array initializer of USBFSH peripheral base addresses */
  #define USBFSH_BASE_ADDRS                        { USBFSH_BASE }
  /** Array initializer of USBFSH peripheral base pointers */
  #define USBFSH_BASE_PTRS                         { USBFSH }
#endif
/** Interrupt vectors for the USBFSH peripheral type */
#define USBFSH_IRQS                              { USB0_IRQn }
#define USBFSH_NEEDCLK_IRQS                      { USB0_NEEDCLK_IRQn }

/*!
 * @}
 */ /* end of group USBFSH_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- UTICK Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer
 * @{
 */

/** UTICK - Register Layout Typedef */
typedef struct {
  __IO uint32_t CTRL;                              /**< Control, offset: 0x0 */
  __IO uint32_t STAT;                              /**< Status, offset: 0x4 */
  __IO uint32_t CFG;                               /**< Capture Configuration, offset: 0x8 */
  __O  uint32_t CAPCLR;                            /**< Capture Clear, offset: 0xC */
  __I  uint32_t CAP[4];                            /**< Capture, array offset: 0x10, array step: 0x4 */
} UTICK_Type;

/* ----------------------------------------------------------------------------
   -- UTICK Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup UTICK_Register_Masks UTICK Register Masks
 * @{
 */

/*! @name CTRL - Control */
/*! @{ */

#define UTICK_CTRL_DELAYVAL_MASK                 (0x7FFFFFFFU)
#define UTICK_CTRL_DELAYVAL_SHIFT                (0U)
/*! DELAYVAL - Tick interval
 */
#define UTICK_CTRL_DELAYVAL(x)                   (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK)

#define UTICK_CTRL_REPEAT_MASK                   (0x80000000U)
#define UTICK_CTRL_REPEAT_SHIFT                  (31U)
/*! REPEAT - Repeat delay
 *  0b0..One-time delay
 *  0b1..Delay repeats continuously
 */
#define UTICK_CTRL_REPEAT(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK)
/*! @} */

/*! @name STAT - Status */
/*! @{ */

#define UTICK_STAT_INTR_MASK                     (0x1U)
#define UTICK_STAT_INTR_SHIFT                    (0U)
/*! INTR - Interrupt flag
 *  0b0..No interrupt is pending
 *  0b1..An interrupt is pending
 */
#define UTICK_STAT_INTR(x)                       (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK)

#define UTICK_STAT_ACTIVE_MASK                   (0x2U)
#define UTICK_STAT_ACTIVE_SHIFT                  (1U)
/*! ACTIVE - Timer active flag
 *  0b0..The Micro-Tick Timer is not active (stopped)
 *  0b1..The Micro-Tick Timer is currently active
 */
#define UTICK_STAT_ACTIVE(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK)
/*! @} */

/*! @name CFG - Capture Configuration */
/*! @{ */

#define UTICK_CFG_CAPEN0_MASK                    (0x1U)
#define UTICK_CFG_CAPEN0_SHIFT                   (0U)
/*! CAPEN0 - Enable Capture 0
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define UTICK_CFG_CAPEN0(x)                      (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK)

#define UTICK_CFG_CAPEN1_MASK                    (0x2U)
#define UTICK_CFG_CAPEN1_SHIFT                   (1U)
/*! CAPEN1 - Enable Capture 1
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define UTICK_CFG_CAPEN1(x)                      (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK)

#define UTICK_CFG_CAPEN2_MASK                    (0x4U)
#define UTICK_CFG_CAPEN2_SHIFT                   (2U)
/*! CAPEN2 - Enable Capture 2
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define UTICK_CFG_CAPEN2(x)                      (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK)

#define UTICK_CFG_CAPEN3_MASK                    (0x8U)
#define UTICK_CFG_CAPEN3_SHIFT                   (3U)
/*! CAPEN3 - Enable Capture 3
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define UTICK_CFG_CAPEN3(x)                      (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK)

#define UTICK_CFG_CAPPOL0_MASK                   (0x100U)
#define UTICK_CFG_CAPPOL0_SHIFT                  (8U)
/*! CAPPOL0 - Capture Polarity 0
 *  0b0..Positive edge capture
 *  0b1..Negative edge capture
 */
#define UTICK_CFG_CAPPOL0(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK)

#define UTICK_CFG_CAPPOL1_MASK                   (0x200U)
#define UTICK_CFG_CAPPOL1_SHIFT                  (9U)
/*! CAPPOL1 - Capture Polarity 1
 *  0b0..Positive edge capture
 *  0b1..Negative edge capture
 */
#define UTICK_CFG_CAPPOL1(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK)

#define UTICK_CFG_CAPPOL2_MASK                   (0x400U)
#define UTICK_CFG_CAPPOL2_SHIFT                  (10U)
/*! CAPPOL2 - Capture Polarity 2
 *  0b0..Positive edge capture
 *  0b1..Negative edge capture
 */
#define UTICK_CFG_CAPPOL2(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK)

#define UTICK_CFG_CAPPOL3_MASK                   (0x800U)
#define UTICK_CFG_CAPPOL3_SHIFT                  (11U)
/*! CAPPOL3 - Capture Polarity 3
 *  0b0..Positive edge capture
 *  0b1..Negative edge capture
 */
#define UTICK_CFG_CAPPOL3(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK)
/*! @} */

/*! @name CAPCLR - Capture Clear */
/*! @{ */

#define UTICK_CAPCLR_CAPCLR0_MASK                (0x1U)
#define UTICK_CAPCLR_CAPCLR0_SHIFT               (0U)
/*! CAPCLR0 - Clear capture 0
 *  0b0..Does nothing
 *  0b1..Write 1 to clear the CAP0 register value
 */
#define UTICK_CAPCLR_CAPCLR0(x)                  (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK)

#define UTICK_CAPCLR_CAPCLR1_MASK                (0x2U)
#define UTICK_CAPCLR_CAPCLR1_SHIFT               (1U)
/*! CAPCLR1 - Clear capture 1
 *  0b0..Does nothing
 *  0b1..Write 1 to clear the CAP1 register value
 */
#define UTICK_CAPCLR_CAPCLR1(x)                  (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK)

#define UTICK_CAPCLR_CAPCLR2_MASK                (0x4U)
#define UTICK_CAPCLR_CAPCLR2_SHIFT               (2U)
/*! CAPCLR2 - Clear capture 2
 *  0b0..Does nothing
 *  0b1..Write 1 to clear the CAP2 register value
 */
#define UTICK_CAPCLR_CAPCLR2(x)                  (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK)

#define UTICK_CAPCLR_CAPCLR3_MASK                (0x8U)
#define UTICK_CAPCLR_CAPCLR3_SHIFT               (3U)
/*! CAPCLR3 - Clear capture 3
 *  0b0..Does nothing
 *  0b1..Write 1 to clear the CAP3 register value
 */
#define UTICK_CAPCLR_CAPCLR3(x)                  (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK)
/*! @} */

/*! @name CAP - Capture */
/*! @{ */

#define UTICK_CAP_CAP_VALUE_MASK                 (0x7FFFFFFFU)
#define UTICK_CAP_CAP_VALUE_SHIFT                (0U)
/*! CAP_VALUE - Captured value for the related capture event
 */
#define UTICK_CAP_CAP_VALUE(x)                   (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK)

#define UTICK_CAP_VALID_MASK                     (0x80000000U)
#define UTICK_CAP_VALID_SHIFT                    (31U)
/*! VALID - Captured value is valid
 *  0b0..A valid value has been not been captured
 *  0b1..A valid value has been captured, based on a transition of the related UTICK_CAPn pin
 */
#define UTICK_CAP_VALID(x)                       (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK)
/*! @} */

/* The count of UTICK_CAP */
#define UTICK_CAP_COUNT                          (4U)


/*!
 * @}
 */ /* end of group UTICK_Register_Masks */


/* UTICK - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral UTICK0 base address */
  #define UTICK0_BASE                              (0x5000E000u)
  /** Peripheral UTICK0 base address */
  #define UTICK0_BASE_NS                           (0x4000E000u)
  /** Peripheral UTICK0 base pointer */
  #define UTICK0                                   ((UTICK_Type *)UTICK0_BASE)
  /** Peripheral UTICK0 base pointer */
  #define UTICK0_NS                                ((UTICK_Type *)UTICK0_BASE_NS)
  /** Array initializer of UTICK peripheral base addresses */
  #define UTICK_BASE_ADDRS                         { UTICK0_BASE }
  /** Array initializer of UTICK peripheral base pointers */
  #define UTICK_BASE_PTRS                          { UTICK0 }
  /** Array initializer of UTICK peripheral base addresses */
  #define UTICK_BASE_ADDRS_NS                      { UTICK0_BASE_NS }
  /** Array initializer of UTICK peripheral base pointers */
  #define UTICK_BASE_PTRS_NS                       { UTICK0_NS }
#else
  /** Peripheral UTICK0 base address */
  #define UTICK0_BASE                              (0x4000E000u)
  /** Peripheral UTICK0 base pointer */
  #define UTICK0                                   ((UTICK_Type *)UTICK0_BASE)
  /** Array initializer of UTICK peripheral base addresses */
  #define UTICK_BASE_ADDRS                         { UTICK0_BASE }
  /** Array initializer of UTICK peripheral base pointers */
  #define UTICK_BASE_PTRS                          { UTICK0 }
#endif
/** Interrupt vectors for the UTICK peripheral type */
#define UTICK_IRQS                               { UTICK0_IRQn }

/*!
 * @}
 */ /* end of group UTICK_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- VREF Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
 * @{
 */

/** VREF - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< VREF Version ID, offset: 0x0 */
       uint32_t PARAM;                             /**< VREF Parameter, offset: 0x4 */
  __IO uint32_t CSR;                               /**< VREF Control and Status Register, offset: 0x8 */
       uint8_t RESERVED_0[4];
  __IO uint32_t UTRIM;                             /**< VREF User Trim, offset: 0x10 */
       uint8_t RESERVED_1[8];
  __IO uint32_t TEST_UNLOCK;                       /**< Unlock test registers, offset: 0x1C */
       uint8_t RESERVED_2[4];
  __IO uint32_t TRIM0;                             /**< VREF Test Trim 0, offset: 0x24 */
  __IO uint32_t TRIM1;                             /**< VREF Test Trim 1, offset: 0x28 */
} VREF_Type;

/* ----------------------------------------------------------------------------
   -- VREF Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup VREF_Register_Masks VREF Register Masks
 * @{
 */

/*! @name VERID - VREF Version ID */
/*! @{ */

#define VREF_VERID_FEATURE_MASK                  (0xFFFFU)
#define VREF_VERID_FEATURE_SHIFT                 (0U)
/*! FEATURE - FEATURE
 */
#define VREF_VERID_FEATURE(x)                    (((uint32_t)(((uint32_t)(x)) << VREF_VERID_FEATURE_SHIFT)) & VREF_VERID_FEATURE_MASK)

#define VREF_VERID_MINOR_MASK                    (0xFF0000U)
#define VREF_VERID_MINOR_SHIFT                   (16U)
/*! MINOR - MINOR
 */
#define VREF_VERID_MINOR(x)                      (((uint32_t)(((uint32_t)(x)) << VREF_VERID_MINOR_SHIFT)) & VREF_VERID_MINOR_MASK)

#define VREF_VERID_MAJOR_MASK                    (0xFF000000U)
#define VREF_VERID_MAJOR_SHIFT                   (24U)
/*! MAJOR - MAJOR
 */
#define VREF_VERID_MAJOR(x)                      (((uint32_t)(((uint32_t)(x)) << VREF_VERID_MAJOR_SHIFT)) & VREF_VERID_MAJOR_MASK)
/*! @} */

/*! @name CSR - VREF Control and Status Register */
/*! @{ */

#define VREF_CSR_HCBGEN_MASK                     (0x1U)
#define VREF_CSR_HCBGEN_SHIFT                    (0U)
/*! HCBGEN - HC Bandgap enabled
 *  0b0..HC Bandgap is disabled
 *  0b1..HC Bandgap is enabled
 */
#define VREF_CSR_HCBGEN(x)                       (((uint32_t)(((uint32_t)(x)) << VREF_CSR_HCBGEN_SHIFT)) & VREF_CSR_HCBGEN_MASK)

#define VREF_CSR_LPBGEN_MASK                     (0x2U)
#define VREF_CSR_LPBGEN_SHIFT                    (1U)
/*! LPBGEN - Low Power Bandgap enable
 *  0b0..LP Bandgap is disabled
 *  0b1..LP Bandgap is enabled
 */
#define VREF_CSR_LPBGEN(x)                       (((uint32_t)(((uint32_t)(x)) << VREF_CSR_LPBGEN_SHIFT)) & VREF_CSR_LPBGEN_MASK)

#define VREF_CSR_LPBG_BUF_EN_MASK                (0x4U)
#define VREF_CSR_LPBG_BUF_EN_SHIFT               (2U)
/*! LPBG_BUF_EN
 *  0b0..disable
 *  0b1..enable
 */
#define VREF_CSR_LPBG_BUF_EN(x)                  (((uint32_t)(((uint32_t)(x)) << VREF_CSR_LPBG_BUF_EN_SHIFT)) & VREF_CSR_LPBG_BUF_EN_MASK)

#define VREF_CSR_CHOPEN_MASK                     (0x8U)
#define VREF_CSR_CHOPEN_SHIFT                    (3U)
/*! CHOPEN - Chop oscillator enable. When set, the internal chopping operation is enabled and the
 *    internal analog offset will be minimized.
 *  0b0..Chop oscillator is disabled.
 *  0b1..Chop oscillator is enabled.
 */
#define VREF_CSR_CHOPEN(x)                       (((uint32_t)(((uint32_t)(x)) << VREF_CSR_CHOPEN_SHIFT)) & VREF_CSR_CHOPEN_MASK)

#define VREF_CSR_ICOMPEN_MASK                    (0x10U)
#define VREF_CSR_ICOMPEN_SHIFT                   (4U)
/*! ICOMPEN - Second order curvature compensation enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define VREF_CSR_ICOMPEN(x)                      (((uint32_t)(((uint32_t)(x)) << VREF_CSR_ICOMPEN_SHIFT)) & VREF_CSR_ICOMPEN_MASK)

#define VREF_CSR_REGEN_MASK                      (0x20U)
#define VREF_CSR_REGEN_SHIFT                     (5U)
/*! REGEN - Regulator enable
 *  0b0..Internal 1.75 V regulator is disabled.
 *  0b1..Internal 1.75 V regulator is enabled.
 */
#define VREF_CSR_REGEN(x)                        (((uint32_t)(((uint32_t)(x)) << VREF_CSR_REGEN_SHIFT)) & VREF_CSR_REGEN_MASK)

#define VREF_CSR_REFCHSELN_EN_MASK               (0x40U)
#define VREF_CSR_REFCHSELN_EN_SHIFT              (6U)
/*! REFCHSELN_EN
 *  0b0..disable
 *  0b1..enable
 */
#define VREF_CSR_REFCHSELN_EN(x)                 (((uint32_t)(((uint32_t)(x)) << VREF_CSR_REFCHSELN_EN_SHIFT)) & VREF_CSR_REFCHSELN_EN_MASK)

#define VREF_CSR_REFCHSELP_EN_MASK               (0x80U)
#define VREF_CSR_REFCHSELP_EN_SHIFT              (7U)
/*! REFCHSELP_EN
 *  0b0..disable
 *  0b1..enable
 */
#define VREF_CSR_REFCHSELP_EN(x)                 (((uint32_t)(((uint32_t)(x)) << VREF_CSR_REFCHSELP_EN_SHIFT)) & VREF_CSR_REFCHSELP_EN_MASK)

#define VREF_CSR_VRSEL_MASK                      (0x300U)
#define VREF_CSR_VRSEL_SHIFT                     (8U)
/*! VRSEL
 *  0b00..Internal bandgap
 *  0b01..Low power buffered 1v
 *  0b10..Buffer 2.1v output
 */
#define VREF_CSR_VRSEL(x)                        (((uint32_t)(((uint32_t)(x)) << VREF_CSR_VRSEL_SHIFT)) & VREF_CSR_VRSEL_MASK)

#define VREF_CSR_REFL_GRD_SEL_MASK               (0x400U)
#define VREF_CSR_REFL_GRD_SEL_SHIFT              (10U)
/*! REFL_GRD_SEL
 *  0b0..vrefl_3v
 *  0b1..vssa
 */
#define VREF_CSR_REFL_GRD_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << VREF_CSR_REFL_GRD_SEL_SHIFT)) & VREF_CSR_REFL_GRD_SEL_MASK)

#define VREF_CSR_HI_PWR_LV_MASK                  (0x800U)
#define VREF_CSR_HI_PWR_LV_SHIFT                 (11U)
#define VREF_CSR_HI_PWR_LV(x)                    (((uint32_t)(((uint32_t)(x)) << VREF_CSR_HI_PWR_LV_SHIFT)) & VREF_CSR_HI_PWR_LV_MASK)

#define VREF_CSR_BUF21EN_MASK                    (0x10000U)
#define VREF_CSR_BUF21EN_SHIFT                   (16U)
/*! Buf21EN - Internal buf21 Enable
 *  0b0..buf21 is disabled
 *  0b1..buf21 is enabled
 */
#define VREF_CSR_BUF21EN(x)                      (((uint32_t)(((uint32_t)(x)) << VREF_CSR_BUF21EN_SHIFT)) & VREF_CSR_BUF21EN_MASK)

#define VREF_CSR_VREFST_MASK                     (0x80000000U)
#define VREF_CSR_VREFST_SHIFT                    (31U)
/*! VREFST - Internal HC Voltage Reference stable
 *  0b0..The module is disabled or not stable.
 *  0b1..The module is stable.
 */
#define VREF_CSR_VREFST(x)                       (((uint32_t)(((uint32_t)(x)) << VREF_CSR_VREFST_SHIFT)) & VREF_CSR_VREFST_MASK)
/*! @} */

/*! @name UTRIM - VREF User Trim */
/*! @{ */

#define VREF_UTRIM_TRIM2V1_MASK                  (0xFU)
#define VREF_UTRIM_TRIM2V1_SHIFT                 (0U)
/*! TRIM2V1 - VREF 2.1V Trim Bits
 */
#define VREF_UTRIM_TRIM2V1(x)                    (((uint32_t)(((uint32_t)(x)) << VREF_UTRIM_TRIM2V1_SHIFT)) & VREF_UTRIM_TRIM2V1_MASK)

#define VREF_UTRIM_VREFTRIM_MASK                 (0x3F00U)
#define VREF_UTRIM_VREFTRIM_SHIFT                (8U)
/*! VREFTRIM - VREF Trim bits
 */
#define VREF_UTRIM_VREFTRIM(x)                   (((uint32_t)(((uint32_t)(x)) << VREF_UTRIM_VREFTRIM_SHIFT)) & VREF_UTRIM_VREFTRIM_MASK)
/*! @} */

/*! @name TEST_UNLOCK - Unlock test registers */
/*! @{ */

#define VREF_TEST_UNLOCK_TEST_UNLOCK_MASK        (0x1U)
#define VREF_TEST_UNLOCK_TEST_UNLOCK_SHIFT       (0U)
/*! test_unlock - Test_unlock status bit
 *  0b0..Lock read/write into test register
 *  0b1..Unlock read/write into test register
 */
#define VREF_TEST_UNLOCK_TEST_UNLOCK(x)          (((uint32_t)(((uint32_t)(x)) << VREF_TEST_UNLOCK_TEST_UNLOCK_SHIFT)) & VREF_TEST_UNLOCK_TEST_UNLOCK_MASK)

#define VREF_TEST_UNLOCK_TEST_UNLOCK_VALUE_MASK  (0xFFFEU)
#define VREF_TEST_UNLOCK_TEST_UNLOCK_VALUE_SHIFT (1U)
/*! test_unlock_value - Test unlock value
 */
#define VREF_TEST_UNLOCK_TEST_UNLOCK_VALUE(x)    (((uint32_t)(((uint32_t)(x)) << VREF_TEST_UNLOCK_TEST_UNLOCK_VALUE_SHIFT)) & VREF_TEST_UNLOCK_TEST_UNLOCK_VALUE_MASK)
/*! @} */

/*! @name TRIM0 - VREF Test Trim 0 */
/*! @{ */

#define VREF_TRIM0_COMPLSB_MASK                  (0x7U)
#define VREF_TRIM0_COMPLSB_SHIFT                 (0U)
/*! COMPLSB - COMPLSB
 */
#define VREF_TRIM0_COMPLSB(x)                    (((uint32_t)(((uint32_t)(x)) << VREF_TRIM0_COMPLSB_SHIFT)) & VREF_TRIM0_COMPLSB_MASK)

#define VREF_TRIM0_COMPMSB_MASK                  (0xE0U)
#define VREF_TRIM0_COMPMSB_SHIFT                 (5U)
/*! COMPMSB - COMPMSB
 */
#define VREF_TRIM0_COMPMSB(x)                    (((uint32_t)(((uint32_t)(x)) << VREF_TRIM0_COMPMSB_SHIFT)) & VREF_TRIM0_COMPMSB_MASK)

#define VREF_TRIM0_BPLSB_MASK                    (0xF00U)
#define VREF_TRIM0_BPLSB_SHIFT                   (8U)
/*! BPLSB - BPLSB
 */
#define VREF_TRIM0_BPLSB(x)                      (((uint32_t)(((uint32_t)(x)) << VREF_TRIM0_BPLSB_SHIFT)) & VREF_TRIM0_BPLSB_MASK)

#define VREF_TRIM0_BPMSB_MASK                    (0xE000U)
#define VREF_TRIM0_BPMSB_SHIFT                   (13U)
/*! BPMSB - BPMSB
 */
#define VREF_TRIM0_BPMSB(x)                      (((uint32_t)(((uint32_t)(x)) << VREF_TRIM0_BPMSB_SHIFT)) & VREF_TRIM0_BPMSB_MASK)

#define VREF_TRIM0_CHOPOSCTRIM_MASK              (0xF0000U)
#define VREF_TRIM0_CHOPOSCTRIM_SHIFT             (16U)
/*! CHOPOSCTRIM - CHOPOSCTRIM
 */
#define VREF_TRIM0_CHOPOSCTRIM(x)                (((uint32_t)(((uint32_t)(x)) << VREF_TRIM0_CHOPOSCTRIM_SHIFT)) & VREF_TRIM0_CHOPOSCTRIM_MASK)

#define VREF_TRIM0_P7_TRIM_MASK                  (0xF000000U)
#define VREF_TRIM0_P7_TRIM_SHIFT                 (24U)
/*! P7_TRIM - P7_TRIM
 *  0b0000..VREF 2.1V is enabled
 *  0b0001..VREF 2.1V is disabled
 */
#define VREF_TRIM0_P7_TRIM(x)                    (((uint32_t)(((uint32_t)(x)) << VREF_TRIM0_P7_TRIM_SHIFT)) & VREF_TRIM0_P7_TRIM_MASK)

#define VREF_TRIM0_FLIP_MASK                     (0x80000000U)
#define VREF_TRIM0_FLIP_SHIFT                    (31U)
/*! FLIP - Amplifier Polarity
 */
#define VREF_TRIM0_FLIP(x)                       (((uint32_t)(((uint32_t)(x)) << VREF_TRIM0_FLIP_SHIFT)) & VREF_TRIM0_FLIP_MASK)
/*! @} */

/*! @name TRIM1 - VREF Test Trim 1 */
/*! @{ */

#define VREF_TRIM1_LP_VTRIM_MASK                 (0x1FU)
#define VREF_TRIM1_LP_VTRIM_SHIFT                (0U)
/*! LP_VTRIM - LP Bandgap Voltage Trim
 */
#define VREF_TRIM1_LP_VTRIM(x)                   (((uint32_t)(((uint32_t)(x)) << VREF_TRIM1_LP_VTRIM_SHIFT)) & VREF_TRIM1_LP_VTRIM_MASK)

#define VREF_TRIM1_LP_TCTRIM_MASK                (0x700U)
#define VREF_TRIM1_LP_TCTRIM_SHIFT               (8U)
/*! LP_TCTRIM - LP_TCTRIM
 */
#define VREF_TRIM1_LP_TCTRIM(x)                  (((uint32_t)(((uint32_t)(x)) << VREF_TRIM1_LP_TCTRIM_SHIFT)) & VREF_TRIM1_LP_TCTRIM_MASK)

#define VREF_TRIM1_IREF_TRIM_MASK                (0x70000U)
#define VREF_TRIM1_IREF_TRIM_SHIFT               (16U)
/*! IREF_TRIM - IREF_TRIM
 */
#define VREF_TRIM1_IREF_TRIM(x)                  (((uint32_t)(((uint32_t)(x)) << VREF_TRIM1_IREF_TRIM_SHIFT)) & VREF_TRIM1_IREF_TRIM_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group VREF_Register_Masks */


/* VREF - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral VREF base address */
  #define VREF_BASE                                (0x500B5000u)
  /** Peripheral VREF base address */
  #define VREF_BASE_NS                             (0x400B5000u)
  /** Peripheral VREF base pointer */
  #define VREF                                     ((VREF_Type *)VREF_BASE)
  /** Peripheral VREF base pointer */
  #define VREF_NS                                  ((VREF_Type *)VREF_BASE_NS)
  /** Array initializer of VREF peripheral base addresses */
  #define VREF_BASE_ADDRS                          { VREF_BASE }
  /** Array initializer of VREF peripheral base pointers */
  #define VREF_BASE_PTRS                           { VREF }
  /** Array initializer of VREF peripheral base addresses */
  #define VREF_BASE_ADDRS_NS                       { VREF_BASE_NS }
  /** Array initializer of VREF peripheral base pointers */
  #define VREF_BASE_PTRS_NS                        { VREF_NS }
#else
  /** Peripheral VREF base address */
  #define VREF_BASE                                (0x400B5000u)
  /** Peripheral VREF base pointer */
  #define VREF                                     ((VREF_Type *)VREF_BASE)
  /** Array initializer of VREF peripheral base addresses */
  #define VREF_BASE_ADDRS                          { VREF_BASE }
  /** Array initializer of VREF peripheral base pointers */
  #define VREF_BASE_PTRS                           { VREF }
#endif

/*!
 * @}
 */ /* end of group VREF_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- WWDT Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer
 * @{
 */

/** WWDT - Register Layout Typedef */
typedef struct {
  __IO uint32_t MOD;                               /**< Mode, offset: 0x0 */
  __IO uint32_t TC;                                /**< Timer Constant, offset: 0x4 */
  __O  uint32_t FEED;                              /**< Feed Sequence, offset: 0x8 */
  __I  uint32_t TV;                                /**< Timer Value, offset: 0xC */
       uint8_t RESERVED_0[4];
  __IO uint32_t WARNINT;                           /**< Warning Interrupt Compare Value, offset: 0x14 */
  __IO uint32_t WINDOW;                            /**< Window Compare Value, offset: 0x18 */
} WWDT_Type;

/* ----------------------------------------------------------------------------
   -- WWDT Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup WWDT_Register_Masks WWDT Register Masks
 * @{
 */

/*! @name MOD - Mode */
/*! @{ */

#define WWDT_MOD_WDEN_MASK                       (0x1U)
#define WWDT_MOD_WDEN_SHIFT                      (0U)
/*! WDEN - Watchdog Enable
 *  0b0..Stop. The Watchdog timer is stopped.
 *  0b1..Run. The Watchdog timer is running.
 */
#define WWDT_MOD_WDEN(x)                         (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK)

#define WWDT_MOD_WDRESET_MASK                    (0x2U)
#define WWDT_MOD_WDRESET_SHIFT                   (1U)
/*! WDRESET - Watchdog Reset Enable
 *  0b0..Interrupt. A Watchdog timeout will not cause a chip reset.
 *  0b1..Reset. A Watchdog timeout will cause a chip reset.
 */
#define WWDT_MOD_WDRESET(x)                      (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK)

#define WWDT_MOD_WDTOF_MASK                      (0x4U)
#define WWDT_MOD_WDTOF_SHIFT                     (2U)
/*! WDTOF - Watchdog Timeout Flag
 *  0b0..Clear.
 *  0b1..Reset. Causes a chip reset if WDRESET = 1.
 */
#define WWDT_MOD_WDTOF(x)                        (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK)

#define WWDT_MOD_WDINT_MASK                      (0x8U)
#define WWDT_MOD_WDINT_SHIFT                     (3U)
/*! WDINT - Warning Interrupt Flag
 *  0b0..No flag.
 *  0b1..Flag. The Watchdog interrupt flag is set when the Watchdog counter is no longer greater than the value specified by WARNINT.
 */
#define WWDT_MOD_WDINT(x)                        (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK)

#define WWDT_MOD_WDPROTECT_MASK                  (0x10U)
#define WWDT_MOD_WDPROTECT_SHIFT                 (4U)
/*! WDPROTECT - Watchdog Update Mode
 *  0b0..Flexible
 *  0b1..Threshold
 */
#define WWDT_MOD_WDPROTECT(x)                    (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK)

#define WWDT_MOD_LOCK_MASK                       (0x20U)
#define WWDT_MOD_LOCK_SHIFT                      (5U)
/*! LOCK - Lock
 *  0b0..No Lock
 *  0b1..Lock
 */
#define WWDT_MOD_LOCK(x)                         (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_LOCK_SHIFT)) & WWDT_MOD_LOCK_MASK)
/*! @} */

/*! @name TC - Timer Constant */
/*! @{ */

#define WWDT_TC_COUNT_MASK                       (0xFFFFFFU)
#define WWDT_TC_COUNT_SHIFT                      (0U)
/*! COUNT - Watchdog Timeout Value
 */
#define WWDT_TC_COUNT(x)                         (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK)
/*! @} */

/*! @name FEED - Feed Sequence */
/*! @{ */

#define WWDT_FEED_FEED_MASK                      (0xFFU)
#define WWDT_FEED_FEED_SHIFT                     (0U)
/*! FEED - Feed Value
 */
#define WWDT_FEED_FEED(x)                        (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK)
/*! @} */

/*! @name TV - Timer Value */
/*! @{ */

#define WWDT_TV_COUNT_MASK                       (0xFFFFFFU)
#define WWDT_TV_COUNT_SHIFT                      (0U)
/*! COUNT - Counter Timer Value
 */
#define WWDT_TV_COUNT(x)                         (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK)
/*! @} */

/*! @name WARNINT - Warning Interrupt Compare Value */
/*! @{ */

#define WWDT_WARNINT_WARNINT_MASK                (0x3FFU)
#define WWDT_WARNINT_WARNINT_SHIFT               (0U)
/*! WARNINT - Watchdog Warning Interrupt Compare Value
 */
#define WWDT_WARNINT_WARNINT(x)                  (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK)
/*! @} */

/*! @name WINDOW - Window Compare Value */
/*! @{ */

#define WWDT_WINDOW_WINDOW_MASK                  (0xFFFFFFU)
#define WWDT_WINDOW_WINDOW_SHIFT                 (0U)
/*! WINDOW - Watchdog Window Value.
 */
#define WWDT_WINDOW_WINDOW(x)                    (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group WWDT_Register_Masks */


/* WWDT - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral WWDT base address */
  #define WWDT_BASE                                (0x5000C000u)
  /** Peripheral WWDT base address */
  #define WWDT_BASE_NS                             (0x4000C000u)
  /** Peripheral WWDT base pointer */
  #define WWDT                                     ((WWDT_Type *)WWDT_BASE)
  /** Peripheral WWDT base pointer */
  #define WWDT_NS                                  ((WWDT_Type *)WWDT_BASE_NS)
  /** Array initializer of WWDT peripheral base addresses */
  #define WWDT_BASE_ADDRS                          { WWDT_BASE }
  /** Array initializer of WWDT peripheral base pointers */
  #define WWDT_BASE_PTRS                           { WWDT }
  /** Array initializer of WWDT peripheral base addresses */
  #define WWDT_BASE_ADDRS_NS                       { WWDT_BASE_NS }
  /** Array initializer of WWDT peripheral base pointers */
  #define WWDT_BASE_PTRS_NS                        { WWDT_NS }
#else
  /** Peripheral WWDT base address */
  #define WWDT_BASE                                (0x4000C000u)
  /** Peripheral WWDT base pointer */
  #define WWDT                                     ((WWDT_Type *)WWDT_BASE)
  /** Array initializer of WWDT peripheral base addresses */
  #define WWDT_BASE_ADDRS                          { WWDT_BASE }
  /** Array initializer of WWDT peripheral base pointers */
  #define WWDT_BASE_PTRS                           { WWDT }
#endif
/** Interrupt vectors for the WWDT peripheral type */
#define WWDT_IRQS                                { WDT_BOD_IRQn }

/*!
 * @}
 */ /* end of group WWDT_Peripheral_Access_Layer */


/*
** End of section using anonymous unions
*/

#if defined(__ARMCC_VERSION)
  #if (__ARMCC_VERSION >= 6010050)
    #pragma clang diagnostic pop
  #else
    #pragma pop
  #endif
#elif defined(__GNUC__)
  /* leave anonymous unions enabled */
#elif defined(__IAR_SYSTEMS_ICC__)
  #pragma language=default
#else
  #error Not supported compiler type
#endif

/*!
 * @}
 */ /* end of group Peripheral_access_layer */


/* ----------------------------------------------------------------------------
   -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
 * @{
 */

#if defined(__ARMCC_VERSION)
  #if (__ARMCC_VERSION >= 6010050)
    #pragma clang system_header
  #endif
#elif defined(__IAR_SYSTEMS_ICC__)
  #pragma system_include
#endif

/**
 * @brief Mask and left-shift a bit field value for use in a register bit range.
 * @param field Name of the register bit field.
 * @param value Value of the bit field.
 * @return Masked and shifted value.
 */
#define NXP_VAL2FLD(field, value)    (((value) << (field ## _SHIFT)) & (field ## _MASK))
/**
 * @brief Mask and right-shift a register value to extract a bit field value.
 * @param field Name of the register bit field.
 * @param value Value of the register.
 * @return Masked and shifted bit field value.
 */
#define NXP_FLD2VAL(field, value)    (((value) & (field ## _MASK)) >> (field ## _SHIFT))

/*!
 * @}
 */ /* end of group Bit_Field_Generic_Macros */


/* ----------------------------------------------------------------------------
   -- SDK Compatibility
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
 * @{
 */

/** AHB Secure Control */
#if defined(SECTRL0)
    #define AHB_SECURE_CTRL                                SECTRL0
#endif


/*!
 * @}
 */ /* end of group SDK_Compatibility_Symbols */


#endif  /* _LPC55S36_H_ */

