/*
** ###################################################################
**     Processors:          KW45B41Z83AFPA
**                          KW45B41Z83AFTA
**
**     Compilers:           GNU C Compiler
**                          IAR ANSI C/C++ Compiler for ARM
**                          Keil ARM C/C++ Compiler
**                          MCUXpresso Compiler
**
**     Reference manual:    Rev. 6, 05/22/2022
**     Version:             rev. 1.0, 2020-05-12
**     Build:               b220804
**
**     Abstract:
**         CMSIS Peripheral Access Layer for KW45B41Z83
**
**     Copyright 1997-2016 Freescale Semiconductor, Inc.
**     Copyright 2016-2022 NXP
**     All rights reserved.
**
**     SPDX-License-Identifier: BSD-3-Clause
**
**     http:                 www.nxp.com
**     mail:                 support@nxp.com
**
**     Revisions:
**     - rev. 1.0 (2020-05-12)
**         Initial version.
**
** ###################################################################
*/

/*!
 * @file KW45B41Z83.h
 * @version 1.0
 * @date 2020-05-12
 * @brief CMSIS Peripheral Access Layer for KW45B41Z83
 *
 * CMSIS Peripheral Access Layer for KW45B41Z83
 */

#ifndef _KW45B41Z83_H_
#define _KW45B41Z83_H_                           /**< Symbol preventing repeated inclusion */

/** Memory map major version (memory maps with equal major version number are
 * compatible) */
#define MCU_MEM_MAP_VERSION 0x0100U
/** Memory map minor version */
#define MCU_MEM_MAP_VERSION_MINOR 0x0000U


/* ----------------------------------------------------------------------------
   -- Interrupt vector numbers
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
 * @{
 */

/** Interrupt Number Definitions */
#define NUMBER_OF_INT_VECTORS 92                 /**< Number of interrupts in the Vector table */

typedef enum IRQn {
  /* Auxiliary constants */
  NotAvail_IRQn                = -128,             /**< Not available device specific interrupt */

  /* Core interrupts */
  NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
  HardFault_IRQn               = -13,              /**< Cortex-M33 SV Hard Fault Interrupt */
  MemoryManagement_IRQn        = -12,              /**< Cortex-M33 Memory Management Interrupt */
  BusFault_IRQn                = -11,              /**< Cortex-M33 Bus Fault Interrupt */
  UsageFault_IRQn              = -10,              /**< Cortex-M33 Usage Fault Interrupt */
  SecureFault_IRQn             = -9,               /**< Cortex-M33 Secure Fault Interrupt */
  SVCall_IRQn                  = -5,               /**< Cortex-M33 SV Call Interrupt */
  DebugMonitor_IRQn            = -4,               /**< Cortex-M33 Debug Monitor Interrupt */
  PendSV_IRQn                  = -2,               /**< Cortex-M33 Pend SV Interrupt */
  SysTick_IRQn                 = -1,               /**< Cortex-M33 System Tick Interrupt */

  /* Device specific interrupts */
  CTI_IRQn                     = 0,                /**< Cross Trigger Interface interrupt */
  CMC0_IRQn                    = 1,                /**< Core Mode Controller interrupt */
  DMA0_CH0_IRQn                = 2,                /**< eDMA channel 0 error or transfer complete */
  DMA0_CH1_IRQn                = 3,                /**< eDMA channel 1 error or transfer complete */
  DMA0_CH2_IRQn                = 4,                /**< eDMA channel 2 error or transfer complete */
  DMA0_CH3_IRQn                = 5,                /**< eDMA channel 3 error or transfer complete */
  DMA0_CH4_IRQn                = 6,                /**< eDMA channel 4 error or transfer complete */
  DMA0_CH5_IRQn                = 7,                /**< eDMA channel 5 error or transfer complete */
  DMA0_CH6_IRQn                = 8,                /**< eDMA channel 6 error or transfer complete */
  DMA0_CH7_IRQn                = 9,                /**< eDMA channel 7 error or transfer complete */
  DMA0_CH8_IRQn                = 10,               /**< eDMA channel 8 error or transfer complete */
  DMA0_CH9_IRQn                = 11,               /**< eDMA channel 9 error or transfer complete */
  DMA0_CH10_IRQn               = 12,               /**< eDMA channel 10 error or transfer complete */
  DMA0_CH11_IRQn               = 13,               /**< eDMA channel 11 error or transfer complete */
  DMA0_CH12_IRQn               = 14,               /**< eDMA channel 12 error or transfer complete */
  DMA0_CH13_IRQn               = 15,               /**< eDMA channel 13 error or transfer complete */
  DMA0_CH14_IRQn               = 16,               /**< eDMA channel 14 error or transfer complete */
  DMA0_CH15_IRQn               = 17,               /**< eDMA channel 15 error or transfer complete */
  EWM0_IRQn                    = 18,               /**< External Watchdog Monitor 0 interrupt */
  MCM0_IRQn                    = 19,               /**< Miscellaneous Control Module interrupt */
  MSCM0_IRQn                   = 20,               /**< Miscellaneous System Control Module interrupt */
  SPC0_IRQn                    = 21,               /**< System Power Controller 0 interrupt */
  WUU0_IRQn                    = 22,               /**< Wake-Up Unit 0 interrupt */
  WDOG0_IRQn                   = 23,               /**< Watchdog Timer 0 interrupt */
  WDOG1_IRQn                   = 24,               /**< Watchdog Timer 1 interrupt */
  SCG0_IRQn                    = 25,               /**< System Clock Generator 0 interrupt */
  SFA0_IRQn                    = 26,               /**< Singal Frequency Analyzer 0 interrupt */
  FMU0_IRQn                    = 27,               /**< Flash Memory Unit 0 interrupt */
  ELE_CMD_IRQn                 = 28,               /**< EdgeLock enclave command interface interrupt */
  ELE_SECURE_IRQn              = 29,               /**< EdgeLock enclave interrupt */
  ELE_NONSECURE_IRQn           = 30,               /**< EdgeLock enclave non-secure interrupt */
  TRDC0_IRQn                   = 31,               /**< Trusted Resource Domain Controller 0 interrupt */
  RTC_Alarm_IRQn               = 32,               /**< Real Time Clock 0 alarm interrupt */
  RTC_Seconds_IRQn             = 33,               /**< Real Time Clock 0 seconds interrupt */
  LPTMR0_IRQn                  = 34,               /**< Low-Power Timer0 interrupt */
  LPTMR1_IRQn                  = 35,               /**< Low-Power Timer1 interrupt */
  LPIT0_IRQn                   = 36,               /**< Low-Power Periodic Interrupt Timer 0 interrupt */
  TPM0_IRQn                    = 37,               /**< Timer / PWM Module 0 interrupt */
  TPM1_IRQn                    = 38,               /**< Timer / PWM Module 1 interrupt */
  LPI2C0_IRQn                  = 39,               /**< Low-Power Inter Integrated Circuit 0 interrupt */
  LPI2C1_IRQn                  = 40,               /**< Low-Power Inter Integrated Circuit 1 interrupt */
  I3C0_IRQn                    = 41,               /**< Improved Inter-Integrated Circuit 0 interrupt */
  LPSPI0_IRQn                  = 42,               /**< Low-Power Serial Peripheral Interface 0 interrupt */
  LPSPI1_IRQn                  = 43,               /**< Low-Power Serial Peripheral Interface 1 interrupt */
  LPUART0_IRQn                 = 44,               /**< Low-Power Universal Asynchronous Receiver/Transmitter 0 interrupt */
  LPUART1_IRQn                 = 45,               /**< Low-Power Universal Asynchronous Receiver/Transmitter 1 interrupt */
  FLEXIO0_IRQn                 = 46,               /**< Flexible Input/Output 0 interrupt */
  CAN0_IRQn                    = 47,               /**< Controller Area Network 0 interrupt */
  RF_IMU0_IRQn                 = 48,               /**< Radio IMU interrupt 0 (msg_rdy_imu) */
  RF_IMU1_IRQn                 = 49,               /**< Radio IMU interrupt 1(msg_space_avail_imu) */
  RF_NBU_IRQn                  = 50,               /**< Radio NBU timeout interrupt */
  RF_FMU_IRQn                  = 51,               /**< Radio FMU interrupt */
  RF_WOR_IRQn                  = 52,               /**< Radio WOR RX FAIL interrupt */
  Reserved69_IRQn              = 53,               /**< Reserved interrupt */
  RF_Generic_IRQn              = 54,               /**< Radio Frequency 2.4 GHz - Generic Link Layer interrupt */
  RF_BRIC_IRQn                 = 55,               /**< Radio Frequency 2.4 GHz - BRIC interrupt */
  RF_LANT_SW_IRQn              = 56,               /**< Radio Transceiver - Radio LANT_SW interrupt */
  RFMC_IRQn                    = 57,               /**< RFMC interrupt */
  DSB_IRQn                     = 58,               /**< Data Stream Buffer interrupt */
  GPIOA_INT0_IRQn              = 59,               /**< General Purpose Input/Output A interrupt 0 */
  GPIOA_INT1_IRQn              = 60,               /**< General Purpose Input/Output A interrupt 1 */
  GPIOB_INT0_IRQn              = 61,               /**< General Purpose Input/Output B interrupt 0 */
  GPIOB_INT1_IRQn              = 62,               /**< General Purpose Input/Output B interrupt 1 */
  GPIOC_INT0_IRQn              = 63,               /**< General Purpose Input/Output C interrupt 0 */
  GPIOC_INT1_IRQn              = 64,               /**< General Purpose Input/Output C interrupt 1 */
  GPIOD_INT0_IRQn              = 65,               /**< General Purpose Input/Output D interrupt 0 */
  GPIOD_INT1_IRQn              = 66,               /**< General Purpose Input/Output D interrupt 1 */
  PORTA_IRQn                   = 67,               /**< PortA EFT interrupt */
  PORTB_IRQn                   = 68,               /**< PortB EFT interrupt */
  PORTC_IRQn                   = 69,               /**< PortC EFT interrupt */
  PORTD_IRQn                   = 70,               /**< PortD EFT interrupt */
  ADC0_IRQn                    = 71,               /**< Analog-to-Digital Converter 0 interrupt */
  LPCMP0_IRQn                  = 72,               /**< Low-Power Comparator 0 interrupt */
  LPCMP1_IRQn                  = 73,               /**< Low-Power Comparator 1 interrupt */
  VBAT_IRQn                    = 74,               /**< Smart Power Switch Domain interrupt */
  Reserved91_IRQn              = 75                /**< Reserved interrupt */
} IRQn_Type;

/*!
 * @}
 */ /* end of group Interrupt_vector_numbers */


/* ----------------------------------------------------------------------------
   -- Cortex M33 Core Configuration
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration
 * @{
 */

#define __MPU_PRESENT                  1         /**< Defines if an MPU is present or not */
#define __NVIC_PRIO_BITS               3         /**< Number of priority bits implemented in the NVIC */
#define __Vendor_SysTickConfig         0         /**< Vendor specific implementation of SysTickConfig is defined */
#define __FPU_PRESENT                  1         /**< Defines if an FPU is present or not */
#define __DSP_PRESENT                  1         /**< Defines if Armv8-M Mainline core supports DSP instructions */
#define __SAUREGION_PRESENT            1         /**< Defines if an SAU is present or not */

#include "core_cm33.h"                 /* Core Peripheral Access Layer */
#include "system_KW45B41Z83.h"         /* Device specific configuration file */

/*!
 * @}
 */ /* end of group Cortex_Core_Configuration */


/* ----------------------------------------------------------------------------
   -- Mapping Information
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup Mapping_Information Mapping Information
 * @{
 */

/** Mapping Information */
/*!
 * @addtogroup edma_request
 * @{
 */

/*******************************************************************************
 * Definitions
*******************************************************************************/

/*!
 * @brief Enumeration for the DMA hardware request
 *
 * Defines the enumeration for the DMA hardware request collections.
 */

typedef enum _dma_request_source
{
    kDmaRequestDisabled             = 0U,          /**< Disabled */
    kDmaRequestWUU0                 = 1U,          /**< WUU0 Wake up event */
    kDmaRequestELE                  = 2U,          /**< EdgeLocK enclave Data request */
    kDmaRequestLPTMR0               = 3U,          /**< LPTMR0 Counter match event */
    kDmaRequestLPTMR1               = 4U,          /**< LPTMR1 Counter match event */
    kDmaRequestTPM0Channel0         = 5U,          /**< TPM0 Channel 0 request */
    kDmaRequestTPM0Channel1         = 6U,          /**< TPM0 Channel 1 request */
    kDmaRequestTPM0Channel2         = 7U,          /**< TPM0 Channel 2 request */
    kDmaRequestTPM0Channel3         = 8U,          /**< TPM0 Channel 3 request */
    kDmaRequestTPM0Channel4         = 9U,          /**< TPM0 Channel 4 request */
    kDmaRequestTPM0Channel5         = 10U,         /**< TPM0 Channel 5 request */
    kDmaRequestTPM0Overflow         = 11U,         /**< TPM0 Counter overflow request */
    kDmaRequestTPM1Channel0         = 12U,         /**< TPM1 Channel 0 request */
    kDmaRequestTPM1Channel1         = 13U,         /**< TPM1 Channel 1 request */
    kDmaRequestTPM1Channel2         = 14U,         /**< TPM1 Channel 2 request */
    kDmaRequestTPM1Channel3         = 15U,         /**< TPM1 Channel 3 request */
    kDmaRequestTPM1Channel4         = 16U,         /**< TPM1 Channel 4 request */
    kDmaRequestTPM1Channel5         = 17U,         /**< TPM1 Channel 5 request */
    kDmaRequestTPM1Overflow         = 18U,         /**< TPM1 Counter overflow request */
    kDmaRequestRFInputData          = 19U,         /**< Radio Bric Input data request */
    kDmaRequestRFOutputData         = 20U,         /**< Radio Bric Output data request */
    kDmaRequestLPI2C0Rx             = 21U,         /**< LPI2C0 Master / Slave receive request */
    kDmaRequestLPI2C0Tx             = 22U,         /**< LPI2C0 Master / Slave transmit request */
    kDmaRequestLPI2C1Rx             = 23U,         /**< LPI2C1 Master / Slave receive request */
    kDmaRequestLPI2C1Tx             = 24U,         /**< LPI2C1 Master / Slave transmit request */
    kDmaRequestI3C0Rx               = 25U,         /**< I3C0 Master / Slave receive request */
    kDmaRequestI3C0Tx               = 26U,         /**< I3C0 Master / Slave transmit request */
    kDmaRequestLPSPI0Rx             = 27U,         /**< LPSPI0 Master / Slave receive request */
    kDmaRequestLPSPI0Tx             = 28U,         /**< LPSPI0 Master / Slave transmit request */
    kDmaRequestLPSPI1Rx             = 29U,         /**< LPSPI1 Master / Slave receive request */
    kDmaRequestLPSPI1Tx             = 30U,         /**< LPSPI1 Master / Slave transmit request */
    kDmaRequestLPUART0Rx            = 31U,         /**< LPUART0 receive request */
    kDmaRequestLPUART0Tx            = 32U,         /**< LPUART0 transmit request */
    kDmaRequestLPUART1Rx            = 33U,         /**< LPUART1 receive request */
    kDmaRequestLPUART1Tx            = 34U,         /**< LPUART1 transmit request */
    kDmaRequestFLEXIO0ShiftReg0     = 35U,         /**< FLEXIO0 Shift register 0 request */
    kDmaRequestFLEXIO0ShiftReg1     = 36U,         /**< FLEXIO0 Shift register 1 request */
    kDmaRequestFLEXIO0ShiftReg2     = 37U,         /**< FLEXIO0 Shift register 2 request */
    kDmaRequestFLEXIO0ShiftReg3     = 38U,         /**< FLEXIO0 Shift register 3 request */
    kDmaRequestFLEXIO0ShiftReg4     = 39U,         /**< FLEXIO0 Shift register 4 request */
    kDmaRequestFLEXIO0ShiftReg5     = 40U,         /**< FLEXIO0 Shift register 5 request */
    kDmaRequestFLEXIO0ShiftReg6     = 41U,         /**< FLEXIO0 Shift register 6 request */
    kDmaRequestFLEXIO0ShiftReg7     = 42U,         /**< FLEXIO0 Shift register 7 request */
    kDmaRequestCAN0                 = 43U,         /**< CAN0 DMA request */
    kDmaRequestGPIOAPinEvent0       = 44U,         /**< GPIOA Pin event request 0 */
    kDmaRequestGPIOAPinEvent1       = 45U,         /**< GPIOA Pin event request 1 */
    kDmaRequestGPIOBPinEvent0       = 46U,         /**< GPIOB Pin event request 0 */
    kDmaRequestGPIOBPinEvent1       = 47U,         /**< GPIOB Pin event request 1 */
    kDmaRequestGPIOCPinEvent0       = 48U,         /**< GPIOC Pin event request 0 */
    kDmaRequestGPIOCPinEvent1       = 49U,         /**< GPIOC Pin event request 1 */
    kDmaRequestGPIODPinEvent0       = 50U,         /**< GPIOD Pin event request 0 */
    kDmaRequestGPIODPinEvent1       = 51U,         /**< GPIOD Pin event request 1 */
    kDmaRequestADCFifoA             = 52U,         /**< ADC FIFO A request */
    kDmaRequestADCFifoB             = 53U,         /**< ADC FIFO B request */
    kDmaRequestCMP0                 = 54U,         /**< CMP0 DMA request */
    kDmaRequestCMP1                 = 55U,         /**< CMP1 DMA request */
} dma_request_source_t;

/* @} */

/*!
 * @addtogroup trdc_mapping
 * @{
 */

/*******************************************************************************
 * Definitions
*******************************************************************************/

/*!
 * @brief Enumeration for the TRDC master mapping
 *
 * Defines the enumeration for the TRDC master resource collections.
 */

typedef enum _trdc_master
{
    kTRDC_MasterCM33                = 0U,          /**< CM33 */
    kTRDC_MasterDMA3                = 1U,          /**< DMA3 */
    kTRDC_MasterDataSteamBuffer     = 2U,          /**< Data stream buffer */
    kTRDC_MasterRadioNBU            = 3U,          /**< Radio NBU */
} trdc_master_t;

/* @} */

/*!
 * @brief Enumeration for the TRDC MBC0 slave mapping
 *
 * Defines the enumeration for the TRDC MBC0 slave resource collections.
 */
typedef enum _trdc_mbc0_slave
{
    kTRDC_SlaveFlash                = 0U,          /**< Flash - 1MB */
    kTRDC_SlaveFlashIFR0            = 1U,          /**< Flash IFR0 - 32 KB */
    kTRDC_SlaveFlashIFR1            = 2U,          /**< Flash IFR1 - 8 KB */
    kTRDC_SlaveROM                  = 3U,          /**< ROM - 96KB */
} trdc_mbc0_slave_t;

/*!
 * @brief Enumeration for the TRDC MBC1 slave mapping
 *
 * Defines the enumeration for the TRDC MBC1 slave resource collections.
 */
typedef enum _trdc_mbc1_slave
{
    kTRDC_SlaveCTCM0_1              = 0U,          /**< CTCM0,1 - 16 KB (with ECC) */
    kTRDC_SlaveSTCM0_1_2            = 1U,          /**< STCM0,1,2 - 16,16,32 KB (with ECC) */
    kTRDC_SlaveSTCM3_4              = 2U,          /**< STCM3,4 - 32,8 KB (with ECC) */
    kTRDC_SlaveSTCM5                = 3U,          /**< STCM5 - 8 KB (with ECC) */
} trdc_mbc1_slave_t;

/*!
 * @brief Enumeration for the TRDC MBC2 slave mapping
 *
 * Defines the enumeration for the TRDC MBC2 slave resource collections.
 */
typedef enum _trdc_mbc2_slave
{
    kTRDC_SlavePBRIDGE2             = 0U,          /**< PBRIDGE2 */
    kTRDC_SlaveRadioPridge          = 1U,          /**< Radio Pridge in Fast Peripheral 1 */
    kTRDC_SlaveNBU                  = 2U,          /**< NBU part in Fast Peripheral 1 */
} trdc_mbc2_slave_t;

/*!
 * @addtogroup trgmux_source
 * @{ */

/*******************************************************************************
 * Definitions
*******************************************************************************/

/*!
 * @brief Enumeration for the TRGMUX source
 *
 * Defines the enumeration for the TRGMUX source collections.
 */
typedef enum _trgmux_source
{
    kTRGMUX_SourceDisabled          = 0U,          /**< Trigger function is disabled */
    kTRGMUX_SourceAlwaysHigh        = 1U,          /**< Trigger function is always high */
    kTRGMUX_SourceTrgmux0Input0     = 2U,          /**< TRGMUX0 Input 0 is selected */
    kTRGMUX_SourceTrgmux0Input1     = 3U,          /**< TRGMUX0 Input 1 is selected */
    kTRGMUX_SourceTrgmux0Input2     = 4U,          /**< TRGMUX0 Input 2 is selected */
    kTRGMUX_SourceTrgmux0Input3     = 5U,          /**< TRGMUX0 Input 3 is selected */
    kTRGMUX_SourceWuu0Trigger       = 6U,          /**< WUU0 Trigger Event is selected */
    kTRGMUX_SourceRtcAlarm          = 7U,          /**< RTC Alarm Event is selected */
    kTRGMUX_SourceRtcSeconds        = 8U,          /**< RTC Seconds Match is selected */
    kTRGMUX_SourceLptmr0Trigger     = 9U,          /**< LPTMR0 Counter Match is selected */
    kTRGMUX_SourceLptmr1Trigger     = 10U,         /**< LPTMR1 Counter Match is selected */
    kTRGMUX_SourceLpit0Channel0     = 11U,         /**< LPIT0 Channel 0 is selected */
    kTRGMUX_SourceLpit0Channel1     = 12U,         /**< LPIT0 Channel 1 is selected */
    kTRGMUX_SourceLpit0Channel2     = 13U,         /**< LPIT0 Channel 2 is selected */
    kTRGMUX_SourceLpit0Channel3     = 14U,         /**< LPIT0 Channel 3 is selected */
    kTRGMUX_SourceTpm0Channel0      = 15U,         /**< TPM0 Channel 0 is selected */
    kTRGMUX_SourceTpm0Channel1      = 16U,         /**< TPM0 Channel 1 is selected */
    kTRGMUX_SourceTpm0Channel2      = 17U,         /**< TPM0 Channel 2 is selected */
    kTRGMUX_SourceTpm0Channel3      = 18U,         /**< TPM0 Channel 3 is selected */
    kTRGMUX_SourceTpm0Channel4      = 19U,         /**< TPM0 Channel 4 is selected */
    kTRGMUX_SourceTpm0Channel5      = 20U,         /**< TPM0 Channel 5 is selected */
    kTRGMUX_SourceTpm0Overflow      = 21U,         /**< TPM0 Overflow is selected */
    kTRGMUX_SourceTpm1Channel0      = 22U,         /**< TPM1 Channel 0 is selected */
    kTRGMUX_SourceTpm1Channel1      = 23U,         /**< TPM1 Channel 1 is selected */
    kTRGMUX_SourceTpm1Channel2      = 24U,         /**< TPM1 Channel 2 is selected */
    kTRGMUX_SourceTpm1Channel3      = 25U,         /**< TPM1 Channel 3 is selected */
    kTRGMUX_SourceTpm1Channel4      = 26U,         /**< TPM1 Channel 4 is selected */
    kTRGMUX_SourceTpm1Channel5      = 27U,         /**< TPM1 Channel 5 is selected */
    kTRGMUX_SourceTpm1Overflow      = 28U,         /**< TPM1 Overflow is selected */
    kTRGMUX_SourceLpi2c0MasterStop  = 29U,         /**< LPI2C0 Master End of Packet is selected */
    kTRGMUX_SourceLpi2c0SlaveStop   = 30U,         /**< LPI2C0 Slave End of Packet is selected */
    kTRGMUX_SourceLpi2c1MasterStop  = 31U,         /**< LPI2C1 Master End of Packet is selected */
    kTRGMUX_SourceLpi2c1SlaveStop   = 32U,         /**< LPI2C1 Slave End of Packet is selected */
    kTRGMUX_SourceLpspi0Frame       = 33U,         /**< LPSPI0 End of Frame is selected */
    kTRGMUX_SourceLpspi0Rx          = 34U,         /**< LPSPI0 Received Data Word is selected */
    kTRGMUX_SourceLpspi1Frame       = 35U,         /**< LPSPI1 End of Frame is selected */
    kTRGMUX_SourceLpspi1Rx          = 36U,         /**< LPSPI1 Received Data Word is selected */
    kTRGMUX_SourceLpuart0RxData     = 37U,         /**< LPUART0 Received Data Word is selected */
    kTRGMUX_SourceLpuart0TxData     = 38U,         /**< LPUART0 Transmitted Data Word is selected */
    kTRGMUX_SourceLpuart0RxIdle     = 39U,         /**< LPUART0 Receive Line Idle is selected */
    kTRGMUX_SourceLpuart1RxData     = 40U,         /**< LPUART1 Received Data Word is selected */
    kTRGMUX_SourceLpuart1TxData     = 41U,         /**< LPUART1 Transmitted Data Word is selected */
    kTRGMUX_SourceLpuart1RxIdle     = 42U,         /**< LPUART1 Receive Line Idle is selected */
    kTRGMUX_SourceFlexIO0Timer0     = 43U,         /**< FlexIO0 Channel 0 is selected */
    kTRGMUX_SourceFlexIO0Timer1     = 44U,         /**< FlexIO0 Channel 1 is selected */
    kTRGMUX_SourceFlexIO0Timer2     = 45U,         /**< FlexIO0 Channel 2 is selected */
    kTRGMUX_SourceFlexIO0Timer3     = 46U,         /**< FlexIO0 Channel 3 is selected */
    kTRGMUX_SourceFlexIO0Timer4     = 47U,         /**< FLexIO0 Channel 4 is selected */
    kTRGMUX_SourceFlexIO0Timer5     = 48U,         /**< FlexIO0 Channel 5 is selected */
    kTRGMUX_SourceFlexIO0Timer6     = 49U,         /**< FlexIO0 Channel 6 is selected */
    kTRGMUX_SourceFlexIO0Timer7     = 50U,         /**< FlexIO0 Channel 7 is selected */
    kTRGMUX_SourceGpioAPinTrigger0  = 51U,         /**< GPIOA Pin event Trigger 0 is selected */
    kTRGMUX_SourceGpioAPinTrigger1  = 52U,         /**< GPIOA Pin event Trigger 1 is selected */
    kTRGMUX_SourceGpioBPinTrigger0  = 53U,         /**< GPIOB Pin event Trigger 0 is selected */
    kTRGMUX_SourceGpioBPinTrigger1  = 54U,         /**< GPIOB Pin event Trigger 1 is selected */
    kTRGMUX_SourceGpioCPinTrigger0  = 55U,         /**< GPIOC Pin event Trigger 0 is selected */
    kTRGMUX_SourceGpioCPinTrigger1  = 56U,         /**< GPIOC Pin event Trigger 1 is selected */
    kTRGMUX_SourceGpioDPinTrigger0  = 57U,         /**< GPIOD Pin event Trigger 0 is selected */
    kTRGMUX_SourceGpioDPinTrigger1  = 58U,         /**< GPIOD Pin event Trigger 1 is selected */
    kTRGMUX_SourceAdcGp0Output0     = 59U,         /**< ADC-GP0 Trigger Output 0 is selected */
    kTRGMUX_SourceAdcGp0Output1     = 60U,         /**< ADC-GP0 Trigger Output 1 is selected */
    kTRGMUX_SourceAdcGp0Output2     = 61U,         /**< ADC-GP0 Trigger Output 2 is selected */
    kTRGMUX_SourceAdcGp0Output3     = 62U,         /**< ADC-GP0 Trigger Output 3 is selected */
    kTRGMUX_SourceCmpGp0Output      = 63U,         /**< CMP-GP0 Comparator Output is selected */
    kTRGMUX_SourceCmpGp1Output      = 64U,         /**< CMP-GP1 Comparator Output is selected */
    kTRGMUX_SourceSpc0DcdcBurst     = 65U,         /**< SPC0 DCDC Burst Trig is selected */
    kTRGMUX_SourceRf2p4gTofTimestamp = 66U,        /**< RF-2.4G TOF TIMESTAMP TRIG is selected */
    kTRGMUX_SourceRf2p4gLantSw      = 67U,         /**< RF-2.4G LANT_SW is selected */
} trgmux_source_t;

/* @} */

/*!
 * @brief Enumeration for the TRGMUX device
 *
 * Defines the enumeration for the TRGMUX device collections.
 */
typedef enum _trgmux_device
{
    kTRGMUX_Trgmux0Output0          = 0U,          /**< TRGMUX_OUT0 device trigger input */
    kTRGMUX_Trgmux0Lpit0            = 1U,          /**< LPIT0 device trigger input */
    kTRGMUX_Trgmux0Tpm0             = 2U,          /**< TPM0 device trigger input */
    kTRGMUX_Trgmux0Tpm1             = 3U,          /**< TPM1 device trigger input */
    kTRGMUX_Trgmux0Lpi2c0           = 4U,          /**< LPI2C0 device trigger input */
    kTRGMUX_Trgmux0Lpi2c1           = 5U,          /**< LPI2C1 device trigger input */
    kTRGMUX_Trgmux0Lpspi0           = 6U,          /**< LPSPI0 device trigger input */
    kTRGMUX_Trgmux0Lpspi1           = 7U,          /**< LPSPI1 device trigger input */
    kTRGMUX_Trgmux0Lpuart0          = 8U,          /**< LPUART0 device trigger input */
    kTRGMUX_Trgmux0Lpuart1          = 9U,          /**< LPUART1 device trigger input */
    kTRGMUX_Trgmux0Flexio0          = 10U,         /**< FlexIO0 device trigger input */
    kTRGMUX_Trgmux0AdcGp0           = 11U,         /**< ADC_GP0 device trigger input */
    kTRGMUX_Trgmux0CmpGp0           = 12U,         /**< CMP_GP0 device trigger input */
    kTRGMUX_Trgmux0CmpGp1           = 13U,         /**< CMP_GP1 device trigger input */
} trgmux_device_t;

/* @} */


/*!
 * @}
 */ /* end of group Mapping_Information */


/* ----------------------------------------------------------------------------
   -- Device Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
 * @{
 */


/*
** Start of section using anonymous unions
*/

#if defined(__ARMCC_VERSION)
  #if (__ARMCC_VERSION >= 6010050)
    #pragma clang diagnostic push
  #else
    #pragma push
    #pragma anon_unions
  #endif
#elif defined(__GNUC__)
  /* anonymous unions are enabled by default */
#elif defined(__IAR_SYSTEMS_ICC__)
  #pragma language=extended
#else
  #error Not supported compiler type
#endif

/* ----------------------------------------------------------------------------
   -- ADC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
 * @{
 */

/** ADC - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
       uint8_t RESERVED_0[8];
  __IO uint32_t CTRL;                              /**< ADC Control Register, offset: 0x10 */
  __IO uint32_t STAT;                              /**< ADC Status Register, offset: 0x14 */
  __IO uint32_t IE;                                /**< Interrupt Enable Register, offset: 0x18 */
  __IO uint32_t DE;                                /**< DMA Enable Register, offset: 0x1C */
  __IO uint32_t CFG;                               /**< ADC Configuration Register, offset: 0x20 */
  __IO uint32_t PAUSE;                             /**< ADC Pause Register, offset: 0x24 */
       uint8_t RESERVED_1[12];
  __O  uint32_t SWTRIG;                            /**< Software Trigger Register, offset: 0x34 */
  __IO uint32_t TSTAT;                             /**< Trigger Status Register, offset: 0x38 */
       uint8_t RESERVED_2[4];
  __IO uint32_t OFSTRIM;                           /**< ADC Offset Trim Register, offset: 0x40 */
       uint8_t RESERVED_3[92];
  __IO uint32_t TCTRL[4];                          /**< Trigger Control Register, array offset: 0xA0, array step: 0x4 */
       uint8_t RESERVED_4[48];
  __IO uint32_t FCTRL[2];                          /**< FIFO Control Register, array offset: 0xE0, array step: 0x4 */
       uint8_t RESERVED_5[8];
  __I  uint32_t GCC[2];                            /**< Gain Calibration Control, array offset: 0xF0, array step: 0x4 */
  __IO uint32_t GCR[2];                            /**< Gain Calculation Result, array offset: 0xF8, array step: 0x4 */
  struct {                                         /* offset: 0x100, array step: 0x8 */
    __IO uint32_t CMDL;                              /**< ADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */
    __IO uint32_t CMDH;                              /**< ADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */
  } CMD[15];
       uint8_t RESERVED_6[136];
  __IO uint32_t CV[15];                            /**< Compare Value Register, array offset: 0x200, array step: 0x4 */
       uint8_t RESERVED_7[196];
  __I  uint32_t RESFIFO[2];                        /**< ADC Data Result FIFO Register, array offset: 0x300, array step: 0x4 */
       uint8_t RESERVED_8[248];
  __IO uint32_t CAL_GAR0;                          /**< Calibration General A-Side Registers, offset: 0x400 */
  __IO uint32_t CAL_GAR1;                          /**< Calibration General A-Side Registers, offset: 0x404 */
  __IO uint32_t CAL_GAR2;                          /**< Calibration General A-Side Registers, offset: 0x408 */
  __IO uint32_t CAL_GAR3;                          /**< Calibration General A-Side Registers, offset: 0x40C */
  __IO uint32_t CAL_GAR4;                          /**< Calibration General A-Side Registers, offset: 0x410 */
  __IO uint32_t CAL_GAR5;                          /**< Calibration General A-Side Registers, offset: 0x414 */
  __IO uint32_t CAL_GAR6;                          /**< Calibration General A-Side Registers, offset: 0x418 */
  __IO uint32_t CAL_GAR7;                          /**< Calibration General A-Side Registers, offset: 0x41C */
  __IO uint32_t CAL_GAR8;                          /**< Calibration General A-Side Registers, offset: 0x420 */
  __IO uint32_t CAL_GAR9;                          /**< Calibration General A-Side Registers, offset: 0x424 */
  __IO uint32_t CAL_GAR10;                         /**< Calibration General A-Side Registers, offset: 0x428 */
  __IO uint32_t CAL_GAR11;                         /**< Calibration General A-Side Registers, offset: 0x42C */
  __IO uint32_t CAL_GAR12;                         /**< Calibration General A-Side Registers, offset: 0x430 */
  __IO uint32_t CAL_GAR13;                         /**< Calibration General A-Side Registers, offset: 0x434 */
  __IO uint32_t CAL_GAR14;                         /**< Calibration General A-Side Registers, offset: 0x438 */
  __IO uint32_t CAL_GAR15;                         /**< Calibration General A-Side Registers, offset: 0x43C */
  __IO uint32_t CAL_GAR16;                         /**< Calibration General A-Side Registers, offset: 0x440 */
  __IO uint32_t CAL_GAR17;                         /**< Calibration General A-Side Registers, offset: 0x444 */
  __IO uint32_t CAL_GAR18;                         /**< Calibration General A-Side Registers, offset: 0x448 */
  __IO uint32_t CAL_GAR19;                         /**< Calibration General A-Side Registers, offset: 0x44C */
  __IO uint32_t CAL_GAR20;                         /**< Calibration General A-Side Registers, offset: 0x450 */
  __IO uint32_t CAL_GAR21;                         /**< Calibration General A-Side Registers, offset: 0x454 */
  __IO uint32_t CAL_GAR22;                         /**< Calibration General A-Side Registers, offset: 0x458 */
  __IO uint32_t CAL_GAR23;                         /**< Calibration General A-Side Registers, offset: 0x45C */
  __IO uint32_t CAL_GAR24;                         /**< Calibration General A-Side Registers, offset: 0x460 */
  __IO uint32_t CAL_GAR25;                         /**< Calibration General A-Side Registers, offset: 0x464 */
  __IO uint32_t CAL_GAR26;                         /**< Calibration General A-Side Registers, offset: 0x468 */
  __IO uint32_t CAL_GAR27;                         /**< Calibration General A-Side Registers, offset: 0x46C */
  __IO uint32_t CAL_GAR28;                         /**< Calibration General A-Side Registers, offset: 0x470 */
  __IO uint32_t CAL_GAR29;                         /**< Calibration General A-Side Registers, offset: 0x474 */
  __IO uint32_t CAL_GAR30;                         /**< Calibration General A-Side Registers, offset: 0x478 */
  __IO uint32_t CAL_GAR31;                         /**< Calibration General A-Side Registers, offset: 0x47C */
  __IO uint32_t CAL_GAR32;                         /**< Calibration General A-Side Registers, offset: 0x480 */
       uint8_t RESERVED_9[124];
  __IO uint32_t CAL_GBR0;                          /**< Calibration General B-Side Registers, offset: 0x500 */
  __IO uint32_t CAL_GBR1;                          /**< Calibration General B-Side Registers, offset: 0x504 */
  __IO uint32_t CAL_GBR2;                          /**< Calibration General B-Side Registers, offset: 0x508 */
  __IO uint32_t CAL_GBR3;                          /**< Calibration General B-Side Registers, offset: 0x50C */
  __IO uint32_t CAL_GBR4;                          /**< Calibration General B-Side Registers, offset: 0x510 */
  __IO uint32_t CAL_GBR5;                          /**< Calibration General B-Side Registers, offset: 0x514 */
  __IO uint32_t CAL_GBR6;                          /**< Calibration General B-Side Registers, offset: 0x518 */
  __IO uint32_t CAL_GBR7;                          /**< Calibration General B-Side Registers, offset: 0x51C */
  __IO uint32_t CAL_GBR8;                          /**< Calibration General B-Side Registers, offset: 0x520 */
  __IO uint32_t CAL_GBR9;                          /**< Calibration General B-Side Registers, offset: 0x524 */
  __IO uint32_t CAL_GBR10;                         /**< Calibration General B-Side Registers, offset: 0x528 */
  __IO uint32_t CAL_GBR11;                         /**< Calibration General B-Side Registers, offset: 0x52C */
  __IO uint32_t CAL_GBR12;                         /**< Calibration General B-Side Registers, offset: 0x530 */
  __IO uint32_t CAL_GBR13;                         /**< Calibration General B-Side Registers, offset: 0x534 */
  __IO uint32_t CAL_GBR14;                         /**< Calibration General B-Side Registers, offset: 0x538 */
  __IO uint32_t CAL_GBR15;                         /**< Calibration General B-Side Registers, offset: 0x53C */
  __IO uint32_t CAL_GBR16;                         /**< Calibration General B-Side Registers, offset: 0x540 */
  __IO uint32_t CAL_GBR17;                         /**< Calibration General B-Side Registers, offset: 0x544 */
  __IO uint32_t CAL_GBR18;                         /**< Calibration General B-Side Registers, offset: 0x548 */
  __IO uint32_t CAL_GBR19;                         /**< Calibration General B-Side Registers, offset: 0x54C */
  __IO uint32_t CAL_GBR20;                         /**< Calibration General B-Side Registers, offset: 0x550 */
  __IO uint32_t CAL_GBR21;                         /**< Calibration General B-Side Registers, offset: 0x554 */
  __IO uint32_t CAL_GBR22;                         /**< Calibration General B-Side Registers, offset: 0x558 */
  __IO uint32_t CAL_GBR23;                         /**< Calibration General B-Side Registers, offset: 0x55C */
  __IO uint32_t CAL_GBR24;                         /**< Calibration General B-Side Registers, offset: 0x560 */
  __IO uint32_t CAL_GBR25;                         /**< Calibration General B-Side Registers, offset: 0x564 */
  __IO uint32_t CAL_GBR26;                         /**< Calibration General B-Side Registers, offset: 0x568 */
  __IO uint32_t CAL_GBR27;                         /**< Calibration General B-Side Registers, offset: 0x56C */
  __IO uint32_t CAL_GBR28;                         /**< Calibration General B-Side Registers, offset: 0x570 */
  __IO uint32_t CAL_GBR29;                         /**< Calibration General B-Side Registers, offset: 0x574 */
  __IO uint32_t CAL_GBR30;                         /**< Calibration General B-Side Registers, offset: 0x578 */
  __IO uint32_t CAL_GBR31;                         /**< Calibration General B-Side Registers, offset: 0x57C */
  __IO uint32_t CAL_GBR32;                         /**< Calibration General B-Side Registers, offset: 0x580 */
} ADC_Type;

/* ----------------------------------------------------------------------------
   -- ADC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup ADC_Register_Masks ADC Register Masks
 * @{
 */

/*! @name VERID - Version ID Register */
/*! @{ */

#define ADC_VERID_RES_MASK                       (0x1U)
#define ADC_VERID_RES_SHIFT                      (0U)
/*! RES - Resolution
 *  0b0..Up to 13-bit differential/12-bit single ended resolution supported.
 *  0b1..Up to 16-bit differential/16-bit single ended resolution supported.
 */
#define ADC_VERID_RES(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK)

#define ADC_VERID_DIFFEN_MASK                    (0x2U)
#define ADC_VERID_DIFFEN_SHIFT                   (1U)
/*! DIFFEN - Differential Supported
 *  0b0..Differential operation not supported.
 *  0b1..Differential operation supported. CMDLa[CTYPE] controls fields implemented.
 */
#define ADC_VERID_DIFFEN(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK)

#define ADC_VERID_MVI_MASK                       (0x8U)
#define ADC_VERID_MVI_SHIFT                      (3U)
/*! MVI - Multi Vref Implemented
 *  0b0..Single voltage reference high (VREFH) input supported.
 *  0b1..Multiple voltage reference high (VREFH) inputs supported.
 */
#define ADC_VERID_MVI(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK)

#define ADC_VERID_CSW_MASK                       (0x70U)
#define ADC_VERID_CSW_SHIFT                      (4U)
/*! CSW - Channel Scale Width
 *  0b000..Channel scaling not supported.
 *  0b001..Channel scaling supported. 1-bit CSCALE control field.
 *  0b110..Channel scaling supported. 6-bit CSCALE control field.
 */
#define ADC_VERID_CSW(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK)

#define ADC_VERID_VR1RNGI_MASK                   (0x100U)
#define ADC_VERID_VR1RNGI_SHIFT                  (8U)
/*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented
 *  0b0..Range control not required. CFG[VREF1RNG] is not implemented.
 *  0b1..Range control required. CFG[VREF1RNG] is implemented.
 */
#define ADC_VERID_VR1RNGI(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK)

#define ADC_VERID_IADCKI_MASK                    (0x200U)
#define ADC_VERID_IADCKI_SHIFT                   (9U)
/*! IADCKI - Internal ADC Clock implemented
 *  0b0..Internal clock source not implemented.
 *  0b1..Internal clock source (and CFG[ADCKEN]) implemented.
 */
#define ADC_VERID_IADCKI(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK)

#define ADC_VERID_CALOFSI_MASK                   (0x400U)
#define ADC_VERID_CALOFSI_SHIFT                  (10U)
/*! CALOFSI - Calibration Function Implemented
 *  0b0..Calibration Not Implemented.
 *  0b1..Calibration Implemented.
 */
#define ADC_VERID_CALOFSI(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK)

#define ADC_VERID_NUM_SEC_MASK                   (0x800U)
#define ADC_VERID_NUM_SEC_SHIFT                  (11U)
/*! NUM_SEC - Number of Single Ended Outputs Supported
 *  0b0..This design supports one single ended conversion at a time.
 *  0b1..This design supports two simultanious single ended conversions.
 */
#define ADC_VERID_NUM_SEC(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_SEC_SHIFT)) & ADC_VERID_NUM_SEC_MASK)

#define ADC_VERID_NUM_FIFO_MASK                  (0x7000U)
#define ADC_VERID_NUM_FIFO_SHIFT                 (12U)
/*! NUM_FIFO - Number of FIFOs
 *  0b000..N/A
 *  0b001..This design supports one result FIFO.
 *  0b010..This design supports two result FIFOs.
 *  0b011..This design supports three result FIFOs.
 *  0b100..This design supports four result FIFOs.
 */
#define ADC_VERID_NUM_FIFO(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_FIFO_SHIFT)) & ADC_VERID_NUM_FIFO_MASK)

#define ADC_VERID_MINOR_MASK                     (0xFF0000U)
#define ADC_VERID_MINOR_SHIFT                    (16U)
/*! MINOR - Minor Version Number
 */
#define ADC_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK)

#define ADC_VERID_MAJOR_MASK                     (0xFF000000U)
#define ADC_VERID_MAJOR_SHIFT                    (24U)
/*! MAJOR - Major Version Number
 */
#define ADC_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK)
/*! @} */

/*! @name PARAM - Parameter Register */
/*! @{ */

#define ADC_PARAM_TRIG_NUM_MASK                  (0xFFU)
#define ADC_PARAM_TRIG_NUM_SHIFT                 (0U)
/*! TRIG_NUM - Trigger Number
 */
#define ADC_PARAM_TRIG_NUM(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK)

#define ADC_PARAM_FIFOSIZE_MASK                  (0xFF00U)
#define ADC_PARAM_FIFOSIZE_SHIFT                 (8U)
/*! FIFOSIZE - Result FIFO Depth
 *  0b00000001..Result FIFO depth = 2 dataword.
 *  0b00000100..Result FIFO depth = 4 datawords.
 *  0b00001000..Result FIFO depth = 8 datawords.
 *  0b00010000..Result FIFO depth = 16 datawords.
 *  0b00100000..Result FIFO depth = 32 datawords.
 *  0b01000000..Result FIFO depth = 64 datawords.
 */
#define ADC_PARAM_FIFOSIZE(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK)

#define ADC_PARAM_CV_NUM_MASK                    (0xFF0000U)
#define ADC_PARAM_CV_NUM_SHIFT                   (16U)
/*! CV_NUM - Compare Value Number
 */
#define ADC_PARAM_CV_NUM(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK)

#define ADC_PARAM_CMD_NUM_MASK                   (0xFF000000U)
#define ADC_PARAM_CMD_NUM_SHIFT                  (24U)
/*! CMD_NUM - Command Buffer Number
 */
#define ADC_PARAM_CMD_NUM(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK)
/*! @} */

/*! @name CTRL - ADC Control Register */
/*! @{ */

#define ADC_CTRL_ADCEN_MASK                      (0x1U)
#define ADC_CTRL_ADCEN_SHIFT                     (0U)
/*! ADCEN - ADC Enable
 *  0b0..ADC is disabled.
 *  0b1..ADC is enabled.
 */
#define ADC_CTRL_ADCEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK)

#define ADC_CTRL_RST_MASK                        (0x2U)
#define ADC_CTRL_RST_SHIFT                       (1U)
/*! RST - Software Reset
 *  0b0..ADC logic is not reset.
 *  0b1..ADC logic is reset.
 */
#define ADC_CTRL_RST(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK)

#define ADC_CTRL_DOZEN_MASK                      (0x4U)
#define ADC_CTRL_DOZEN_SHIFT                     (2U)
/*! DOZEN - Doze Enable
 *  0b0..ADC is enabled in low power mode.
 *  0b1..ADC is disabled in low power mode.
 */
#define ADC_CTRL_DOZEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK)

#define ADC_CTRL_CAL_REQ_MASK                    (0x8U)
#define ADC_CTRL_CAL_REQ_SHIFT                   (3U)
/*! CAL_REQ - Auto-Calibration Request
 *  0b0..No request for hardware calibration has been made.
 *  0b1..A request for hardware calibration has been made
 */
#define ADC_CTRL_CAL_REQ(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_REQ_SHIFT)) & ADC_CTRL_CAL_REQ_MASK)

#define ADC_CTRL_CALOFS_MASK                     (0x10U)
#define ADC_CTRL_CALOFS_SHIFT                    (4U)
/*! CALOFS - Offset Calibration Request
 *  0b0..Calibration function disabled
 *  0b1..Request for offset calibration function
 */
#define ADC_CTRL_CALOFS(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALOFS_SHIFT)) & ADC_CTRL_CALOFS_MASK)

#define ADC_CTRL_RSTFIFO0_MASK                   (0x100U)
#define ADC_CTRL_RSTFIFO0_SHIFT                  (8U)
/*! RSTFIFO0 - Reset FIFO 0
 *  0b0..No effect.
 *  0b1..FIFO 0 is reset.
 */
#define ADC_CTRL_RSTFIFO0(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO0_SHIFT)) & ADC_CTRL_RSTFIFO0_MASK)

#define ADC_CTRL_RSTFIFO1_MASK                   (0x200U)
#define ADC_CTRL_RSTFIFO1_SHIFT                  (9U)
/*! RSTFIFO1 - Reset FIFO 1
 *  0b0..No effect.
 *  0b1..FIFO 1 is reset.
 */
#define ADC_CTRL_RSTFIFO1(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO1_SHIFT)) & ADC_CTRL_RSTFIFO1_MASK)

#define ADC_CTRL_CAL_AVGS_MASK                   (0x70000U)
#define ADC_CTRL_CAL_AVGS_SHIFT                  (16U)
/*! CAL_AVGS - Auto-Calibration Averages
 *  0b000..Single conversion.
 *  0b001..2 conversions averaged.
 *  0b010..4 conversions averaged.
 *  0b011..8 conversions averaged.
 *  0b100..16 conversions averaged.
 *  0b101..32 conversions averaged.
 *  0b110..64 conversions averaged.
 *  0b111..128 conversions averaged.
 */
#define ADC_CTRL_CAL_AVGS(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_AVGS_SHIFT)) & ADC_CTRL_CAL_AVGS_MASK)
/*! @} */

/*! @name STAT - ADC Status Register */
/*! @{ */

#define ADC_STAT_RDY0_MASK                       (0x1U)
#define ADC_STAT_RDY0_SHIFT                      (0U)
/*! RDY0 - Result FIFO 0 Ready Flag
 *  0b0..Result FIFO 0 data level not above watermark level.
 *  0b1..Result FIFO 0 holding data above watermark level.
 */
#define ADC_STAT_RDY0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY0_SHIFT)) & ADC_STAT_RDY0_MASK)

#define ADC_STAT_FOF0_MASK                       (0x2U)
#define ADC_STAT_FOF0_SHIFT                      (1U)
/*! FOF0 - Result FIFO 0 Overflow Flag
 *  0b0..No result FIFO 0 overflow has occurred since the last time the flag was cleared.
 *  0b1..At least one result FIFO 0 overflow has occurred since the last time the flag was cleared.
 */
#define ADC_STAT_FOF0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF0_SHIFT)) & ADC_STAT_FOF0_MASK)

#define ADC_STAT_RDY1_MASK                       (0x4U)
#define ADC_STAT_RDY1_SHIFT                      (2U)
/*! RDY1 - Result FIFO1 Ready Flag
 *  0b0..Result FIFO1 data level not above watermark level.
 *  0b1..Result FIFO1 holding data above watermark level.
 */
#define ADC_STAT_RDY1(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY1_SHIFT)) & ADC_STAT_RDY1_MASK)

#define ADC_STAT_FOF1_MASK                       (0x8U)
#define ADC_STAT_FOF1_SHIFT                      (3U)
/*! FOF1 - Result FIFO1 Overflow Flag
 *  0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared.
 *  0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared.
 */
#define ADC_STAT_FOF1(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF1_SHIFT)) & ADC_STAT_FOF1_MASK)

#define ADC_STAT_TEXC_INT_MASK                   (0x100U)
#define ADC_STAT_TEXC_INT_SHIFT                  (8U)
/*! TEXC_INT - Interrupt Flag For High Priority Trigger Exception
 *  0b0..No trigger exceptions have occurred.
 *  0b1..A trigger exception has occurred and is pending acknowledgement.
 */
#define ADC_STAT_TEXC_INT(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TEXC_INT_SHIFT)) & ADC_STAT_TEXC_INT_MASK)

#define ADC_STAT_TCOMP_INT_MASK                  (0x200U)
#define ADC_STAT_TCOMP_INT_SHIFT                 (9U)
/*! TCOMP_INT - Interrupt Flag For Trigger Completion
 *  0b0..Either IE[TCOMP_IE] is set to 0, or no trigger sequences have run to completion.
 *  0b1..Trigger sequence has been completed and all data is stored in the associated FIFO.
 */
#define ADC_STAT_TCOMP_INT(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TCOMP_INT_SHIFT)) & ADC_STAT_TCOMP_INT_MASK)

#define ADC_STAT_CAL_RDY_MASK                    (0x400U)
#define ADC_STAT_CAL_RDY_SHIFT                   (10U)
/*! CAL_RDY - Calibration Ready
 *  0b0..Calibration is incomplete or hasn't been ran.
 *  0b1..The ADC is calibrated.
 */
#define ADC_STAT_CAL_RDY(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CAL_RDY_SHIFT)) & ADC_STAT_CAL_RDY_MASK)

#define ADC_STAT_ADC_ACTIVE_MASK                 (0x800U)
#define ADC_STAT_ADC_ACTIVE_SHIFT                (11U)
/*! ADC_ACTIVE - ADC Active
 *  0b0..The ADC is IDLE. There are no pending triggers to service and no active commands are being processed.
 *  0b1..The ADC is processing a conversion, running through the power up delay, or servicing a trigger.
 */
#define ADC_STAT_ADC_ACTIVE(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK)

#define ADC_STAT_TRGACT_MASK                     (0x30000U)
#define ADC_STAT_TRGACT_SHIFT                    (16U)
/*! TRGACT - Trigger Active
 *  0b00..Command (sequence) associated with Trigger 0 currently being executed.
 *  0b01..Command (sequence) associated with Trigger 1 currently being executed.
 *  0b10..Command (sequence) associated with Trigger 2 currently being executed.
 *  0b11..Command (sequence) associated with Trigger 3 currently being executed.
 */
#define ADC_STAT_TRGACT(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK)

#define ADC_STAT_CMDACT_MASK                     (0xF000000U)
#define ADC_STAT_CMDACT_SHIFT                    (24U)
/*! CMDACT - Command Active
 *  0b0000..No command is currently in progress.
 *  0b0001..Command 1 currently being executed.
 *  0b0010..Command 2 currently being executed.
 *  0b0011-0b1111..Associated command number is currently being executed.
 */
#define ADC_STAT_CMDACT(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK)
/*! @} */

/*! @name IE - Interrupt Enable Register */
/*! @{ */

#define ADC_IE_FWMIE0_MASK                       (0x1U)
#define ADC_IE_FWMIE0_SHIFT                      (0U)
/*! FWMIE0 - FIFO 0 Watermark Interrupt Enable
 *  0b0..FIFO 0 watermark interrupts are not enabled.
 *  0b1..FIFO 0 watermark interrupts are enabled.
 */
#define ADC_IE_FWMIE0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE0_SHIFT)) & ADC_IE_FWMIE0_MASK)

#define ADC_IE_FOFIE0_MASK                       (0x2U)
#define ADC_IE_FOFIE0_SHIFT                      (1U)
/*! FOFIE0 - Result FIFO 0 Overflow Interrupt Enable
 *  0b0..FIFO 0 overflow interrupts are not enabled.
 *  0b1..FIFO 0 overflow interrupts are enabled.
 */
#define ADC_IE_FOFIE0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE0_SHIFT)) & ADC_IE_FOFIE0_MASK)

#define ADC_IE_FWMIE1_MASK                       (0x4U)
#define ADC_IE_FWMIE1_SHIFT                      (2U)
/*! FWMIE1 - FIFO1 Watermark Interrupt Enable
 *  0b0..FIFO1 watermark interrupts are not enabled.
 *  0b1..FIFO1 watermark interrupts are enabled.
 */
#define ADC_IE_FWMIE1(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE1_SHIFT)) & ADC_IE_FWMIE1_MASK)

#define ADC_IE_FOFIE1_MASK                       (0x8U)
#define ADC_IE_FOFIE1_SHIFT                      (3U)
/*! FOFIE1 - Result FIFO1 Overflow Interrupt Enable
 *  0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared.
 *  0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared.
 */
#define ADC_IE_FOFIE1(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE1_SHIFT)) & ADC_IE_FOFIE1_MASK)

#define ADC_IE_TEXC_IE_MASK                      (0x100U)
#define ADC_IE_TEXC_IE_SHIFT                     (8U)
/*! TEXC_IE - Trigger Exception Interrupt Enable
 *  0b0..Trigger exception interrupts are disabled.
 *  0b1..Trigger exception interrupts are enabled.
 */
#define ADC_IE_TEXC_IE(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_IE_TEXC_IE_SHIFT)) & ADC_IE_TEXC_IE_MASK)

#define ADC_IE_TCOMP_IE_MASK                     (0xF0000U)
#define ADC_IE_TCOMP_IE_SHIFT                    (16U)
/*! TCOMP_IE - Trigger Completion Interrupt Enable
 *  0b0000..Trigger completion interrupts are disabled.
 *  0b0001..Trigger completion interrupts are enabled for trigger source 0 only.
 *  0b0010..Trigger completion interrupts are enabled for trigger source 1 only.
 *  0b0011-0b1110..Associated trigger completion interrupts are enabled.
 *  0b1111..Trigger completion interrupts are enabled for every trigger source.
 */
#define ADC_IE_TCOMP_IE(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_IE_TCOMP_IE_SHIFT)) & ADC_IE_TCOMP_IE_MASK)
/*! @} */

/*! @name DE - DMA Enable Register */
/*! @{ */

#define ADC_DE_FWMDE0_MASK                       (0x1U)
#define ADC_DE_FWMDE0_SHIFT                      (0U)
/*! FWMDE0 - FIFO 0 Watermark DMA Enable
 *  0b0..DMA request disabled.
 *  0b1..DMA request enabled.
 */
#define ADC_DE_FWMDE0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE0_SHIFT)) & ADC_DE_FWMDE0_MASK)

#define ADC_DE_FWMDE1_MASK                       (0x2U)
#define ADC_DE_FWMDE1_SHIFT                      (1U)
/*! FWMDE1 - FIFO1 Watermark DMA Enable
 *  0b0..DMA request disabled.
 *  0b1..DMA request enabled.
 */
#define ADC_DE_FWMDE1(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE1_SHIFT)) & ADC_DE_FWMDE1_MASK)
/*! @} */

/*! @name CFG - ADC Configuration Register */
/*! @{ */

#define ADC_CFG_TPRICTRL_MASK                    (0x3U)
#define ADC_CFG_TPRICTRL_SHIFT                   (0U)
/*! TPRICTRL - ADC trigger priority control
 *  0b00..If a higher priority trigger is detected during command processing, the current conversion is aborted
 *        and the new command specified by the trigger is started.
 *  0b01..If a higher priority trigger is received during command processing, the current command is stopped after
 *        completing the current conversion. If averaging is enabled, the averaging loop will be completed.
 *        However, CMDHa[LOOP] will be ignored and the higher priority trigger will be serviced.
 *  0b10..If a higher priority trigger is received during command processing, the current command will be
 *        completed (averaging, looping, compare) before servicing the higher priority trigger.
 *  0b11..RESERVED
 */
#define ADC_CFG_TPRICTRL(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK)

#define ADC_CFG_PWRSEL_MASK                      (0x30U)
#define ADC_CFG_PWRSEL_SHIFT                     (4U)
/*! PWRSEL - Power Configuration Select
 *  0b0x..Low power setting.
 *  0b1x..High power setting.
 */
#define ADC_CFG_PWRSEL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK)

#define ADC_CFG_REFSEL_MASK                      (0xC0U)
#define ADC_CFG_REFSEL_SHIFT                     (6U)
/*! REFSEL - Voltage Reference Selection
 *  0b00..(Default) Option 1 setting.
 *  0b01..Option 2 setting.
 *  0b10..Option 3 setting.
 *  0b11..Reserved
 */
#define ADC_CFG_REFSEL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)

#define ADC_CFG_TRES_MASK                        (0x100U)
#define ADC_CFG_TRES_SHIFT                       (8U)
/*! TRES - Trigger Resume Enable
 *  0b0..Trigger sequences interrupted by a high priority trigger exception are not automatically resumed or restarted.
 *  0b1..Trigger sequences interrupted by a high priority trigger exception are automatically resumed or restarted.
 */
#define ADC_CFG_TRES(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TRES_SHIFT)) & ADC_CFG_TRES_MASK)

#define ADC_CFG_TCMDRES_MASK                     (0x200U)
#define ADC_CFG_TCMDRES_SHIFT                    (9U)
/*! TCMDRES - Trigger Command Resume
 *  0b0..Trigger sequences interrupted by a high priority trigger exception is automatically restarted.
 *  0b1..Trigger sequences interrupted by a high priority trigger exception is resumed from the command executing before the exception.
 */
#define ADC_CFG_TCMDRES(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TCMDRES_SHIFT)) & ADC_CFG_TCMDRES_MASK)

#define ADC_CFG_HPT_EXDI_MASK                    (0x400U)
#define ADC_CFG_HPT_EXDI_SHIFT                   (10U)
/*! HPT_EXDI - High Priority Trigger Exception Disable
 *  0b0..High priority trigger exceptions are enabled.
 *  0b1..High priority trigger exceptions are disabled.
 */
#define ADC_CFG_HPT_EXDI(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CFG_HPT_EXDI_SHIFT)) & ADC_CFG_HPT_EXDI_MASK)

#define ADC_CFG_PUDLY_MASK                       (0xFF0000U)
#define ADC_CFG_PUDLY_SHIFT                      (16U)
/*! PUDLY - Power Up Delay
 */
#define ADC_CFG_PUDLY(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK)

#define ADC_CFG_PWREN_MASK                       (0x10000000U)
#define ADC_CFG_PWREN_SHIFT                      (28U)
/*! PWREN - ADC Analog Pre-Enable
 *  0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays.
 *  0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost
 *       of higher DC current consumption). Note that a single power up delay (CFG[PUDLY]) is executed immediately
 *       once PWREN is set, and any detected trigger does not begin ADC operation until the power up delay time has
 *       passed. After this initial delay expires the analog remains pre-enabled and no additional delays are
 *       executed.
 */
#define ADC_CFG_PWREN(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK)
/*! @} */

/*! @name PAUSE - ADC Pause Register */
/*! @{ */

#define ADC_PAUSE_PAUSEDLY_MASK                  (0x1FFU)
#define ADC_PAUSE_PAUSEDLY_SHIFT                 (0U)
/*! PAUSEDLY - Pause Delay
 */
#define ADC_PAUSE_PAUSEDLY(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK)

#define ADC_PAUSE_PAUSEEN_MASK                   (0x80000000U)
#define ADC_PAUSE_PAUSEEN_SHIFT                  (31U)
/*! PAUSEEN - PAUSE Option Enable
 *  0b0..Pause operation disabled
 *  0b1..Pause operation enabled
 */
#define ADC_PAUSE_PAUSEEN(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK)
/*! @} */

/*! @name SWTRIG - Software Trigger Register */
/*! @{ */

#define ADC_SWTRIG_SWT0_MASK                     (0x1U)
#define ADC_SWTRIG_SWT0_SHIFT                    (0U)
/*! SWT0 - Software trigger 0 event
 *  0b0..No trigger 0 event generated.
 *  0b1..Trigger 0 event generated.
 */
#define ADC_SWTRIG_SWT0(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK)

#define ADC_SWTRIG_SWT1_MASK                     (0x2U)
#define ADC_SWTRIG_SWT1_SHIFT                    (1U)
/*! SWT1 - Software trigger 1 event
 *  0b0..No trigger 1 event generated.
 *  0b1..Trigger 1 event generated.
 */
#define ADC_SWTRIG_SWT1(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK)

#define ADC_SWTRIG_SWT2_MASK                     (0x4U)
#define ADC_SWTRIG_SWT2_SHIFT                    (2U)
/*! SWT2 - Software trigger 2 event
 *  0b0..No trigger 2 event generated.
 *  0b1..Trigger 2 event generated.
 */
#define ADC_SWTRIG_SWT2(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK)

#define ADC_SWTRIG_SWT3_MASK                     (0x8U)
#define ADC_SWTRIG_SWT3_SHIFT                    (3U)
/*! SWT3 - Software trigger 3 event
 *  0b0..No trigger 3 event generated.
 *  0b1..Trigger 3 event generated.
 */
#define ADC_SWTRIG_SWT3(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK)
/*! @} */

/*! @name TSTAT - Trigger Status Register */
/*! @{ */

#define ADC_TSTAT_TEXC_NUM_MASK                  (0xFU)
#define ADC_TSTAT_TEXC_NUM_SHIFT                 (0U)
/*! TEXC_NUM - Trigger Exception Number
 *  0b0000..No triggers have been interrupted by a high priority exception. Or CFG[TRES] = 1.
 *  0b0001..Trigger 0 has been interrupted by a high priority exception.
 *  0b0010..Trigger 1 has been interrupted by a high priority exception.
 *  0b0011-0b1110..Associated trigger sequence has interrupted by a high priority exception.
 *  0b1111..Every trigger sequence has been interrupted by a high priority exception.
 */
#define ADC_TSTAT_TEXC_NUM(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TEXC_NUM_SHIFT)) & ADC_TSTAT_TEXC_NUM_MASK)

#define ADC_TSTAT_TCOMP_FLAG_MASK                (0xF0000U)
#define ADC_TSTAT_TCOMP_FLAG_SHIFT               (16U)
/*! TCOMP_FLAG - Trigger Completion Flag
 *  0b0000..No triggers have been completed. Trigger completion interrupts are disabled.
 *  0b0001..Trigger 0 has been completed and trigger 0 has enabled completion interrupts.
 *  0b0010..Trigger 1 has been completed and trigger 1 has enabled completion interrupts.
 *  0b0011-0b1110..Associated trigger sequence has completed and has enabled completion interrupts.
 *  0b1111..Every trigger sequence has been completed and every trigger has enabled completion interrupts.
 */
#define ADC_TSTAT_TCOMP_FLAG(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TCOMP_FLAG_SHIFT)) & ADC_TSTAT_TCOMP_FLAG_MASK)
/*! @} */

/*! @name OFSTRIM - ADC Offset Trim Register */
/*! @{ */

#define ADC_OFSTRIM_OFSTRIM_A_MASK               (0x1FU)
#define ADC_OFSTRIM_OFSTRIM_A_SHIFT              (0U)
/*! OFSTRIM_A - Trim for offset
 */
#define ADC_OFSTRIM_OFSTRIM_A(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_A_SHIFT)) & ADC_OFSTRIM_OFSTRIM_A_MASK)

#define ADC_OFSTRIM_OFSTRIM_B_MASK               (0x1F0000U)
#define ADC_OFSTRIM_OFSTRIM_B_SHIFT              (16U)
/*! OFSTRIM_B - Trim for offset
 */
#define ADC_OFSTRIM_OFSTRIM_B(x)                 (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_B_SHIFT)) & ADC_OFSTRIM_OFSTRIM_B_MASK)
/*! @} */

/*! @name TCTRL - Trigger Control Register */
/*! @{ */

#define ADC_TCTRL_HTEN_MASK                      (0x1U)
#define ADC_TCTRL_HTEN_SHIFT                     (0U)
/*! HTEN - Trigger enable
 *  0b0..Hardware trigger source disabled
 *  0b1..Hardware trigger source enabled
 */
#define ADC_TCTRL_HTEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK)

#define ADC_TCTRL_FIFO_SEL_A_MASK                (0x2U)
#define ADC_TCTRL_FIFO_SEL_A_SHIFT               (1U)
/*! FIFO_SEL_A - SAR Result Destination For Channel A
 *  0b0..Result written to FIFO 0
 *  0b1..Result written to FIFO 1
 */
#define ADC_TCTRL_FIFO_SEL_A(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_A_SHIFT)) & ADC_TCTRL_FIFO_SEL_A_MASK)

#define ADC_TCTRL_FIFO_SEL_B_MASK                (0x4U)
#define ADC_TCTRL_FIFO_SEL_B_SHIFT               (2U)
/*! FIFO_SEL_B - SAR Result Destination For Channel B
 *  0b0..Result written to FIFO 0
 *  0b1..Result written to FIFO 1
 */
#define ADC_TCTRL_FIFO_SEL_B(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_B_SHIFT)) & ADC_TCTRL_FIFO_SEL_B_MASK)

#define ADC_TCTRL_TPRI_MASK                      (0x300U)
#define ADC_TCTRL_TPRI_SHIFT                     (8U)
/*! TPRI - Trigger priority setting
 *  0b00..Set to highest priority, Level 1
 *  0b01-0b10..Set to corresponding priority level
 *  0b11..Set to lowest priority, Level 4
 */
#define ADC_TCTRL_TPRI(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK)

#define ADC_TCTRL_RSYNC_MASK                     (0x8000U)
#define ADC_TCTRL_RSYNC_SHIFT                    (15U)
/*! RSYNC - Trigger Resync
 */
#define ADC_TCTRL_RSYNC(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_RSYNC_SHIFT)) & ADC_TCTRL_RSYNC_MASK)

#define ADC_TCTRL_TDLY_MASK                      (0xF0000U)
#define ADC_TCTRL_TDLY_SHIFT                     (16U)
/*! TDLY - Trigger delay select
 */
#define ADC_TCTRL_TDLY(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK)

#define ADC_TCTRL_TCMD_MASK                      (0xF000000U)
#define ADC_TCTRL_TCMD_SHIFT                     (24U)
/*! TCMD - Trigger command select
 *  0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
 *  0b0001..CMD1 is executed
 *  0b0010-0b1110..Corresponding CMD is executed
 *  0b1111..CMD15 is executed
 */
#define ADC_TCTRL_TCMD(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK)
/*! @} */

/* The count of ADC_TCTRL */
#define ADC_TCTRL_COUNT                          (4U)

/*! @name FCTRL - FIFO Control Register */
/*! @{ */

#define ADC_FCTRL_FCOUNT_MASK                    (0x1FU)
#define ADC_FCTRL_FCOUNT_SHIFT                   (0U)
/*! FCOUNT - Result FIFO counter
 */
#define ADC_FCTRL_FCOUNT(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK)

#define ADC_FCTRL_FWMARK_MASK                    (0xF0000U)
#define ADC_FCTRL_FWMARK_SHIFT                   (16U)
/*! FWMARK - Watermark level selection
 */
#define ADC_FCTRL_FWMARK(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK)
/*! @} */

/* The count of ADC_FCTRL */
#define ADC_FCTRL_COUNT                          (2U)

/*! @name GCC - Gain Calibration Control */
/*! @{ */

#define ADC_GCC_GAIN_CAL_MASK                    (0xFFFFU)
#define ADC_GCC_GAIN_CAL_SHIFT                   (0U)
/*! GAIN_CAL - Gain Calibration Value
 */
#define ADC_GCC_GAIN_CAL(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_GCC_GAIN_CAL_SHIFT)) & ADC_GCC_GAIN_CAL_MASK)

#define ADC_GCC_RDY_MASK                         (0x1000000U)
#define ADC_GCC_RDY_SHIFT                        (24U)
/*! RDY - Gain Calibration Value Valid
 *  0b0..The GAIN_CAL value is invalid. Run the hardware calibration routine for this value to be set.
 *  0b1..The GAIN_CAL value is valid. GAIN_CAL should be used by software to derive GCRa[GCALR].
 */
#define ADC_GCC_RDY(x)                           (((uint32_t)(((uint32_t)(x)) << ADC_GCC_RDY_SHIFT)) & ADC_GCC_RDY_MASK)
/*! @} */

/* The count of ADC_GCC */
#define ADC_GCC_COUNT                            (2U)

/*! @name GCR - Gain Calculation Result */
/*! @{ */

#define ADC_GCR_GCALR_MASK                       (0xFFFFU)
#define ADC_GCR_GCALR_SHIFT                      (0U)
/*! GCALR - Gain Calculation Result
 */
#define ADC_GCR_GCALR(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_GCR_GCALR_SHIFT)) & ADC_GCR_GCALR_MASK)

#define ADC_GCR_RDY_MASK                         (0x1000000U)
#define ADC_GCR_RDY_SHIFT                        (24U)
/*! RDY - Gain Calculation Ready
 *  0b0..The GCALR value is invalid.
 *  0b1..The GCALR value is valid.
 */
#define ADC_GCR_RDY(x)                           (((uint32_t)(((uint32_t)(x)) << ADC_GCR_RDY_SHIFT)) & ADC_GCR_RDY_MASK)
/*! @} */

/* The count of ADC_GCR */
#define ADC_GCR_COUNT                            (2U)

/*! @name CMDL - ADC Command Low Buffer Register */
/*! @{ */

#define ADC_CMDL_ADCH_MASK                       (0x1FU)
#define ADC_CMDL_ADCH_SHIFT                      (0U)
/*! ADCH - Input channel select
 *  0b00000..Select CH0A or CH0B or CH0A/CH0B pair.
 *  0b00001..Select CH1A or CH1B or CH1A/CH1B pair.
 *  0b00010..Select CH2A or CH2B or CH2A/CH2B pair.
 *  0b00011..Select CH3A or CH3B or CH3A/CH3B pair.
 *  0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
 *  0b11110..Select CH30A or CH30B or CH30A/CH30B pair.
 *  0b11111..Select CH31A or CH31B or CH31A/CH31B pair.
 */
#define ADC_CMDL_ADCH(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK)

#define ADC_CMDL_CTYPE_MASK                      (0x60U)
#define ADC_CMDL_CTYPE_SHIFT                     (5U)
/*! CTYPE - Conversion Type
 *  0b00..Single-Ended Mode. Only A side channel is converted.
 *  0b01..Single-Ended Mode. Only B side channel is converted.
 *  0b10..Differential Mode. A-B.
 *  0b11..Dual-Single-Ended Mode. Both A side and B side channels are converted independently.
 */
#define ADC_CMDL_CTYPE(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CTYPE_SHIFT)) & ADC_CMDL_CTYPE_MASK)

#define ADC_CMDL_MODE_MASK                       (0x80U)
#define ADC_CMDL_MODE_SHIFT                      (7U)
/*! MODE - Select resolution of conversions
 *  0b0..Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output.
 *  0b1..High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output.
 */
#define ADC_CMDL_MODE(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_MODE_SHIFT)) & ADC_CMDL_MODE_MASK)
/*! @} */

/* The count of ADC_CMDL */
#define ADC_CMDL_COUNT                           (15U)

/*! @name CMDH - ADC Command High Buffer Register */
/*! @{ */

#define ADC_CMDH_CMPEN_MASK                      (0x3U)
#define ADC_CMDH_CMPEN_SHIFT                     (0U)
/*! CMPEN - Compare Function Enable
 *  0b00..Compare disabled.
 *  0b01..Reserved
 *  0b10..Compare enabled. Store on true.
 *  0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.
 */
#define ADC_CMDH_CMPEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK)

#define ADC_CMDH_WAIT_TRIG_MASK                  (0x4U)
#define ADC_CMDH_WAIT_TRIG_SHIFT                 (2U)
/*! WAIT_TRIG - Wait for trigger assertion before execution.
 *  0b0..This command will be automatically executed.
 *  0b1..The active trigger must be asserted again before executing this command.
 */
#define ADC_CMDH_WAIT_TRIG(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_WAIT_TRIG_SHIFT)) & ADC_CMDH_WAIT_TRIG_MASK)

#define ADC_CMDH_LWI_MASK                        (0x80U)
#define ADC_CMDH_LWI_SHIFT                       (7U)
/*! LWI - Loop with Increment
 *  0b0..Auto channel increment disabled
 *  0b1..Auto channel increment enabled
 */
#define ADC_CMDH_LWI(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK)

#define ADC_CMDH_STS_MASK                        (0x700U)
#define ADC_CMDH_STS_SHIFT                       (8U)
/*! STS - Sample Time Select
 *  0b000..Minimum sample time of 3.5 ADCK cycles.
 *  0b001..3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time.
 *  0b010..3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time.
 *  0b011..3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time.
 *  0b100..3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time.
 *  0b101..3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time.
 *  0b110..3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time.
 *  0b111..3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time.
 */
#define ADC_CMDH_STS(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK)

#define ADC_CMDH_AVGS_MASK                       (0x7000U)
#define ADC_CMDH_AVGS_SHIFT                      (12U)
/*! AVGS - Hardware Average Select
 *  0b000..Single conversion.
 *  0b001..2 conversions averaged.
 *  0b010..4 conversions averaged.
 *  0b011..8 conversions averaged.
 *  0b100..16 conversions averaged.
 *  0b101..32 conversions averaged.
 *  0b110..64 conversions averaged.
 *  0b111..128 conversions averaged.
 */
#define ADC_CMDH_AVGS(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK)

#define ADC_CMDH_LOOP_MASK                       (0xF0000U)
#define ADC_CMDH_LOOP_SHIFT                      (16U)
/*! LOOP - Loop Count Select
 *  0b0000..Looping not enabled. Command executes 1 time.
 *  0b0001..Loop 1 time. Command executes 2 times.
 *  0b0010..Loop 2 times. Command executes 3 times.
 *  0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times.
 *  0b1111..Loop 15 times. Command executes 16 times.
 */
#define ADC_CMDH_LOOP(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK)

#define ADC_CMDH_NEXT_MASK                       (0xF000000U)
#define ADC_CMDH_NEXT_SHIFT                      (24U)
/*! NEXT - Next Command Select
 *  0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority
 *          trigger pending, begin command associated with lower priority trigger.
 *  0b0001..Select CMD1 command buffer register as next command.
 *  0b0010-0b1110..Select corresponding CMD command buffer register as next command
 *  0b1111..Select CMD15 command buffer register as next command.
 */
#define ADC_CMDH_NEXT(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK)
/*! @} */

/* The count of ADC_CMDH */
#define ADC_CMDH_COUNT                           (15U)

/*! @name CV - Compare Value Register */
/*! @{ */

#define ADC_CV_CVL_MASK                          (0xFFFFU)
#define ADC_CV_CVL_SHIFT                         (0U)
/*! CVL - Compare Value Low.
 */
#define ADC_CV_CVL(x)                            (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK)

#define ADC_CV_CVH_MASK                          (0xFFFF0000U)
#define ADC_CV_CVH_SHIFT                         (16U)
/*! CVH - Compare Value High.
 */
#define ADC_CV_CVH(x)                            (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK)
/*! @} */

/* The count of ADC_CV */
#define ADC_CV_COUNT                             (15U)

/*! @name RESFIFO - ADC Data Result FIFO Register */
/*! @{ */

#define ADC_RESFIFO_D_MASK                       (0xFFFFU)
#define ADC_RESFIFO_D_SHIFT                      (0U)
/*! D - Data result
 */
#define ADC_RESFIFO_D(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK)

#define ADC_RESFIFO_TSRC_MASK                    (0x30000U)
#define ADC_RESFIFO_TSRC_SHIFT                   (16U)
/*! TSRC - Trigger Source
 *  0b00..Trigger source 0 initiated this conversion.
 *  0b01..Trigger source 1 initiated this conversion.
 *  0b10-0b10..Corresponding trigger source initiated this conversion.
 *  0b11..Trigger source 3 initiated this conversion.
 */
#define ADC_RESFIFO_TSRC(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK)

#define ADC_RESFIFO_LOOPCNT_MASK                 (0xF00000U)
#define ADC_RESFIFO_LOOPCNT_SHIFT                (20U)
/*! LOOPCNT - Loop count value
 *  0b0000..Result is from initial conversion in command.
 *  0b0001..Result is from second conversion in command.
 *  0b0010-0b1110..Result is from LOOPCNT+1 conversion in command.
 *  0b1111..Result is from 16th conversion in command.
 */
#define ADC_RESFIFO_LOOPCNT(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK)

#define ADC_RESFIFO_CMDSRC_MASK                  (0xF000000U)
#define ADC_RESFIFO_CMDSRC_SHIFT                 (24U)
/*! CMDSRC - Command Buffer Source
 *  0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state
 *          prior to an ADC conversion result dataword being stored to a RESFIFO buffer.
 *  0b0001..CMD1 buffer used as control settings for this conversion.
 *  0b0010-0b1110..Corresponding command buffer used as control settings for this conversion.
 *  0b1111..CMD15 buffer used as control settings for this conversion.
 */
#define ADC_RESFIFO_CMDSRC(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK)

#define ADC_RESFIFO_VALID_MASK                   (0x80000000U)
#define ADC_RESFIFO_VALID_SHIFT                  (31U)
/*! VALID - FIFO entry is valid
 *  0b0..FIFO is empty. Discard any read from RESFIFO.
 *  0b1..FIFO record read from RESFIFO is valid.
 */
#define ADC_RESFIFO_VALID(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK)
/*! @} */

/* The count of ADC_RESFIFO */
#define ADC_RESFIFO_COUNT                        (2U)

/*! @name CAL_GAR0 - Calibration General A-Side Registers */
/*! @{ */

#define ADC_CAL_GAR0_CAL_GAR_VAL_MASK            (0x7FFU)
#define ADC_CAL_GAR0_CAL_GAR_VAL_SHIFT           (0U)
/*! CAL_GAR_VAL - Calibration General A Side Register Element
 */
#define ADC_CAL_GAR0_CAL_GAR_VAL(x)              (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR0_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR0_CAL_GAR_VAL_MASK)
/*! @} */

/*! @name CAL_GAR1 - Calibration General A-Side Registers */
/*! @{ */

#define ADC_CAL_GAR1_CAL_GAR_VAL_MASK            (0xFFFU)
#define ADC_CAL_GAR1_CAL_GAR_VAL_SHIFT           (0U)
/*! CAL_GAR_VAL - Calibration General A Side Register Element
 */
#define ADC_CAL_GAR1_CAL_GAR_VAL(x)              (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR1_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR1_CAL_GAR_VAL_MASK)
/*! @} */

/*! @name CAL_GAR2 - Calibration General A-Side Registers */
/*! @{ */

#define ADC_CAL_GAR2_CAL_GAR_VAL_MASK            (0x1FFFU)
#define ADC_CAL_GAR2_CAL_GAR_VAL_SHIFT           (0U)
/*! CAL_GAR_VAL - Calibration General A Side Register Element
 */
#define ADC_CAL_GAR2_CAL_GAR_VAL(x)              (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR2_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR2_CAL_GAR_VAL_MASK)
/*! @} */

/*! @name CAL_GAR3 - Calibration General A-Side Registers */
/*! @{ */

#define ADC_CAL_GAR3_CAL_GAR_VAL_MASK            (0x1FFFU)
#define ADC_CAL_GAR3_CAL_GAR_VAL_SHIFT           (0U)
/*! CAL_GAR_VAL - Calibration General A Side Register Element
 */
#define ADC_CAL_GAR3_CAL_GAR_VAL(x)              (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR3_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR3_CAL_GAR_VAL_MASK)
/*! @} */

/*! @name CAL_GAR4 - Calibration General A-Side Registers */
/*! @{ */

#define ADC_CAL_GAR4_CAL_GAR_VAL_MASK            (0x3FFFU)
#define ADC_CAL_GAR4_CAL_GAR_VAL_SHIFT           (0U)
/*! CAL_GAR_VAL - Calibration General A Side Register Element
 */
#define ADC_CAL_GAR4_CAL_GAR_VAL(x)              (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR4_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR4_CAL_GAR_VAL_MASK)
/*! @} */

/*! @name CAL_GAR5 - Calibration General A-Side Registers */
/*! @{ */

#define ADC_CAL_GAR5_CAL_GAR_VAL_MASK            (0x3FFFU)
#define ADC_CAL_GAR5_CAL_GAR_VAL_SHIFT           (0U)
/*! CAL_GAR_VAL - Calibration General A Side Register Element
 */
#define ADC_CAL_GAR5_CAL_GAR_VAL(x)              (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR5_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR5_CAL_GAR_VAL_MASK)
/*! @} */

/*! @name CAL_GAR6 - Calibration General A-Side Registers */
/*! @{ */

#define ADC_CAL_GAR6_CAL_GAR_VAL_MASK            (0x3FFFU)
#define ADC_CAL_GAR6_CAL_GAR_VAL_SHIFT           (0U)
/*! CAL_GAR_VAL - Calibration General A Side Register Element
 */
#define ADC_CAL_GAR6_CAL_GAR_VAL(x)              (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR6_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR6_CAL_GAR_VAL_MASK)
/*! @} */

/*! @name CAL_GAR7 - Calibration General A-Side Registers */
/*! @{ */

#define ADC_CAL_GAR7_CAL_GAR_VAL_MASK            (0x3FFFU)
#define ADC_CAL_GAR7_CAL_GAR_VAL_SHIFT           (0U)
/*! CAL_GAR_VAL - Calibration General A Side Register Element
 */
#define ADC_CAL_GAR7_CAL_GAR_VAL(x)              (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR7_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR7_CAL_GAR_VAL_MASK)
/*! @} */

/*! @name CAL_GAR8 - Calibration General A-Side Registers */
/*! @{ */

#define ADC_CAL_GAR8_CAL_GAR_VAL_MASK            (0x7FFFU)
#define ADC_CAL_GAR8_CAL_GAR_VAL_SHIFT           (0U)
/*! CAL_GAR_VAL - Calibration General A Side Register Element
 */
#define ADC_CAL_GAR8_CAL_GAR_VAL(x)              (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR8_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR8_CAL_GAR_VAL_MASK)
/*! @} */

/*! @name CAL_GAR9 - Calibration General A-Side Registers */
/*! @{ */

#define ADC_CAL_GAR9_CAL_GAR_VAL_MASK            (0x7FFFU)
#define ADC_CAL_GAR9_CAL_GAR_VAL_SHIFT           (0U)
/*! CAL_GAR_VAL - Calibration General A Side Register Element
 */
#define ADC_CAL_GAR9_CAL_GAR_VAL(x)              (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR9_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR9_CAL_GAR_VAL_MASK)
/*! @} */

/*! @name CAL_GAR10 - Calibration General A-Side Registers */
/*! @{ */

#define ADC_CAL_GAR10_CAL_GAR_VAL_MASK           (0x7FFFU)
#define ADC_CAL_GAR10_CAL_GAR_VAL_SHIFT          (0U)
/*! CAL_GAR_VAL - Calibration General A Side Register Element
 */
#define ADC_CAL_GAR10_CAL_GAR_VAL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR10_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR10_CAL_GAR_VAL_MASK)
/*! @} */

/*! @name CAL_GAR11 - Calibration General A-Side Registers */
/*! @{ */

#define ADC_CAL_GAR11_CAL_GAR_VAL_MASK           (0x7FFFU)
#define ADC_CAL_GAR11_CAL_GAR_VAL_SHIFT          (0U)
/*! CAL_GAR_VAL - Calibration General A Side Register Element
 */
#define ADC_CAL_GAR11_CAL_GAR_VAL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR11_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR11_CAL_GAR_VAL_MASK)
/*! @} */

/*! @name CAL_GAR12 - Calibration General A-Side Registers */
/*! @{ */

#define ADC_CAL_GAR12_CAL_GAR_VAL_MASK           (0x7FFFU)
#define ADC_CAL_GAR12_CAL_GAR_VAL_SHIFT          (0U)
/*! CAL_GAR_VAL - Calibration General A Side Register Element
 */
#define ADC_CAL_GAR12_CAL_GAR_VAL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR12_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR12_CAL_GAR_VAL_MASK)
/*! @} */

/*! @name CAL_GAR13 - Calibration General A-Side Registers */
/*! @{ */

#define ADC_CAL_GAR13_CAL_GAR_VAL_MASK           (0x7FFFU)
#define ADC_CAL_GAR13_CAL_GAR_VAL_SHIFT          (0U)
/*! CAL_GAR_VAL - Calibration General A Side Register Element
 */
#define ADC_CAL_GAR13_CAL_GAR_VAL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR13_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR13_CAL_GAR_VAL_MASK)
/*! @} */

/*! @name CAL_GAR14 - Calibration General A-Side Registers */
/*! @{ */

#define ADC_CAL_GAR14_CAL_GAR_VAL_MASK           (0x7FFFU)
#define ADC_CAL_GAR14_CAL_GAR_VAL_SHIFT          (0U)
/*! CAL_GAR_VAL - Calibration General A Side Register Element
 */
#define ADC_CAL_GAR14_CAL_GAR_VAL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR14_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR14_CAL_GAR_VAL_MASK)
/*! @} */

/*! @name CAL_GAR15 - Calibration General A-Side Registers */
/*! @{ */

#define ADC_CAL_GAR15_CAL_GAR_VAL_MASK           (0x7FFFU)
#define ADC_CAL_GAR15_CAL_GAR_VAL_SHIFT          (0U)
/*! CAL_GAR_VAL - Calibration General A Side Register Element
 */
#define ADC_CAL_GAR15_CAL_GAR_VAL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR15_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR15_CAL_GAR_VAL_MASK)
/*! @} */

/*! @name CAL_GAR16 - Calibration General A-Side Registers */
/*! @{ */

#define ADC_CAL_GAR16_CAL_GAR_VAL_MASK           (0xFFFFU)
#define ADC_CAL_GAR16_CAL_GAR_VAL_SHIFT          (0U)
/*! CAL_GAR_VAL - Calibration General A Side Register Element
 */
#define ADC_CAL_GAR16_CAL_GAR_VAL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR16_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR16_CAL_GAR_VAL_MASK)
/*! @} */

/*! @name CAL_GAR17 - Calibration General A-Side Registers */
/*! @{ */

#define ADC_CAL_GAR17_CAL_GAR_VAL_MASK           (0xFFFFU)
#define ADC_CAL_GAR17_CAL_GAR_VAL_SHIFT          (0U)
/*! CAL_GAR_VAL - Calibration General A Side Register Element
 */
#define ADC_CAL_GAR17_CAL_GAR_VAL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR17_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR17_CAL_GAR_VAL_MASK)
/*! @} */

/*! @name CAL_GAR18 - Calibration General A-Side Registers */
/*! @{ */

#define ADC_CAL_GAR18_CAL_GAR_VAL_MASK           (0xFFFFU)
#define ADC_CAL_GAR18_CAL_GAR_VAL_SHIFT          (0U)
/*! CAL_GAR_VAL - Calibration General A Side Register Element
 */
#define ADC_CAL_GAR18_CAL_GAR_VAL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR18_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR18_CAL_GAR_VAL_MASK)
/*! @} */

/*! @name CAL_GAR19 - Calibration General A-Side Registers */
/*! @{ */

#define ADC_CAL_GAR19_CAL_GAR_VAL_MASK           (0xFFFFU)
#define ADC_CAL_GAR19_CAL_GAR_VAL_SHIFT          (0U)
/*! CAL_GAR_VAL - Calibration General A Side Register Element
 */
#define ADC_CAL_GAR19_CAL_GAR_VAL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR19_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR19_CAL_GAR_VAL_MASK)
/*! @} */

/*! @name CAL_GAR20 - Calibration General A-Side Registers */
/*! @{ */

#define ADC_CAL_GAR20_CAL_GAR_VAL_MASK           (0xFFFFU)
#define ADC_CAL_GAR20_CAL_GAR_VAL_SHIFT          (0U)
/*! CAL_GAR_VAL - Calibration General A Side Register Element
 */
#define ADC_CAL_GAR20_CAL_GAR_VAL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR20_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR20_CAL_GAR_VAL_MASK)
/*! @} */

/*! @name CAL_GAR21 - Calibration General A-Side Registers */
/*! @{ */

#define ADC_CAL_GAR21_CAL_GAR_VAL_MASK           (0xFFFFU)
#define ADC_CAL_GAR21_CAL_GAR_VAL_SHIFT          (0U)
/*! CAL_GAR_VAL - Calibration General A Side Register Element
 */
#define ADC_CAL_GAR21_CAL_GAR_VAL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR21_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR21_CAL_GAR_VAL_MASK)
/*! @} */

/*! @name CAL_GAR22 - Calibration General A-Side Registers */
/*! @{ */

#define ADC_CAL_GAR22_CAL_GAR_VAL_MASK           (0xFFFFU)
#define ADC_CAL_GAR22_CAL_GAR_VAL_SHIFT          (0U)
/*! CAL_GAR_VAL - Calibration General A Side Register Element
 */
#define ADC_CAL_GAR22_CAL_GAR_VAL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR22_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR22_CAL_GAR_VAL_MASK)
/*! @} */

/*! @name CAL_GAR23 - Calibration General A-Side Registers */
/*! @{ */

#define ADC_CAL_GAR23_CAL_GAR_VAL_MASK           (0xFFFFU)
#define ADC_CAL_GAR23_CAL_GAR_VAL_SHIFT          (0U)
/*! CAL_GAR_VAL - Calibration General A Side Register Element
 */
#define ADC_CAL_GAR23_CAL_GAR_VAL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR23_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR23_CAL_GAR_VAL_MASK)
/*! @} */

/*! @name CAL_GAR24 - Calibration General A-Side Registers */
/*! @{ */

#define ADC_CAL_GAR24_CAL_GAR_VAL_MASK           (0xFFFFU)
#define ADC_CAL_GAR24_CAL_GAR_VAL_SHIFT          (0U)
/*! CAL_GAR_VAL - Calibration General A Side Register Element
 */
#define ADC_CAL_GAR24_CAL_GAR_VAL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR24_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR24_CAL_GAR_VAL_MASK)
/*! @} */

/*! @name CAL_GAR25 - Calibration General A-Side Registers */
/*! @{ */

#define ADC_CAL_GAR25_CAL_GAR_VAL_MASK           (0xFFFFU)
#define ADC_CAL_GAR25_CAL_GAR_VAL_SHIFT          (0U)
/*! CAL_GAR_VAL - Calibration General A Side Register Element
 */
#define ADC_CAL_GAR25_CAL_GAR_VAL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR25_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR25_CAL_GAR_VAL_MASK)
/*! @} */

/*! @name CAL_GAR26 - Calibration General A-Side Registers */
/*! @{ */

#define ADC_CAL_GAR26_CAL_GAR_VAL_MASK           (0xFFFFU)
#define ADC_CAL_GAR26_CAL_GAR_VAL_SHIFT          (0U)
/*! CAL_GAR_VAL - Calibration General A Side Register Element
 */
#define ADC_CAL_GAR26_CAL_GAR_VAL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR26_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR26_CAL_GAR_VAL_MASK)
/*! @} */

/*! @name CAL_GAR27 - Calibration General A-Side Registers */
/*! @{ */

#define ADC_CAL_GAR27_CAL_GAR_VAL_MASK           (0xFFFFU)
#define ADC_CAL_GAR27_CAL_GAR_VAL_SHIFT          (0U)
/*! CAL_GAR_VAL - Calibration General A Side Register Element
 */
#define ADC_CAL_GAR27_CAL_GAR_VAL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR27_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR27_CAL_GAR_VAL_MASK)
/*! @} */

/*! @name CAL_GAR28 - Calibration General A-Side Registers */
/*! @{ */

#define ADC_CAL_GAR28_CAL_GAR_VAL_MASK           (0xFFFFU)
#define ADC_CAL_GAR28_CAL_GAR_VAL_SHIFT          (0U)
/*! CAL_GAR_VAL - Calibration General A Side Register Element
 */
#define ADC_CAL_GAR28_CAL_GAR_VAL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR28_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR28_CAL_GAR_VAL_MASK)
/*! @} */

/*! @name CAL_GAR29 - Calibration General A-Side Registers */
/*! @{ */

#define ADC_CAL_GAR29_CAL_GAR_VAL_MASK           (0xFFFFU)
#define ADC_CAL_GAR29_CAL_GAR_VAL_SHIFT          (0U)
/*! CAL_GAR_VAL - Calibration General A Side Register Element
 */
#define ADC_CAL_GAR29_CAL_GAR_VAL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR29_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR29_CAL_GAR_VAL_MASK)
/*! @} */

/*! @name CAL_GAR30 - Calibration General A-Side Registers */
/*! @{ */

#define ADC_CAL_GAR30_CAL_GAR_VAL_MASK           (0xFFFFU)
#define ADC_CAL_GAR30_CAL_GAR_VAL_SHIFT          (0U)
/*! CAL_GAR_VAL - Calibration General A Side Register Element
 */
#define ADC_CAL_GAR30_CAL_GAR_VAL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR30_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR30_CAL_GAR_VAL_MASK)
/*! @} */

/*! @name CAL_GAR31 - Calibration General A-Side Registers */
/*! @{ */

#define ADC_CAL_GAR31_CAL_GAR_VAL_MASK           (0xFFFFU)
#define ADC_CAL_GAR31_CAL_GAR_VAL_SHIFT          (0U)
/*! CAL_GAR_VAL - Calibration General A Side Register Element
 */
#define ADC_CAL_GAR31_CAL_GAR_VAL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR31_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR31_CAL_GAR_VAL_MASK)
/*! @} */

/*! @name CAL_GAR32 - Calibration General A-Side Registers */
/*! @{ */

#define ADC_CAL_GAR32_CAL_GAR_VAL_MASK           (0x7FFU)
#define ADC_CAL_GAR32_CAL_GAR_VAL_SHIFT          (0U)
/*! CAL_GAR_VAL - Calibration General A Side Register Element
 */
#define ADC_CAL_GAR32_CAL_GAR_VAL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR32_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR32_CAL_GAR_VAL_MASK)
/*! @} */

/*! @name CAL_GBR0 - Calibration General B-Side Registers */
/*! @{ */

#define ADC_CAL_GBR0_CAL_GBR_VAL_MASK            (0x7FFU)
#define ADC_CAL_GBR0_CAL_GBR_VAL_SHIFT           (0U)
/*! CAL_GBR_VAL - Calibration General B Side Register Element
 */
#define ADC_CAL_GBR0_CAL_GBR_VAL(x)              (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR0_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR0_CAL_GBR_VAL_MASK)
/*! @} */

/*! @name CAL_GBR1 - Calibration General B-Side Registers */
/*! @{ */

#define ADC_CAL_GBR1_CAL_GBR_VAL_MASK            (0xFFFU)
#define ADC_CAL_GBR1_CAL_GBR_VAL_SHIFT           (0U)
/*! CAL_GBR_VAL - Calibration General B Side Register Element
 */
#define ADC_CAL_GBR1_CAL_GBR_VAL(x)              (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR1_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR1_CAL_GBR_VAL_MASK)
/*! @} */

/*! @name CAL_GBR2 - Calibration General B-Side Registers */
/*! @{ */

#define ADC_CAL_GBR2_CAL_GBR_VAL_MASK            (0x1FFFU)
#define ADC_CAL_GBR2_CAL_GBR_VAL_SHIFT           (0U)
/*! CAL_GBR_VAL - Calibration General B Side Register Element
 */
#define ADC_CAL_GBR2_CAL_GBR_VAL(x)              (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR2_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR2_CAL_GBR_VAL_MASK)
/*! @} */

/*! @name CAL_GBR3 - Calibration General B-Side Registers */
/*! @{ */

#define ADC_CAL_GBR3_CAL_GBR_VAL_MASK            (0x1FFFU)
#define ADC_CAL_GBR3_CAL_GBR_VAL_SHIFT           (0U)
/*! CAL_GBR_VAL - Calibration General B Side Register Element
 */
#define ADC_CAL_GBR3_CAL_GBR_VAL(x)              (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR3_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR3_CAL_GBR_VAL_MASK)
/*! @} */

/*! @name CAL_GBR4 - Calibration General B-Side Registers */
/*! @{ */

#define ADC_CAL_GBR4_CAL_GBR_VAL_MASK            (0x3FFFU)
#define ADC_CAL_GBR4_CAL_GBR_VAL_SHIFT           (0U)
/*! CAL_GBR_VAL - Calibration General B Side Register Element
 */
#define ADC_CAL_GBR4_CAL_GBR_VAL(x)              (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR4_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR4_CAL_GBR_VAL_MASK)
/*! @} */

/*! @name CAL_GBR5 - Calibration General B-Side Registers */
/*! @{ */

#define ADC_CAL_GBR5_CAL_GBR_VAL_MASK            (0x3FFFU)
#define ADC_CAL_GBR5_CAL_GBR_VAL_SHIFT           (0U)
/*! CAL_GBR_VAL - Calibration General B Side Register Element
 */
#define ADC_CAL_GBR5_CAL_GBR_VAL(x)              (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR5_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR5_CAL_GBR_VAL_MASK)
/*! @} */

/*! @name CAL_GBR6 - Calibration General B-Side Registers */
/*! @{ */

#define ADC_CAL_GBR6_CAL_GBR_VAL_MASK            (0x3FFFU)
#define ADC_CAL_GBR6_CAL_GBR_VAL_SHIFT           (0U)
/*! CAL_GBR_VAL - Calibration General B Side Register Element
 */
#define ADC_CAL_GBR6_CAL_GBR_VAL(x)              (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR6_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR6_CAL_GBR_VAL_MASK)
/*! @} */

/*! @name CAL_GBR7 - Calibration General B-Side Registers */
/*! @{ */

#define ADC_CAL_GBR7_CAL_GBR_VAL_MASK            (0x3FFFU)
#define ADC_CAL_GBR7_CAL_GBR_VAL_SHIFT           (0U)
/*! CAL_GBR_VAL - Calibration General B Side Register Element
 */
#define ADC_CAL_GBR7_CAL_GBR_VAL(x)              (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR7_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR7_CAL_GBR_VAL_MASK)
/*! @} */

/*! @name CAL_GBR8 - Calibration General B-Side Registers */
/*! @{ */

#define ADC_CAL_GBR8_CAL_GBR_VAL_MASK            (0x7FFFU)
#define ADC_CAL_GBR8_CAL_GBR_VAL_SHIFT           (0U)
/*! CAL_GBR_VAL - Calibration General B Side Register Element
 */
#define ADC_CAL_GBR8_CAL_GBR_VAL(x)              (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR8_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR8_CAL_GBR_VAL_MASK)
/*! @} */

/*! @name CAL_GBR9 - Calibration General B-Side Registers */
/*! @{ */

#define ADC_CAL_GBR9_CAL_GBR_VAL_MASK            (0x7FFFU)
#define ADC_CAL_GBR9_CAL_GBR_VAL_SHIFT           (0U)
/*! CAL_GBR_VAL - Calibration General B Side Register Element
 */
#define ADC_CAL_GBR9_CAL_GBR_VAL(x)              (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR9_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR9_CAL_GBR_VAL_MASK)
/*! @} */

/*! @name CAL_GBR10 - Calibration General B-Side Registers */
/*! @{ */

#define ADC_CAL_GBR10_CAL_GBR_VAL_MASK           (0x7FFFU)
#define ADC_CAL_GBR10_CAL_GBR_VAL_SHIFT          (0U)
/*! CAL_GBR_VAL - Calibration General B Side Register Element
 */
#define ADC_CAL_GBR10_CAL_GBR_VAL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR10_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR10_CAL_GBR_VAL_MASK)
/*! @} */

/*! @name CAL_GBR11 - Calibration General B-Side Registers */
/*! @{ */

#define ADC_CAL_GBR11_CAL_GBR_VAL_MASK           (0x7FFFU)
#define ADC_CAL_GBR11_CAL_GBR_VAL_SHIFT          (0U)
/*! CAL_GBR_VAL - Calibration General B Side Register Element
 */
#define ADC_CAL_GBR11_CAL_GBR_VAL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR11_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR11_CAL_GBR_VAL_MASK)
/*! @} */

/*! @name CAL_GBR12 - Calibration General B-Side Registers */
/*! @{ */

#define ADC_CAL_GBR12_CAL_GBR_VAL_MASK           (0x7FFFU)
#define ADC_CAL_GBR12_CAL_GBR_VAL_SHIFT          (0U)
/*! CAL_GBR_VAL - Calibration General B Side Register Element
 */
#define ADC_CAL_GBR12_CAL_GBR_VAL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR12_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR12_CAL_GBR_VAL_MASK)
/*! @} */

/*! @name CAL_GBR13 - Calibration General B-Side Registers */
/*! @{ */

#define ADC_CAL_GBR13_CAL_GBR_VAL_MASK           (0x7FFFU)
#define ADC_CAL_GBR13_CAL_GBR_VAL_SHIFT          (0U)
/*! CAL_GBR_VAL - Calibration General B Side Register Element
 */
#define ADC_CAL_GBR13_CAL_GBR_VAL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR13_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR13_CAL_GBR_VAL_MASK)
/*! @} */

/*! @name CAL_GBR14 - Calibration General B-Side Registers */
/*! @{ */

#define ADC_CAL_GBR14_CAL_GBR_VAL_MASK           (0x7FFFU)
#define ADC_CAL_GBR14_CAL_GBR_VAL_SHIFT          (0U)
/*! CAL_GBR_VAL - Calibration General B Side Register Element
 */
#define ADC_CAL_GBR14_CAL_GBR_VAL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR14_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR14_CAL_GBR_VAL_MASK)
/*! @} */

/*! @name CAL_GBR15 - Calibration General B-Side Registers */
/*! @{ */

#define ADC_CAL_GBR15_CAL_GBR_VAL_MASK           (0x7FFFU)
#define ADC_CAL_GBR15_CAL_GBR_VAL_SHIFT          (0U)
/*! CAL_GBR_VAL - Calibration General B Side Register Element
 */
#define ADC_CAL_GBR15_CAL_GBR_VAL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR15_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR15_CAL_GBR_VAL_MASK)
/*! @} */

/*! @name CAL_GBR16 - Calibration General B-Side Registers */
/*! @{ */

#define ADC_CAL_GBR16_CAL_GBR_VAL_MASK           (0xFFFFU)
#define ADC_CAL_GBR16_CAL_GBR_VAL_SHIFT          (0U)
/*! CAL_GBR_VAL - Calibration General B Side Register Element
 */
#define ADC_CAL_GBR16_CAL_GBR_VAL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR16_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR16_CAL_GBR_VAL_MASK)
/*! @} */

/*! @name CAL_GBR17 - Calibration General B-Side Registers */
/*! @{ */

#define ADC_CAL_GBR17_CAL_GBR_VAL_MASK           (0xFFFFU)
#define ADC_CAL_GBR17_CAL_GBR_VAL_SHIFT          (0U)
/*! CAL_GBR_VAL - Calibration General B Side Register Element
 */
#define ADC_CAL_GBR17_CAL_GBR_VAL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR17_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR17_CAL_GBR_VAL_MASK)
/*! @} */

/*! @name CAL_GBR18 - Calibration General B-Side Registers */
/*! @{ */

#define ADC_CAL_GBR18_CAL_GBR_VAL_MASK           (0xFFFFU)
#define ADC_CAL_GBR18_CAL_GBR_VAL_SHIFT          (0U)
/*! CAL_GBR_VAL - Calibration General B Side Register Element
 */
#define ADC_CAL_GBR18_CAL_GBR_VAL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR18_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR18_CAL_GBR_VAL_MASK)
/*! @} */

/*! @name CAL_GBR19 - Calibration General B-Side Registers */
/*! @{ */

#define ADC_CAL_GBR19_CAL_GBR_VAL_MASK           (0xFFFFU)
#define ADC_CAL_GBR19_CAL_GBR_VAL_SHIFT          (0U)
/*! CAL_GBR_VAL - Calibration General B Side Register Element
 */
#define ADC_CAL_GBR19_CAL_GBR_VAL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR19_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR19_CAL_GBR_VAL_MASK)
/*! @} */

/*! @name CAL_GBR20 - Calibration General B-Side Registers */
/*! @{ */

#define ADC_CAL_GBR20_CAL_GBR_VAL_MASK           (0xFFFFU)
#define ADC_CAL_GBR20_CAL_GBR_VAL_SHIFT          (0U)
/*! CAL_GBR_VAL - Calibration General B Side Register Element
 */
#define ADC_CAL_GBR20_CAL_GBR_VAL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR20_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR20_CAL_GBR_VAL_MASK)
/*! @} */

/*! @name CAL_GBR21 - Calibration General B-Side Registers */
/*! @{ */

#define ADC_CAL_GBR21_CAL_GBR_VAL_MASK           (0xFFFFU)
#define ADC_CAL_GBR21_CAL_GBR_VAL_SHIFT          (0U)
/*! CAL_GBR_VAL - Calibration General B Side Register Element
 */
#define ADC_CAL_GBR21_CAL_GBR_VAL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR21_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR21_CAL_GBR_VAL_MASK)
/*! @} */

/*! @name CAL_GBR22 - Calibration General B-Side Registers */
/*! @{ */

#define ADC_CAL_GBR22_CAL_GBR_VAL_MASK           (0xFFFFU)
#define ADC_CAL_GBR22_CAL_GBR_VAL_SHIFT          (0U)
/*! CAL_GBR_VAL - Calibration General B Side Register Element
 */
#define ADC_CAL_GBR22_CAL_GBR_VAL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR22_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR22_CAL_GBR_VAL_MASK)
/*! @} */

/*! @name CAL_GBR23 - Calibration General B-Side Registers */
/*! @{ */

#define ADC_CAL_GBR23_CAL_GBR_VAL_MASK           (0xFFFFU)
#define ADC_CAL_GBR23_CAL_GBR_VAL_SHIFT          (0U)
/*! CAL_GBR_VAL - Calibration General B Side Register Element
 */
#define ADC_CAL_GBR23_CAL_GBR_VAL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR23_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR23_CAL_GBR_VAL_MASK)
/*! @} */

/*! @name CAL_GBR24 - Calibration General B-Side Registers */
/*! @{ */

#define ADC_CAL_GBR24_CAL_GBR_VAL_MASK           (0xFFFFU)
#define ADC_CAL_GBR24_CAL_GBR_VAL_SHIFT          (0U)
/*! CAL_GBR_VAL - Calibration General B Side Register Element
 */
#define ADC_CAL_GBR24_CAL_GBR_VAL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR24_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR24_CAL_GBR_VAL_MASK)
/*! @} */

/*! @name CAL_GBR25 - Calibration General B-Side Registers */
/*! @{ */

#define ADC_CAL_GBR25_CAL_GBR_VAL_MASK           (0xFFFFU)
#define ADC_CAL_GBR25_CAL_GBR_VAL_SHIFT          (0U)
/*! CAL_GBR_VAL - Calibration General B Side Register Element
 */
#define ADC_CAL_GBR25_CAL_GBR_VAL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR25_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR25_CAL_GBR_VAL_MASK)
/*! @} */

/*! @name CAL_GBR26 - Calibration General B-Side Registers */
/*! @{ */

#define ADC_CAL_GBR26_CAL_GBR_VAL_MASK           (0xFFFFU)
#define ADC_CAL_GBR26_CAL_GBR_VAL_SHIFT          (0U)
/*! CAL_GBR_VAL - Calibration General B Side Register Element
 */
#define ADC_CAL_GBR26_CAL_GBR_VAL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR26_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR26_CAL_GBR_VAL_MASK)
/*! @} */

/*! @name CAL_GBR27 - Calibration General B-Side Registers */
/*! @{ */

#define ADC_CAL_GBR27_CAL_GBR_VAL_MASK           (0xFFFFU)
#define ADC_CAL_GBR27_CAL_GBR_VAL_SHIFT          (0U)
/*! CAL_GBR_VAL - Calibration General B Side Register Element
 */
#define ADC_CAL_GBR27_CAL_GBR_VAL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR27_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR27_CAL_GBR_VAL_MASK)
/*! @} */

/*! @name CAL_GBR28 - Calibration General B-Side Registers */
/*! @{ */

#define ADC_CAL_GBR28_CAL_GBR_VAL_MASK           (0xFFFFU)
#define ADC_CAL_GBR28_CAL_GBR_VAL_SHIFT          (0U)
/*! CAL_GBR_VAL - Calibration General B Side Register Element
 */
#define ADC_CAL_GBR28_CAL_GBR_VAL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR28_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR28_CAL_GBR_VAL_MASK)
/*! @} */

/*! @name CAL_GBR29 - Calibration General B-Side Registers */
/*! @{ */

#define ADC_CAL_GBR29_CAL_GBR_VAL_MASK           (0xFFFFU)
#define ADC_CAL_GBR29_CAL_GBR_VAL_SHIFT          (0U)
/*! CAL_GBR_VAL - Calibration General B Side Register Element
 */
#define ADC_CAL_GBR29_CAL_GBR_VAL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR29_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR29_CAL_GBR_VAL_MASK)
/*! @} */

/*! @name CAL_GBR30 - Calibration General B-Side Registers */
/*! @{ */

#define ADC_CAL_GBR30_CAL_GBR_VAL_MASK           (0xFFFFU)
#define ADC_CAL_GBR30_CAL_GBR_VAL_SHIFT          (0U)
/*! CAL_GBR_VAL - Calibration General B Side Register Element
 */
#define ADC_CAL_GBR30_CAL_GBR_VAL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR30_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR30_CAL_GBR_VAL_MASK)
/*! @} */

/*! @name CAL_GBR31 - Calibration General B-Side Registers */
/*! @{ */

#define ADC_CAL_GBR31_CAL_GBR_VAL_MASK           (0xFFFFU)
#define ADC_CAL_GBR31_CAL_GBR_VAL_SHIFT          (0U)
/*! CAL_GBR_VAL - Calibration General B Side Register Element
 */
#define ADC_CAL_GBR31_CAL_GBR_VAL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR31_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR31_CAL_GBR_VAL_MASK)
/*! @} */

/*! @name CAL_GBR32 - Calibration General B-Side Registers */
/*! @{ */

#define ADC_CAL_GBR32_CAL_GBR_VAL_MASK           (0x7FFU)
#define ADC_CAL_GBR32_CAL_GBR_VAL_SHIFT          (0U)
/*! CAL_GBR_VAL - Calibration General B Side Register Element
 */
#define ADC_CAL_GBR32_CAL_GBR_VAL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR32_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR32_CAL_GBR_VAL_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group ADC_Register_Masks */


/* ADC - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral ADC0 base address */
  #define ADC0_BASE                                (0x50047000u)
  /** Peripheral ADC0 base address */
  #define ADC0_BASE_NS                             (0x40047000u)
  /** Peripheral ADC0 base pointer */
  #define ADC0                                     ((ADC_Type *)ADC0_BASE)
  /** Peripheral ADC0 base pointer */
  #define ADC0_NS                                  ((ADC_Type *)ADC0_BASE_NS)
  /** Array initializer of ADC peripheral base addresses */
  #define ADC_BASE_ADDRS                           { ADC0_BASE }
  /** Array initializer of ADC peripheral base pointers */
  #define ADC_BASE_PTRS                            { ADC0 }
  /** Array initializer of ADC peripheral base addresses */
  #define ADC_BASE_ADDRS_NS                        { ADC0_BASE_NS }
  /** Array initializer of ADC peripheral base pointers */
  #define ADC_BASE_PTRS_NS                         { ADC0_NS }
#else
  /** Peripheral ADC0 base address */
  #define ADC0_BASE                                (0x40047000u)
  /** Peripheral ADC0 base pointer */
  #define ADC0                                     ((ADC_Type *)ADC0_BASE)
  /** Array initializer of ADC peripheral base addresses */
  #define ADC_BASE_ADDRS                           { ADC0_BASE }
  /** Array initializer of ADC peripheral base pointers */
  #define ADC_BASE_PTRS                            { ADC0 }
#endif
/** Interrupt vectors for the ADC peripheral type */
#define ADC_IRQS                                 { ADC0_IRQn }

/*!
 * @}
 */ /* end of group ADC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- AXBS Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer
 * @{
 */

/** AXBS - Register Layout Typedef */
typedef struct {
  __IO uint32_t PRS0;                              /**< Priority Slave Registers, offset: 0x0 */
       uint8_t RESERVED_0[12];
  __IO uint32_t CRS0;                              /**< Control Register, offset: 0x10 */
       uint8_t RESERVED_1[236];
  __IO uint32_t PRS1;                              /**< Priority Slave Registers, offset: 0x100 */
       uint8_t RESERVED_2[12];
  __IO uint32_t CRS1;                              /**< Control Register, offset: 0x110 */
       uint8_t RESERVED_3[236];
  __IO uint32_t PRS2;                              /**< Priority Slave Registers, offset: 0x200 */
       uint8_t RESERVED_4[12];
  __IO uint32_t CRS2;                              /**< Control Register, offset: 0x210 */
       uint8_t RESERVED_5[236];
  __IO uint32_t PRS3;                              /**< Priority Slave Registers, offset: 0x300 */
       uint8_t RESERVED_6[12];
  __IO uint32_t CRS3;                              /**< Control Register, offset: 0x310 */
       uint8_t RESERVED_7[236];
  __IO uint32_t PRS4;                              /**< Priority Slave Registers, offset: 0x400 */
       uint8_t RESERVED_8[12];
  __IO uint32_t CRS4;                              /**< Control Register, offset: 0x410 */
       uint8_t RESERVED_9[236];
  __IO uint32_t PRS5;                              /**< Priority Slave Registers, offset: 0x500 */
       uint8_t RESERVED_10[12];
  __IO uint32_t CRS5;                              /**< Control Register, offset: 0x510 */
       uint8_t RESERVED_11[236];
  __IO uint32_t PRS6;                              /**< Priority Slave Registers, offset: 0x600 */
       uint8_t RESERVED_12[12];
  __IO uint32_t CRS6;                              /**< Control Register, offset: 0x610 */
       uint8_t RESERVED_13[236];
  __IO uint32_t PRS7;                              /**< Priority Slave Registers, offset: 0x700 */
       uint8_t RESERVED_14[12];
  __IO uint32_t CRS7;                              /**< Control Register, offset: 0x710 */
       uint8_t RESERVED_15[236];
  __IO uint32_t MGPCR0;                            /**< Master General Purpose Control Register, offset: 0x800 */
       uint8_t RESERVED_16[252];
  __IO uint32_t MGPCR1;                            /**< Master General Purpose Control Register, offset: 0x900 */
       uint8_t RESERVED_17[252];
  __IO uint32_t MGPCR2;                            /**< Master General Purpose Control Register, offset: 0xA00 */
       uint8_t RESERVED_18[252];
  __IO uint32_t MGPCR3;                            /**< Master General Purpose Control Register, offset: 0xB00 */
       uint8_t RESERVED_19[252];
  __IO uint32_t MGPCR4;                            /**< Master General Purpose Control Register, offset: 0xC00 */
       uint8_t RESERVED_20[252];
  __IO uint32_t MGPCR5;                            /**< Master General Purpose Control Register, offset: 0xD00 */
} AXBS_Type;

/* ----------------------------------------------------------------------------
   -- AXBS Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AXBS_Register_Masks AXBS Register Masks
 * @{
 */

/*! @name PRS0 - Priority Slave Registers */
/*! @{ */

#define AXBS_PRS0_M0_MASK                        (0x7U)
#define AXBS_PRS0_M0_SHIFT                       (0U)
/*! M0 - Master 0 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS0_M0(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_PRS0_M0_SHIFT)) & AXBS_PRS0_M0_MASK)

#define AXBS_PRS0_M1_MASK                        (0x70U)
#define AXBS_PRS0_M1_SHIFT                       (4U)
/*! M1 - Master 1 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS0_M1(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_PRS0_M1_SHIFT)) & AXBS_PRS0_M1_MASK)

#define AXBS_PRS0_M2_MASK                        (0x700U)
#define AXBS_PRS0_M2_SHIFT                       (8U)
/*! M2 - Master 2 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS0_M2(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_PRS0_M2_SHIFT)) & AXBS_PRS0_M2_MASK)

#define AXBS_PRS0_M3_MASK                        (0x7000U)
#define AXBS_PRS0_M3_SHIFT                       (12U)
/*! M3 - Master 3 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS0_M3(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_PRS0_M3_SHIFT)) & AXBS_PRS0_M3_MASK)

#define AXBS_PRS0_M4_MASK                        (0x70000U)
#define AXBS_PRS0_M4_SHIFT                       (16U)
/*! M4 - Master 4 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS0_M4(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_PRS0_M4_SHIFT)) & AXBS_PRS0_M4_MASK)

#define AXBS_PRS0_M5_MASK                        (0x700000U)
#define AXBS_PRS0_M5_SHIFT                       (20U)
/*! M5 - Master 5 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS0_M5(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_PRS0_M5_SHIFT)) & AXBS_PRS0_M5_MASK)
/*! @} */

/*! @name CRS0 - Control Register */
/*! @{ */

#define AXBS_CRS0_PARK_MASK                      (0x7U)
#define AXBS_CRS0_PARK_SHIFT                     (0U)
/*! PARK - Park
 *  0b111..Park on master port M0.
 *  0b001..Park on master port M1.
 *  0b010..Park on master port M2.
 *  0b011..Park on master port M3.
 *  0b100..Park on master port M4.
 *  0b101..Park on master port M5.
 */
#define AXBS_CRS0_PARK(x)                        (((uint32_t)(((uint32_t)(x)) << AXBS_CRS0_PARK_SHIFT)) & AXBS_CRS0_PARK_MASK)

#define AXBS_CRS0_PCTL_MASK                      (0x30U)
#define AXBS_CRS0_PCTL_SHIFT                     (4U)
/*! PCTL - Parking Control
 *  0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field.
 *  0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port.
 *  0b10..When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state.
 *  0b11..Reserved
 */
#define AXBS_CRS0_PCTL(x)                        (((uint32_t)(((uint32_t)(x)) << AXBS_CRS0_PCTL_SHIFT)) & AXBS_CRS0_PCTL_MASK)

#define AXBS_CRS0_ARB_MASK                       (0x300U)
#define AXBS_CRS0_ARB_SHIFT                      (8U)
/*! ARB - Arbitration Mode
 *  0b00..Fixed priority
 *  0b01..Round-robin(RR) or rotating priority
 *  0b10..Reserved
 *  0b11..Reserved
 */
#define AXBS_CRS0_ARB(x)                         (((uint32_t)(((uint32_t)(x)) << AXBS_CRS0_ARB_SHIFT)) & AXBS_CRS0_ARB_MASK)

#define AXBS_CRS0_HLP_MASK                       (0x40000000U)
#define AXBS_CRS0_HLP_SHIFT                      (30U)
/*! HLP - Halt Low Priority
 *  0b0..The low-power mode request has the highest priority for arbitration on this slave port.
 *  0b1..The low-power mode request has the lowest initial priority for arbitration on this slave port.
 */
#define AXBS_CRS0_HLP(x)                         (((uint32_t)(((uint32_t)(x)) << AXBS_CRS0_HLP_SHIFT)) & AXBS_CRS0_HLP_MASK)

#define AXBS_CRS0_RO_MASK                        (0x80000000U)
#define AXBS_CRS0_RO_SHIFT                       (31U)
/*! RO - Read Only
 *  0b0..The slave port's registers are writeable.
 *  0b1..The slave port's registers are read-only and cannot be written. Attempted writes have no effect on the
 *       registers and result in a bus error response.
 */
#define AXBS_CRS0_RO(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_CRS0_RO_SHIFT)) & AXBS_CRS0_RO_MASK)
/*! @} */

/*! @name PRS1 - Priority Slave Registers */
/*! @{ */

#define AXBS_PRS1_M0_MASK                        (0x7U)
#define AXBS_PRS1_M0_SHIFT                       (0U)
/*! M0 - Master 0 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS1_M0(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_PRS1_M0_SHIFT)) & AXBS_PRS1_M0_MASK)

#define AXBS_PRS1_M1_MASK                        (0x70U)
#define AXBS_PRS1_M1_SHIFT                       (4U)
/*! M1 - Master 1 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS1_M1(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_PRS1_M1_SHIFT)) & AXBS_PRS1_M1_MASK)

#define AXBS_PRS1_M2_MASK                        (0x700U)
#define AXBS_PRS1_M2_SHIFT                       (8U)
/*! M2 - Master 2 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS1_M2(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_PRS1_M2_SHIFT)) & AXBS_PRS1_M2_MASK)

#define AXBS_PRS1_M3_MASK                        (0x7000U)
#define AXBS_PRS1_M3_SHIFT                       (12U)
/*! M3 - Master 3 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS1_M3(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_PRS1_M3_SHIFT)) & AXBS_PRS1_M3_MASK)

#define AXBS_PRS1_M4_MASK                        (0x70000U)
#define AXBS_PRS1_M4_SHIFT                       (16U)
/*! M4 - Master 4 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS1_M4(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_PRS1_M4_SHIFT)) & AXBS_PRS1_M4_MASK)

#define AXBS_PRS1_M5_MASK                        (0x700000U)
#define AXBS_PRS1_M5_SHIFT                       (20U)
/*! M5 - Master 5 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS1_M5(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_PRS1_M5_SHIFT)) & AXBS_PRS1_M5_MASK)
/*! @} */

/*! @name CRS1 - Control Register */
/*! @{ */

#define AXBS_CRS1_PARK_MASK                      (0x7U)
#define AXBS_CRS1_PARK_SHIFT                     (0U)
/*! PARK - Park
 *  0b111..Park on master port M0.
 *  0b001..Park on master port M1.
 *  0b010..Park on master port M2.
 *  0b011..Park on master port M3.
 *  0b100..Park on master port M4.
 *  0b101..Park on master port M5.
 */
#define AXBS_CRS1_PARK(x)                        (((uint32_t)(((uint32_t)(x)) << AXBS_CRS1_PARK_SHIFT)) & AXBS_CRS1_PARK_MASK)

#define AXBS_CRS1_PCTL_MASK                      (0x30U)
#define AXBS_CRS1_PCTL_SHIFT                     (4U)
/*! PCTL - Parking Control
 *  0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field.
 *  0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port.
 *  0b10..When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state.
 *  0b11..Reserved
 */
#define AXBS_CRS1_PCTL(x)                        (((uint32_t)(((uint32_t)(x)) << AXBS_CRS1_PCTL_SHIFT)) & AXBS_CRS1_PCTL_MASK)

#define AXBS_CRS1_ARB_MASK                       (0x300U)
#define AXBS_CRS1_ARB_SHIFT                      (8U)
/*! ARB - Arbitration Mode
 *  0b00..Fixed priority
 *  0b01..Round-robin(RR) or rotating priority
 *  0b10..Reserved
 *  0b11..Reserved
 */
#define AXBS_CRS1_ARB(x)                         (((uint32_t)(((uint32_t)(x)) << AXBS_CRS1_ARB_SHIFT)) & AXBS_CRS1_ARB_MASK)

#define AXBS_CRS1_HLP_MASK                       (0x40000000U)
#define AXBS_CRS1_HLP_SHIFT                      (30U)
/*! HLP - Halt Low Priority
 *  0b0..The low-power mode request has the highest priority for arbitration on this slave port.
 *  0b1..The low-power mode request has the lowest initial priority for arbitration on this slave port.
 */
#define AXBS_CRS1_HLP(x)                         (((uint32_t)(((uint32_t)(x)) << AXBS_CRS1_HLP_SHIFT)) & AXBS_CRS1_HLP_MASK)

#define AXBS_CRS1_RO_MASK                        (0x80000000U)
#define AXBS_CRS1_RO_SHIFT                       (31U)
/*! RO - Read Only
 *  0b0..The slave port's registers are writeable.
 *  0b1..The slave port's registers are read-only and cannot be written. Attempted writes have no effect on the
 *       registers and result in a bus error response.
 */
#define AXBS_CRS1_RO(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_CRS1_RO_SHIFT)) & AXBS_CRS1_RO_MASK)
/*! @} */

/*! @name PRS2 - Priority Slave Registers */
/*! @{ */

#define AXBS_PRS2_M0_MASK                        (0x7U)
#define AXBS_PRS2_M0_SHIFT                       (0U)
/*! M0 - Master 0 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS2_M0(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_PRS2_M0_SHIFT)) & AXBS_PRS2_M0_MASK)

#define AXBS_PRS2_M1_MASK                        (0x70U)
#define AXBS_PRS2_M1_SHIFT                       (4U)
/*! M1 - Master 1 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS2_M1(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_PRS2_M1_SHIFT)) & AXBS_PRS2_M1_MASK)

#define AXBS_PRS2_M2_MASK                        (0x700U)
#define AXBS_PRS2_M2_SHIFT                       (8U)
/*! M2 - Master 2 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS2_M2(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_PRS2_M2_SHIFT)) & AXBS_PRS2_M2_MASK)

#define AXBS_PRS2_M3_MASK                        (0x7000U)
#define AXBS_PRS2_M3_SHIFT                       (12U)
/*! M3 - Master 3 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS2_M3(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_PRS2_M3_SHIFT)) & AXBS_PRS2_M3_MASK)

#define AXBS_PRS2_M4_MASK                        (0x70000U)
#define AXBS_PRS2_M4_SHIFT                       (16U)
/*! M4 - Master 4 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS2_M4(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_PRS2_M4_SHIFT)) & AXBS_PRS2_M4_MASK)

#define AXBS_PRS2_M5_MASK                        (0x700000U)
#define AXBS_PRS2_M5_SHIFT                       (20U)
/*! M5 - Master 5 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS2_M5(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_PRS2_M5_SHIFT)) & AXBS_PRS2_M5_MASK)
/*! @} */

/*! @name CRS2 - Control Register */
/*! @{ */

#define AXBS_CRS2_PARK_MASK                      (0x7U)
#define AXBS_CRS2_PARK_SHIFT                     (0U)
/*! PARK - Park
 *  0b111..Park on master port M0.
 *  0b001..Park on master port M1.
 *  0b010..Park on master port M2.
 *  0b011..Park on master port M3.
 *  0b100..Park on master port M4.
 *  0b101..Park on master port M5.
 */
#define AXBS_CRS2_PARK(x)                        (((uint32_t)(((uint32_t)(x)) << AXBS_CRS2_PARK_SHIFT)) & AXBS_CRS2_PARK_MASK)

#define AXBS_CRS2_PCTL_MASK                      (0x30U)
#define AXBS_CRS2_PCTL_SHIFT                     (4U)
/*! PCTL - Parking Control
 *  0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field.
 *  0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port.
 *  0b10..When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state.
 *  0b11..Reserved
 */
#define AXBS_CRS2_PCTL(x)                        (((uint32_t)(((uint32_t)(x)) << AXBS_CRS2_PCTL_SHIFT)) & AXBS_CRS2_PCTL_MASK)

#define AXBS_CRS2_ARB_MASK                       (0x300U)
#define AXBS_CRS2_ARB_SHIFT                      (8U)
/*! ARB - Arbitration Mode
 *  0b00..Fixed priority
 *  0b01..Round-robin(RR) or rotating priority
 *  0b10..Reserved
 *  0b11..Reserved
 */
#define AXBS_CRS2_ARB(x)                         (((uint32_t)(((uint32_t)(x)) << AXBS_CRS2_ARB_SHIFT)) & AXBS_CRS2_ARB_MASK)

#define AXBS_CRS2_HLP_MASK                       (0x40000000U)
#define AXBS_CRS2_HLP_SHIFT                      (30U)
/*! HLP - Halt Low Priority
 *  0b0..The low-power mode request has the highest priority for arbitration on this slave port.
 *  0b1..The low-power mode request has the lowest initial priority for arbitration on this slave port.
 */
#define AXBS_CRS2_HLP(x)                         (((uint32_t)(((uint32_t)(x)) << AXBS_CRS2_HLP_SHIFT)) & AXBS_CRS2_HLP_MASK)

#define AXBS_CRS2_RO_MASK                        (0x80000000U)
#define AXBS_CRS2_RO_SHIFT                       (31U)
/*! RO - Read Only
 *  0b0..The slave port's registers are writeable.
 *  0b1..The slave port's registers are read-only and cannot be written. Attempted writes have no effect on the
 *       registers and result in a bus error response.
 */
#define AXBS_CRS2_RO(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_CRS2_RO_SHIFT)) & AXBS_CRS2_RO_MASK)
/*! @} */

/*! @name PRS3 - Priority Slave Registers */
/*! @{ */

#define AXBS_PRS3_M0_MASK                        (0x7U)
#define AXBS_PRS3_M0_SHIFT                       (0U)
/*! M0 - Master 0 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS3_M0(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_PRS3_M0_SHIFT)) & AXBS_PRS3_M0_MASK)

#define AXBS_PRS3_M1_MASK                        (0x70U)
#define AXBS_PRS3_M1_SHIFT                       (4U)
/*! M1 - Master 1 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS3_M1(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_PRS3_M1_SHIFT)) & AXBS_PRS3_M1_MASK)

#define AXBS_PRS3_M2_MASK                        (0x700U)
#define AXBS_PRS3_M2_SHIFT                       (8U)
/*! M2 - Master 2 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS3_M2(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_PRS3_M2_SHIFT)) & AXBS_PRS3_M2_MASK)

#define AXBS_PRS3_M3_MASK                        (0x7000U)
#define AXBS_PRS3_M3_SHIFT                       (12U)
/*! M3 - Master 3 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS3_M3(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_PRS3_M3_SHIFT)) & AXBS_PRS3_M3_MASK)

#define AXBS_PRS3_M4_MASK                        (0x70000U)
#define AXBS_PRS3_M4_SHIFT                       (16U)
/*! M4 - Master 4 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS3_M4(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_PRS3_M4_SHIFT)) & AXBS_PRS3_M4_MASK)

#define AXBS_PRS3_M5_MASK                        (0x700000U)
#define AXBS_PRS3_M5_SHIFT                       (20U)
/*! M5 - Master 5 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS3_M5(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_PRS3_M5_SHIFT)) & AXBS_PRS3_M5_MASK)
/*! @} */

/*! @name CRS3 - Control Register */
/*! @{ */

#define AXBS_CRS3_PARK_MASK                      (0x7U)
#define AXBS_CRS3_PARK_SHIFT                     (0U)
/*! PARK - Park
 *  0b111..Park on master port M0.
 *  0b001..Park on master port M1.
 *  0b010..Park on master port M2.
 *  0b011..Park on master port M3.
 *  0b100..Park on master port M4.
 *  0b101..Park on master port M5.
 */
#define AXBS_CRS3_PARK(x)                        (((uint32_t)(((uint32_t)(x)) << AXBS_CRS3_PARK_SHIFT)) & AXBS_CRS3_PARK_MASK)

#define AXBS_CRS3_PCTL_MASK                      (0x30U)
#define AXBS_CRS3_PCTL_SHIFT                     (4U)
/*! PCTL - Parking Control
 *  0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field.
 *  0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port.
 *  0b10..When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state.
 *  0b11..Reserved
 */
#define AXBS_CRS3_PCTL(x)                        (((uint32_t)(((uint32_t)(x)) << AXBS_CRS3_PCTL_SHIFT)) & AXBS_CRS3_PCTL_MASK)

#define AXBS_CRS3_ARB_MASK                       (0x300U)
#define AXBS_CRS3_ARB_SHIFT                      (8U)
/*! ARB - Arbitration Mode
 *  0b00..Fixed priority
 *  0b01..Round-robin(RR) or rotating priority
 *  0b10..Reserved
 *  0b11..Reserved
 */
#define AXBS_CRS3_ARB(x)                         (((uint32_t)(((uint32_t)(x)) << AXBS_CRS3_ARB_SHIFT)) & AXBS_CRS3_ARB_MASK)

#define AXBS_CRS3_HLP_MASK                       (0x40000000U)
#define AXBS_CRS3_HLP_SHIFT                      (30U)
/*! HLP - Halt Low Priority
 *  0b0..The low-power mode request has the highest priority for arbitration on this slave port.
 *  0b1..The low-power mode request has the lowest initial priority for arbitration on this slave port.
 */
#define AXBS_CRS3_HLP(x)                         (((uint32_t)(((uint32_t)(x)) << AXBS_CRS3_HLP_SHIFT)) & AXBS_CRS3_HLP_MASK)

#define AXBS_CRS3_RO_MASK                        (0x80000000U)
#define AXBS_CRS3_RO_SHIFT                       (31U)
/*! RO - Read Only
 *  0b0..The slave port's registers are writeable.
 *  0b1..The slave port's registers are read-only and cannot be written. Attempted writes have no effect on the
 *       registers and result in a bus error response.
 */
#define AXBS_CRS3_RO(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_CRS3_RO_SHIFT)) & AXBS_CRS3_RO_MASK)
/*! @} */

/*! @name PRS4 - Priority Slave Registers */
/*! @{ */

#define AXBS_PRS4_M0_MASK                        (0x7U)
#define AXBS_PRS4_M0_SHIFT                       (0U)
/*! M0 - Master 0 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS4_M0(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_PRS4_M0_SHIFT)) & AXBS_PRS4_M0_MASK)

#define AXBS_PRS4_M1_MASK                        (0x70U)
#define AXBS_PRS4_M1_SHIFT                       (4U)
/*! M1 - Master 1 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS4_M1(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_PRS4_M1_SHIFT)) & AXBS_PRS4_M1_MASK)

#define AXBS_PRS4_M2_MASK                        (0x700U)
#define AXBS_PRS4_M2_SHIFT                       (8U)
/*! M2 - Master 2 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS4_M2(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_PRS4_M2_SHIFT)) & AXBS_PRS4_M2_MASK)

#define AXBS_PRS4_M3_MASK                        (0x7000U)
#define AXBS_PRS4_M3_SHIFT                       (12U)
/*! M3 - Master 3 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS4_M3(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_PRS4_M3_SHIFT)) & AXBS_PRS4_M3_MASK)

#define AXBS_PRS4_M4_MASK                        (0x70000U)
#define AXBS_PRS4_M4_SHIFT                       (16U)
/*! M4 - Master 4 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS4_M4(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_PRS4_M4_SHIFT)) & AXBS_PRS4_M4_MASK)

#define AXBS_PRS4_M5_MASK                        (0x700000U)
#define AXBS_PRS4_M5_SHIFT                       (20U)
/*! M5 - Master 5 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS4_M5(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_PRS4_M5_SHIFT)) & AXBS_PRS4_M5_MASK)
/*! @} */

/*! @name CRS4 - Control Register */
/*! @{ */

#define AXBS_CRS4_PARK_MASK                      (0x7U)
#define AXBS_CRS4_PARK_SHIFT                     (0U)
/*! PARK - Park
 *  0b111..Park on master port M0.
 *  0b001..Park on master port M1.
 *  0b010..Park on master port M2.
 *  0b011..Park on master port M3.
 *  0b100..Park on master port M4.
 *  0b101..Park on master port M5.
 */
#define AXBS_CRS4_PARK(x)                        (((uint32_t)(((uint32_t)(x)) << AXBS_CRS4_PARK_SHIFT)) & AXBS_CRS4_PARK_MASK)

#define AXBS_CRS4_PCTL_MASK                      (0x30U)
#define AXBS_CRS4_PCTL_SHIFT                     (4U)
/*! PCTL - Parking Control
 *  0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field.
 *  0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port.
 *  0b10..When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state.
 *  0b11..Reserved
 */
#define AXBS_CRS4_PCTL(x)                        (((uint32_t)(((uint32_t)(x)) << AXBS_CRS4_PCTL_SHIFT)) & AXBS_CRS4_PCTL_MASK)

#define AXBS_CRS4_ARB_MASK                       (0x300U)
#define AXBS_CRS4_ARB_SHIFT                      (8U)
/*! ARB - Arbitration Mode
 *  0b00..Fixed priority
 *  0b01..Round-robin(RR) or rotating priority
 *  0b10..Reserved
 *  0b11..Reserved
 */
#define AXBS_CRS4_ARB(x)                         (((uint32_t)(((uint32_t)(x)) << AXBS_CRS4_ARB_SHIFT)) & AXBS_CRS4_ARB_MASK)

#define AXBS_CRS4_HLP_MASK                       (0x40000000U)
#define AXBS_CRS4_HLP_SHIFT                      (30U)
/*! HLP - Halt Low Priority
 *  0b0..The low-power mode request has the highest priority for arbitration on this slave port.
 *  0b1..The low-power mode request has the lowest initial priority for arbitration on this slave port.
 */
#define AXBS_CRS4_HLP(x)                         (((uint32_t)(((uint32_t)(x)) << AXBS_CRS4_HLP_SHIFT)) & AXBS_CRS4_HLP_MASK)

#define AXBS_CRS4_RO_MASK                        (0x80000000U)
#define AXBS_CRS4_RO_SHIFT                       (31U)
/*! RO - Read Only
 *  0b0..The slave port's registers are writeable.
 *  0b1..The slave port's registers are read-only and cannot be written. Attempted writes have no effect on the
 *       registers and result in a bus error response.
 */
#define AXBS_CRS4_RO(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_CRS4_RO_SHIFT)) & AXBS_CRS4_RO_MASK)
/*! @} */

/*! @name PRS5 - Priority Slave Registers */
/*! @{ */

#define AXBS_PRS5_M0_MASK                        (0x7U)
#define AXBS_PRS5_M0_SHIFT                       (0U)
/*! M0 - Master 0 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS5_M0(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_PRS5_M0_SHIFT)) & AXBS_PRS5_M0_MASK)

#define AXBS_PRS5_M1_MASK                        (0x70U)
#define AXBS_PRS5_M1_SHIFT                       (4U)
/*! M1 - Master 1 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS5_M1(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_PRS5_M1_SHIFT)) & AXBS_PRS5_M1_MASK)

#define AXBS_PRS5_M2_MASK                        (0x700U)
#define AXBS_PRS5_M2_SHIFT                       (8U)
/*! M2 - Master 2 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS5_M2(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_PRS5_M2_SHIFT)) & AXBS_PRS5_M2_MASK)

#define AXBS_PRS5_M3_MASK                        (0x7000U)
#define AXBS_PRS5_M3_SHIFT                       (12U)
/*! M3 - Master 3 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS5_M3(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_PRS5_M3_SHIFT)) & AXBS_PRS5_M3_MASK)

#define AXBS_PRS5_M4_MASK                        (0x70000U)
#define AXBS_PRS5_M4_SHIFT                       (16U)
/*! M4 - Master 4 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS5_M4(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_PRS5_M4_SHIFT)) & AXBS_PRS5_M4_MASK)

#define AXBS_PRS5_M5_MASK                        (0x700000U)
#define AXBS_PRS5_M5_SHIFT                       (20U)
/*! M5 - Master 5 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS5_M5(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_PRS5_M5_SHIFT)) & AXBS_PRS5_M5_MASK)
/*! @} */

/*! @name CRS5 - Control Register */
/*! @{ */

#define AXBS_CRS5_PARK_MASK                      (0x7U)
#define AXBS_CRS5_PARK_SHIFT                     (0U)
/*! PARK - Park
 *  0b111..Park on master port M0.
 *  0b001..Park on master port M1.
 *  0b010..Park on master port M2.
 *  0b011..Park on master port M3.
 *  0b100..Park on master port M4.
 *  0b101..Park on master port M5.
 */
#define AXBS_CRS5_PARK(x)                        (((uint32_t)(((uint32_t)(x)) << AXBS_CRS5_PARK_SHIFT)) & AXBS_CRS5_PARK_MASK)

#define AXBS_CRS5_PCTL_MASK                      (0x30U)
#define AXBS_CRS5_PCTL_SHIFT                     (4U)
/*! PCTL - Parking Control
 *  0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field.
 *  0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port.
 *  0b10..When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state.
 *  0b11..Reserved
 */
#define AXBS_CRS5_PCTL(x)                        (((uint32_t)(((uint32_t)(x)) << AXBS_CRS5_PCTL_SHIFT)) & AXBS_CRS5_PCTL_MASK)

#define AXBS_CRS5_ARB_MASK                       (0x300U)
#define AXBS_CRS5_ARB_SHIFT                      (8U)
/*! ARB - Arbitration Mode
 *  0b00..Fixed priority
 *  0b01..Round-robin(RR) or rotating priority
 *  0b10..Reserved
 *  0b11..Reserved
 */
#define AXBS_CRS5_ARB(x)                         (((uint32_t)(((uint32_t)(x)) << AXBS_CRS5_ARB_SHIFT)) & AXBS_CRS5_ARB_MASK)

#define AXBS_CRS5_HLP_MASK                       (0x40000000U)
#define AXBS_CRS5_HLP_SHIFT                      (30U)
/*! HLP - Halt Low Priority
 *  0b0..The low-power mode request has the highest priority for arbitration on this slave port.
 *  0b1..The low-power mode request has the lowest initial priority for arbitration on this slave port.
 */
#define AXBS_CRS5_HLP(x)                         (((uint32_t)(((uint32_t)(x)) << AXBS_CRS5_HLP_SHIFT)) & AXBS_CRS5_HLP_MASK)

#define AXBS_CRS5_RO_MASK                        (0x80000000U)
#define AXBS_CRS5_RO_SHIFT                       (31U)
/*! RO - Read Only
 *  0b0..The slave port's registers are writeable.
 *  0b1..The slave port's registers are read-only and cannot be written. Attempted writes have no effect on the
 *       registers and result in a bus error response.
 */
#define AXBS_CRS5_RO(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_CRS5_RO_SHIFT)) & AXBS_CRS5_RO_MASK)
/*! @} */

/*! @name PRS6 - Priority Slave Registers */
/*! @{ */

#define AXBS_PRS6_M0_MASK                        (0x7U)
#define AXBS_PRS6_M0_SHIFT                       (0U)
/*! M0 - Master 0 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS6_M0(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_PRS6_M0_SHIFT)) & AXBS_PRS6_M0_MASK)

#define AXBS_PRS6_M1_MASK                        (0x70U)
#define AXBS_PRS6_M1_SHIFT                       (4U)
/*! M1 - Master 1 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS6_M1(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_PRS6_M1_SHIFT)) & AXBS_PRS6_M1_MASK)

#define AXBS_PRS6_M2_MASK                        (0x700U)
#define AXBS_PRS6_M2_SHIFT                       (8U)
/*! M2 - Master 2 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS6_M2(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_PRS6_M2_SHIFT)) & AXBS_PRS6_M2_MASK)

#define AXBS_PRS6_M3_MASK                        (0x7000U)
#define AXBS_PRS6_M3_SHIFT                       (12U)
/*! M3 - Master 3 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS6_M3(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_PRS6_M3_SHIFT)) & AXBS_PRS6_M3_MASK)

#define AXBS_PRS6_M4_MASK                        (0x70000U)
#define AXBS_PRS6_M4_SHIFT                       (16U)
/*! M4 - Master 4 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS6_M4(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_PRS6_M4_SHIFT)) & AXBS_PRS6_M4_MASK)

#define AXBS_PRS6_M5_MASK                        (0x700000U)
#define AXBS_PRS6_M5_SHIFT                       (20U)
/*! M5 - Master 5 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS6_M5(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_PRS6_M5_SHIFT)) & AXBS_PRS6_M5_MASK)
/*! @} */

/*! @name CRS6 - Control Register */
/*! @{ */

#define AXBS_CRS6_PARK_MASK                      (0x7U)
#define AXBS_CRS6_PARK_SHIFT                     (0U)
/*! PARK - Park
 *  0b111..Park on master port M0.
 *  0b001..Park on master port M1.
 *  0b010..Park on master port M2.
 *  0b011..Park on master port M3.
 *  0b100..Park on master port M4.
 *  0b101..Park on master port M5.
 */
#define AXBS_CRS6_PARK(x)                        (((uint32_t)(((uint32_t)(x)) << AXBS_CRS6_PARK_SHIFT)) & AXBS_CRS6_PARK_MASK)

#define AXBS_CRS6_PCTL_MASK                      (0x30U)
#define AXBS_CRS6_PCTL_SHIFT                     (4U)
/*! PCTL - Parking Control
 *  0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field.
 *  0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port.
 *  0b10..When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state.
 *  0b11..Reserved
 */
#define AXBS_CRS6_PCTL(x)                        (((uint32_t)(((uint32_t)(x)) << AXBS_CRS6_PCTL_SHIFT)) & AXBS_CRS6_PCTL_MASK)

#define AXBS_CRS6_ARB_MASK                       (0x300U)
#define AXBS_CRS6_ARB_SHIFT                      (8U)
/*! ARB - Arbitration Mode
 *  0b00..Fixed priority
 *  0b01..Round-robin(RR) or rotating priority
 *  0b10..Reserved
 *  0b11..Reserved
 */
#define AXBS_CRS6_ARB(x)                         (((uint32_t)(((uint32_t)(x)) << AXBS_CRS6_ARB_SHIFT)) & AXBS_CRS6_ARB_MASK)

#define AXBS_CRS6_HLP_MASK                       (0x40000000U)
#define AXBS_CRS6_HLP_SHIFT                      (30U)
/*! HLP - Halt Low Priority
 *  0b0..The low-power mode request has the highest priority for arbitration on this slave port.
 *  0b1..The low-power mode request has the lowest initial priority for arbitration on this slave port.
 */
#define AXBS_CRS6_HLP(x)                         (((uint32_t)(((uint32_t)(x)) << AXBS_CRS6_HLP_SHIFT)) & AXBS_CRS6_HLP_MASK)

#define AXBS_CRS6_RO_MASK                        (0x80000000U)
#define AXBS_CRS6_RO_SHIFT                       (31U)
/*! RO - Read Only
 *  0b0..The slave port's registers are writeable.
 *  0b1..The slave port's registers are read-only and cannot be written. Attempted writes have no effect on the
 *       registers and result in a bus error response.
 */
#define AXBS_CRS6_RO(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_CRS6_RO_SHIFT)) & AXBS_CRS6_RO_MASK)
/*! @} */

/*! @name PRS7 - Priority Slave Registers */
/*! @{ */

#define AXBS_PRS7_M0_MASK                        (0x7U)
#define AXBS_PRS7_M0_SHIFT                       (0U)
/*! M0 - Master 0 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS7_M0(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_PRS7_M0_SHIFT)) & AXBS_PRS7_M0_MASK)

#define AXBS_PRS7_M1_MASK                        (0x70U)
#define AXBS_PRS7_M1_SHIFT                       (4U)
/*! M1 - Master 1 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS7_M1(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_PRS7_M1_SHIFT)) & AXBS_PRS7_M1_MASK)

#define AXBS_PRS7_M2_MASK                        (0x700U)
#define AXBS_PRS7_M2_SHIFT                       (8U)
/*! M2 - Master 2 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS7_M2(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_PRS7_M2_SHIFT)) & AXBS_PRS7_M2_MASK)

#define AXBS_PRS7_M3_MASK                        (0x7000U)
#define AXBS_PRS7_M3_SHIFT                       (12U)
/*! M3 - Master 3 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS7_M3(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_PRS7_M3_SHIFT)) & AXBS_PRS7_M3_MASK)

#define AXBS_PRS7_M4_MASK                        (0x70000U)
#define AXBS_PRS7_M4_SHIFT                       (16U)
/*! M4 - Master 4 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS7_M4(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_PRS7_M4_SHIFT)) & AXBS_PRS7_M4_MASK)

#define AXBS_PRS7_M5_MASK                        (0x700000U)
#define AXBS_PRS7_M5_SHIFT                       (20U)
/*! M5 - Master 5 Priority
 *  0b000..This master has level 1 or highest priority when accessing the slave port.
 *  0b001..This master has level 2 priority when accessing the slave port.
 *  0b010..This master has level 3 priority when accessing the slave port.
 *  0b011..This master has level 4 priority when accessing the slave port.
 *  0b100..This master has level 5 priority when accessing the slave port.
 *  0b101..This master has level 6 priority when accessing the slave port.
 *  0b110..This master has level 7 priority when accessing the slave port.
 *  0b111..This master has level 8 or lowest priority when accessing the slave port.
 */
#define AXBS_PRS7_M5(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_PRS7_M5_SHIFT)) & AXBS_PRS7_M5_MASK)
/*! @} */

/*! @name CRS7 - Control Register */
/*! @{ */

#define AXBS_CRS7_PARK_MASK                      (0x7U)
#define AXBS_CRS7_PARK_SHIFT                     (0U)
/*! PARK - Park
 *  0b111..Park on master port M0.
 *  0b001..Park on master port M1.
 *  0b010..Park on master port M2.
 *  0b011..Park on master port M3.
 *  0b100..Park on master port M4.
 *  0b101..Park on master port M5.
 */
#define AXBS_CRS7_PARK(x)                        (((uint32_t)(((uint32_t)(x)) << AXBS_CRS7_PARK_SHIFT)) & AXBS_CRS7_PARK_MASK)

#define AXBS_CRS7_PCTL_MASK                      (0x30U)
#define AXBS_CRS7_PCTL_SHIFT                     (4U)
/*! PCTL - Parking Control
 *  0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field.
 *  0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port.
 *  0b10..When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state.
 *  0b11..Reserved
 */
#define AXBS_CRS7_PCTL(x)                        (((uint32_t)(((uint32_t)(x)) << AXBS_CRS7_PCTL_SHIFT)) & AXBS_CRS7_PCTL_MASK)

#define AXBS_CRS7_ARB_MASK                       (0x300U)
#define AXBS_CRS7_ARB_SHIFT                      (8U)
/*! ARB - Arbitration Mode
 *  0b00..Fixed priority
 *  0b01..Round-robin(RR) or rotating priority
 *  0b10..Reserved
 *  0b11..Reserved
 */
#define AXBS_CRS7_ARB(x)                         (((uint32_t)(((uint32_t)(x)) << AXBS_CRS7_ARB_SHIFT)) & AXBS_CRS7_ARB_MASK)

#define AXBS_CRS7_HLP_MASK                       (0x40000000U)
#define AXBS_CRS7_HLP_SHIFT                      (30U)
/*! HLP - Halt Low Priority
 *  0b0..The low-power mode request has the highest priority for arbitration on this slave port.
 *  0b1..The low-power mode request has the lowest initial priority for arbitration on this slave port.
 */
#define AXBS_CRS7_HLP(x)                         (((uint32_t)(((uint32_t)(x)) << AXBS_CRS7_HLP_SHIFT)) & AXBS_CRS7_HLP_MASK)

#define AXBS_CRS7_RO_MASK                        (0x80000000U)
#define AXBS_CRS7_RO_SHIFT                       (31U)
/*! RO - Read Only
 *  0b0..The slave port's registers are writeable.
 *  0b1..The slave port's registers are read-only and cannot be written. Attempted writes have no effect on the
 *       registers and result in a bus error response.
 */
#define AXBS_CRS7_RO(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_CRS7_RO_SHIFT)) & AXBS_CRS7_RO_MASK)
/*! @} */

/*! @name MGPCR0 - Master General Purpose Control Register */
/*! @{ */

#define AXBS_MGPCR0_AULB_MASK                    (0x7U)
#define AXBS_MGPCR0_AULB_SHIFT                   (0U)
/*! AULB - Arbitrates On Undefined Length Bursts
 *  0b000..No arbitration is allowed during an undefined length burst.
 *  0b001..Arbitration is allowed at any time during an undefined length burst.
 *  0b010..Arbitration is allowed after four beats of an undefined length burst.
 *  0b011..Arbitration is allowed after eight beats of an undefined length burst.
 *  0b100..Arbitration is allowed after 16 beats of an undefined length burst.
 *  0b101..Reserved
 *  0b110..Reserved
 *  0b111..Reserved
 */
#define AXBS_MGPCR0_AULB(x)                      (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR0_AULB_SHIFT)) & AXBS_MGPCR0_AULB_MASK)
/*! @} */

/*! @name MGPCR1 - Master General Purpose Control Register */
/*! @{ */

#define AXBS_MGPCR1_AULB_MASK                    (0x7U)
#define AXBS_MGPCR1_AULB_SHIFT                   (0U)
/*! AULB - Arbitrates On Undefined Length Bursts
 *  0b000..No arbitration is allowed during an undefined length burst.
 *  0b001..Arbitration is allowed at any time during an undefined length burst.
 *  0b010..Arbitration is allowed after four beats of an undefined length burst.
 *  0b011..Arbitration is allowed after eight beats of an undefined length burst.
 *  0b100..Arbitration is allowed after 16 beats of an undefined length burst.
 *  0b101..Reserved
 *  0b110..Reserved
 *  0b111..Reserved
 */
#define AXBS_MGPCR1_AULB(x)                      (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR1_AULB_SHIFT)) & AXBS_MGPCR1_AULB_MASK)
/*! @} */

/*! @name MGPCR2 - Master General Purpose Control Register */
/*! @{ */

#define AXBS_MGPCR2_AULB_MASK                    (0x7U)
#define AXBS_MGPCR2_AULB_SHIFT                   (0U)
/*! AULB - Arbitrates On Undefined Length Bursts
 *  0b000..No arbitration is allowed during an undefined length burst.
 *  0b001..Arbitration is allowed at any time during an undefined length burst.
 *  0b010..Arbitration is allowed after four beats of an undefined length burst.
 *  0b011..Arbitration is allowed after eight beats of an undefined length burst.
 *  0b100..Arbitration is allowed after 16 beats of an undefined length burst.
 *  0b101..Reserved
 *  0b110..Reserved
 *  0b111..Reserved
 */
#define AXBS_MGPCR2_AULB(x)                      (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR2_AULB_SHIFT)) & AXBS_MGPCR2_AULB_MASK)
/*! @} */

/*! @name MGPCR3 - Master General Purpose Control Register */
/*! @{ */

#define AXBS_MGPCR3_AULB_MASK                    (0x7U)
#define AXBS_MGPCR3_AULB_SHIFT                   (0U)
/*! AULB - Arbitrates On Undefined Length Bursts
 *  0b000..No arbitration is allowed during an undefined length burst.
 *  0b001..Arbitration is allowed at any time during an undefined length burst.
 *  0b010..Arbitration is allowed after four beats of an undefined length burst.
 *  0b011..Arbitration is allowed after eight beats of an undefined length burst.
 *  0b100..Arbitration is allowed after 16 beats of an undefined length burst.
 *  0b101..Reserved
 *  0b110..Reserved
 *  0b111..Reserved
 */
#define AXBS_MGPCR3_AULB(x)                      (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR3_AULB_SHIFT)) & AXBS_MGPCR3_AULB_MASK)
/*! @} */

/*! @name MGPCR4 - Master General Purpose Control Register */
/*! @{ */

#define AXBS_MGPCR4_AULB_MASK                    (0x7U)
#define AXBS_MGPCR4_AULB_SHIFT                   (0U)
/*! AULB - Arbitrates On Undefined Length Bursts
 *  0b000..No arbitration is allowed during an undefined length burst.
 *  0b001..Arbitration is allowed at any time during an undefined length burst.
 *  0b010..Arbitration is allowed after four beats of an undefined length burst.
 *  0b011..Arbitration is allowed after eight beats of an undefined length burst.
 *  0b100..Arbitration is allowed after 16 beats of an undefined length burst.
 *  0b101..Reserved
 *  0b110..Reserved
 *  0b111..Reserved
 */
#define AXBS_MGPCR4_AULB(x)                      (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR4_AULB_SHIFT)) & AXBS_MGPCR4_AULB_MASK)
/*! @} */

/*! @name MGPCR5 - Master General Purpose Control Register */
/*! @{ */

#define AXBS_MGPCR5_AULB_MASK                    (0x7U)
#define AXBS_MGPCR5_AULB_SHIFT                   (0U)
/*! AULB - Arbitrates On Undefined Length Bursts
 *  0b000..No arbitration is allowed during an undefined length burst.
 *  0b001..Arbitration is allowed at any time during an undefined length burst.
 *  0b010..Arbitration is allowed after four beats of an undefined length burst.
 *  0b011..Arbitration is allowed after eight beats of an undefined length burst.
 *  0b100..Arbitration is allowed after 16 beats of an undefined length burst.
 *  0b101..Reserved
 *  0b110..Reserved
 *  0b111..Reserved
 */
#define AXBS_MGPCR5_AULB(x)                      (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR5_AULB_SHIFT)) & AXBS_MGPCR5_AULB_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group AXBS_Register_Masks */


/* AXBS - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral AXBS0 base address */
  #define AXBS0_BASE                               (0x50000000u)
  /** Peripheral AXBS0 base address */
  #define AXBS0_BASE_NS                            (0x40000000u)
  /** Peripheral AXBS0 base pointer */
  #define AXBS0                                    ((AXBS_Type *)AXBS0_BASE)
  /** Peripheral AXBS0 base pointer */
  #define AXBS0_NS                                 ((AXBS_Type *)AXBS0_BASE_NS)
  /** Array initializer of AXBS peripheral base addresses */
  #define AXBS_BASE_ADDRS                          { AXBS0_BASE }
  /** Array initializer of AXBS peripheral base pointers */
  #define AXBS_BASE_PTRS                           { AXBS0 }
  /** Array initializer of AXBS peripheral base addresses */
  #define AXBS_BASE_ADDRS_NS                       { AXBS0_BASE_NS }
  /** Array initializer of AXBS peripheral base pointers */
  #define AXBS_BASE_PTRS_NS                        { AXBS0_NS }
#else
  /** Peripheral AXBS0 base address */
  #define AXBS0_BASE                               (0x40000000u)
  /** Peripheral AXBS0 base pointer */
  #define AXBS0                                    ((AXBS_Type *)AXBS0_BASE)
  /** Array initializer of AXBS peripheral base addresses */
  #define AXBS_BASE_ADDRS                          { AXBS0_BASE }
  /** Array initializer of AXBS peripheral base pointers */
  #define AXBS_BASE_PTRS                           { AXBS0 }
#endif

/*!
 * @}
 */ /* end of group AXBS_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- BRIC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup BRIC_Peripheral_Access_Layer BRIC Peripheral Access Layer
 * @{
 */

/** BRIC - Register Layout Typedef */
typedef struct {
  __O  uint32_t KEY0[4];                           /**< KEY0 Registers (PKB), array offset: 0x0, array step: 0x4 */
  __O  uint32_t KEY1[4];                           /**< KEY1 Registers (PKB), array offset: 0x10, array step: 0x4 */
  __IO uint32_t BRIC_CONFIG;                       /**< BRIC CONFIG register, offset: 0x20 */
} BRIC_Type;

/* ----------------------------------------------------------------------------
   -- BRIC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup BRIC_Register_Masks BRIC Register Masks
 * @{
 */

/*! @name KEY0 - KEY0 Registers (PKB) */
/*! @{ */

#define BRIC_KEY0_KEY0_x_MASK                    (0xFFFFFFFFU)
#define BRIC_KEY0_KEY0_x_SHIFT                   (0U)
/*! KEY0_x - KEY0 written through PKB interface
 */
#define BRIC_KEY0_KEY0_x(x)                      (((uint32_t)(((uint32_t)(x)) << BRIC_KEY0_KEY0_x_SHIFT)) & BRIC_KEY0_KEY0_x_MASK)
/*! @} */

/* The count of BRIC_KEY0 */
#define BRIC_KEY0_COUNT                          (4U)

/*! @name KEY1 - KEY1 Registers (PKB) */
/*! @{ */

#define BRIC_KEY1_KEY1_x_MASK                    (0xFFFFFFFFU)
#define BRIC_KEY1_KEY1_x_SHIFT                   (0U)
/*! KEY1_x - KEY1 written through PKB interface
 */
#define BRIC_KEY1_KEY1_x(x)                      (((uint32_t)(((uint32_t)(x)) << BRIC_KEY1_KEY1_x_SHIFT)) & BRIC_KEY1_KEY1_x_MASK)
/*! @} */

/* The count of BRIC_KEY1 */
#define BRIC_KEY1_COUNT                          (4U)

/*! @name BRIC_CONFIG - BRIC CONFIG register */
/*! @{ */

#define BRIC_BRIC_CONFIG_KEY_INDEX_MASK          (0xFFU)
#define BRIC_BRIC_CONFIG_KEY_INDEX_SHIFT         (0U)
/*! KEY_INDEX - KEY INDEX
 */
#define BRIC_BRIC_CONFIG_KEY_INDEX(x)            (((uint32_t)(((uint32_t)(x)) << BRIC_BRIC_CONFIG_KEY_INDEX_SHIFT)) & BRIC_BRIC_CONFIG_KEY_INDEX_MASK)

#define BRIC_BRIC_CONFIG_IPS_XFR_ERR_EN_MASK     (0x100U)
#define BRIC_BRIC_CONFIG_IPS_XFR_ERR_EN_SHIFT    (8U)
#define BRIC_BRIC_CONFIG_IPS_XFR_ERR_EN(x)       (((uint32_t)(((uint32_t)(x)) << BRIC_BRIC_CONFIG_IPS_XFR_ERR_EN_SHIFT)) & BRIC_BRIC_CONFIG_IPS_XFR_ERR_EN_MASK)

#define BRIC_BRIC_CONFIG_IPS_XFR_WAIT_EN_MASK    (0x200U)
#define BRIC_BRIC_CONFIG_IPS_XFR_WAIT_EN_SHIFT   (9U)
#define BRIC_BRIC_CONFIG_IPS_XFR_WAIT_EN(x)      (((uint32_t)(((uint32_t)(x)) << BRIC_BRIC_CONFIG_IPS_XFR_WAIT_EN_SHIFT)) & BRIC_BRIC_CONFIG_IPS_XFR_WAIT_EN_MASK)

#define BRIC_BRIC_CONFIG_HI_MODE_MASK            (0x400U)
#define BRIC_BRIC_CONFIG_HI_MODE_SHIFT           (10U)
#define BRIC_BRIC_CONFIG_HI_MODE(x)              (((uint32_t)(((uint32_t)(x)) << BRIC_BRIC_CONFIG_HI_MODE_SHIFT)) & BRIC_BRIC_CONFIG_HI_MODE_MASK)

#define BRIC_BRIC_CONFIG_HI_READY_MASK           (0x800U)
#define BRIC_BRIC_CONFIG_HI_READY_SHIFT          (11U)
#define BRIC_BRIC_CONFIG_HI_READY(x)             (((uint32_t)(((uint32_t)(x)) << BRIC_BRIC_CONFIG_HI_READY_SHIFT)) & BRIC_BRIC_CONFIG_HI_READY_MASK)

#define BRIC_BRIC_CONFIG_DIS_PKB_ERR_RESP_MASK   (0x1000U)
#define BRIC_BRIC_CONFIG_DIS_PKB_ERR_RESP_SHIFT  (12U)
#define BRIC_BRIC_CONFIG_DIS_PKB_ERR_RESP(x)     (((uint32_t)(((uint32_t)(x)) << BRIC_BRIC_CONFIG_DIS_PKB_ERR_RESP_SHIFT)) & BRIC_BRIC_CONFIG_DIS_PKB_ERR_RESP_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group BRIC_Register_Masks */


/* BRIC - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral BRIC base address */
  #define BRIC_BASE                                (0x58A06700u)
  /** Peripheral BRIC base address */
  #define BRIC_BASE_NS                             (0x48A06700u)
  /** Peripheral BRIC base pointer */
  #define BRIC                                     ((BRIC_Type *)BRIC_BASE)
  /** Peripheral BRIC base pointer */
  #define BRIC_NS                                  ((BRIC_Type *)BRIC_BASE_NS)
  /** Array initializer of BRIC peripheral base addresses */
  #define BRIC_BASE_ADDRS                          { BRIC_BASE }
  /** Array initializer of BRIC peripheral base pointers */
  #define BRIC_BASE_PTRS                           { BRIC }
  /** Array initializer of BRIC peripheral base addresses */
  #define BRIC_BASE_ADDRS_NS                       { BRIC_BASE_NS }
  /** Array initializer of BRIC peripheral base pointers */
  #define BRIC_BASE_PTRS_NS                        { BRIC_NS }
#else
  /** Peripheral BRIC base address */
  #define BRIC_BASE                                (0x48A06700u)
  /** Peripheral BRIC base pointer */
  #define BRIC                                     ((BRIC_Type *)BRIC_BASE)
  /** Array initializer of BRIC peripheral base addresses */
  #define BRIC_BASE_ADDRS                          { BRIC_BASE }
  /** Array initializer of BRIC peripheral base pointers */
  #define BRIC_BASE_PTRS                           { BRIC }
#endif

/*!
 * @}
 */ /* end of group BRIC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CAN Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
 * @{
 */

/** CAN - Register Layout Typedef */
typedef struct {
  __IO uint32_t MCR;                               /**< Module Configuration Register, offset: 0x0 */
  __IO uint32_t CTRL1;                             /**< Control 1 Register, offset: 0x4 */
  __IO uint32_t TIMER;                             /**< Free Running Timer, offset: 0x8 */
       uint8_t RESERVED_0[4];
  __IO uint32_t RXMGMASK;                          /**< Rx Mailboxes Global Mask Register, offset: 0x10 */
  __IO uint32_t RX14MASK;                          /**< Rx 14 Mask Register, offset: 0x14 */
  __IO uint32_t RX15MASK;                          /**< Rx 15 Mask Register, offset: 0x18 */
  __IO uint32_t ECR;                               /**< Error Counter, offset: 0x1C */
  __IO uint32_t ESR1;                              /**< Error and Status 1 Register, offset: 0x20 */
       uint8_t RESERVED_1[4];
  __IO uint32_t IMASK1;                            /**< Interrupt Masks 1 Register, offset: 0x28 */
       uint8_t RESERVED_2[4];
  __IO uint32_t IFLAG1;                            /**< Interrupt Flags 1 Register, offset: 0x30 */
  __IO uint32_t CTRL2;                             /**< Control 2 Register, offset: 0x34 */
  __I  uint32_t ESR2;                              /**< Error and Status 2 Register, offset: 0x38 */
       uint8_t RESERVED_3[8];
  __I  uint32_t CRCR;                              /**< CRC Register, offset: 0x44 */
  __IO uint32_t RXFGMASK;                          /**< Legacy Rx FIFO Global Mask Register, offset: 0x48 */
  __I  uint32_t RXFIR;                             /**< Legacy Rx FIFO Information Register, offset: 0x4C */
  __IO uint32_t CBT;                               /**< CAN Bit Timing Register, offset: 0x50 */
       uint8_t RESERVED_4[44];
  union {                                          /* offset: 0x80 */
    struct {                                         /* offset: 0x80, array step: 0x10 */
      __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 31 CS Register, array offset: 0x80, array step: 0x10 */
      __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 31 ID Register, array offset: 0x84, array step: 0x10 */
      __IO uint32_t WORD[2];                           /**< Message Buffer 0 WORD_8B Register..Message Buffer 31 WORD_8B Register, array offset: 0x88, array step: index*0x10, index2*0x4 */
    } MB_8B[32];
    struct {                                         /* offset: 0x80, array step: 0x18 */
      __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 20 CS Register, array offset: 0x80, array step: 0x18 */
      __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 20 ID Register, array offset: 0x84, array step: 0x18 */
      __IO uint32_t WORD[4];                           /**< Message Buffer 0 WORD_16B Register..Message Buffer 20 WORD_16B Register, array offset: 0x88, array step: index*0x18, index2*0x4 */
    } MB_16B[21];
    struct {                                         /* offset: 0x80, array step: 0x28 */
      __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 11 CS Register, array offset: 0x80, array step: 0x28 */
      __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 11 ID Register, array offset: 0x84, array step: 0x28 */
      __IO uint32_t WORD[8];                           /**< Message Buffer 0 WORD_32B Register..Message Buffer 11 WORD_32B Register, array offset: 0x88, array step: index*0x28, index2*0x4 */
    } MB_32B[12];
    struct {                                         /* offset: 0x80, array step: 0x48 */
      __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 6 CS Register, array offset: 0x80, array step: 0x48 */
      __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 6 ID Register, array offset: 0x84, array step: 0x48 */
      __IO uint32_t WORD[16];                          /**< Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register, array offset: 0x88, array step: index*0x48, index2*0x4 */
    } MB_64B[7];
    struct {                                         /* offset: 0x80, array step: 0x10 */
      __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 31 CS Register, array offset: 0x80, array step: 0x10 */
      __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 31 ID Register, array offset: 0x84, array step: 0x10 */
      __IO uint32_t WORD0;                             /**< Message Buffer 0 WORD0 Register..Message Buffer 31 WORD0 Register, array offset: 0x88, array step: 0x10 */
      __IO uint32_t WORD1;                             /**< Message Buffer 0 WORD1 Register..Message Buffer 31 WORD1 Register, array offset: 0x8C, array step: 0x10 */
    } MB[32];
  };
       uint8_t RESERVED_5[1536];
  __IO uint32_t RXIMR[32];                         /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
       uint8_t RESERVED_6[512];
  __IO uint32_t CTRL1_PN;                          /**< Pretended Networking Control 1 Register, offset: 0xB00 */
  __IO uint32_t CTRL2_PN;                          /**< Pretended Networking Control 2 Register, offset: 0xB04 */
  __IO uint32_t WU_MTC;                            /**< Pretended Networking Wake Up Match Register, offset: 0xB08 */
  __IO uint32_t FLT_ID1;                           /**< Pretended Networking ID Filter 1 Register, offset: 0xB0C */
  __IO uint32_t FLT_DLC;                           /**< Pretended Networking DLC Filter Register, offset: 0xB10 */
  __IO uint32_t PL1_LO;                            /**< Pretended Networking Payload Low Filter 1 Register, offset: 0xB14 */
  __IO uint32_t PL1_HI;                            /**< Pretended Networking Payload High Filter 1 Register, offset: 0xB18 */
  __IO uint32_t FLT_ID2_IDMASK;                    /**< Pretended Networking ID Filter 2 Register / ID Mask Register, offset: 0xB1C */
  __IO uint32_t PL2_PLMASK_LO;                     /**< Pretended Networking Payload Low Filter 2 Register / Payload Low Mask register, offset: 0xB20 */
  __IO uint32_t PL2_PLMASK_HI;                     /**< Pretended Networking Payload High Filter 2 low order bits / Payload High Mask register, offset: 0xB24 */
       uint8_t RESERVED_7[24];
  struct {                                         /* offset: 0xB40, array step: 0x10 */
    __I  uint32_t CS;                                /**< Wake Up Message Buffer register for C/S, array offset: 0xB40, array step: 0x10 */
    __I  uint32_t ID;                                /**< Wake Up Message Buffer Register for ID, array offset: 0xB44, array step: 0x10 */
    __I  uint32_t D03;                               /**< Wake Up Message Buffer Register for Data 0-3, array offset: 0xB48, array step: 0x10 */
    __I  uint32_t D47;                               /**< Wake Up Message Buffer Register Data 4-7, array offset: 0xB4C, array step: 0x10 */
  } WMB[4];
       uint8_t RESERVED_8[112];
  __IO uint32_t EPRS;                              /**< Enhanced CAN Bit Timing Prescalers, offset: 0xBF0 */
  __IO uint32_t ENCBT;                             /**< Enhanced Nominal CAN Bit Timing, offset: 0xBF4 */
  __IO uint32_t EDCBT;                             /**< Enhanced Data Phase CAN bit Timing, offset: 0xBF8 */
  __IO uint32_t ETDC;                              /**< Enhanced Transceiver Delay Compensation, offset: 0xBFC */
  __IO uint32_t FDCTRL;                            /**< CAN FD Control Register, offset: 0xC00 */
  __IO uint32_t FDCBT;                             /**< CAN FD Bit Timing Register, offset: 0xC04 */
  __I  uint32_t FDCRC;                             /**< CAN FD CRC Register, offset: 0xC08 */
  __IO uint32_t ERFCR;                             /**< Enhanced Rx FIFO Control Register, offset: 0xC0C */
  __IO uint32_t ERFIER;                            /**< Enhanced Rx FIFO Interrupt Enable Register, offset: 0xC10 */
  __IO uint32_t ERFSR;                             /**< Enhanced Rx FIFO Status Register, offset: 0xC14 */
       uint8_t RESERVED_9[9192];
  __IO uint32_t ERFFEL[32];                        /**< Enhanced Rx FIFO Filter Element, array offset: 0x3000, array step: 0x4 */
} CAN_Type;

/* ----------------------------------------------------------------------------
   -- CAN Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CAN_Register_Masks CAN Register Masks
 * @{
 */

/*! @name MCR - Module Configuration Register */
/*! @{ */

#define CAN_MCR_MAXMB_MASK                       (0x7FU)
#define CAN_MCR_MAXMB_SHIFT                      (0U)
/*! MAXMB - Number Of The Last Message Buffer
 */
#define CAN_MCR_MAXMB(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)

#define CAN_MCR_IDAM_MASK                        (0x300U)
#define CAN_MCR_IDAM_SHIFT                       (8U)
/*! IDAM - ID Acceptance Mode
 *  0b00..Format A: One full ID (standard and extended) per ID filter table element.
 *  0b01..Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID filter table element.
 *  0b10..Format C: Four partial 8-bit standard IDs per ID filter table element.
 *  0b11..Format D: All frames rejected.
 */
#define CAN_MCR_IDAM(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)

#define CAN_MCR_FDEN_MASK                        (0x800U)
#define CAN_MCR_FDEN_SHIFT                       (11U)
/*! FDEN - CAN FD operation enable
 *  0b1..CAN FD is enabled. FlexCAN is able to receive and transmit messages in both CAN FD and CAN 2.0 formats.
 *  0b0..CAN FD is disabled. FlexCAN is able to receive and transmit messages in CAN 2.0 format.
 */
#define CAN_MCR_FDEN(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FDEN_SHIFT)) & CAN_MCR_FDEN_MASK)

#define CAN_MCR_AEN_MASK                         (0x1000U)
#define CAN_MCR_AEN_SHIFT                        (12U)
/*! AEN - Abort Enable
 *  0b0..Abort disabled.
 *  0b1..Abort enabled.
 */
#define CAN_MCR_AEN(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)

#define CAN_MCR_LPRIOEN_MASK                     (0x2000U)
#define CAN_MCR_LPRIOEN_SHIFT                    (13U)
/*! LPRIOEN - Local Priority Enable
 *  0b0..Local Priority disabled.
 *  0b1..Local Priority enabled.
 */
#define CAN_MCR_LPRIOEN(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)

#define CAN_MCR_PNET_EN_MASK                     (0x4000U)
#define CAN_MCR_PNET_EN_SHIFT                    (14U)
/*! PNET_EN - Pretended Networking Enable
 *  0b0..Pretended Networking mode is disabled.
 *  0b1..Pretended Networking mode is enabled.
 */
#define CAN_MCR_PNET_EN(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_MCR_PNET_EN_SHIFT)) & CAN_MCR_PNET_EN_MASK)

#define CAN_MCR_DMA_MASK                         (0x8000U)
#define CAN_MCR_DMA_SHIFT                        (15U)
/*! DMA - DMA Enable
 *  0b0..DMA feature for Legacy RX FIFO or Enhanced Rx FIFO disabled.
 *  0b1..DMA feature for Legacy RX FIFO or Enhanced Rx FIFO enabled.
 */
#define CAN_MCR_DMA(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DMA_SHIFT)) & CAN_MCR_DMA_MASK)

#define CAN_MCR_IRMQ_MASK                        (0x10000U)
#define CAN_MCR_IRMQ_SHIFT                       (16U)
/*! IRMQ - Individual Rx Masking And Queue Enable
 *  0b0..Individual Rx masking and queue feature are disabled. For backward compatibility with legacy
 *       applications, the reading of C/S word locks the MB even if it is EMPTY.
 *  0b1..Individual Rx masking and queue feature are enabled.
 */
#define CAN_MCR_IRMQ(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)

#define CAN_MCR_SRXDIS_MASK                      (0x20000U)
#define CAN_MCR_SRXDIS_SHIFT                     (17U)
/*! SRXDIS - Self Reception Disable
 *  0b0..Self-reception enabled.
 *  0b1..Self-reception disabled.
 */
#define CAN_MCR_SRXDIS(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)

#define CAN_MCR_DOZE_MASK                        (0x40000U)
#define CAN_MCR_DOZE_SHIFT                       (18U)
/*! DOZE - Doze Mode Enable
 *  0b0..FlexCAN is not enabled to enter low-power mode when Doze mode is requested.
 *  0b1..FlexCAN is enabled to enter low-power mode when Doze mode is requested.
 */
#define CAN_MCR_DOZE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DOZE_SHIFT)) & CAN_MCR_DOZE_MASK)

#define CAN_MCR_WAKSRC_MASK                      (0x80000U)
#define CAN_MCR_WAKSRC_SHIFT                     (19U)
/*! WAKSRC - Wake Up Source
 *  0b0..FlexCAN uses the unfiltered Rx input to detect recessive to dominant edges on the CAN bus.
 *  0b1..FlexCAN uses the filtered Rx input to detect recessive to dominant edges on the CAN bus.
 */
#define CAN_MCR_WAKSRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)

#define CAN_MCR_LPMACK_MASK                      (0x100000U)
#define CAN_MCR_LPMACK_SHIFT                     (20U)
/*! LPMACK - Low-Power Mode Acknowledge
 *  0b0..FlexCAN is not in a low-power mode.
 *  0b1..FlexCAN is in a low-power mode.
 */
#define CAN_MCR_LPMACK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)

#define CAN_MCR_WRNEN_MASK                       (0x200000U)
#define CAN_MCR_WRNEN_SHIFT                      (21U)
/*! WRNEN - Warning Interrupt Enable
 *  0b0..TWRNINT and RWRNINT bits are zero, independent of the values in the error counters.
 *  0b1..TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96.
 */
#define CAN_MCR_WRNEN(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)

#define CAN_MCR_SLFWAK_MASK                      (0x400000U)
#define CAN_MCR_SLFWAK_SHIFT                     (22U)
/*! SLFWAK - Self Wake Up
 *  0b0..FlexCAN Self Wake Up feature is disabled.
 *  0b1..FlexCAN Self Wake Up feature is enabled.
 */
#define CAN_MCR_SLFWAK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)

#define CAN_MCR_FRZACK_MASK                      (0x1000000U)
#define CAN_MCR_FRZACK_SHIFT                     (24U)
/*! FRZACK - Freeze Mode Acknowledge
 *  0b0..FlexCAN not in Freeze mode, prescaler running.
 *  0b1..FlexCAN in Freeze mode, prescaler stopped.
 */
#define CAN_MCR_FRZACK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)

#define CAN_MCR_SOFTRST_MASK                     (0x2000000U)
#define CAN_MCR_SOFTRST_SHIFT                    (25U)
/*! SOFTRST - Soft Reset
 *  0b0..No reset request.
 *  0b1..Resets the registers affected by soft reset.
 */
#define CAN_MCR_SOFTRST(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)

#define CAN_MCR_WAKMSK_MASK                      (0x4000000U)
#define CAN_MCR_WAKMSK_SHIFT                     (26U)
/*! WAKMSK - Wake Up Interrupt Mask
 *  0b0..Wake Up interrupt is disabled.
 *  0b1..Wake Up interrupt is enabled.
 */
#define CAN_MCR_WAKMSK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)

#define CAN_MCR_NOTRDY_MASK                      (0x8000000U)
#define CAN_MCR_NOTRDY_SHIFT                     (27U)
/*! NOTRDY - FlexCAN Not Ready
 *  0b0..FlexCAN module is either in Normal mode, Listen-Only mode, or Loop-Back mode.
 *  0b1..FlexCAN module is either in Disable mode, Doze mode, Stop mode, or Freeze mode.
 */
#define CAN_MCR_NOTRDY(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)

#define CAN_MCR_HALT_MASK                        (0x10000000U)
#define CAN_MCR_HALT_SHIFT                       (28U)
/*! HALT - Halt FlexCAN
 *  0b0..No Freeze mode request.
 *  0b1..Enters Freeze mode if the FRZ bit is asserted.
 */
#define CAN_MCR_HALT(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)

#define CAN_MCR_RFEN_MASK                        (0x20000000U)
#define CAN_MCR_RFEN_SHIFT                       (29U)
/*! RFEN - Legacy Rx FIFO Enable
 *  0b0..Legacy Rx FIFO not enabled.
 *  0b1..Legacy Rx FIFO enabled.
 */
#define CAN_MCR_RFEN(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)

#define CAN_MCR_FRZ_MASK                         (0x40000000U)
#define CAN_MCR_FRZ_SHIFT                        (30U)
/*! FRZ - Freeze Enable
 *  0b0..Not enabled to enter Freeze mode.
 *  0b1..Enabled to enter Freeze mode.
 */
#define CAN_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)

#define CAN_MCR_MDIS_MASK                        (0x80000000U)
#define CAN_MCR_MDIS_SHIFT                       (31U)
/*! MDIS - Module Disable
 *  0b0..Enable the FlexCAN module.
 *  0b1..Disable the FlexCAN module.
 */
#define CAN_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
/*! @} */

/*! @name CTRL1 - Control 1 Register */
/*! @{ */

#define CAN_CTRL1_PROPSEG_MASK                   (0x7U)
#define CAN_CTRL1_PROPSEG_SHIFT                  (0U)
/*! PROPSEG - Propagation Segment
 */
#define CAN_CTRL1_PROPSEG(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)

#define CAN_CTRL1_LOM_MASK                       (0x8U)
#define CAN_CTRL1_LOM_SHIFT                      (3U)
/*! LOM - Listen-Only Mode
 *  0b0..Listen-Only mode is deactivated.
 *  0b1..FlexCAN module operates in Listen-Only mode.
 */
#define CAN_CTRL1_LOM(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)

#define CAN_CTRL1_LBUF_MASK                      (0x10U)
#define CAN_CTRL1_LBUF_SHIFT                     (4U)
/*! LBUF - Lowest Buffer Transmitted First
 *  0b0..Buffer with highest priority is transmitted first.
 *  0b1..Lowest number buffer is transmitted first.
 */
#define CAN_CTRL1_LBUF(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)

#define CAN_CTRL1_TSYN_MASK                      (0x20U)
#define CAN_CTRL1_TSYN_SHIFT                     (5U)
/*! TSYN - Timer Sync
 *  0b0..Timer sync feature disabled
 *  0b1..Timer sync feature enabled
 */
#define CAN_CTRL1_TSYN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)

#define CAN_CTRL1_BOFFREC_MASK                   (0x40U)
#define CAN_CTRL1_BOFFREC_SHIFT                  (6U)
/*! BOFFREC - Bus Off Recovery
 *  0b0..Automatic recovering from Bus Off state enabled.
 *  0b1..Automatic recovering from Bus Off state disabled.
 */
#define CAN_CTRL1_BOFFREC(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)

#define CAN_CTRL1_SMP_MASK                       (0x80U)
#define CAN_CTRL1_SMP_SHIFT                      (7U)
/*! SMP - CAN Bit Sampling
 *  0b0..Just one sample is used to determine the bit value.
 *  0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and two
 *       preceding samples; a majority rule is used.
 */
#define CAN_CTRL1_SMP(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)

#define CAN_CTRL1_RWRNMSK_MASK                   (0x400U)
#define CAN_CTRL1_RWRNMSK_SHIFT                  (10U)
/*! RWRNMSK - Rx Warning Interrupt Mask
 *  0b0..Rx Warning interrupt disabled.
 *  0b1..Rx Warning interrupt enabled.
 */
#define CAN_CTRL1_RWRNMSK(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)

#define CAN_CTRL1_TWRNMSK_MASK                   (0x800U)
#define CAN_CTRL1_TWRNMSK_SHIFT                  (11U)
/*! TWRNMSK - Tx Warning Interrupt Mask
 *  0b0..Tx Warning interrupt disabled.
 *  0b1..Tx Warning interrupt enabled.
 */
#define CAN_CTRL1_TWRNMSK(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)

#define CAN_CTRL1_LPB_MASK                       (0x1000U)
#define CAN_CTRL1_LPB_SHIFT                      (12U)
/*! LPB - Loop Back Mode
 *  0b0..Loop Back disabled.
 *  0b1..Loop Back enabled.
 */
#define CAN_CTRL1_LPB(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)

#define CAN_CTRL1_ERRMSK_MASK                    (0x4000U)
#define CAN_CTRL1_ERRMSK_SHIFT                   (14U)
/*! ERRMSK - Error Interrupt Mask
 *  0b0..Error interrupt disabled.
 *  0b1..Error interrupt enabled.
 */
#define CAN_CTRL1_ERRMSK(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)

#define CAN_CTRL1_BOFFMSK_MASK                   (0x8000U)
#define CAN_CTRL1_BOFFMSK_SHIFT                  (15U)
/*! BOFFMSK - Bus Off Interrupt Mask
 *  0b0..Bus Off interrupt disabled.
 *  0b1..Bus Off interrupt enabled.
 */
#define CAN_CTRL1_BOFFMSK(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)

#define CAN_CTRL1_PSEG2_MASK                     (0x70000U)
#define CAN_CTRL1_PSEG2_SHIFT                    (16U)
/*! PSEG2 - Phase Segment 2
 */
#define CAN_CTRL1_PSEG2(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)

#define CAN_CTRL1_PSEG1_MASK                     (0x380000U)
#define CAN_CTRL1_PSEG1_SHIFT                    (19U)
/*! PSEG1 - Phase Segment 1
 */
#define CAN_CTRL1_PSEG1(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)

#define CAN_CTRL1_RJW_MASK                       (0xC00000U)
#define CAN_CTRL1_RJW_SHIFT                      (22U)
/*! RJW - Resync Jump Width
 */
#define CAN_CTRL1_RJW(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)

#define CAN_CTRL1_PRESDIV_MASK                   (0xFF000000U)
#define CAN_CTRL1_PRESDIV_SHIFT                  (24U)
/*! PRESDIV - Prescaler Division Factor
 */
#define CAN_CTRL1_PRESDIV(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
/*! @} */

/*! @name TIMER - Free Running Timer */
/*! @{ */

#define CAN_TIMER_TIMER_MASK                     (0xFFFFU)
#define CAN_TIMER_TIMER_SHIFT                    (0U)
/*! TIMER - Timer Value
 */
#define CAN_TIMER_TIMER(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
/*! @} */

/*! @name RXMGMASK - Rx Mailboxes Global Mask Register */
/*! @{ */

#define CAN_RXMGMASK_MG_MASK                     (0xFFFFFFFFU)
#define CAN_RXMGMASK_MG_SHIFT                    (0U)
/*! MG - Rx Mailboxes Global Mask Bits
 */
#define CAN_RXMGMASK_MG(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
/*! @} */

/*! @name RX14MASK - Rx 14 Mask Register */
/*! @{ */

#define CAN_RX14MASK_RX14M_MASK                  (0xFFFFFFFFU)
#define CAN_RX14MASK_RX14M_SHIFT                 (0U)
/*! RX14M - Rx Buffer 14 Mask Bits
 */
#define CAN_RX14MASK_RX14M(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
/*! @} */

/*! @name RX15MASK - Rx 15 Mask Register */
/*! @{ */

#define CAN_RX15MASK_RX15M_MASK                  (0xFFFFFFFFU)
#define CAN_RX15MASK_RX15M_SHIFT                 (0U)
/*! RX15M - Rx Buffer 15 Mask Bits
 */
#define CAN_RX15MASK_RX15M(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
/*! @} */

/*! @name ECR - Error Counter */
/*! @{ */

#define CAN_ECR_TXERRCNT_MASK                    (0xFFU)
#define CAN_ECR_TXERRCNT_SHIFT                   (0U)
/*! TXERRCNT - Transmit Error Counter
 */
#define CAN_ECR_TXERRCNT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK)

#define CAN_ECR_RXERRCNT_MASK                    (0xFF00U)
#define CAN_ECR_RXERRCNT_SHIFT                   (8U)
/*! RXERRCNT - Receive Error Counter
 */
#define CAN_ECR_RXERRCNT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK)

#define CAN_ECR_TXERRCNT_FAST_MASK               (0xFF0000U)
#define CAN_ECR_TXERRCNT_FAST_SHIFT              (16U)
/*! TXERRCNT_FAST - Transmit Error Counter for fast bits
 */
#define CAN_ECR_TXERRCNT_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_FAST_SHIFT)) & CAN_ECR_TXERRCNT_FAST_MASK)

#define CAN_ECR_RXERRCNT_FAST_MASK               (0xFF000000U)
#define CAN_ECR_RXERRCNT_FAST_SHIFT              (24U)
/*! RXERRCNT_FAST - Receive Error Counter for fast bits
 */
#define CAN_ECR_RXERRCNT_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_FAST_SHIFT)) & CAN_ECR_RXERRCNT_FAST_MASK)
/*! @} */

/*! @name ESR1 - Error and Status 1 Register */
/*! @{ */

#define CAN_ESR1_WAKINT_MASK                     (0x1U)
#define CAN_ESR1_WAKINT_SHIFT                    (0U)
/*! WAKINT - Wake-Up Interrupt
 *  0b0..No such occurrence.
 *  0b1..Indicates a recessive to dominant transition was received on the CAN bus.
 */
#define CAN_ESR1_WAKINT(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)

#define CAN_ESR1_ERRINT_MASK                     (0x2U)
#define CAN_ESR1_ERRINT_SHIFT                    (1U)
/*! ERRINT - Error Interrupt
 *  0b0..No such occurrence.
 *  0b1..Indicates setting of any error bit in the Error and Status register.
 */
#define CAN_ESR1_ERRINT(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)

#define CAN_ESR1_BOFFINT_MASK                    (0x4U)
#define CAN_ESR1_BOFFINT_SHIFT                   (2U)
/*! BOFFINT - Bus Off Interrupt
 *  0b0..No such occurrence.
 *  0b1..FlexCAN module entered Bus Off state.
 */
#define CAN_ESR1_BOFFINT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)

#define CAN_ESR1_RX_MASK                         (0x8U)
#define CAN_ESR1_RX_SHIFT                        (3U)
/*! RX - FlexCAN In Reception
 *  0b0..FlexCAN is not receiving a message.
 *  0b1..FlexCAN is receiving a message.
 */
#define CAN_ESR1_RX(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)

#define CAN_ESR1_FLTCONF_MASK                    (0x30U)
#define CAN_ESR1_FLTCONF_SHIFT                   (4U)
/*! FLTCONF - Fault Confinement State
 *  0b00..Error Active
 *  0b01..Error Passive
 *  0b1x..Bus Off
 */
#define CAN_ESR1_FLTCONF(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)

#define CAN_ESR1_TX_MASK                         (0x40U)
#define CAN_ESR1_TX_SHIFT                        (6U)
/*! TX - FlexCAN In Transmission
 *  0b0..FlexCAN is not transmitting a message.
 *  0b1..FlexCAN is transmitting a message.
 */
#define CAN_ESR1_TX(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)

#define CAN_ESR1_IDLE_MASK                       (0x80U)
#define CAN_ESR1_IDLE_SHIFT                      (7U)
/*! IDLE - IDLE
 *  0b0..No such occurrence.
 *  0b1..CAN bus is now IDLE.
 */
#define CAN_ESR1_IDLE(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)

#define CAN_ESR1_RXWRN_MASK                      (0x100U)
#define CAN_ESR1_RXWRN_SHIFT                     (8U)
/*! RXWRN - Rx Error Warning
 *  0b0..No such occurrence.
 *  0b1..RXERRCNT is greater than or equal to 96.
 */
#define CAN_ESR1_RXWRN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)

#define CAN_ESR1_TXWRN_MASK                      (0x200U)
#define CAN_ESR1_TXWRN_SHIFT                     (9U)
/*! TXWRN - TX Error Warning
 *  0b0..No such occurrence.
 *  0b1..TXERRCNT is greater than or equal to 96.
 */
#define CAN_ESR1_TXWRN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)

#define CAN_ESR1_STFERR_MASK                     (0x400U)
#define CAN_ESR1_STFERR_SHIFT                    (10U)
/*! STFERR - Stuffing Error
 *  0b0..No such occurrence.
 *  0b1..A stuffing error occurred since last read of this register.
 */
#define CAN_ESR1_STFERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)

#define CAN_ESR1_FRMERR_MASK                     (0x800U)
#define CAN_ESR1_FRMERR_SHIFT                    (11U)
/*! FRMERR - Form Error
 *  0b0..No such occurrence.
 *  0b1..A Form Error occurred since last read of this register.
 */
#define CAN_ESR1_FRMERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)

#define CAN_ESR1_CRCERR_MASK                     (0x1000U)
#define CAN_ESR1_CRCERR_SHIFT                    (12U)
/*! CRCERR - Cyclic Redundancy Check Error
 *  0b0..No such occurrence.
 *  0b1..A CRC error occurred since last read of this register.
 */
#define CAN_ESR1_CRCERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)

#define CAN_ESR1_ACKERR_MASK                     (0x2000U)
#define CAN_ESR1_ACKERR_SHIFT                    (13U)
/*! ACKERR - Acknowledge Error
 *  0b0..No such occurrence.
 *  0b1..An ACK error occurred since last read of this register.
 */
#define CAN_ESR1_ACKERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)

#define CAN_ESR1_BIT0ERR_MASK                    (0x4000U)
#define CAN_ESR1_BIT0ERR_SHIFT                   (14U)
/*! BIT0ERR - Bit0 Error
 *  0b0..No such occurrence.
 *  0b1..At least one bit sent as dominant is received as recessive.
 */
#define CAN_ESR1_BIT0ERR(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)

#define CAN_ESR1_BIT1ERR_MASK                    (0x8000U)
#define CAN_ESR1_BIT1ERR_SHIFT                   (15U)
/*! BIT1ERR - Bit1 Error
 *  0b0..No such occurrence.
 *  0b1..At least one bit sent as recessive is received as dominant.
 */
#define CAN_ESR1_BIT1ERR(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)

#define CAN_ESR1_RWRNINT_MASK                    (0x10000U)
#define CAN_ESR1_RWRNINT_SHIFT                   (16U)
/*! RWRNINT - Rx Warning Interrupt Flag
 *  0b0..No such occurrence.
 *  0b1..The Rx error counter transitioned from less than 96 to greater than or equal to 96.
 */
#define CAN_ESR1_RWRNINT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)

#define CAN_ESR1_TWRNINT_MASK                    (0x20000U)
#define CAN_ESR1_TWRNINT_SHIFT                   (17U)
/*! TWRNINT - Tx Warning Interrupt Flag
 *  0b0..No such occurrence.
 *  0b1..The Tx error counter transitioned from less than 96 to greater than or equal to 96.
 */
#define CAN_ESR1_TWRNINT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)

#define CAN_ESR1_SYNCH_MASK                      (0x40000U)
#define CAN_ESR1_SYNCH_SHIFT                     (18U)
/*! SYNCH - CAN Synchronization Status
 *  0b0..FlexCAN is not synchronized to the CAN bus.
 *  0b1..FlexCAN is synchronized to the CAN bus.
 */
#define CAN_ESR1_SYNCH(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)

#define CAN_ESR1_BOFFDONEINT_MASK                (0x80000U)
#define CAN_ESR1_BOFFDONEINT_SHIFT               (19U)
/*! BOFFDONEINT - Bus Off Done Interrupt
 *  0b0..No such occurrence.
 *  0b1..FlexCAN module has completed Bus Off process.
 */
#define CAN_ESR1_BOFFDONEINT(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFDONEINT_SHIFT)) & CAN_ESR1_BOFFDONEINT_MASK)

#define CAN_ESR1_ERRINT_FAST_MASK                (0x100000U)
#define CAN_ESR1_ERRINT_FAST_SHIFT               (20U)
/*! ERRINT_FAST - Error interrupt for errors detected in Data Phase of CAN FD frames with BRS bit set
 *  0b0..No such occurrence.
 *  0b1..Indicates setting of any error bit detected in the data phase of CAN FD frames with the BRS bit set.
 */
#define CAN_ESR1_ERRINT_FAST(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_FAST_SHIFT)) & CAN_ESR1_ERRINT_FAST_MASK)

#define CAN_ESR1_ERROVR_MASK                     (0x200000U)
#define CAN_ESR1_ERROVR_SHIFT                    (21U)
/*! ERROVR - Error Overrun
 *  0b0..Overrun has not occurred.
 *  0b1..Overrun has occurred.
 */
#define CAN_ESR1_ERROVR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERROVR_SHIFT)) & CAN_ESR1_ERROVR_MASK)

#define CAN_ESR1_STFERR_FAST_MASK                (0x4000000U)
#define CAN_ESR1_STFERR_FAST_SHIFT               (26U)
/*! STFERR_FAST - Stuffing Error in the Data Phase of CAN FD frames with the BRS bit set
 *  0b0..No such occurrence.
 *  0b1..A stuffing error occurred since last read of this register.
 */
#define CAN_ESR1_STFERR_FAST(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_FAST_SHIFT)) & CAN_ESR1_STFERR_FAST_MASK)

#define CAN_ESR1_FRMERR_FAST_MASK                (0x8000000U)
#define CAN_ESR1_FRMERR_FAST_SHIFT               (27U)
/*! FRMERR_FAST - Form Error in the Data Phase of CAN FD frames with the BRS bit set
 *  0b0..No such occurrence.
 *  0b1..A form error occurred since last read of this register.
 */
#define CAN_ESR1_FRMERR_FAST(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_FAST_SHIFT)) & CAN_ESR1_FRMERR_FAST_MASK)

#define CAN_ESR1_CRCERR_FAST_MASK                (0x10000000U)
#define CAN_ESR1_CRCERR_FAST_SHIFT               (28U)
/*! CRCERR_FAST - Cyclic Redundancy Check Error in the CRC field of CAN FD frames with the BRS bit set
 *  0b0..No such occurrence.
 *  0b1..A CRC error occurred since last read of this register.
 */
#define CAN_ESR1_CRCERR_FAST(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_FAST_SHIFT)) & CAN_ESR1_CRCERR_FAST_MASK)

#define CAN_ESR1_BIT0ERR_FAST_MASK               (0x40000000U)
#define CAN_ESR1_BIT0ERR_FAST_SHIFT              (30U)
/*! BIT0ERR_FAST - Bit0 Error in the Data Phase of CAN FD frames with the BRS bit set
 *  0b0..No such occurrence.
 *  0b1..At least one bit sent as dominant is received as recessive.
 */
#define CAN_ESR1_BIT0ERR_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_FAST_SHIFT)) & CAN_ESR1_BIT0ERR_FAST_MASK)

#define CAN_ESR1_BIT1ERR_FAST_MASK               (0x80000000U)
#define CAN_ESR1_BIT1ERR_FAST_SHIFT              (31U)
/*! BIT1ERR_FAST - Bit1 Error in the Data Phase of CAN FD frames with the BRS bit set
 *  0b0..No such occurrence.
 *  0b1..At least one bit sent as recessive is received as dominant.
 */
#define CAN_ESR1_BIT1ERR_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_FAST_SHIFT)) & CAN_ESR1_BIT1ERR_FAST_MASK)
/*! @} */

/*! @name IMASK1 - Interrupt Masks 1 Register */
/*! @{ */

#define CAN_IMASK1_BUF31TO0M_MASK                (0xFFFFFFFFU)
#define CAN_IMASK1_BUF31TO0M_SHIFT               (0U)
/*! BUF31TO0M - Buffer MBi Mask
 */
#define CAN_IMASK1_BUF31TO0M(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUF31TO0M_SHIFT)) & CAN_IMASK1_BUF31TO0M_MASK)
/*! @} */

/*! @name IFLAG1 - Interrupt Flags 1 Register */
/*! @{ */

#define CAN_IFLAG1_BUF0I_MASK                    (0x1U)
#define CAN_IFLAG1_BUF0I_SHIFT                   (0U)
/*! BUF0I - Buffer MB0 Interrupt Or Clear Legacy FIFO bit
 *  0b0..The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0.
 *  0b1..The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0.
 */
#define CAN_IFLAG1_BUF0I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK)

#define CAN_IFLAG1_BUF4TO1I_MASK                 (0x1EU)
#define CAN_IFLAG1_BUF4TO1I_SHIFT                (1U)
/*! BUF4TO1I - Buffer MBi Interrupt Or Reserved
 */
#define CAN_IFLAG1_BUF4TO1I(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK)

#define CAN_IFLAG1_BUF5I_MASK                    (0x20U)
#define CAN_IFLAG1_BUF5I_SHIFT                   (5U)
/*! BUF5I - Buffer MB5 Interrupt Or Frames available in Legacy Rx FIFO
 *  0b0..No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the Legacy FIFO, when MCR[RFEN]=1
 *  0b1..MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Legacy Rx FIFO when
 *       MCR[RFEN]=1. It generates a DMA request in case of MCR[RFEN] and MCR[DMA] are enabled.
 */
#define CAN_IFLAG1_BUF5I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)

#define CAN_IFLAG1_BUF6I_MASK                    (0x40U)
#define CAN_IFLAG1_BUF6I_SHIFT                   (6U)
/*! BUF6I - Buffer MB6 Interrupt Or Legacy Rx FIFO Warning
 *  0b0..No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Legacy Rx FIFO almost full when MCR[RFEN]=1
 *  0b1..MB6 completed transmission/reception when MCR[RFEN]=0, or Legacy Rx FIFO almost full when MCR[RFEN]=1
 */
#define CAN_IFLAG1_BUF6I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)

#define CAN_IFLAG1_BUF7I_MASK                    (0x80U)
#define CAN_IFLAG1_BUF7I_SHIFT                   (7U)
/*! BUF7I - Buffer MB7 Interrupt Or Legacy Rx FIFO Overflow
 *  0b0..No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Legacy Rx FIFO overflow when MCR[RFEN]=1
 *  0b1..MB7 completed transmission/reception when MCR[RFEN]=0, or Legacy Rx FIFO overflow when MCR[RFEN]=1
 */
#define CAN_IFLAG1_BUF7I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)

#define CAN_IFLAG1_BUF31TO8I_MASK                (0xFFFFFF00U)
#define CAN_IFLAG1_BUF31TO8I_SHIFT               (8U)
/*! BUF31TO8I - Buffer MBi Interrupt
 */
#define CAN_IFLAG1_BUF31TO8I(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
/*! @} */

/*! @name CTRL2 - Control 2 Register */
/*! @{ */

#define CAN_CTRL2_EDFLTDIS_MASK                  (0x800U)
#define CAN_CTRL2_EDFLTDIS_SHIFT                 (11U)
/*! EDFLTDIS - Edge Filter Disable
 *  0b0..Edge filter is enabled
 *  0b1..Edge filter is disabled
 */
#define CAN_CTRL2_EDFLTDIS(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EDFLTDIS_SHIFT)) & CAN_CTRL2_EDFLTDIS_MASK)

#define CAN_CTRL2_ISOCANFDEN_MASK                (0x1000U)
#define CAN_CTRL2_ISOCANFDEN_SHIFT               (12U)
/*! ISOCANFDEN - ISO CAN FD Enable
 *  0b0..FlexCAN operates using the non-ISO CAN FD protocol.
 *  0b1..FlexCAN operates using the ISO CAN FD protocol (ISO 11898-1:2015).
 */
#define CAN_CTRL2_ISOCANFDEN(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ISOCANFDEN_SHIFT)) & CAN_CTRL2_ISOCANFDEN_MASK)

#define CAN_CTRL2_BTE_MASK                       (0x2000U)
#define CAN_CTRL2_BTE_SHIFT                      (13U)
/*! BTE - Bit Timing Expansion enable
 *  0b0..CAN Bit timing expansion is disabled.
 *  0b1..CAN bit timing expansion is enabled.
 */
#define CAN_CTRL2_BTE(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BTE_SHIFT)) & CAN_CTRL2_BTE_MASK)

#define CAN_CTRL2_PREXCEN_MASK                   (0x4000U)
#define CAN_CTRL2_PREXCEN_SHIFT                  (14U)
/*! PREXCEN - Protocol Exception Enable
 *  0b0..Protocol exception is disabled.
 *  0b1..Protocol exception is enabled.
 */
#define CAN_CTRL2_PREXCEN(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PREXCEN_SHIFT)) & CAN_CTRL2_PREXCEN_MASK)

#define CAN_CTRL2_EACEN_MASK                     (0x10000U)
#define CAN_CTRL2_EACEN_SHIFT                    (16U)
/*! EACEN - Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes
 *  0b0..Rx mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits.
 *  0b1..Enables the comparison of both Rx mailbox filter's IDE and RTR bit with their corresponding bits within
 *       the incoming frame. Mask bits do apply.
 */
#define CAN_CTRL2_EACEN(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)

#define CAN_CTRL2_RRS_MASK                       (0x20000U)
#define CAN_CTRL2_RRS_SHIFT                      (17U)
/*! RRS - Remote Request Storing
 *  0b0..Remote response frame is generated.
 *  0b1..Remote request frame is stored.
 */
#define CAN_CTRL2_RRS(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)

#define CAN_CTRL2_MRP_MASK                       (0x40000U)
#define CAN_CTRL2_MRP_SHIFT                      (18U)
/*! MRP - Mailboxes Reception Priority
 *  0b0..Matching starts from Legacy Rx FIFO or Enhanced Rx FIFO and continues on mailboxes.
 *  0b1..Matching starts from mailboxes and continues on Legacy Rx FIFO or Enhanced Rx FIFO.
 */
#define CAN_CTRL2_MRP(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)

#define CAN_CTRL2_TASD_MASK                      (0xF80000U)
#define CAN_CTRL2_TASD_SHIFT                     (19U)
/*! TASD - Tx Arbitration Start Delay
 */
#define CAN_CTRL2_TASD(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)

#define CAN_CTRL2_RFFN_MASK                      (0xF000000U)
#define CAN_CTRL2_RFFN_SHIFT                     (24U)
/*! RFFN - Number Of Legacy Rx FIFO Filters
 */
#define CAN_CTRL2_RFFN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)

#define CAN_CTRL2_BOFFDONEMSK_MASK               (0x40000000U)
#define CAN_CTRL2_BOFFDONEMSK_SHIFT              (30U)
/*! BOFFDONEMSK - Bus Off Done Interrupt Mask
 *  0b0..Bus off done interrupt disabled.
 *  0b1..Bus off done interrupt enabled.
 */
#define CAN_CTRL2_BOFFDONEMSK(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BOFFDONEMSK_SHIFT)) & CAN_CTRL2_BOFFDONEMSK_MASK)

#define CAN_CTRL2_ERRMSK_FAST_MASK               (0x80000000U)
#define CAN_CTRL2_ERRMSK_FAST_SHIFT              (31U)
/*! ERRMSK_FAST - Error Interrupt Mask for errors detected in the data phase of fast CAN FD frames
 *  0b0..ERRINT_FAST error interrupt disabled.
 *  0b1..ERRINT_FAST error interrupt enabled.
 */
#define CAN_CTRL2_ERRMSK_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ERRMSK_FAST_SHIFT)) & CAN_CTRL2_ERRMSK_FAST_MASK)
/*! @} */

/*! @name ESR2 - Error and Status 2 Register */
/*! @{ */

#define CAN_ESR2_IMB_MASK                        (0x2000U)
#define CAN_ESR2_IMB_SHIFT                       (13U)
/*! IMB - Inactive Mailbox
 *  0b0..If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive mailbox.
 *  0b1..If ESR2[VPS] is asserted, there is at least one inactive mailbox. LPTM content is the number of the first one.
 */
#define CAN_ESR2_IMB(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)

#define CAN_ESR2_VPS_MASK                        (0x4000U)
#define CAN_ESR2_VPS_SHIFT                       (14U)
/*! VPS - Valid Priority Status
 *  0b0..Contents of IMB and LPTM are invalid.
 *  0b1..Contents of IMB and LPTM are valid.
 */
#define CAN_ESR2_VPS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)

#define CAN_ESR2_LPTM_MASK                       (0x7F0000U)
#define CAN_ESR2_LPTM_SHIFT                      (16U)
/*! LPTM - Lowest Priority Tx Mailbox
 */
#define CAN_ESR2_LPTM(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
/*! @} */

/*! @name CRCR - CRC Register */
/*! @{ */

#define CAN_CRCR_TXCRC_MASK                      (0x7FFFU)
#define CAN_CRCR_TXCRC_SHIFT                     (0U)
/*! TXCRC - Transmitted CRC value
 */
#define CAN_CRCR_TXCRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)

#define CAN_CRCR_MBCRC_MASK                      (0x7F0000U)
#define CAN_CRCR_MBCRC_SHIFT                     (16U)
/*! MBCRC - CRC Mailbox
 */
#define CAN_CRCR_MBCRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
/*! @} */

/*! @name RXFGMASK - Legacy Rx FIFO Global Mask Register */
/*! @{ */

#define CAN_RXFGMASK_FGM_MASK                    (0xFFFFFFFFU)
#define CAN_RXFGMASK_FGM_SHIFT                   (0U)
/*! FGM - Legacy Rx FIFO Global Mask Bits
 */
#define CAN_RXFGMASK_FGM(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
/*! @} */

/*! @name RXFIR - Legacy Rx FIFO Information Register */
/*! @{ */

#define CAN_RXFIR_IDHIT_MASK                     (0x1FFU)
#define CAN_RXFIR_IDHIT_SHIFT                    (0U)
/*! IDHIT - Identifier Acceptance Filter Hit Indicator
 */
#define CAN_RXFIR_IDHIT(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
/*! @} */

/*! @name CBT - CAN Bit Timing Register */
/*! @{ */

#define CAN_CBT_EPSEG2_MASK                      (0x1FU)
#define CAN_CBT_EPSEG2_SHIFT                     (0U)
/*! EPSEG2 - Extended Phase Segment 2
 */
#define CAN_CBT_EPSEG2(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG2_SHIFT)) & CAN_CBT_EPSEG2_MASK)

#define CAN_CBT_EPSEG1_MASK                      (0x3E0U)
#define CAN_CBT_EPSEG1_SHIFT                     (5U)
/*! EPSEG1 - Extended Phase Segment 1
 */
#define CAN_CBT_EPSEG1(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG1_SHIFT)) & CAN_CBT_EPSEG1_MASK)

#define CAN_CBT_EPROPSEG_MASK                    (0xFC00U)
#define CAN_CBT_EPROPSEG_SHIFT                   (10U)
/*! EPROPSEG - Extended Propagation Segment
 */
#define CAN_CBT_EPROPSEG(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPROPSEG_SHIFT)) & CAN_CBT_EPROPSEG_MASK)

#define CAN_CBT_ERJW_MASK                        (0x1F0000U)
#define CAN_CBT_ERJW_SHIFT                       (16U)
/*! ERJW - Extended Resync Jump Width
 */
#define CAN_CBT_ERJW(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CBT_ERJW_SHIFT)) & CAN_CBT_ERJW_MASK)

#define CAN_CBT_EPRESDIV_MASK                    (0x7FE00000U)
#define CAN_CBT_EPRESDIV_SHIFT                   (21U)
/*! EPRESDIV - Extended Prescaler Division Factor
 */
#define CAN_CBT_EPRESDIV(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPRESDIV_SHIFT)) & CAN_CBT_EPRESDIV_MASK)

#define CAN_CBT_BTF_MASK                         (0x80000000U)
#define CAN_CBT_BTF_SHIFT                        (31U)
/*! BTF - Bit Timing Format Enable
 *  0b0..Extended bit time definitions disabled.
 *  0b1..Extended bit time definitions enabled.
 */
#define CAN_CBT_BTF(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_CBT_BTF_SHIFT)) & CAN_CBT_BTF_MASK)
/*! @} */

/* The count of CAN_CS */
#define CAN_CS_COUNT_MB8B                        (32U)

/* The count of CAN_ID */
#define CAN_ID_COUNT_MB8B                        (32U)

/* The count of CAN_WORD */
#define CAN_WORD_COUNT_MB8B                      (32U)

/* The count of CAN_WORD */
#define CAN_WORD_COUNT_MB8B2                     (2U)

/* The count of CAN_CS */
#define CAN_CS_COUNT_MB16B                       (21U)

/* The count of CAN_ID */
#define CAN_ID_COUNT_MB16B                       (21U)

/* The count of CAN_WORD */
#define CAN_WORD_COUNT_MB16B                     (21U)

/* The count of CAN_WORD */
#define CAN_WORD_COUNT_MB16B2                    (4U)

/* The count of CAN_CS */
#define CAN_CS_COUNT_MB32B                       (12U)

/* The count of CAN_ID */
#define CAN_ID_COUNT_MB32B                       (12U)

/* The count of CAN_WORD */
#define CAN_WORD_COUNT_MB32B                     (12U)

/* The count of CAN_WORD */
#define CAN_WORD_COUNT_MB32B2                    (8U)

/*! @name CS - Message Buffer 0 CS Register..Message Buffer 6 CS Register */
/*! @{ */

#define CAN_CS_TIME_STAMP_MASK                   (0xFFFFU)
#define CAN_CS_TIME_STAMP_SHIFT                  (0U)
/*! TIME_STAMP - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running
 *    Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field
 *    appears on the CAN bus.
 */
#define CAN_CS_TIME_STAMP(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)

#define CAN_CS_DLC_MASK                          (0xF0000U)
#define CAN_CS_DLC_SHIFT                         (16U)
/*! DLC - Length of the data to be stored/transmitted.
 */
#define CAN_CS_DLC(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)

#define CAN_CS_RTR_MASK                          (0x100000U)
#define CAN_CS_RTR_SHIFT                         (20U)
/*! RTR - Remote Transmission Request. One/zero for remote/data frame.
 */
#define CAN_CS_RTR(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)

#define CAN_CS_IDE_MASK                          (0x200000U)
#define CAN_CS_IDE_SHIFT                         (21U)
/*! IDE - ID Extended. One/zero for extended/standard format frame.
 */
#define CAN_CS_IDE(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)

#define CAN_CS_SRR_MASK                          (0x400000U)
#define CAN_CS_SRR_SHIFT                         (22U)
/*! SRR - Substitute Remote Request. Contains a fixed recessive bit.
 */
#define CAN_CS_SRR(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)

#define CAN_CS_CODE_MASK                         (0xF000000U)
#define CAN_CS_CODE_SHIFT                        (24U)
/*! CODE - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by
 *    the FlexCAN module itself, as part of the message buffer matching and arbitration process.
 */
#define CAN_CS_CODE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)

#define CAN_CS_ESI_MASK                          (0x20000000U)
#define CAN_CS_ESI_SHIFT                         (29U)
/*! ESI - Error State Indicator. This bit indicates if the transmitting node is error active or error passive.
 */
#define CAN_CS_ESI(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK)

#define CAN_CS_BRS_MASK                          (0x40000000U)
#define CAN_CS_BRS_SHIFT                         (30U)
/*! BRS - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.
 */
#define CAN_CS_BRS(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK)

#define CAN_CS_EDL_MASK                          (0x80000000U)
#define CAN_CS_EDL_SHIFT                         (31U)
/*! EDL - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames.
 *    The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.
 */
#define CAN_CS_EDL(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK)
/*! @} */

/* The count of CAN_CS */
#define CAN_CS_COUNT_MB64B                       (7U)

/*! @name ID - Message Buffer 0 ID Register..Message Buffer 6 ID Register */
/*! @{ */

#define CAN_ID_EXT_MASK                          (0x3FFFFU)
#define CAN_ID_EXT_SHIFT                         (0U)
/*! EXT - Contains extended (LOW word) identifier of message buffer.
 */
#define CAN_ID_EXT(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)

#define CAN_ID_STD_MASK                          (0x1FFC0000U)
#define CAN_ID_STD_SHIFT                         (18U)
/*! STD - Contains standard/extended (HIGH word) identifier of message buffer.
 */
#define CAN_ID_STD(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)

#define CAN_ID_PRIO_MASK                         (0xE0000000U)
#define CAN_ID_PRIO_SHIFT                        (29U)
/*! PRIO - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only
 *    makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular
 *    ID to define the transmission priority.
 */
#define CAN_ID_PRIO(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
/*! @} */

/* The count of CAN_ID */
#define CAN_ID_COUNT_MB64B                       (7U)

/*! @name WORD - Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register */
/*! @{ */

#define CAN_WORD_DATA_BYTE_3_MASK                (0xFFU)
#define CAN_WORD_DATA_BYTE_3_SHIFT               (0U)
/*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_3(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_3_SHIFT)) & CAN_WORD_DATA_BYTE_3_MASK)

#define CAN_WORD_DATA_BYTE_7_MASK                (0xFFU)
#define CAN_WORD_DATA_BYTE_7_SHIFT               (0U)
/*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_7(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_7_SHIFT)) & CAN_WORD_DATA_BYTE_7_MASK)

#define CAN_WORD_DATA_BYTE_11_MASK               (0xFFU)
#define CAN_WORD_DATA_BYTE_11_SHIFT              (0U)
/*! DATA_BYTE_11 - Data byte 0 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_11(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_11_SHIFT)) & CAN_WORD_DATA_BYTE_11_MASK)

#define CAN_WORD_DATA_BYTE_15_MASK               (0xFFU)
#define CAN_WORD_DATA_BYTE_15_SHIFT              (0U)
/*! DATA_BYTE_15 - Data byte 0 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_15(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_15_SHIFT)) & CAN_WORD_DATA_BYTE_15_MASK)

#define CAN_WORD_DATA_BYTE_19_MASK               (0xFFU)
#define CAN_WORD_DATA_BYTE_19_SHIFT              (0U)
/*! DATA_BYTE_19 - Data byte 0 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_19(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_19_SHIFT)) & CAN_WORD_DATA_BYTE_19_MASK)

#define CAN_WORD_DATA_BYTE_23_MASK               (0xFFU)
#define CAN_WORD_DATA_BYTE_23_SHIFT              (0U)
/*! DATA_BYTE_23 - Data byte 0 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_23(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_23_SHIFT)) & CAN_WORD_DATA_BYTE_23_MASK)

#define CAN_WORD_DATA_BYTE_27_MASK               (0xFFU)
#define CAN_WORD_DATA_BYTE_27_SHIFT              (0U)
/*! DATA_BYTE_27 - Data byte 0 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_27(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_27_SHIFT)) & CAN_WORD_DATA_BYTE_27_MASK)

#define CAN_WORD_DATA_BYTE_31_MASK               (0xFFU)
#define CAN_WORD_DATA_BYTE_31_SHIFT              (0U)
/*! DATA_BYTE_31 - Data byte 0 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_31(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_31_SHIFT)) & CAN_WORD_DATA_BYTE_31_MASK)

#define CAN_WORD_DATA_BYTE_35_MASK               (0xFFU)
#define CAN_WORD_DATA_BYTE_35_SHIFT              (0U)
/*! DATA_BYTE_35 - Data byte 0 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_35(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_35_SHIFT)) & CAN_WORD_DATA_BYTE_35_MASK)

#define CAN_WORD_DATA_BYTE_39_MASK               (0xFFU)
#define CAN_WORD_DATA_BYTE_39_SHIFT              (0U)
/*! DATA_BYTE_39 - Data byte 0 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_39(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_39_SHIFT)) & CAN_WORD_DATA_BYTE_39_MASK)

#define CAN_WORD_DATA_BYTE_43_MASK               (0xFFU)
#define CAN_WORD_DATA_BYTE_43_SHIFT              (0U)
/*! DATA_BYTE_43 - Data byte 0 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_43(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_43_SHIFT)) & CAN_WORD_DATA_BYTE_43_MASK)

#define CAN_WORD_DATA_BYTE_47_MASK               (0xFFU)
#define CAN_WORD_DATA_BYTE_47_SHIFT              (0U)
/*! DATA_BYTE_47 - Data byte 0 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_47(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_47_SHIFT)) & CAN_WORD_DATA_BYTE_47_MASK)

#define CAN_WORD_DATA_BYTE_51_MASK               (0xFFU)
#define CAN_WORD_DATA_BYTE_51_SHIFT              (0U)
/*! DATA_BYTE_51 - Data byte 0 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_51(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_51_SHIFT)) & CAN_WORD_DATA_BYTE_51_MASK)

#define CAN_WORD_DATA_BYTE_55_MASK               (0xFFU)
#define CAN_WORD_DATA_BYTE_55_SHIFT              (0U)
/*! DATA_BYTE_55 - Data byte 0 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_55(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_55_SHIFT)) & CAN_WORD_DATA_BYTE_55_MASK)

#define CAN_WORD_DATA_BYTE_59_MASK               (0xFFU)
#define CAN_WORD_DATA_BYTE_59_SHIFT              (0U)
/*! DATA_BYTE_59 - Data byte 0 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_59(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_59_SHIFT)) & CAN_WORD_DATA_BYTE_59_MASK)

#define CAN_WORD_DATA_BYTE_63_MASK               (0xFFU)
#define CAN_WORD_DATA_BYTE_63_SHIFT              (0U)
/*! DATA_BYTE_63 - Data byte 0 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_63(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_63_SHIFT)) & CAN_WORD_DATA_BYTE_63_MASK)

#define CAN_WORD_DATA_BYTE_2_MASK                (0xFF00U)
#define CAN_WORD_DATA_BYTE_2_SHIFT               (8U)
/*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_2(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_2_SHIFT)) & CAN_WORD_DATA_BYTE_2_MASK)

#define CAN_WORD_DATA_BYTE_6_MASK                (0xFF00U)
#define CAN_WORD_DATA_BYTE_6_SHIFT               (8U)
/*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_6(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_6_SHIFT)) & CAN_WORD_DATA_BYTE_6_MASK)

#define CAN_WORD_DATA_BYTE_10_MASK               (0xFF00U)
#define CAN_WORD_DATA_BYTE_10_SHIFT              (8U)
/*! DATA_BYTE_10 - Data byte 1 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_10(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_10_SHIFT)) & CAN_WORD_DATA_BYTE_10_MASK)

#define CAN_WORD_DATA_BYTE_14_MASK               (0xFF00U)
#define CAN_WORD_DATA_BYTE_14_SHIFT              (8U)
/*! DATA_BYTE_14 - Data byte 1 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_14(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_14_SHIFT)) & CAN_WORD_DATA_BYTE_14_MASK)

#define CAN_WORD_DATA_BYTE_18_MASK               (0xFF00U)
#define CAN_WORD_DATA_BYTE_18_SHIFT              (8U)
/*! DATA_BYTE_18 - Data byte 1 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_18(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_18_SHIFT)) & CAN_WORD_DATA_BYTE_18_MASK)

#define CAN_WORD_DATA_BYTE_22_MASK               (0xFF00U)
#define CAN_WORD_DATA_BYTE_22_SHIFT              (8U)
/*! DATA_BYTE_22 - Data byte 1 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_22(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_22_SHIFT)) & CAN_WORD_DATA_BYTE_22_MASK)

#define CAN_WORD_DATA_BYTE_26_MASK               (0xFF00U)
#define CAN_WORD_DATA_BYTE_26_SHIFT              (8U)
/*! DATA_BYTE_26 - Data byte 1 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_26(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_26_SHIFT)) & CAN_WORD_DATA_BYTE_26_MASK)

#define CAN_WORD_DATA_BYTE_30_MASK               (0xFF00U)
#define CAN_WORD_DATA_BYTE_30_SHIFT              (8U)
/*! DATA_BYTE_30 - Data byte 1 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_30(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_30_SHIFT)) & CAN_WORD_DATA_BYTE_30_MASK)

#define CAN_WORD_DATA_BYTE_34_MASK               (0xFF00U)
#define CAN_WORD_DATA_BYTE_34_SHIFT              (8U)
/*! DATA_BYTE_34 - Data byte 1 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_34(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_34_SHIFT)) & CAN_WORD_DATA_BYTE_34_MASK)

#define CAN_WORD_DATA_BYTE_38_MASK               (0xFF00U)
#define CAN_WORD_DATA_BYTE_38_SHIFT              (8U)
/*! DATA_BYTE_38 - Data byte 1 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_38(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_38_SHIFT)) & CAN_WORD_DATA_BYTE_38_MASK)

#define CAN_WORD_DATA_BYTE_42_MASK               (0xFF00U)
#define CAN_WORD_DATA_BYTE_42_SHIFT              (8U)
/*! DATA_BYTE_42 - Data byte 1 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_42(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_42_SHIFT)) & CAN_WORD_DATA_BYTE_42_MASK)

#define CAN_WORD_DATA_BYTE_46_MASK               (0xFF00U)
#define CAN_WORD_DATA_BYTE_46_SHIFT              (8U)
/*! DATA_BYTE_46 - Data byte 1 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_46(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_46_SHIFT)) & CAN_WORD_DATA_BYTE_46_MASK)

#define CAN_WORD_DATA_BYTE_50_MASK               (0xFF00U)
#define CAN_WORD_DATA_BYTE_50_SHIFT              (8U)
/*! DATA_BYTE_50 - Data byte 1 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_50(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_50_SHIFT)) & CAN_WORD_DATA_BYTE_50_MASK)

#define CAN_WORD_DATA_BYTE_54_MASK               (0xFF00U)
#define CAN_WORD_DATA_BYTE_54_SHIFT              (8U)
/*! DATA_BYTE_54 - Data byte 1 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_54(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_54_SHIFT)) & CAN_WORD_DATA_BYTE_54_MASK)

#define CAN_WORD_DATA_BYTE_58_MASK               (0xFF00U)
#define CAN_WORD_DATA_BYTE_58_SHIFT              (8U)
/*! DATA_BYTE_58 - Data byte 1 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_58(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_58_SHIFT)) & CAN_WORD_DATA_BYTE_58_MASK)

#define CAN_WORD_DATA_BYTE_62_MASK               (0xFF00U)
#define CAN_WORD_DATA_BYTE_62_SHIFT              (8U)
/*! DATA_BYTE_62 - Data byte 1 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_62(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_62_SHIFT)) & CAN_WORD_DATA_BYTE_62_MASK)

#define CAN_WORD_DATA_BYTE_1_MASK                (0xFF0000U)
#define CAN_WORD_DATA_BYTE_1_SHIFT               (16U)
/*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_1(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_1_SHIFT)) & CAN_WORD_DATA_BYTE_1_MASK)

#define CAN_WORD_DATA_BYTE_5_MASK                (0xFF0000U)
#define CAN_WORD_DATA_BYTE_5_SHIFT               (16U)
/*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_5(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_5_SHIFT)) & CAN_WORD_DATA_BYTE_5_MASK)

#define CAN_WORD_DATA_BYTE_9_MASK                (0xFF0000U)
#define CAN_WORD_DATA_BYTE_9_SHIFT               (16U)
/*! DATA_BYTE_9 - Data byte 2 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_9(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_9_SHIFT)) & CAN_WORD_DATA_BYTE_9_MASK)

#define CAN_WORD_DATA_BYTE_13_MASK               (0xFF0000U)
#define CAN_WORD_DATA_BYTE_13_SHIFT              (16U)
/*! DATA_BYTE_13 - Data byte 2 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_13(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_13_SHIFT)) & CAN_WORD_DATA_BYTE_13_MASK)

#define CAN_WORD_DATA_BYTE_17_MASK               (0xFF0000U)
#define CAN_WORD_DATA_BYTE_17_SHIFT              (16U)
/*! DATA_BYTE_17 - Data byte 2 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_17(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_17_SHIFT)) & CAN_WORD_DATA_BYTE_17_MASK)

#define CAN_WORD_DATA_BYTE_21_MASK               (0xFF0000U)
#define CAN_WORD_DATA_BYTE_21_SHIFT              (16U)
/*! DATA_BYTE_21 - Data byte 2 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_21(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_21_SHIFT)) & CAN_WORD_DATA_BYTE_21_MASK)

#define CAN_WORD_DATA_BYTE_25_MASK               (0xFF0000U)
#define CAN_WORD_DATA_BYTE_25_SHIFT              (16U)
/*! DATA_BYTE_25 - Data byte 2 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_25(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_25_SHIFT)) & CAN_WORD_DATA_BYTE_25_MASK)

#define CAN_WORD_DATA_BYTE_29_MASK               (0xFF0000U)
#define CAN_WORD_DATA_BYTE_29_SHIFT              (16U)
/*! DATA_BYTE_29 - Data byte 2 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_29(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_29_SHIFT)) & CAN_WORD_DATA_BYTE_29_MASK)

#define CAN_WORD_DATA_BYTE_33_MASK               (0xFF0000U)
#define CAN_WORD_DATA_BYTE_33_SHIFT              (16U)
/*! DATA_BYTE_33 - Data byte 2 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_33(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_33_SHIFT)) & CAN_WORD_DATA_BYTE_33_MASK)

#define CAN_WORD_DATA_BYTE_37_MASK               (0xFF0000U)
#define CAN_WORD_DATA_BYTE_37_SHIFT              (16U)
/*! DATA_BYTE_37 - Data byte 2 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_37(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_37_SHIFT)) & CAN_WORD_DATA_BYTE_37_MASK)

#define CAN_WORD_DATA_BYTE_41_MASK               (0xFF0000U)
#define CAN_WORD_DATA_BYTE_41_SHIFT              (16U)
/*! DATA_BYTE_41 - Data byte 2 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_41(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_41_SHIFT)) & CAN_WORD_DATA_BYTE_41_MASK)

#define CAN_WORD_DATA_BYTE_45_MASK               (0xFF0000U)
#define CAN_WORD_DATA_BYTE_45_SHIFT              (16U)
/*! DATA_BYTE_45 - Data byte 2 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_45(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_45_SHIFT)) & CAN_WORD_DATA_BYTE_45_MASK)

#define CAN_WORD_DATA_BYTE_49_MASK               (0xFF0000U)
#define CAN_WORD_DATA_BYTE_49_SHIFT              (16U)
/*! DATA_BYTE_49 - Data byte 2 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_49(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_49_SHIFT)) & CAN_WORD_DATA_BYTE_49_MASK)

#define CAN_WORD_DATA_BYTE_53_MASK               (0xFF0000U)
#define CAN_WORD_DATA_BYTE_53_SHIFT              (16U)
/*! DATA_BYTE_53 - Data byte 2 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_53(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_53_SHIFT)) & CAN_WORD_DATA_BYTE_53_MASK)

#define CAN_WORD_DATA_BYTE_57_MASK               (0xFF0000U)
#define CAN_WORD_DATA_BYTE_57_SHIFT              (16U)
/*! DATA_BYTE_57 - Data byte 2 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_57(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_57_SHIFT)) & CAN_WORD_DATA_BYTE_57_MASK)

#define CAN_WORD_DATA_BYTE_61_MASK               (0xFF0000U)
#define CAN_WORD_DATA_BYTE_61_SHIFT              (16U)
/*! DATA_BYTE_61 - Data byte 2 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_61(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_61_SHIFT)) & CAN_WORD_DATA_BYTE_61_MASK)

#define CAN_WORD_DATA_BYTE_0_MASK                (0xFF000000U)
#define CAN_WORD_DATA_BYTE_0_SHIFT               (24U)
/*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_0(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_0_SHIFT)) & CAN_WORD_DATA_BYTE_0_MASK)

#define CAN_WORD_DATA_BYTE_4_MASK                (0xFF000000U)
#define CAN_WORD_DATA_BYTE_4_SHIFT               (24U)
/*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_4(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_4_SHIFT)) & CAN_WORD_DATA_BYTE_4_MASK)

#define CAN_WORD_DATA_BYTE_8_MASK                (0xFF000000U)
#define CAN_WORD_DATA_BYTE_8_SHIFT               (24U)
/*! DATA_BYTE_8 - Data byte 3 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_8(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_8_SHIFT)) & CAN_WORD_DATA_BYTE_8_MASK)

#define CAN_WORD_DATA_BYTE_12_MASK               (0xFF000000U)
#define CAN_WORD_DATA_BYTE_12_SHIFT              (24U)
/*! DATA_BYTE_12 - Data byte 3 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_12(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_12_SHIFT)) & CAN_WORD_DATA_BYTE_12_MASK)

#define CAN_WORD_DATA_BYTE_16_MASK               (0xFF000000U)
#define CAN_WORD_DATA_BYTE_16_SHIFT              (24U)
/*! DATA_BYTE_16 - Data byte 3 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_16(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_16_SHIFT)) & CAN_WORD_DATA_BYTE_16_MASK)

#define CAN_WORD_DATA_BYTE_20_MASK               (0xFF000000U)
#define CAN_WORD_DATA_BYTE_20_SHIFT              (24U)
/*! DATA_BYTE_20 - Data byte 3 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_20(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_20_SHIFT)) & CAN_WORD_DATA_BYTE_20_MASK)

#define CAN_WORD_DATA_BYTE_24_MASK               (0xFF000000U)
#define CAN_WORD_DATA_BYTE_24_SHIFT              (24U)
/*! DATA_BYTE_24 - Data byte 3 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_24(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_24_SHIFT)) & CAN_WORD_DATA_BYTE_24_MASK)

#define CAN_WORD_DATA_BYTE_28_MASK               (0xFF000000U)
#define CAN_WORD_DATA_BYTE_28_SHIFT              (24U)
/*! DATA_BYTE_28 - Data byte 3 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_28(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_28_SHIFT)) & CAN_WORD_DATA_BYTE_28_MASK)

#define CAN_WORD_DATA_BYTE_32_MASK               (0xFF000000U)
#define CAN_WORD_DATA_BYTE_32_SHIFT              (24U)
/*! DATA_BYTE_32 - Data byte 3 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_32(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_32_SHIFT)) & CAN_WORD_DATA_BYTE_32_MASK)

#define CAN_WORD_DATA_BYTE_36_MASK               (0xFF000000U)
#define CAN_WORD_DATA_BYTE_36_SHIFT              (24U)
/*! DATA_BYTE_36 - Data byte 3 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_36(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_36_SHIFT)) & CAN_WORD_DATA_BYTE_36_MASK)

#define CAN_WORD_DATA_BYTE_40_MASK               (0xFF000000U)
#define CAN_WORD_DATA_BYTE_40_SHIFT              (24U)
/*! DATA_BYTE_40 - Data byte 3 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_40(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_40_SHIFT)) & CAN_WORD_DATA_BYTE_40_MASK)

#define CAN_WORD_DATA_BYTE_44_MASK               (0xFF000000U)
#define CAN_WORD_DATA_BYTE_44_SHIFT              (24U)
/*! DATA_BYTE_44 - Data byte 3 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_44(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_44_SHIFT)) & CAN_WORD_DATA_BYTE_44_MASK)

#define CAN_WORD_DATA_BYTE_48_MASK               (0xFF000000U)
#define CAN_WORD_DATA_BYTE_48_SHIFT              (24U)
/*! DATA_BYTE_48 - Data byte 3 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_48(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_48_SHIFT)) & CAN_WORD_DATA_BYTE_48_MASK)

#define CAN_WORD_DATA_BYTE_52_MASK               (0xFF000000U)
#define CAN_WORD_DATA_BYTE_52_SHIFT              (24U)
/*! DATA_BYTE_52 - Data byte 3 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_52(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_52_SHIFT)) & CAN_WORD_DATA_BYTE_52_MASK)

#define CAN_WORD_DATA_BYTE_56_MASK               (0xFF000000U)
#define CAN_WORD_DATA_BYTE_56_SHIFT              (24U)
/*! DATA_BYTE_56 - Data byte 3 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_56(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_56_SHIFT)) & CAN_WORD_DATA_BYTE_56_MASK)

#define CAN_WORD_DATA_BYTE_60_MASK               (0xFF000000U)
#define CAN_WORD_DATA_BYTE_60_SHIFT              (24U)
/*! DATA_BYTE_60 - Data byte 3 of Rx/Tx frame.
 */
#define CAN_WORD_DATA_BYTE_60(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_60_SHIFT)) & CAN_WORD_DATA_BYTE_60_MASK)
/*! @} */

/* The count of CAN_WORD */
#define CAN_WORD_COUNT_MB64B                     (7U)

/* The count of CAN_WORD */
#define CAN_WORD_COUNT_MB64B2                    (16U)

/* The count of CAN_CS */
#define CAN_CS_COUNT                             (32U)

/* The count of CAN_ID */
#define CAN_ID_COUNT                             (32U)

/*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 31 WORD0 Register */
/*! @{ */

#define CAN_WORD0_DATA_BYTE_3_MASK               (0xFFU)
#define CAN_WORD0_DATA_BYTE_3_SHIFT              (0U)
/*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame.
 */
#define CAN_WORD0_DATA_BYTE_3(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)

#define CAN_WORD0_DATA_BYTE_2_MASK               (0xFF00U)
#define CAN_WORD0_DATA_BYTE_2_SHIFT              (8U)
/*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame.
 */
#define CAN_WORD0_DATA_BYTE_2(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)

#define CAN_WORD0_DATA_BYTE_1_MASK               (0xFF0000U)
#define CAN_WORD0_DATA_BYTE_1_SHIFT              (16U)
/*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame.
 */
#define CAN_WORD0_DATA_BYTE_1(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)

#define CAN_WORD0_DATA_BYTE_0_MASK               (0xFF000000U)
#define CAN_WORD0_DATA_BYTE_0_SHIFT              (24U)
/*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame.
 */
#define CAN_WORD0_DATA_BYTE_0(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
/*! @} */

/* The count of CAN_WORD0 */
#define CAN_WORD0_COUNT                          (32U)

/*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 31 WORD1 Register */
/*! @{ */

#define CAN_WORD1_DATA_BYTE_7_MASK               (0xFFU)
#define CAN_WORD1_DATA_BYTE_7_SHIFT              (0U)
/*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame.
 */
#define CAN_WORD1_DATA_BYTE_7(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)

#define CAN_WORD1_DATA_BYTE_6_MASK               (0xFF00U)
#define CAN_WORD1_DATA_BYTE_6_SHIFT              (8U)
/*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame.
 */
#define CAN_WORD1_DATA_BYTE_6(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)

#define CAN_WORD1_DATA_BYTE_5_MASK               (0xFF0000U)
#define CAN_WORD1_DATA_BYTE_5_SHIFT              (16U)
/*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame.
 */
#define CAN_WORD1_DATA_BYTE_5(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)

#define CAN_WORD1_DATA_BYTE_4_MASK               (0xFF000000U)
#define CAN_WORD1_DATA_BYTE_4_SHIFT              (24U)
/*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame.
 */
#define CAN_WORD1_DATA_BYTE_4(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
/*! @} */

/* The count of CAN_WORD1 */
#define CAN_WORD1_COUNT                          (32U)

/*! @name RXIMR - Rx Individual Mask Registers */
/*! @{ */

#define CAN_RXIMR_MI_MASK                        (0xFFFFFFFFU)
#define CAN_RXIMR_MI_SHIFT                       (0U)
/*! MI - Individual Mask Bits
 */
#define CAN_RXIMR_MI(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
/*! @} */

/* The count of CAN_RXIMR */
#define CAN_RXIMR_COUNT                          (32U)

/*! @name CTRL1_PN - Pretended Networking Control 1 Register */
/*! @{ */

#define CAN_CTRL1_PN_FCS_MASK                    (0x3U)
#define CAN_CTRL1_PN_FCS_SHIFT                   (0U)
/*! FCS - Filtering Combination Selection
 *  0b00..Message ID filtering only
 *  0b01..Message ID filtering and payload filtering
 *  0b10..Message ID filtering occurring a specified number of times
 *  0b11..Message ID filtering and payload filtering a specified number of times
 */
#define CAN_CTRL1_PN_FCS(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_FCS_SHIFT)) & CAN_CTRL1_PN_FCS_MASK)

#define CAN_CTRL1_PN_IDFS_MASK                   (0xCU)
#define CAN_CTRL1_PN_IDFS_SHIFT                  (2U)
/*! IDFS - ID Filtering Selection
 *  0b00..Match upon ID contents against an exact target value
 *  0b01..Match upon an ID value greater than or equal to a specified target value
 *  0b10..Match upon an ID value smaller than or equal to a specified target value
 *  0b11..Match upon an ID value inside a range, greater than or equal to a specified lower limit, and smaller
 *        than or equal to a specified upper limit
 */
#define CAN_CTRL1_PN_IDFS(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_IDFS_SHIFT)) & CAN_CTRL1_PN_IDFS_MASK)

#define CAN_CTRL1_PN_PLFS_MASK                   (0x30U)
#define CAN_CTRL1_PN_PLFS_SHIFT                  (4U)
/*! PLFS - Payload Filtering Selection
 *  0b00..Match upon a payload contents against an exact target value
 *  0b01..Match upon a payload value greater than or equal to a specified target value
 *  0b10..Match upon a payload value smaller than or equal to a specified target value
 *  0b11..Match upon a payload value inside a range, greater than or equal to a specified lower limit, and smaller
 *        than or equal to a specified upper limit
 */
#define CAN_CTRL1_PN_PLFS(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_PLFS_SHIFT)) & CAN_CTRL1_PN_PLFS_MASK)

#define CAN_CTRL1_PN_NMATCH_MASK                 (0xFF00U)
#define CAN_CTRL1_PN_NMATCH_SHIFT                (8U)
/*! NMATCH - Number of Messages Matching the Same Filtering Criteria
 *  0b00000001..Received message must match the predefined filtering criteria for ID and/or PL once before generating a wakeup event.
 *  0b00000010..Received message must match the predefined filtering criteria for ID and/or PL twice before generating a wakeup event.
 *  0b11111111..Received message must match the predefined filtering criteria for ID and/or PL 255 times before generating a wakeup event.
 */
#define CAN_CTRL1_PN_NMATCH(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_NMATCH_SHIFT)) & CAN_CTRL1_PN_NMATCH_MASK)

#define CAN_CTRL1_PN_WUMF_MSK_MASK               (0x10000U)
#define CAN_CTRL1_PN_WUMF_MSK_SHIFT              (16U)
/*! WUMF_MSK - Wake Up by Match Flag Mask Bit
 *  0b0..Wakeup match event is disabled
 *  0b1..Wakeup match event is enabled
 */
#define CAN_CTRL1_PN_WUMF_MSK(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_WUMF_MSK_SHIFT)) & CAN_CTRL1_PN_WUMF_MSK_MASK)

#define CAN_CTRL1_PN_WTOF_MSK_MASK               (0x20000U)
#define CAN_CTRL1_PN_WTOF_MSK_SHIFT              (17U)
/*! WTOF_MSK - Wake Up by Timeout Flag Mask Bit
 *  0b0..Timeout wakeup event is disabled
 *  0b1..Timeout wakeup event is enabled
 */
#define CAN_CTRL1_PN_WTOF_MSK(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_WTOF_MSK_SHIFT)) & CAN_CTRL1_PN_WTOF_MSK_MASK)
/*! @} */

/*! @name CTRL2_PN - Pretended Networking Control 2 Register */
/*! @{ */

#define CAN_CTRL2_PN_MATCHTO_MASK                (0xFFFFU)
#define CAN_CTRL2_PN_MATCHTO_SHIFT               (0U)
/*! MATCHTO - Timeout for No Message Matching the Filtering Criteria
 */
#define CAN_CTRL2_PN_MATCHTO(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PN_MATCHTO_SHIFT)) & CAN_CTRL2_PN_MATCHTO_MASK)
/*! @} */

/*! @name WU_MTC - Pretended Networking Wake Up Match Register */
/*! @{ */

#define CAN_WU_MTC_MCOUNTER_MASK                 (0xFF00U)
#define CAN_WU_MTC_MCOUNTER_SHIFT                (8U)
/*! MCOUNTER - Number of Matches when in Pretended Networking
 */
#define CAN_WU_MTC_MCOUNTER(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_WU_MTC_MCOUNTER_SHIFT)) & CAN_WU_MTC_MCOUNTER_MASK)

#define CAN_WU_MTC_WUMF_MASK                     (0x10000U)
#define CAN_WU_MTC_WUMF_SHIFT                    (16U)
/*! WUMF - Wake Up by Match Flag Bit
 *  0b0..No wakeup by match event detected
 *  0b1..Wakeup by match event detected
 */
#define CAN_WU_MTC_WUMF(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_WU_MTC_WUMF_SHIFT)) & CAN_WU_MTC_WUMF_MASK)

#define CAN_WU_MTC_WTOF_MASK                     (0x20000U)
#define CAN_WU_MTC_WTOF_SHIFT                    (17U)
/*! WTOF - Wake Up by Timeout Flag Bit
 *  0b0..No wakeup by timeout event detected
 *  0b1..Wakeup by timeout event detected
 */
#define CAN_WU_MTC_WTOF(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_WU_MTC_WTOF_SHIFT)) & CAN_WU_MTC_WTOF_MASK)
/*! @} */

/*! @name FLT_ID1 - Pretended Networking ID Filter 1 Register */
/*! @{ */

#define CAN_FLT_ID1_FLT_ID1_MASK                 (0x1FFFFFFFU)
#define CAN_FLT_ID1_FLT_ID1_SHIFT                (0U)
/*! FLT_ID1 - ID Filter 1 for Pretended Networking filtering
 */
#define CAN_FLT_ID1_FLT_ID1(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID1_FLT_ID1_SHIFT)) & CAN_FLT_ID1_FLT_ID1_MASK)

#define CAN_FLT_ID1_FLT_RTR_MASK                 (0x20000000U)
#define CAN_FLT_ID1_FLT_RTR_SHIFT                (29U)
/*! FLT_RTR - Remote Transmission Request Filter
 *  0b0..Reject remote frame (accept data frame)
 *  0b1..Accept remote frame
 */
#define CAN_FLT_ID1_FLT_RTR(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID1_FLT_RTR_SHIFT)) & CAN_FLT_ID1_FLT_RTR_MASK)

#define CAN_FLT_ID1_FLT_IDE_MASK                 (0x40000000U)
#define CAN_FLT_ID1_FLT_IDE_SHIFT                (30U)
/*! FLT_IDE - ID Extended Filter
 *  0b0..Accept standard frame format
 *  0b1..Accept extended frame format
 */
#define CAN_FLT_ID1_FLT_IDE(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID1_FLT_IDE_SHIFT)) & CAN_FLT_ID1_FLT_IDE_MASK)
/*! @} */

/*! @name FLT_DLC - Pretended Networking DLC Filter Register */
/*! @{ */

#define CAN_FLT_DLC_FLT_DLC_HI_MASK              (0xFU)
#define CAN_FLT_DLC_FLT_DLC_HI_SHIFT             (0U)
/*! FLT_DLC_HI - Upper Limit for Length of Data Bytes Filter
 */
#define CAN_FLT_DLC_FLT_DLC_HI(x)                (((uint32_t)(((uint32_t)(x)) << CAN_FLT_DLC_FLT_DLC_HI_SHIFT)) & CAN_FLT_DLC_FLT_DLC_HI_MASK)

#define CAN_FLT_DLC_FLT_DLC_LO_MASK              (0xF0000U)
#define CAN_FLT_DLC_FLT_DLC_LO_SHIFT             (16U)
/*! FLT_DLC_LO - Lower Limit for Length of Data Bytes Filter
 */
#define CAN_FLT_DLC_FLT_DLC_LO(x)                (((uint32_t)(((uint32_t)(x)) << CAN_FLT_DLC_FLT_DLC_LO_SHIFT)) & CAN_FLT_DLC_FLT_DLC_LO_MASK)
/*! @} */

/*! @name PL1_LO - Pretended Networking Payload Low Filter 1 Register */
/*! @{ */

#define CAN_PL1_LO_Data_byte_3_MASK              (0xFFU)
#define CAN_PL1_LO_Data_byte_3_SHIFT             (0U)
/*! Data_byte_3 - Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to data byte 3.
 */
#define CAN_PL1_LO_Data_byte_3(x)                (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_3_SHIFT)) & CAN_PL1_LO_Data_byte_3_MASK)

#define CAN_PL1_LO_Data_byte_2_MASK              (0xFF00U)
#define CAN_PL1_LO_Data_byte_2_SHIFT             (8U)
/*! Data_byte_2 - Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to data byte 2.
 */
#define CAN_PL1_LO_Data_byte_2(x)                (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_2_SHIFT)) & CAN_PL1_LO_Data_byte_2_MASK)

#define CAN_PL1_LO_Data_byte_1_MASK              (0xFF0000U)
#define CAN_PL1_LO_Data_byte_1_SHIFT             (16U)
/*! Data_byte_1 - Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to data byte 1.
 */
#define CAN_PL1_LO_Data_byte_1(x)                (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_1_SHIFT)) & CAN_PL1_LO_Data_byte_1_MASK)

#define CAN_PL1_LO_Data_byte_0_MASK              (0xFF000000U)
#define CAN_PL1_LO_Data_byte_0_SHIFT             (24U)
/*! Data_byte_0 - Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to data byte 0.
 */
#define CAN_PL1_LO_Data_byte_0(x)                (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_0_SHIFT)) & CAN_PL1_LO_Data_byte_0_MASK)
/*! @} */

/*! @name PL1_HI - Pretended Networking Payload High Filter 1 Register */
/*! @{ */

#define CAN_PL1_HI_Data_byte_7_MASK              (0xFFU)
#define CAN_PL1_HI_Data_byte_7_SHIFT             (0U)
/*! Data_byte_7 - Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to data byte 7.
 */
#define CAN_PL1_HI_Data_byte_7(x)                (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_7_SHIFT)) & CAN_PL1_HI_Data_byte_7_MASK)

#define CAN_PL1_HI_Data_byte_6_MASK              (0xFF00U)
#define CAN_PL1_HI_Data_byte_6_SHIFT             (8U)
/*! Data_byte_6 - Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to data byte 6.
 */
#define CAN_PL1_HI_Data_byte_6(x)                (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_6_SHIFT)) & CAN_PL1_HI_Data_byte_6_MASK)

#define CAN_PL1_HI_Data_byte_5_MASK              (0xFF0000U)
#define CAN_PL1_HI_Data_byte_5_SHIFT             (16U)
/*! Data_byte_5 - Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to data byte 5.
 */
#define CAN_PL1_HI_Data_byte_5(x)                (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_5_SHIFT)) & CAN_PL1_HI_Data_byte_5_MASK)

#define CAN_PL1_HI_Data_byte_4_MASK              (0xFF000000U)
#define CAN_PL1_HI_Data_byte_4_SHIFT             (24U)
/*! Data_byte_4 - Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to data byte 4.
 */
#define CAN_PL1_HI_Data_byte_4(x)                (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_4_SHIFT)) & CAN_PL1_HI_Data_byte_4_MASK)
/*! @} */

/*! @name FLT_ID2_IDMASK - Pretended Networking ID Filter 2 Register / ID Mask Register */
/*! @{ */

#define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_MASK   (0x1FFFFFFFU)
#define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_SHIFT  (0U)
/*! FLT_ID2_IDMASK - ID Filter 2 for Pretended Networking Filtering / ID Mask Bits for Pretended Networking ID Filtering
 */
#define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK(x)     (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_SHIFT)) & CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_MASK)

#define CAN_FLT_ID2_IDMASK_RTR_MSK_MASK          (0x20000000U)
#define CAN_FLT_ID2_IDMASK_RTR_MSK_SHIFT         (29U)
/*! RTR_MSK - Remote Transmission Request Mask Bit
 *  0b0..The corresponding bit in the filter is "don't care"
 *  0b1..The corresponding bit in the filter is checked
 */
#define CAN_FLT_ID2_IDMASK_RTR_MSK(x)            (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID2_IDMASK_RTR_MSK_SHIFT)) & CAN_FLT_ID2_IDMASK_RTR_MSK_MASK)

#define CAN_FLT_ID2_IDMASK_IDE_MSK_MASK          (0x40000000U)
#define CAN_FLT_ID2_IDMASK_IDE_MSK_SHIFT         (30U)
/*! IDE_MSK - ID Extended Mask Bit
 *  0b0..The corresponding bit in the filter is "don't care"
 *  0b1..The corresponding bit in the filter is checked
 */
#define CAN_FLT_ID2_IDMASK_IDE_MSK(x)            (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID2_IDMASK_IDE_MSK_SHIFT)) & CAN_FLT_ID2_IDMASK_IDE_MSK_MASK)
/*! @} */

/*! @name PL2_PLMASK_LO - Pretended Networking Payload Low Filter 2 Register / Payload Low Mask register */
/*! @{ */

#define CAN_PL2_PLMASK_LO_Data_byte_3_MASK       (0xFFU)
#define CAN_PL2_PLMASK_LO_Data_byte_3_SHIFT      (0U)
/*! Data_byte_3 - Payload Filter 2 low order bits / Payload Mask low order bits for Pretended
 *    Networking payload filtering corresponding to the data byte 3.
 */
#define CAN_PL2_PLMASK_LO_Data_byte_3(x)         (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_3_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_3_MASK)

#define CAN_PL2_PLMASK_LO_Data_byte_2_MASK       (0xFF00U)
#define CAN_PL2_PLMASK_LO_Data_byte_2_SHIFT      (8U)
/*! Data_byte_2 - Payload Filter 2 low order bits / Payload Mask low order bits for Pretended
 *    Networking payload filtering corresponding to the data byte 2.
 */
#define CAN_PL2_PLMASK_LO_Data_byte_2(x)         (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_2_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_2_MASK)

#define CAN_PL2_PLMASK_LO_Data_byte_1_MASK       (0xFF0000U)
#define CAN_PL2_PLMASK_LO_Data_byte_1_SHIFT      (16U)
/*! Data_byte_1 - Payload Filter 2 low order bits / Payload Mask low order bits for Pretended
 *    Networking payload filtering corresponding to the data byte 1.
 */
#define CAN_PL2_PLMASK_LO_Data_byte_1(x)         (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_1_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_1_MASK)

#define CAN_PL2_PLMASK_LO_Data_byte_0_MASK       (0xFF000000U)
#define CAN_PL2_PLMASK_LO_Data_byte_0_SHIFT      (24U)
/*! Data_byte_0 - Payload Filter 2 low order bits / Payload Mask low order bits for Pretended
 *    Networking payload filtering corresponding to the data byte 0.
 */
#define CAN_PL2_PLMASK_LO_Data_byte_0(x)         (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_0_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_0_MASK)
/*! @} */

/*! @name PL2_PLMASK_HI - Pretended Networking Payload High Filter 2 low order bits / Payload High Mask register */
/*! @{ */

#define CAN_PL2_PLMASK_HI_Data_byte_7_MASK       (0xFFU)
#define CAN_PL2_PLMASK_HI_Data_byte_7_SHIFT      (0U)
/*! Data_byte_7 - Payload Filter 2 high order bits / Payload Mask high order bits for Pretended
 *    Networking payload filtering corresponding to the data byte 7.
 */
#define CAN_PL2_PLMASK_HI_Data_byte_7(x)         (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_7_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_7_MASK)

#define CAN_PL2_PLMASK_HI_Data_byte_6_MASK       (0xFF00U)
#define CAN_PL2_PLMASK_HI_Data_byte_6_SHIFT      (8U)
/*! Data_byte_6 - Payload Filter 2 high order bits / Payload Mask high order bits for Pretended
 *    Networking payload filtering corresponding to the data byte 6.
 */
#define CAN_PL2_PLMASK_HI_Data_byte_6(x)         (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_6_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_6_MASK)

#define CAN_PL2_PLMASK_HI_Data_byte_5_MASK       (0xFF0000U)
#define CAN_PL2_PLMASK_HI_Data_byte_5_SHIFT      (16U)
/*! Data_byte_5 - Payload Filter 2 high order bits / Payload Mask high order bits for Pretended
 *    Networking payload filtering corresponding to the data byte 5.
 */
#define CAN_PL2_PLMASK_HI_Data_byte_5(x)         (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_5_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_5_MASK)

#define CAN_PL2_PLMASK_HI_Data_byte_4_MASK       (0xFF000000U)
#define CAN_PL2_PLMASK_HI_Data_byte_4_SHIFT      (24U)
/*! Data_byte_4 - Payload Filter 2 high order bits / Payload Mask high order bits for Pretended
 *    Networking payload filtering corresponding to the data byte 4.
 */
#define CAN_PL2_PLMASK_HI_Data_byte_4(x)         (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_4_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_4_MASK)
/*! @} */

/*! @name WMB_CS - Wake Up Message Buffer register for C/S */
/*! @{ */

#define CAN_WMB_CS_DLC_MASK                      (0xF0000U)
#define CAN_WMB_CS_DLC_SHIFT                     (16U)
/*! DLC - Length of Data in Bytes
 */
#define CAN_WMB_CS_DLC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_WMB_CS_DLC_SHIFT)) & CAN_WMB_CS_DLC_MASK)

#define CAN_WMB_CS_RTR_MASK                      (0x100000U)
#define CAN_WMB_CS_RTR_SHIFT                     (20U)
/*! RTR - Remote Transmission Request Bit
 *  0b0..Frame is data one (not remote)
 *  0b1..Frame is a remote one
 */
#define CAN_WMB_CS_RTR(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_WMB_CS_RTR_SHIFT)) & CAN_WMB_CS_RTR_MASK)

#define CAN_WMB_CS_IDE_MASK                      (0x200000U)
#define CAN_WMB_CS_IDE_SHIFT                     (21U)
/*! IDE - ID Extended Bit
 *  0b0..Frame format is standard
 *  0b1..Frame format is extended
 */
#define CAN_WMB_CS_IDE(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_WMB_CS_IDE_SHIFT)) & CAN_WMB_CS_IDE_MASK)

#define CAN_WMB_CS_SRR_MASK                      (0x400000U)
#define CAN_WMB_CS_SRR_SHIFT                     (22U)
/*! SRR - Substitute Remote Request
 */
#define CAN_WMB_CS_SRR(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_WMB_CS_SRR_SHIFT)) & CAN_WMB_CS_SRR_MASK)
/*! @} */

/* The count of CAN_WMB_CS */
#define CAN_WMB_CS_COUNT                         (4U)

/*! @name WMB_ID - Wake Up Message Buffer Register for ID */
/*! @{ */

#define CAN_WMB_ID_ID_MASK                       (0x1FFFFFFFU)
#define CAN_WMB_ID_ID_SHIFT                      (0U)
/*! ID - Received ID under Pretended Networking mode
 */
#define CAN_WMB_ID_ID(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_WMB_ID_ID_SHIFT)) & CAN_WMB_ID_ID_MASK)
/*! @} */

/* The count of CAN_WMB_ID */
#define CAN_WMB_ID_COUNT                         (4U)

/*! @name WMB_D03 - Wake Up Message Buffer Register for Data 0-3 */
/*! @{ */

#define CAN_WMB_D03_Data_byte_3_MASK             (0xFFU)
#define CAN_WMB_D03_Data_byte_3_SHIFT            (0U)
/*! Data_byte_3 - Received payload corresponding to the data byte 3 under Pretended Networking mode
 */
#define CAN_WMB_D03_Data_byte_3(x)               (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D03_Data_byte_3_SHIFT)) & CAN_WMB_D03_Data_byte_3_MASK)

#define CAN_WMB_D03_Data_byte_2_MASK             (0xFF00U)
#define CAN_WMB_D03_Data_byte_2_SHIFT            (8U)
/*! Data_byte_2 - Received payload corresponding to the data byte 2 under Pretended Networking mode
 */
#define CAN_WMB_D03_Data_byte_2(x)               (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D03_Data_byte_2_SHIFT)) & CAN_WMB_D03_Data_byte_2_MASK)

#define CAN_WMB_D03_Data_byte_1_MASK             (0xFF0000U)
#define CAN_WMB_D03_Data_byte_1_SHIFT            (16U)
/*! Data_byte_1 - Received payload corresponding to the data byte 1 under Pretended Networking mode
 */
#define CAN_WMB_D03_Data_byte_1(x)               (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D03_Data_byte_1_SHIFT)) & CAN_WMB_D03_Data_byte_1_MASK)

#define CAN_WMB_D03_Data_byte_0_MASK             (0xFF000000U)
#define CAN_WMB_D03_Data_byte_0_SHIFT            (24U)
/*! Data_byte_0 - Received payload corresponding to the data byte 0 under Pretended Networking mode
 */
#define CAN_WMB_D03_Data_byte_0(x)               (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D03_Data_byte_0_SHIFT)) & CAN_WMB_D03_Data_byte_0_MASK)
/*! @} */

/* The count of CAN_WMB_D03 */
#define CAN_WMB_D03_COUNT                        (4U)

/*! @name WMB_D47 - Wake Up Message Buffer Register Data 4-7 */
/*! @{ */

#define CAN_WMB_D47_Data_byte_7_MASK             (0xFFU)
#define CAN_WMB_D47_Data_byte_7_SHIFT            (0U)
/*! Data_byte_7 - Received payload corresponding to the data byte 7 under Pretended Networking mode
 */
#define CAN_WMB_D47_Data_byte_7(x)               (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D47_Data_byte_7_SHIFT)) & CAN_WMB_D47_Data_byte_7_MASK)

#define CAN_WMB_D47_Data_byte_6_MASK             (0xFF00U)
#define CAN_WMB_D47_Data_byte_6_SHIFT            (8U)
/*! Data_byte_6 - Received payload corresponding to the data byte 6 under Pretended Networking mode
 */
#define CAN_WMB_D47_Data_byte_6(x)               (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D47_Data_byte_6_SHIFT)) & CAN_WMB_D47_Data_byte_6_MASK)

#define CAN_WMB_D47_Data_byte_5_MASK             (0xFF0000U)
#define CAN_WMB_D47_Data_byte_5_SHIFT            (16U)
/*! Data_byte_5 - Received payload corresponding to the data byte 5 under Pretended Networking mode
 */
#define CAN_WMB_D47_Data_byte_5(x)               (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D47_Data_byte_5_SHIFT)) & CAN_WMB_D47_Data_byte_5_MASK)

#define CAN_WMB_D47_Data_byte_4_MASK             (0xFF000000U)
#define CAN_WMB_D47_Data_byte_4_SHIFT            (24U)
/*! Data_byte_4 - Received payload corresponding to the data byte 4 under Pretended Networking mode
 */
#define CAN_WMB_D47_Data_byte_4(x)               (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D47_Data_byte_4_SHIFT)) & CAN_WMB_D47_Data_byte_4_MASK)
/*! @} */

/* The count of CAN_WMB_D47 */
#define CAN_WMB_D47_COUNT                        (4U)

/*! @name EPRS - Enhanced CAN Bit Timing Prescalers */
/*! @{ */

#define CAN_EPRS_ENPRESDIV_MASK                  (0x3FFU)
#define CAN_EPRS_ENPRESDIV_SHIFT                 (0U)
/*! ENPRESDIV - Extended Nominal Prescaler Division Factor
 */
#define CAN_EPRS_ENPRESDIV(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_EPRS_ENPRESDIV_SHIFT)) & CAN_EPRS_ENPRESDIV_MASK)

#define CAN_EPRS_EDPRESDIV_MASK                  (0x3FF0000U)
#define CAN_EPRS_EDPRESDIV_SHIFT                 (16U)
/*! EDPRESDIV - Extended Data Phase Prescaler Division Factor
 */
#define CAN_EPRS_EDPRESDIV(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_EPRS_EDPRESDIV_SHIFT)) & CAN_EPRS_EDPRESDIV_MASK)
/*! @} */

/*! @name ENCBT - Enhanced Nominal CAN Bit Timing */
/*! @{ */

#define CAN_ENCBT_NTSEG1_MASK                    (0xFFU)
#define CAN_ENCBT_NTSEG1_SHIFT                   (0U)
/*! NTSEG1 - Nominal Time Segment 1
 */
#define CAN_ENCBT_NTSEG1(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NTSEG1_SHIFT)) & CAN_ENCBT_NTSEG1_MASK)

#define CAN_ENCBT_NTSEG2_MASK                    (0x7F000U)
#define CAN_ENCBT_NTSEG2_SHIFT                   (12U)
/*! NTSEG2 - Nominal Time Segment 2
 */
#define CAN_ENCBT_NTSEG2(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NTSEG2_SHIFT)) & CAN_ENCBT_NTSEG2_MASK)

#define CAN_ENCBT_NRJW_MASK                      (0x1FC00000U)
#define CAN_ENCBT_NRJW_SHIFT                     (22U)
/*! NRJW - Nominal Resynchronization Jump Width
 */
#define CAN_ENCBT_NRJW(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NRJW_SHIFT)) & CAN_ENCBT_NRJW_MASK)
/*! @} */

/*! @name EDCBT - Enhanced Data Phase CAN bit Timing */
/*! @{ */

#define CAN_EDCBT_DTSEG1_MASK                    (0x1FU)
#define CAN_EDCBT_DTSEG1_SHIFT                   (0U)
/*! DTSEG1 - Data Phase Segment 1
 */
#define CAN_EDCBT_DTSEG1(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DTSEG1_SHIFT)) & CAN_EDCBT_DTSEG1_MASK)

#define CAN_EDCBT_DTSEG2_MASK                    (0xF000U)
#define CAN_EDCBT_DTSEG2_SHIFT                   (12U)
/*! DTSEG2 - Data Phase Time Segment 2
 */
#define CAN_EDCBT_DTSEG2(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DTSEG2_SHIFT)) & CAN_EDCBT_DTSEG2_MASK)

#define CAN_EDCBT_DRJW_MASK                      (0x3C00000U)
#define CAN_EDCBT_DRJW_SHIFT                     (22U)
/*! DRJW - Data Phase Resynchronization Jump Width
 */
#define CAN_EDCBT_DRJW(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DRJW_SHIFT)) & CAN_EDCBT_DRJW_MASK)
/*! @} */

/*! @name ETDC - Enhanced Transceiver Delay Compensation */
/*! @{ */

#define CAN_ETDC_ETDCVAL_MASK                    (0xFFU)
#define CAN_ETDC_ETDCVAL_SHIFT                   (0U)
/*! ETDCVAL - Enhanced Transceiver Delay Compensation Value
 */
#define CAN_ETDC_ETDCVAL(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCVAL_SHIFT)) & CAN_ETDC_ETDCVAL_MASK)

#define CAN_ETDC_ETDCFAIL_MASK                   (0x8000U)
#define CAN_ETDC_ETDCFAIL_SHIFT                  (15U)
/*! ETDCFAIL - Transceiver Delay Compensation Fail
 *  0b0..Measured loop delay is in range.
 *  0b1..Measured loop delay is out of range.
 */
#define CAN_ETDC_ETDCFAIL(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCFAIL_SHIFT)) & CAN_ETDC_ETDCFAIL_MASK)

#define CAN_ETDC_ETDCOFF_MASK                    (0x7F0000U)
#define CAN_ETDC_ETDCOFF_SHIFT                   (16U)
/*! ETDCOFF - Enhanced Transceiver Delay Compensation Offset
 */
#define CAN_ETDC_ETDCOFF(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCOFF_SHIFT)) & CAN_ETDC_ETDCOFF_MASK)

#define CAN_ETDC_TDMDIS_MASK                     (0x40000000U)
#define CAN_ETDC_TDMDIS_SHIFT                    (30U)
/*! TDMDIS - Transceiver Delay Measurement Disable
 *  0b0..TDC measurement is enabled
 *  0b1..TDC measurement is disabled
 */
#define CAN_ETDC_TDMDIS(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_TDMDIS_SHIFT)) & CAN_ETDC_TDMDIS_MASK)

#define CAN_ETDC_ETDCEN_MASK                     (0x80000000U)
#define CAN_ETDC_ETDCEN_SHIFT                    (31U)
/*! ETDCEN - Transceiver Delay Compensation Enable
 *  0b0..TDC is disabled
 *  0b1..TDC is enabled
 */
#define CAN_ETDC_ETDCEN(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCEN_SHIFT)) & CAN_ETDC_ETDCEN_MASK)
/*! @} */

/*! @name FDCTRL - CAN FD Control Register */
/*! @{ */

#define CAN_FDCTRL_TDCVAL_MASK                   (0x3FU)
#define CAN_FDCTRL_TDCVAL_SHIFT                  (0U)
/*! TDCVAL - Transceiver Delay Compensation Value
 */
#define CAN_FDCTRL_TDCVAL(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCVAL_SHIFT)) & CAN_FDCTRL_TDCVAL_MASK)

#define CAN_FDCTRL_TDCOFF_MASK                   (0x1F00U)
#define CAN_FDCTRL_TDCOFF_SHIFT                  (8U)
/*! TDCOFF - Transceiver Delay Compensation Offset
 */
#define CAN_FDCTRL_TDCOFF(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCOFF_SHIFT)) & CAN_FDCTRL_TDCOFF_MASK)

#define CAN_FDCTRL_TDCFAIL_MASK                  (0x4000U)
#define CAN_FDCTRL_TDCFAIL_SHIFT                 (14U)
/*! TDCFAIL - Transceiver Delay Compensation Fail
 *  0b0..Measured loop delay is in range.
 *  0b1..Measured loop delay is out of range.
 */
#define CAN_FDCTRL_TDCFAIL(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCFAIL_SHIFT)) & CAN_FDCTRL_TDCFAIL_MASK)

#define CAN_FDCTRL_TDCEN_MASK                    (0x8000U)
#define CAN_FDCTRL_TDCEN_SHIFT                   (15U)
/*! TDCEN - Transceiver Delay Compensation Enable
 *  0b0..TDC is disabled
 *  0b1..TDC is enabled
 */
#define CAN_FDCTRL_TDCEN(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCEN_SHIFT)) & CAN_FDCTRL_TDCEN_MASK)

#define CAN_FDCTRL_MBDSR0_MASK                   (0x30000U)
#define CAN_FDCTRL_MBDSR0_SHIFT                  (16U)
/*! MBDSR0 - Message Buffer Data Size for Region 0
 *  0b00..Selects 8 bytes per message buffer.
 *  0b01..Selects 16 bytes per message buffer.
 *  0b10..Selects 32 bytes per message buffer.
 *  0b11..Selects 64 bytes per message buffer.
 */
#define CAN_FDCTRL_MBDSR0(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR0_SHIFT)) & CAN_FDCTRL_MBDSR0_MASK)

#define CAN_FDCTRL_FDRATE_MASK                   (0x80000000U)
#define CAN_FDCTRL_FDRATE_SHIFT                  (31U)
/*! FDRATE - Bit Rate Switch Enable
 *  0b0..Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect.
 *  0b1..Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive.
 */
#define CAN_FDCTRL_FDRATE(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_FDRATE_SHIFT)) & CAN_FDCTRL_FDRATE_MASK)
/*! @} */

/*! @name FDCBT - CAN FD Bit Timing Register */
/*! @{ */

#define CAN_FDCBT_FPSEG2_MASK                    (0x7U)
#define CAN_FDCBT_FPSEG2_SHIFT                   (0U)
/*! FPSEG2 - Fast Phase Segment 2
 */
#define CAN_FDCBT_FPSEG2(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG2_SHIFT)) & CAN_FDCBT_FPSEG2_MASK)

#define CAN_FDCBT_FPSEG1_MASK                    (0xE0U)
#define CAN_FDCBT_FPSEG1_SHIFT                   (5U)
/*! FPSEG1 - Fast Phase Segment 1
 */
#define CAN_FDCBT_FPSEG1(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK)

#define CAN_FDCBT_FPROPSEG_MASK                  (0x7C00U)
#define CAN_FDCBT_FPROPSEG_SHIFT                 (10U)
/*! FPROPSEG - Fast Propagation Segment
 */
#define CAN_FDCBT_FPROPSEG(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPROPSEG_SHIFT)) & CAN_FDCBT_FPROPSEG_MASK)

#define CAN_FDCBT_FRJW_MASK                      (0x70000U)
#define CAN_FDCBT_FRJW_SHIFT                     (16U)
/*! FRJW - Fast Resync Jump Width
 */
#define CAN_FDCBT_FRJW(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FRJW_SHIFT)) & CAN_FDCBT_FRJW_MASK)

#define CAN_FDCBT_FPRESDIV_MASK                  (0x3FF00000U)
#define CAN_FDCBT_FPRESDIV_SHIFT                 (20U)
/*! FPRESDIV - Fast Prescaler Division Factor
 */
#define CAN_FDCBT_FPRESDIV(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPRESDIV_SHIFT)) & CAN_FDCBT_FPRESDIV_MASK)
/*! @} */

/*! @name FDCRC - CAN FD CRC Register */
/*! @{ */

#define CAN_FDCRC_FD_TXCRC_MASK                  (0x1FFFFFU)
#define CAN_FDCRC_FD_TXCRC_SHIFT                 (0U)
/*! FD_TXCRC - Extended Transmitted CRC value
 */
#define CAN_FDCRC_FD_TXCRC(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_TXCRC_SHIFT)) & CAN_FDCRC_FD_TXCRC_MASK)

#define CAN_FDCRC_FD_MBCRC_MASK                  (0x7F000000U)
#define CAN_FDCRC_FD_MBCRC_SHIFT                 (24U)
/*! FD_MBCRC - CRC Mailbox Number for FD_TXCRC
 */
#define CAN_FDCRC_FD_MBCRC(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_MBCRC_SHIFT)) & CAN_FDCRC_FD_MBCRC_MASK)
/*! @} */

/*! @name ERFCR - Enhanced Rx FIFO Control Register */
/*! @{ */

#define CAN_ERFCR_ERFWM_MASK                     (0x1FU)
#define CAN_ERFCR_ERFWM_SHIFT                    (0U)
/*! ERFWM - Enhanced Rx FIFO Watermark
 */
#define CAN_ERFCR_ERFWM(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFWM_SHIFT)) & CAN_ERFCR_ERFWM_MASK)

#define CAN_ERFCR_NFE_MASK                       (0x3F00U)
#define CAN_ERFCR_NFE_SHIFT                      (8U)
/*! NFE - Number of Enhanced Rx FIFO Filter Elements
 */
#define CAN_ERFCR_NFE(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_NFE_SHIFT)) & CAN_ERFCR_NFE_MASK)

#define CAN_ERFCR_NEXIF_MASK                     (0x7F0000U)
#define CAN_ERFCR_NEXIF_SHIFT                    (16U)
/*! NEXIF - Number of Extended ID Filter Elements
 */
#define CAN_ERFCR_NEXIF(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_NEXIF_SHIFT)) & CAN_ERFCR_NEXIF_MASK)

#define CAN_ERFCR_DMALW_MASK                     (0x7C000000U)
#define CAN_ERFCR_DMALW_SHIFT                    (26U)
/*! DMALW - DMA Last Word
 */
#define CAN_ERFCR_DMALW(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_DMALW_SHIFT)) & CAN_ERFCR_DMALW_MASK)

#define CAN_ERFCR_ERFEN_MASK                     (0x80000000U)
#define CAN_ERFCR_ERFEN_SHIFT                    (31U)
/*! ERFEN - Enhanced Rx FIFO enable
 *  0b0..Enhanced Rx FIFO is disabled
 *  0b1..Enhanced Rx FIFO is enabled
 */
#define CAN_ERFCR_ERFEN(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFEN_SHIFT)) & CAN_ERFCR_ERFEN_MASK)
/*! @} */

/*! @name ERFIER - Enhanced Rx FIFO Interrupt Enable Register */
/*! @{ */

#define CAN_ERFIER_ERFDAIE_MASK                  (0x10000000U)
#define CAN_ERFIER_ERFDAIE_SHIFT                 (28U)
/*! ERFDAIE - Enhanced Rx FIFO Data Available Interrupt Enable
 *  0b0..Enhanced Rx FIFO Data Available interrupt is disabled
 *  0b1..Enhanced Rx FIFO Data Available interrupt is enabled
 */
#define CAN_ERFIER_ERFDAIE(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFDAIE_SHIFT)) & CAN_ERFIER_ERFDAIE_MASK)

#define CAN_ERFIER_ERFWMIIE_MASK                 (0x20000000U)
#define CAN_ERFIER_ERFWMIIE_SHIFT                (29U)
/*! ERFWMIIE - Enhanced Rx FIFO Watermark Indication Interrupt Enable
 *  0b0..Enhanced Rx FIFO Watermark interrupt is disabled
 *  0b1..Enhanced Rx FIFO Watermark interrupt is enabled
 */
#define CAN_ERFIER_ERFWMIIE(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFWMIIE_SHIFT)) & CAN_ERFIER_ERFWMIIE_MASK)

#define CAN_ERFIER_ERFOVFIE_MASK                 (0x40000000U)
#define CAN_ERFIER_ERFOVFIE_SHIFT                (30U)
/*! ERFOVFIE - Enhanced Rx FIFO Overflow Interrupt Enable
 *  0b0..Enhanced Rx FIFO Overflow is disabled
 *  0b1..Enhanced Rx FIFO Overflow is enabled
 */
#define CAN_ERFIER_ERFOVFIE(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFOVFIE_SHIFT)) & CAN_ERFIER_ERFOVFIE_MASK)

#define CAN_ERFIER_ERFUFWIE_MASK                 (0x80000000U)
#define CAN_ERFIER_ERFUFWIE_SHIFT                (31U)
/*! ERFUFWIE - Enhanced Rx FIFO Underflow Interrupt Enable
 *  0b0..Enhanced Rx FIFO Underflow interrupt is disabled
 *  0b1..Enhanced Rx FIFO Underflow interrupt is enabled
 */
#define CAN_ERFIER_ERFUFWIE(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFUFWIE_SHIFT)) & CAN_ERFIER_ERFUFWIE_MASK)
/*! @} */

/*! @name ERFSR - Enhanced Rx FIFO Status Register */
/*! @{ */

#define CAN_ERFSR_ERFEL_MASK                     (0x3FU)
#define CAN_ERFSR_ERFEL_SHIFT                    (0U)
/*! ERFEL - Enhanced Rx FIFO Elements
 */
#define CAN_ERFSR_ERFEL(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFEL_SHIFT)) & CAN_ERFSR_ERFEL_MASK)

#define CAN_ERFSR_ERFF_MASK                      (0x10000U)
#define CAN_ERFSR_ERFF_SHIFT                     (16U)
/*! ERFF - Enhanced Rx FIFO full
 *  0b0..Enhanced Rx FIFO is not full
 *  0b1..Enhanced Rx FIFO is full
 */
#define CAN_ERFSR_ERFF(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFF_SHIFT)) & CAN_ERFSR_ERFF_MASK)

#define CAN_ERFSR_ERFE_MASK                      (0x20000U)
#define CAN_ERFSR_ERFE_SHIFT                     (17U)
/*! ERFE - Enhanced Rx FIFO empty
 *  0b0..Enhanced Rx FIFO is not empty
 *  0b1..Enhanced Rx FIFO is empty
 */
#define CAN_ERFSR_ERFE(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFE_SHIFT)) & CAN_ERFSR_ERFE_MASK)

#define CAN_ERFSR_ERFCLR_MASK                    (0x8000000U)
#define CAN_ERFSR_ERFCLR_SHIFT                   (27U)
/*! ERFCLR - Enhanced Rx FIFO Clear
 *  0b0..No effect
 *  0b1..Clear Enhanced Rx FIFO content
 */
#define CAN_ERFSR_ERFCLR(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFCLR_SHIFT)) & CAN_ERFSR_ERFCLR_MASK)

#define CAN_ERFSR_ERFDA_MASK                     (0x10000000U)
#define CAN_ERFSR_ERFDA_SHIFT                    (28U)
/*! ERFDA - Enhanced Rx FIFO Data Available
 *  0b0..No such occurrence
 *  0b1..There is at least one message stored in Enhanced Rx FIFO
 */
#define CAN_ERFSR_ERFDA(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFDA_SHIFT)) & CAN_ERFSR_ERFDA_MASK)

#define CAN_ERFSR_ERFWMI_MASK                    (0x20000000U)
#define CAN_ERFSR_ERFWMI_SHIFT                   (29U)
/*! ERFWMI - Enhanced Rx FIFO Watermark Indication
 *  0b0..No such occurrence
 *  0b1..The number of messages in FIFO is greater than the watermark
 */
#define CAN_ERFSR_ERFWMI(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFWMI_SHIFT)) & CAN_ERFSR_ERFWMI_MASK)

#define CAN_ERFSR_ERFOVF_MASK                    (0x40000000U)
#define CAN_ERFSR_ERFOVF_SHIFT                   (30U)
/*! ERFOVF - Enhanced Rx FIFO Overflow
 *  0b0..No such occurrence
 *  0b1..Enhanced Rx FIFO overflow
 */
#define CAN_ERFSR_ERFOVF(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFOVF_SHIFT)) & CAN_ERFSR_ERFOVF_MASK)

#define CAN_ERFSR_ERFUFW_MASK                    (0x80000000U)
#define CAN_ERFSR_ERFUFW_SHIFT                   (31U)
/*! ERFUFW - Enhanced Rx FIFO Underflow
 *  0b0..No such occurrence
 *  0b1..Enhanced Rx FIFO underflow
 */
#define CAN_ERFSR_ERFUFW(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFUFW_SHIFT)) & CAN_ERFSR_ERFUFW_MASK)
/*! @} */

/*! @name ERFFEL - Enhanced Rx FIFO Filter Element */
/*! @{ */

#define CAN_ERFFEL_FEL_MASK                      (0xFFFFFFFFU)
#define CAN_ERFFEL_FEL_SHIFT                     (0U)
/*! FEL - Filter Element Bits
 */
#define CAN_ERFFEL_FEL(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ERFFEL_FEL_SHIFT)) & CAN_ERFFEL_FEL_MASK)
/*! @} */

/* The count of CAN_ERFFEL */
#define CAN_ERFFEL_COUNT                         (32U)


/*!
 * @}
 */ /* end of group CAN_Register_Masks */


/* CAN - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral CAN0 base address */
  #define CAN0_BASE                                (0x5003B000u)
  /** Peripheral CAN0 base address */
  #define CAN0_BASE_NS                             (0x4003B000u)
  /** Peripheral CAN0 base pointer */
  #define CAN0                                     ((CAN_Type *)CAN0_BASE)
  /** Peripheral CAN0 base pointer */
  #define CAN0_NS                                  ((CAN_Type *)CAN0_BASE_NS)
  /** Array initializer of CAN peripheral base addresses */
  #define CAN_BASE_ADDRS                           { CAN0_BASE }
  /** Array initializer of CAN peripheral base pointers */
  #define CAN_BASE_PTRS                            { CAN0 }
  /** Array initializer of CAN peripheral base addresses */
  #define CAN_BASE_ADDRS_NS                        { CAN0_BASE_NS }
  /** Array initializer of CAN peripheral base pointers */
  #define CAN_BASE_PTRS_NS                         { CAN0_NS }
#else
  /** Peripheral CAN0 base address */
  #define CAN0_BASE                                (0x4003B000u)
  /** Peripheral CAN0 base pointer */
  #define CAN0                                     ((CAN_Type *)CAN0_BASE)
  /** Array initializer of CAN peripheral base addresses */
  #define CAN_BASE_ADDRS                           { CAN0_BASE }
  /** Array initializer of CAN peripheral base pointers */
  #define CAN_BASE_PTRS                            { CAN0 }
#endif
/** Interrupt vectors for the CAN peripheral type */
#define CAN_Rx_Warning_IRQS                      { CAN0_IRQn }
#define CAN_Tx_Warning_IRQS                      { CAN0_IRQn }
#define CAN_Wake_Up_IRQS                         { CAN0_IRQn }
#define CAN_Error_IRQS                           { CAN0_IRQn }
#define CAN_Bus_Off_IRQS                         { CAN0_IRQn }
#define CAN_ORed_Message_buffer_IRQS             { CAN0_IRQn }

/*!
 * @}
 */ /* end of group CAN_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CCM32K Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CCM32K_Peripheral_Access_Layer CCM32K Peripheral Access Layer
 * @{
 */

/** CCM32K - Register Layout Typedef */
typedef struct {
  __IO uint32_t FRO32K_CTRL;                       /**< Free Running 32 kHz Oscillator Control Register, offset: 0x0 */
  __IO uint32_t FRO32K_TRIM;                       /**< Free Running 32 kHz Oscillator Trim Register, offset: 0x4 */
  __IO uint32_t OSC32K_CTRL;                       /**< 32 kHz OSC Control Register, offset: 0x8 */
  __I  uint32_t STATUS;                            /**< Status Register, offset: 0xC */
       uint8_t RESERVED_0[4];
  __IO uint32_t CLKMON_CTRL;                       /**< Clock Monitor Control Register, offset: 0x14 */
       uint8_t RESERVED_1[4];
  __IO uint32_t CGC32K;                            /**< 32 kHz Clock Gate Control Register, offset: 0x1C */
} CCM32K_Type;

/* ----------------------------------------------------------------------------
   -- CCM32K Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CCM32K_Register_Masks CCM32K Register Masks
 * @{
 */

/*! @name FRO32K_CTRL - Free Running 32 kHz Oscillator Control Register */
/*! @{ */

#define CCM32K_FRO32K_CTRL_FRO_EN_MASK           (0x1U)
#define CCM32K_FRO32K_CTRL_FRO_EN_SHIFT          (0U)
/*! FRO_EN - FRO Enable
 *  0b0..FRO is disabled
 *  0b1..FRO is enabled
 */
#define CCM32K_FRO32K_CTRL_FRO_EN(x)             (((uint32_t)(((uint32_t)(x)) << CCM32K_FRO32K_CTRL_FRO_EN_SHIFT)) & CCM32K_FRO32K_CTRL_FRO_EN_MASK)

#define CCM32K_FRO32K_CTRL_LOCK_EN_MASK          (0x80000000U)
#define CCM32K_FRO32K_CTRL_LOCK_EN_SHIFT         (31U)
/*! LOCK_EN - Write Access Lock
 *  0b0..Register write access is unlocked
 *  0b1..Register write access is locked
 */
#define CCM32K_FRO32K_CTRL_LOCK_EN(x)            (((uint32_t)(((uint32_t)(x)) << CCM32K_FRO32K_CTRL_LOCK_EN_SHIFT)) & CCM32K_FRO32K_CTRL_LOCK_EN_MASK)
/*! @} */

/*! @name FRO32K_TRIM - Free Running 32 kHz Oscillator Trim Register */
/*! @{ */

#define CCM32K_FRO32K_TRIM_FREQ_TRIM_MASK        (0x7FFU)
#define CCM32K_FRO32K_TRIM_FREQ_TRIM_SHIFT       (0U)
/*! FREQ_TRIM - Frequency Trim
 *  0b10000000000..Default trim value
 */
#define CCM32K_FRO32K_TRIM_FREQ_TRIM(x)          (((uint32_t)(((uint32_t)(x)) << CCM32K_FRO32K_TRIM_FREQ_TRIM_SHIFT)) & CCM32K_FRO32K_TRIM_FREQ_TRIM_MASK)

#define CCM32K_FRO32K_TRIM_IFR_DIS_MASK          (0x20000000U)
#define CCM32K_FRO32K_TRIM_IFR_DIS_SHIFT         (29U)
/*! IFR_DIS - IFR Loading Disable Control
 *  0b0..IFR loading is enabled
 *  0b1..IFR loading is disabled
 */
#define CCM32K_FRO32K_TRIM_IFR_DIS(x)            (((uint32_t)(((uint32_t)(x)) << CCM32K_FRO32K_TRIM_IFR_DIS_SHIFT)) & CCM32K_FRO32K_TRIM_IFR_DIS_MASK)

#define CCM32K_FRO32K_TRIM_LOCK_EN_MASK          (0x80000000U)
#define CCM32K_FRO32K_TRIM_LOCK_EN_SHIFT         (31U)
/*! LOCK_EN - Write Access Lock
 *  0b0..Register write access is unlocked
 *  0b1..Register write access is locked
 */
#define CCM32K_FRO32K_TRIM_LOCK_EN(x)            (((uint32_t)(((uint32_t)(x)) << CCM32K_FRO32K_TRIM_LOCK_EN_SHIFT)) & CCM32K_FRO32K_TRIM_LOCK_EN_MASK)
/*! @} */

/*! @name OSC32K_CTRL - 32 kHz OSC Control Register */
/*! @{ */

#define CCM32K_OSC32K_CTRL_OSC_EN_MASK           (0x1U)
#define CCM32K_OSC32K_CTRL_OSC_EN_SHIFT          (0U)
/*! OSC_EN - Crystal Oscillator Enable
 *  0b0..Oscillator is disabled
 *  0b1..Oscillator is enabled
 */
#define CCM32K_OSC32K_CTRL_OSC_EN(x)             (((uint32_t)(((uint32_t)(x)) << CCM32K_OSC32K_CTRL_OSC_EN_SHIFT)) & CCM32K_OSC32K_CTRL_OSC_EN_MASK)

#define CCM32K_OSC32K_CTRL_OSC_BYP_EN_MASK       (0x2U)
#define CCM32K_OSC32K_CTRL_OSC_BYP_EN_SHIFT      (1U)
/*! OSC_BYP_EN - Crystal Oscillator Bypass Enable
 *  0b0..Crystal oscillator is not bypassed
 *  0b1..Crystal oscillator is bypassed
 */
#define CCM32K_OSC32K_CTRL_OSC_BYP_EN(x)         (((uint32_t)(((uint32_t)(x)) << CCM32K_OSC32K_CTRL_OSC_BYP_EN_SHIFT)) & CCM32K_OSC32K_CTRL_OSC_BYP_EN_MASK)

#define CCM32K_OSC32K_CTRL_CAP_SEL_EN_MASK       (0x80U)
#define CCM32K_OSC32K_CTRL_CAP_SEL_EN_SHIFT      (7U)
/*! CAP_SEL_EN - Crystal Load Capacitance Selection Enable
 *  0b0..Internal capacitance bank is not enabled
 *  0b1..Internal capacitance bank is enabled
 */
#define CCM32K_OSC32K_CTRL_CAP_SEL_EN(x)         (((uint32_t)(((uint32_t)(x)) << CCM32K_OSC32K_CTRL_CAP_SEL_EN_SHIFT)) & CCM32K_OSC32K_CTRL_CAP_SEL_EN_MASK)

#define CCM32K_OSC32K_CTRL_EXTAL_CAP_SEL_MASK    (0xF00U)
#define CCM32K_OSC32K_CTRL_EXTAL_CAP_SEL_SHIFT   (8U)
/*! EXTAL_CAP_SEL - Crystal load capacitance selection bits
 *  0b0000..0 pF
 *  0b0001..2 pF
 *  0b0010..4 pF
 *  0b0011..6 pF
 *  0b0100..8 pF
 *  0b0101..10 pF
 *  0b0110..12 pF
 *  0b0111..14 pF
 *  0b1000..16 pF
 *  0b1001..18 pF
 *  0b1010..20 pF
 *  0b1011..22 pF
 *  0b1100..24 pF
 *  0b1101..26 pF
 *  0b1110..28 pF
 *  0b1111..30 pF
 */
#define CCM32K_OSC32K_CTRL_EXTAL_CAP_SEL(x)      (((uint32_t)(((uint32_t)(x)) << CCM32K_OSC32K_CTRL_EXTAL_CAP_SEL_SHIFT)) & CCM32K_OSC32K_CTRL_EXTAL_CAP_SEL_MASK)

#define CCM32K_OSC32K_CTRL_XTAL_CAP_SEL_MASK     (0xF000U)
#define CCM32K_OSC32K_CTRL_XTAL_CAP_SEL_SHIFT    (12U)
/*! XTAL_CAP_SEL - Crystal load capacitance selection bits
 *  0b0000..0 pF
 *  0b0001..2 pF
 *  0b0010..4 pF
 *  0b0011..6 pF
 *  0b0100..8 pF
 *  0b0101..10 pF
 *  0b0110..12 pF
 *  0b0111..14 pF
 *  0b1000..16 pF
 *  0b1001..18 pF
 *  0b1010..20 pF
 *  0b1011..22 pF
 *  0b1100..24 pF
 *  0b1101..26 pF
 *  0b1110..28 pF
 *  0b1111..30 pF
 */
#define CCM32K_OSC32K_CTRL_XTAL_CAP_SEL(x)       (((uint32_t)(((uint32_t)(x)) << CCM32K_OSC32K_CTRL_XTAL_CAP_SEL_SHIFT)) & CCM32K_OSC32K_CTRL_XTAL_CAP_SEL_MASK)

#define CCM32K_OSC32K_CTRL_COARSE_AMP_GAIN_MASK  (0x300000U)
#define CCM32K_OSC32K_CTRL_COARSE_AMP_GAIN_SHIFT (20U)
/*! COARSE_AMP_GAIN - Amplifier gain adjustment bits to allow the use of a wide range of external crystal ESR values.
 *  0b00..ESR_Range0
 *  0b01..ESR_Range1
 *  0b10..ESR_Range2
 *  0b11..ESR_Range3
 */
#define CCM32K_OSC32K_CTRL_COARSE_AMP_GAIN(x)    (((uint32_t)(((uint32_t)(x)) << CCM32K_OSC32K_CTRL_COARSE_AMP_GAIN_SHIFT)) & CCM32K_OSC32K_CTRL_COARSE_AMP_GAIN_MASK)

#define CCM32K_OSC32K_CTRL_SOX_EN_MASK           (0x1000000U)
#define CCM32K_OSC32K_CTRL_SOX_EN_SHIFT          (24U)
/*! SOX_EN - SOX Mode Enable
 *  0b1..SOX mode is enabled.
 *  0b0..SOX mode is disabled.
 */
#define CCM32K_OSC32K_CTRL_SOX_EN(x)             (((uint32_t)(((uint32_t)(x)) << CCM32K_OSC32K_CTRL_SOX_EN_SHIFT)) & CCM32K_OSC32K_CTRL_SOX_EN_MASK)

#define CCM32K_OSC32K_CTRL_LOCK_EN_MASK          (0x80000000U)
#define CCM32K_OSC32K_CTRL_LOCK_EN_SHIFT         (31U)
/*! LOCK_EN - Write Access Lock bit
 *  0b0..Register write access is unlocked
 *  0b1..Register write access is locked
 */
#define CCM32K_OSC32K_CTRL_LOCK_EN(x)            (((uint32_t)(((uint32_t)(x)) << CCM32K_OSC32K_CTRL_LOCK_EN_SHIFT)) & CCM32K_OSC32K_CTRL_LOCK_EN_MASK)
/*! @} */

/*! @name STATUS - Status Register */
/*! @{ */

#define CCM32K_STATUS_OSC32K_RDY_MASK            (0x1U)
#define CCM32K_STATUS_OSC32K_RDY_SHIFT           (0U)
/*! OSC32K_RDY - 32 kHz Oscillator ready bit.
 *  0b0..Clock output from crystal oscillator is not stable.
 *  0b1..Clock output from crystal oscillator is stable.
 */
#define CCM32K_STATUS_OSC32K_RDY(x)              (((uint32_t)(((uint32_t)(x)) << CCM32K_STATUS_OSC32K_RDY_SHIFT)) & CCM32K_STATUS_OSC32K_RDY_MASK)

#define CCM32K_STATUS_OSC32K_ACTIVE_MASK         (0x4U)
#define CCM32K_STATUS_OSC32K_ACTIVE_SHIFT        (2U)
/*! OSC32K_ACTIVE - 32 kHz Oscillator active bit
 *  0b1..OSC32K is the active clock source
 *  0b0..OSC32K is not the active clock source
 */
#define CCM32K_STATUS_OSC32K_ACTIVE(x)           (((uint32_t)(((uint32_t)(x)) << CCM32K_STATUS_OSC32K_ACTIVE_SHIFT)) & CCM32K_STATUS_OSC32K_ACTIVE_MASK)

#define CCM32K_STATUS_FRO32K_ACTIVE_MASK         (0x10U)
#define CCM32K_STATUS_FRO32K_ACTIVE_SHIFT        (4U)
/*! FRO32K_ACTIVE - 32 kHz FRO active bit
 *  0b1..FRO32K is the active clock source
 *  0b0..FRO32K is not the active clock source
 */
#define CCM32K_STATUS_FRO32K_ACTIVE(x)           (((uint32_t)(((uint32_t)(x)) << CCM32K_STATUS_FRO32K_ACTIVE_SHIFT)) & CCM32K_STATUS_FRO32K_ACTIVE_MASK)

#define CCM32K_STATUS_CLOCK_DET_MASK             (0x40U)
#define CCM32K_STATUS_CLOCK_DET_SHIFT            (6U)
/*! CLOCK_DET - Clock Detect
 *  0b1..Clock error is detected
 *  0b0..Clock error is not detected
 */
#define CCM32K_STATUS_CLOCK_DET(x)               (((uint32_t)(((uint32_t)(x)) << CCM32K_STATUS_CLOCK_DET_SHIFT)) & CCM32K_STATUS_CLOCK_DET_MASK)
/*! @} */

/*! @name CLKMON_CTRL - Clock Monitor Control Register */
/*! @{ */

#define CCM32K_CLKMON_CTRL_MON_EN_MASK           (0x1U)
#define CCM32K_CLKMON_CTRL_MON_EN_SHIFT          (0U)
/*! MON_EN - CLKMON Enable
 *  0b0..CLKMON is disabled
 *  0b1..CLKMON is enabled
 */
#define CCM32K_CLKMON_CTRL_MON_EN(x)             (((uint32_t)(((uint32_t)(x)) << CCM32K_CLKMON_CTRL_MON_EN_SHIFT)) & CCM32K_CLKMON_CTRL_MON_EN_MASK)

#define CCM32K_CLKMON_CTRL_FREQ_TRIM_MASK        (0x6U)
#define CCM32K_CLKMON_CTRL_FREQ_TRIM_SHIFT       (1U)
/*! FREQ_TRIM - Frequency trim bits
 *  0b00..Clock monitor asserts 2 cycle after expected edge (assert after 10 cycles with no edge)
 *  0b01..Clock monitor asserts 4 cycles after expected edge (assert after 12 cycles with no edge)
 *  0b10..Clock monitor asserts 6 cycles after expected edge (assert after 14 cycles with no edge)
 *  0b11..Clock monitor asserts 8 cycles after expected edge (assert after 16 cycles with no edge)
 */
#define CCM32K_CLKMON_CTRL_FREQ_TRIM(x)          (((uint32_t)(((uint32_t)(x)) << CCM32K_CLKMON_CTRL_FREQ_TRIM_SHIFT)) & CCM32K_CLKMON_CTRL_FREQ_TRIM_MASK)

#define CCM32K_CLKMON_CTRL_DIVIDE_TRIM_MASK      (0x18U)
#define CCM32K_CLKMON_CTRL_DIVIDE_TRIM_SHIFT     (3U)
/*! DIVIDE_TRIM - Divide Trim
 *  0b00..Clock monitor operates at 1 kHz for both FRO32K and OSC32K
 *  0b01..Clock monitor operates at 64 Hz for FRO32K and clock monitor operates at 1 kHz for OSC32K (Reserved)
 *  0b10..Clock monitor operates at 1 kHz for FRO32K and clock monitor operates at 64 Hz for OSC32K (Reserved)
 *  0b11..Clock monitor operates at 64 Hz for both FRO32K and OSC32K
 */
#define CCM32K_CLKMON_CTRL_DIVIDE_TRIM(x)        (((uint32_t)(((uint32_t)(x)) << CCM32K_CLKMON_CTRL_DIVIDE_TRIM_SHIFT)) & CCM32K_CLKMON_CTRL_DIVIDE_TRIM_MASK)

#define CCM32K_CLKMON_CTRL_LOCK_EN_MASK          (0x80000000U)
#define CCM32K_CLKMON_CTRL_LOCK_EN_SHIFT         (31U)
/*! LOCK_EN - Write Access Lock bit
 *  0b0..Register write access is unlocked
 *  0b1..Register write access is locked
 */
#define CCM32K_CLKMON_CTRL_LOCK_EN(x)            (((uint32_t)(((uint32_t)(x)) << CCM32K_CLKMON_CTRL_LOCK_EN_SHIFT)) & CCM32K_CLKMON_CTRL_LOCK_EN_MASK)
/*! @} */

/*! @name CGC32K - 32 kHz Clock Gate Control Register */
/*! @{ */

#define CCM32K_CGC32K_CLK_OE_32K_MASK            (0x1FU)
#define CCM32K_CGC32K_CLK_OE_32K_SHIFT           (0U)
/*! CLK_OE_32K - 32 kHz clock output enable bits
 *  0b00000..Clock output is disabled
 *  0b00001..Clock output is enabled
 */
#define CCM32K_CGC32K_CLK_OE_32K(x)              (((uint32_t)(((uint32_t)(x)) << CCM32K_CGC32K_CLK_OE_32K_SHIFT)) & CCM32K_CGC32K_CLK_OE_32K_MASK)

#define CCM32K_CGC32K_CLK_SEL_32K_MASK           (0x20U)
#define CCM32K_CGC32K_CLK_SEL_32K_SHIFT          (5U)
/*! CLK_SEL_32K - 32 kHz clock source selection bit
 *  0b0..FRO32K clock output is selected as clock source
 *  0b1..OSC32K clock output is selected as clock source
 */
#define CCM32K_CGC32K_CLK_SEL_32K(x)             (((uint32_t)(((uint32_t)(x)) << CCM32K_CGC32K_CLK_SEL_32K_SHIFT)) & CCM32K_CGC32K_CLK_SEL_32K_MASK)

#define CCM32K_CGC32K_LOCK_EN_MASK               (0x80000000U)
#define CCM32K_CGC32K_LOCK_EN_SHIFT              (31U)
/*! LOCK_EN - Write Access Lock bit
 *  0b0..Register write access is unlocked
 *  0b1..Register write access is locked
 */
#define CCM32K_CGC32K_LOCK_EN(x)                 (((uint32_t)(((uint32_t)(x)) << CCM32K_CGC32K_LOCK_EN_SHIFT)) & CCM32K_CGC32K_LOCK_EN_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group CCM32K_Register_Masks */


/* CCM32K - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral CCM32K base address */
  #define CCM32K_BASE                              (0x5001F000u)
  /** Peripheral CCM32K base address */
  #define CCM32K_BASE_NS                           (0x4001F000u)
  /** Peripheral CCM32K base pointer */
  #define CCM32K                                   ((CCM32K_Type *)CCM32K_BASE)
  /** Peripheral CCM32K base pointer */
  #define CCM32K_NS                                ((CCM32K_Type *)CCM32K_BASE_NS)
  /** Array initializer of CCM32K peripheral base addresses */
  #define CCM32K_BASE_ADDRS                        { CCM32K_BASE }
  /** Array initializer of CCM32K peripheral base pointers */
  #define CCM32K_BASE_PTRS                         { CCM32K }
  /** Array initializer of CCM32K peripheral base addresses */
  #define CCM32K_BASE_ADDRS_NS                     { CCM32K_BASE_NS }
  /** Array initializer of CCM32K peripheral base pointers */
  #define CCM32K_BASE_PTRS_NS                      { CCM32K_NS }
#else
  /** Peripheral CCM32K base address */
  #define CCM32K_BASE                              (0x4001F000u)
  /** Peripheral CCM32K base pointer */
  #define CCM32K                                   ((CCM32K_Type *)CCM32K_BASE)
  /** Array initializer of CCM32K peripheral base addresses */
  #define CCM32K_BASE_ADDRS                        { CCM32K_BASE }
  /** Array initializer of CCM32K peripheral base pointers */
  #define CCM32K_BASE_PTRS                         { CCM32K }
#endif

/*!
 * @}
 */ /* end of group CCM32K_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CIU2 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CIU2_Peripheral_Access_Layer CIU2 Peripheral Access Layer
 * @{
 */

/** CIU2 - Register Layout Typedef */
typedef struct {
  __IO uint32_t CIU2_CLK_ENABLE;                   /**< Clock enable, offset: 0x0 */
  __IO uint32_t CIU2_ECO_0;                        /**< ECO Register 0, offset: 0x4 */
  __IO uint32_t CIU2_ECO_1;                        /**< ECO Register 1, offset: 0x8 */
  __IO uint32_t CIU2_ECO_2;                        /**< ECO Register 2, offset: 0xC */
  __IO uint32_t CIU2_ECO_3;                        /**< ECO Register 3, offset: 0x10 */
  __IO uint32_t CIU2_ECO_4;                        /**< ECO Register 4, offset: 0x14 */
  __IO uint32_t CIU2_ECO_5;                        /**< ECO Register 5, offset: 0x18 */
  __IO uint32_t CIU2_ECO_6;                        /**< ECO Register 6, offset: 0x1C */
  __IO uint32_t CIU2_ECO_7;                        /**< ECO Register 7, offset: 0x20 */
  __IO uint32_t CIU2_ECO_8;                        /**< ECO Register 8, offset: 0x24 */
  __IO uint32_t CIU2_ECO_9;                        /**< ECO Register 9, offset: 0x28 */
  __IO uint32_t CIU2_ECO_10;                       /**< ECO Register 10, offset: 0x2C */
  __IO uint32_t CIU2_ECO_11;                       /**< ECO Register 11, offset: 0x30 */
  __IO uint32_t CIU2_ECO_12;                       /**< ECO Register 12, offset: 0x34 */
  __IO uint32_t CIU2_ECO_13;                       /**< ECO Register 13, offset: 0x38 */
  __IO uint32_t CIU2_ECO_14;                       /**< ECO Register 14, offset: 0x3C */
  __IO uint32_t CIU2_ECO_15;                       /**< ECO Register 15, offset: 0x40 */
       uint8_t RESERVED_0[188];
  __IO uint32_t CIU2_CLK_ENABLE4;                  /**< Clock Enable 4, offset: 0x100 */
  __IO uint32_t CIU2_CLK_ENABLE5;                  /**< Clock Enable 5, offset: 0x104 */
  __IO uint32_t CIU2_CLK_CPU2CLK_CTRL;             /**< CPU2_AHB2 Clock Control, offset: 0x108 */
  __IO uint32_t CIU2_CLK_UARTCLK_CTRL;             /**< UART Clock Control, offset: 0x10C */
  __IO uint32_t CIU2_CLK_LBU2_BTRTU1_CTRL;         /**< LBU2 BT_RTU1 Clock Control, offset: 0x110 */
       uint8_t RESERVED_1[4];
  __IO uint32_t CIU2_CLK_CP15_DIS3;                /**< Clock Auto Shut-off Enable3, offset: 0x118 */
  __IO uint32_t CIU2_RST_SW3;                      /**< Software Module Reset, offset: 0x11C */
  __IO uint32_t CIU2_MEM_WRTC3;                    /**< Memory WRTC Control 3, offset: 0x120 */
  __IO uint32_t CIU2_MEM_WRTC4;                    /**< Memory WRTC Control 4, offset: 0x124 */
  __IO uint32_t CIU2_MEM_PWDN3;                    /**< Memory Powerdown Control, offset: 0x128 */
       uint8_t RESERVED_2[20];
  __IO uint32_t CIU2_BLE_CTRL;                     /**< BLE Control and Status, offset: 0x140 */
  __I  uint32_t CIU2_AHB2_TO_LAST_ADDR;            /**< AHB2 Timeout Last Address, offset: 0x144 */
  __I  uint32_t CIU2_AHB2_TO_CUR_ADDR;             /**< AHB2 Current Timeout Address, offset: 0x148 */
  __IO uint32_t CIU2_AHB2_TO_CTRL;                 /**< AHB2 ARB Control, offset: 0x14C */
  __IO uint32_t CIU2_AHB2_SMU1_ACCESS_ADDR;        /**< AHB2 to SMU1 Accessible Address, offset: 0x150 */
  __IO uint32_t CIU2_AHB2_SMU1_ACCESS_MASK;        /**< AHB2 to SMU1 Accessible Mask, offset: 0x154 */
  __IO uint32_t CIU2_CPU2_FABRIC_ARB_CTRL;         /**< CPU2 fabric arbiter control, offset: 0x158 */
  __IO uint32_t CIU2_CPU2_ICODE_INV_ADDR_CTRL;     /**< CPU2 Icode invalid address access control, offset: 0x15C */
  __I  uint32_t CIU2_CPU2_ICODE_INV_ADDR;          /**< CPU2 Icode invalid address, offset: 0x160 */
  __IO uint32_t CIU2_CPU2_DCODE_INV_ADDR_CTRL;     /**< CPU2 Dcode invalid address access control, offset: 0x164 */
  __I  uint32_t CIU2_CPU2_DCODE_INV_ADDR;          /**< CPU2 Dcode invalid address, offset: 0x168 */
  __IO uint32_t CIU2_CPU_CPU2_CTRL;                /**< CPU2 control register, offset: 0x16C */
  __IO uint32_t CIU2_BRF_CTRL;                     /**< BRF Control and Status, offset: 0x170 */
  __IO uint32_t CIU2_BRF_EXTRA_PORT;               /**< BRF Extra Port Connection, offset: 0x174 */
       uint8_t RESERVED_3[4];
  __IO uint32_t CIU2_BRF_ECO_CTRL;                 /**< BRF ECO Control, offset: 0x17C */
  __IO uint32_t CIU2_BTU_CTRL;                     /**< BTU Control and Status, offset: 0x180 */
  __IO uint32_t CIU2_BT_PS;                        /**< BT Clock Power Save, offset: 0x184 */
  __IO uint32_t CIU2_BT_PS2;                       /**< BT Clock Power Save 2, offset: 0x188 */
  __IO uint32_t CIU2_BT_REF_CTRL;                  /**< BT Ref Control, offset: 0x18C */
       uint8_t RESERVED_4[4];
  __IO uint32_t CIU2_BT_PS3;                       /**< BT Clock Power Save 3, offset: 0x194 */
  __IO uint32_t CIU2_BTU_ECO_CTRL;                 /**< BTU ECO Control, offset: 0x198 */
       uint8_t RESERVED_5[4];
  __IO uint32_t CIU2_INT_MASK;                     /**< CIU2 Interrupt Mask, offset: 0x1A0 */
  __IO uint32_t CIU2_INT_SELECT;                   /**< CIU2 Interrupt Select, offset: 0x1A4 */
  __IO uint32_t CIU2_INT_EVENT_MASK;               /**< CIU2 Interrupt Event Mask, offset: 0x1A8 */
  __I  uint32_t CIU2_INT_STATUS;                   /**< CIU2 Interrupt Status, offset: 0x1AC */
  __IO uint32_t CPU2_ERR_INT_MASK;                 /**< CPU2 ERR Interrupt Mask, offset: 0x1B0 */
  __IO uint32_t CPU2_ERR_INT_SELECT;               /**< CPU2 ERR Interrupt Clear Select, offset: 0x1B4 */
  __IO uint32_t CPU2_ERR_INT_EVENT_MASK;           /**< CPU2 ERR Interrupt Event Mask, offset: 0x1B8 */
  __I  uint32_t CPU2_ERR_INT_STATUS;               /**< CPU2 ERR Interrupt Status, offset: 0x1BC */
  __IO uint32_t CPU2_ERR_INT2_MASK;                /**< CPU2 ERR Interrupt 2 Mask, offset: 0x1C0 */
  __IO uint32_t CPU2_ERR_INT2_SELECT;              /**< CPU2 ERR Interrupt 2 Clear Select, offset: 0x1C4 */
  __IO uint32_t CPU2_ERR_INT2_EVENT_MASK;          /**< CPU2 ERR Interrupt 2 Event Mask, offset: 0x1C8 */
  __I  uint32_t CPU2_ERR_INT2_STATUS;              /**< CPU2 ERR Interrupt 2 Status, offset: 0x1CC */
  __IO uint32_t CIU2_CPU_CPU2_MSG_CTRL;            /**< CPU2 message register, offset: 0x1D0 */
  __IO uint32_t CIU2_IMU_CPU1_WR_MSG_TO_CPU2;      /**< CPU1 write message to CPU2, offset: 0x1D4 */
  __I  uint32_t CIU2_IMU_CPU1_RD_MSG_FROM_CPU2;    /**< CPU1 read message from CPU2, offset: 0x1D8 */
  __I  uint32_t CIU2_IMU_CPU1_CPU2_MSG_FIFO_STATUS; /**< CPU1 to CPU2 message FIFO status, offset: 0x1DC */
  __IO uint32_t CIU2_IMU_CPU1_CPU2_MSG_FIFO_CNTL;  /**< CPU1 to CPU2 message FIFO control, offset: 0x1E0 */
  __I  uint32_t CIU2_IMU_CPU2_RD_MSG_FROM_CPU1_VAL_DBG; /**< CPU2 last message read (from cpu1), offset: 0x1E4 */
  __IO uint32_t CIU2_IMU_CPU2_WR_MSG_TO_CPU1;      /**< CPU2 write message to CPU1, offset: 0x1E8 */
  __I  uint32_t CIU2_IMU_CPU2_RD_MSG_FROM_CPU1;    /**< CPU2 read message from CPU1, offset: 0x1EC */
  __I  uint32_t CIU2_IMU_CPU2_CPU1_MSG_FIFO_STATUS; /**< CPU2 to CPU1 message FIFO status, offset: 0x1F0 */
  __IO uint32_t CIU2_IMU_CPU2_CPU1_MSG_FIFO_CNTL;  /**< CPU2 to CPU1 message FIFO control, offset: 0x1F4 */
  __I  uint32_t CIU2_IMU_CPU1_RD_MSG_FROM_CPU2_VAL_DBG; /**< CPU1 last message read (from cpu2), offset: 0x1F8 */
       uint8_t RESERVED_6[4];
  __IO uint32_t CIU2_BCA1_CPU2_INT_MASK;           /**< BCA1 to CPU2 Interrupt Mask, offset: 0x200 */
  __IO uint32_t CIU2_BCA1_CPU2_INT_SELECT;         /**< BCA1 to CPU2 Interrupt Select, offset: 0x204 */
  __IO uint32_t CIU2_BCA1_CPU2_INT_EVENT_MASK;     /**< BCA1 to CPU2 Interrupt Event Mask, offset: 0x208 */
  __I  uint32_t CIU2_BCA1_CPU2_INT_STATUS;         /**< BCA1 to CPU2 Interrupt Status, offset: 0x20C */
  __IO uint32_t CIU2_APU_BYPASS1;                  /**< CIU2 APU Bypass Register 1, offset: 0x210 */
  __IO uint32_t CIU2_CPU2_LMU_STA_BYPASS0;         /**< LMU static bank control byapss0 Register for CPU2 mem, offset: 0x214 */
  __IO uint32_t CIU2_CPU2_LMU_STA_BYPASS1;         /**< LMU static bank control byapss1 Register for CPU2, offset: 0x218 */
  __IO uint32_t CIU2_CPU2_LMU_STA_BYPASS2;         /**< LMU static bank byapss2 Register for CPU2, offset: 0x21C */
  __IO uint32_t CIU2_CPU2_LMU_G2BIST_CTRL_BYPASS;  /**< LMU G2Bist control byapss Register for CPU2, offset: 0x220 */
       uint8_t RESERVED_7[8];
  __IO uint32_t CIU2_APU_PWR_CTRL_BYPASS1;         /**< APU power control Bypass Register 1, offset: 0x22C */
  __IO uint32_t CIU2_AHB2AHB_BRIDGE_CTRL;          /**< AHB2AHB Bridge Control Register, offset: 0x230 */
  __IO uint32_t CIU2_AHB1_AHB2_TO_CLEAR;           /**< AHB1 AHB2 timeout logic clear register, offset: 0x234 */
  __I  uint32_t CIU2_CPU_CPU2_DBG_STAT;            /**< CPU2 debug register, offset: 0x238 */
  __IO uint32_t CIU2_CPU_CPU1_CTRL;                /**< CPU1 control register, offset: 0x23C */
  __IO uint32_t CIU2_TESTBUS_CTRL;                 /**< CPU2 debug register, offset: 0x240 */
       uint8_t RESERVED_8[12];
  __IO uint32_t CIU2_LBC_CTRL;                     /**< LBC Control and Status, offset: 0x250 */
  __IO uint32_t CIU2_LBC_SLPCLK_NCO;               /**< LBC NCO Step for Sleep Clock, offset: 0x254 */
} CIU2_Type;

/* ----------------------------------------------------------------------------
   -- CIU2 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CIU2_Register_Masks CIU2 Register Masks
 * @{
 */

/*! @name CIU2_CLK_ENABLE - Clock enable */
/*! @{ */

#define CIU2_CIU2_CLK_ENABLE_AHB2_CLK_ENABLE_MASK (0x20000000U)
#define CIU2_CIU2_CLK_ENABLE_AHB2_CLK_ENABLE_SHIFT (29U)
/*! ahb2_clk_enable - Clock ahb2_clk enable signal. Ahb2_clk enable. 1: enable, 0: disable
 */
#define CIU2_CIU2_CLK_ENABLE_AHB2_CLK_ENABLE(x)  (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE_AHB2_CLK_ENABLE_SHIFT)) & CIU2_CIU2_CLK_ENABLE_AHB2_CLK_ENABLE_MASK)

#define CIU2_CIU2_CLK_ENABLE_CPU1_DIV_CLK_ENABLE_MASK (0x40000000U)
#define CIU2_CIU2_CLK_ENABLE_CPU1_DIV_CLK_ENABLE_SHIFT (30U)
/*! cpu1_div_clk_enable - Clock cpu1_div_clk enable signal. cpu1_div_clk enable. 1: enable, 0: disable
 */
#define CIU2_CIU2_CLK_ENABLE_CPU1_DIV_CLK_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE_CPU1_DIV_CLK_ENABLE_SHIFT)) & CIU2_CIU2_CLK_ENABLE_CPU1_DIV_CLK_ENABLE_MASK)

#define CIU2_CIU2_CLK_ENABLE_SOC_AHB_CLK_SEL_MASK (0x80000000U)
#define CIU2_CIU2_CLK_ENABLE_SOC_AHB_CLK_SEL_SHIFT (31U)
/*! soc_ahb_clk_sel - Clock selection for soc_ahb_clk. 0: AHB2_CLK, 1: CPU1_CLK_DIV
 */
#define CIU2_CIU2_CLK_ENABLE_SOC_AHB_CLK_SEL(x)  (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE_SOC_AHB_CLK_SEL_SHIFT)) & CIU2_CIU2_CLK_ENABLE_SOC_AHB_CLK_SEL_MASK)
/*! @} */

/*! @name CIU2_ECO_0 - ECO Register 0 */
/*! @{ */

#define CIU2_CIU2_ECO_0_SPARE_MASK               (0xFFFFFFFFU)
#define CIU2_CIU2_ECO_0_SPARE_SHIFT              (0U)
/*! spare - Eco Reserve Register
 */
#define CIU2_CIU2_ECO_0_SPARE(x)                 (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_ECO_0_SPARE_SHIFT)) & CIU2_CIU2_ECO_0_SPARE_MASK)
/*! @} */

/*! @name CIU2_ECO_1 - ECO Register 1 */
/*! @{ */

#define CIU2_CIU2_ECO_1_SPARE_MASK               (0xFFFFFFFFU)
#define CIU2_CIU2_ECO_1_SPARE_SHIFT              (0U)
/*! spare - Eco Reserve Register
 */
#define CIU2_CIU2_ECO_1_SPARE(x)                 (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_ECO_1_SPARE_SHIFT)) & CIU2_CIU2_ECO_1_SPARE_MASK)
/*! @} */

/*! @name CIU2_ECO_2 - ECO Register 2 */
/*! @{ */

#define CIU2_CIU2_ECO_2_SPARE_MASK               (0xFFFFFFFFU)
#define CIU2_CIU2_ECO_2_SPARE_SHIFT              (0U)
/*! spare - Eco Reserve Register
 */
#define CIU2_CIU2_ECO_2_SPARE(x)                 (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_ECO_2_SPARE_SHIFT)) & CIU2_CIU2_ECO_2_SPARE_MASK)
/*! @} */

/*! @name CIU2_ECO_3 - ECO Register 3 */
/*! @{ */

#define CIU2_CIU2_ECO_3_SPARE_MASK               (0xFFFFFFFFU)
#define CIU2_CIU2_ECO_3_SPARE_SHIFT              (0U)
/*! spare - Eco Reserve Register
 */
#define CIU2_CIU2_ECO_3_SPARE(x)                 (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_ECO_3_SPARE_SHIFT)) & CIU2_CIU2_ECO_3_SPARE_MASK)
/*! @} */

/*! @name CIU2_ECO_4 - ECO Register 4 */
/*! @{ */

#define CIU2_CIU2_ECO_4_SPARE_MASK               (0xFFFFFFFFU)
#define CIU2_CIU2_ECO_4_SPARE_SHIFT              (0U)
/*! spare - Eco Reserve Register
 */
#define CIU2_CIU2_ECO_4_SPARE(x)                 (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_ECO_4_SPARE_SHIFT)) & CIU2_CIU2_ECO_4_SPARE_MASK)
/*! @} */

/*! @name CIU2_ECO_5 - ECO Register 5 */
/*! @{ */

#define CIU2_CIU2_ECO_5_SPARE_MASK               (0xFFFFFFFFU)
#define CIU2_CIU2_ECO_5_SPARE_SHIFT              (0U)
/*! spare - Eco Reserve Register
 */
#define CIU2_CIU2_ECO_5_SPARE(x)                 (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_ECO_5_SPARE_SHIFT)) & CIU2_CIU2_ECO_5_SPARE_MASK)
/*! @} */

/*! @name CIU2_ECO_6 - ECO Register 6 */
/*! @{ */

#define CIU2_CIU2_ECO_6_SPARE_MASK               (0xFFFFFFFFU)
#define CIU2_CIU2_ECO_6_SPARE_SHIFT              (0U)
/*! spare - Eco Reserve Register
 */
#define CIU2_CIU2_ECO_6_SPARE(x)                 (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_ECO_6_SPARE_SHIFT)) & CIU2_CIU2_ECO_6_SPARE_MASK)
/*! @} */

/*! @name CIU2_ECO_7 - ECO Register 7 */
/*! @{ */

#define CIU2_CIU2_ECO_7_SPARE_MASK               (0xFFFFFFFFU)
#define CIU2_CIU2_ECO_7_SPARE_SHIFT              (0U)
/*! spare - Eco Reserve Register
 */
#define CIU2_CIU2_ECO_7_SPARE(x)                 (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_ECO_7_SPARE_SHIFT)) & CIU2_CIU2_ECO_7_SPARE_MASK)
/*! @} */

/*! @name CIU2_ECO_8 - ECO Register 8 */
/*! @{ */

#define CIU2_CIU2_ECO_8_SPARE_MASK               (0xFFFFFFFFU)
#define CIU2_CIU2_ECO_8_SPARE_SHIFT              (0U)
/*! spare - Eco Reserve Register
 */
#define CIU2_CIU2_ECO_8_SPARE(x)                 (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_ECO_8_SPARE_SHIFT)) & CIU2_CIU2_ECO_8_SPARE_MASK)
/*! @} */

/*! @name CIU2_ECO_9 - ECO Register 9 */
/*! @{ */

#define CIU2_CIU2_ECO_9_SPARE_MASK               (0xFFFFFFFFU)
#define CIU2_CIU2_ECO_9_SPARE_SHIFT              (0U)
/*! spare - Eco Reserve Register
 */
#define CIU2_CIU2_ECO_9_SPARE(x)                 (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_ECO_9_SPARE_SHIFT)) & CIU2_CIU2_ECO_9_SPARE_MASK)
/*! @} */

/*! @name CIU2_ECO_10 - ECO Register 10 */
/*! @{ */

#define CIU2_CIU2_ECO_10_SPARE_MASK              (0xFFFFFFFFU)
#define CIU2_CIU2_ECO_10_SPARE_SHIFT             (0U)
/*! spare - Eco Reserve Register
 */
#define CIU2_CIU2_ECO_10_SPARE(x)                (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_ECO_10_SPARE_SHIFT)) & CIU2_CIU2_ECO_10_SPARE_MASK)
/*! @} */

/*! @name CIU2_ECO_11 - ECO Register 11 */
/*! @{ */

#define CIU2_CIU2_ECO_11_SPARE_MASK              (0xFFFFFFFFU)
#define CIU2_CIU2_ECO_11_SPARE_SHIFT             (0U)
/*! spare - Eco Reserve Register
 */
#define CIU2_CIU2_ECO_11_SPARE(x)                (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_ECO_11_SPARE_SHIFT)) & CIU2_CIU2_ECO_11_SPARE_MASK)
/*! @} */

/*! @name CIU2_ECO_12 - ECO Register 12 */
/*! @{ */

#define CIU2_CIU2_ECO_12_SPARE_MASK              (0xFFFFFFFFU)
#define CIU2_CIU2_ECO_12_SPARE_SHIFT             (0U)
/*! spare - Eco Reserve Register
 */
#define CIU2_CIU2_ECO_12_SPARE(x)                (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_ECO_12_SPARE_SHIFT)) & CIU2_CIU2_ECO_12_SPARE_MASK)
/*! @} */

/*! @name CIU2_ECO_13 - ECO Register 13 */
/*! @{ */

#define CIU2_CIU2_ECO_13_SPARE_MASK              (0xFFFFFFFFU)
#define CIU2_CIU2_ECO_13_SPARE_SHIFT             (0U)
/*! spare - Eco Reserve Register
 */
#define CIU2_CIU2_ECO_13_SPARE(x)                (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_ECO_13_SPARE_SHIFT)) & CIU2_CIU2_ECO_13_SPARE_MASK)
/*! @} */

/*! @name CIU2_ECO_14 - ECO Register 14 */
/*! @{ */

#define CIU2_CIU2_ECO_14_SPARE_MASK              (0xFFFFFFFFU)
#define CIU2_CIU2_ECO_14_SPARE_SHIFT             (0U)
/*! spare - Eco Reserve Register
 */
#define CIU2_CIU2_ECO_14_SPARE(x)                (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_ECO_14_SPARE_SHIFT)) & CIU2_CIU2_ECO_14_SPARE_MASK)
/*! @} */

/*! @name CIU2_ECO_15 - ECO Register 15 */
/*! @{ */

#define CIU2_CIU2_ECO_15_SPARE_MASK              (0xFFFFFFFFU)
#define CIU2_CIU2_ECO_15_SPARE_SHIFT             (0U)
/*! spare - Eco Reserve Register
 */
#define CIU2_CIU2_ECO_15_SPARE(x)                (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_ECO_15_SPARE_SHIFT)) & CIU2_CIU2_ECO_15_SPARE_MASK)
/*! @} */

/*! @name CIU2_CLK_ENABLE4 - Clock Enable 4 */
/*! @{ */

#define CIU2_CIU2_CLK_ENABLE4_BIST_AHB2_CLK_GATING_EN_MASK (0x1U)
#define CIU2_CIU2_CLK_ENABLE4_BIST_AHB2_CLK_GATING_EN_SHIFT (0U)
/*! bist_ahb2_clk_gating_en - CPU2 Redbist and Rombist Clock for ITCM/DTCM/SQU/BROM
 */
#define CIU2_CIU2_CLK_ENABLE4_BIST_AHB2_CLK_GATING_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE4_BIST_AHB2_CLK_GATING_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE4_BIST_AHB2_CLK_GATING_EN_MASK)

#define CIU2_CIU2_CLK_ENABLE4_BRU_AHB2_ADDR_MASK_DIS_MASK (0x2U)
#define CIU2_CIU2_CLK_ENABLE4_BRU_AHB2_ADDR_MASK_DIS_SHIFT (1U)
/*! bru_ahb2_addr_mask_dis - CPU2 ROM Address Mask Selection
 */
#define CIU2_CIU2_CLK_ENABLE4_BRU_AHB2_ADDR_MASK_DIS(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE4_BRU_AHB2_ADDR_MASK_DIS_SHIFT)) & CIU2_CIU2_CLK_ENABLE4_BRU_AHB2_ADDR_MASK_DIS_MASK)

#define CIU2_CIU2_CLK_ENABLE4_ITCM_AHB2_DYN_CLK_GATING_DIS_MASK (0x4U)
#define CIU2_CIU2_CLK_ENABLE4_ITCM_AHB2_DYN_CLK_GATING_DIS_SHIFT (2U)
/*! itcm_ahb2_dyn_clk_gating_dis - CPU2 ITCM Dynamic Clock Gating Feature
 */
#define CIU2_CIU2_CLK_ENABLE4_ITCM_AHB2_DYN_CLK_GATING_DIS(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE4_ITCM_AHB2_DYN_CLK_GATING_DIS_SHIFT)) & CIU2_CIU2_CLK_ENABLE4_ITCM_AHB2_DYN_CLK_GATING_DIS_MASK)

#define CIU2_CIU2_CLK_ENABLE4_DTCM_AHB2_DYN_CLK_GATING_DIS_MASK (0x8U)
#define CIU2_CIU2_CLK_ENABLE4_DTCM_AHB2_DYN_CLK_GATING_DIS_SHIFT (3U)
/*! dtcm_ahb2_dyn_clk_gating_dis - CPU2 DTCM Dynamic Clock Gating Feature
 */
#define CIU2_CIU2_CLK_ENABLE4_DTCM_AHB2_DYN_CLK_GATING_DIS(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE4_DTCM_AHB2_DYN_CLK_GATING_DIS_SHIFT)) & CIU2_CIU2_CLK_ENABLE4_DTCM_AHB2_DYN_CLK_GATING_DIS_MASK)

#define CIU2_CIU2_CLK_ENABLE4_BRU_AHB2_DYN_CLK_GATING_DIS_MASK (0x10U)
#define CIU2_CIU2_CLK_ENABLE4_BRU_AHB2_DYN_CLK_GATING_DIS_SHIFT (4U)
/*! bru_ahb2_dyn_clk_gating_dis - CPU2 ROM Dynamic Clock Gating Feature
 */
#define CIU2_CIU2_CLK_ENABLE4_BRU_AHB2_DYN_CLK_GATING_DIS(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE4_BRU_AHB2_DYN_CLK_GATING_DIS_SHIFT)) & CIU2_CIU2_CLK_ENABLE4_BRU_AHB2_DYN_CLK_GATING_DIS_MASK)

#define CIU2_CIU2_CLK_ENABLE4_SMU2_DYN_CLK_GATING_DIS_MASK (0x20U)
#define CIU2_CIU2_CLK_ENABLE4_SMU2_DYN_CLK_GATING_DIS_SHIFT (5U)
/*! smu2_dyn_clk_gating_dis - SMU2 Dynamic Clock Gating Feature
 */
#define CIU2_CIU2_CLK_ENABLE4_SMU2_DYN_CLK_GATING_DIS(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE4_SMU2_DYN_CLK_GATING_DIS_SHIFT)) & CIU2_CIU2_CLK_ENABLE4_SMU2_DYN_CLK_GATING_DIS_MASK)

#define CIU2_CIU2_CLK_ENABLE4_EBRAM_BIST_CLK_EN_MASK (0x100U)
#define CIU2_CIU2_CLK_ENABLE4_EBRAM_BIST_CLK_EN_SHIFT (8U)
/*! ebram_bist_clk_en - EBRAM BIST Clock Enable
 */
#define CIU2_CIU2_CLK_ENABLE4_EBRAM_BIST_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE4_EBRAM_BIST_CLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE4_EBRAM_BIST_CLK_EN_MASK)

#define CIU2_CIU2_CLK_ENABLE4_BT_ECLK_EN_MASK    (0x200U)
#define CIU2_CIU2_CLK_ENABLE4_BT_ECLK_EN_SHIFT   (9U)
/*! bt_eclk_en - BTU EBC Clock Enable
 */
#define CIU2_CIU2_CLK_ENABLE4_BT_ECLK_EN(x)      (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE4_BT_ECLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE4_BT_ECLK_EN_MASK)

#define CIU2_CIU2_CLK_ENABLE4_BT_4MCLK_EN_MASK   (0x400U)
#define CIU2_CIU2_CLK_ENABLE4_BT_4MCLK_EN_SHIFT  (10U)
/*! bt_4mclk_en - BTU 4 MHz Clock Enable
 */
#define CIU2_CIU2_CLK_ENABLE4_BT_4MCLK_EN(x)     (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE4_BT_4MCLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE4_BT_4MCLK_EN_MASK)

#define CIU2_CIU2_CLK_ENABLE4_BTU_AHB_CLK_EN_MASK (0x2000U)
#define CIU2_CIU2_CLK_ENABLE4_BTU_AHB_CLK_EN_SHIFT (13U)
/*! btu_ahb_clk_en - BTU AHB Clock Enable
 */
#define CIU2_CIU2_CLK_ENABLE4_BTU_AHB_CLK_EN(x)  (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE4_BTU_AHB_CLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE4_BTU_AHB_CLK_EN_MASK)

#define CIU2_CIU2_CLK_ENABLE4_SIU_CLK_EN_MASK    (0x4000U)
#define CIU2_CIU2_CLK_ENABLE4_SIU_CLK_EN_SHIFT   (14U)
/*! siu_clk_en - BT SIU (UART) clock enable
 */
#define CIU2_CIU2_CLK_ENABLE4_SIU_CLK_EN(x)      (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE4_SIU_CLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE4_SIU_CLK_EN_MASK)

#define CIU2_CIU2_CLK_ENABLE4_SMU2_AHB_CLK_EN_MASK (0x10000U)
#define CIU2_CIU2_CLK_ENABLE4_SMU2_AHB_CLK_EN_SHIFT (16U)
/*! smu2_ahb_clk_en - SMU2 AHB Clock Enable
 */
#define CIU2_CIU2_CLK_ENABLE4_SMU2_AHB_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE4_SMU2_AHB_CLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE4_SMU2_AHB_CLK_EN_MASK)

#define CIU2_CIU2_CLK_ENABLE4_HPU2_CIU_CLK_EN_MASK (0x80000U)
#define CIU2_CIU2_CLK_ENABLE4_HPU2_CIU_CLK_EN_SHIFT (19U)
/*! hpu2_ciu_clk_en - HPU2 CIU Clock Enable
 */
#define CIU2_CIU2_CLK_ENABLE4_HPU2_CIU_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE4_HPU2_CIU_CLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE4_HPU2_CIU_CLK_EN_MASK)

#define CIU2_CIU2_CLK_ENABLE4_BLE_AHB_CLK_EN_MASK (0x100000U)
#define CIU2_CIU2_CLK_ENABLE4_BLE_AHB_CLK_EN_SHIFT (20U)
/*! ble_ahb_clk_en - BLE ARM Clock Enable
 */
#define CIU2_CIU2_CLK_ENABLE4_BLE_AHB_CLK_EN(x)  (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE4_BLE_AHB_CLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE4_BLE_AHB_CLK_EN_MASK)

#define CIU2_CIU2_CLK_ENABLE4_BLE_SYS_CLK_EN_MASK (0x200000U)
#define CIU2_CIU2_CLK_ENABLE4_BLE_SYS_CLK_EN_SHIFT (21U)
/*! ble_sys_clk_en - BLE SYS Clock Enable
 */
#define CIU2_CIU2_CLK_ENABLE4_BLE_SYS_CLK_EN(x)  (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE4_BLE_SYS_CLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE4_BLE_SYS_CLK_EN_MASK)

#define CIU2_CIU2_CLK_ENABLE4_BLE_AEU_CLK_EN_MASK (0x400000U)
#define CIU2_CIU2_CLK_ENABLE4_BLE_AEU_CLK_EN_SHIFT (22U)
/*! ble_aeu_clk_en - BT/BLE AEU Clock Enable
 */
#define CIU2_CIU2_CLK_ENABLE4_BLE_AEU_CLK_EN(x)  (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE4_BLE_AEU_CLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE4_BLE_AEU_CLK_EN_MASK)

#define CIU2_CIU2_CLK_ENABLE4_BT_16M_CLK_EN_MASK (0x800000U)
#define CIU2_CIU2_CLK_ENABLE4_BT_16M_CLK_EN_SHIFT (23U)
/*! bt_16m_clk_en - BT 16MHz Clock Enable
 */
#define CIU2_CIU2_CLK_ENABLE4_BT_16M_CLK_EN(x)   (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE4_BT_16M_CLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE4_BT_16M_CLK_EN_MASK)

#define CIU2_CIU2_CLK_ENABLE4_DBUS_CLK_EN_MASK   (0x1000000U)
#define CIU2_CIU2_CLK_ENABLE4_DBUS_CLK_EN_SHIFT  (24U)
/*! dbus_clk_en - BLE DBUS Clock Enable
 */
#define CIU2_CIU2_CLK_ENABLE4_DBUS_CLK_EN(x)     (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE4_DBUS_CLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE4_DBUS_CLK_EN_MASK)

#define CIU2_CIU2_CLK_ENABLE4_SIU_AHB2_CLK_EN_MASK (0x20000000U)
#define CIU2_CIU2_CLK_ENABLE4_SIU_AHB2_CLK_EN_SHIFT (29U)
/*! siu_ahb2_clk_en - BT SIU (UART) AHB clock enable
 */
#define CIU2_CIU2_CLK_ENABLE4_SIU_AHB2_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE4_SIU_AHB2_CLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE4_SIU_AHB2_CLK_EN_MASK)

#define CIU2_CIU2_CLK_ENABLE4_BTRTU1_CLK_EN_MASK (0x40000000U)
#define CIU2_CIU2_CLK_ENABLE4_BTRTU1_CLK_EN_SHIFT (30U)
/*! btrtu1_clk_en - BT RTU1 clock enable
 */
#define CIU2_CIU2_CLK_ENABLE4_BTRTU1_CLK_EN(x)   (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE4_BTRTU1_CLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE4_BTRTU1_CLK_EN_MASK)
/*! @} */

/*! @name CIU2_CLK_ENABLE5 - Clock Enable 5 */
/*! @{ */

#define CIU2_CIU2_CLK_ENABLE5_ITCM_AHB2_CLK_EN_MASK (0x7U)
#define CIU2_CIU2_CLK_ENABLE5_ITCM_AHB2_CLK_EN_SHIFT (0U)
/*! itcm_ahb2_clk_en - Enable CPU2 ITCM Banks 1-2
 */
#define CIU2_CIU2_CLK_ENABLE5_ITCM_AHB2_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE5_ITCM_AHB2_CLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE5_ITCM_AHB2_CLK_EN_MASK)

#define CIU2_CIU2_CLK_ENABLE5_BT_ADMA_AHB_CLK_EN_MASK (0x8U)
#define CIU2_CIU2_CLK_ENABLE5_BT_ADMA_AHB_CLK_EN_SHIFT (3U)
/*! bt_adma_ahb_clk_en - BT ADMA AHB Clock Enable
 */
#define CIU2_CIU2_CLK_ENABLE5_BT_ADMA_AHB_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE5_BT_ADMA_AHB_CLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE5_BT_ADMA_AHB_CLK_EN_MASK)

#define CIU2_CIU2_CLK_ENABLE5_CIU2_REG_CLK_EN_MASK (0x80U)
#define CIU2_CIU2_CLK_ENABLE5_CIU2_REG_CLK_EN_SHIFT (7U)
/*! ciu2_reg_clk_en - CIU2 Reg Clock Enable
 */
#define CIU2_CIU2_CLK_ENABLE5_CIU2_REG_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE5_CIU2_REG_CLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE5_CIU2_REG_CLK_EN_MASK)

#define CIU2_CIU2_CLK_ENABLE5_BR_AHB2_CLK_EN_MASK (0x7FFF00U)
#define CIU2_CIU2_CLK_ENABLE5_BR_AHB2_CLK_EN_SHIFT (8U)
/*! br_ahb2_clk_en - CPU2 BROM AHB Clock Enable
 */
#define CIU2_CIU2_CLK_ENABLE5_BR_AHB2_CLK_EN(x)  (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE5_BR_AHB2_CLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE5_BR_AHB2_CLK_EN_MASK)

#define CIU2_CIU2_CLK_ENABLE5_BTU_MCLK_EN_MASK   (0x800000U)
#define CIU2_CIU2_CLK_ENABLE5_BTU_MCLK_EN_SHIFT  (23U)
/*! btu_mclk_en - BTU MCLK Enalbe
 */
#define CIU2_CIU2_CLK_ENABLE5_BTU_MCLK_EN(x)     (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE5_BTU_MCLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE5_BTU_MCLK_EN_MASK)

#define CIU2_CIU2_CLK_ENABLE5_SMU2_BANK_CLK_EN_MASK (0x7000000U)
#define CIU2_CIU2_CLK_ENABLE5_SMU2_BANK_CLK_EN_SHIFT (24U)
/*! smu2_bank_clk_en - SMU2 bank Clock Enable
 */
#define CIU2_CIU2_CLK_ENABLE5_SMU2_BANK_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE5_SMU2_BANK_CLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE5_SMU2_BANK_CLK_EN_MASK)

#define CIU2_CIU2_CLK_ENABLE5_SIF_CLK_SEL_MASK   (0x8000000U)
#define CIU2_CIU2_CLK_ENABLE5_SIF_CLK_SEL_SHIFT  (27U)
/*! sif_clk_sel - SIF Clock Select
 */
#define CIU2_CIU2_CLK_ENABLE5_SIF_CLK_SEL(x)     (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE5_SIF_CLK_SEL_SHIFT)) & CIU2_CIU2_CLK_ENABLE5_SIF_CLK_SEL_MASK)

#define CIU2_CIU2_CLK_ENABLE5_CPU2_GATEHCLK_EN_MASK (0x10000000U)
#define CIU2_CIU2_CLK_ENABLE5_CPU2_GATEHCLK_EN_SHIFT (28U)
#define CIU2_CIU2_CLK_ENABLE5_CPU2_GATEHCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE5_CPU2_GATEHCLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE5_CPU2_GATEHCLK_EN_MASK)

#define CIU2_CIU2_CLK_ENABLE5_CPU2_FABRIC_CLK_EN_MASK (0x20000000U)
#define CIU2_CIU2_CLK_ENABLE5_CPU2_FABRIC_CLK_EN_SHIFT (29U)
#define CIU2_CIU2_CLK_ENABLE5_CPU2_FABRIC_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE5_CPU2_FABRIC_CLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE5_CPU2_FABRIC_CLK_EN_MASK)

#define CIU2_CIU2_CLK_ENABLE5_CPU2_MEM_SLV_CLK_EN_MASK (0x40000000U)
#define CIU2_CIU2_CLK_ENABLE5_CPU2_MEM_SLV_CLK_EN_SHIFT (30U)
#define CIU2_CIU2_CLK_ENABLE5_CPU2_MEM_SLV_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE5_CPU2_MEM_SLV_CLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE5_CPU2_MEM_SLV_CLK_EN_MASK)

#define CIU2_CIU2_CLK_ENABLE5_SIF_AHB2_CLK_EN_MASK (0x80000000U)
#define CIU2_CIU2_CLK_ENABLE5_SIF_AHB2_CLK_EN_SHIFT (31U)
/*! sif_ahb2_clk_en - SIF ahb2 Clock Enalbe
 */
#define CIU2_CIU2_CLK_ENABLE5_SIF_AHB2_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_ENABLE5_SIF_AHB2_CLK_EN_SHIFT)) & CIU2_CIU2_CLK_ENABLE5_SIF_AHB2_CLK_EN_MASK)
/*! @} */

/*! @name CIU2_CLK_CPU2CLK_CTRL - CPU2_AHB2 Clock Control */
/*! @{ */

#define CIU2_CIU2_CLK_CPU2CLK_CTRL_T1_FREQ_SEL_MASK (0xFU)
#define CIU2_CIU2_CLK_CPU2CLK_CTRL_T1_FREQ_SEL_SHIFT (0U)
/*! t1_freq_sel - AHB2 Clock Frequency Select
 */
#define CIU2_CIU2_CLK_CPU2CLK_CTRL_T1_FREQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_CPU2CLK_CTRL_T1_FREQ_SEL_SHIFT)) & CIU2_CIU2_CLK_CPU2CLK_CTRL_T1_FREQ_SEL_MASK)
/*! @} */

/*! @name CIU2_CLK_UARTCLK_CTRL - UART Clock Control */
/*! @{ */

#define CIU2_CIU2_CLK_UARTCLK_CTRL_REFCLK_SEL_MASK (0x1U)
#define CIU2_CIU2_CLK_UARTCLK_CTRL_REFCLK_SEL_SHIFT (0U)
/*! refclk_sel - Reference Clock Select
 */
#define CIU2_CIU2_CLK_UARTCLK_CTRL_REFCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_UARTCLK_CTRL_REFCLK_SEL_SHIFT)) & CIU2_CIU2_CLK_UARTCLK_CTRL_REFCLK_SEL_MASK)

#define CIU2_CIU2_CLK_UARTCLK_CTRL_NCO_STEP_SIZE_MASK (0xFFFFFF80U)
#define CIU2_CIU2_CLK_UARTCLK_CTRL_NCO_STEP_SIZE_SHIFT (7U)
/*! nco_step_size - Programmable UART Clock Frequency
 */
#define CIU2_CIU2_CLK_UARTCLK_CTRL_NCO_STEP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_UARTCLK_CTRL_NCO_STEP_SIZE_SHIFT)) & CIU2_CIU2_CLK_UARTCLK_CTRL_NCO_STEP_SIZE_MASK)
/*! @} */

/*! @name CIU2_CLK_LBU2_BTRTU1_CTRL - LBU2 BT_RTU1 Clock Control */
/*! @{ */

#define CIU2_CIU2_CLK_LBU2_BTRTU1_CTRL_LBU2_USE_REFCLK_MASK (0x2U)
#define CIU2_CIU2_CLK_LBU2_BTRTU1_CTRL_LBU2_USE_REFCLK_SHIFT (1U)
/*! lbu2_use_refclk - Static bit set by FW based on Reference Clock Frequency. If reference clock
 *    frequency is lower and LBU can not support high baud rate of UART, then FW will set
 *    soc_use_ref_mode = 0. This is an indication for Bluetooth subsystem that there is some IP which need PLL
 *    to function which is LBU in this case.
 */
#define CIU2_CIU2_CLK_LBU2_BTRTU1_CTRL_LBU2_USE_REFCLK(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_LBU2_BTRTU1_CTRL_LBU2_USE_REFCLK_SHIFT)) & CIU2_CIU2_CLK_LBU2_BTRTU1_CTRL_LBU2_USE_REFCLK_MASK)

#define CIU2_CIU2_CLK_LBU2_BTRTU1_CTRL_BTRTU1_TIMER1_USE_SLP_CLK_MASK (0x800U)
#define CIU2_CIU2_CLK_LBU2_BTRTU1_CTRL_BTRTU1_TIMER1_USE_SLP_CLK_SHIFT (11U)
/*! btrtu1_timer1_use_slp_clk - Timer 1 BT_RTU1 Clock
 */
#define CIU2_CIU2_CLK_LBU2_BTRTU1_CTRL_BTRTU1_TIMER1_USE_SLP_CLK(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_LBU2_BTRTU1_CTRL_BTRTU1_TIMER1_USE_SLP_CLK_SHIFT)) & CIU2_CIU2_CLK_LBU2_BTRTU1_CTRL_BTRTU1_TIMER1_USE_SLP_CLK_MASK)

#define CIU2_CIU2_CLK_LBU2_BTRTU1_CTRL_BTRTU1_USE_REF_CLK_MASK (0x1000U)
#define CIU2_CIU2_CLK_LBU2_BTRTU1_CTRL_BTRTU1_USE_REF_CLK_SHIFT (12U)
/*! btrtu1_use_ref_clk - Static bit set by FW. If it is required that timers need not be programmed
 *    with dynamic switching of T1/Reference, the BT_RTU1 source clock is set on reference clock so
 *    that the timer are not distrubed.
 */
#define CIU2_CIU2_CLK_LBU2_BTRTU1_CTRL_BTRTU1_USE_REF_CLK(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_LBU2_BTRTU1_CTRL_BTRTU1_USE_REF_CLK_SHIFT)) & CIU2_CIU2_CLK_LBU2_BTRTU1_CTRL_BTRTU1_USE_REF_CLK_MASK)

#define CIU2_CIU2_CLK_LBU2_BTRTU1_CTRL_BTRTU1_DBG_CLK_CTRL_MASK (0x8000U)
#define CIU2_CIU2_CLK_LBU2_BTRTU1_CTRL_BTRTU1_DBG_CLK_CTRL_SHIFT (15U)
#define CIU2_CIU2_CLK_LBU2_BTRTU1_CTRL_BTRTU1_DBG_CLK_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_LBU2_BTRTU1_CTRL_BTRTU1_DBG_CLK_CTRL_SHIFT)) & CIU2_CIU2_CLK_LBU2_BTRTU1_CTRL_BTRTU1_DBG_CLK_CTRL_MASK)
/*! @} */

/*! @name CIU2_CLK_CP15_DIS3 - Clock Auto Shut-off Enable3 */
/*! @{ */

#define CIU2_CIU2_CLK_CP15_DIS3_BR_AHB2_CLK_MASK (0xFFFFU)
#define CIU2_CIU2_CLK_CP15_DIS3_BR_AHB2_CLK_SHIFT (0U)
/*! br_ahb2_clk - BRU_AHB2 Shut Off
 */
#define CIU2_CIU2_CLK_CP15_DIS3_BR_AHB2_CLK(x)   (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_CP15_DIS3_BR_AHB2_CLK_SHIFT)) & CIU2_CIU2_CLK_CP15_DIS3_BR_AHB2_CLK_MASK)

#define CIU2_CIU2_CLK_CP15_DIS3_IMEM_AHB2_CLK_MASK (0x1E00000U)
#define CIU2_CIU2_CLK_CP15_DIS3_IMEM_AHB2_CLK_SHIFT (21U)
/*! imem_ahb2_clk - IMEM_AHB2 Shut Off
 */
#define CIU2_CIU2_CLK_CP15_DIS3_IMEM_AHB2_CLK(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_CP15_DIS3_IMEM_AHB2_CLK_SHIFT)) & CIU2_CIU2_CLK_CP15_DIS3_IMEM_AHB2_CLK_MASK)

#define CIU2_CIU2_CLK_CP15_DIS3_DMEM_AHB2_CLK_MASK (0x6000000U)
#define CIU2_CIU2_CLK_CP15_DIS3_DMEM_AHB2_CLK_SHIFT (25U)
/*! dmem_ahb2_clk - DMEM_AHB2 Shut Off
 */
#define CIU2_CIU2_CLK_CP15_DIS3_DMEM_AHB2_CLK(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_CP15_DIS3_DMEM_AHB2_CLK_SHIFT)) & CIU2_CIU2_CLK_CP15_DIS3_DMEM_AHB2_CLK_MASK)

#define CIU2_CIU2_CLK_CP15_DIS3_ARB_AHB2_CLK_MASK (0x10000000U)
#define CIU2_CIU2_CLK_CP15_DIS3_ARB_AHB2_CLK_SHIFT (28U)
/*! arb_ahb2_clk - AHB2 Arbiter Shut Off
 */
#define CIU2_CIU2_CLK_CP15_DIS3_ARB_AHB2_CLK(x)  (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_CP15_DIS3_ARB_AHB2_CLK_SHIFT)) & CIU2_CIU2_CLK_CP15_DIS3_ARB_AHB2_CLK_MASK)

#define CIU2_CIU2_CLK_CP15_DIS3_DEC_AHB2_CLK_MASK (0x20000000U)
#define CIU2_CIU2_CLK_CP15_DIS3_DEC_AHB2_CLK_SHIFT (29U)
/*! dec_ahb2_clk - AHB2 Decoder Shut Off
 */
#define CIU2_CIU2_CLK_CP15_DIS3_DEC_AHB2_CLK(x)  (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_CP15_DIS3_DEC_AHB2_CLK_SHIFT)) & CIU2_CIU2_CLK_CP15_DIS3_DEC_AHB2_CLK_MASK)

#define CIU2_CIU2_CLK_CP15_DIS3_BTU_AHB_CLK_MASK (0x40000000U)
#define CIU2_CIU2_CLK_CP15_DIS3_BTU_AHB_CLK_SHIFT (30U)
/*! btu_ahb_clk - BTU Shut Off
 */
#define CIU2_CIU2_CLK_CP15_DIS3_BTU_AHB_CLK(x)   (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_CP15_DIS3_BTU_AHB_CLK_SHIFT)) & CIU2_CIU2_CLK_CP15_DIS3_BTU_AHB_CLK_MASK)

#define CIU2_CIU2_CLK_CP15_DIS3_BLE_AHB_CLK_MASK (0x80000000U)
#define CIU2_CIU2_CLK_CP15_DIS3_BLE_AHB_CLK_SHIFT (31U)
/*! ble_ahb_clk - BLE Shut Off
 */
#define CIU2_CIU2_CLK_CP15_DIS3_BLE_AHB_CLK(x)   (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CLK_CP15_DIS3_BLE_AHB_CLK_SHIFT)) & CIU2_CIU2_CLK_CP15_DIS3_BLE_AHB_CLK_MASK)
/*! @} */

/*! @name CIU2_RST_SW3 - Software Module Reset */
/*! @{ */

#define CIU2_CIU2_RST_SW3_BTU_AHB_CLK__MASK      (0x1U)
#define CIU2_CIU2_RST_SW3_BTU_AHB_CLK__SHIFT     (0U)
/*! btu_ahb_clk_ - BTU (ARM_Clk) Soft Reset
 */
#define CIU2_CIU2_RST_SW3_BTU_AHB_CLK_(x)        (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW3_BTU_AHB_CLK__SHIFT)) & CIU2_CIU2_RST_SW3_BTU_AHB_CLK__MASK)

#define CIU2_CIU2_RST_SW3_BLE_SOC__MASK          (0x2U)
#define CIU2_CIU2_RST_SW3_BLE_SOC__SHIFT         (1U)
/*! ble_soc_ - BLE SoC Soft Reset
 */
#define CIU2_CIU2_RST_SW3_BLE_SOC_(x)            (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW3_BLE_SOC__SHIFT)) & CIU2_CIU2_RST_SW3_BLE_SOC__MASK)

#define CIU2_CIU2_RST_SW3_BT_COMMON__MASK        (0x4U)
#define CIU2_CIU2_RST_SW3_BT_COMMON__SHIFT       (2U)
/*! bt_common_ - BT Common Soft Rest
 */
#define CIU2_CIU2_RST_SW3_BT_COMMON_(x)          (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW3_BT_COMMON__SHIFT)) & CIU2_CIU2_RST_SW3_BT_COMMON__MASK)

#define CIU2_CIU2_RST_SW3_CPU2_CORE__MASK        (0x10U)
#define CIU2_CIU2_RST_SW3_CPU2_CORE__SHIFT       (4U)
/*! cpu2_core_ - CPU2 core reset
 */
#define CIU2_CIU2_RST_SW3_CPU2_CORE_(x)          (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW3_CPU2_CORE__SHIFT)) & CIU2_CIU2_RST_SW3_CPU2_CORE__MASK)

#define CIU2_CIU2_RST_SW3_CPU2_TCM__MASK         (0x20U)
#define CIU2_CIU2_RST_SW3_CPU2_TCM__SHIFT        (5U)
/*! cpu2_tcm_ - CPU2 TCM/DMA/Arbiter reset
 */
#define CIU2_CIU2_RST_SW3_CPU2_TCM_(x)           (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW3_CPU2_TCM__SHIFT)) & CIU2_CIU2_RST_SW3_CPU2_TCM__MASK)

#define CIU2_CIU2_RST_SW3_ARB_AHB2_CLK__MASK     (0x80U)
#define CIU2_CIU2_RST_SW3_ARB_AHB2_CLK__SHIFT    (7U)
/*! arb_ahb2_clk_ - AHB2 Arbiter Soft Reset
 */
#define CIU2_CIU2_RST_SW3_ARB_AHB2_CLK_(x)       (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW3_ARB_AHB2_CLK__SHIFT)) & CIU2_CIU2_RST_SW3_ARB_AHB2_CLK__MASK)

#define CIU2_CIU2_RST_SW3_DEC_AHB2_CLK__MASK     (0x100U)
#define CIU2_CIU2_RST_SW3_DEC_AHB2_CLK__SHIFT    (8U)
/*! dec_ahb2_clk_ - AHB2 Decoder Mux Soft Reset
 */
#define CIU2_CIU2_RST_SW3_DEC_AHB2_CLK_(x)       (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW3_DEC_AHB2_CLK__SHIFT)) & CIU2_CIU2_RST_SW3_DEC_AHB2_CLK__MASK)

#define CIU2_CIU2_RST_SW3_BRU_AHB2_CLK__MASK     (0x200U)
#define CIU2_CIU2_RST_SW3_BRU_AHB2_CLK__SHIFT    (9U)
/*! bru_ahb2_clk_ - BRU_AHB2 Soft Reset
 */
#define CIU2_CIU2_RST_SW3_BRU_AHB2_CLK_(x)       (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW3_BRU_AHB2_CLK__SHIFT)) & CIU2_CIU2_RST_SW3_BRU_AHB2_CLK__MASK)

#define CIU2_CIU2_RST_SW3_BT_UART_N_MASK         (0x400U)
#define CIU2_CIU2_RST_SW3_BT_UART_N_SHIFT        (10U)
/*! bt_uart_n - BT UART soft reset
 */
#define CIU2_CIU2_RST_SW3_BT_UART_N(x)           (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW3_BT_UART_N_SHIFT)) & CIU2_CIU2_RST_SW3_BT_UART_N_MASK)

#define CIU2_CIU2_RST_SW3_SIU_AHB2_CLK_N_MASK    (0x800U)
#define CIU2_CIU2_RST_SW3_SIU_AHB2_CLK_N_SHIFT   (11U)
/*! siu_ahb2_clk_n - BT SIU (UART) AHB soft reset
 */
#define CIU2_CIU2_RST_SW3_SIU_AHB2_CLK_N(x)      (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW3_SIU_AHB2_CLK_N_SHIFT)) & CIU2_CIU2_RST_SW3_SIU_AHB2_CLK_N_MASK)

#define CIU2_CIU2_RST_SW3_SMU2_AHB_CLK__MASK     (0x10000U)
#define CIU2_CIU2_RST_SW3_SMU2_AHB_CLK__SHIFT    (16U)
/*! smu2_ahb_clk_ - SMU2 (AHB_Clk) Soft Reset
 */
#define CIU2_CIU2_RST_SW3_SMU2_AHB_CLK_(x)       (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW3_SMU2_AHB_CLK__SHIFT)) & CIU2_CIU2_RST_SW3_SMU2_AHB_CLK__MASK)

#define CIU2_CIU2_RST_SW3_SIF__MASK              (0x40000U)
#define CIU2_CIU2_RST_SW3_SIF__SHIFT             (18U)
/*! sif_ - sif clock Soft Reset
 */
#define CIU2_CIU2_RST_SW3_SIF_(x)                (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW3_SIF__SHIFT)) & CIU2_CIU2_RST_SW3_SIF__MASK)

#define CIU2_CIU2_RST_SW3_SIF_AHB2_CLK__MASK     (0x80000U)
#define CIU2_CIU2_RST_SW3_SIF_AHB2_CLK__SHIFT    (19U)
/*! sif_ahb2_clk_ - sif ahb2 Clock Soft Reset
 */
#define CIU2_CIU2_RST_SW3_SIF_AHB2_CLK_(x)       (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW3_SIF_AHB2_CLK__SHIFT)) & CIU2_CIU2_RST_SW3_SIF_AHB2_CLK__MASK)

#define CIU2_CIU2_RST_SW3_HPU2__MASK             (0x100000U)
#define CIU2_CIU2_RST_SW3_HPU2__SHIFT            (20U)
/*! hpu2_ - HPU2 Reset
 */
#define CIU2_CIU2_RST_SW3_HPU2_(x)               (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW3_HPU2__SHIFT)) & CIU2_CIU2_RST_SW3_HPU2__MASK)

#define CIU2_CIU2_RST_SW3_CIU2_AHB_CLK__MASK     (0x400000U)
#define CIU2_CIU2_RST_SW3_CIU2_AHB_CLK__SHIFT    (22U)
/*! ciu2_ahb_clk_ - CIU2 AHB Soft Reset
 */
#define CIU2_CIU2_RST_SW3_CIU2_AHB_CLK_(x)       (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW3_CIU2_AHB_CLK__SHIFT)) & CIU2_CIU2_RST_SW3_CIU2_AHB_CLK__MASK)

#define CIU2_CIU2_RST_SW3_BRF_PR__MASK           (0x4000000U)
#define CIU2_CIU2_RST_SW3_BRF_PR__SHIFT          (26U)
/*! brf_pr_ - BRF_PR Reset
 */
#define CIU2_CIU2_RST_SW3_BRF_PR_(x)             (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW3_BRF_PR__SHIFT)) & CIU2_CIU2_RST_SW3_BRF_PR__MASK)

#define CIU2_CIU2_RST_SW3_WD2_CHIP_RST_DISABLE_MASK (0x10000000U)
#define CIU2_CIU2_RST_SW3_WD2_CHIP_RST_DISABLE_SHIFT (28U)
#define CIU2_CIU2_RST_SW3_WD2_CHIP_RST_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW3_WD2_CHIP_RST_DISABLE_SHIFT)) & CIU2_CIU2_RST_SW3_WD2_CHIP_RST_DISABLE_MASK)

#define CIU2_CIU2_RST_SW3_WD2_CPU2_RST_DISABLE_MASK (0x20000000U)
#define CIU2_CIU2_RST_SW3_WD2_CPU2_RST_DISABLE_SHIFT (29U)
#define CIU2_CIU2_RST_SW3_WD2_CPU2_RST_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW3_WD2_CPU2_RST_DISABLE_SHIFT)) & CIU2_CIU2_RST_SW3_WD2_CPU2_RST_DISABLE_MASK)

#define CIU2_CIU2_RST_SW3_BT_16M_CLK__MASK       (0x40000000U)
#define CIU2_CIU2_RST_SW3_BT_16M_CLK__SHIFT      (30U)
/*! bt_16m_clk_ - Bt 16M clock reset
 */
#define CIU2_CIU2_RST_SW3_BT_16M_CLK_(x)         (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW3_BT_16M_CLK__SHIFT)) & CIU2_CIU2_RST_SW3_BT_16M_CLK__MASK)

#define CIU2_CIU2_RST_SW3_BT_ADMA__MASK          (0x80000000U)
#define CIU2_CIU2_RST_SW3_BT_ADMA__SHIFT         (31U)
/*! bt_adma_ - BT ADMA Soft Reset
 */
#define CIU2_CIU2_RST_SW3_BT_ADMA_(x)            (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_RST_SW3_BT_ADMA__SHIFT)) & CIU2_CIU2_RST_SW3_BT_ADMA__MASK)
/*! @} */

/*! @name CIU2_MEM_WRTC3 - Memory WRTC Control 3 */
/*! @{ */

#define CIU2_CIU2_MEM_WRTC3_BLE_ROM_RTC_MASK     (0x700U)
#define CIU2_CIU2_MEM_WRTC3_BLE_ROM_RTC_SHIFT    (8U)
/*! ble_rom_rtc - BLE ROM RTC
 */
#define CIU2_CIU2_MEM_WRTC3_BLE_ROM_RTC(x)       (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_WRTC3_BLE_ROM_RTC_SHIFT)) & CIU2_CIU2_MEM_WRTC3_BLE_ROM_RTC_MASK)

#define CIU2_CIU2_MEM_WRTC3_BLE_ROM_RTC_REF_MASK (0x3000U)
#define CIU2_CIU2_MEM_WRTC3_BLE_ROM_RTC_REF_SHIFT (12U)
/*! ble_rom_rtc_ref - BLE ROM RTC_REF
 */
#define CIU2_CIU2_MEM_WRTC3_BLE_ROM_RTC_REF(x)   (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_WRTC3_BLE_ROM_RTC_REF_SHIFT)) & CIU2_CIU2_MEM_WRTC3_BLE_ROM_RTC_REF_MASK)
/*! @} */

/*! @name CIU2_MEM_WRTC4 - Memory WRTC Control 4 */
/*! @{ */

#define CIU2_CIU2_MEM_WRTC4_CPU2_ITCM_RTC_MASK   (0x3U)
#define CIU2_CIU2_MEM_WRTC4_CPU2_ITCM_RTC_SHIFT  (0U)
/*! cpu2_itcm_rtc - CPU2 ITCM RTC
 */
#define CIU2_CIU2_MEM_WRTC4_CPU2_ITCM_RTC(x)     (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_WRTC4_CPU2_ITCM_RTC_SHIFT)) & CIU2_CIU2_MEM_WRTC4_CPU2_ITCM_RTC_MASK)

#define CIU2_CIU2_MEM_WRTC4_CPU2_ITCM_WTC_MASK   (0xCU)
#define CIU2_CIU2_MEM_WRTC4_CPU2_ITCM_WTC_SHIFT  (2U)
/*! cpu2_itcm_wtc - CPU2 ITCM WTC
 */
#define CIU2_CIU2_MEM_WRTC4_CPU2_ITCM_WTC(x)     (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_WRTC4_CPU2_ITCM_WTC_SHIFT)) & CIU2_CIU2_MEM_WRTC4_CPU2_ITCM_WTC_MASK)

#define CIU2_CIU2_MEM_WRTC4_CPU2_DTCM_RTC_MASK   (0x30U)
#define CIU2_CIU2_MEM_WRTC4_CPU2_DTCM_RTC_SHIFT  (4U)
/*! cpu2_dtcm_rtc - CPU2 DTCM RTC
 */
#define CIU2_CIU2_MEM_WRTC4_CPU2_DTCM_RTC(x)     (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_WRTC4_CPU2_DTCM_RTC_SHIFT)) & CIU2_CIU2_MEM_WRTC4_CPU2_DTCM_RTC_MASK)

#define CIU2_CIU2_MEM_WRTC4_CPU2_DTCM_WTC_MASK   (0xC0U)
#define CIU2_CIU2_MEM_WRTC4_CPU2_DTCM_WTC_SHIFT  (6U)
/*! cpu2_dtcm_wtc - CPU2 DTCM WTC
 */
#define CIU2_CIU2_MEM_WRTC4_CPU2_DTCM_WTC(x)     (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_WRTC4_CPU2_DTCM_WTC_SHIFT)) & CIU2_CIU2_MEM_WRTC4_CPU2_DTCM_WTC_MASK)

#define CIU2_CIU2_MEM_WRTC4_SMU2_RTC_MASK        (0x300U)
#define CIU2_CIU2_MEM_WRTC4_SMU2_RTC_SHIFT       (8U)
/*! smu2_rtc - SMU2 RTC
 */
#define CIU2_CIU2_MEM_WRTC4_SMU2_RTC(x)          (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_WRTC4_SMU2_RTC_SHIFT)) & CIU2_CIU2_MEM_WRTC4_SMU2_RTC_MASK)

#define CIU2_CIU2_MEM_WRTC4_SMU2_WTC_MASK        (0xC00U)
#define CIU2_CIU2_MEM_WRTC4_SMU2_WTC_SHIFT       (10U)
/*! smu2_wtc - SMU2 WTC
 */
#define CIU2_CIU2_MEM_WRTC4_SMU2_WTC(x)          (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_WRTC4_SMU2_WTC_SHIFT)) & CIU2_CIU2_MEM_WRTC4_SMU2_WTC_MASK)

#define CIU2_CIU2_MEM_WRTC4_CPU2_BRU_RTC_MASK    (0x7000U)
#define CIU2_CIU2_MEM_WRTC4_CPU2_BRU_RTC_SHIFT   (12U)
/*! cpu2_bru_rtc - CPU2 BROM RTC
 */
#define CIU2_CIU2_MEM_WRTC4_CPU2_BRU_RTC(x)      (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_WRTC4_CPU2_BRU_RTC_SHIFT)) & CIU2_CIU2_MEM_WRTC4_CPU2_BRU_RTC_MASK)

#define CIU2_CIU2_MEM_WRTC4_CPU2_BRU_RTC_REF_MASK (0x30000U)
#define CIU2_CIU2_MEM_WRTC4_CPU2_BRU_RTC_REF_SHIFT (16U)
/*! cpu2_bru_rtc_ref - CPU2 BROM RTC_REF
 */
#define CIU2_CIU2_MEM_WRTC4_CPU2_BRU_RTC_REF(x)  (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_WRTC4_CPU2_BRU_RTC_REF_SHIFT)) & CIU2_CIU2_MEM_WRTC4_CPU2_BRU_RTC_REF_MASK)

#define CIU2_CIU2_MEM_WRTC4_BTU_RTC_MASK         (0xC0000U)
#define CIU2_CIU2_MEM_WRTC4_BTU_RTC_SHIFT        (18U)
/*! btu_rtc - BTU EBRAM RTC
 */
#define CIU2_CIU2_MEM_WRTC4_BTU_RTC(x)           (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_WRTC4_BTU_RTC_SHIFT)) & CIU2_CIU2_MEM_WRTC4_BTU_RTC_MASK)

#define CIU2_CIU2_MEM_WRTC4_BTU_WTC_MASK         (0x300000U)
#define CIU2_CIU2_MEM_WRTC4_BTU_WTC_SHIFT        (20U)
/*! btu_wtc - BTU EBRAM WTC
 */
#define CIU2_CIU2_MEM_WRTC4_BTU_WTC(x)           (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_WRTC4_BTU_WTC_SHIFT)) & CIU2_CIU2_MEM_WRTC4_BTU_WTC_MASK)

#define CIU2_CIU2_MEM_WRTC4_BLE_RTC_MASK         (0xC000000U)
#define CIU2_CIU2_MEM_WRTC4_BLE_RTC_SHIFT        (26U)
/*! ble_rtc - ble RTC
 */
#define CIU2_CIU2_MEM_WRTC4_BLE_RTC(x)           (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_WRTC4_BLE_RTC_SHIFT)) & CIU2_CIU2_MEM_WRTC4_BLE_RTC_MASK)

#define CIU2_CIU2_MEM_WRTC4_BLE_WTC_MASK         (0x30000000U)
#define CIU2_CIU2_MEM_WRTC4_BLE_WTC_SHIFT        (28U)
/*! ble_wtc - ble WTC
 */
#define CIU2_CIU2_MEM_WRTC4_BLE_WTC(x)           (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_WRTC4_BLE_WTC_SHIFT)) & CIU2_CIU2_MEM_WRTC4_BLE_WTC_MASK)
/*! @} */

/*! @name CIU2_MEM_PWDN3 - Memory Powerdown Control */
/*! @{ */

#define CIU2_CIU2_MEM_PWDN3_CPU2_BRU_BYPASS_VAL_MASK (0x1U)
#define CIU2_CIU2_MEM_PWDN3_CPU2_BRU_BYPASS_VAL_SHIFT (0U)
/*! cpu2_bru_bypass_val - Firmware Bypass value for CPU2 Boot ROM Memories Power Down
 */
#define CIU2_CIU2_MEM_PWDN3_CPU2_BRU_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_PWDN3_CPU2_BRU_BYPASS_VAL_SHIFT)) & CIU2_CIU2_MEM_PWDN3_CPU2_BRU_BYPASS_VAL_MASK)

#define CIU2_CIU2_MEM_PWDN3_CPU2_DTCM_BYPASS_VAL_MASK (0x2U)
#define CIU2_CIU2_MEM_PWDN3_CPU2_DTCM_BYPASS_VAL_SHIFT (1U)
/*! cpu2_dtcm_bypass_val - Firmware Bypass value for CPU2 DTCM Memories Power Down
 */
#define CIU2_CIU2_MEM_PWDN3_CPU2_DTCM_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_PWDN3_CPU2_DTCM_BYPASS_VAL_SHIFT)) & CIU2_CIU2_MEM_PWDN3_CPU2_DTCM_BYPASS_VAL_MASK)

#define CIU2_CIU2_MEM_PWDN3_CPU2_ITCM_BYPASS_VAL_MASK (0x4U)
#define CIU2_CIU2_MEM_PWDN3_CPU2_ITCM_BYPASS_VAL_SHIFT (2U)
/*! cpu2_itcm_bypass_val - Firmware Bypass value for CPU2 ITCM Memories Power Down
 */
#define CIU2_CIU2_MEM_PWDN3_CPU2_ITCM_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_PWDN3_CPU2_ITCM_BYPASS_VAL_SHIFT)) & CIU2_CIU2_MEM_PWDN3_CPU2_ITCM_BYPASS_VAL_MASK)

#define CIU2_CIU2_MEM_PWDN3_SMU2_BYPASS_VAL_MASK (0x10U)
#define CIU2_CIU2_MEM_PWDN3_SMU2_BYPASS_VAL_SHIFT (4U)
/*! smu2_bypass_val - Firmware Bypass value for SMU2 Memories Power Down
 */
#define CIU2_CIU2_MEM_PWDN3_SMU2_BYPASS_VAL(x)   (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_PWDN3_SMU2_BYPASS_VAL_SHIFT)) & CIU2_CIU2_MEM_PWDN3_SMU2_BYPASS_VAL_MASK)

#define CIU2_CIU2_MEM_PWDN3_SIU_BYPASS_VAL_MASK  (0x20U)
#define CIU2_CIU2_MEM_PWDN3_SIU_BYPASS_VAL_SHIFT (5U)
/*! siu_bypass_val - Firmware Bypass value for UART Memories Power Down
 */
#define CIU2_CIU2_MEM_PWDN3_SIU_BYPASS_VAL(x)    (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_PWDN3_SIU_BYPASS_VAL_SHIFT)) & CIU2_CIU2_MEM_PWDN3_SIU_BYPASS_VAL_MASK)

#define CIU2_CIU2_MEM_PWDN3_BTU_BYPASS_VAL_MASK  (0x40U)
#define CIU2_CIU2_MEM_PWDN3_BTU_BYPASS_VAL_SHIFT (6U)
/*! btu_bypass_val - Firmware Bypass value for BTU Memories Power Down
 */
#define CIU2_CIU2_MEM_PWDN3_BTU_BYPASS_VAL(x)    (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_PWDN3_BTU_BYPASS_VAL_SHIFT)) & CIU2_CIU2_MEM_PWDN3_BTU_BYPASS_VAL_MASK)

#define CIU2_CIU2_MEM_PWDN3_BT_ADMA_BYPASS_VAL_MASK (0x200U)
#define CIU2_CIU2_MEM_PWDN3_BT_ADMA_BYPASS_VAL_SHIFT (9U)
/*! bt_adma_bypass_val - Firmware Bypass value for BT ADMA Memories Power Down
 */
#define CIU2_CIU2_MEM_PWDN3_BT_ADMA_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_PWDN3_BT_ADMA_BYPASS_VAL_SHIFT)) & CIU2_CIU2_MEM_PWDN3_BT_ADMA_BYPASS_VAL_MASK)

#define CIU2_CIU2_MEM_PWDN3_CPU2_BRU_BYPASS_EN_MASK (0x10000U)
#define CIU2_CIU2_MEM_PWDN3_CPU2_BRU_BYPASS_EN_SHIFT (16U)
/*! cpu2_bru_bypass_en - Firmware Bypass Enable for CPU2 Boot ROM Memories Power Down
 */
#define CIU2_CIU2_MEM_PWDN3_CPU2_BRU_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_PWDN3_CPU2_BRU_BYPASS_EN_SHIFT)) & CIU2_CIU2_MEM_PWDN3_CPU2_BRU_BYPASS_EN_MASK)

#define CIU2_CIU2_MEM_PWDN3_CPU2_DTCM_BYPASS_EN_MASK (0x20000U)
#define CIU2_CIU2_MEM_PWDN3_CPU2_DTCM_BYPASS_EN_SHIFT (17U)
/*! cpu2_dtcm_bypass_en - Firmware Bypass Enable for CPU2 DTCM Memories Power Down
 */
#define CIU2_CIU2_MEM_PWDN3_CPU2_DTCM_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_PWDN3_CPU2_DTCM_BYPASS_EN_SHIFT)) & CIU2_CIU2_MEM_PWDN3_CPU2_DTCM_BYPASS_EN_MASK)

#define CIU2_CIU2_MEM_PWDN3_CPU2_ITCM_BYPASS_EN_MASK (0x40000U)
#define CIU2_CIU2_MEM_PWDN3_CPU2_ITCM_BYPASS_EN_SHIFT (18U)
/*! cpu2_itcm_bypass_en - Firmware Bypass Enable for CPU2 ITCM Memories Power Down
 */
#define CIU2_CIU2_MEM_PWDN3_CPU2_ITCM_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_PWDN3_CPU2_ITCM_BYPASS_EN_SHIFT)) & CIU2_CIU2_MEM_PWDN3_CPU2_ITCM_BYPASS_EN_MASK)

#define CIU2_CIU2_MEM_PWDN3_SMU2_BYPASS_EN_MASK  (0x100000U)
#define CIU2_CIU2_MEM_PWDN3_SMU2_BYPASS_EN_SHIFT (20U)
/*! smu2_bypass_en - Firmware Bypass Enable for SMU2 Memories Power Down
 */
#define CIU2_CIU2_MEM_PWDN3_SMU2_BYPASS_EN(x)    (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_PWDN3_SMU2_BYPASS_EN_SHIFT)) & CIU2_CIU2_MEM_PWDN3_SMU2_BYPASS_EN_MASK)

#define CIU2_CIU2_MEM_PWDN3_SIU_BYPASS_EN_MASK   (0x200000U)
#define CIU2_CIU2_MEM_PWDN3_SIU_BYPASS_EN_SHIFT  (21U)
/*! siu_bypass_en - Firmware Bypass Enable for UART Memories Power Down
 */
#define CIU2_CIU2_MEM_PWDN3_SIU_BYPASS_EN(x)     (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_PWDN3_SIU_BYPASS_EN_SHIFT)) & CIU2_CIU2_MEM_PWDN3_SIU_BYPASS_EN_MASK)

#define CIU2_CIU2_MEM_PWDN3_BTU_BYPASS_EN_MASK   (0x400000U)
#define CIU2_CIU2_MEM_PWDN3_BTU_BYPASS_EN_SHIFT  (22U)
/*! btu_bypass_en - Firmware Bypass Enable for BTU Memories Power Down
 */
#define CIU2_CIU2_MEM_PWDN3_BTU_BYPASS_EN(x)     (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_PWDN3_BTU_BYPASS_EN_SHIFT)) & CIU2_CIU2_MEM_PWDN3_BTU_BYPASS_EN_MASK)

#define CIU2_CIU2_MEM_PWDN3_BT_ADMA_BYPASS_EN_MASK (0x2000000U)
#define CIU2_CIU2_MEM_PWDN3_BT_ADMA_BYPASS_EN_SHIFT (25U)
/*! bt_adma_bypass_en - Firmware Bypass Enable for BT ADMA Memories Power Down
 */
#define CIU2_CIU2_MEM_PWDN3_BT_ADMA_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_MEM_PWDN3_BT_ADMA_BYPASS_EN_SHIFT)) & CIU2_CIU2_MEM_PWDN3_BT_ADMA_BYPASS_EN_MASK)
/*! @} */

/*! @name CIU2_BLE_CTRL - BLE Control and Status */
/*! @{ */

#define CIU2_CIU2_BLE_CTRL_BT_AES_CLK_FREQ_SEL_MASK (0x100U)
#define CIU2_CIU2_BLE_CTRL_BT_AES_CLK_FREQ_SEL_SHIFT (8U)
/*! bt_aes_clk_freq_sel - btu_aes_clk Frequency Select
 */
#define CIU2_CIU2_BLE_CTRL_BT_AES_CLK_FREQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BLE_CTRL_BT_AES_CLK_FREQ_SEL_SHIFT)) & CIU2_CIU2_BLE_CTRL_BT_AES_CLK_FREQ_SEL_MASK)
/*! @} */

/*! @name CIU2_AHB2_TO_LAST_ADDR - AHB2 Timeout Last Address */
/*! @{ */

#define CIU2_CIU2_AHB2_TO_LAST_ADDR_ADDRESS_MASK (0xFFFFFFFFU)
#define CIU2_CIU2_AHB2_TO_LAST_ADDR_ADDRESS_SHIFT (0U)
/*! address - Last AHB2 Address Right Before the Current Timeout
 */
#define CIU2_CIU2_AHB2_TO_LAST_ADDR_ADDRESS(x)   (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_AHB2_TO_LAST_ADDR_ADDRESS_SHIFT)) & CIU2_CIU2_AHB2_TO_LAST_ADDR_ADDRESS_MASK)
/*! @} */

/*! @name CIU2_AHB2_TO_CUR_ADDR - AHB2 Current Timeout Address */
/*! @{ */

#define CIU2_CIU2_AHB2_TO_CUR_ADDR_ADDRESS_MASK  (0xFFFFFFFFU)
#define CIU2_CIU2_AHB2_TO_CUR_ADDR_ADDRESS_SHIFT (0U)
/*! address - Current_TO_Addr
 */
#define CIU2_CIU2_AHB2_TO_CUR_ADDR_ADDRESS(x)    (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_AHB2_TO_CUR_ADDR_ADDRESS_SHIFT)) & CIU2_CIU2_AHB2_TO_CUR_ADDR_ADDRESS_MASK)
/*! @} */

/*! @name CIU2_AHB2_TO_CTRL - AHB2 ARB Control */
/*! @{ */

#define CIU2_CIU2_AHB2_TO_CTRL_CURRENT_TO_SLAVE_ID_MASK (0xFU)
#define CIU2_CIU2_AHB2_TO_CTRL_CURRENT_TO_SLAVE_ID_SHIFT (0U)
/*! current_to_slave_id - Current_TO_Slave_ID
 */
#define CIU2_CIU2_AHB2_TO_CTRL_CURRENT_TO_SLAVE_ID(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_AHB2_TO_CTRL_CURRENT_TO_SLAVE_ID_SHIFT)) & CIU2_CIU2_AHB2_TO_CTRL_CURRENT_TO_SLAVE_ID_MASK)

#define CIU2_CIU2_AHB2_TO_CTRL_LAST_TO_SLAVE_ID_MASK (0xF0U)
#define CIU2_CIU2_AHB2_TO_CTRL_LAST_TO_SLAVE_ID_SHIFT (4U)
/*! last_to_slave_id - Last_TO_Slave_ID
 */
#define CIU2_CIU2_AHB2_TO_CTRL_LAST_TO_SLAVE_ID(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_AHB2_TO_CTRL_LAST_TO_SLAVE_ID_SHIFT)) & CIU2_CIU2_AHB2_TO_CTRL_LAST_TO_SLAVE_ID_MASK)

#define CIU2_CIU2_AHB2_TO_CTRL_CURRENT_TO_MASTER_ID_MASK (0xF00U)
#define CIU2_CIU2_AHB2_TO_CTRL_CURRENT_TO_MASTER_ID_SHIFT (8U)
/*! current_to_master_id - AHB2 Current_TO_Master_ID
 */
#define CIU2_CIU2_AHB2_TO_CTRL_CURRENT_TO_MASTER_ID(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_AHB2_TO_CTRL_CURRENT_TO_MASTER_ID_SHIFT)) & CIU2_CIU2_AHB2_TO_CTRL_CURRENT_TO_MASTER_ID_MASK)

#define CIU2_CIU2_AHB2_TO_CTRL_LAST_TO_MASTER_ID_MASK (0xF000U)
#define CIU2_CIU2_AHB2_TO_CTRL_LAST_TO_MASTER_ID_SHIFT (12U)
/*! last_to_master_id - AHB2 Last_TO_Master_ID
 */
#define CIU2_CIU2_AHB2_TO_CTRL_LAST_TO_MASTER_ID(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_AHB2_TO_CTRL_LAST_TO_MASTER_ID_SHIFT)) & CIU2_CIU2_AHB2_TO_CTRL_LAST_TO_MASTER_ID_MASK)

#define CIU2_CIU2_AHB2_TO_CTRL_AHB2_SMU1_MEM_PROT_DIS_MASK (0x10000U)
#define CIU2_CIU2_AHB2_TO_CTRL_AHB2_SMU1_MEM_PROT_DIS_SHIFT (16U)
/*! ahb2_smu1_mem_prot_dis - Disable SMU1 Memory Protection from AHB2 side
 */
#define CIU2_CIU2_AHB2_TO_CTRL_AHB2_SMU1_MEM_PROT_DIS(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_AHB2_TO_CTRL_AHB2_SMU1_MEM_PROT_DIS_SHIFT)) & CIU2_CIU2_AHB2_TO_CTRL_AHB2_SMU1_MEM_PROT_DIS_MASK)

#define CIU2_CIU2_AHB2_TO_CTRL_AHB2_CPU2_IMEM_PROT_DIS_MASK (0x20000U)
#define CIU2_CIU2_AHB2_TO_CTRL_AHB2_CPU2_IMEM_PROT_DIS_SHIFT (17U)
/*! ahb2_cpu2_imem_prot_dis - 1 = Disable CPU2 Imem Memory Protection from AHB2 side and allow AHB2 to read/write Imem
 */
#define CIU2_CIU2_AHB2_TO_CTRL_AHB2_CPU2_IMEM_PROT_DIS(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_AHB2_TO_CTRL_AHB2_CPU2_IMEM_PROT_DIS_SHIFT)) & CIU2_CIU2_AHB2_TO_CTRL_AHB2_CPU2_IMEM_PROT_DIS_MASK)

#define CIU2_CIU2_AHB2_TO_CTRL_AHB2_CPU2_DMEM_PROT_DIS_MASK (0x40000U)
#define CIU2_CIU2_AHB2_TO_CTRL_AHB2_CPU2_DMEM_PROT_DIS_SHIFT (18U)
/*! ahb2_cpu2_dmem_prot_dis - 1 = Disable CPU2 Dmem Memory Protection from AHB2 side and allow AHB2 to read/write Dmem
 */
#define CIU2_CIU2_AHB2_TO_CTRL_AHB2_CPU2_DMEM_PROT_DIS(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_AHB2_TO_CTRL_AHB2_CPU2_DMEM_PROT_DIS_SHIFT)) & CIU2_CIU2_AHB2_TO_CTRL_AHB2_CPU2_DMEM_PROT_DIS_MASK)

#define CIU2_CIU2_AHB2_TO_CTRL_AHB2_TIMEOUT_MODE_MASK (0xC0000000U)
#define CIU2_CIU2_AHB2_TO_CTRL_AHB2_TIMEOUT_MODE_SHIFT (30U)
/*! ahb2_timeout_mode - AHB2_TimeoutMode[1:0]
 */
#define CIU2_CIU2_AHB2_TO_CTRL_AHB2_TIMEOUT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_AHB2_TO_CTRL_AHB2_TIMEOUT_MODE_SHIFT)) & CIU2_CIU2_AHB2_TO_CTRL_AHB2_TIMEOUT_MODE_MASK)
/*! @} */

/*! @name CIU2_AHB2_SMU1_ACCESS_ADDR - AHB2 to SMU1 Accessible Address */
/*! @{ */

#define CIU2_CIU2_AHB2_SMU1_ACCESS_ADDR_AHB2_SMU1_ACCESS_ADDR_MASK (0xFFFFFFFFU)
#define CIU2_CIU2_AHB2_SMU1_ACCESS_ADDR_AHB2_SMU1_ACCESS_ADDR_SHIFT (0U)
/*! ahb2_smu1_access_addr - SMU1 Accessible Memory Address from AHB2 side
 */
#define CIU2_CIU2_AHB2_SMU1_ACCESS_ADDR_AHB2_SMU1_ACCESS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_AHB2_SMU1_ACCESS_ADDR_AHB2_SMU1_ACCESS_ADDR_SHIFT)) & CIU2_CIU2_AHB2_SMU1_ACCESS_ADDR_AHB2_SMU1_ACCESS_ADDR_MASK)
/*! @} */

/*! @name CIU2_AHB2_SMU1_ACCESS_MASK - AHB2 to SMU1 Accessible Mask */
/*! @{ */

#define CIU2_CIU2_AHB2_SMU1_ACCESS_MASK_AHB2_SMU1_ACCESS_MASK_MASK (0xFFFFFFFFU)
#define CIU2_CIU2_AHB2_SMU1_ACCESS_MASK_AHB2_SMU1_ACCESS_MASK_SHIFT (0U)
/*! ahb2_smu1_access_mask - SMU1 Accessible Memory Mask from AHB2 side
 */
#define CIU2_CIU2_AHB2_SMU1_ACCESS_MASK_AHB2_SMU1_ACCESS_MASK(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_AHB2_SMU1_ACCESS_MASK_AHB2_SMU1_ACCESS_MASK_SHIFT)) & CIU2_CIU2_AHB2_SMU1_ACCESS_MASK_AHB2_SMU1_ACCESS_MASK_MASK)
/*! @} */

/*! @name CIU2_CPU2_FABRIC_ARB_CTRL - CPU2 fabric arbiter control */
/*! @{ */

#define CIU2_CIU2_CPU2_FABRIC_ARB_CTRL_DMEM_BRST_TERM_CNT_MASK (0x3U)
#define CIU2_CIU2_CPU2_FABRIC_ARB_CTRL_DMEM_BRST_TERM_CNT_SHIFT (0U)
#define CIU2_CIU2_CPU2_FABRIC_ARB_CTRL_DMEM_BRST_TERM_CNT(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_FABRIC_ARB_CTRL_DMEM_BRST_TERM_CNT_SHIFT)) & CIU2_CIU2_CPU2_FABRIC_ARB_CTRL_DMEM_BRST_TERM_CNT_MASK)

#define CIU2_CIU2_CPU2_FABRIC_ARB_CTRL_IMEM_BRST_TERM_CNT_MASK (0xCU)
#define CIU2_CIU2_CPU2_FABRIC_ARB_CTRL_IMEM_BRST_TERM_CNT_SHIFT (2U)
#define CIU2_CIU2_CPU2_FABRIC_ARB_CTRL_IMEM_BRST_TERM_CNT(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_FABRIC_ARB_CTRL_IMEM_BRST_TERM_CNT_SHIFT)) & CIU2_CIU2_CPU2_FABRIC_ARB_CTRL_IMEM_BRST_TERM_CNT_MASK)

#define CIU2_CIU2_CPU2_FABRIC_ARB_CTRL_DMEM_NOBURSTTERM_MASK (0x10U)
#define CIU2_CIU2_CPU2_FABRIC_ARB_CTRL_DMEM_NOBURSTTERM_SHIFT (4U)
#define CIU2_CIU2_CPU2_FABRIC_ARB_CTRL_DMEM_NOBURSTTERM(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_FABRIC_ARB_CTRL_DMEM_NOBURSTTERM_SHIFT)) & CIU2_CIU2_CPU2_FABRIC_ARB_CTRL_DMEM_NOBURSTTERM_MASK)

#define CIU2_CIU2_CPU2_FABRIC_ARB_CTRL_DMEM_PRIORITY_MASK (0x60U)
#define CIU2_CIU2_CPU2_FABRIC_ARB_CTRL_DMEM_PRIORITY_SHIFT (5U)
#define CIU2_CIU2_CPU2_FABRIC_ARB_CTRL_DMEM_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_FABRIC_ARB_CTRL_DMEM_PRIORITY_SHIFT)) & CIU2_CIU2_CPU2_FABRIC_ARB_CTRL_DMEM_PRIORITY_MASK)

#define CIU2_CIU2_CPU2_FABRIC_ARB_CTRL_DMEM_ROUND_ROBIN_EN_MASK (0x80U)
#define CIU2_CIU2_CPU2_FABRIC_ARB_CTRL_DMEM_ROUND_ROBIN_EN_SHIFT (7U)
#define CIU2_CIU2_CPU2_FABRIC_ARB_CTRL_DMEM_ROUND_ROBIN_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_FABRIC_ARB_CTRL_DMEM_ROUND_ROBIN_EN_SHIFT)) & CIU2_CIU2_CPU2_FABRIC_ARB_CTRL_DMEM_ROUND_ROBIN_EN_MASK)

#define CIU2_CIU2_CPU2_FABRIC_ARB_CTRL_IMEM_NOBURSTTERM_MASK (0x100U)
#define CIU2_CIU2_CPU2_FABRIC_ARB_CTRL_IMEM_NOBURSTTERM_SHIFT (8U)
#define CIU2_CIU2_CPU2_FABRIC_ARB_CTRL_IMEM_NOBURSTTERM(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_FABRIC_ARB_CTRL_IMEM_NOBURSTTERM_SHIFT)) & CIU2_CIU2_CPU2_FABRIC_ARB_CTRL_IMEM_NOBURSTTERM_MASK)

#define CIU2_CIU2_CPU2_FABRIC_ARB_CTRL_IMEM_PRIORITY_MASK (0x600U)
#define CIU2_CIU2_CPU2_FABRIC_ARB_CTRL_IMEM_PRIORITY_SHIFT (9U)
#define CIU2_CIU2_CPU2_FABRIC_ARB_CTRL_IMEM_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_FABRIC_ARB_CTRL_IMEM_PRIORITY_SHIFT)) & CIU2_CIU2_CPU2_FABRIC_ARB_CTRL_IMEM_PRIORITY_MASK)

#define CIU2_CIU2_CPU2_FABRIC_ARB_CTRL_IMEM_ROUND_ROBIN_EN_MASK (0x800U)
#define CIU2_CIU2_CPU2_FABRIC_ARB_CTRL_IMEM_ROUND_ROBIN_EN_SHIFT (11U)
#define CIU2_CIU2_CPU2_FABRIC_ARB_CTRL_IMEM_ROUND_ROBIN_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_FABRIC_ARB_CTRL_IMEM_ROUND_ROBIN_EN_SHIFT)) & CIU2_CIU2_CPU2_FABRIC_ARB_CTRL_IMEM_ROUND_ROBIN_EN_MASK)
/*! @} */

/*! @name CIU2_CPU2_ICODE_INV_ADDR_CTRL - CPU2 Icode invalid address access control */
/*! @{ */

#define CIU2_CIU2_CPU2_ICODE_INV_ADDR_CTRL_LAST2_INV_ADDR_SLAVE_ID_MASK (0xFU)
#define CIU2_CIU2_CPU2_ICODE_INV_ADDR_CTRL_LAST2_INV_ADDR_SLAVE_ID_SHIFT (0U)
/*! last2_inv_addr_slave_id - Last2_inv_addr_Slave_ID
 */
#define CIU2_CIU2_CPU2_ICODE_INV_ADDR_CTRL_LAST2_INV_ADDR_SLAVE_ID(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_ICODE_INV_ADDR_CTRL_LAST2_INV_ADDR_SLAVE_ID_SHIFT)) & CIU2_CIU2_CPU2_ICODE_INV_ADDR_CTRL_LAST2_INV_ADDR_SLAVE_ID_MASK)

#define CIU2_CIU2_CPU2_ICODE_INV_ADDR_CTRL_LAST_INV_ADDR_SLAVE_ID_MASK (0xF0U)
#define CIU2_CIU2_CPU2_ICODE_INV_ADDR_CTRL_LAST_INV_ADDR_SLAVE_ID_SHIFT (4U)
/*! last_inv_addr_slave_id - Last_inv_addr_Slave_ID
 */
#define CIU2_CIU2_CPU2_ICODE_INV_ADDR_CTRL_LAST_INV_ADDR_SLAVE_ID(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_ICODE_INV_ADDR_CTRL_LAST_INV_ADDR_SLAVE_ID_SHIFT)) & CIU2_CIU2_CPU2_ICODE_INV_ADDR_CTRL_LAST_INV_ADDR_SLAVE_ID_MASK)

#define CIU2_CIU2_CPU2_ICODE_INV_ADDR_CTRL_CUR_INV_ADDR_SLAVE_ID_MASK (0xF00U)
#define CIU2_CIU2_CPU2_ICODE_INV_ADDR_CTRL_CUR_INV_ADDR_SLAVE_ID_SHIFT (8U)
/*! cur_inv_addr_slave_id - Cur_inv_addr_Slave_ID
 */
#define CIU2_CIU2_CPU2_ICODE_INV_ADDR_CTRL_CUR_INV_ADDR_SLAVE_ID(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_ICODE_INV_ADDR_CTRL_CUR_INV_ADDR_SLAVE_ID_SHIFT)) & CIU2_CIU2_CPU2_ICODE_INV_ADDR_CTRL_CUR_INV_ADDR_SLAVE_ID_MASK)

#define CIU2_CIU2_CPU2_ICODE_INV_ADDR_CTRL_HADDR_ICOD_SEL_MASK (0xC0000000U)
#define CIU2_CIU2_CPU2_ICODE_INV_ADDR_CTRL_HADDR_ICOD_SEL_SHIFT (30U)
/*! haddr_icod_sel - There are 3 haddr which can be observed by selecting this:
 */
#define CIU2_CIU2_CPU2_ICODE_INV_ADDR_CTRL_HADDR_ICOD_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_ICODE_INV_ADDR_CTRL_HADDR_ICOD_SEL_SHIFT)) & CIU2_CIU2_CPU2_ICODE_INV_ADDR_CTRL_HADDR_ICOD_SEL_MASK)
/*! @} */

/*! @name CIU2_CPU2_ICODE_INV_ADDR - CPU2 Icode invalid address */
/*! @{ */

#define CIU2_CIU2_CPU2_ICODE_INV_ADDR_HADDR_INV_ADDR_MASK (0xFFFFFFFFU)
#define CIU2_CIU2_CPU2_ICODE_INV_ADDR_HADDR_INV_ADDR_SHIFT (0U)
/*! haddr_inv_addr - based on CIU_CPU2_ICODE_INV_ADDR_CTRL[31:30], the address status is obsrved in this register
 */
#define CIU2_CIU2_CPU2_ICODE_INV_ADDR_HADDR_INV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_ICODE_INV_ADDR_HADDR_INV_ADDR_SHIFT)) & CIU2_CIU2_CPU2_ICODE_INV_ADDR_HADDR_INV_ADDR_MASK)
/*! @} */

/*! @name CIU2_CPU2_DCODE_INV_ADDR_CTRL - CPU2 Dcode invalid address access control */
/*! @{ */

#define CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_LAST2_INV_ADDR_SLAVE_ID_MASK (0xFU)
#define CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_LAST2_INV_ADDR_SLAVE_ID_SHIFT (0U)
/*! last2_inv_addr_slave_id - Last2_inv_addr_Slave_ID
 */
#define CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_LAST2_INV_ADDR_SLAVE_ID(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_LAST2_INV_ADDR_SLAVE_ID_SHIFT)) & CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_LAST2_INV_ADDR_SLAVE_ID_MASK)

#define CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_LAST_INV_ADDR_SLAVE_ID_MASK (0xF0U)
#define CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_LAST_INV_ADDR_SLAVE_ID_SHIFT (4U)
/*! last_inv_addr_slave_id - Last_inv_addr_Slave_ID
 */
#define CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_LAST_INV_ADDR_SLAVE_ID(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_LAST_INV_ADDR_SLAVE_ID_SHIFT)) & CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_LAST_INV_ADDR_SLAVE_ID_MASK)

#define CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_CUR_INV_ADDR_SLAVE_ID_MASK (0xF00U)
#define CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_CUR_INV_ADDR_SLAVE_ID_SHIFT (8U)
/*! cur_inv_addr_slave_id - Cur_inv_addr_Slave_ID
 */
#define CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_CUR_INV_ADDR_SLAVE_ID(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_CUR_INV_ADDR_SLAVE_ID_SHIFT)) & CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_CUR_INV_ADDR_SLAVE_ID_MASK)

#define CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_LAST2_INV_ADDR_MASTER_ID_MASK (0xF000U)
#define CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_LAST2_INV_ADDR_MASTER_ID_SHIFT (12U)
/*! last2_inv_addr_master_id - Last2_inv_addr_master_ID
 */
#define CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_LAST2_INV_ADDR_MASTER_ID(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_LAST2_INV_ADDR_MASTER_ID_SHIFT)) & CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_LAST2_INV_ADDR_MASTER_ID_MASK)

#define CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_LAST_INV_ADDR_MASTER_ID_MASK (0xF0000U)
#define CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_LAST_INV_ADDR_MASTER_ID_SHIFT (16U)
/*! last_inv_addr_master_id - Last_inv_addr_master_ID
 */
#define CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_LAST_INV_ADDR_MASTER_ID(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_LAST_INV_ADDR_MASTER_ID_SHIFT)) & CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_LAST_INV_ADDR_MASTER_ID_MASK)

#define CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_CUR_INV_ADDR_MASTER_ID_MASK (0xF00000U)
#define CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_CUR_INV_ADDR_MASTER_ID_SHIFT (20U)
/*! cur_inv_addr_master_id - Cur_inv_addr_master_ID
 */
#define CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_CUR_INV_ADDR_MASTER_ID(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_CUR_INV_ADDR_MASTER_ID_SHIFT)) & CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_CUR_INV_ADDR_MASTER_ID_MASK)

#define CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_HADDR_ICOD_SEL_MASK (0xC0000000U)
#define CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_HADDR_ICOD_SEL_SHIFT (30U)
/*! haddr_icod_sel - There are 3 haddr which can be observed by selecting this:
 */
#define CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_HADDR_ICOD_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_HADDR_ICOD_SEL_SHIFT)) & CIU2_CIU2_CPU2_DCODE_INV_ADDR_CTRL_HADDR_ICOD_SEL_MASK)
/*! @} */

/*! @name CIU2_CPU2_DCODE_INV_ADDR - CPU2 Dcode invalid address */
/*! @{ */

#define CIU2_CIU2_CPU2_DCODE_INV_ADDR_HADDR_INV_ADDR_MASK (0xFFFFFFFFU)
#define CIU2_CIU2_CPU2_DCODE_INV_ADDR_HADDR_INV_ADDR_SHIFT (0U)
/*! haddr_inv_addr - based on CIU_CPU2_DCODE_INV_ADDR_CTRL[31:30], the address status is obsrved in this register
 */
#define CIU2_CIU2_CPU2_DCODE_INV_ADDR_HADDR_INV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_DCODE_INV_ADDR_HADDR_INV_ADDR_SHIFT)) & CIU2_CIU2_CPU2_DCODE_INV_ADDR_HADDR_INV_ADDR_MASK)
/*! @} */

/*! @name CIU2_CPU_CPU2_CTRL - CPU2 control register */
/*! @{ */

#define CIU2_CIU2_CPU_CPU2_CTRL_VINITHI_MASK     (0x1U)
#define CIU2_CIU2_CPU_CPU2_CTRL_VINITHI_SHIFT    (0U)
#define CIU2_CIU2_CPU_CPU2_CTRL_VINITHI(x)       (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU_CPU2_CTRL_VINITHI_SHIFT)) & CIU2_CIU2_CPU_CPU2_CTRL_VINITHI_MASK)

#define CIU2_CIU2_CPU_CPU2_CTRL_CPU2_JTAG_CHAIN_BYPASS_MASK (0x4U)
#define CIU2_CIU2_CPU_CPU2_CTRL_CPU2_JTAG_CHAIN_BYPASS_SHIFT (2U)
#define CIU2_CIU2_CPU_CPU2_CTRL_CPU2_JTAG_CHAIN_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU_CPU2_CTRL_CPU2_JTAG_CHAIN_BYPASS_SHIFT)) & CIU2_CIU2_CPU_CPU2_CTRL_CPU2_JTAG_CHAIN_BYPASS_MASK)

#define CIU2_CIU2_CPU_CPU2_CTRL_CPU2_BOOT_IMEM_MUX_EN_MASK (0x10U)
#define CIU2_CIU2_CPU_CPU2_CTRL_CPU2_BOOT_IMEM_MUX_EN_SHIFT (4U)
#define CIU2_CIU2_CPU_CPU2_CTRL_CPU2_BOOT_IMEM_MUX_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU_CPU2_CTRL_CPU2_BOOT_IMEM_MUX_EN_SHIFT)) & CIU2_CIU2_CPU_CPU2_CTRL_CPU2_BOOT_IMEM_MUX_EN_MASK)

#define CIU2_CIU2_CPU_CPU2_CTRL_CPU2_BOOT_DMEM_MUX_EN_MASK (0x20U)
#define CIU2_CIU2_CPU_CPU2_CTRL_CPU2_BOOT_DMEM_MUX_EN_SHIFT (5U)
#define CIU2_CIU2_CPU_CPU2_CTRL_CPU2_BOOT_DMEM_MUX_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU_CPU2_CTRL_CPU2_BOOT_DMEM_MUX_EN_SHIFT)) & CIU2_CIU2_CPU_CPU2_CTRL_CPU2_BOOT_DMEM_MUX_EN_MASK)

#define CIU2_CIU2_CPU_CPU2_CTRL_CPU2_DBG_CTRL_MASK (0xFFF0000U)
#define CIU2_CIU2_CPU_CPU2_CTRL_CPU2_DBG_CTRL_SHIFT (16U)
/*! cpu2_dbg_ctrl - cpu2 debug control
 */
#define CIU2_CIU2_CPU_CPU2_CTRL_CPU2_DBG_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU_CPU2_CTRL_CPU2_DBG_CTRL_SHIFT)) & CIU2_CIU2_CPU_CPU2_CTRL_CPU2_DBG_CTRL_MASK)

#define CIU2_CIU2_CPU_CPU2_CTRL_CPU3_RESET_INT_MASK (0x20000000U)
#define CIU2_CIU2_CPU_CPU2_CTRL_CPU3_RESET_INT_SHIFT (29U)
/*! cpu3_reset_int - cpu2 fw resets cpu3(or cpu3 fw resets cpu2 if this register is used by cpu3)
 */
#define CIU2_CIU2_CPU_CPU2_CTRL_CPU3_RESET_INT(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU_CPU2_CTRL_CPU3_RESET_INT_SHIFT)) & CIU2_CIU2_CPU_CPU2_CTRL_CPU3_RESET_INT_MASK)

#define CIU2_CIU2_CPU_CPU2_CTRL_DSR_WKUP_IN_USE_MASK (0x40000000U)
#define CIU2_CIU2_CPU_CPU2_CTRL_DSR_WKUP_IN_USE_SHIFT (30U)
/*! dsr_wkup_in_use - dsr wkup when dsr_wkup_in_use = 1'b1
 */
#define CIU2_CIU2_CPU_CPU2_CTRL_DSR_WKUP_IN_USE(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU_CPU2_CTRL_DSR_WKUP_IN_USE_SHIFT)) & CIU2_CIU2_CPU_CPU2_CTRL_DSR_WKUP_IN_USE_MASK)

#define CIU2_CIU2_CPU_CPU2_CTRL_CPU1_RESET_INT_MASK (0x80000000U)
#define CIU2_CIU2_CPU_CPU2_CTRL_CPU1_RESET_INT_SHIFT (31U)
/*! cpu1_reset_int - cpu2 fw resets cpu1( or cpu3 fw resets cpu1 if this register is used by cpu3)
 */
#define CIU2_CIU2_CPU_CPU2_CTRL_CPU1_RESET_INT(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU_CPU2_CTRL_CPU1_RESET_INT_SHIFT)) & CIU2_CIU2_CPU_CPU2_CTRL_CPU1_RESET_INT_MASK)
/*! @} */

/*! @name CIU2_BRF_CTRL - BRF Control and Status */
/*! @{ */

#define CIU2_CIU2_BRF_CTRL_AHB_SLV_BRF_SER_EN_MASK (0x1U)
#define CIU2_CIU2_BRF_CTRL_AHB_SLV_BRF_SER_EN_SHIFT (0U)
/*! ahb_slv_brf_ser_en - When set to 1, BRF serial interface will be accessed thru AHB slave memory mapped from 0xA800A000 to 0xA8011FFF
 */
#define CIU2_CIU2_BRF_CTRL_AHB_SLV_BRF_SER_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BRF_CTRL_AHB_SLV_BRF_SER_EN_SHIFT)) & CIU2_CIU2_BRF_CTRL_AHB_SLV_BRF_SER_EN_MASK)

#define CIU2_CIU2_BRF_CTRL_SEL_BRF_TO_SSU_DUMP_PATH_MASK (0x2U)
#define CIU2_CIU2_BRF_CTRL_SEL_BRF_TO_SSU_DUMP_PATH_SHIFT (1U)
/*! sel_brf_to_ssu_dump_path - When set to 0, select BRF to SSU dump path
 */
#define CIU2_CIU2_BRF_CTRL_SEL_BRF_TO_SSU_DUMP_PATH(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BRF_CTRL_SEL_BRF_TO_SSU_DUMP_PATH_SHIFT)) & CIU2_CIU2_BRF_CTRL_SEL_BRF_TO_SSU_DUMP_PATH_MASK)

#define CIU2_CIU2_BRF_CTRL_CIU_BRF_REF1X_CLK_CTRL_BYPASS_EN_MASK (0x100U)
#define CIU2_CIU2_BRF_CTRL_CIU_BRF_REF1X_CLK_CTRL_BYPASS_EN_SHIFT (8U)
#define CIU2_CIU2_BRF_CTRL_CIU_BRF_REF1X_CLK_CTRL_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BRF_CTRL_CIU_BRF_REF1X_CLK_CTRL_BYPASS_EN_SHIFT)) & CIU2_CIU2_BRF_CTRL_CIU_BRF_REF1X_CLK_CTRL_BYPASS_EN_MASK)

#define CIU2_CIU2_BRF_CTRL_CIU_BRF_REF1X_CLK_CTRL_BYPASS_VAL_MASK (0x200U)
#define CIU2_CIU2_BRF_CTRL_CIU_BRF_REF1X_CLK_CTRL_BYPASS_VAL_SHIFT (9U)
/*! ciu_brf_ref1x_clk_ctrl_bypass_val - 1. brf ref clk 1x is enabled
 */
#define CIU2_CIU2_BRF_CTRL_CIU_BRF_REF1X_CLK_CTRL_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BRF_CTRL_CIU_BRF_REF1X_CLK_CTRL_BYPASS_VAL_SHIFT)) & CIU2_CIU2_BRF_CTRL_CIU_BRF_REF1X_CLK_CTRL_BYPASS_VAL_MASK)

#define CIU2_CIU2_BRF_CTRL_BRF_CHIP_RDY_MASK     (0x80000000U)
#define CIU2_CIU2_BRF_CTRL_BRF_CHIP_RDY_SHIFT    (31U)
/*! brf_chip_rdy - BRF Chip_Rdy Status
 */
#define CIU2_CIU2_BRF_CTRL_BRF_CHIP_RDY(x)       (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BRF_CTRL_BRF_CHIP_RDY_SHIFT)) & CIU2_CIU2_BRF_CTRL_BRF_CHIP_RDY_MASK)
/*! @} */

/*! @name CIU2_BRF_EXTRA_PORT - BRF Extra Port Connection */
/*! @{ */

#define CIU2_CIU2_BRF_EXTRA_PORT_SOC_BRF_EXTRA_MASK (0xFU)
#define CIU2_CIU2_BRF_EXTRA_PORT_SOC_BRF_EXTRA_SHIFT (0U)
/*! soc_brf_extra - SOC_BRF_EXTRA[3:0]
 */
#define CIU2_CIU2_BRF_EXTRA_PORT_SOC_BRF_EXTRA(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BRF_EXTRA_PORT_SOC_BRF_EXTRA_SHIFT)) & CIU2_CIU2_BRF_EXTRA_PORT_SOC_BRF_EXTRA_MASK)
/*! @} */

/*! @name CIU2_BRF_ECO_CTRL - BRF ECO Control */
/*! @{ */

#define CIU2_CIU2_BRF_ECO_CTRL_ECO_BITS_MASK     (0xFFFFFFFFU)
#define CIU2_CIU2_BRF_ECO_CTRL_ECO_BITS_SHIFT    (0U)
/*! eco_bits - Reserved
 */
#define CIU2_CIU2_BRF_ECO_CTRL_ECO_BITS(x)       (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BRF_ECO_CTRL_ECO_BITS_SHIFT)) & CIU2_CIU2_BRF_ECO_CTRL_ECO_BITS_MASK)
/*! @} */

/*! @name CIU2_BTU_CTRL - BTU Control and Status */
/*! @{ */

#define CIU2_CIU2_BTU_CTRL_BTU_CIPHER_EN_MASK    (0x1U)
#define CIU2_CIU2_BTU_CTRL_BTU_CIPHER_EN_SHIFT   (0U)
/*! btu_cipher_en - Bluetooth Cipher Logic
 */
#define CIU2_CIU2_BTU_CTRL_BTU_CIPHER_EN(x)      (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BTU_CTRL_BTU_CIPHER_EN_SHIFT)) & CIU2_CIU2_BTU_CTRL_BTU_CIPHER_EN_MASK)

#define CIU2_CIU2_BTU_CTRL_DBUS_HIGH_SPEED_SEL_MASK (0x2U)
#define CIU2_CIU2_BTU_CTRL_DBUS_HIGH_SPEED_SEL_SHIFT (1U)
/*! dbus_high_speed_sel - Dbus High Speed Select Signal for Greater than 4 MHz
 */
#define CIU2_CIU2_BTU_CTRL_DBUS_HIGH_SPEED_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BTU_CTRL_DBUS_HIGH_SPEED_SEL_SHIFT)) & CIU2_CIU2_BTU_CTRL_DBUS_HIGH_SPEED_SEL_MASK)

#define CIU2_CIU2_BTU_CTRL_BT_CLK_SEL_MASK       (0xCU)
#define CIU2_CIU2_BTU_CTRL_BT_CLK_SEL_SHIFT      (2U)
/*! bt_clk_sel - Bluetooth sys Clock Select
 */
#define CIU2_CIU2_BTU_CTRL_BT_CLK_SEL(x)         (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BTU_CTRL_BT_CLK_SEL_SHIFT)) & CIU2_CIU2_BTU_CTRL_BT_CLK_SEL_MASK)

#define CIU2_CIU2_BTU_CTRL_BT_IP_SER_SEL_MASK    (0x700U)
#define CIU2_CIU2_BTU_CTRL_BT_IP_SER_SEL_SHIFT   (8U)
/*! bt_ip_ser_sel - bt_ip_ser_sel
 */
#define CIU2_CIU2_BTU_CTRL_BT_IP_SER_SEL(x)      (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BTU_CTRL_BT_IP_SER_SEL_SHIFT)) & CIU2_CIU2_BTU_CTRL_BT_IP_SER_SEL_MASK)

#define CIU2_CIU2_BTU_CTRL_BTU_MC_WAKEUP_MASK    (0x80000000U)
#define CIU2_CIU2_BTU_CTRL_BTU_MC_WAKEUP_SHIFT   (31U)
/*! btu_mc_wakeup - BTU MC_Wakeup Status
 */
#define CIU2_CIU2_BTU_CTRL_BTU_MC_WAKEUP(x)      (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BTU_CTRL_BTU_MC_WAKEUP_SHIFT)) & CIU2_CIU2_BTU_CTRL_BTU_MC_WAKEUP_MASK)
/*! @} */

/*! @name CIU2_BT_PS - BT Clock Power Save */
/*! @{ */

#define CIU2_CIU2_BT_PS_BT_MCLK_NCO_MVAL_MASK    (0x3FFFFFFU)
#define CIU2_CIU2_BT_PS_BT_MCLK_NCO_MVAL_SHIFT   (0U)
/*! bt_mclk_nco_mval - BT_MCLK NCO Module Step Control (default 0x0)
 */
#define CIU2_CIU2_BT_PS_BT_MCLK_NCO_MVAL(x)      (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BT_PS_BT_MCLK_NCO_MVAL_SHIFT)) & CIU2_CIU2_BT_PS_BT_MCLK_NCO_MVAL_MASK)

#define CIU2_CIU2_BT_PS_BT_MCLK_NCO_EN_MASK      (0x4000000U)
#define CIU2_CIU2_BT_PS_BT_MCLK_NCO_EN_SHIFT     (26U)
/*! bt_mclk_nco_en - BT_MCLK_NCO logic to count
 */
#define CIU2_CIU2_BT_PS_BT_MCLK_NCO_EN(x)        (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BT_PS_BT_MCLK_NCO_EN_SHIFT)) & CIU2_CIU2_BT_PS_BT_MCLK_NCO_EN_MASK)

#define CIU2_CIU2_BT_PS_BT_MCLK_TBG_NCO_SEL_MASK (0x8000000U)
#define CIU2_CIU2_BT_PS_BT_MCLK_TBG_NCO_SEL_SHIFT (27U)
/*! bt_mclk_tbg_nco_sel - BT_4M_PCM_CLK
 */
#define CIU2_CIU2_BT_PS_BT_MCLK_TBG_NCO_SEL(x)   (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BT_PS_BT_MCLK_TBG_NCO_SEL_SHIFT)) & CIU2_CIU2_BT_PS_BT_MCLK_TBG_NCO_SEL_MASK)

#define CIU2_CIU2_BT_PS_BT_MCLK_FROM_SOC_SEL_MASK (0x10000000U)
#define CIU2_CIU2_BT_PS_BT_MCLK_FROM_SOC_SEL_SHIFT (28U)
/*! bt_mclk_from_soc_sel - BT_MCLK
 */
#define CIU2_CIU2_BT_PS_BT_MCLK_FROM_SOC_SEL(x)  (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BT_PS_BT_MCLK_FROM_SOC_SEL_SHIFT)) & CIU2_CIU2_BT_PS_BT_MCLK_FROM_SOC_SEL_MASK)
/*! @} */

/*! @name CIU2_BT_PS2 - BT Clock Power Save 2 */
/*! @{ */

#define CIU2_CIU2_BT_PS2_BT_PCM_CLK_NCO_MVAL_MASK (0x3FFFFFFU)
#define CIU2_CIU2_BT_PS2_BT_PCM_CLK_NCO_MVAL_SHIFT (0U)
/*! bt_pcm_clk_nco_mval - BT_PCM_CLK NCO Module Step Control (default 0x0)
 */
#define CIU2_CIU2_BT_PS2_BT_PCM_CLK_NCO_MVAL(x)  (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BT_PS2_BT_PCM_CLK_NCO_MVAL_SHIFT)) & CIU2_CIU2_BT_PS2_BT_PCM_CLK_NCO_MVAL_MASK)

#define CIU2_CIU2_BT_PS2_BT_PCM_CLK_NCO_EN_MASK  (0x4000000U)
#define CIU2_CIU2_BT_PS2_BT_PCM_CLK_NCO_EN_SHIFT (26U)
/*! bt_pcm_clk_nco_en - BT_PCM_CLK_NCO logic to count
 */
#define CIU2_CIU2_BT_PS2_BT_PCM_CLK_NCO_EN(x)    (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BT_PS2_BT_PCM_CLK_NCO_EN_SHIFT)) & CIU2_CIU2_BT_PS2_BT_PCM_CLK_NCO_EN_MASK)

#define CIU2_CIU2_BT_PS2_BT_PCM_CLK_TBG_NCO_SEL_MASK (0x8000000U)
#define CIU2_CIU2_BT_PS2_BT_PCM_CLK_TBG_NCO_SEL_SHIFT (27U)
/*! bt_pcm_clk_tbg_nco_sel - BT_4M_PCM_CLK
 */
#define CIU2_CIU2_BT_PS2_BT_PCM_CLK_TBG_NCO_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BT_PS2_BT_PCM_CLK_TBG_NCO_SEL_SHIFT)) & CIU2_CIU2_BT_PS2_BT_PCM_CLK_TBG_NCO_SEL_MASK)
/*! @} */

/*! @name CIU2_BT_REF_CTRL - BT Ref Control */
/*! @{ */

#define CIU2_CIU2_BT_REF_CTRL_NCO_EN_MASK        (0x1U)
#define CIU2_CIU2_BT_REF_CTRL_NCO_EN_SHIFT       (0U)
/*! nco_en - Bluetooth Reference Clock NCO Enable information to APU.
 */
#define CIU2_CIU2_BT_REF_CTRL_NCO_EN(x)          (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BT_REF_CTRL_NCO_EN_SHIFT)) & CIU2_CIU2_BT_REF_CTRL_NCO_EN_MASK)

#define CIU2_CIU2_BT_REF_CTRL_NCO_SEL_MASK       (0x2U)
#define CIU2_CIU2_BT_REF_CTRL_NCO_SEL_SHIFT      (1U)
/*! nco_sel - Bluetooth Reference Clock NCO Select Value
 */
#define CIU2_CIU2_BT_REF_CTRL_NCO_SEL(x)         (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BT_REF_CTRL_NCO_SEL_SHIFT)) & CIU2_CIU2_BT_REF_CTRL_NCO_SEL_MASK)

#define CIU2_CIU2_BT_REF_CTRL_NCO_GEN_MASK       (0x3FFFCU)
#define CIU2_CIU2_BT_REF_CTRL_NCO_GEN_SHIFT      (2U)
/*! nco_gen - Bluetooth Reference Clock NCO Gen Value
 */
#define CIU2_CIU2_BT_REF_CTRL_NCO_GEN(x)         (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BT_REF_CTRL_NCO_GEN_SHIFT)) & CIU2_CIU2_BT_REF_CTRL_NCO_GEN_MASK)

#define CIU2_CIU2_BT_REF_CTRL_BT_CLK_NCO_REFCLK_SEL_MASK (0x100000U)
#define CIU2_CIU2_BT_REF_CTRL_BT_CLK_NCO_REFCLK_SEL_SHIFT (20U)
/*! bt_clk_nco_refclk_sel - BT clk (bt sys clk) selection
 */
#define CIU2_CIU2_BT_REF_CTRL_BT_CLK_NCO_REFCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BT_REF_CTRL_BT_CLK_NCO_REFCLK_SEL_SHIFT)) & CIU2_CIU2_BT_REF_CTRL_BT_CLK_NCO_REFCLK_SEL_MASK)
/*! @} */

/*! @name CIU2_BT_PS3 - BT Clock Power Save 3 */
/*! @{ */

#define CIU2_CIU2_BT_PS3_BTU_16M_CLK_NCO_STEP_CTRL_MASK (0x3FFFFFFU)
#define CIU2_CIU2_BT_PS3_BTU_16M_CLK_NCO_STEP_CTRL_SHIFT (0U)
/*! btu_16m_clk_nco_step_ctrl - BT_16M_CLK NCO Module Step Control
 */
#define CIU2_CIU2_BT_PS3_BTU_16M_CLK_NCO_STEP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BT_PS3_BTU_16M_CLK_NCO_STEP_CTRL_SHIFT)) & CIU2_CIU2_BT_PS3_BTU_16M_CLK_NCO_STEP_CTRL_MASK)

#define CIU2_CIU2_BT_PS3_BTU_16M_CLK_NCO_EN_MASK (0x4000000U)
#define CIU2_CIU2_BT_PS3_BTU_16M_CLK_NCO_EN_SHIFT (26U)
/*! btu_16m_clk_nco_en - BTU 16M Clock NCO Enable
 */
#define CIU2_CIU2_BT_PS3_BTU_16M_CLK_NCO_EN(x)   (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BT_PS3_BTU_16M_CLK_NCO_EN_SHIFT)) & CIU2_CIU2_BT_PS3_BTU_16M_CLK_NCO_EN_MASK)

#define CIU2_CIU2_BT_PS3_BTU_16M_CLK_NCO_SEL_MASK (0x8000000U)
#define CIU2_CIU2_BT_PS3_BTU_16M_CLK_NCO_SEL_SHIFT (27U)
/*! btu_16m_clk_nco_sel - BTU 16M clock NCO Select Value
 */
#define CIU2_CIU2_BT_PS3_BTU_16M_CLK_NCO_SEL(x)  (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BT_PS3_BTU_16M_CLK_NCO_SEL_SHIFT)) & CIU2_CIU2_BT_PS3_BTU_16M_CLK_NCO_SEL_MASK)

#define CIU2_CIU2_BT_PS3_BTU_CLK_NCO_MODE_MASK   (0x20000000U)
#define CIU2_CIU2_BT_PS3_BTU_CLK_NCO_MODE_SHIFT  (29U)
/*! btu_clk_nco_mode - BTU Clock source from ref clock (nco mode)
 */
#define CIU2_CIU2_BT_PS3_BTU_CLK_NCO_MODE(x)     (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BT_PS3_BTU_CLK_NCO_MODE_SHIFT)) & CIU2_CIU2_BT_PS3_BTU_CLK_NCO_MODE_MASK)
/*! @} */

/*! @name CIU2_BTU_ECO_CTRL - BTU ECO Control */
/*! @{ */

#define CIU2_CIU2_BTU_ECO_CTRL_ECO_BITS_MASK     (0xFFFFFFFFU)
#define CIU2_CIU2_BTU_ECO_CTRL_ECO_BITS_SHIFT    (0U)
/*! eco_bits - Reserved
 */
#define CIU2_CIU2_BTU_ECO_CTRL_ECO_BITS(x)       (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BTU_ECO_CTRL_ECO_BITS_SHIFT)) & CIU2_CIU2_BTU_ECO_CTRL_ECO_BITS_MASK)
/*! @} */

/*! @name CIU2_INT_MASK - CIU2 Interrupt Mask */
/*! @{ */

#define CIU2_CIU2_INT_MASK_MASK_MASK             (0xFFFFFFFFU)
#define CIU2_CIU2_INT_MASK_MASK_SHIFT            (0U)
/*! mask - Interrupt Mask for CIU2 Interrupts
 */
#define CIU2_CIU2_INT_MASK_MASK(x)               (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_INT_MASK_MASK_SHIFT)) & CIU2_CIU2_INT_MASK_MASK_MASK)
/*! @} */

/*! @name CIU2_INT_SELECT - CIU2 Interrupt Select */
/*! @{ */

#define CIU2_CIU2_INT_SELECT_SEL_MASK            (0xFFFFFFFFU)
#define CIU2_CIU2_INT_SELECT_SEL_SHIFT           (0U)
/*! sel - Interrupt Read/Write Clear for CIU2 Interrupts
 */
#define CIU2_CIU2_INT_SELECT_SEL(x)              (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_INT_SELECT_SEL_SHIFT)) & CIU2_CIU2_INT_SELECT_SEL_MASK)
/*! @} */

/*! @name CIU2_INT_EVENT_MASK - CIU2 Interrupt Event Mask */
/*! @{ */

#define CIU2_CIU2_INT_EVENT_MASK_MASK_MASK       (0xFFFFFFFFU)
#define CIU2_CIU2_INT_EVENT_MASK_MASK_SHIFT      (0U)
/*! mask - Interrupt Event Mask for CIU2 Interrupts
 */
#define CIU2_CIU2_INT_EVENT_MASK_MASK(x)         (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_INT_EVENT_MASK_MASK_SHIFT)) & CIU2_CIU2_INT_EVENT_MASK_MASK_MASK)
/*! @} */

/*! @name CIU2_INT_STATUS - CIU2 Interrupt Status */
/*! @{ */

#define CIU2_CIU2_INT_STATUS_CIU_ISR_MASK        (0xFFFFFFFFU)
#define CIU2_CIU2_INT_STATUS_CIU_ISR_SHIFT       (0U)
/*! ciu_isr - CIU2 Interrupt Status (ISR)
 */
#define CIU2_CIU2_INT_STATUS_CIU_ISR(x)          (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_INT_STATUS_CIU_ISR_SHIFT)) & CIU2_CIU2_INT_STATUS_CIU_ISR_MASK)
/*! @} */

/*! @name CPU2_ERR_INT_MASK - CPU2 ERR Interrupt Mask */
/*! @{ */

#define CIU2_CPU2_ERR_INT_MASK_MASK_MASK         (0xFFFFFFFFU)
#define CIU2_CPU2_ERR_INT_MASK_MASK_SHIFT        (0U)
/*! mask - Interrupt Mask for CPU2 ERR Interrupts
 */
#define CIU2_CPU2_ERR_INT_MASK_MASK(x)           (((uint32_t)(((uint32_t)(x)) << CIU2_CPU2_ERR_INT_MASK_MASK_SHIFT)) & CIU2_CPU2_ERR_INT_MASK_MASK_MASK)
/*! @} */

/*! @name CPU2_ERR_INT_SELECT - CPU2 ERR Interrupt Clear Select */
/*! @{ */

#define CIU2_CPU2_ERR_INT_SELECT_SEL_MASK        (0xFFFFFFFFU)
#define CIU2_CPU2_ERR_INT_SELECT_SEL_SHIFT       (0U)
/*! sel - Interrupt Read/Write Clear for CPU2 ERR Interrupts
 */
#define CIU2_CPU2_ERR_INT_SELECT_SEL(x)          (((uint32_t)(((uint32_t)(x)) << CIU2_CPU2_ERR_INT_SELECT_SEL_SHIFT)) & CIU2_CPU2_ERR_INT_SELECT_SEL_MASK)
/*! @} */

/*! @name CPU2_ERR_INT_EVENT_MASK - CPU2 ERR Interrupt Event Mask */
/*! @{ */

#define CIU2_CPU2_ERR_INT_EVENT_MASK_MASK_MASK   (0xFFFFFFFFU)
#define CIU2_CPU2_ERR_INT_EVENT_MASK_MASK_SHIFT  (0U)
/*! mask - Interrupt Event Mask for CPU2 ERR Interrupts
 */
#define CIU2_CPU2_ERR_INT_EVENT_MASK_MASK(x)     (((uint32_t)(((uint32_t)(x)) << CIU2_CPU2_ERR_INT_EVENT_MASK_MASK_SHIFT)) & CIU2_CPU2_ERR_INT_EVENT_MASK_MASK_MASK)
/*! @} */

/*! @name CPU2_ERR_INT_STATUS - CPU2 ERR Interrupt Status */
/*! @{ */

#define CIU2_CPU2_ERR_INT_STATUS_ERR_ISR_MASK    (0xFFFFFFFFU)
#define CIU2_CPU2_ERR_INT_STATUS_ERR_ISR_SHIFT   (0U)
/*! err_isr - CPU2 ERR Interrupt Status (ISR)
 */
#define CIU2_CPU2_ERR_INT_STATUS_ERR_ISR(x)      (((uint32_t)(((uint32_t)(x)) << CIU2_CPU2_ERR_INT_STATUS_ERR_ISR_SHIFT)) & CIU2_CPU2_ERR_INT_STATUS_ERR_ISR_MASK)
/*! @} */

/*! @name CPU2_ERR_INT2_MASK - CPU2 ERR Interrupt 2 Mask */
/*! @{ */

#define CIU2_CPU2_ERR_INT2_MASK_MASK_MASK        (0xFFFFFFFFU)
#define CIU2_CPU2_ERR_INT2_MASK_MASK_SHIFT       (0U)
/*! mask - Interrupt Mask for CPU2 ERR Interrupts 2
 */
#define CIU2_CPU2_ERR_INT2_MASK_MASK(x)          (((uint32_t)(((uint32_t)(x)) << CIU2_CPU2_ERR_INT2_MASK_MASK_SHIFT)) & CIU2_CPU2_ERR_INT2_MASK_MASK_MASK)
/*! @} */

/*! @name CPU2_ERR_INT2_SELECT - CPU2 ERR Interrupt 2 Clear Select */
/*! @{ */

#define CIU2_CPU2_ERR_INT2_SELECT_SEL_MASK       (0xFFFFFFFFU)
#define CIU2_CPU2_ERR_INT2_SELECT_SEL_SHIFT      (0U)
/*! sel - Interrupt Read/Write Clear for CPU2 ERR Interrupts 2
 */
#define CIU2_CPU2_ERR_INT2_SELECT_SEL(x)         (((uint32_t)(((uint32_t)(x)) << CIU2_CPU2_ERR_INT2_SELECT_SEL_SHIFT)) & CIU2_CPU2_ERR_INT2_SELECT_SEL_MASK)
/*! @} */

/*! @name CPU2_ERR_INT2_EVENT_MASK - CPU2 ERR Interrupt 2 Event Mask */
/*! @{ */

#define CIU2_CPU2_ERR_INT2_EVENT_MASK_MASK_MASK  (0xFFFFFFFFU)
#define CIU2_CPU2_ERR_INT2_EVENT_MASK_MASK_SHIFT (0U)
/*! mask - Interrupt Event Mask for CPU2 ERR Interrupts 2
 */
#define CIU2_CPU2_ERR_INT2_EVENT_MASK_MASK(x)    (((uint32_t)(((uint32_t)(x)) << CIU2_CPU2_ERR_INT2_EVENT_MASK_MASK_SHIFT)) & CIU2_CPU2_ERR_INT2_EVENT_MASK_MASK_MASK)
/*! @} */

/*! @name CPU2_ERR_INT2_STATUS - CPU2 ERR Interrupt 2 Status */
/*! @{ */

#define CIU2_CPU2_ERR_INT2_STATUS_ERR_ISR_MASK   (0xFFFFFFFFU)
#define CIU2_CPU2_ERR_INT2_STATUS_ERR_ISR_SHIFT  (0U)
/*! err_isr - CPU1 ERR Interrupt 2 Status (ISR)
 */
#define CIU2_CPU2_ERR_INT2_STATUS_ERR_ISR(x)     (((uint32_t)(((uint32_t)(x)) << CIU2_CPU2_ERR_INT2_STATUS_ERR_ISR_SHIFT)) & CIU2_CPU2_ERR_INT2_STATUS_ERR_ISR_MASK)
/*! @} */

/*! @name CIU2_CPU_CPU2_MSG_CTRL - CPU2 message register */
/*! @{ */

#define CIU2_CIU2_CPU_CPU2_MSG_CTRL_CPU1_TO_CPU2_MSG_RDY_MASK (0x1U)
#define CIU2_CIU2_CPU_CPU2_MSG_CTRL_CPU1_TO_CPU2_MSG_RDY_SHIFT (0U)
/*! cpu1_to_cpu2_msg_rdy - CPU1 Message for CPU2 is ready. This is self clearing bit. The CPU1
 *    writes 1 to indicate that message for CPU2 is ready. This generates an Interrupt to CPU2 via APU.
 *    This is old schem and we should use IMU based scheme.
 */
#define CIU2_CIU2_CPU_CPU2_MSG_CTRL_CPU1_TO_CPU2_MSG_RDY(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU_CPU2_MSG_CTRL_CPU1_TO_CPU2_MSG_RDY_SHIFT)) & CIU2_CIU2_CPU_CPU2_MSG_CTRL_CPU1_TO_CPU2_MSG_RDY_MASK)

#define CIU2_CIU2_CPU_CPU2_MSG_CTRL_CPU3_TO_CPU2_MSG_RDY_MASK (0x2U)
#define CIU2_CIU2_CPU_CPU2_MSG_CTRL_CPU3_TO_CPU2_MSG_RDY_SHIFT (1U)
/*! cpu3_to_cpu2_msg_rdy - CPU3 Message for CPU2 is ready. This is self clearing bit. The CPU3
 *    writes 1 to indicate that message for CPU2 is ready. This generates an Interrupt to CPU2 via APU.
 *    This is old schem and we should use IMU based scheme.
 */
#define CIU2_CIU2_CPU_CPU2_MSG_CTRL_CPU3_TO_CPU2_MSG_RDY(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU_CPU2_MSG_CTRL_CPU3_TO_CPU2_MSG_RDY_SHIFT)) & CIU2_CIU2_CPU_CPU2_MSG_CTRL_CPU3_TO_CPU2_MSG_RDY_MASK)

#define CIU2_CIU2_CPU_CPU2_MSG_CTRL_CPU1_TO_CPU2_MSG_PROCESS_DONE_MASK (0x100U)
#define CIU2_CIU2_CPU_CPU2_MSG_CTRL_CPU1_TO_CPU2_MSG_PROCESS_DONE_SHIFT (8U)
/*! cpu1_to_cpu2_msg_process_done - CPU1 Message for CPU2 has been read by CPU2 and executed. This
 *    is self clearing bit. The CPU2 writes 1 to indicate that message send by CPU1 is executed. This
 *    generates an Interrupt to CPU1 via CIU1.
 */
#define CIU2_CIU2_CPU_CPU2_MSG_CTRL_CPU1_TO_CPU2_MSG_PROCESS_DONE(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU_CPU2_MSG_CTRL_CPU1_TO_CPU2_MSG_PROCESS_DONE_SHIFT)) & CIU2_CIU2_CPU_CPU2_MSG_CTRL_CPU1_TO_CPU2_MSG_PROCESS_DONE_MASK)

#define CIU2_CIU2_CPU_CPU2_MSG_CTRL_CPU3_TO_CPU2_MSG_PROCESS_DONE_MASK (0x200U)
#define CIU2_CIU2_CPU_CPU2_MSG_CTRL_CPU3_TO_CPU2_MSG_PROCESS_DONE_SHIFT (9U)
/*! cpu3_to_cpu2_msg_process_done - CPU3 Message for CPU2 has been read by CPU2 and executed. This
 *    is self clearing bit. The CPU2 writes 1 to indicate that message send by CPU3 is executed. This
 *    generates an Interrupt to CPU3 via CIU3.
 */
#define CIU2_CIU2_CPU_CPU2_MSG_CTRL_CPU3_TO_CPU2_MSG_PROCESS_DONE(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU_CPU2_MSG_CTRL_CPU3_TO_CPU2_MSG_PROCESS_DONE_SHIFT)) & CIU2_CIU2_CPU_CPU2_MSG_CTRL_CPU3_TO_CPU2_MSG_PROCESS_DONE_MASK)
/*! @} */

/*! @name CIU2_IMU_CPU1_WR_MSG_TO_CPU2 - CPU1 write message to CPU2 */
/*! @{ */

#define CIU2_CIU2_IMU_CPU1_WR_MSG_TO_CPU2_CPU1_WR_MSG_CPU2_MASK (0xFFFFFFFFU)
#define CIU2_CIU2_IMU_CPU1_WR_MSG_TO_CPU2_CPU1_WR_MSG_CPU2_SHIFT (0U)
/*! cpu1_wr_msg_cpu2 - Write CPU1 message data to CPU2 (push to FIFO)
 */
#define CIU2_CIU2_IMU_CPU1_WR_MSG_TO_CPU2_CPU1_WR_MSG_CPU2(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU1_WR_MSG_TO_CPU2_CPU1_WR_MSG_CPU2_SHIFT)) & CIU2_CIU2_IMU_CPU1_WR_MSG_TO_CPU2_CPU1_WR_MSG_CPU2_MASK)
/*! @} */

/*! @name CIU2_IMU_CPU1_RD_MSG_FROM_CPU2 - CPU1 read message from CPU2 */
/*! @{ */

#define CIU2_CIU2_IMU_CPU1_RD_MSG_FROM_CPU2_CPU1_RD_MSG_CPU2_MASK (0xFFFFFFFFU)
#define CIU2_CIU2_IMU_CPU1_RD_MSG_FROM_CPU2_CPU1_RD_MSG_CPU2_SHIFT (0U)
/*! cpu1_rd_msg_cpu2 - CPU1 read message data from CPU2 (pop from FIFO)
 */
#define CIU2_CIU2_IMU_CPU1_RD_MSG_FROM_CPU2_CPU1_RD_MSG_CPU2(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU1_RD_MSG_FROM_CPU2_CPU1_RD_MSG_CPU2_SHIFT)) & CIU2_CIU2_IMU_CPU1_RD_MSG_FROM_CPU2_CPU1_RD_MSG_CPU2_MASK)
/*! @} */

/*! @name CIU2_IMU_CPU1_CPU2_MSG_FIFO_STATUS - CPU1 to CPU2 message FIFO status */
/*! @{ */

#define CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_STATUS_CPU1_TO_CPU2_MSG_FIFO_LOCKED_MASK (0x1U)
#define CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_STATUS_CPU1_TO_CPU2_MSG_FIFO_LOCKED_SHIFT (0U)
/*! cpu1_to_cpu2_msg_fifo_locked - cpu1_to_cpu2_msg_fifo_locked
 */
#define CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_STATUS_CPU1_TO_CPU2_MSG_FIFO_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_STATUS_CPU1_TO_CPU2_MSG_FIFO_LOCKED_SHIFT)) & CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_STATUS_CPU1_TO_CPU2_MSG_FIFO_LOCKED_MASK)

#define CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_STATUS_CPU1_TO_CPU2_MSG_FIFO_ALMOST_FULL_MASK (0x2U)
#define CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_STATUS_CPU1_TO_CPU2_MSG_FIFO_ALMOST_FULL_SHIFT (1U)
/*! cpu1_to_cpu2_msg_fifo_almost_full - cpu1_to_cpu2_msg_fifo_almost_full (based upon FIFO watermark)
 */
#define CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_STATUS_CPU1_TO_CPU2_MSG_FIFO_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_STATUS_CPU1_TO_CPU2_MSG_FIFO_ALMOST_FULL_SHIFT)) & CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_STATUS_CPU1_TO_CPU2_MSG_FIFO_ALMOST_FULL_MASK)

#define CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_STATUS_CPU1_TO_CPU2_MSG_FIFO_FULL_MASK (0x4U)
#define CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_STATUS_CPU1_TO_CPU2_MSG_FIFO_FULL_SHIFT (2U)
/*! cpu1_to_cpu2_msg_fifo_full - cpu1_to_cpu2_msg_fifo_full (based upon FIFO depth)
 */
#define CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_STATUS_CPU1_TO_CPU2_MSG_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_STATUS_CPU1_TO_CPU2_MSG_FIFO_FULL_SHIFT)) & CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_STATUS_CPU1_TO_CPU2_MSG_FIFO_FULL_MASK)

#define CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_STATUS_CPU1_TO_CPU2_MSG_FIFO_EMPTY_MASK (0x8U)
#define CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_STATUS_CPU1_TO_CPU2_MSG_FIFO_EMPTY_SHIFT (3U)
/*! cpu1_to_cpu2_msg_fifo_empty - cpu1_to_cpu2_msg_fifo_empty
 */
#define CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_STATUS_CPU1_TO_CPU2_MSG_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_STATUS_CPU1_TO_CPU2_MSG_FIFO_EMPTY_SHIFT)) & CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_STATUS_CPU1_TO_CPU2_MSG_FIFO_EMPTY_MASK)

#define CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_STATUS_CPU1_TO_CPU2_MSG_COUNT_MASK (0x1F0U)
#define CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_STATUS_CPU1_TO_CPU2_MSG_COUNT_SHIFT (4U)
/*! cpu1_to_cpu2_msg_count - cpu1_to_cpu2_msg_count
 */
#define CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_STATUS_CPU1_TO_CPU2_MSG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_STATUS_CPU1_TO_CPU2_MSG_COUNT_SHIFT)) & CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_STATUS_CPU1_TO_CPU2_MSG_COUNT_MASK)

#define CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_STATUS_CPU1_TO_CPU2_MSG_FIFO_WR_PTR_MASK (0xF0000U)
#define CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_STATUS_CPU1_TO_CPU2_MSG_FIFO_WR_PTR_SHIFT (16U)
/*! cpu1_to_cpu2_msg_fifo_wr_ptr - cpu1 to cpu2 msg fifo write pointer for debug
 */
#define CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_STATUS_CPU1_TO_CPU2_MSG_FIFO_WR_PTR(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_STATUS_CPU1_TO_CPU2_MSG_FIFO_WR_PTR_SHIFT)) & CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_STATUS_CPU1_TO_CPU2_MSG_FIFO_WR_PTR_MASK)

#define CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_STATUS_CPU1_TO_CPU2_MSG_FIFO_RD_PTR_MASK (0xF00000U)
#define CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_STATUS_CPU1_TO_CPU2_MSG_FIFO_RD_PTR_SHIFT (20U)
/*! cpu1_to_cpu2_msg_fifo_rd_ptr - cpu1 to cpu2 msg fifo read pointer for debug
 */
#define CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_STATUS_CPU1_TO_CPU2_MSG_FIFO_RD_PTR(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_STATUS_CPU1_TO_CPU2_MSG_FIFO_RD_PTR_SHIFT)) & CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_STATUS_CPU1_TO_CPU2_MSG_FIFO_RD_PTR_MASK)
/*! @} */

/*! @name CIU2_IMU_CPU1_CPU2_MSG_FIFO_CNTL - CPU1 to CPU2 message FIFO control */
/*! @{ */

#define CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_CNTL_CPU1_MSG_RDY_INT_CLR_MASK (0x1U)
#define CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_CNTL_CPU1_MSG_RDY_INT_CLR_SHIFT (0U)
/*! cpu1_msg_rdy_int_clr - Writing 1 to this bit will clear message ready interrupt to CPU1 (self clear bit)
 */
#define CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_CNTL_CPU1_MSG_RDY_INT_CLR(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_CNTL_CPU1_MSG_RDY_INT_CLR_SHIFT)) & CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_CNTL_CPU1_MSG_RDY_INT_CLR_MASK)

#define CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_CNTL_CPU1_MSG_SP_AV_INT_CLR_MASK (0x100U)
#define CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_CNTL_CPU1_MSG_SP_AV_INT_CLR_SHIFT (8U)
/*! cpu1_msg_sp_av_int_clr - Writing 1 to this bit will clear message space available interrupt to CPU1 (self clear bit)
 */
#define CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_CNTL_CPU1_MSG_SP_AV_INT_CLR(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_CNTL_CPU1_MSG_SP_AV_INT_CLR_SHIFT)) & CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_CNTL_CPU1_MSG_SP_AV_INT_CLR_MASK)

#define CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_CNTL_CPU1_TO_CPU2_MSG_FIFO_FLUSH_MASK (0x10000U)
#define CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_CNTL_CPU1_TO_CPU2_MSG_FIFO_FLUSH_SHIFT (16U)
/*! cpu1_to_cpu2_msg_fifo_flush - Writing 1 to this bit will flush cpu1_to_cpu2 message fifo
 */
#define CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_CNTL_CPU1_TO_CPU2_MSG_FIFO_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_CNTL_CPU1_TO_CPU2_MSG_FIFO_FLUSH_SHIFT)) & CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_CNTL_CPU1_TO_CPU2_MSG_FIFO_FLUSH_MASK)

#define CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_CNTL_CPU1_WAIT_FOR_ACK_MASK (0x20000U)
#define CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_CNTL_CPU1_WAIT_FOR_ACK_SHIFT (17U)
#define CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_CNTL_CPU1_WAIT_FOR_ACK(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_CNTL_CPU1_WAIT_FOR_ACK_SHIFT)) & CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_CNTL_CPU1_WAIT_FOR_ACK_MASK)

#define CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_CNTL_CPU1_CPU2_MSG_FIFO_FULL_WATERMARK_MASK (0xF00000U)
#define CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_CNTL_CPU1_CPU2_MSG_FIFO_FULL_WATERMARK_SHIFT (20U)
/*! cpu1_cpu2_msg_fifo_full_watermark - cpu1_to_cpu2 message fifo full watermark (space avail intr based upon it)
 */
#define CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_CNTL_CPU1_CPU2_MSG_FIFO_FULL_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_CNTL_CPU1_CPU2_MSG_FIFO_FULL_WATERMARK_SHIFT)) & CIU2_CIU2_IMU_CPU1_CPU2_MSG_FIFO_CNTL_CPU1_CPU2_MSG_FIFO_FULL_WATERMARK_MASK)
/*! @} */

/*! @name CIU2_IMU_CPU2_RD_MSG_FROM_CPU1_VAL_DBG - CPU2 last message read (from cpu1) */
/*! @{ */

#define CIU2_CIU2_IMU_CPU2_RD_MSG_FROM_CPU1_VAL_DBG_CPU2_RD_MSG_MASK (0xFFFFFFFFU)
#define CIU2_CIU2_IMU_CPU2_RD_MSG_FROM_CPU1_VAL_DBG_CPU2_RD_MSG_SHIFT (0U)
/*! cpu2_rd_msg - CPU2 last message read (from cpu1)
 */
#define CIU2_CIU2_IMU_CPU2_RD_MSG_FROM_CPU1_VAL_DBG_CPU2_RD_MSG(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU2_RD_MSG_FROM_CPU1_VAL_DBG_CPU2_RD_MSG_SHIFT)) & CIU2_CIU2_IMU_CPU2_RD_MSG_FROM_CPU1_VAL_DBG_CPU2_RD_MSG_MASK)
/*! @} */

/*! @name CIU2_IMU_CPU2_WR_MSG_TO_CPU1 - CPU2 write message to CPU1 */
/*! @{ */

#define CIU2_CIU2_IMU_CPU2_WR_MSG_TO_CPU1_CPU2_WR_MSG_CPU1_MASK (0xFFFFFFFFU)
#define CIU2_CIU2_IMU_CPU2_WR_MSG_TO_CPU1_CPU2_WR_MSG_CPU1_SHIFT (0U)
/*! cpu2_wr_msg_cpu1 - Write CPU2 message data to CPU1 (push to FIFO)
 */
#define CIU2_CIU2_IMU_CPU2_WR_MSG_TO_CPU1_CPU2_WR_MSG_CPU1(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU2_WR_MSG_TO_CPU1_CPU2_WR_MSG_CPU1_SHIFT)) & CIU2_CIU2_IMU_CPU2_WR_MSG_TO_CPU1_CPU2_WR_MSG_CPU1_MASK)
/*! @} */

/*! @name CIU2_IMU_CPU2_RD_MSG_FROM_CPU1 - CPU2 read message from CPU1 */
/*! @{ */

#define CIU2_CIU2_IMU_CPU2_RD_MSG_FROM_CPU1_CPU2_RD_MSG_CPU1_MASK (0xFFFFFFFFU)
#define CIU2_CIU2_IMU_CPU2_RD_MSG_FROM_CPU1_CPU2_RD_MSG_CPU1_SHIFT (0U)
/*! cpu2_rd_msg_cpu1 - CPU2 read message data from CPU1 (pop from FIFO)
 */
#define CIU2_CIU2_IMU_CPU2_RD_MSG_FROM_CPU1_CPU2_RD_MSG_CPU1(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU2_RD_MSG_FROM_CPU1_CPU2_RD_MSG_CPU1_SHIFT)) & CIU2_CIU2_IMU_CPU2_RD_MSG_FROM_CPU1_CPU2_RD_MSG_CPU1_MASK)
/*! @} */

/*! @name CIU2_IMU_CPU2_CPU1_MSG_FIFO_STATUS - CPU2 to CPU1 message FIFO status */
/*! @{ */

#define CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_STATUS_CPU2_TO_CPU1_MSG_FIFO_LOCKED_MASK (0x1U)
#define CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_STATUS_CPU2_TO_CPU1_MSG_FIFO_LOCKED_SHIFT (0U)
/*! cpu2_to_cpu1_msg_fifo_locked - cpu2_to_cpu1_msg_fifo_locked
 */
#define CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_STATUS_CPU2_TO_CPU1_MSG_FIFO_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_STATUS_CPU2_TO_CPU1_MSG_FIFO_LOCKED_SHIFT)) & CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_STATUS_CPU2_TO_CPU1_MSG_FIFO_LOCKED_MASK)

#define CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_STATUS_CPU2_TO_CPU1_MSG_FIFO_ALMOST_FULL_MASK (0x2U)
#define CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_STATUS_CPU2_TO_CPU1_MSG_FIFO_ALMOST_FULL_SHIFT (1U)
/*! cpu2_to_cpu1_msg_fifo_almost_full - cpu2_to_cpu1_msg_fifo_almost_full (based upon FIFO watermark)
 */
#define CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_STATUS_CPU2_TO_CPU1_MSG_FIFO_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_STATUS_CPU2_TO_CPU1_MSG_FIFO_ALMOST_FULL_SHIFT)) & CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_STATUS_CPU2_TO_CPU1_MSG_FIFO_ALMOST_FULL_MASK)

#define CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_STATUS_CPU2_TO_CPU1_MSG_FIFO_FULL_MASK (0x4U)
#define CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_STATUS_CPU2_TO_CPU1_MSG_FIFO_FULL_SHIFT (2U)
/*! cpu2_to_cpu1_msg_fifo_full - cpu2_to_cpu1_msg_fifo_full (based upon FIFO depth)
 */
#define CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_STATUS_CPU2_TO_CPU1_MSG_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_STATUS_CPU2_TO_CPU1_MSG_FIFO_FULL_SHIFT)) & CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_STATUS_CPU2_TO_CPU1_MSG_FIFO_FULL_MASK)

#define CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_STATUS_CPU2_TO_CPU1_MSG_FIFO_EMPTY_MASK (0x8U)
#define CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_STATUS_CPU2_TO_CPU1_MSG_FIFO_EMPTY_SHIFT (3U)
/*! cpu2_to_cpu1_msg_fifo_empty - cpu2_to_cpu1_msg_fifo_empty
 */
#define CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_STATUS_CPU2_TO_CPU1_MSG_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_STATUS_CPU2_TO_CPU1_MSG_FIFO_EMPTY_SHIFT)) & CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_STATUS_CPU2_TO_CPU1_MSG_FIFO_EMPTY_MASK)

#define CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_STATUS_CPU2_TO_CPU1_MSG_COUNT_MASK (0x1F0U)
#define CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_STATUS_CPU2_TO_CPU1_MSG_COUNT_SHIFT (4U)
/*! cpu2_to_cpu1_msg_count - cpu2_to_cpu1_msg_count
 */
#define CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_STATUS_CPU2_TO_CPU1_MSG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_STATUS_CPU2_TO_CPU1_MSG_COUNT_SHIFT)) & CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_STATUS_CPU2_TO_CPU1_MSG_COUNT_MASK)

#define CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_STATUS_CPU2_TO_CPU1_MSG_FIFO_WR_PTR_MASK (0xF0000U)
#define CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_STATUS_CPU2_TO_CPU1_MSG_FIFO_WR_PTR_SHIFT (16U)
/*! cpu2_to_cpu1_msg_fifo_wr_ptr - cpu1 to cpu2 msg fifo write pointer for debug
 */
#define CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_STATUS_CPU2_TO_CPU1_MSG_FIFO_WR_PTR(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_STATUS_CPU2_TO_CPU1_MSG_FIFO_WR_PTR_SHIFT)) & CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_STATUS_CPU2_TO_CPU1_MSG_FIFO_WR_PTR_MASK)

#define CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_STATUS_CPU2_TO_CPU1_MSG_FIFO_RD_PTR_MASK (0xF00000U)
#define CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_STATUS_CPU2_TO_CPU1_MSG_FIFO_RD_PTR_SHIFT (20U)
/*! cpu2_to_cpu1_msg_fifo_rd_ptr - cpu1 to cpu2 msg fifo read pointer for debug
 */
#define CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_STATUS_CPU2_TO_CPU1_MSG_FIFO_RD_PTR(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_STATUS_CPU2_TO_CPU1_MSG_FIFO_RD_PTR_SHIFT)) & CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_STATUS_CPU2_TO_CPU1_MSG_FIFO_RD_PTR_MASK)
/*! @} */

/*! @name CIU2_IMU_CPU2_CPU1_MSG_FIFO_CNTL - CPU2 to CPU1 message FIFO control */
/*! @{ */

#define CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_CNTL_CPU2_MSG_RDY_INT_CLR_MASK (0x1U)
#define CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_CNTL_CPU2_MSG_RDY_INT_CLR_SHIFT (0U)
/*! cpu2_msg_rdy_int_clr - Writing 1 to this bit will clear message ready interrupt to CPU2 (self clear bit)
 */
#define CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_CNTL_CPU2_MSG_RDY_INT_CLR(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_CNTL_CPU2_MSG_RDY_INT_CLR_SHIFT)) & CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_CNTL_CPU2_MSG_RDY_INT_CLR_MASK)

#define CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_CNTL_CPU2_MSG_SP_AV_INT_CLR_MASK (0x100U)
#define CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_CNTL_CPU2_MSG_SP_AV_INT_CLR_SHIFT (8U)
/*! cpu2_msg_sp_av_int_clr - Writing 1 to this bit will clear message space available interrupt to CPU2 (self clear bit)
 */
#define CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_CNTL_CPU2_MSG_SP_AV_INT_CLR(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_CNTL_CPU2_MSG_SP_AV_INT_CLR_SHIFT)) & CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_CNTL_CPU2_MSG_SP_AV_INT_CLR_MASK)

#define CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_CNTL_CPU2_TO_CPU1_MSG_FIFO_FLUSH_MASK (0x10000U)
#define CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_CNTL_CPU2_TO_CPU1_MSG_FIFO_FLUSH_SHIFT (16U)
/*! cpu2_to_cpu1_msg_fifo_flush - Writing 1 to this bit will flush cpu2_to_cpu1 message fifo
 */
#define CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_CNTL_CPU2_TO_CPU1_MSG_FIFO_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_CNTL_CPU2_TO_CPU1_MSG_FIFO_FLUSH_SHIFT)) & CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_CNTL_CPU2_TO_CPU1_MSG_FIFO_FLUSH_MASK)

#define CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_CNTL_CPU2_WAIT_FOR_ACK_MASK (0x20000U)
#define CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_CNTL_CPU2_WAIT_FOR_ACK_SHIFT (17U)
#define CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_CNTL_CPU2_WAIT_FOR_ACK(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_CNTL_CPU2_WAIT_FOR_ACK_SHIFT)) & CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_CNTL_CPU2_WAIT_FOR_ACK_MASK)

#define CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_CNTL_CPU2_CPU1_MSG_FIFO_FULL_WATERMARK_MASK (0xF00000U)
#define CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_CNTL_CPU2_CPU1_MSG_FIFO_FULL_WATERMARK_SHIFT (20U)
/*! cpu2_cpu1_msg_fifo_full_watermark - cpu2_to_cpu1 message fifo full watermark (space avail intr based upon it)
 */
#define CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_CNTL_CPU2_CPU1_MSG_FIFO_FULL_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_CNTL_CPU2_CPU1_MSG_FIFO_FULL_WATERMARK_SHIFT)) & CIU2_CIU2_IMU_CPU2_CPU1_MSG_FIFO_CNTL_CPU2_CPU1_MSG_FIFO_FULL_WATERMARK_MASK)
/*! @} */

/*! @name CIU2_IMU_CPU1_RD_MSG_FROM_CPU2_VAL_DBG - CPU1 last message read (from cpu2) */
/*! @{ */

#define CIU2_CIU2_IMU_CPU1_RD_MSG_FROM_CPU2_VAL_DBG_CPU1_RD_MSG_MASK (0xFFFFFFFFU)
#define CIU2_CIU2_IMU_CPU1_RD_MSG_FROM_CPU2_VAL_DBG_CPU1_RD_MSG_SHIFT (0U)
/*! cpu1_rd_msg - CPU1 last message read (from cpu2)
 */
#define CIU2_CIU2_IMU_CPU1_RD_MSG_FROM_CPU2_VAL_DBG_CPU1_RD_MSG(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_IMU_CPU1_RD_MSG_FROM_CPU2_VAL_DBG_CPU1_RD_MSG_SHIFT)) & CIU2_CIU2_IMU_CPU1_RD_MSG_FROM_CPU2_VAL_DBG_CPU1_RD_MSG_MASK)
/*! @} */

/*! @name CIU2_BCA1_CPU2_INT_MASK - BCA1 to CPU2 Interrupt Mask */
/*! @{ */

#define CIU2_CIU2_BCA1_CPU2_INT_MASK_IMR_MASK    (0xFFFFFFFFU)
#define CIU2_CIU2_BCA1_CPU2_INT_MASK_IMR_SHIFT   (0U)
/*! imr - Interrupt Mask for BCA1 to CPU2 Interrupts
 */
#define CIU2_CIU2_BCA1_CPU2_INT_MASK_IMR(x)      (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BCA1_CPU2_INT_MASK_IMR_SHIFT)) & CIU2_CIU2_BCA1_CPU2_INT_MASK_IMR_MASK)
/*! @} */

/*! @name CIU2_BCA1_CPU2_INT_SELECT - BCA1 to CPU2 Interrupt Select */
/*! @{ */

#define CIU2_CIU2_BCA1_CPU2_INT_SELECT_RSR_MASK  (0xFFFFFFFFU)
#define CIU2_CIU2_BCA1_CPU2_INT_SELECT_RSR_SHIFT (0U)
/*! rsr - Interrupt Read/Write Clear for BCA1 to CPU2 Interrupts
 */
#define CIU2_CIU2_BCA1_CPU2_INT_SELECT_RSR(x)    (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BCA1_CPU2_INT_SELECT_RSR_SHIFT)) & CIU2_CIU2_BCA1_CPU2_INT_SELECT_RSR_MASK)
/*! @} */

/*! @name CIU2_BCA1_CPU2_INT_EVENT_MASK - BCA1 to CPU2 Interrupt Event Mask */
/*! @{ */

#define CIU2_CIU2_BCA1_CPU2_INT_EVENT_MASK_SMR_MASK (0xFFFFFFFFU)
#define CIU2_CIU2_BCA1_CPU2_INT_EVENT_MASK_SMR_SHIFT (0U)
/*! smr - Interrupt Event Mask for BCA1 to CPU2 Interrupts
 */
#define CIU2_CIU2_BCA1_CPU2_INT_EVENT_MASK_SMR(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BCA1_CPU2_INT_EVENT_MASK_SMR_SHIFT)) & CIU2_CIU2_BCA1_CPU2_INT_EVENT_MASK_SMR_MASK)
/*! @} */

/*! @name CIU2_BCA1_CPU2_INT_STATUS - BCA1 to CPU2 Interrupt Status */
/*! @{ */

#define CIU2_CIU2_BCA1_CPU2_INT_STATUS_ISR_MASK  (0xFFFFFFFFU)
#define CIU2_CIU2_BCA1_CPU2_INT_STATUS_ISR_SHIFT (0U)
/*! isr - BCA1 to CPU2 Interrupt Status
 */
#define CIU2_CIU2_BCA1_CPU2_INT_STATUS_ISR(x)    (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_BCA1_CPU2_INT_STATUS_ISR_SHIFT)) & CIU2_CIU2_BCA1_CPU2_INT_STATUS_ISR_MASK)
/*! @} */

/*! @name CIU2_APU_BYPASS1 - CIU2 APU Bypass Register 1 */
/*! @{ */

#define CIU2_CIU2_APU_BYPASS1_BRF_CLK_EN_BYPASS_EN_MASK (0x1U)
#define CIU2_CIU2_APU_BYPASS1_BRF_CLK_EN_BYPASS_EN_SHIFT (0U)
/*! brf_clk_en_bypass_en - Firmware Bypass BRF_Clk_En
 */
#define CIU2_CIU2_APU_BYPASS1_BRF_CLK_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_APU_BYPASS1_BRF_CLK_EN_BYPASS_EN_SHIFT)) & CIU2_CIU2_APU_BYPASS1_BRF_CLK_EN_BYPASS_EN_MASK)

#define CIU2_CIU2_APU_BYPASS1_BRF_CLK_EN_BYPASS_VAL_MASK (0x2U)
#define CIU2_CIU2_APU_BYPASS1_BRF_CLK_EN_BYPASS_VAL_SHIFT (1U)
/*! brf_clk_en_bypass_val - Firmware Bypass Value for BRF_Clk_En (active high signal)
 */
#define CIU2_CIU2_APU_BYPASS1_BRF_CLK_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_APU_BYPASS1_BRF_CLK_EN_BYPASS_VAL_SHIFT)) & CIU2_CIU2_APU_BYPASS1_BRF_CLK_EN_BYPASS_VAL_MASK)

#define CIU2_CIU2_APU_BYPASS1_BT_AES_CLK_EN_BYPASS_EN_MASK (0x4U)
#define CIU2_CIU2_APU_BYPASS1_BT_AES_CLK_EN_BYPASS_EN_SHIFT (2U)
/*! bt_aes_clk_en_bypass_en - Firmware Bypass for Btu_Aes_Clk
 */
#define CIU2_CIU2_APU_BYPASS1_BT_AES_CLK_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_APU_BYPASS1_BT_AES_CLK_EN_BYPASS_EN_SHIFT)) & CIU2_CIU2_APU_BYPASS1_BT_AES_CLK_EN_BYPASS_EN_MASK)

#define CIU2_CIU2_APU_BYPASS1_BT_AES_CLK_EN_BYPASS_VAL_MASK (0x8U)
#define CIU2_CIU2_APU_BYPASS1_BT_AES_CLK_EN_BYPASS_VAL_SHIFT (3U)
/*! bt_aes_clk_en_bypass_val - Firmware Bypass Value for Btu_Aes_Clk
 */
#define CIU2_CIU2_APU_BYPASS1_BT_AES_CLK_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_APU_BYPASS1_BT_AES_CLK_EN_BYPASS_VAL_SHIFT)) & CIU2_CIU2_APU_BYPASS1_BT_AES_CLK_EN_BYPASS_VAL_MASK)

#define CIU2_CIU2_APU_BYPASS1_SOC_CLK_EN2_T1_BYPASS_EN_MASK (0x10U)
#define CIU2_CIU2_APU_BYPASS1_SOC_CLK_EN2_T1_BYPASS_EN_SHIFT (4U)
/*! soc_clk_en2_T1_bypass_en - Firmware Bypass for SoC_Clk_En2
 */
#define CIU2_CIU2_APU_BYPASS1_SOC_CLK_EN2_T1_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_APU_BYPASS1_SOC_CLK_EN2_T1_BYPASS_EN_SHIFT)) & CIU2_CIU2_APU_BYPASS1_SOC_CLK_EN2_T1_BYPASS_EN_MASK)

#define CIU2_CIU2_APU_BYPASS1_SOC_CLK_EN2_T1_BYPASS_VAL_MASK (0x20U)
#define CIU2_CIU2_APU_BYPASS1_SOC_CLK_EN2_T1_BYPASS_VAL_SHIFT (5U)
/*! soc_clk_en2_T1_bypass_val - Firmware Bypass Value for SoC_Clk_En2(active high signal)
 */
#define CIU2_CIU2_APU_BYPASS1_SOC_CLK_EN2_T1_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_APU_BYPASS1_SOC_CLK_EN2_T1_BYPASS_VAL_SHIFT)) & CIU2_CIU2_APU_BYPASS1_SOC_CLK_EN2_T1_BYPASS_VAL_MASK)

#define CIU2_CIU2_APU_BYPASS1_TBG_BTU_CLK_EN_BYPASS_SEL_MASK (0xC0U)
#define CIU2_CIU2_APU_BYPASS1_TBG_BTU_CLK_EN_BYPASS_SEL_SHIFT (6U)
/*! tbg_btu_clk_en_bypass_sel - TBG512_320_176_BTU_Clk_En_Sel to TBG512_320_176 of CAU
 */
#define CIU2_CIU2_APU_BYPASS1_TBG_BTU_CLK_EN_BYPASS_SEL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_APU_BYPASS1_TBG_BTU_CLK_EN_BYPASS_SEL_SHIFT)) & CIU2_CIU2_APU_BYPASS1_TBG_BTU_CLK_EN_BYPASS_SEL_MASK)

#define CIU2_CIU2_APU_BYPASS1_BT_AES_CLK_SEL_BYPASS_EN_MASK (0x100U)
#define CIU2_CIU2_APU_BYPASS1_BT_AES_CLK_SEL_BYPASS_EN_SHIFT (8U)
/*! bt_aes_clk_sel_bypass_en - Firmware Bypass for Btu_Aes_Clk_Sel
 */
#define CIU2_CIU2_APU_BYPASS1_BT_AES_CLK_SEL_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_APU_BYPASS1_BT_AES_CLK_SEL_BYPASS_EN_SHIFT)) & CIU2_CIU2_APU_BYPASS1_BT_AES_CLK_SEL_BYPASS_EN_MASK)

#define CIU2_CIU2_APU_BYPASS1_BT_AES_CLK_SEL_BYPASS_VAL_MASK (0x200U)
#define CIU2_CIU2_APU_BYPASS1_BT_AES_CLK_SEL_BYPASS_VAL_SHIFT (9U)
/*! bt_aes_clk_sel_bypass_val - Firmware Bypass Value for Btu_Aes_Clk_Sel
 */
#define CIU2_CIU2_APU_BYPASS1_BT_AES_CLK_SEL_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_APU_BYPASS1_BT_AES_CLK_SEL_BYPASS_VAL_SHIFT)) & CIU2_CIU2_APU_BYPASS1_BT_AES_CLK_SEL_BYPASS_VAL_MASK)

#define CIU2_CIU2_APU_BYPASS1_TBG_BTU_CLK_EN_BYPASS_VAL_MASK (0x400U)
#define CIU2_CIU2_APU_BYPASS1_TBG_BTU_CLK_EN_BYPASS_VAL_SHIFT (10U)
/*! tbg_btu_clk_en_bypass_val - TBG512_320_176_BTU_Clk_En Bypass Value
 */
#define CIU2_CIU2_APU_BYPASS1_TBG_BTU_CLK_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_APU_BYPASS1_TBG_BTU_CLK_EN_BYPASS_VAL_SHIFT)) & CIU2_CIU2_APU_BYPASS1_TBG_BTU_CLK_EN_BYPASS_VAL_MASK)
/*! @} */

/*! @name CIU2_CPU2_LMU_STA_BYPASS0 - LMU static bank control byapss0 Register for CPU2 mem */
/*! @{ */

#define CIU2_CIU2_CPU2_LMU_STA_BYPASS0_LMU_STA_BANKS_ISO_EN_BP_EN_MASK (0xFFU)
#define CIU2_CIU2_CPU2_LMU_STA_BYPASS0_LMU_STA_BANKS_ISO_EN_BP_EN_SHIFT (0U)
/*! lmu_sta_banks_iso_en_bp_en - Firmware Bypass enable for lmu static banks iso_en
 */
#define CIU2_CIU2_CPU2_LMU_STA_BYPASS0_LMU_STA_BANKS_ISO_EN_BP_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_LMU_STA_BYPASS0_LMU_STA_BANKS_ISO_EN_BP_EN_SHIFT)) & CIU2_CIU2_CPU2_LMU_STA_BYPASS0_LMU_STA_BANKS_ISO_EN_BP_EN_MASK)

#define CIU2_CIU2_CPU2_LMU_STA_BYPASS0_LMU_STA_BANKS_ISO_EN_BP_VAL_MASK (0xFF00U)
#define CIU2_CIU2_CPU2_LMU_STA_BYPASS0_LMU_STA_BANKS_ISO_EN_BP_VAL_SHIFT (8U)
/*! lmu_sta_banks_iso_en_bp_val - Firmware Bypass value for lmu static banks iso_en
 */
#define CIU2_CIU2_CPU2_LMU_STA_BYPASS0_LMU_STA_BANKS_ISO_EN_BP_VAL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_LMU_STA_BYPASS0_LMU_STA_BANKS_ISO_EN_BP_VAL_SHIFT)) & CIU2_CIU2_CPU2_LMU_STA_BYPASS0_LMU_STA_BANKS_ISO_EN_BP_VAL_MASK)

#define CIU2_CIU2_CPU2_LMU_STA_BYPASS0_LMU_STA_BANKS_PSW_EN_BP_EN_MASK (0xFF0000U)
#define CIU2_CIU2_CPU2_LMU_STA_BYPASS0_LMU_STA_BANKS_PSW_EN_BP_EN_SHIFT (16U)
/*! lmu_sta_banks_psw_en_bp_en - Firmware Bypass enable for lmu static banks psw_en
 */
#define CIU2_CIU2_CPU2_LMU_STA_BYPASS0_LMU_STA_BANKS_PSW_EN_BP_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_LMU_STA_BYPASS0_LMU_STA_BANKS_PSW_EN_BP_EN_SHIFT)) & CIU2_CIU2_CPU2_LMU_STA_BYPASS0_LMU_STA_BANKS_PSW_EN_BP_EN_MASK)

#define CIU2_CIU2_CPU2_LMU_STA_BYPASS0_LMU_STA_BANKS_PSW_EN_BP_VAL_MASK (0xFF000000U)
#define CIU2_CIU2_CPU2_LMU_STA_BYPASS0_LMU_STA_BANKS_PSW_EN_BP_VAL_SHIFT (24U)
/*! lmu_sta_banks_psw_en_bp_val - Firmware Bypass value for lmu static banks psw_en
 */
#define CIU2_CIU2_CPU2_LMU_STA_BYPASS0_LMU_STA_BANKS_PSW_EN_BP_VAL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_LMU_STA_BYPASS0_LMU_STA_BANKS_PSW_EN_BP_VAL_SHIFT)) & CIU2_CIU2_CPU2_LMU_STA_BYPASS0_LMU_STA_BANKS_PSW_EN_BP_VAL_MASK)
/*! @} */

/*! @name CIU2_CPU2_LMU_STA_BYPASS1 - LMU static bank control byapss1 Register for CPU2 */
/*! @{ */

#define CIU2_CIU2_CPU2_LMU_STA_BYPASS1_LMU_STA_BANKS_SRAM_PD_BP_EN_MASK (0xFFU)
#define CIU2_CIU2_CPU2_LMU_STA_BYPASS1_LMU_STA_BANKS_SRAM_PD_BP_EN_SHIFT (0U)
/*! lmu_sta_banks_sram_pd_bp_en - Firmware Bypass enable for lmu static banks sram_pd
 */
#define CIU2_CIU2_CPU2_LMU_STA_BYPASS1_LMU_STA_BANKS_SRAM_PD_BP_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_LMU_STA_BYPASS1_LMU_STA_BANKS_SRAM_PD_BP_EN_SHIFT)) & CIU2_CIU2_CPU2_LMU_STA_BYPASS1_LMU_STA_BANKS_SRAM_PD_BP_EN_MASK)

#define CIU2_CIU2_CPU2_LMU_STA_BYPASS1_LMU_STA_BANKS_SRAM_PD_BP_VAL_MASK (0xFF00U)
#define CIU2_CIU2_CPU2_LMU_STA_BYPASS1_LMU_STA_BANKS_SRAM_PD_BP_VAL_SHIFT (8U)
/*! lmu_sta_banks_sram_pd_bp_val - Firmware Bypass value for lmu static banks sram_pd
 */
#define CIU2_CIU2_CPU2_LMU_STA_BYPASS1_LMU_STA_BANKS_SRAM_PD_BP_VAL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_LMU_STA_BYPASS1_LMU_STA_BANKS_SRAM_PD_BP_VAL_SHIFT)) & CIU2_CIU2_CPU2_LMU_STA_BYPASS1_LMU_STA_BANKS_SRAM_PD_BP_VAL_MASK)

#define CIU2_CIU2_CPU2_LMU_STA_BYPASS1_LMU_STA_BANKS_FNRST_BP_EN_MASK (0xFF0000U)
#define CIU2_CIU2_CPU2_LMU_STA_BYPASS1_LMU_STA_BANKS_FNRST_BP_EN_SHIFT (16U)
/*! lmu_sta_banks_fnrst_bp_en - Firmware Bypass enable for lmu static banks fnrst
 */
#define CIU2_CIU2_CPU2_LMU_STA_BYPASS1_LMU_STA_BANKS_FNRST_BP_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_LMU_STA_BYPASS1_LMU_STA_BANKS_FNRST_BP_EN_SHIFT)) & CIU2_CIU2_CPU2_LMU_STA_BYPASS1_LMU_STA_BANKS_FNRST_BP_EN_MASK)

#define CIU2_CIU2_CPU2_LMU_STA_BYPASS1_LMU_STA_BANKS_FNRST_BP_VAL_MASK (0xFF000000U)
#define CIU2_CIU2_CPU2_LMU_STA_BYPASS1_LMU_STA_BANKS_FNRST_BP_VAL_SHIFT (24U)
/*! lmu_sta_banks_fnrst_bp_val - Firmware Bypass value for lmu static banks fnrst
 */
#define CIU2_CIU2_CPU2_LMU_STA_BYPASS1_LMU_STA_BANKS_FNRST_BP_VAL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_LMU_STA_BYPASS1_LMU_STA_BANKS_FNRST_BP_VAL_SHIFT)) & CIU2_CIU2_CPU2_LMU_STA_BYPASS1_LMU_STA_BANKS_FNRST_BP_VAL_MASK)
/*! @} */

/*! @name CIU2_CPU2_LMU_STA_BYPASS2 - LMU static bank byapss2 Register for CPU2 */
/*! @{ */

#define CIU2_CIU2_CPU2_LMU_STA_BYPASS2_LMU_STA_BANKS_VDDMC_SW_PD_CTRL_BP_EN_MASK (0xFFU)
#define CIU2_CIU2_CPU2_LMU_STA_BYPASS2_LMU_STA_BANKS_VDDMC_SW_PD_CTRL_BP_EN_SHIFT (0U)
/*! lmu_sta_banks_vddmc_sw_pd_ctrl_bp_en - Firmware Bypass enable for lmu static banks vddmc_sw_pd_ctrl
 */
#define CIU2_CIU2_CPU2_LMU_STA_BYPASS2_LMU_STA_BANKS_VDDMC_SW_PD_CTRL_BP_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_LMU_STA_BYPASS2_LMU_STA_BANKS_VDDMC_SW_PD_CTRL_BP_EN_SHIFT)) & CIU2_CIU2_CPU2_LMU_STA_BYPASS2_LMU_STA_BANKS_VDDMC_SW_PD_CTRL_BP_EN_MASK)

#define CIU2_CIU2_CPU2_LMU_STA_BYPASS2_LMU_STA_BANKS_VDDMC_SW_PD_CTRL_BP_VAL_MASK (0xFF00U)
#define CIU2_CIU2_CPU2_LMU_STA_BYPASS2_LMU_STA_BANKS_VDDMC_SW_PD_CTRL_BP_VAL_SHIFT (8U)
/*! lmu_sta_banks_vddmc_sw_pd_ctrl_bp_val - Firmware Bypass value for lmu static banks vddmc_sw_pd_ctrl
 */
#define CIU2_CIU2_CPU2_LMU_STA_BYPASS2_LMU_STA_BANKS_VDDMC_SW_PD_CTRL_BP_VAL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_LMU_STA_BYPASS2_LMU_STA_BANKS_VDDMC_SW_PD_CTRL_BP_VAL_SHIFT)) & CIU2_CIU2_CPU2_LMU_STA_BYPASS2_LMU_STA_BANKS_VDDMC_SW_PD_CTRL_BP_VAL_MASK)
/*! @} */

/*! @name CIU2_CPU2_LMU_G2BIST_CTRL_BYPASS - LMU G2Bist control byapss Register for CPU2 */
/*! @{ */

#define CIU2_CIU2_CPU2_LMU_G2BIST_CTRL_BYPASS_LMU_CPU2_STA_PWRDMN_RPR_REQ_BP_EN_MASK (0x1U)
#define CIU2_CIU2_CPU2_LMU_G2BIST_CTRL_BYPASS_LMU_CPU2_STA_PWRDMN_RPR_REQ_BP_EN_SHIFT (0U)
/*! lmu_cpu2_sta_pwrdmn_rpr_req_bp_en - Firmware Bypass enable for CPU2 static banks lmu powerdomain repair request
 */
#define CIU2_CIU2_CPU2_LMU_G2BIST_CTRL_BYPASS_LMU_CPU2_STA_PWRDMN_RPR_REQ_BP_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_LMU_G2BIST_CTRL_BYPASS_LMU_CPU2_STA_PWRDMN_RPR_REQ_BP_EN_SHIFT)) & CIU2_CIU2_CPU2_LMU_G2BIST_CTRL_BYPASS_LMU_CPU2_STA_PWRDMN_RPR_REQ_BP_EN_MASK)

#define CIU2_CIU2_CPU2_LMU_G2BIST_CTRL_BYPASS_LMU_CPU2_STA_PWRDMN_RPR_REQ_BP_VAL_MASK (0xFEU)
#define CIU2_CIU2_CPU2_LMU_G2BIST_CTRL_BYPASS_LMU_CPU2_STA_PWRDMN_RPR_REQ_BP_VAL_SHIFT (1U)
/*! lmu_cpu2_sta_pwrdmn_rpr_req_bp_val - Firmware Bypass value for CPU2 static banks lmu powerdomain repair request
 */
#define CIU2_CIU2_CPU2_LMU_G2BIST_CTRL_BYPASS_LMU_CPU2_STA_PWRDMN_RPR_REQ_BP_VAL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU2_LMU_G2BIST_CTRL_BYPASS_LMU_CPU2_STA_PWRDMN_RPR_REQ_BP_VAL_SHIFT)) & CIU2_CIU2_CPU2_LMU_G2BIST_CTRL_BYPASS_LMU_CPU2_STA_PWRDMN_RPR_REQ_BP_VAL_MASK)
/*! @} */

/*! @name CIU2_APU_PWR_CTRL_BYPASS1 - APU power control Bypass Register 1 */
/*! @{ */

#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_PSW_BYPASS_VAL_MASK (0x1U)
#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_PSW_BYPASS_VAL_SHIFT (0U)
/*! brf_psw_bypass_val - brf Power Switch Control
 */
#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_PSW_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_PSW_BYPASS_VAL_SHIFT)) & CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_PSW_BYPASS_VAL_MASK)

#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_PSW_BYPASS_EN_MASK (0x2U)
#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_PSW_BYPASS_EN_SHIFT (1U)
/*! brf_psw_bypass_en - brf Power Switch Control Enable
 */
#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_PSW_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_PSW_BYPASS_EN_SHIFT)) & CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_PSW_BYPASS_EN_MASK)

#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_FWBAR_BYPASS_VAL_MASK (0x4U)
#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_FWBAR_BYPASS_VAL_SHIFT (2U)
/*! brf_fwbar_bypass_val - brf Firewallbar Control
 */
#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_FWBAR_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_FWBAR_BYPASS_VAL_SHIFT)) & CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_FWBAR_BYPASS_VAL_MASK)

#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_FWBAR_BYPASS_EN_MASK (0x8U)
#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_FWBAR_BYPASS_EN_SHIFT (3U)
/*! brf_fwbar_bypass_en - brf Firewallbar Control Enable
 */
#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_FWBAR_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_FWBAR_BYPASS_EN_SHIFT)) & CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_FWBAR_BYPASS_EN_MASK)

#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_ISO_EN_BYPASS_VAL_MASK (0x10U)
#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_ISO_EN_BYPASS_VAL_SHIFT (4U)
/*! brf_iso_en_bypass_val - brf Isolation Cell Control
 */
#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_ISO_EN_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_ISO_EN_BYPASS_VAL_SHIFT)) & CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_ISO_EN_BYPASS_VAL_MASK)

#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_ISO_EN_BYPASS_EN_MASK (0x20U)
#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_ISO_EN_BYPASS_EN_SHIFT (5U)
/*! brf_iso_en_bypass_en - brf Isolation Cell Control Enable
 */
#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_ISO_EN_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_ISO_EN_BYPASS_EN_SHIFT)) & CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_ISO_EN_BYPASS_EN_MASK)

#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_CLK_DIV_RSTB_BYPASS_VAL_MASK (0x40U)
#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_CLK_DIV_RSTB_BYPASS_VAL_SHIFT (6U)
/*! brf_clk_div_rstb_bypass_val - Firmware Bypass Value for brf Clk_Div_Rstb (active low signal)
 */
#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_CLK_DIV_RSTB_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_CLK_DIV_RSTB_BYPASS_VAL_SHIFT)) & CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_CLK_DIV_RSTB_BYPASS_VAL_MASK)

#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_CLK_DIV_RSTB_BYPASS_EN_MASK (0x80U)
#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_CLK_DIV_RSTB_BYPASS_EN_SHIFT (7U)
/*! brf_clk_div_rstb_bypass_en - Firmware Bypass brf Clk_Div_Rstb from APU
 */
#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_CLK_DIV_RSTB_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_CLK_DIV_RSTB_BYPASS_EN_SHIFT)) & CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_CLK_DIV_RSTB_BYPASS_EN_MASK)

#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_SRAM_PD_BYPASS_VAL_MASK (0x100U)
#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_SRAM_PD_BYPASS_VAL_SHIFT (8U)
/*! brf_sram_pd_bypass_val - Firmware Bypass Value for SRAM_PD (active high signal)
 */
#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_SRAM_PD_BYPASS_VAL(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_SRAM_PD_BYPASS_VAL_SHIFT)) & CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_SRAM_PD_BYPASS_VAL_MASK)

#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_SRAM_PD_BYPASS_EN_MASK (0x200U)
#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_SRAM_PD_BYPASS_EN_SHIFT (9U)
/*! brf_sram_pd_bypass_en - Firmware Bypass SRAM_PD from APU
 */
#define CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_SRAM_PD_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_SRAM_PD_BYPASS_EN_SHIFT)) & CIU2_CIU2_APU_PWR_CTRL_BYPASS1_BRF_SRAM_PD_BYPASS_EN_MASK)
/*! @} */

/*! @name CIU2_AHB2AHB_BRIDGE_CTRL - AHB2AHB Bridge Control Register */
/*! @{ */

#define CIU2_CIU2_AHB2AHB_BRIDGE_CTRL_PREFETCH_HSEL_EN_MASK (0x1U)
#define CIU2_CIU2_AHB2AHB_BRIDGE_CTRL_PREFETCH_HSEL_EN_SHIFT (0U)
/*! prefetch_hsel_en - ahb2ahb bridge pre-fetch hsel enable
 */
#define CIU2_CIU2_AHB2AHB_BRIDGE_CTRL_PREFETCH_HSEL_EN(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_AHB2AHB_BRIDGE_CTRL_PREFETCH_HSEL_EN_SHIFT)) & CIU2_CIU2_AHB2AHB_BRIDGE_CTRL_PREFETCH_HSEL_EN_MASK)
/*! @} */

/*! @name CIU2_AHB1_AHB2_TO_CLEAR - AHB1 AHB2 timeout logic clear register */
/*! @{ */

#define CIU2_CIU2_AHB1_AHB2_TO_CLEAR_AHB2_TIMEOUT_CLEAR_MASK (0x100U)
#define CIU2_CIU2_AHB1_AHB2_TO_CLEAR_AHB2_TIMEOUT_CLEAR_SHIFT (8U)
/*! ahb2_timeout_clear - After the timeout happended on AHB2 bus, the cpu will read the ERR ISR and
 *    read the bus state which cause the timeout and then set this bit to 1 to clear the AHB2
 *    timeout logic to start recroding next transaction. This is self clearing bit
 */
#define CIU2_CIU2_AHB1_AHB2_TO_CLEAR_AHB2_TIMEOUT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_AHB1_AHB2_TO_CLEAR_AHB2_TIMEOUT_CLEAR_SHIFT)) & CIU2_CIU2_AHB1_AHB2_TO_CLEAR_AHB2_TIMEOUT_CLEAR_MASK)

#define CIU2_CIU2_AHB1_AHB2_TO_CLEAR_CPU2_DCODE_INV_ADDR_CLR_MASK (0x200U)
#define CIU2_CIU2_AHB1_AHB2_TO_CLEAR_CPU2_DCODE_INV_ADDR_CLR_SHIFT (9U)
/*! cpu2_dcode_inv_addr_clr - After the invalid address int happended on CPU2 dcode bus, the cpu2
 *    will read the ERR ISR and read the bus state which cause the timeout and then set this bit to 1
 *    to clear the CPU2 Dcode invalid addr logic to start recroding next transaction. This is self
 *    clearing bit
 */
#define CIU2_CIU2_AHB1_AHB2_TO_CLEAR_CPU2_DCODE_INV_ADDR_CLR(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_AHB1_AHB2_TO_CLEAR_CPU2_DCODE_INV_ADDR_CLR_SHIFT)) & CIU2_CIU2_AHB1_AHB2_TO_CLEAR_CPU2_DCODE_INV_ADDR_CLR_MASK)

#define CIU2_CIU2_AHB1_AHB2_TO_CLEAR_CPU2_ICODE_INV_ADDR_CLR_MASK (0x400U)
#define CIU2_CIU2_AHB1_AHB2_TO_CLEAR_CPU2_ICODE_INV_ADDR_CLR_SHIFT (10U)
/*! cpu2_icode_inv_addr_clr - After the invalid address int happended on CPU2 icode bus, the cpu2
 *    will read the ERR ISR and read the bus state which cause the timeout and then set this bit to 1
 *    to clear the CPU2 Icode invalid addr logic to start recroding next transaction. This is self
 *    clearing bit
 */
#define CIU2_CIU2_AHB1_AHB2_TO_CLEAR_CPU2_ICODE_INV_ADDR_CLR(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_AHB1_AHB2_TO_CLEAR_CPU2_ICODE_INV_ADDR_CLR_SHIFT)) & CIU2_CIU2_AHB1_AHB2_TO_CLEAR_CPU2_ICODE_INV_ADDR_CLR_MASK)
/*! @} */

/*! @name CIU2_CPU_CPU2_DBG_STAT - CPU2 debug register */
/*! @{ */

#define CIU2_CIU2_CPU_CPU2_DBG_STAT_CPU2_RO_STATUS_MASK (0xFFFFFFFFU)
#define CIU2_CIU2_CPU_CPU2_DBG_STAT_CPU2_RO_STATUS_SHIFT (0U)
/*! cpu2_ro_status - cpu2 debug output
 */
#define CIU2_CIU2_CPU_CPU2_DBG_STAT_CPU2_RO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU_CPU2_DBG_STAT_CPU2_RO_STATUS_SHIFT)) & CIU2_CIU2_CPU_CPU2_DBG_STAT_CPU2_RO_STATUS_MASK)
/*! @} */

/*! @name CIU2_CPU_CPU1_CTRL - CPU1 control register */
/*! @{ */

#define CIU2_CIU2_CPU_CPU1_CTRL_CPU1_JTAG_CHAIN_BYPASS_MASK (0x20000U)
#define CIU2_CIU2_CPU_CPU1_CTRL_CPU1_JTAG_CHAIN_BYPASS_SHIFT (17U)
#define CIU2_CIU2_CPU_CPU1_CTRL_CPU1_JTAG_CHAIN_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU_CPU1_CTRL_CPU1_JTAG_CHAIN_BYPASS_SHIFT)) & CIU2_CIU2_CPU_CPU1_CTRL_CPU1_JTAG_CHAIN_BYPASS_MASK)

#define CIU2_CIU2_CPU_CPU1_CTRL_CPU1_CPU2_MSG_SCHEME_MASK (0x40000U)
#define CIU2_CIU2_CPU_CPU1_CTRL_CPU1_CPU2_MSG_SCHEME_SHIFT (18U)
#define CIU2_CIU2_CPU_CPU1_CTRL_CPU1_CPU2_MSG_SCHEME(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU_CPU1_CTRL_CPU1_CPU2_MSG_SCHEME_SHIFT)) & CIU2_CIU2_CPU_CPU1_CTRL_CPU1_CPU2_MSG_SCHEME_MASK)

#define CIU2_CIU2_CPU_CPU1_CTRL_CPU2_RESET_INT_MASK (0x80000000U)
#define CIU2_CIU2_CPU_CPU1_CTRL_CPU2_RESET_INT_SHIFT (31U)
/*! cpu2_reset_int - cpu1 fw reset cpu2
 */
#define CIU2_CIU2_CPU_CPU1_CTRL_CPU2_RESET_INT(x) (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_CPU_CPU1_CTRL_CPU2_RESET_INT_SHIFT)) & CIU2_CIU2_CPU_CPU1_CTRL_CPU2_RESET_INT_MASK)
/*! @} */

/*! @name CIU2_TESTBUS_CTRL - CPU2 debug register */
/*! @{ */

#define CIU2_CIU2_TESTBUS_CTRL_TESTBUS_SEL_MASK  (0xFU)
#define CIU2_CIU2_TESTBUS_CTRL_TESTBUS_SEL_SHIFT (0U)
/*! testbus_sel - Select testbus debug output
 */
#define CIU2_CIU2_TESTBUS_CTRL_TESTBUS_SEL(x)    (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_TESTBUS_CTRL_TESTBUS_SEL_SHIFT)) & CIU2_CIU2_TESTBUS_CTRL_TESTBUS_SEL_MASK)
/*! @} */

/*! @name CIU2_LBC_CTRL - LBC Control and Status */
/*! @{ */

#define CIU2_CIU2_LBC_CTRL_LBC_NCO_EN_MASK       (0x1U)
#define CIU2_CIU2_LBC_CTRL_LBC_NCO_EN_SHIFT      (0U)
/*! lbc_nco_en - LBC NCO Enable Signal
 */
#define CIU2_CIU2_LBC_CTRL_LBC_NCO_EN(x)         (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_LBC_CTRL_LBC_NCO_EN_SHIFT)) & CIU2_CIU2_LBC_CTRL_LBC_NCO_EN_MASK)

#define CIU2_CIU2_LBC_CTRL_LBC_DEBUG_CTRL_MASK   (0x60U)
#define CIU2_CIU2_LBC_CTRL_LBC_DEBUG_CTRL_SHIFT  (5U)
/*! lbc_debug_ctrl - LBC Debug Control Signal
 */
#define CIU2_CIU2_LBC_CTRL_LBC_DEBUG_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_LBC_CTRL_LBC_DEBUG_CTRL_SHIFT)) & CIU2_CIU2_LBC_CTRL_LBC_DEBUG_CTRL_MASK)

#define CIU2_CIU2_LBC_CTRL_DEJIT_EN_MASK         (0x10000U)
#define CIU2_CIU2_LBC_CTRL_DEJIT_EN_SHIFT        (16U)
/*! dejit_en - De-jitter Enable
 */
#define CIU2_CIU2_LBC_CTRL_DEJIT_EN(x)           (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_LBC_CTRL_DEJIT_EN_SHIFT)) & CIU2_CIU2_LBC_CTRL_DEJIT_EN_MASK)

#define CIU2_CIU2_LBC_CTRL_AUTO_DEJIT_MASK       (0x20000U)
#define CIU2_CIU2_LBC_CTRL_AUTO_DEJIT_SHIFT      (17U)
/*! auto_dejit - Auto de-jitter
 */
#define CIU2_CIU2_LBC_CTRL_AUTO_DEJIT(x)         (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_LBC_CTRL_AUTO_DEJIT_SHIFT)) & CIU2_CIU2_LBC_CTRL_AUTO_DEJIT_MASK)

#define CIU2_CIU2_LBC_CTRL_MAN_SEL_NCO_MASK      (0x40000U)
#define CIU2_CIU2_LBC_CTRL_MAN_SEL_NCO_SHIFT     (18U)
/*! man_sel_nco - Manual select NCO
 */
#define CIU2_CIU2_LBC_CTRL_MAN_SEL_NCO(x)        (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_LBC_CTRL_MAN_SEL_NCO_SHIFT)) & CIU2_CIU2_LBC_CTRL_MAN_SEL_NCO_MASK)

#define CIU2_CIU2_LBC_CTRL_NCO_LPO_RAMP_DN_MASK  (0x800000U)
#define CIU2_CIU2_LBC_CTRL_NCO_LPO_RAMP_DN_SHIFT (23U)
/*! nco_lpo_ramp_dn - Status nco_lpo_ramp_dn
 */
#define CIU2_CIU2_LBC_CTRL_NCO_LPO_RAMP_DN(x)    (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_LBC_CTRL_NCO_LPO_RAMP_DN_SHIFT)) & CIU2_CIU2_LBC_CTRL_NCO_LPO_RAMP_DN_MASK)

#define CIU2_CIU2_LBC_CTRL_REF_LPO_CLK_GOOD_MASK (0x1000000U)
#define CIU2_CIU2_LBC_CTRL_REF_LPO_CLK_GOOD_SHIFT (24U)
/*! ref_lpo_clk_good - Status ref_lpo_clk_good
 */
#define CIU2_CIU2_LBC_CTRL_REF_LPO_CLK_GOOD(x)   (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_LBC_CTRL_REF_LPO_CLK_GOOD_SHIFT)) & CIU2_CIU2_LBC_CTRL_REF_LPO_CLK_GOOD_MASK)

#define CIU2_CIU2_LBC_CTRL_REF_LPO_RAMP_DN_MASK  (0x2000000U)
#define CIU2_CIU2_LBC_CTRL_REF_LPO_RAMP_DN_SHIFT (25U)
/*! ref_lpo_ramp_dn - Status ref_lpo_ramp_dn
 */
#define CIU2_CIU2_LBC_CTRL_REF_LPO_RAMP_DN(x)    (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_LBC_CTRL_REF_LPO_RAMP_DN_SHIFT)) & CIU2_CIU2_LBC_CTRL_REF_LPO_RAMP_DN_MASK)

#define CIU2_CIU2_LBC_CTRL_LPO_CLK_SEL_FSM_MASK  (0x4000000U)
#define CIU2_CIU2_LBC_CTRL_LPO_CLK_SEL_FSM_SHIFT (26U)
/*! lpo_clk_sel_fsm - Status lpo_clk_sel_fsm
 */
#define CIU2_CIU2_LBC_CTRL_LPO_CLK_SEL_FSM(x)    (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_LBC_CTRL_LPO_CLK_SEL_FSM_SHIFT)) & CIU2_CIU2_LBC_CTRL_LPO_CLK_SEL_FSM_MASK)

#define CIU2_CIU2_LBC_CTRL_LPO_CLK_3K2_CNT_MASK  (0xF8000000U)
#define CIU2_CIU2_LBC_CTRL_LPO_CLK_3K2_CNT_SHIFT (27U)
/*! lpo_clk_3k2_cnt - Status lpo_clk_3k2_cnt, 3.2KHz Count
 */
#define CIU2_CIU2_LBC_CTRL_LPO_CLK_3K2_CNT(x)    (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_LBC_CTRL_LPO_CLK_3K2_CNT_SHIFT)) & CIU2_CIU2_LBC_CTRL_LPO_CLK_3K2_CNT_MASK)
/*! @} */

/*! @name CIU2_LBC_SLPCLK_NCO - LBC NCO Step for Sleep Clock */
/*! @{ */

#define CIU2_CIU2_LBC_SLPCLK_NCO_STEP_MASK       (0xFFFFFFFFU)
#define CIU2_CIU2_LBC_SLPCLK_NCO_STEP_SHIFT      (0U)
/*! step - LBC NCO step for sleep clock. Please refer to design spreadsheet for more details.
 */
#define CIU2_CIU2_LBC_SLPCLK_NCO_STEP(x)         (((uint32_t)(((uint32_t)(x)) << CIU2_CIU2_LBC_SLPCLK_NCO_STEP_SHIFT)) & CIU2_CIU2_LBC_SLPCLK_NCO_STEP_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group CIU2_Register_Masks */


/* CIU2 - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral CIU2 base address */
  #define CIU2_BASE                                (0x58948000u)
  /** Peripheral CIU2 base address */
  #define CIU2_BASE_NS                             (0x48948000u)
  /** Peripheral CIU2 base pointer */
  #define CIU2                                     ((CIU2_Type *)CIU2_BASE)
  /** Peripheral CIU2 base pointer */
  #define CIU2_NS                                  ((CIU2_Type *)CIU2_BASE_NS)
  /** Array initializer of CIU2 peripheral base addresses */
  #define CIU2_BASE_ADDRS                          { CIU2_BASE }
  /** Array initializer of CIU2 peripheral base pointers */
  #define CIU2_BASE_PTRS                           { CIU2 }
  /** Array initializer of CIU2 peripheral base addresses */
  #define CIU2_BASE_ADDRS_NS                       { CIU2_BASE_NS }
  /** Array initializer of CIU2 peripheral base pointers */
  #define CIU2_BASE_PTRS_NS                        { CIU2_NS }
#else
  /** Peripheral CIU2 base address */
  #define CIU2_BASE                                (0x48948000u)
  /** Peripheral CIU2 base pointer */
  #define CIU2                                     ((CIU2_Type *)CIU2_BASE)
  /** Array initializer of CIU2 peripheral base addresses */
  #define CIU2_BASE_ADDRS                          { CIU2_BASE }
  /** Array initializer of CIU2 peripheral base pointers */
  #define CIU2_BASE_PTRS                           { CIU2 }
#endif

/*!
 * @}
 */ /* end of group CIU2_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CMC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CMC_Peripheral_Access_Layer CMC Peripheral Access Layer
 * @{
 */

/** CMC - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
       uint8_t RESERVED_0[12];
  __IO uint32_t CKCTRL;                            /**< Clock Control Register, offset: 0x10 */
  __IO uint32_t CKSTAT;                            /**< Clock Status Register, offset: 0x14 */
  __IO uint32_t PMPROT;                            /**< Power Mode Protection Register, offset: 0x18 */
  __O  uint32_t GPMCTRL;                           /**< Global Power Mode Control Register, offset: 0x1C */
  __IO uint32_t PMCTRL[2];                         /**< Power Mode Control Register, array offset: 0x20, array step: 0x4 */
       uint8_t RESERVED_1[88];
  __I  uint32_t SRS;                               /**< System Reset Status Register, offset: 0x80 */
  __IO uint32_t RPC;                               /**< Reset Pin Control Register, offset: 0x84 */
  __IO uint32_t SSRS;                              /**< Sticky System Reset Status Register, offset: 0x88 */
  __IO uint32_t SRIE;                              /**< System Reset Interrupt Enable Register, offset: 0x8C */
  __IO uint32_t SRIF;                              /**< System Reset Interrupt Flag Register, offset: 0x90 */
       uint8_t RESERVED_2[8];
  __I  uint32_t RSTCNT;                            /**< Reset Count Register, offset: 0x9C */
  __IO uint32_t MR[1];                             /**< Mode Register, array offset: 0xA0, array step: 0x4 */
       uint8_t RESERVED_3[12];
  __IO uint32_t FM[1];                             /**< Force Mode Register, array offset: 0xB0, array step: 0x4 */
       uint8_t RESERVED_4[12];
  __IO uint32_t SRAMDIS[1];                        /**< SRAM Disable Register, array offset: 0xC0, array step: 0x4 */
       uint8_t RESERVED_5[12];
  __IO uint32_t SRAMRET[1];                        /**< SRAM Retention Register, array offset: 0xD0, array step: 0x4 */
       uint8_t RESERVED_6[12];
  __IO uint32_t FLASHCR;                           /**< Flash Control Register, offset: 0xE0 */
       uint8_t RESERVED_7[28];
  __IO uint32_t BSR;                               /**< BootROM Status Register, offset: 0x100 */
       uint8_t RESERVED_8[8];
  __IO uint32_t BLR;                               /**< BootROM Lock Register, offset: 0x10C */
  __IO uint32_t CORECTL;                           /**< Core Control Register, offset: 0x110 */
       uint8_t RESERVED_9[12];
  __IO uint32_t DBGCTL;                            /**< Debug Control Register, offset: 0x120 */
} CMC_Type;

/* ----------------------------------------------------------------------------
   -- CMC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CMC_Register_Masks CMC Register Masks
 * @{
 */

/*! @name VERID - Version ID Register */
/*! @{ */

#define CMC_VERID_FEATURE_MASK                   (0xFFFFU)
#define CMC_VERID_FEATURE_SHIFT                  (0U)
/*! FEATURE - Feature Specification Number
 */
#define CMC_VERID_FEATURE(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_VERID_FEATURE_SHIFT)) & CMC_VERID_FEATURE_MASK)

#define CMC_VERID_MINOR_MASK                     (0xFF0000U)
#define CMC_VERID_MINOR_SHIFT                    (16U)
/*! MINOR - Minor Version Number
 */
#define CMC_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_VERID_MINOR_SHIFT)) & CMC_VERID_MINOR_MASK)

#define CMC_VERID_MAJOR_MASK                     (0xFF000000U)
#define CMC_VERID_MAJOR_SHIFT                    (24U)
/*! MAJOR - Major Version Number
 */
#define CMC_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_VERID_MAJOR_SHIFT)) & CMC_VERID_MAJOR_MASK)
/*! @} */

/*! @name CKCTRL - Clock Control Register */
/*! @{ */

#define CMC_CKCTRL_CKMODE_MASK                   (0xFU)
#define CMC_CKCTRL_CKMODE_SHIFT                  (0U)
/*! CKMODE - Clocking Mode
 *  0b0000..No clock gating.
 *  0b0001..Core clock is gated.
 *  0b0011..Core and platform clocks are gated.
 *  0b0111..Core, platform, and peripheral clocks are gated, but no change in low power mode.
 *  0b1111..Core, platform, and peripheral clocks are gated, and core enters low power mode.
 */
#define CMC_CKCTRL_CKMODE(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_CKCTRL_CKMODE_SHIFT)) & CMC_CKCTRL_CKMODE_MASK)

#define CMC_CKCTRL_LOCK_MASK                     (0x80000000U)
#define CMC_CKCTRL_LOCK_SHIFT                    (31U)
/*! LOCK - Lock Register
 *  0b0..Register writes are allowed.
 *  0b1..Register writes are blocked.
 */
#define CMC_CKCTRL_LOCK(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_CKCTRL_LOCK_SHIFT)) & CMC_CKCTRL_LOCK_MASK)
/*! @} */

/*! @name CKSTAT - Clock Status Register */
/*! @{ */

#define CMC_CKSTAT_CKMODE_MASK                   (0xFU)
#define CMC_CKSTAT_CKMODE_SHIFT                  (0U)
/*! CKMODE - Low Power Status
 *  0b0000..Core clock not gated.
 *  0b0001..Core clock was gated
 *  0b0011..Core and platform clocks were gated
 *  0b0111..Core, platform, and peripheral clocks were gated
 *  0b1111..Core, platform, and peripheral clocks were gated, and power domain entered low power mode.
 */
#define CMC_CKSTAT_CKMODE(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_CKSTAT_CKMODE_SHIFT)) & CMC_CKSTAT_CKMODE_MASK)

#define CMC_CKSTAT_WAKEUP_MASK                   (0x7F00U)
#define CMC_CKSTAT_WAKEUP_SHIFT                  (8U)
/*! WAKEUP - Wakeup Source
 */
#define CMC_CKSTAT_WAKEUP(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_CKSTAT_WAKEUP_SHIFT)) & CMC_CKSTAT_WAKEUP_MASK)

#define CMC_CKSTAT_VALID_MASK                    (0x80000000U)
#define CMC_CKSTAT_VALID_SHIFT                   (31U)
/*! VALID - Clock Status Valid
 *  0b0..Core clock not gated.
 *  0b1..Core clock was gated due to low power mode entry.
 */
#define CMC_CKSTAT_VALID(x)                      (((uint32_t)(((uint32_t)(x)) << CMC_CKSTAT_VALID_SHIFT)) & CMC_CKSTAT_VALID_MASK)
/*! @} */

/*! @name PMPROT - Power Mode Protection Register */
/*! @{ */

#define CMC_PMPROT_LPMODE_MASK                   (0xFU)
#define CMC_PMPROT_LPMODE_SHIFT                  (0U)
/*! LPMODE - Low Power Mode
 */
#define CMC_PMPROT_LPMODE(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_PMPROT_LPMODE_SHIFT)) & CMC_PMPROT_LPMODE_MASK)

#define CMC_PMPROT_LOCK_MASK                     (0x80000000U)
#define CMC_PMPROT_LOCK_SHIFT                    (31U)
/*! LOCK - Lock Register
 *  0b0..Register writes are allowed.
 *  0b1..Register writes are blocked.
 */
#define CMC_PMPROT_LOCK(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_PMPROT_LOCK_SHIFT)) & CMC_PMPROT_LOCK_MASK)
/*! @} */

/*! @name GPMCTRL - Global Power Mode Control Register */
/*! @{ */

#define CMC_GPMCTRL_LPMODE_MASK                  (0xFU)
#define CMC_GPMCTRL_LPMODE_SHIFT                 (0U)
/*! LPMODE - Low Power Mode
 */
#define CMC_GPMCTRL_LPMODE(x)                    (((uint32_t)(((uint32_t)(x)) << CMC_GPMCTRL_LPMODE_SHIFT)) & CMC_GPMCTRL_LPMODE_MASK)
/*! @} */

/*! @name PMCTRL - Power Mode Control Register */
/*! @{ */

#define CMC_PMCTRL_LPMODE_MASK                   (0xFU)
#define CMC_PMCTRL_LPMODE_SHIFT                  (0U)
/*! LPMODE - Low Power Mode
 *  0b0000..Active
 *  0b0001..Sleep
 *  0b0011..Deep Sleep
 *  0b0111..Power Down
 *  0b1111..Deep Power Down
 */
#define CMC_PMCTRL_LPMODE(x)                     (((uint32_t)(((uint32_t)(x)) << CMC_PMCTRL_LPMODE_SHIFT)) & CMC_PMCTRL_LPMODE_MASK)
/*! @} */

/* The count of CMC_PMCTRL */
#define CMC_PMCTRL_COUNT                         (2U)

/*! @name SRS - System Reset Status Register */
/*! @{ */

#define CMC_SRS_WAKEUP_MASK                      (0x1U)
#define CMC_SRS_WAKEUP_SHIFT                     (0U)
/*! WAKEUP - Wakeup Reset
 *  0b0..Reset not generated by wakeup from Power Down or Deep Power Down mode.
 *  0b1..Reset generated by wakeup from Power Down or Deep Power Down mode.
 */
#define CMC_SRS_WAKEUP(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SRS_WAKEUP_SHIFT)) & CMC_SRS_WAKEUP_MASK)

#define CMC_SRS_POR_MASK                         (0x2U)
#define CMC_SRS_POR_SHIFT                        (1U)
/*! POR - Power-on Reset
 *  0b0..Reset not generated by POR.
 *  0b1..Reset generated by POR.
 */
#define CMC_SRS_POR(x)                           (((uint32_t)(((uint32_t)(x)) << CMC_SRS_POR_SHIFT)) & CMC_SRS_POR_MASK)

#define CMC_SRS_LVD_MASK                         (0x4U)
#define CMC_SRS_LVD_SHIFT                        (2U)
/*! LVD - Low Voltage Detect Reset
 *  0b0..Reset not generated by LVD.
 *  0b1..Reset generated by LVD.
 */
#define CMC_SRS_LVD(x)                           (((uint32_t)(((uint32_t)(x)) << CMC_SRS_LVD_SHIFT)) & CMC_SRS_LVD_MASK)

#define CMC_SRS_HVD_MASK                         (0x8U)
#define CMC_SRS_HVD_SHIFT                        (3U)
/*! HVD - High Voltage Detect Reset
 *  0b0..Reset not generated by HVD.
 *  0b1..Reset generated by HVD.
 */
#define CMC_SRS_HVD(x)                           (((uint32_t)(((uint32_t)(x)) << CMC_SRS_HVD_SHIFT)) & CMC_SRS_HVD_MASK)

#define CMC_SRS_WARM_MASK                        (0x10U)
#define CMC_SRS_WARM_SHIFT                       (4U)
/*! WARM - Warm Reset
 *  0b0..Reset not generated by Warm Reset source.
 *  0b1..Reset generated by Warm Reset source.
 */
#define CMC_SRS_WARM(x)                          (((uint32_t)(((uint32_t)(x)) << CMC_SRS_WARM_SHIFT)) & CMC_SRS_WARM_MASK)

#define CMC_SRS_FATAL_MASK                       (0x20U)
#define CMC_SRS_FATAL_SHIFT                      (5U)
/*! FATAL - Fatal Reset
 *  0b0..Reset was not generated by a fatal reset source.
 *  0b1..Reset was generated by a fatal reset source.
 */
#define CMC_SRS_FATAL(x)                         (((uint32_t)(((uint32_t)(x)) << CMC_SRS_FATAL_SHIFT)) & CMC_SRS_FATAL_MASK)

#define CMC_SRS_PIN_MASK                         (0x100U)
#define CMC_SRS_PIN_SHIFT                        (8U)
/*! PIN - Pin Reset
 *  0b0..Reset was not generated from the assertion of RESET_b pin.
 *  0b1..Reset was generated from the assertion of RESET_b pin.
 */
#define CMC_SRS_PIN(x)                           (((uint32_t)(((uint32_t)(x)) << CMC_SRS_PIN_SHIFT)) & CMC_SRS_PIN_MASK)

#define CMC_SRS_DAP_MASK                         (0x200U)
#define CMC_SRS_DAP_SHIFT                        (9U)
/*! DAP - Debug Access Port Reset
 *  0b0..Reset was not generated from a DAP reset request.
 *  0b1..Reset was generated from a DAP reset request.
 */
#define CMC_SRS_DAP(x)                           (((uint32_t)(((uint32_t)(x)) << CMC_SRS_DAP_SHIFT)) & CMC_SRS_DAP_MASK)

#define CMC_SRS_RSTACK_MASK                      (0x400U)
#define CMC_SRS_RSTACK_SHIFT                     (10U)
/*! RSTACK - Reset Timeout
 *  0b0..Reset not generated from Reset Controller Timeout.
 *  0b1..Reset generated from Reset Controller Timeout.
 */
#define CMC_SRS_RSTACK(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SRS_RSTACK_SHIFT)) & CMC_SRS_RSTACK_MASK)

#define CMC_SRS_LPACK_MASK                       (0x800U)
#define CMC_SRS_LPACK_SHIFT                      (11U)
/*! LPACK - Low Power Acknowledge Timeout Reset
 *  0b0..Reset not generated by Low Power Acknowledge Timeout.
 *  0b1..Reset generated by Low Power Acknowledge Timeout.
 */
#define CMC_SRS_LPACK(x)                         (((uint32_t)(((uint32_t)(x)) << CMC_SRS_LPACK_SHIFT)) & CMC_SRS_LPACK_MASK)

#define CMC_SRS_SCG_MASK                         (0x1000U)
#define CMC_SRS_SCG_SHIFT                        (12U)
/*! SCG - System Clock Generation Reset
 *  0b0..Reset is not generated from an SCG loss of lock or loss of clock.
 *  0b1..Reset is generated from an SCG loss of lock or loss of clock.
 */
#define CMC_SRS_SCG(x)                           (((uint32_t)(((uint32_t)(x)) << CMC_SRS_SCG_SHIFT)) & CMC_SRS_SCG_MASK)

#define CMC_SRS_WDOG0_MASK                       (0x2000U)
#define CMC_SRS_WDOG0_SHIFT                      (13U)
/*! WDOG0 - Watchdog 0 Reset
 *  0b0..Reset is not generated from the WatchDog 0 timeout.
 *  0b1..Reset is generated from the WatchDog 0 timeout.
 */
#define CMC_SRS_WDOG0(x)                         (((uint32_t)(((uint32_t)(x)) << CMC_SRS_WDOG0_SHIFT)) & CMC_SRS_WDOG0_MASK)

#define CMC_SRS_SW_MASK                          (0x4000U)
#define CMC_SRS_SW_SHIFT                         (14U)
/*! SW - Software Reset
 *  0b0..Reset not generated by software request from core.
 *  0b1..Reset generated by software request from core.
 */
#define CMC_SRS_SW(x)                            (((uint32_t)(((uint32_t)(x)) << CMC_SRS_SW_SHIFT)) & CMC_SRS_SW_MASK)

#define CMC_SRS_LOCKUP_MASK                      (0x8000U)
#define CMC_SRS_LOCKUP_SHIFT                     (15U)
/*! LOCKUP - Lockup Reset
 *  0b0..Reset not generated by core lockup or exception.
 *  0b1..Reset generated by core lockup or exception.
 */
#define CMC_SRS_LOCKUP(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SRS_LOCKUP_SHIFT)) & CMC_SRS_LOCKUP_MASK)

#define CMC_SRS_WDOG1_MASK                       (0x2000000U)
#define CMC_SRS_WDOG1_SHIFT                      (25U)
/*! WDOG1 - Watchdog 1 Reset
 *  0b0..Reset is not generated from the WatchDog 1 timeout.
 *  0b1..Reset is generated from the WatchDog 1 timeout.
 */
#define CMC_SRS_WDOG1(x)                         (((uint32_t)(((uint32_t)(x)) << CMC_SRS_WDOG1_SHIFT)) & CMC_SRS_WDOG1_MASK)

#define CMC_SRS_SECVIO_MASK                      (0x40000000U)
#define CMC_SRS_SECVIO_SHIFT                     (30U)
/*! SECVIO - Security Violation Reset
 *  0b0..Reset not generated by security violation.
 *  0b1..Reset generated by security violation.
 */
#define CMC_SRS_SECVIO(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SRS_SECVIO_SHIFT)) & CMC_SRS_SECVIO_MASK)
/*! @} */

/*! @name RPC - Reset Pin Control Register */
/*! @{ */

#define CMC_RPC_FILTCFG_MASK                     (0x1FU)
#define CMC_RPC_FILTCFG_SHIFT                    (0U)
/*! FILTCFG - Reset Filter Configuration
 */
#define CMC_RPC_FILTCFG(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_RPC_FILTCFG_SHIFT)) & CMC_RPC_FILTCFG_MASK)

#define CMC_RPC_FILTEN_MASK                      (0x100U)
#define CMC_RPC_FILTEN_SHIFT                     (8U)
/*! FILTEN - Filter Enable
 *  0b0..Slow clock reset pin filter disabled.
 *  0b1..Slow clock reset pin filter enabled in Active modes.
 */
#define CMC_RPC_FILTEN(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_RPC_FILTEN_SHIFT)) & CMC_RPC_FILTEN_MASK)

#define CMC_RPC_LPFEN_MASK                       (0x200U)
#define CMC_RPC_LPFEN_SHIFT                      (9U)
/*! LPFEN - Low Power Filter Enable
 *  0b0..Low power reset pin filter disabled.
 *  0b1..Low power reset pin filter enabled in Active and Low Power modes.
 */
#define CMC_RPC_LPFEN(x)                         (((uint32_t)(((uint32_t)(x)) << CMC_RPC_LPFEN_SHIFT)) & CMC_RPC_LPFEN_MASK)
/*! @} */

/*! @name SSRS - Sticky System Reset Status Register */
/*! @{ */

#define CMC_SSRS_WAKEUP_MASK                     (0x1U)
#define CMC_SSRS_WAKEUP_SHIFT                    (0U)
/*! WAKEUP - Wakeup Reset
 *  0b0..Reset not generated by wakeup from VLLS mode.
 *  0b1..Reset generated by wakeup from VLLS mode.
 */
#define CMC_SSRS_WAKEUP(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_WAKEUP_SHIFT)) & CMC_SSRS_WAKEUP_MASK)

#define CMC_SSRS_POR_MASK                        (0x2U)
#define CMC_SSRS_POR_SHIFT                       (1U)
/*! POR - Power-on Reset
 *  0b0..Reset not generated by POR.
 *  0b1..Reset generated by POR.
 */
#define CMC_SSRS_POR(x)                          (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_POR_SHIFT)) & CMC_SSRS_POR_MASK)

#define CMC_SSRS_LVD_MASK                        (0x4U)
#define CMC_SSRS_LVD_SHIFT                       (2U)
/*! LVD - Low Voltage Detect Reset
 *  0b0..Reset not generated by LVD.
 *  0b1..Reset generated by LVD.
 */
#define CMC_SSRS_LVD(x)                          (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_LVD_SHIFT)) & CMC_SSRS_LVD_MASK)

#define CMC_SSRS_HVD_MASK                        (0x8U)
#define CMC_SSRS_HVD_SHIFT                       (3U)
/*! HVD - High Voltage Detect Reset
 *  0b0..Reset not generated by HVD.
 *  0b1..Reset generated by HVD.
 */
#define CMC_SSRS_HVD(x)                          (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_HVD_SHIFT)) & CMC_SSRS_HVD_MASK)

#define CMC_SSRS_WARM_MASK                       (0x10U)
#define CMC_SSRS_WARM_SHIFT                      (4U)
/*! WARM - Warm Reset
 *  0b0..Reset not generated by warm reset source.
 *  0b1..Reset generated by warm reset source.
 */
#define CMC_SSRS_WARM(x)                         (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_WARM_SHIFT)) & CMC_SSRS_WARM_MASK)

#define CMC_SSRS_FATAL_MASK                      (0x20U)
#define CMC_SSRS_FATAL_SHIFT                     (5U)
/*! FATAL - Fatal Reset
 *  0b0..Reset was not generated by a fatal reset source.
 *  0b1..Reset was generated by a fatal reset source.
 */
#define CMC_SSRS_FATAL(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_FATAL_SHIFT)) & CMC_SSRS_FATAL_MASK)

#define CMC_SSRS_PIN_MASK                        (0x100U)
#define CMC_SSRS_PIN_SHIFT                       (8U)
/*! PIN - Pin Reset
 *  0b0..Reset was not generated from the RESET_B pin.
 *  0b1..Reset was generated from the RESET_B pin.
 */
#define CMC_SSRS_PIN(x)                          (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_PIN_SHIFT)) & CMC_SSRS_PIN_MASK)

#define CMC_SSRS_DAP_MASK                        (0x200U)
#define CMC_SSRS_DAP_SHIFT                       (9U)
/*! DAP - DAP Reset
 *  0b0..Reset was not generated from a DAP reset request.
 *  0b1..Reset was generated from a DAP reset request.
 */
#define CMC_SSRS_DAP(x)                          (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_DAP_SHIFT)) & CMC_SSRS_DAP_MASK)

#define CMC_SSRS_RSTACK_MASK                     (0x400U)
#define CMC_SSRS_RSTACK_SHIFT                    (10U)
/*! RSTACK - Reset Timeout
 *  0b0..Reset not generated from Reset Controller Timeout.
 *  0b1..Reset generated from Reset Controller Timeout.
 */
#define CMC_SSRS_RSTACK(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_RSTACK_SHIFT)) & CMC_SSRS_RSTACK_MASK)

#define CMC_SSRS_LPACK_MASK                      (0x800U)
#define CMC_SSRS_LPACK_SHIFT                     (11U)
/*! LPACK - Low Power Acknowledge Timeout Reset
 *  0b0..Reset not generated by Low Power Acknowledge Timeout.
 *  0b1..Reset generated by Low Power Acknowledge Timeout.
 */
#define CMC_SSRS_LPACK(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_LPACK_SHIFT)) & CMC_SSRS_LPACK_MASK)

#define CMC_SSRS_SCG_MASK                        (0x1000U)
#define CMC_SSRS_SCG_SHIFT                       (12U)
/*! SCG - System Clock Generation Reset
 *  0b0..Reset is not generated from an SCG loss of lock or loss of clock.
 *  0b1..Reset is generated from an SCG loss of lock or loss of clock.
 */
#define CMC_SSRS_SCG(x)                          (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_SCG_SHIFT)) & CMC_SSRS_SCG_MASK)

#define CMC_SSRS_WDOG0_MASK                      (0x2000U)
#define CMC_SSRS_WDOG0_SHIFT                     (13U)
/*! WDOG0 - Watchdog 0 Reset
 *  0b0..Reset is not generated from the WatchDog 0 timeout.
 *  0b1..Reset is generated from the WatchDog 0 timeout.
 */
#define CMC_SSRS_WDOG0(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_WDOG0_SHIFT)) & CMC_SSRS_WDOG0_MASK)

#define CMC_SSRS_SW_MASK                         (0x4000U)
#define CMC_SSRS_SW_SHIFT                        (14U)
/*! SW - Software Reset
 *  0b0..Reset not generated by software request from core.
 *  0b1..Reset generated by software request from core.
 */
#define CMC_SSRS_SW(x)                           (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_SW_SHIFT)) & CMC_SSRS_SW_MASK)

#define CMC_SSRS_LOCKUP_MASK                     (0x8000U)
#define CMC_SSRS_LOCKUP_SHIFT                    (15U)
/*! LOCKUP - Lockup Reset
 *  0b0..Reset not generated by core lockup.
 *  0b1..Reset generated by core lockup.
 */
#define CMC_SSRS_LOCKUP(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_LOCKUP_SHIFT)) & CMC_SSRS_LOCKUP_MASK)

#define CMC_SSRS_WDOG1_MASK                      (0x2000000U)
#define CMC_SSRS_WDOG1_SHIFT                     (25U)
/*! WDOG1 - Watchdog 1 Reset
 *  0b0..Reset is not generated from the WatchDog 1 timeout.
 *  0b1..Reset is generated from the WatchDog 1 timeout.
 */
#define CMC_SSRS_WDOG1(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_WDOG1_SHIFT)) & CMC_SSRS_WDOG1_MASK)

#define CMC_SSRS_SECVIO_MASK                     (0x40000000U)
#define CMC_SSRS_SECVIO_SHIFT                    (30U)
/*! SECVIO - Security Violation Reset
 *  0b0..Reset not generated by Security Violation detection.
 *  0b1..Reset generated by Security Violation detection.
 */
#define CMC_SSRS_SECVIO(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_SECVIO_SHIFT)) & CMC_SSRS_SECVIO_MASK)
/*! @} */

/*! @name SRIE - System Reset Interrupt Enable Register */
/*! @{ */

#define CMC_SRIE_PIN_MASK                        (0x100U)
#define CMC_SRIE_PIN_SHIFT                       (8U)
/*! PIN - Pin Reset
 *  0b0..Interrupt disabled.
 *  0b1..Interrupt enabled.
 */
#define CMC_SRIE_PIN(x)                          (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_PIN_SHIFT)) & CMC_SRIE_PIN_MASK)

#define CMC_SRIE_DAP_MASK                        (0x200U)
#define CMC_SRIE_DAP_SHIFT                       (9U)
/*! DAP - DAP Reset
 *  0b0..Interrupt disabled.
 *  0b1..Interrupt enabled.
 */
#define CMC_SRIE_DAP(x)                          (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_DAP_SHIFT)) & CMC_SRIE_DAP_MASK)

#define CMC_SRIE_LPACK_MASK                      (0x800U)
#define CMC_SRIE_LPACK_SHIFT                     (11U)
/*! LPACK - Low Power Acknowledge Timeout Reset
 *  0b0..Interrupt disabled.
 *  0b1..Interrupt enabled.
 */
#define CMC_SRIE_LPACK(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_LPACK_SHIFT)) & CMC_SRIE_LPACK_MASK)

#define CMC_SRIE_WDOG0_MASK                      (0x2000U)
#define CMC_SRIE_WDOG0_SHIFT                     (13U)
/*! WDOG0 - Watchdog 0 Reset
 *  0b0..Interrupt disabled.
 *  0b1..Interrupt enabled.
 */
#define CMC_SRIE_WDOG0(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_WDOG0_SHIFT)) & CMC_SRIE_WDOG0_MASK)

#define CMC_SRIE_SW_MASK                         (0x4000U)
#define CMC_SRIE_SW_SHIFT                        (14U)
/*! SW - Software Reset
 *  0b0..Interrupt disabled.
 *  0b1..Interrupt enabled.
 */
#define CMC_SRIE_SW(x)                           (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_SW_SHIFT)) & CMC_SRIE_SW_MASK)

#define CMC_SRIE_LOCKUP_MASK                     (0x8000U)
#define CMC_SRIE_LOCKUP_SHIFT                    (15U)
/*! LOCKUP - Lockup Reset
 *  0b0..Interrupt disabled.
 *  0b1..Interrupt enabled.
 */
#define CMC_SRIE_LOCKUP(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_LOCKUP_SHIFT)) & CMC_SRIE_LOCKUP_MASK)

#define CMC_SRIE_WDOG1_MASK                      (0x2000000U)
#define CMC_SRIE_WDOG1_SHIFT                     (25U)
/*! WDOG1 - Watchdog 1 Reset
 *  0b0..Interrupt disabled.
 *  0b1..Interrupt enabled.
 */
#define CMC_SRIE_WDOG1(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_WDOG1_SHIFT)) & CMC_SRIE_WDOG1_MASK)
/*! @} */

/*! @name SRIF - System Reset Interrupt Flag Register */
/*! @{ */

#define CMC_SRIF_PIN_MASK                        (0x100U)
#define CMC_SRIF_PIN_SHIFT                       (8U)
/*! PIN - Pin Reset
 *  0b0..Reset source not pending.
 *  0b1..Reset source pending.
 */
#define CMC_SRIF_PIN(x)                          (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_PIN_SHIFT)) & CMC_SRIF_PIN_MASK)

#define CMC_SRIF_DAP_MASK                        (0x200U)
#define CMC_SRIF_DAP_SHIFT                       (9U)
/*! DAP - DAP Reset
 *  0b0..Reset source not pending.
 *  0b1..Reset source pending.
 */
#define CMC_SRIF_DAP(x)                          (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_DAP_SHIFT)) & CMC_SRIF_DAP_MASK)

#define CMC_SRIF_LPACK_MASK                      (0x800U)
#define CMC_SRIF_LPACK_SHIFT                     (11U)
/*! LPACK - Low Power Acknowledge Timeout Reset
 *  0b0..Reset source not pending.
 *  0b1..Reset source pending.
 */
#define CMC_SRIF_LPACK(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_LPACK_SHIFT)) & CMC_SRIF_LPACK_MASK)

#define CMC_SRIF_WDOG0_MASK                      (0x2000U)
#define CMC_SRIF_WDOG0_SHIFT                     (13U)
/*! WDOG0 - Watchdog 0 Reset
 *  0b0..Reset source not pending.
 *  0b1..Reset source pending.
 */
#define CMC_SRIF_WDOG0(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_WDOG0_SHIFT)) & CMC_SRIF_WDOG0_MASK)

#define CMC_SRIF_SW_MASK                         (0x4000U)
#define CMC_SRIF_SW_SHIFT                        (14U)
/*! SW - Software Reset
 *  0b0..Reset source not pending.
 *  0b1..Reset source pending.
 */
#define CMC_SRIF_SW(x)                           (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_SW_SHIFT)) & CMC_SRIF_SW_MASK)

#define CMC_SRIF_LOCKUP_MASK                     (0x8000U)
#define CMC_SRIF_LOCKUP_SHIFT                    (15U)
/*! LOCKUP - Lockup Reset
 *  0b0..Reset source not pending.
 *  0b1..Reset source pending.
 */
#define CMC_SRIF_LOCKUP(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_LOCKUP_SHIFT)) & CMC_SRIF_LOCKUP_MASK)

#define CMC_SRIF_WDOG1_MASK                      (0x2000000U)
#define CMC_SRIF_WDOG1_SHIFT                     (25U)
/*! WDOG1 - Watchdog 1 Reset
 *  0b0..Reset source not pending.
 *  0b1..Reset source pending.
 */
#define CMC_SRIF_WDOG1(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_WDOG1_SHIFT)) & CMC_SRIF_WDOG1_MASK)
/*! @} */

/*! @name RSTCNT - Reset Count Register */
/*! @{ */

#define CMC_RSTCNT_COUNT_MASK                    (0xFFU)
#define CMC_RSTCNT_COUNT_SHIFT                   (0U)
/*! COUNT - Count
 */
#define CMC_RSTCNT_COUNT(x)                      (((uint32_t)(((uint32_t)(x)) << CMC_RSTCNT_COUNT_SHIFT)) & CMC_RSTCNT_COUNT_MASK)
/*! @} */

/*! @name MR - Mode Register */
/*! @{ */

#define CMC_MR_ISPMODE_n_MASK                    (0x1U)
#define CMC_MR_ISPMODE_n_SHIFT                   (0U)
/*! ISPMODE_n - In System Programming Mode
 */
#define CMC_MR_ISPMODE_n(x)                      (((uint32_t)(((uint32_t)(x)) << CMC_MR_ISPMODE_n_SHIFT)) & CMC_MR_ISPMODE_n_MASK)
/*! @} */

/* The count of CMC_MR */
#define CMC_MR_COUNT                             (1U)

/*! @name FM - Force Mode Register */
/*! @{ */

#define CMC_FM_FORCECFG_MASK                     (0x1U)
#define CMC_FM_FORCECFG_SHIFT                    (0U)
/*! FORCECFG - Boot Configuration
 *  0b0..No effect.
 *  0b1..Assert corresponding bit in Mode Register on next system reset.
 */
#define CMC_FM_FORCECFG(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_FM_FORCECFG_SHIFT)) & CMC_FM_FORCECFG_MASK)
/*! @} */

/* The count of CMC_FM */
#define CMC_FM_COUNT                             (1U)

/*! @name SRAMDIS - SRAM Disable Register */
/*! @{ */

#define CMC_SRAMDIS_DIS_MASK                     (0xFFU)
#define CMC_SRAMDIS_DIS_SHIFT                    (0U)
/*! DIS - SRAM Disable
 */
#define CMC_SRAMDIS_DIS(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS_SHIFT)) & CMC_SRAMDIS_DIS_MASK)
/*! @} */

/* The count of CMC_SRAMDIS */
#define CMC_SRAMDIS_COUNT                        (1U)

/*! @name SRAMRET - SRAM Retention Register */
/*! @{ */

#define CMC_SRAMRET_RET_MASK                     (0xFFU)
#define CMC_SRAMRET_RET_SHIFT                    (0U)
/*! RET - SRAM Retention
 */
#define CMC_SRAMRET_RET(x)                       (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET_SHIFT)) & CMC_SRAMRET_RET_MASK)
/*! @} */

/* The count of CMC_SRAMRET */
#define CMC_SRAMRET_COUNT                        (1U)

/*! @name FLASHCR - Flash Control Register */
/*! @{ */

#define CMC_FLASHCR_FLASHDIS_MASK                (0x1U)
#define CMC_FLASHCR_FLASHDIS_SHIFT               (0U)
/*! FLASHDIS - Flash Disable
 *  0b0..No effect.
 *  0b1..Flash is disabled.
 */
#define CMC_FLASHCR_FLASHDIS(x)                  (((uint32_t)(((uint32_t)(x)) << CMC_FLASHCR_FLASHDIS_SHIFT)) & CMC_FLASHCR_FLASHDIS_MASK)

#define CMC_FLASHCR_FLASHDOZE_MASK               (0x2U)
#define CMC_FLASHCR_FLASHDOZE_SHIFT              (1U)
/*! FLASHDOZE - Flash Doze
 *  0b0..No effect.
 *  0b1..Flash is disabled while core is sleeping (CKMODE > 0).
 */
#define CMC_FLASHCR_FLASHDOZE(x)                 (((uint32_t)(((uint32_t)(x)) << CMC_FLASHCR_FLASHDOZE_SHIFT)) & CMC_FLASHCR_FLASHDOZE_MASK)

#define CMC_FLASHCR_FLASHWAKE_MASK               (0x4U)
#define CMC_FLASHCR_FLASHWAKE_SHIFT              (2U)
/*! FLASHWAKE - Flash Wake
 *  0b0..No effect.
 *  0b1..Flash is not disabled during Flash memory accesses.
 */
#define CMC_FLASHCR_FLASHWAKE(x)                 (((uint32_t)(((uint32_t)(x)) << CMC_FLASHCR_FLASHWAKE_SHIFT)) & CMC_FLASHCR_FLASHWAKE_MASK)
/*! @} */

/*! @name BSR - BootROM Status Register */
/*! @{ */

#define CMC_BSR_STAT_MASK                        (0xFFFFFFFFU)
#define CMC_BSR_STAT_SHIFT                       (0U)
/*! STAT - This register field provides status information written by the BootROM.
 */
#define CMC_BSR_STAT(x)                          (((uint32_t)(((uint32_t)(x)) << CMC_BSR_STAT_SHIFT)) & CMC_BSR_STAT_MASK)
/*! @} */

/*! @name BLR - BootROM Lock Register */
/*! @{ */

#define CMC_BLR_LOCK_MASK                        (0x7U)
#define CMC_BLR_LOCK_SHIFT                       (0U)
/*! LOCK - Lock
 *  0b010..BootROM Status and Lock Registers can be written
 *  0b101..BootROM Status and Lock Registers cannot be written
 */
#define CMC_BLR_LOCK(x)                          (((uint32_t)(((uint32_t)(x)) << CMC_BLR_LOCK_SHIFT)) & CMC_BLR_LOCK_MASK)
/*! @} */

/*! @name CORECTL - Core Control Register */
/*! @{ */

#define CMC_CORECTL_NPIE_MASK                    (0x1U)
#define CMC_CORECTL_NPIE_SHIFT                   (0U)
/*! NPIE - Non-maskable Pin Interrupt Enable
 *  0b0..Pin interrupt disabled
 *  0b1..Pin interrupt enabled
 */
#define CMC_CORECTL_NPIE(x)                      (((uint32_t)(((uint32_t)(x)) << CMC_CORECTL_NPIE_SHIFT)) & CMC_CORECTL_NPIE_MASK)
/*! @} */

/*! @name DBGCTL - Debug Control Register */
/*! @{ */

#define CMC_DBGCTL_SOD_MASK                      (0x1U)
#define CMC_DBGCTL_SOD_SHIFT                     (0U)
/*! SOD - Sleep Or Debug
 *  0b0..Debug remains enabled when Core is sleeping.
 *  0b1..Debug is disabled when Core is sleeping.
 */
#define CMC_DBGCTL_SOD(x)                        (((uint32_t)(((uint32_t)(x)) << CMC_DBGCTL_SOD_SHIFT)) & CMC_DBGCTL_SOD_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group CMC_Register_Masks */


/* CMC - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral CMC0 base address */
  #define CMC0_BASE                                (0x50001000u)
  /** Peripheral CMC0 base address */
  #define CMC0_BASE_NS                             (0x40001000u)
  /** Peripheral CMC0 base pointer */
  #define CMC0                                     ((CMC_Type *)CMC0_BASE)
  /** Peripheral CMC0 base pointer */
  #define CMC0_NS                                  ((CMC_Type *)CMC0_BASE_NS)
  /** Array initializer of CMC peripheral base addresses */
  #define CMC_BASE_ADDRS                           { CMC0_BASE }
  /** Array initializer of CMC peripheral base pointers */
  #define CMC_BASE_PTRS                            { CMC0 }
  /** Array initializer of CMC peripheral base addresses */
  #define CMC_BASE_ADDRS_NS                        { CMC0_BASE_NS }
  /** Array initializer of CMC peripheral base pointers */
  #define CMC_BASE_PTRS_NS                         { CMC0_NS }
#else
  /** Peripheral CMC0 base address */
  #define CMC0_BASE                                (0x40001000u)
  /** Peripheral CMC0 base pointer */
  #define CMC0                                     ((CMC_Type *)CMC0_BASE)
  /** Array initializer of CMC peripheral base addresses */
  #define CMC_BASE_ADDRS                           { CMC0_BASE }
  /** Array initializer of CMC peripheral base pointers */
  #define CMC_BASE_PTRS                            { CMC0 }
#endif

/*!
 * @}
 */ /* end of group CMC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CRC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
 * @{
 */

/** CRC - Register Layout Typedef */
typedef struct {
  union {                                          /* offset: 0x0 */
    struct {                                         /* offset: 0x0 */
      __IO uint8_t DATALL;                             /**< CRC_DATALL register, offset: 0x0 */
      __IO uint8_t DATALU;                             /**< CRC_DATALU register, offset: 0x1 */
      __IO uint8_t DATAHL;                             /**< CRC_DATAHL register, offset: 0x2 */
      __IO uint8_t DATAHU;                             /**< CRC_DATAHU register, offset: 0x3 */
    } ACCESS8BIT;
    struct {                                         /* offset: 0x0 */
      __IO uint16_t DATAL;                             /**< CRC_DATAL register, offset: 0x0 */
      __IO uint16_t DATAH;                             /**< CRC_DATAH register, offset: 0x2 */
    } ACCESS16BIT;
    __IO uint32_t DATA;                              /**< CRC DATA register, offset: 0x0 */
  };
  union {                                          /* offset: 0x4 */
    struct {                                         /* offset: 0x4 */
      __IO uint8_t GPOLYLL;                            /**< CRC_GPOLYLL register, offset: 0x4 */
      __IO uint8_t GPOLYLU;                            /**< CRC_GPOLYLU register, offset: 0x5 */
      __IO uint8_t GPOLYHL;                            /**< CRC_GPOLYHL register, offset: 0x6 */
      __IO uint8_t GPOLYHU;                            /**< CRC_GPOLYHU register, offset: 0x7 */
    } GPOLY_ACCESS8BIT;
    struct {                                         /* offset: 0x4 */
      __IO uint16_t GPOLYL;                            /**< CRC_GPOLYL register, offset: 0x4 */
      __IO uint16_t GPOLYH;                            /**< CRC_GPOLYH register, offset: 0x6 */
    } GPOLY_ACCESS16BIT;
    __IO uint32_t GPOLY;                             /**< CRC Polynomial register, offset: 0x4 */
  };
  union {                                          /* offset: 0x8 */
    struct {                                         /* offset: 0x8 */
           uint8_t RESERVED_0[3];
      __IO uint8_t CTRLHU;                             /**< CRC_CTRLHU register, offset: 0xB */
    } CTRL_ACCESS8BIT;
    __IO uint32_t CTRL;                              /**< CRC Control register, offset: 0x8 */
  };
} CRC_Type;

/* ----------------------------------------------------------------------------
   -- CRC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CRC_Register_Masks CRC Register Masks
 * @{
 */

/*! @name DATALL - CRC_DATALL register */
/*! @{ */

#define CRC_DATALL_DATALL_MASK                   (0xFFU)
#define CRC_DATALL_DATALL_SHIFT                  (0U)
#define CRC_DATALL_DATALL(x)                     (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK)
/*! @} */

/*! @name DATALU - CRC_DATALU register */
/*! @{ */

#define CRC_DATALU_DATALU_MASK                   (0xFFU)
#define CRC_DATALU_DATALU_SHIFT                  (0U)
#define CRC_DATALU_DATALU(x)                     (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK)
/*! @} */

/*! @name DATAHL - CRC_DATAHL register */
/*! @{ */

#define CRC_DATAHL_DATAHL_MASK                   (0xFFU)
#define CRC_DATAHL_DATAHL_SHIFT                  (0U)
#define CRC_DATAHL_DATAHL(x)                     (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK)
/*! @} */

/*! @name DATAHU - CRC_DATAHU register */
/*! @{ */

#define CRC_DATAHU_DATAHU_MASK                   (0xFFU)
#define CRC_DATAHU_DATAHU_SHIFT                  (0U)
#define CRC_DATAHU_DATAHU(x)                     (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK)
/*! @} */

/*! @name DATAL - CRC_DATAL register */
/*! @{ */

#define CRC_DATAL_DATAL_MASK                     (0xFFFFU)
#define CRC_DATAL_DATAL_SHIFT                    (0U)
#define CRC_DATAL_DATAL(x)                       (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK)
/*! @} */

/*! @name DATAH - CRC_DATAH register */
/*! @{ */

#define CRC_DATAH_DATAH_MASK                     (0xFFFFU)
#define CRC_DATAH_DATAH_SHIFT                    (0U)
#define CRC_DATAH_DATAH(x)                       (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK)
/*! @} */

/*! @name DATA - CRC DATA register */
/*! @{ */

#define CRC_DATA_LL_MASK                         (0xFFU)
#define CRC_DATA_LL_SHIFT                        (0U)
/*! LL - CRC Low Lower Byte
 */
#define CRC_DATA_LL(x)                           (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK)

#define CRC_DATA_LU_MASK                         (0xFF00U)
#define CRC_DATA_LU_SHIFT                        (8U)
/*! LU - CRC Low Upper Byte
 */
#define CRC_DATA_LU(x)                           (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK)

#define CRC_DATA_HL_MASK                         (0xFF0000U)
#define CRC_DATA_HL_SHIFT                        (16U)
/*! HL - CRC High Lower Byte
 */
#define CRC_DATA_HL(x)                           (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK)

#define CRC_DATA_HU_MASK                         (0xFF000000U)
#define CRC_DATA_HU_SHIFT                        (24U)
/*! HU - CRC High Upper Byte
 */
#define CRC_DATA_HU(x)                           (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK)
/*! @} */

/*! @name GPOLYLL - CRC_GPOLYLL register */
/*! @{ */

#define CRC_GPOLYLL_GPOLYLL_MASK                 (0xFFU)
#define CRC_GPOLYLL_GPOLYLL_SHIFT                (0U)
#define CRC_GPOLYLL_GPOLYLL(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK)
/*! @} */

/*! @name GPOLYLU - CRC_GPOLYLU register */
/*! @{ */

#define CRC_GPOLYLU_GPOLYLU_MASK                 (0xFFU)
#define CRC_GPOLYLU_GPOLYLU_SHIFT                (0U)
#define CRC_GPOLYLU_GPOLYLU(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK)
/*! @} */

/*! @name GPOLYHL - CRC_GPOLYHL register */
/*! @{ */

#define CRC_GPOLYHL_GPOLYHL_MASK                 (0xFFU)
#define CRC_GPOLYHL_GPOLYHL_SHIFT                (0U)
#define CRC_GPOLYHL_GPOLYHL(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK)
/*! @} */

/*! @name GPOLYHU - CRC_GPOLYHU register */
/*! @{ */

#define CRC_GPOLYHU_GPOLYHU_MASK                 (0xFFU)
#define CRC_GPOLYHU_GPOLYHU_SHIFT                (0U)
#define CRC_GPOLYHU_GPOLYHU(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK)
/*! @} */

/*! @name GPOLYL - CRC_GPOLYL register */
/*! @{ */

#define CRC_GPOLYL_GPOLYL_MASK                   (0xFFFFU)
#define CRC_GPOLYL_GPOLYL_SHIFT                  (0U)
#define CRC_GPOLYL_GPOLYL(x)                     (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK)
/*! @} */

/*! @name GPOLYH - CRC_GPOLYH register */
/*! @{ */

#define CRC_GPOLYH_GPOLYH_MASK                   (0xFFFFU)
#define CRC_GPOLYH_GPOLYH_SHIFT                  (0U)
#define CRC_GPOLYH_GPOLYH(x)                     (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK)
/*! @} */

/*! @name GPOLY - CRC Polynomial register */
/*! @{ */

#define CRC_GPOLY_LOW_MASK                       (0xFFFFU)
#define CRC_GPOLY_LOW_SHIFT                      (0U)
/*! LOW - Low Polynominal Half-word
 */
#define CRC_GPOLY_LOW(x)                         (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK)

#define CRC_GPOLY_HIGH_MASK                      (0xFFFF0000U)
#define CRC_GPOLY_HIGH_SHIFT                     (16U)
/*! HIGH - High Polynominal Half-word
 */
#define CRC_GPOLY_HIGH(x)                        (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK)
/*! @} */

/*! @name CTRLHU - CRC_CTRLHU register */
/*! @{ */

#define CRC_CTRLHU_TCRC_MASK                     (0x1U)
#define CRC_CTRLHU_TCRC_SHIFT                    (0U)
/*! TCRC - TCRC
 *  0b0..16-bit CRC protocol.
 *  0b1..32-bit CRC protocol.
 */
#define CRC_CTRLHU_TCRC(x)                       (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK)

#define CRC_CTRLHU_WAS_MASK                      (0x2U)
#define CRC_CTRLHU_WAS_SHIFT                     (1U)
/*! WAS - Write CRC DATA register As Seed
 *  0b0..Writes to the CRC DATA register are data values.
 *  0b1..Writes to the CRC DATA register are seed values.
 */
#define CRC_CTRLHU_WAS(x)                        (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK)

#define CRC_CTRLHU_FXOR_MASK                     (0x4U)
#define CRC_CTRLHU_FXOR_SHIFT                    (2U)
/*! FXOR - Complement Read Of CRC DATA register
 *  0b0..No XOR on reading.
 *  0b1..Invert or complement the read value of the CRC DATA register.
 */
#define CRC_CTRLHU_FXOR(x)                       (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK)

#define CRC_CTRLHU_TOTR_MASK                     (0x30U)
#define CRC_CTRLHU_TOTR_SHIFT                    (4U)
/*! TOTR - Type Of Transpose For Read
 *  0b00..No transposition.
 *  0b01..Bits in bytes are transposed; bytes are not transposed.
 *  0b10..Both bits in bytes and bytes are transposed.
 *  0b11..Only bytes are transposed; no bits in a byte are transposed.
 */
#define CRC_CTRLHU_TOTR(x)                       (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK)

#define CRC_CTRLHU_TOT_MASK                      (0xC0U)
#define CRC_CTRLHU_TOT_SHIFT                     (6U)
/*! TOT - Type Of Transpose For Writes
 *  0b00..No transposition.
 *  0b01..Bits in bytes are transposed; bytes are not transposed.
 *  0b10..Both bits in bytes and bytes are transposed.
 *  0b11..Only bytes are transposed; no bits in a byte are transposed.
 */
#define CRC_CTRLHU_TOT(x)                        (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK)
/*! @} */

/*! @name CTRL - CRC Control register */
/*! @{ */

#define CRC_CTRL_TCRC_MASK                       (0x1000000U)
#define CRC_CTRL_TCRC_SHIFT                      (24U)
/*! TCRC - TCRC
 *  0b0..16-bit CRC protocol.
 *  0b1..32-bit CRC protocol.
 */
#define CRC_CTRL_TCRC(x)                         (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK)

#define CRC_CTRL_WAS_MASK                        (0x2000000U)
#define CRC_CTRL_WAS_SHIFT                       (25U)
/*! WAS - Write CRC DATA register As Seed
 *  0b0..Writes to the CRC DATA register are data values.
 *  0b1..Writes to the CRC DATA register are seed values.
 */
#define CRC_CTRL_WAS(x)                          (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK)

#define CRC_CTRL_FXOR_MASK                       (0x4000000U)
#define CRC_CTRL_FXOR_SHIFT                      (26U)
/*! FXOR - Complement Read Of CRC DATA register
 *  0b0..No XOR on reading.
 *  0b1..Invert or complement the read value of the CRC DATA register.
 */
#define CRC_CTRL_FXOR(x)                         (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK)

#define CRC_CTRL_TOTR_MASK                       (0x30000000U)
#define CRC_CTRL_TOTR_SHIFT                      (28U)
/*! TOTR - Type Of Transpose For Read
 *  0b00..No transposition.
 *  0b01..Bits in bytes are transposed; bytes are not transposed.
 *  0b10..Both bits in bytes and bytes are transposed.
 *  0b11..Only bytes are transposed; no bits in a byte are transposed.
 */
#define CRC_CTRL_TOTR(x)                         (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK)

#define CRC_CTRL_TOT_MASK                        (0xC0000000U)
#define CRC_CTRL_TOT_SHIFT                       (30U)
/*! TOT - Type Of Transpose For Writes
 *  0b00..No transposition.
 *  0b01..Bits in bytes are transposed; bytes are not transposed.
 *  0b10..Both bits in bytes and bytes are transposed.
 *  0b11..Only bytes are transposed; no bits in a byte are transposed.
 */
#define CRC_CTRL_TOT(x)                          (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group CRC_Register_Masks */


/* CRC - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral CRC0 base address */
  #define CRC0_BASE                                (0x50023000u)
  /** Peripheral CRC0 base address */
  #define CRC0_BASE_NS                             (0x40023000u)
  /** Peripheral CRC0 base pointer */
  #define CRC0                                     ((CRC_Type *)CRC0_BASE)
  /** Peripheral CRC0 base pointer */
  #define CRC0_NS                                  ((CRC_Type *)CRC0_BASE_NS)
  /** Array initializer of CRC peripheral base addresses */
  #define CRC_BASE_ADDRS                           { CRC0_BASE }
  /** Array initializer of CRC peripheral base pointers */
  #define CRC_BASE_PTRS                            { CRC0 }
  /** Array initializer of CRC peripheral base addresses */
  #define CRC_BASE_ADDRS_NS                        { CRC0_BASE_NS }
  /** Array initializer of CRC peripheral base pointers */
  #define CRC_BASE_PTRS_NS                         { CRC0_NS }
#else
  /** Peripheral CRC0 base address */
  #define CRC0_BASE                                (0x40023000u)
  /** Peripheral CRC0 base pointer */
  #define CRC0                                     ((CRC_Type *)CRC0_BASE)
  /** Array initializer of CRC peripheral base addresses */
  #define CRC_BASE_ADDRS                           { CRC0_BASE }
  /** Array initializer of CRC peripheral base pointers */
  #define CRC_BASE_PTRS                            { CRC0 }
#endif

/*!
 * @}
 */ /* end of group CRC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DMA Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
 * @{
 */

/** DMA - Register Layout Typedef */
typedef struct {
  __IO uint32_t MP_CSR;                            /**< Management Page Control, offset: 0x0 */
  __I  uint32_t MP_ES;                             /**< Management Page Error Status, offset: 0x4 */
  __I  uint32_t MP_INT;                            /**< Management Page Interrupt Request Status, offset: 0x8 */
  __I  uint32_t MP_HRS;                            /**< Management Page Hardware Request Status, offset: 0xC */
       uint8_t RESERVED_0[240];
  __IO uint32_t CH_GRPRI[16];                      /**< Channel Arbitration Group, array offset: 0x100, array step: 0x4 */
       uint8_t RESERVED_1[3776];
  struct {                                         /* offset: 0x1000, array step: 0x1000 */
    __IO uint32_t CH_CSR;                            /**< Channel Control and Status, array offset: 0x1000, array step: 0x1000 */
    __IO uint32_t CH_ES;                             /**< Channel Error Status, array offset: 0x1004, array step: 0x1000 */
    __IO uint32_t CH_INT;                            /**< Channel Interrupt Status, array offset: 0x1008, array step: 0x1000 */
    __IO uint32_t CH_SBR;                            /**< Channel System Bus, array offset: 0x100C, array step: 0x1000 */
    __IO uint32_t CH_PRI;                            /**< Channel Priority, array offset: 0x1010, array step: 0x1000 */
    __IO uint32_t CH_MUX;                            /**< Channel Multiplexor Configuration, array offset: 0x1014, array step: 0x1000 */
         uint8_t RESERVED_0[8];
    __IO uint32_t TCD_SADDR;                         /**< TCD Source Address, array offset: 0x1020, array step: 0x1000 */
    __IO uint16_t TCD_SOFF;                          /**< TCD Signed Source Address Offset, array offset: 0x1024, array step: 0x1000 */
    __IO uint16_t TCD_ATTR;                          /**< TCD Transfer Attributes, array offset: 0x1026, array step: 0x1000 */
    union {                                          /* offset: 0x1028, array step: 0x1000 */
      __IO uint32_t TCD_NBYTES_MLOFFNO;                /**< TCD Transfer Size Without Minor Loop Offsets, array offset: 0x1028, array step: 0x1000 */
      __IO uint32_t TCD_NBYTES_MLOFFYES;               /**< TCD Transfer Size with Minor Loop Offsets, array offset: 0x1028, array step: 0x1000 */
    };
    __IO uint32_t TCD_SLAST_SDA;                     /**< TCD Last Source Address Adjustment / Store DADDR Address, array offset: 0x102C, array step: 0x1000 */
    __IO uint32_t TCD_DADDR;                         /**< TCD Destination Address, array offset: 0x1030, array step: 0x1000 */
    __IO uint16_t TCD_DOFF;                          /**< TCD Signed Destination Address Offset, array offset: 0x1034, array step: 0x1000 */
    union {                                          /* offset: 0x1036, array step: 0x1000 */
      __IO uint16_t TCD_CITER_ELINKNO;                 /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), array offset: 0x1036, array step: 0x1000 */
      __IO uint16_t TCD_CITER_ELINKYES;                /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), array offset: 0x1036, array step: 0x1000 */
    };
    __IO uint32_t TCD_DLAST_SGA;                     /**< TCD Last Destination Address Adjustment / Scatter Gather Address, array offset: 0x1038, array step: 0x1000 */
    __IO uint16_t TCD_CSR;                           /**< TCD Control and Status, array offset: 0x103C, array step: 0x1000 */
    union {                                          /* offset: 0x103E, array step: 0x1000 */
      __IO uint16_t TCD_BITER_ELINKNO;                 /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), array offset: 0x103E, array step: 0x1000 */
      __IO uint16_t TCD_BITER_ELINKYES;                /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), array offset: 0x103E, array step: 0x1000 */
    };
         uint8_t RESERVED_1[4032];
  } CH[16];
} DMA_Type;

/* ----------------------------------------------------------------------------
   -- DMA Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_Register_Masks DMA Register Masks
 * @{
 */

/*! @name MP_CSR - Management Page Control */
/*! @{ */

#define DMA_MP_CSR_EDBG_MASK                     (0x2U)
#define DMA_MP_CSR_EDBG_SHIFT                    (1U)
/*! EDBG - Enable Debug
 *  0b0..Debug mode disabled
 *  0b1..Debug mode is enabled.
 */
#define DMA_MP_CSR_EDBG(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_EDBG_SHIFT)) & DMA_MP_CSR_EDBG_MASK)

#define DMA_MP_CSR_ERCA_MASK                     (0x4U)
#define DMA_MP_CSR_ERCA_SHIFT                    (2U)
/*! ERCA - Enable Round Robin Channel Arbitration
 *  0b0..Round-robin channel arbitration disabled
 *  0b1..Round-robin channel arbitration enabled
 */
#define DMA_MP_CSR_ERCA(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ERCA_SHIFT)) & DMA_MP_CSR_ERCA_MASK)

#define DMA_MP_CSR_HAE_MASK                      (0x10U)
#define DMA_MP_CSR_HAE_SHIFT                     (4U)
/*! HAE - Halt After Error
 *  0b0..Normal operation
 *  0b1..Any error causes the HALT field to be set to 1
 */
#define DMA_MP_CSR_HAE(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_HAE_SHIFT)) & DMA_MP_CSR_HAE_MASK)

#define DMA_MP_CSR_HALT_MASK                     (0x20U)
#define DMA_MP_CSR_HALT_SHIFT                    (5U)
/*! HALT - Halt DMA Operations
 *  0b0..Normal operation
 *  0b1..Stall the start of any new channels
 */
#define DMA_MP_CSR_HALT(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_HALT_SHIFT)) & DMA_MP_CSR_HALT_MASK)

#define DMA_MP_CSR_GCLC_MASK                     (0x40U)
#define DMA_MP_CSR_GCLC_SHIFT                    (6U)
/*! GCLC - Global Channel Linking Control
 *  0b0..Channel linking disabled for all channels
 *  0b1..Channel linking available and controlled by each channel's link settings
 */
#define DMA_MP_CSR_GCLC(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_GCLC_SHIFT)) & DMA_MP_CSR_GCLC_MASK)

#define DMA_MP_CSR_GMRC_MASK                     (0x80U)
#define DMA_MP_CSR_GMRC_SHIFT                    (7U)
/*! GMRC - Global Master ID Replication Control
 *  0b0..Master ID replication disabled for all channels
 *  0b1..Master ID replication available and controlled by each channel's CHn_SBR[EMI] setting
 */
#define DMA_MP_CSR_GMRC(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_GMRC_SHIFT)) & DMA_MP_CSR_GMRC_MASK)

#define DMA_MP_CSR_ECX_MASK                      (0x100U)
#define DMA_MP_CSR_ECX_SHIFT                     (8U)
/*! ECX - Cancel Transfer With Error
 *  0b0..Normal operation
 *  0b1..Cancel the remaining data transfer
 */
#define DMA_MP_CSR_ECX(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ECX_SHIFT)) & DMA_MP_CSR_ECX_MASK)

#define DMA_MP_CSR_CX_MASK                       (0x200U)
#define DMA_MP_CSR_CX_SHIFT                      (9U)
/*! CX - Cancel Transfer
 *  0b0..Normal operation
 *  0b1..Cancel the remaining data transfer
 */
#define DMA_MP_CSR_CX(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_CX_SHIFT)) & DMA_MP_CSR_CX_MASK)

#define DMA_MP_CSR_ACTIVE_ID_MASK                (0xF000000U)
#define DMA_MP_CSR_ACTIVE_ID_SHIFT               (24U)
/*! ACTIVE_ID - Active Channel ID
 */
#define DMA_MP_CSR_ACTIVE_ID(x)                  (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ACTIVE_ID_SHIFT)) & DMA_MP_CSR_ACTIVE_ID_MASK)

#define DMA_MP_CSR_ACTIVE_MASK                   (0x80000000U)
#define DMA_MP_CSR_ACTIVE_SHIFT                  (31U)
/*! ACTIVE - DMA Active Status
 *  0b0..eDMA is idle
 *  0b1..eDMA is executing a channel
 */
#define DMA_MP_CSR_ACTIVE(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ACTIVE_SHIFT)) & DMA_MP_CSR_ACTIVE_MASK)
/*! @} */

/*! @name MP_ES - Management Page Error Status */
/*! @{ */

#define DMA_MP_ES_DBE_MASK                       (0x1U)
#define DMA_MP_ES_DBE_SHIFT                      (0U)
/*! DBE - Destination Bus Error
 *  0b0..No destination bus error
 *  0b1..Last recorded error was a bus error on a destination write
 */
#define DMA_MP_ES_DBE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DBE_SHIFT)) & DMA_MP_ES_DBE_MASK)

#define DMA_MP_ES_SBE_MASK                       (0x2U)
#define DMA_MP_ES_SBE_SHIFT                      (1U)
/*! SBE - Source Bus Error
 *  0b0..No source bus error
 *  0b1..Last recorded error was a bus error on a source read
 */
#define DMA_MP_ES_SBE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SBE_SHIFT)) & DMA_MP_ES_SBE_MASK)

#define DMA_MP_ES_SGE_MASK                       (0x4U)
#define DMA_MP_ES_SGE_SHIFT                      (2U)
/*! SGE - Scatter/Gather Configuration Error
 *  0b0..No scatter/gather configuration error
 *  0b1..Last recorded error was a configuration error detected in the TCDn_DLAST_SGA field
 */
#define DMA_MP_ES_SGE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SGE_SHIFT)) & DMA_MP_ES_SGE_MASK)

#define DMA_MP_ES_NCE_MASK                       (0x8U)
#define DMA_MP_ES_NCE_SHIFT                      (3U)
/*! NCE - NBYTES/CITER Configuration Error
 *  0b0..No NBYTES/CITER configuration error
 *  0b1..The last recorded error was NBYTES equal to zero or a CITER not equal to BITER error
 */
#define DMA_MP_ES_NCE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_NCE_SHIFT)) & DMA_MP_ES_NCE_MASK)

#define DMA_MP_ES_DOE_MASK                       (0x10U)
#define DMA_MP_ES_DOE_SHIFT                      (4U)
/*! DOE - Destination Offset Error
 *  0b0..No destination offset configuration error
 *  0b1..Last recorded error was a configuration error detected in the TCDn_DOFF field
 */
#define DMA_MP_ES_DOE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DOE_SHIFT)) & DMA_MP_ES_DOE_MASK)

#define DMA_MP_ES_DAE_MASK                       (0x20U)
#define DMA_MP_ES_DAE_SHIFT                      (5U)
/*! DAE - Destination Address Error
 *  0b0..No destination address configuration error
 *  0b1..Last recorded error was a configuration error detected in the TCDn_DADDR field
 */
#define DMA_MP_ES_DAE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DAE_SHIFT)) & DMA_MP_ES_DAE_MASK)

#define DMA_MP_ES_SOE_MASK                       (0x40U)
#define DMA_MP_ES_SOE_SHIFT                      (6U)
/*! SOE - Source Offset Error
 *  0b0..No source offset configuration error
 *  0b1..Last recorded error was a configuration error detected in the TCDn_SOFF field
 */
#define DMA_MP_ES_SOE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SOE_SHIFT)) & DMA_MP_ES_SOE_MASK)

#define DMA_MP_ES_SAE_MASK                       (0x80U)
#define DMA_MP_ES_SAE_SHIFT                      (7U)
/*! SAE - Source Address Error
 *  0b0..No source address configuration error
 *  0b1..Last recorded error was a configuration error detected in the TCDn_SADDR field
 */
#define DMA_MP_ES_SAE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SAE_SHIFT)) & DMA_MP_ES_SAE_MASK)

#define DMA_MP_ES_ECX_MASK                       (0x100U)
#define DMA_MP_ES_ECX_SHIFT                      (8U)
/*! ECX - Transfer Canceled
 *  0b0..No canceled transfers
 *  0b1..Last recorded entry was a canceled transfer by the error cancel transfer input
 */
#define DMA_MP_ES_ECX(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_ECX_SHIFT)) & DMA_MP_ES_ECX_MASK)

#define DMA_MP_ES_ERRCHN_MASK                    (0xF000000U)
#define DMA_MP_ES_ERRCHN_SHIFT                   (24U)
/*! ERRCHN - Error Channel Number or Canceled Channel Number
 */
#define DMA_MP_ES_ERRCHN(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_ERRCHN_SHIFT)) & DMA_MP_ES_ERRCHN_MASK)

#define DMA_MP_ES_VLD_MASK                       (0x80000000U)
#define DMA_MP_ES_VLD_SHIFT                      (31U)
/*! VLD - Valid
 *  0b0..No ERR fields are set to 1
 *  0b1..At least one ERR field is set to 1, indicating a valid error exists that software has not cleared
 */
#define DMA_MP_ES_VLD(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_VLD_SHIFT)) & DMA_MP_ES_VLD_MASK)
/*! @} */

/*! @name MP_INT - Management Page Interrupt Request Status */
/*! @{ */

#define DMA_MP_INT_INT_MASK                      (0xFFFFU)
#define DMA_MP_INT_INT_SHIFT                     (0U)
/*! INT - Interrupt Request Status
 */
#define DMA_MP_INT_INT(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_MP_INT_INT_SHIFT)) & DMA_MP_INT_INT_MASK)
/*! @} */

/*! @name MP_HRS - Management Page Hardware Request Status */
/*! @{ */

#define DMA_MP_HRS_HRS_MASK                      (0xFFFFFFFFU)
#define DMA_MP_HRS_HRS_SHIFT                     (0U)
/*! HRS - Hardware Request Status
 */
#define DMA_MP_HRS_HRS(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_MP_HRS_HRS_SHIFT)) & DMA_MP_HRS_HRS_MASK)
/*! @} */

/*! @name CH_GRPRI - Channel Arbitration Group */
/*! @{ */

#define DMA_CH_GRPRI_GRPRI_MASK                  (0x1FU)
#define DMA_CH_GRPRI_GRPRI_SHIFT                 (0U)
/*! GRPRI - Arbitration Group For Channel n
 */
#define DMA_CH_GRPRI_GRPRI(x)                    (((uint32_t)(((uint32_t)(x)) << DMA_CH_GRPRI_GRPRI_SHIFT)) & DMA_CH_GRPRI_GRPRI_MASK)
/*! @} */

/* The count of DMA_CH_GRPRI */
#define DMA_CH_GRPRI_COUNT                       (16U)

/*! @name CH_CSR - Channel Control and Status */
/*! @{ */

#define DMA_CH_CSR_ERQ_MASK                      (0x1U)
#define DMA_CH_CSR_ERQ_SHIFT                     (0U)
/*! ERQ - Enable DMA Request
 *  0b0..DMA hardware request signal for corresponding channel disabled
 *  0b1..DMA hardware request signal for corresponding channel enabled
 */
#define DMA_CH_CSR_ERQ(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ERQ_SHIFT)) & DMA_CH_CSR_ERQ_MASK)

#define DMA_CH_CSR_EARQ_MASK                     (0x2U)
#define DMA_CH_CSR_EARQ_SHIFT                    (1U)
/*! EARQ - Enable Asynchronous DMA Request
 *  0b0..Disable asynchronous DMA request for the channel
 *  0b1..Enable asynchronous DMA request for the channel
 */
#define DMA_CH_CSR_EARQ(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EARQ_SHIFT)) & DMA_CH_CSR_EARQ_MASK)

#define DMA_CH_CSR_EEI_MASK                      (0x4U)
#define DMA_CH_CSR_EEI_SHIFT                     (2U)
/*! EEI - Enable Error Interrupt
 *  0b0..Error signal for corresponding channel does not generate error interrupt
 *  0b1..Assertion of error signal for corresponding channel generates error interrupt request
 */
#define DMA_CH_CSR_EEI(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EEI_SHIFT)) & DMA_CH_CSR_EEI_MASK)

#define DMA_CH_CSR_EBW_MASK                      (0x8U)
#define DMA_CH_CSR_EBW_SHIFT                     (3U)
/*! EBW - Enable Buffered Writes
 *  0b0..Buffered writes on system bus disabled
 *  0b1..Buffered writes on system bus enabled
 */
#define DMA_CH_CSR_EBW(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EBW_SHIFT)) & DMA_CH_CSR_EBW_MASK)

#define DMA_CH_CSR_DONE_MASK                     (0x40000000U)
#define DMA_CH_CSR_DONE_SHIFT                    (30U)
/*! DONE - Channel Done
 */
#define DMA_CH_CSR_DONE(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_DONE_SHIFT)) & DMA_CH_CSR_DONE_MASK)

#define DMA_CH_CSR_ACTIVE_MASK                   (0x80000000U)
#define DMA_CH_CSR_ACTIVE_SHIFT                  (31U)
/*! ACTIVE - Channel Active
 */
#define DMA_CH_CSR_ACTIVE(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ACTIVE_SHIFT)) & DMA_CH_CSR_ACTIVE_MASK)
/*! @} */

/* The count of DMA_CH_CSR */
#define DMA_CH_CSR_COUNT                         (16U)

/*! @name CH_ES - Channel Error Status */
/*! @{ */

#define DMA_CH_ES_DBE_MASK                       (0x1U)
#define DMA_CH_ES_DBE_SHIFT                      (0U)
/*! DBE - Destination Bus Error
 *  0b0..No destination bus error
 *  0b1..Last recorded error was bus error on destination write
 */
#define DMA_CH_ES_DBE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DBE_SHIFT)) & DMA_CH_ES_DBE_MASK)

#define DMA_CH_ES_SBE_MASK                       (0x2U)
#define DMA_CH_ES_SBE_SHIFT                      (1U)
/*! SBE - Source Bus Error
 *  0b0..No source bus error
 *  0b1..Last recorded error was bus error on source read
 */
#define DMA_CH_ES_SBE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SBE_SHIFT)) & DMA_CH_ES_SBE_MASK)

#define DMA_CH_ES_SGE_MASK                       (0x4U)
#define DMA_CH_ES_SGE_SHIFT                      (2U)
/*! SGE - Scatter/Gather Configuration Error
 *  0b0..No scatter/gather configuration error
 *  0b1..Last recorded error was a configuration error detected in the TCDn_DLAST_SGA field
 */
#define DMA_CH_ES_SGE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SGE_SHIFT)) & DMA_CH_ES_SGE_MASK)

#define DMA_CH_ES_NCE_MASK                       (0x8U)
#define DMA_CH_ES_NCE_SHIFT                      (3U)
/*! NCE - NBYTES/CITER Configuration Error
 *  0b0..No NBYTES/CITER configuration error
 *  0b1..Last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields
 */
#define DMA_CH_ES_NCE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_NCE_SHIFT)) & DMA_CH_ES_NCE_MASK)

#define DMA_CH_ES_DOE_MASK                       (0x10U)
#define DMA_CH_ES_DOE_SHIFT                      (4U)
/*! DOE - Destination Offset Error
 *  0b0..No destination offset configuration error
 *  0b1..Last recorded error was a configuration error detected in the TCDn_DOFF field
 */
#define DMA_CH_ES_DOE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DOE_SHIFT)) & DMA_CH_ES_DOE_MASK)

#define DMA_CH_ES_DAE_MASK                       (0x20U)
#define DMA_CH_ES_DAE_SHIFT                      (5U)
/*! DAE - Destination Address Error
 *  0b0..No destination address configuration error
 *  0b1..Last recorded error was a configuration error detected in the TCDn_DADDR field
 */
#define DMA_CH_ES_DAE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DAE_SHIFT)) & DMA_CH_ES_DAE_MASK)

#define DMA_CH_ES_SOE_MASK                       (0x40U)
#define DMA_CH_ES_SOE_SHIFT                      (6U)
/*! SOE - Source Offset Error
 *  0b0..No source offset configuration error
 *  0b1..Last recorded error was a configuration error detected in the TCDn_SOFF field
 */
#define DMA_CH_ES_SOE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SOE_SHIFT)) & DMA_CH_ES_SOE_MASK)

#define DMA_CH_ES_SAE_MASK                       (0x80U)
#define DMA_CH_ES_SAE_SHIFT                      (7U)
/*! SAE - Source Address Error
 *  0b0..No source address configuration error
 *  0b1..Last recorded error was a configuration error detected in the TCDn_SADDR field
 */
#define DMA_CH_ES_SAE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SAE_SHIFT)) & DMA_CH_ES_SAE_MASK)

#define DMA_CH_ES_ERR_MASK                       (0x80000000U)
#define DMA_CH_ES_ERR_SHIFT                      (31U)
/*! ERR - Error In Channel
 *  0b0..An error in this channel has not occurred
 *  0b1..An error in this channel has occurred
 */
#define DMA_CH_ES_ERR(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_ERR_SHIFT)) & DMA_CH_ES_ERR_MASK)
/*! @} */

/* The count of DMA_CH_ES */
#define DMA_CH_ES_COUNT                          (16U)

/*! @name CH_INT - Channel Interrupt Status */
/*! @{ */

#define DMA_CH_INT_INT_MASK                      (0x1U)
#define DMA_CH_INT_INT_SHIFT                     (0U)
/*! INT - Interrupt Request
 *  0b0..Interrupt request for corresponding channel cleared
 *  0b1..Interrupt request for corresponding channel active
 */
#define DMA_CH_INT_INT(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_INT_INT_SHIFT)) & DMA_CH_INT_INT_MASK)
/*! @} */

/* The count of DMA_CH_INT */
#define DMA_CH_INT_COUNT                         (16U)

/*! @name CH_SBR - Channel System Bus */
/*! @{ */

#define DMA_CH_SBR_MID_MASK                      (0x3FU)
#define DMA_CH_SBR_MID_SHIFT                     (0U)
/*! MID - Master ID
 */
#define DMA_CH_SBR_MID(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_MID_SHIFT)) & DMA_CH_SBR_MID_MASK)

#define DMA_CH_SBR_SEC_MASK                      (0x4000U)
#define DMA_CH_SBR_SEC_SHIFT                     (14U)
/*! SEC - Security Level
 *  0b0..Nonsecure protection level for DMA transfers
 *  0b1..Secure protection level for DMA transfers
 */
#define DMA_CH_SBR_SEC(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_SEC_SHIFT)) & DMA_CH_SBR_SEC_MASK)

#define DMA_CH_SBR_PAL_MASK                      (0x8000U)
#define DMA_CH_SBR_PAL_SHIFT                     (15U)
/*! PAL - Privileged Access Level
 *  0b0..User protection level for DMA transfers
 *  0b1..Privileged protection level for DMA transfers
 */
#define DMA_CH_SBR_PAL(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_PAL_SHIFT)) & DMA_CH_SBR_PAL_MASK)

#define DMA_CH_SBR_EMI_MASK                      (0x10000U)
#define DMA_CH_SBR_EMI_SHIFT                     (16U)
/*! EMI - Enable Master ID Replication
 *  0b0..Master ID replication is disabled
 *  0b1..Master ID replication is enabled
 */
#define DMA_CH_SBR_EMI(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_EMI_SHIFT)) & DMA_CH_SBR_EMI_MASK)

#define DMA_CH_SBR_ATTR_MASK                     (0x1E0000U)
#define DMA_CH_SBR_ATTR_SHIFT                    (17U)
/*! ATTR - Attribute Output
 */
#define DMA_CH_SBR_ATTR(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_ATTR_SHIFT)) & DMA_CH_SBR_ATTR_MASK)
/*! @} */

/* The count of DMA_CH_SBR */
#define DMA_CH_SBR_COUNT                         (16U)

/*! @name CH_PRI - Channel Priority */
/*! @{ */

#define DMA_CH_PRI_APL_MASK                      (0x7U)
#define DMA_CH_PRI_APL_SHIFT                     (0U)
/*! APL - Arbitration Priority Level
 */
#define DMA_CH_PRI_APL(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_APL_SHIFT)) & DMA_CH_PRI_APL_MASK)

#define DMA_CH_PRI_DPA_MASK                      (0x40000000U)
#define DMA_CH_PRI_DPA_SHIFT                     (30U)
/*! DPA - Disable Preempt Ability
 *  0b0..Channel can suspend a lower-priority channel
 *  0b1..Channel cannot suspend any other channel, regardless of channel priority
 */
#define DMA_CH_PRI_DPA(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_DPA_SHIFT)) & DMA_CH_PRI_DPA_MASK)

#define DMA_CH_PRI_ECP_MASK                      (0x80000000U)
#define DMA_CH_PRI_ECP_SHIFT                     (31U)
/*! ECP - Enable Channel Preemption
 *  0b0..Channel cannot be suspended by a higher-priority channel's service request
 *  0b1..Channel can be temporarily suspended by a higher-priority channel's service request
 */
#define DMA_CH_PRI_ECP(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_ECP_SHIFT)) & DMA_CH_PRI_ECP_MASK)
/*! @} */

/* The count of DMA_CH_PRI */
#define DMA_CH_PRI_COUNT                         (16U)

/*! @name CH_MUX - Channel Multiplexor Configuration */
/*! @{ */

#define DMA_CH_MUX_SRC_MASK                      (0x7FU)
#define DMA_CH_MUX_SRC_SHIFT                     (0U)
/*! SRC - Service Request Source
 */
#define DMA_CH_MUX_SRC(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CH_MUX_SRC_SHIFT)) & DMA_CH_MUX_SRC_MASK)
/*! @} */

/* The count of DMA_CH_MUX */
#define DMA_CH_MUX_COUNT                         (16U)

/*! @name TCD_SADDR - TCD Source Address */
/*! @{ */

#define DMA_TCD_SADDR_SADDR_MASK                 (0xFFFFFFFFU)
#define DMA_TCD_SADDR_SADDR_SHIFT                (0U)
/*! SADDR - Source Address
 */
#define DMA_TCD_SADDR_SADDR(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_TCD_SADDR_SADDR_SHIFT)) & DMA_TCD_SADDR_SADDR_MASK)
/*! @} */

/* The count of DMA_TCD_SADDR */
#define DMA_TCD_SADDR_COUNT                      (16U)

/*! @name TCD_SOFF - TCD Signed Source Address Offset */
/*! @{ */

#define DMA_TCD_SOFF_SOFF_MASK                   (0xFFFFU)
#define DMA_TCD_SOFF_SOFF_SHIFT                  (0U)
/*! SOFF - Source Address Signed Offset
 */
#define DMA_TCD_SOFF_SOFF(x)                     (((uint16_t)(((uint16_t)(x)) << DMA_TCD_SOFF_SOFF_SHIFT)) & DMA_TCD_SOFF_SOFF_MASK)
/*! @} */

/* The count of DMA_TCD_SOFF */
#define DMA_TCD_SOFF_COUNT                       (16U)

/*! @name TCD_ATTR - TCD Transfer Attributes */
/*! @{ */

#define DMA_TCD_ATTR_DSIZE_MASK                  (0x7U)
#define DMA_TCD_ATTR_DSIZE_SHIFT                 (0U)
/*! DSIZE - Destination Data Transfer Size
 */
#define DMA_TCD_ATTR_DSIZE(x)                    (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_DSIZE_SHIFT)) & DMA_TCD_ATTR_DSIZE_MASK)

#define DMA_TCD_ATTR_DMOD_MASK                   (0xF8U)
#define DMA_TCD_ATTR_DMOD_SHIFT                  (3U)
/*! DMOD - Destination Address Modulo
 */
#define DMA_TCD_ATTR_DMOD(x)                     (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_DMOD_SHIFT)) & DMA_TCD_ATTR_DMOD_MASK)

#define DMA_TCD_ATTR_SSIZE_MASK                  (0x700U)
#define DMA_TCD_ATTR_SSIZE_SHIFT                 (8U)
/*! SSIZE - Source Data Transfer Size
 *  0b000..8-bit
 *  0b001..16-bit
 *  0b010..32-bit
 *  0b011..64-bit
 *  0b100..16-byte
 *  0b101..32-byte
 *  0b110..
 *  0b111..
 */
#define DMA_TCD_ATTR_SSIZE(x)                    (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_SSIZE_SHIFT)) & DMA_TCD_ATTR_SSIZE_MASK)

#define DMA_TCD_ATTR_SMOD_MASK                   (0xF800U)
#define DMA_TCD_ATTR_SMOD_SHIFT                  (11U)
/*! SMOD - Source Address Modulo
 *  0b00000..Source address modulo feature disabled
 *  0b00001..Source address modulo feature enabled for any non-zero value [1-31]
 */
#define DMA_TCD_ATTR_SMOD(x)                     (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_SMOD_SHIFT)) & DMA_TCD_ATTR_SMOD_MASK)
/*! @} */

/* The count of DMA_TCD_ATTR */
#define DMA_TCD_ATTR_COUNT                       (16U)

/*! @name TCD_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */
/*! @{ */

#define DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK       (0x3FFFFFFFU)
#define DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT      (0U)
/*! NBYTES - Number of Bytes To Transfer Per Service Request
 */
#define DMA_TCD_NBYTES_MLOFFNO_NBYTES(x)         (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK)

#define DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK        (0x40000000U)
#define DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT       (30U)
/*! DMLOE - Destination Minor Loop Offset Enable
 *  0b0..Minor loop offset not applied to DADDR
 *  0b1..Minor loop offset applied to DADDR
 */
#define DMA_TCD_NBYTES_MLOFFNO_DMLOE(x)          (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK)

#define DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK        (0x80000000U)
#define DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT       (31U)
/*! SMLOE - Source Minor Loop Offset Enable
 *  0b0..Minor loop offset not applied to SADDR
 *  0b1..Minor loop offset applied to SADDR
 */
#define DMA_TCD_NBYTES_MLOFFNO_SMLOE(x)          (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK)
/*! @} */

/* The count of DMA_TCD_NBYTES_MLOFFNO */
#define DMA_TCD_NBYTES_MLOFFNO_COUNT             (16U)

/*! @name TCD_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */
/*! @{ */

#define DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK      (0x3FFU)
#define DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT     (0U)
/*! NBYTES - Number of Bytes To Transfer Per Service Request
 */
#define DMA_TCD_NBYTES_MLOFFYES_NBYTES(x)        (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK)

#define DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK       (0x3FFFFC00U)
#define DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT      (10U)
/*! MLOFF - Minor Loop Offset
 */
#define DMA_TCD_NBYTES_MLOFFYES_MLOFF(x)         (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK)

#define DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK       (0x40000000U)
#define DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT      (30U)
/*! DMLOE - Destination Minor Loop Offset Enable
 *  0b0..Minor loop offset not applied to DADDR
 *  0b1..Minor loop offset applied to DADDR
 */
#define DMA_TCD_NBYTES_MLOFFYES_DMLOE(x)         (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK)

#define DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK       (0x80000000U)
#define DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT      (31U)
/*! SMLOE - Source Minor Loop Offset Enable
 *  0b0..Minor loop offset not applied to SADDR
 *  0b1..Minor loop offset applied to SADDR
 */
#define DMA_TCD_NBYTES_MLOFFYES_SMLOE(x)         (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK)
/*! @} */

/* The count of DMA_TCD_NBYTES_MLOFFYES */
#define DMA_TCD_NBYTES_MLOFFYES_COUNT            (16U)

/*! @name TCD_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */
/*! @{ */

#define DMA_TCD_SLAST_SDA_SLAST_SDA_MASK         (0xFFFFFFFFU)
#define DMA_TCD_SLAST_SDA_SLAST_SDA_SHIFT        (0U)
/*! SLAST_SDA - Last Source Address Adjustment / Store DADDR Address
 */
#define DMA_TCD_SLAST_SDA_SLAST_SDA(x)           (((uint32_t)(((uint32_t)(x)) << DMA_TCD_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_SLAST_SDA_SLAST_SDA_MASK)
/*! @} */

/* The count of DMA_TCD_SLAST_SDA */
#define DMA_TCD_SLAST_SDA_COUNT                  (16U)

/*! @name TCD_DADDR - TCD Destination Address */
/*! @{ */

#define DMA_TCD_DADDR_DADDR_MASK                 (0xFFFFFFFFU)
#define DMA_TCD_DADDR_DADDR_SHIFT                (0U)
/*! DADDR - Destination Address
 */
#define DMA_TCD_DADDR_DADDR(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_TCD_DADDR_DADDR_SHIFT)) & DMA_TCD_DADDR_DADDR_MASK)
/*! @} */

/* The count of DMA_TCD_DADDR */
#define DMA_TCD_DADDR_COUNT                      (16U)

/*! @name TCD_DOFF - TCD Signed Destination Address Offset */
/*! @{ */

#define DMA_TCD_DOFF_DOFF_MASK                   (0xFFFFU)
#define DMA_TCD_DOFF_DOFF_SHIFT                  (0U)
/*! DOFF - Destination Address Signed Offset
 */
#define DMA_TCD_DOFF_DOFF(x)                     (((uint16_t)(((uint16_t)(x)) << DMA_TCD_DOFF_DOFF_SHIFT)) & DMA_TCD_DOFF_DOFF_MASK)
/*! @} */

/* The count of DMA_TCD_DOFF */
#define DMA_TCD_DOFF_COUNT                       (16U)

/*! @name TCD_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */
/*! @{ */

#define DMA_TCD_CITER_ELINKNO_CITER_MASK         (0x7FFFU)
#define DMA_TCD_CITER_ELINKNO_CITER_SHIFT        (0U)
/*! CITER - Current Major Iteration Count
 */
#define DMA_TCD_CITER_ELINKNO_CITER(x)           (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_CITER_ELINKNO_CITER_MASK)

#define DMA_TCD_CITER_ELINKNO_ELINK_MASK         (0x8000U)
#define DMA_TCD_CITER_ELINKNO_ELINK_SHIFT        (15U)
/*! ELINK - Enable Link
 *  0b0..Channel-to-channel linking disabled
 *  0b1..Channel-to-channel linking enabled
 */
#define DMA_TCD_CITER_ELINKNO_ELINK(x)           (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_CITER_ELINKNO_ELINK_MASK)
/*! @} */

/* The count of DMA_TCD_CITER_ELINKNO */
#define DMA_TCD_CITER_ELINKNO_COUNT              (16U)

/*! @name TCD_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */
/*! @{ */

#define DMA_TCD_CITER_ELINKYES_CITER_MASK        (0x1FFU)
#define DMA_TCD_CITER_ELINKYES_CITER_SHIFT       (0U)
/*! CITER - Current Major Iteration Count
 */
#define DMA_TCD_CITER_ELINKYES_CITER(x)          (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_CITER_ELINKYES_CITER_MASK)

#define DMA_TCD_CITER_ELINKYES_LINKCH_MASK       (0x1E00U)
#define DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT      (9U)
/*! LINKCH - Minor Loop Link Channel Number
 */
#define DMA_TCD_CITER_ELINKYES_LINKCH(x)         (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_CITER_ELINKYES_LINKCH_MASK)

#define DMA_TCD_CITER_ELINKYES_ELINK_MASK        (0x8000U)
#define DMA_TCD_CITER_ELINKYES_ELINK_SHIFT       (15U)
/*! ELINK - Enable Link
 *  0b0..Channel-to-channel linking disabled
 *  0b1..Channel-to-channel linking enabled
 */
#define DMA_TCD_CITER_ELINKYES_ELINK(x)          (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_CITER_ELINKYES_ELINK_MASK)
/*! @} */

/* The count of DMA_TCD_CITER_ELINKYES */
#define DMA_TCD_CITER_ELINKYES_COUNT             (16U)

/*! @name TCD_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */
/*! @{ */

#define DMA_TCD_DLAST_SGA_DLAST_SGA_MASK         (0xFFFFFFFFU)
#define DMA_TCD_DLAST_SGA_DLAST_SGA_SHIFT        (0U)
/*! DLAST_SGA - Last Destination Address Adjustment / Scatter Gather Address
 */
#define DMA_TCD_DLAST_SGA_DLAST_SGA(x)           (((uint32_t)(((uint32_t)(x)) << DMA_TCD_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_DLAST_SGA_DLAST_SGA_MASK)
/*! @} */

/* The count of DMA_TCD_DLAST_SGA */
#define DMA_TCD_DLAST_SGA_COUNT                  (16U)

/*! @name TCD_CSR - TCD Control and Status */
/*! @{ */

#define DMA_TCD_CSR_START_MASK                   (0x1U)
#define DMA_TCD_CSR_START_SHIFT                  (0U)
/*! START - Channel Start
 *  0b0..Channel not explicitly started
 *  0b1..Channel explicitly started via a software-initiated service request
 */
#define DMA_TCD_CSR_START(x)                     (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_START_SHIFT)) & DMA_TCD_CSR_START_MASK)

#define DMA_TCD_CSR_INTMAJOR_MASK                (0x2U)
#define DMA_TCD_CSR_INTMAJOR_SHIFT               (1U)
/*! INTMAJOR - Enable Interrupt If Major count complete
 *  0b0..End-of-major loop interrupt disabled
 *  0b1..End-of-major loop interrupt enabled
 */
#define DMA_TCD_CSR_INTMAJOR(x)                  (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_INTMAJOR_SHIFT)) & DMA_TCD_CSR_INTMAJOR_MASK)

#define DMA_TCD_CSR_INTHALF_MASK                 (0x4U)
#define DMA_TCD_CSR_INTHALF_SHIFT                (2U)
/*! INTHALF - Enable Interrupt If Major Counter Half-complete
 *  0b0..Halfway point interrupt disabled
 *  0b1..Halfway point interrupt enabled
 */
#define DMA_TCD_CSR_INTHALF(x)                   (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_INTHALF_SHIFT)) & DMA_TCD_CSR_INTHALF_MASK)

#define DMA_TCD_CSR_DREQ_MASK                    (0x8U)
#define DMA_TCD_CSR_DREQ_SHIFT                   (3U)
/*! DREQ - Disable Request
 *  0b0..No operation
 *  0b1..Clear the ERQ field to 0 upon major loop completion, thus disabling hardware service requests
 */
#define DMA_TCD_CSR_DREQ(x)                      (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_DREQ_SHIFT)) & DMA_TCD_CSR_DREQ_MASK)

#define DMA_TCD_CSR_ESG_MASK                     (0x10U)
#define DMA_TCD_CSR_ESG_SHIFT                    (4U)
/*! ESG - Enable Scatter/Gather Processing
 *  0b0..Current channel's TCD is normal format
 *  0b1..Current channel's TCD specifies scatter/gather format.
 */
#define DMA_TCD_CSR_ESG(x)                       (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_ESG_SHIFT)) & DMA_TCD_CSR_ESG_MASK)

#define DMA_TCD_CSR_MAJORELINK_MASK              (0x20U)
#define DMA_TCD_CSR_MAJORELINK_SHIFT             (5U)
/*! MAJORELINK - Enable Link When Major Loop Complete
 *  0b0..Channel-to-channel linking disabled
 *  0b1..Channel-to-channel linking enabled
 */
#define DMA_TCD_CSR_MAJORELINK(x)                (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_MAJORELINK_SHIFT)) & DMA_TCD_CSR_MAJORELINK_MASK)

#define DMA_TCD_CSR_EEOP_MASK                    (0x40U)
#define DMA_TCD_CSR_EEOP_SHIFT                   (6U)
/*! EEOP - Enable End-Of-Packet Processing
 *  0b0..End-of-packet operation disabled
 *  0b1..End-of-packet hardware input signal enabled
 */
#define DMA_TCD_CSR_EEOP(x)                      (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_EEOP_SHIFT)) & DMA_TCD_CSR_EEOP_MASK)

#define DMA_TCD_CSR_ESDA_MASK                    (0x80U)
#define DMA_TCD_CSR_ESDA_SHIFT                   (7U)
/*! ESDA - Enable Store Destination Address
 *  0b0..Ability to store destination address to system memory disabled
 *  0b1..Ability to store destination address to system memory enabled
 */
#define DMA_TCD_CSR_ESDA(x)                      (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_ESDA_SHIFT)) & DMA_TCD_CSR_ESDA_MASK)

#define DMA_TCD_CSR_MAJORLINKCH_MASK             (0xF00U)
#define DMA_TCD_CSR_MAJORLINKCH_SHIFT            (8U)
/*! MAJORLINKCH - Major Loop Link Channel Number
 */
#define DMA_TCD_CSR_MAJORLINKCH(x)               (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_CSR_MAJORLINKCH_MASK)

#define DMA_TCD_CSR_BWC_MASK                     (0xC000U)
#define DMA_TCD_CSR_BWC_SHIFT                    (14U)
/*! BWC - Bandwidth Control
 *  0b00..No eDMA engine stalls
 *  0b01..
 *  0b10..eDMA engine stalls for 4 cycles after each R/W
 *  0b11..eDMA engine stalls for 8 cycles after each R/W
 */
#define DMA_TCD_CSR_BWC(x)                       (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_BWC_SHIFT)) & DMA_TCD_CSR_BWC_MASK)
/*! @} */

/* The count of DMA_TCD_CSR */
#define DMA_TCD_CSR_COUNT                        (16U)

/*! @name TCD_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */
/*! @{ */

#define DMA_TCD_BITER_ELINKNO_BITER_MASK         (0x7FFFU)
#define DMA_TCD_BITER_ELINKNO_BITER_SHIFT        (0U)
/*! BITER - Starting Major Iteration Count
 */
#define DMA_TCD_BITER_ELINKNO_BITER(x)           (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_BITER_ELINKNO_BITER_MASK)

#define DMA_TCD_BITER_ELINKNO_ELINK_MASK         (0x8000U)
#define DMA_TCD_BITER_ELINKNO_ELINK_SHIFT        (15U)
/*! ELINK - Enables Link
 *  0b0..Channel-to-channel linking disabled
 *  0b1..Channel-to-channel linking enabled
 */
#define DMA_TCD_BITER_ELINKNO_ELINK(x)           (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_BITER_ELINKNO_ELINK_MASK)
/*! @} */

/* The count of DMA_TCD_BITER_ELINKNO */
#define DMA_TCD_BITER_ELINKNO_COUNT              (16U)

/*! @name TCD_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */
/*! @{ */

#define DMA_TCD_BITER_ELINKYES_BITER_MASK        (0x1FFU)
#define DMA_TCD_BITER_ELINKYES_BITER_SHIFT       (0U)
/*! BITER - Starting Major Iteration Count
 */
#define DMA_TCD_BITER_ELINKYES_BITER(x)          (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_BITER_ELINKYES_BITER_MASK)

#define DMA_TCD_BITER_ELINKYES_LINKCH_MASK       (0x1E00U)
#define DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT      (9U)
/*! LINKCH - Link Channel Number
 */
#define DMA_TCD_BITER_ELINKYES_LINKCH(x)         (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_BITER_ELINKYES_LINKCH_MASK)

#define DMA_TCD_BITER_ELINKYES_ELINK_MASK        (0x8000U)
#define DMA_TCD_BITER_ELINKYES_ELINK_SHIFT       (15U)
/*! ELINK - Enable Link
 *  0b0..Channel-to-channel linking disabled
 *  0b1..Channel-to-channel linking enabled
 */
#define DMA_TCD_BITER_ELINKYES_ELINK(x)          (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_BITER_ELINKYES_ELINK_MASK)
/*! @} */

/* The count of DMA_TCD_BITER_ELINKYES */
#define DMA_TCD_BITER_ELINKYES_COUNT             (16U)


/*!
 * @}
 */ /* end of group DMA_Register_Masks */


/* DMA - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral DMA0 base address */
  #define DMA0_BASE                                (0x50002000u)
  /** Peripheral DMA0 base address */
  #define DMA0_BASE_NS                             (0x40002000u)
  /** Peripheral DMA0 base pointer */
  #define DMA0                                     ((DMA_Type *)DMA0_BASE)
  /** Peripheral DMA0 base pointer */
  #define DMA0_NS                                  ((DMA_Type *)DMA0_BASE_NS)
  /** Array initializer of DMA peripheral base addresses */
  #define DMA_BASE_ADDRS                           { DMA0_BASE }
  /** Array initializer of DMA peripheral base pointers */
  #define DMA_BASE_PTRS                            { DMA0 }
  /** Array initializer of DMA peripheral base addresses */
  #define DMA_BASE_ADDRS_NS                        { DMA0_BASE_NS }
  /** Array initializer of DMA peripheral base pointers */
  #define DMA_BASE_PTRS_NS                         { DMA0_NS }
#else
  /** Peripheral DMA0 base address */
  #define DMA0_BASE                                (0x40002000u)
  /** Peripheral DMA0 base pointer */
  #define DMA0                                     ((DMA_Type *)DMA0_BASE)
  /** Array initializer of DMA peripheral base addresses */
  #define DMA_BASE_ADDRS                           { DMA0_BASE }
  /** Array initializer of DMA peripheral base pointers */
  #define DMA_BASE_PTRS                            { DMA0 }
#endif
/** Interrupt vectors for the DMA peripheral type */
#define DMA_IRQS                                 { { DMA0_CH0_IRQn, DMA0_CH1_IRQn, DMA0_CH2_IRQn, DMA0_CH3_IRQn, DMA0_CH4_IRQn, DMA0_CH5_IRQn, DMA0_CH6_IRQn, DMA0_CH7_IRQn, DMA0_CH8_IRQn, DMA0_CH9_IRQn, DMA0_CH10_IRQn, DMA0_CH11_IRQn, DMA0_CH12_IRQn, DMA0_CH13_IRQn, DMA0_CH14_IRQn, DMA0_CH15_IRQn } }


/*!
 * @}
 */ /* end of group DMA_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DSB Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DSB_Peripheral_Access_Layer DSB Peripheral Access Layer
 * @{
 */

/** DSB - Register Layout Typedef */
typedef struct {
  __IO uint32_t CSR;                               /**< Control Register, offset: 0x0 */
  __IO uint32_t INT;                               /**< Interrupt Request Status Register, offset: 0x4 */
  __IO uint32_t WMC;                               /**< Watermark Configuration Register, offset: 0x8 */
  __I  uint32_t RDATA;                             /**< FIFO Read Data Register, offset: 0xC */
  __IO uint32_t DADDR;                             /**< DMA Destination Address Register, offset: 0x10 */
  __IO uint32_t XCR;                               /**< DMA Transfer Count Register, offset: 0x14 */
} DSB_Type;

/* ----------------------------------------------------------------------------
   -- DSB Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DSB_Register_Masks DSB Register Masks
 * @{
 */

/*! @name CSR - Control Register */
/*! @{ */

#define DSB_CSR_SFTRST_MASK                      (0x1U)
#define DSB_CSR_SFTRST_SHIFT                     (0U)
/*! SFTRST - Soft Reset
 *  0b0..No operation.
 *  0b1..Reset the data stream buffer.
 */
#define DSB_CSR_SFTRST(x)                        (((uint32_t)(((uint32_t)(x)) << DSB_CSR_SFTRST_SHIFT)) & DSB_CSR_SFTRST_MASK)

#define DSB_CSR_DSB_EN_MASK                      (0x2U)
#define DSB_CSR_DSB_EN_SHIFT                     (1U)
/*! DSB_EN - Data Stream Buffer Enable
 *  0b0..Buffer is disabled.
 *  0b1..Buffer is enabled.
 */
#define DSB_CSR_DSB_EN(x)                        (((uint32_t)(((uint32_t)(x)) << DSB_CSR_DSB_EN_SHIFT)) & DSB_CSR_DSB_EN_MASK)

#define DSB_CSR_DMA_EN_MASK                      (0x4U)
#define DSB_CSR_DMA_EN_SHIFT                     (2U)
/*! DMA_EN - DMA Transfer Enable
 *  0b0..DMA transfers are disabled.
 *  0b1..DMA transfers are enabled.
 */
#define DSB_CSR_DMA_EN(x)                        (((uint32_t)(((uint32_t)(x)) << DSB_CSR_DMA_EN_SHIFT)) & DSB_CSR_DMA_EN_MASK)

#define DSB_CSR_INT_EN_MASK                      (0x8U)
#define DSB_CSR_INT_EN_SHIFT                     (3U)
/*! INT_EN - Interrupt Request Enable
 *  0b0..Interrupt requests on data ready or DMA done are disabled.
 *  0b1..Interrupt requests on data ready or DMA done are enabled.
 */
#define DSB_CSR_INT_EN(x)                        (((uint32_t)(((uint32_t)(x)) << DSB_CSR_INT_EN_SHIFT)) & DSB_CSR_INT_EN_MASK)

#define DSB_CSR_ERR_EN_MASK                      (0x10U)
#define DSB_CSR_ERR_EN_SHIFT                     (4U)
/*! ERR_EN - Error Interrupt Request Enable
 *  0b0..Error interrupt requests on overflow, underrun, or bus error are disabled.
 *  0b1..Error interrupt requests on overflow, underrun, or bus error are enabled.
 */
#define DSB_CSR_ERR_EN(x)                        (((uint32_t)(((uint32_t)(x)) << DSB_CSR_ERR_EN_SHIFT)) & DSB_CSR_ERR_EN_MASK)

#define DSB_CSR_CBT_EN_MASK                      (0x20U)
#define DSB_CSR_CBT_EN_SHIFT                     (5U)
/*! CBT_EN - Continuous Burst Transfer Enable
 *  0b0..Continuous burst transfer mode is disabled.
 *  0b1..Continuous burst transfer mode is enabled.
 */
#define DSB_CSR_CBT_EN(x)                        (((uint32_t)(((uint32_t)(x)) << DSB_CSR_CBT_EN_SHIFT)) & DSB_CSR_CBT_EN_MASK)
/*! @} */

/*! @name INT - Interrupt Request Status Register */
/*! @{ */

#define DSB_INT_DRDY_MASK                        (0x1U)
#define DSB_INT_DRDY_SHIFT                       (0U)
/*! DRDY - Data Ready
 *  0b0..No data to read (watermark has not been reached)
 *  0b1..Data is ready to read (watermark has been reached)
 */
#define DSB_INT_DRDY(x)                          (((uint32_t)(((uint32_t)(x)) << DSB_INT_DRDY_SHIFT)) & DSB_INT_DRDY_MASK)

#define DSB_INT_OVRF_MASK                        (0x2U)
#define DSB_INT_OVRF_SHIFT                       (1U)
/*! OVRF - Overflow Error
 *  0b0..No overflow error
 *  0b1..The last recorded error is a buffer overflow
 */
#define DSB_INT_OVRF(x)                          (((uint32_t)(((uint32_t)(x)) << DSB_INT_OVRF_SHIFT)) & DSB_INT_OVRF_MASK)

#define DSB_INT_UNDR_MASK                        (0x4U)
#define DSB_INT_UNDR_SHIFT                       (2U)
/*! UNDR - Underrun Error
 *  0b0..No underrun error
 *  0b1..The last recorded error is an underrun on a read
 */
#define DSB_INT_UNDR(x)                          (((uint32_t)(((uint32_t)(x)) << DSB_INT_UNDR_SHIFT)) & DSB_INT_UNDR_MASK)

#define DSB_INT_DBE_MASK                         (0x8U)
#define DSB_INT_DBE_SHIFT                        (3U)
/*! DBE - Destination Bus Error
 *  0b0..No destination bus error
 *  0b1..The last recorded error is bus error on a write
 */
#define DSB_INT_DBE(x)                           (((uint32_t)(((uint32_t)(x)) << DSB_INT_DBE_SHIFT)) & DSB_INT_DBE_MASK)

#define DSB_INT_DONE_MASK                        (0x10U)
#define DSB_INT_DONE_SHIFT                       (4U)
/*! DONE - DMA Packet Transfer Complete
 *  0b0..Packet transfer not done; CCNT less than TCNT
 *  0b1..Packet transfer is done; TCNT 32-bit words transferred
 */
#define DSB_INT_DONE(x)                          (((uint32_t)(((uint32_t)(x)) << DSB_INT_DONE_SHIFT)) & DSB_INT_DONE_MASK)
/*! @} */

/*! @name WMC - Watermark Configuration Register */
/*! @{ */

#define DSB_WMC_WMRK_MASK                        (0xFU)
#define DSB_WMC_WMRK_SHIFT                       (0U)
/*! WMRK - Watermark
 */
#define DSB_WMC_WMRK(x)                          (((uint32_t)(((uint32_t)(x)) << DSB_WMC_WMRK_SHIFT)) & DSB_WMC_WMRK_MASK)

#define DSB_WMC_CNT_MASK                         (0x1F0000U)
#define DSB_WMC_CNT_SHIFT                        (16U)
/*! CNT - FIFO Count
 */
#define DSB_WMC_CNT(x)                           (((uint32_t)(((uint32_t)(x)) << DSB_WMC_CNT_SHIFT)) & DSB_WMC_CNT_MASK)

#define DSB_WMC_SIZE_MASK                        (0x1F000000U)
#define DSB_WMC_SIZE_SHIFT                       (24U)
/*! SIZE - FIFO size
 */
#define DSB_WMC_SIZE(x)                          (((uint32_t)(((uint32_t)(x)) << DSB_WMC_SIZE_SHIFT)) & DSB_WMC_SIZE_MASK)
/*! @} */

/*! @name RDATA - FIFO Read Data Register */
/*! @{ */

#define DSB_RDATA_DATA_MASK                      (0xFFFFFFFFU)
#define DSB_RDATA_DATA_SHIFT                     (0U)
/*! DATA - FIFO Data
 */
#define DSB_RDATA_DATA(x)                        (((uint32_t)(((uint32_t)(x)) << DSB_RDATA_DATA_SHIFT)) & DSB_RDATA_DATA_MASK)
/*! @} */

/*! @name DADDR - DMA Destination Address Register */
/*! @{ */

#define DSB_DADDR_DADDR_MASK                     (0xFFFFFFFFU)
#define DSB_DADDR_DADDR_SHIFT                    (0U)
/*! DADDR - Destination Address
 */
#define DSB_DADDR_DADDR(x)                       (((uint32_t)(((uint32_t)(x)) << DSB_DADDR_DADDR_SHIFT)) & DSB_DADDR_DADDR_MASK)
/*! @} */

/*! @name XCR - DMA Transfer Count Register */
/*! @{ */

#define DSB_XCR_TCNT_MASK                        (0xFFFFU)
#define DSB_XCR_TCNT_SHIFT                       (0U)
/*! TCNT - Total Transfer Count
 */
#define DSB_XCR_TCNT(x)                          (((uint32_t)(((uint32_t)(x)) << DSB_XCR_TCNT_SHIFT)) & DSB_XCR_TCNT_MASK)

#define DSB_XCR_CCNT_MASK                        (0xFFFF0000U)
#define DSB_XCR_CCNT_SHIFT                       (16U)
/*! CCNT - Current Transfer Count
 */
#define DSB_XCR_CCNT(x)                          (((uint32_t)(((uint32_t)(x)) << DSB_XCR_CCNT_SHIFT)) & DSB_XCR_CCNT_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group DSB_Register_Masks */


/* DSB - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral DSB0 base address */
  #define DSB0_BASE                                (0x50041000u)
  /** Peripheral DSB0 base address */
  #define DSB0_BASE_NS                             (0x40041000u)
  /** Peripheral DSB0 base pointer */
  #define DSB0                                     ((DSB_Type *)DSB0_BASE)
  /** Peripheral DSB0 base pointer */
  #define DSB0_NS                                  ((DSB_Type *)DSB0_BASE_NS)
  /** Array initializer of DSB peripheral base addresses */
  #define DSB_BASE_ADDRS                           { DSB0_BASE }
  /** Array initializer of DSB peripheral base pointers */
  #define DSB_BASE_PTRS                            { DSB0 }
  /** Array initializer of DSB peripheral base addresses */
  #define DSB_BASE_ADDRS_NS                        { DSB0_BASE_NS }
  /** Array initializer of DSB peripheral base pointers */
  #define DSB_BASE_PTRS_NS                         { DSB0_NS }
#else
  /** Peripheral DSB0 base address */
  #define DSB0_BASE                                (0x40041000u)
  /** Peripheral DSB0 base pointer */
  #define DSB0                                     ((DSB_Type *)DSB0_BASE)
  /** Array initializer of DSB peripheral base addresses */
  #define DSB_BASE_ADDRS                           { DSB0_BASE }
  /** Array initializer of DSB peripheral base pointers */
  #define DSB_BASE_PTRS                            { DSB0 }
#endif

/*!
 * @}
 */ /* end of group DSB_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- ELEMU Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup ELEMU_Peripheral_Access_Layer ELEMU Peripheral Access Layer
 * @{
 */

/** ELEMU - Register Layout Typedef */
typedef struct {
  __I  uint32_t VER;                               /**< Version ID Register, offset: 0x0 */
  __I  uint32_t PAR;                               /**< Parameter Register, offset: 0x4 */
       uint32_t UNUSED0;                           /**< Unused Register 0, offset: 0x8 */
  __I  uint32_t SR;                                /**< Status Register, offset: 0xC */
       uint8_t RESERVED_0[272];
  __IO uint32_t TCR;                               /**< Transmit Control Register, offset: 0x120 */
  __I  uint32_t TSR;                               /**< Transmit Status Register, offset: 0x124 */
       uint8_t RESERVED_1[4];
  __I  uint32_t RSR;                               /**< Receive Status Register, offset: 0x12C */
       uint8_t RESERVED_2[204];
  __IO uint32_t UNUSED1;                           /**< Unused Register 1, offset: 0x1FC */
  __O  uint32_t TR[16];                            /**< Transmit Register, array offset: 0x200, array step: 0x4 */
       uint8_t RESERVED_3[64];
  __I  uint32_t RR[2];                             /**< Receive Register, array offset: 0x280, array step: 0x4 */
       uint8_t RESERVED_4[376];
  __I  uint32_t SEMA4_SR;                          /**< Semaphore Status Register, offset: 0x400 */
       uint8_t RESERVED_5[112];
  __I  uint32_t SEMA4_OWNR;                        /**< Semaphore Ownership Register, offset: 0x474 */
       uint8_t RESERVED_6[1312];
  __I  uint32_t SEMA4_ACQ;                         /**< Semaphore Acquire Register, offset: 0x998 */
       uint8_t RESERVED_7[304];
  __I  uint32_t SEMA4_REL;                         /**< Semaphore Release Register, offset: 0xACC */
       uint8_t RESERVED_8[212];
  __I  uint32_t SEMA4_FREL;                        /**< Semaphore Forced Release Register, offset: 0xBA4 */
} ELEMU_Type;

/* ----------------------------------------------------------------------------
   -- ELEMU Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup ELEMU_Register_Masks ELEMU Register Masks
 * @{
 */

/*! @name VER - Version ID Register */
/*! @{ */

#define ELEMU_VER_FEATURE_MASK                   (0xFFFFU)
#define ELEMU_VER_FEATURE_SHIFT                  (0U)
/*! FEATURE - Feature Set Number
 *  0b0000000000000000..Standard features are implemented.
 */
#define ELEMU_VER_FEATURE(x)                     (((uint32_t)(((uint32_t)(x)) << ELEMU_VER_FEATURE_SHIFT)) & ELEMU_VER_FEATURE_MASK)

#define ELEMU_VER_MINOR_MASK                     (0xFF0000U)
#define ELEMU_VER_MINOR_SHIFT                    (16U)
/*! MINOR - Minor Version Number (0x00 )
 */
#define ELEMU_VER_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << ELEMU_VER_MINOR_SHIFT)) & ELEMU_VER_MINOR_MASK)

#define ELEMU_VER_MAJOR_MASK                     (0xFF000000U)
#define ELEMU_VER_MAJOR_SHIFT                    (24U)
/*! MAJOR - Major Version Number (0x01 )
 */
#define ELEMU_VER_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << ELEMU_VER_MAJOR_SHIFT)) & ELEMU_VER_MAJOR_MASK)
/*! @} */

/*! @name PAR - Parameter Register */
/*! @{ */

#define ELEMU_PAR_TR_NUM_MASK                    (0xFFU)
#define ELEMU_PAR_TR_NUM_SHIFT                   (0U)
/*! TR_NUM - Number of Transmit (TRn) registers (8'd16)
 */
#define ELEMU_PAR_TR_NUM(x)                      (((uint32_t)(((uint32_t)(x)) << ELEMU_PAR_TR_NUM_SHIFT)) & ELEMU_PAR_TR_NUM_MASK)

#define ELEMU_PAR_RR_NUM_MASK                    (0xFF00U)
#define ELEMU_PAR_RR_NUM_SHIFT                   (8U)
/*! RR_NUM - Number of Receive (RRn) registers (8'd2)
 */
#define ELEMU_PAR_RR_NUM(x)                      (((uint32_t)(((uint32_t)(x)) << ELEMU_PAR_RR_NUM_SHIFT)) & ELEMU_PAR_RR_NUM_MASK)
/*! @} */

/*! @name SR - Status Register */
/*! @{ */

#define ELEMU_SR_TEP_MASK                        (0x20U)
#define ELEMU_SR_TEP_SHIFT                       (5U)
/*! TEP - Transmit Empty Pending
 */
#define ELEMU_SR_TEP(x)                          (((uint32_t)(((uint32_t)(x)) << ELEMU_SR_TEP_SHIFT)) & ELEMU_SR_TEP_MASK)

#define ELEMU_SR_RFP_MASK                        (0x40U)
#define ELEMU_SR_RFP_SHIFT                       (6U)
/*! RFP - Receive Full Pending Flag
 *  0b0..No data is ready to be read. All RSR[RFn] bits are clear.
 *  0b1..Data is ready to be read. One or more RSR[RFn] bits are set.
 */
#define ELEMU_SR_RFP(x)                          (((uint32_t)(((uint32_t)(x)) << ELEMU_SR_RFP_SHIFT)) & ELEMU_SR_RFP_MASK)
/*! @} */

/*! @name TCR - Transmit Control Register */
/*! @{ */

#define ELEMU_TCR_TEIEn_MASK                     (0xFFFFU)
#define ELEMU_TCR_TEIEn_SHIFT                    (0U)
/*! TEIEn - Transmit Register n Empty Interrupt Enable
 */
#define ELEMU_TCR_TEIEn(x)                       (((uint32_t)(((uint32_t)(x)) << ELEMU_TCR_TEIEn_SHIFT)) & ELEMU_TCR_TEIEn_MASK)
/*! @} */

/*! @name TSR - Transmit Status Register */
/*! @{ */

#define ELEMU_TSR_TEn_MASK                       (0xFFFFU)
#define ELEMU_TSR_TEn_SHIFT                      (0U)
/*! TEn - Transmit Register n Empty
 */
#define ELEMU_TSR_TEn(x)                         (((uint32_t)(((uint32_t)(x)) << ELEMU_TSR_TEn_SHIFT)) & ELEMU_TSR_TEn_MASK)
/*! @} */

/*! @name RSR - Receive Status Register */
/*! @{ */

#define ELEMU_RSR_RFn_MASK                       (0x3U)
#define ELEMU_RSR_RFn_SHIFT                      (0U)
/*! RFn - Receive Register n Full
 */
#define ELEMU_RSR_RFn(x)                         (((uint32_t)(((uint32_t)(x)) << ELEMU_RSR_RFn_SHIFT)) & ELEMU_RSR_RFn_MASK)
/*! @} */

/*! @name UNUSED1 - Unused Register 1 */
/*! @{ */

#define ELEMU_UNUSED1_DATA16_MASK                (0xFFFFU)
#define ELEMU_UNUSED1_DATA16_SHIFT               (0U)
/*! DATA16 - Unused 16-bit Register
 */
#define ELEMU_UNUSED1_DATA16(x)                  (((uint32_t)(((uint32_t)(x)) << ELEMU_UNUSED1_DATA16_SHIFT)) & ELEMU_UNUSED1_DATA16_MASK)
/*! @} */

/*! @name TR - Transmit Register */
/*! @{ */

#define ELEMU_TR_TR_DATA_MASK                    (0xFFFFFFFFU)
#define ELEMU_TR_TR_DATA_SHIFT                   (0U)
/*! TR_DATA - Transmit Data
 */
#define ELEMU_TR_TR_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << ELEMU_TR_TR_DATA_SHIFT)) & ELEMU_TR_TR_DATA_MASK)
/*! @} */

/* The count of ELEMU_TR */
#define ELEMU_TR_COUNT                           (16U)

/*! @name RR - Receive Register */
/*! @{ */

#define ELEMU_RR_RR_DATA_MASK                    (0xFFFFFFFFU)
#define ELEMU_RR_RR_DATA_SHIFT                   (0U)
/*! RR_DATA - Receive Data
 */
#define ELEMU_RR_RR_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << ELEMU_RR_RR_DATA_SHIFT)) & ELEMU_RR_RR_DATA_MASK)
/*! @} */

/* The count of ELEMU_RR */
#define ELEMU_RR_COUNT                           (2U)

/*! @name SEMA4_SR - Semaphore Status Register */
/*! @{ */

#define ELEMU_SEMA4_SR_OWNR16_MASK               (0xFFFFU)
#define ELEMU_SEMA4_SR_OWNR16_SHIFT              (0U)
/*! OWNR16 - Semaphore Owner
 */
#define ELEMU_SEMA4_SR_OWNR16(x)                 (((uint32_t)(((uint32_t)(x)) << ELEMU_SEMA4_SR_OWNR16_SHIFT)) & ELEMU_SEMA4_SR_OWNR16_MASK)

#define ELEMU_SEMA4_SR_SSS_CIP2_MASK             (0x10000U)
#define ELEMU_SEMA4_SR_SSS_CIP2_SHIFT            (16U)
/*! SSS_CIP2 - Security SubSystem (ELE) command group 2 in progress
 *  0b0..Service request group 2 not being processed by ELE
 *  0b1..Service request group 2 being processed by ELE
 */
#define ELEMU_SEMA4_SR_SSS_CIP2(x)               (((uint32_t)(((uint32_t)(x)) << ELEMU_SEMA4_SR_SSS_CIP2_SHIFT)) & ELEMU_SEMA4_SR_SSS_CIP2_MASK)

#define ELEMU_SEMA4_SR_SSS_CIP1_MASK             (0x20000U)
#define ELEMU_SEMA4_SR_SSS_CIP1_SHIFT            (17U)
/*! SSS_CIP1 - Security SubSystem (ELE) command group 1 in progress
 *  0b0..Service request group 1 not being processed by ELE
 *  0b1..Service request group 1 being processed by ELE
 */
#define ELEMU_SEMA4_SR_SSS_CIP1(x)               (((uint32_t)(((uint32_t)(x)) << ELEMU_SEMA4_SR_SSS_CIP1_SHIFT)) & ELEMU_SEMA4_SR_SSS_CIP1_MASK)

#define ELEMU_SEMA4_SR_SSS_LCK_MASK              (0x1000000U)
#define ELEMU_SEMA4_SR_SSS_LCK_SHIFT             (24U)
/*! SSS_LCK - Security SubSystem (ELE) lockup
 *  0b0..Edgelock enclave is not locked up
 *  0b1..Edgelock enclave is locked up in an unrecoverable state
 */
#define ELEMU_SEMA4_SR_SSS_LCK(x)                (((uint32_t)(((uint32_t)(x)) << ELEMU_SEMA4_SR_SSS_LCK_SHIFT)) & ELEMU_SEMA4_SR_SSS_LCK_MASK)

#define ELEMU_SEMA4_SR_MISC_BSY_MASK             (0x7E000000U)
#define ELEMU_SEMA4_SR_MISC_BSY_SHIFT            (25U)
/*! MISC_BSY - Miscellaneous ELE Busy Indicators
 */
#define ELEMU_SEMA4_SR_MISC_BSY(x)               (((uint32_t)(((uint32_t)(x)) << ELEMU_SEMA4_SR_MISC_BSY_SHIFT)) & ELEMU_SEMA4_SR_MISC_BSY_MASK)

#define ELEMU_SEMA4_SR_SSS_BSY_MASK              (0x80000000U)
#define ELEMU_SEMA4_SR_SSS_BSY_SHIFT             (31U)
/*! SSS_BSY - Security SubSystem (ELE) Busy
 *  0b0..Edgelock enclave is not busy
 *  0b1..Edgelock enclave CPU is busy
 */
#define ELEMU_SEMA4_SR_SSS_BSY(x)                (((uint32_t)(((uint32_t)(x)) << ELEMU_SEMA4_SR_SSS_BSY_SHIFT)) & ELEMU_SEMA4_SR_SSS_BSY_MASK)
/*! @} */

/*! @name SEMA4_OWNR - Semaphore Ownership Register */
/*! @{ */

#define ELEMU_SEMA4_OWNR_OWNR32_MASK             (0xFFFFFFFFU)
#define ELEMU_SEMA4_OWNR_OWNR32_SHIFT            (0U)
/*! OWNR32 - Semaphore Owner
 */
#define ELEMU_SEMA4_OWNR_OWNR32(x)               (((uint32_t)(((uint32_t)(x)) << ELEMU_SEMA4_OWNR_OWNR32_SHIFT)) & ELEMU_SEMA4_OWNR_OWNR32_MASK)
/*! @} */

/*! @name SEMA4_ACQ - Semaphore Acquire Register */
/*! @{ */

#define ELEMU_SEMA4_ACQ_OWNR32_MASK              (0xFFFFFFFFU)
#define ELEMU_SEMA4_ACQ_OWNR32_SHIFT             (0U)
/*! OWNR32 - Semaphore Owner
 */
#define ELEMU_SEMA4_ACQ_OWNR32(x)                (((uint32_t)(((uint32_t)(x)) << ELEMU_SEMA4_ACQ_OWNR32_SHIFT)) & ELEMU_SEMA4_ACQ_OWNR32_MASK)
/*! @} */

/*! @name SEMA4_REL - Semaphore Release Register */
/*! @{ */

#define ELEMU_SEMA4_REL_OWNR32_MASK              (0xFFFFFFFFU)
#define ELEMU_SEMA4_REL_OWNR32_SHIFT             (0U)
/*! OWNR32 - Semaphore Owner
 */
#define ELEMU_SEMA4_REL_OWNR32(x)                (((uint32_t)(((uint32_t)(x)) << ELEMU_SEMA4_REL_OWNR32_SHIFT)) & ELEMU_SEMA4_REL_OWNR32_MASK)
/*! @} */

/*! @name SEMA4_FREL - Semaphore Forced Release Register */
/*! @{ */

#define ELEMU_SEMA4_FREL_OWNR32_MASK             (0xFFFFFFFFU)
#define ELEMU_SEMA4_FREL_OWNR32_SHIFT            (0U)
/*! OWNR32 - Semaphore Owner
 */
#define ELEMU_SEMA4_FREL_OWNR32(x)               (((uint32_t)(((uint32_t)(x)) << ELEMU_SEMA4_FREL_OWNR32_SHIFT)) & ELEMU_SEMA4_FREL_OWNR32_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group ELEMU_Register_Masks */


/* ELEMU - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral ELEMUA base address */
  #define ELEMUA_BASE                              (0x50024000u)
  /** Peripheral ELEMUA base address */
  #define ELEMUA_BASE_NS                           (0x40024000u)
  /** Peripheral ELEMUA base pointer */
  #define ELEMUA                                   ((ELEMU_Type *)ELEMUA_BASE)
  /** Peripheral ELEMUA base pointer */
  #define ELEMUA_NS                                ((ELEMU_Type *)ELEMUA_BASE_NS)
  /** Array initializer of ELEMU peripheral base addresses */
  #define ELEMU_BASE_ADDRS                         { ELEMUA_BASE }
  /** Array initializer of ELEMU peripheral base pointers */
  #define ELEMU_BASE_PTRS                          { ELEMUA }
  /** Array initializer of ELEMU peripheral base addresses */
  #define ELEMU_BASE_ADDRS_NS                      { ELEMUA_BASE_NS }
  /** Array initializer of ELEMU peripheral base pointers */
  #define ELEMU_BASE_PTRS_NS                       { ELEMUA_NS }
#else
  /** Peripheral ELEMUA base address */
  #define ELEMUA_BASE                              (0x40024000u)
  /** Peripheral ELEMUA base pointer */
  #define ELEMUA                                   ((ELEMU_Type *)ELEMUA_BASE)
  /** Array initializer of ELEMU peripheral base addresses */
  #define ELEMU_BASE_ADDRS                         { ELEMUA_BASE }
  /** Array initializer of ELEMU peripheral base pointers */
  #define ELEMU_BASE_PTRS                          { ELEMUA }
#endif

/*!
 * @}
 */ /* end of group ELEMU_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- EWM Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
 * @{
 */

/** EWM - Register Layout Typedef */
typedef struct {
  __IO uint8_t CTRL;                               /**< Control Register, offset: 0x0 */
  __O  uint8_t SERV;                               /**< Service Register, offset: 0x1 */
  __IO uint8_t CMPL;                               /**< Compare Low Register, offset: 0x2 */
  __IO uint8_t CMPH;                               /**< Compare High Register, offset: 0x3 */
       uint8_t RESERVED_0[1];
  __IO uint8_t CLKPRESCALER;                       /**< Clock Prescaler Register, offset: 0x5 */
} EWM_Type;

/* ----------------------------------------------------------------------------
   -- EWM Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup EWM_Register_Masks EWM Register Masks
 * @{
 */

/*! @name CTRL - Control Register */
/*! @{ */

#define EWM_CTRL_EWMEN_MASK                      (0x1U)
#define EWM_CTRL_EWMEN_SHIFT                     (0U)
/*! EWMEN - EWM enable.
 *  0b0..EWM module is disabled.
 *  0b1..EWM module is enabled.
 */
#define EWM_CTRL_EWMEN(x)                        (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)

#define EWM_CTRL_ASSIN_MASK                      (0x2U)
#define EWM_CTRL_ASSIN_SHIFT                     (1U)
/*! ASSIN - EWM_in's Assertion State Select.
 *  0b0..Default assert state of the EWM_in signal.
 *  0b1..Inverts the assert state of EWM_in signal.
 */
#define EWM_CTRL_ASSIN(x)                        (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)

#define EWM_CTRL_INEN_MASK                       (0x4U)
#define EWM_CTRL_INEN_SHIFT                      (2U)
/*! INEN - Input Enable.
 *  0b0..EWM_in port is disabled.
 *  0b1..EWM_in port is enabled.
 */
#define EWM_CTRL_INEN(x)                         (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)

#define EWM_CTRL_INTEN_MASK                      (0x8U)
#define EWM_CTRL_INTEN_SHIFT                     (3U)
/*! INTEN - Interrupt Enable.
 *  0b1..Generates an interrupt request, when EWM_OUT_b is asserted.
 *  0b0..Deasserts the interrupt request.
 */
#define EWM_CTRL_INTEN(x)                        (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
/*! @} */

/*! @name SERV - Service Register */
/*! @{ */

#define EWM_SERV_SERVICE_MASK                    (0xFFU)
#define EWM_SERV_SERVICE_SHIFT                   (0U)
/*! SERVICE - SERVICE
 */
#define EWM_SERV_SERVICE(x)                      (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)
/*! @} */

/*! @name CMPL - Compare Low Register */
/*! @{ */

#define EWM_CMPL_COMPAREL_MASK                   (0xFFU)
#define EWM_CMPL_COMPAREL_SHIFT                  (0U)
/*! COMPAREL - COMPAREL
 */
#define EWM_CMPL_COMPAREL(x)                     (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)
/*! @} */

/*! @name CMPH - Compare High Register */
/*! @{ */

#define EWM_CMPH_COMPAREH_MASK                   (0xFFU)
#define EWM_CMPH_COMPAREH_SHIFT                  (0U)
/*! COMPAREH - COMPAREH
 */
#define EWM_CMPH_COMPAREH(x)                     (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)
/*! @} */

/*! @name CLKPRESCALER - Clock Prescaler Register */
/*! @{ */

#define EWM_CLKPRESCALER_CLK_DIV_MASK            (0xFFU)
#define EWM_CLKPRESCALER_CLK_DIV_SHIFT           (0U)
/*! CLK_DIV - CLK_DIV
 */
#define EWM_CLKPRESCALER_CLK_DIV(x)              (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group EWM_Register_Masks */


/* EWM - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral EWM0 base address */
  #define EWM0_BASE                                (0x50013000u)
  /** Peripheral EWM0 base address */
  #define EWM0_BASE_NS                             (0x40013000u)
  /** Peripheral EWM0 base pointer */
  #define EWM0                                     ((EWM_Type *)EWM0_BASE)
  /** Peripheral EWM0 base pointer */
  #define EWM0_NS                                  ((EWM_Type *)EWM0_BASE_NS)
  /** Array initializer of EWM peripheral base addresses */
  #define EWM_BASE_ADDRS                           { EWM0_BASE }
  /** Array initializer of EWM peripheral base pointers */
  #define EWM_BASE_PTRS                            { EWM0 }
  /** Array initializer of EWM peripheral base addresses */
  #define EWM_BASE_ADDRS_NS                        { EWM0_BASE_NS }
  /** Array initializer of EWM peripheral base pointers */
  #define EWM_BASE_PTRS_NS                         { EWM0_NS }
#else
  /** Peripheral EWM0 base address */
  #define EWM0_BASE                                (0x40013000u)
  /** Peripheral EWM0 base pointer */
  #define EWM0                                     ((EWM_Type *)EWM0_BASE)
  /** Array initializer of EWM peripheral base addresses */
  #define EWM_BASE_ADDRS                           { EWM0_BASE }
  /** Array initializer of EWM peripheral base pointers */
  #define EWM_BASE_PTRS                            { EWM0 }
#endif

/*!
 * @}
 */ /* end of group EWM_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- FLEXIO Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer
 * @{
 */

/** FLEXIO - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
  __IO uint32_t CTRL;                              /**< FlexIO Control Register, offset: 0x8 */
  __I  uint32_t PIN;                               /**< Pin State Register, offset: 0xC */
  __IO uint32_t SHIFTSTAT;                         /**< Shifter Status Register, offset: 0x10 */
  __IO uint32_t SHIFTERR;                          /**< Shifter Error Register, offset: 0x14 */
  __IO uint32_t TIMSTAT;                           /**< Timer Status Register, offset: 0x18 */
       uint8_t RESERVED_0[4];
  __IO uint32_t SHIFTSIEN;                         /**< Shifter Status Interrupt Enable, offset: 0x20 */
  __IO uint32_t SHIFTEIEN;                         /**< Shifter Error Interrupt Enable, offset: 0x24 */
  __IO uint32_t TIMIEN;                            /**< Timer Interrupt Enable Register, offset: 0x28 */
       uint8_t RESERVED_1[4];
  __IO uint32_t SHIFTSDEN;                         /**< Shifter Status DMA Enable, offset: 0x30 */
       uint8_t RESERVED_2[4];
  __IO uint32_t TIMERSDEN;                         /**< Timer Status DMA Enable, offset: 0x38 */
       uint8_t RESERVED_3[4];
  __IO uint32_t SHIFTSTATE;                        /**< Shifter State Register, offset: 0x40 */
       uint8_t RESERVED_4[4];
  __IO uint32_t TRGSTAT;                           /**< Trigger Status Register, offset: 0x48 */
  __IO uint32_t TRIGIEN;                           /**< External Trigger Interrupt Enable Register, offset: 0x4C */
  __IO uint32_t PINSTAT;                           /**< Pin Status Register, offset: 0x50 */
  __IO uint32_t PINIEN;                            /**< Pin Interrupt Enable Register, offset: 0x54 */
  __IO uint32_t PINREN;                            /**< Pin Rising Edge Enable Register, offset: 0x58 */
  __IO uint32_t PINFEN;                            /**< Pin Falling Edge Enable Register, offset: 0x5C */
  __IO uint32_t PINOUTD;                           /**< Pin Output Data Register, offset: 0x60 */
  __IO uint32_t PINOUTE;                           /**< Pin Output Enable Register, offset: 0x64 */
  __O  uint32_t PINOUTDIS;                         /**< Pin Output Disable Register, offset: 0x68 */
  __O  uint32_t PINOUTCLR;                         /**< Pin Output Clear Register, offset: 0x6C */
  __O  uint32_t PINOUTSET;                         /**< Pin Output Set Register, offset: 0x70 */
  __O  uint32_t PINOUTTOG;                         /**< Pin Output Toggle Register, offset: 0x74 */
       uint8_t RESERVED_5[8];
  __IO uint32_t SHIFTCTL[8];                       /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */
       uint8_t RESERVED_6[96];
  __IO uint32_t SHIFTCFG[8];                       /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */
       uint8_t RESERVED_7[224];
  __IO uint32_t SHIFTBUF[8];                       /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */
       uint8_t RESERVED_8[96];
  __IO uint32_t SHIFTBUFBIS[8];                    /**< Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4 */
       uint8_t RESERVED_9[96];
  __IO uint32_t SHIFTBUFBYS[8];                    /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */
       uint8_t RESERVED_10[96];
  __IO uint32_t SHIFTBUFBBS[8];                    /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4 */
       uint8_t RESERVED_11[96];
  __IO uint32_t TIMCTL[8];                         /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */
       uint8_t RESERVED_12[96];
  __IO uint32_t TIMCFG[8];                         /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */
       uint8_t RESERVED_13[96];
  __IO uint32_t TIMCMP[8];                         /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */
       uint8_t RESERVED_14[352];
  __IO uint32_t SHIFTBUFNBS[8];                    /**< Shifter Buffer N Nibble Byte Swapped Register, array offset: 0x680, array step: 0x4 */
       uint8_t RESERVED_15[96];
  __IO uint32_t SHIFTBUFHWS[8];                    /**< Shifter Buffer N Half Word Swapped Register, array offset: 0x700, array step: 0x4 */
       uint8_t RESERVED_16[96];
  __IO uint32_t SHIFTBUFNIS[8];                    /**< Shifter Buffer N Nibble Swapped Register, array offset: 0x780, array step: 0x4 */
       uint8_t RESERVED_17[96];
  __IO uint32_t SHIFTBUFOES[8];                    /**< Shifter Buffer N Odd Even Swapped Register, array offset: 0x800, array step: 0x4 */
       uint8_t RESERVED_18[96];
  __IO uint32_t SHIFTBUFEOS[8];                    /**< Shifter Buffer N Even Odd Swapped Register, array offset: 0x880, array step: 0x4 */
       uint8_t RESERVED_19[96];
  __IO uint32_t SHIFTBUFHBS[8];                    /**< Shifter Buffer N Halfword Byte Swapped Register, array offset: 0x900, array step: 0x4 */
} FLEXIO_Type;

/* ----------------------------------------------------------------------------
   -- FLEXIO Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks
 * @{
 */

/*! @name VERID - Version ID Register */
/*! @{ */

#define FLEXIO_VERID_FEATURE_MASK                (0xFFFFU)
#define FLEXIO_VERID_FEATURE_SHIFT               (0U)
/*! FEATURE - Feature Specification Number
 *  0b0000000000000000..Standard features implemented.
 *  0b0000000000000001..Supports state, logic and parallel modes.
 *  0b0000000000000010..Supports pin control registers.
 *  0b0000000000000011..Supports state, logic and parallel modes; plus pin control registers.
 */
#define FLEXIO_VERID_FEATURE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK)

#define FLEXIO_VERID_MINOR_MASK                  (0xFF0000U)
#define FLEXIO_VERID_MINOR_SHIFT                 (16U)
/*! MINOR - Minor Version Number
 */
#define FLEXIO_VERID_MINOR(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK)

#define FLEXIO_VERID_MAJOR_MASK                  (0xFF000000U)
#define FLEXIO_VERID_MAJOR_SHIFT                 (24U)
/*! MAJOR - Major Version Number
 */
#define FLEXIO_VERID_MAJOR(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK)
/*! @} */

/*! @name PARAM - Parameter Register */
/*! @{ */

#define FLEXIO_PARAM_SHIFTER_MASK                (0xFFU)
#define FLEXIO_PARAM_SHIFTER_SHIFT               (0U)
/*! SHIFTER - Shifter Number
 */
#define FLEXIO_PARAM_SHIFTER(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK)

#define FLEXIO_PARAM_TIMER_MASK                  (0xFF00U)
#define FLEXIO_PARAM_TIMER_SHIFT                 (8U)
/*! TIMER - Timer Number
 */
#define FLEXIO_PARAM_TIMER(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK)

#define FLEXIO_PARAM_PIN_MASK                    (0xFF0000U)
#define FLEXIO_PARAM_PIN_SHIFT                   (16U)
/*! PIN - Pin Number
 */
#define FLEXIO_PARAM_PIN(x)                      (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK)

#define FLEXIO_PARAM_TRIGGER_MASK                (0xFF000000U)
#define FLEXIO_PARAM_TRIGGER_SHIFT               (24U)
/*! TRIGGER - Trigger Number
 */
#define FLEXIO_PARAM_TRIGGER(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK)
/*! @} */

/*! @name CTRL - FlexIO Control Register */
/*! @{ */

#define FLEXIO_CTRL_FLEXEN_MASK                  (0x1U)
#define FLEXIO_CTRL_FLEXEN_SHIFT                 (0U)
/*! FLEXEN - FlexIO Enable
 *  0b0..FlexIO module is disabled.
 *  0b1..FlexIO module is enabled.
 */
#define FLEXIO_CTRL_FLEXEN(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK)

#define FLEXIO_CTRL_SWRST_MASK                   (0x2U)
#define FLEXIO_CTRL_SWRST_SHIFT                  (1U)
/*! SWRST - Software Reset
 *  0b0..Software reset is disabled
 *  0b1..Software reset is enabled, all FlexIO registers except the Control Register are reset.
 */
#define FLEXIO_CTRL_SWRST(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK)

#define FLEXIO_CTRL_FASTACC_MASK                 (0x4U)
#define FLEXIO_CTRL_FASTACC_SHIFT                (2U)
/*! FASTACC - Fast Access
 *  0b0..Configures for normal register accesses to FlexIO
 *  0b1..Configures for fast register accesses to FlexIO
 */
#define FLEXIO_CTRL_FASTACC(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK)

#define FLEXIO_CTRL_DBGE_MASK                    (0x40000000U)
#define FLEXIO_CTRL_DBGE_SHIFT                   (30U)
/*! DBGE - Debug Enable
 *  0b0..FlexIO is disabled in debug modes.
 *  0b1..FlexIO is enabled in debug modes
 */
#define FLEXIO_CTRL_DBGE(x)                      (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK)

#define FLEXIO_CTRL_DOZEN_MASK                   (0x80000000U)
#define FLEXIO_CTRL_DOZEN_SHIFT                  (31U)
/*! DOZEN - Doze Enable
 *  0b0..FlexIO enabled in Doze modes.
 *  0b1..FlexIO disabled in Doze modes.
 */
#define FLEXIO_CTRL_DOZEN(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK)
/*! @} */

/*! @name PIN - Pin State Register */
/*! @{ */

#define FLEXIO_PIN_PDI_MASK                      (0xFFFFFFFFU)
#define FLEXIO_PIN_PDI_SHIFT                     (0U)
/*! PDI - Pin Data Input
 */
#define FLEXIO_PIN_PDI(x)                        (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK)
/*! @} */

/*! @name SHIFTSTAT - Shifter Status Register */
/*! @{ */

#define FLEXIO_SHIFTSTAT_SSF_MASK                (0xFFU)
#define FLEXIO_SHIFTSTAT_SSF_SHIFT               (0U)
/*! SSF - Shifter Status Flag
 */
#define FLEXIO_SHIFTSTAT_SSF(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK)
/*! @} */

/*! @name SHIFTERR - Shifter Error Register */
/*! @{ */

#define FLEXIO_SHIFTERR_SEF_MASK                 (0xFFU)
#define FLEXIO_SHIFTERR_SEF_SHIFT                (0U)
/*! SEF - Shifter Error Flags
 */
#define FLEXIO_SHIFTERR_SEF(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK)
/*! @} */

/*! @name TIMSTAT - Timer Status Register */
/*! @{ */

#define FLEXIO_TIMSTAT_TSF_MASK                  (0xFFU)
#define FLEXIO_TIMSTAT_TSF_SHIFT                 (0U)
/*! TSF - Timer Status Flags
 */
#define FLEXIO_TIMSTAT_TSF(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK)
/*! @} */

/*! @name SHIFTSIEN - Shifter Status Interrupt Enable */
/*! @{ */

#define FLEXIO_SHIFTSIEN_SSIE_MASK               (0xFFU)
#define FLEXIO_SHIFTSIEN_SSIE_SHIFT              (0U)
/*! SSIE - Shifter Status Interrupt Enable
 */
#define FLEXIO_SHIFTSIEN_SSIE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK)
/*! @} */

/*! @name SHIFTEIEN - Shifter Error Interrupt Enable */
/*! @{ */

#define FLEXIO_SHIFTEIEN_SEIE_MASK               (0xFFU)
#define FLEXIO_SHIFTEIEN_SEIE_SHIFT              (0U)
/*! SEIE - Shifter Error Interrupt Enable
 */
#define FLEXIO_SHIFTEIEN_SEIE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK)
/*! @} */

/*! @name TIMIEN - Timer Interrupt Enable Register */
/*! @{ */

#define FLEXIO_TIMIEN_TEIE_MASK                  (0xFFU)
#define FLEXIO_TIMIEN_TEIE_SHIFT                 (0U)
/*! TEIE - Timer Status Interrupt Enable
 */
#define FLEXIO_TIMIEN_TEIE(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK)
/*! @} */

/*! @name SHIFTSDEN - Shifter Status DMA Enable */
/*! @{ */

#define FLEXIO_SHIFTSDEN_SSDE_MASK               (0xFFU)
#define FLEXIO_SHIFTSDEN_SSDE_SHIFT              (0U)
/*! SSDE - Shifter Status DMA Enable
 */
#define FLEXIO_SHIFTSDEN_SSDE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK)
/*! @} */

/*! @name TIMERSDEN - Timer Status DMA Enable */
/*! @{ */

#define FLEXIO_TIMERSDEN_TSDE_MASK               (0xFFU)
#define FLEXIO_TIMERSDEN_TSDE_SHIFT              (0U)
/*! TSDE - Timer Status DMA Enable
 */
#define FLEXIO_TIMERSDEN_TSDE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMERSDEN_TSDE_SHIFT)) & FLEXIO_TIMERSDEN_TSDE_MASK)
/*! @} */

/*! @name SHIFTSTATE - Shifter State Register */
/*! @{ */

#define FLEXIO_SHIFTSTATE_STATE_MASK             (0x7U)
#define FLEXIO_SHIFTSTATE_STATE_SHIFT            (0U)
/*! STATE - Current State Pointer
 */
#define FLEXIO_SHIFTSTATE_STATE(x)               (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK)
/*! @} */

/*! @name TRGSTAT - Trigger Status Register */
/*! @{ */

#define FLEXIO_TRGSTAT_ETSF_MASK                 (0xFU)
#define FLEXIO_TRGSTAT_ETSF_SHIFT                (0U)
/*! ETSF - External Trigger Status Flags
 */
#define FLEXIO_TRGSTAT_ETSF(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TRGSTAT_ETSF_SHIFT)) & FLEXIO_TRGSTAT_ETSF_MASK)
/*! @} */

/*! @name TRIGIEN - External Trigger Interrupt Enable Register */
/*! @{ */

#define FLEXIO_TRIGIEN_TRIE_MASK                 (0xFU)
#define FLEXIO_TRIGIEN_TRIE_SHIFT                (0U)
/*! TRIE - External Trigger Interrupt Enable
 */
#define FLEXIO_TRIGIEN_TRIE(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TRIGIEN_TRIE_SHIFT)) & FLEXIO_TRIGIEN_TRIE_MASK)
/*! @} */

/*! @name PINSTAT - Pin Status Register */
/*! @{ */

#define FLEXIO_PINSTAT_PSF_MASK                  (0xFFFFFFFFU)
#define FLEXIO_PINSTAT_PSF_SHIFT                 (0U)
/*! PSF - Pin Status Flags
 */
#define FLEXIO_PINSTAT_PSF(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINSTAT_PSF_SHIFT)) & FLEXIO_PINSTAT_PSF_MASK)
/*! @} */

/*! @name PINIEN - Pin Interrupt Enable Register */
/*! @{ */

#define FLEXIO_PINIEN_PSIE_MASK                  (0xFFFFFFFFU)
#define FLEXIO_PINIEN_PSIE_SHIFT                 (0U)
/*! PSIE - Pin Status Interrupt Enable
 */
#define FLEXIO_PINIEN_PSIE(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINIEN_PSIE_SHIFT)) & FLEXIO_PINIEN_PSIE_MASK)
/*! @} */

/*! @name PINREN - Pin Rising Edge Enable Register */
/*! @{ */

#define FLEXIO_PINREN_PRE_MASK                   (0xFFFFFFFFU)
#define FLEXIO_PINREN_PRE_SHIFT                  (0U)
/*! PRE - Pin Rising Edge
 */
#define FLEXIO_PINREN_PRE(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINREN_PRE_SHIFT)) & FLEXIO_PINREN_PRE_MASK)
/*! @} */

/*! @name PINFEN - Pin Falling Edge Enable Register */
/*! @{ */

#define FLEXIO_PINFEN_PFE_MASK                   (0xFFFFFFFFU)
#define FLEXIO_PINFEN_PFE_SHIFT                  (0U)
/*! PFE - Pin Falling Edge
 */
#define FLEXIO_PINFEN_PFE(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINFEN_PFE_SHIFT)) & FLEXIO_PINFEN_PFE_MASK)
/*! @} */

/*! @name PINOUTD - Pin Output Data Register */
/*! @{ */

#define FLEXIO_PINOUTD_OUTD_MASK                 (0xFFFFFFFFU)
#define FLEXIO_PINOUTD_OUTD_SHIFT                (0U)
/*! OUTD - Output Data
 */
#define FLEXIO_PINOUTD_OUTD(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTD_OUTD_SHIFT)) & FLEXIO_PINOUTD_OUTD_MASK)
/*! @} */

/*! @name PINOUTE - Pin Output Enable Register */
/*! @{ */

#define FLEXIO_PINOUTE_OUTE_MASK                 (0xFFFFFFFFU)
#define FLEXIO_PINOUTE_OUTE_SHIFT                (0U)
/*! OUTE - Output Enable
 */
#define FLEXIO_PINOUTE_OUTE(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTE_OUTE_SHIFT)) & FLEXIO_PINOUTE_OUTE_MASK)
/*! @} */

/*! @name PINOUTDIS - Pin Output Disable Register */
/*! @{ */

#define FLEXIO_PINOUTDIS_OUTDIS_MASK             (0xFFFFFFFFU)
#define FLEXIO_PINOUTDIS_OUTDIS_SHIFT            (0U)
/*! OUTDIS - Output Disable
 */
#define FLEXIO_PINOUTDIS_OUTDIS(x)               (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTDIS_OUTDIS_SHIFT)) & FLEXIO_PINOUTDIS_OUTDIS_MASK)
/*! @} */

/*! @name PINOUTCLR - Pin Output Clear Register */
/*! @{ */

#define FLEXIO_PINOUTCLR_OUTCLR_MASK             (0xFFFFFFFFU)
#define FLEXIO_PINOUTCLR_OUTCLR_SHIFT            (0U)
/*! OUTCLR - Output Clear
 */
#define FLEXIO_PINOUTCLR_OUTCLR(x)               (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTCLR_OUTCLR_SHIFT)) & FLEXIO_PINOUTCLR_OUTCLR_MASK)
/*! @} */

/*! @name PINOUTSET - Pin Output Set Register */
/*! @{ */

#define FLEXIO_PINOUTSET_OUTSET_MASK             (0xFFFFFFFFU)
#define FLEXIO_PINOUTSET_OUTSET_SHIFT            (0U)
/*! OUTSET - Output Set
 */
#define FLEXIO_PINOUTSET_OUTSET(x)               (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTSET_OUTSET_SHIFT)) & FLEXIO_PINOUTSET_OUTSET_MASK)
/*! @} */

/*! @name PINOUTTOG - Pin Output Toggle Register */
/*! @{ */

#define FLEXIO_PINOUTTOG_OUTTOG_MASK             (0xFFFFFFFFU)
#define FLEXIO_PINOUTTOG_OUTTOG_SHIFT            (0U)
/*! OUTTOG - Output Toggle
 */
#define FLEXIO_PINOUTTOG_OUTTOG(x)               (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTTOG_OUTTOG_SHIFT)) & FLEXIO_PINOUTTOG_OUTTOG_MASK)
/*! @} */

/*! @name SHIFTCTL - Shifter Control N Register */
/*! @{ */

#define FLEXIO_SHIFTCTL_SMOD_MASK                (0x7U)
#define FLEXIO_SHIFTCTL_SMOD_SHIFT               (0U)
/*! SMOD - Shifter Mode
 *  0b000..Disabled.
 *  0b001..Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer.
 *  0b010..Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer.
 *  0b011..Reserved.
 *  0b100..Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer.
 *  0b101..Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents.
 *  0b110..State mode. SHIFTBUF contents are used for storing programmable state attributes.
 *  0b111..Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table.
 */
#define FLEXIO_SHIFTCTL_SMOD(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK)

#define FLEXIO_SHIFTCTL_PINPOL_MASK              (0x80U)
#define FLEXIO_SHIFTCTL_PINPOL_SHIFT             (7U)
/*! PINPOL - Shifter Pin Polarity
 *  0b0..Pin is active high
 *  0b1..Pin is active low
 */
#define FLEXIO_SHIFTCTL_PINPOL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK)

#define FLEXIO_SHIFTCTL_PINSEL_MASK              (0x1F00U)
#define FLEXIO_SHIFTCTL_PINSEL_SHIFT             (8U)
/*! PINSEL - Shifter Pin Select
 */
#define FLEXIO_SHIFTCTL_PINSEL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK)

#define FLEXIO_SHIFTCTL_PINCFG_MASK              (0x30000U)
#define FLEXIO_SHIFTCTL_PINCFG_SHIFT             (16U)
/*! PINCFG - Shifter Pin Configuration
 *  0b00..Shifter pin output disabled
 *  0b01..Shifter pin open drain or bidirectional output enable
 *  0b10..Shifter pin bidirectional output data
 *  0b11..Shifter pin output
 */
#define FLEXIO_SHIFTCTL_PINCFG(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK)

#define FLEXIO_SHIFTCTL_TIMPOL_MASK              (0x800000U)
#define FLEXIO_SHIFTCTL_TIMPOL_SHIFT             (23U)
/*! TIMPOL - Timer Polarity
 *  0b0..Shift on posedge of Shift clock
 *  0b1..Shift on negedge of Shift clock
 */
#define FLEXIO_SHIFTCTL_TIMPOL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK)

#define FLEXIO_SHIFTCTL_TIMSEL_MASK              (0x7000000U)
#define FLEXIO_SHIFTCTL_TIMSEL_SHIFT             (24U)
/*! TIMSEL - Timer Select
 */
#define FLEXIO_SHIFTCTL_TIMSEL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK)
/*! @} */

/* The count of FLEXIO_SHIFTCTL */
#define FLEXIO_SHIFTCTL_COUNT                    (8U)

/*! @name SHIFTCFG - Shifter Configuration N Register */
/*! @{ */

#define FLEXIO_SHIFTCFG_SSTART_MASK              (0x3U)
#define FLEXIO_SHIFTCFG_SSTART_SHIFT             (0U)
/*! SSTART - Shifter Start bit
 *  0b00..Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable
 *  0b01..Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift
 *  0b10..Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0
 *  0b11..Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1
 */
#define FLEXIO_SHIFTCFG_SSTART(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK)

#define FLEXIO_SHIFTCFG_SSTOP_MASK               (0x30U)
#define FLEXIO_SHIFTCFG_SSTOP_SHIFT              (4U)
/*! SSTOP - Shifter Stop bit
 *  0b00..Stop bit disabled for transmitter/receiver/match store
 *  0b01..Stop bit disabled for transmitter/receiver/match store, receiver/match store will store receive data on
 *        the configured shift edge when timer in stop condition
 *  0b10..Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not
 *        0, receiver/match store will also store receive data on the configured shift edge when timer in stop
 *        condition
 *  0b11..Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not
 *        1, receiver/match store will also store receive data on the configured shift edge when timer in stop
 *        condition
 */
#define FLEXIO_SHIFTCFG_SSTOP(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK)

#define FLEXIO_SHIFTCFG_INSRC_MASK               (0x100U)
#define FLEXIO_SHIFTCFG_INSRC_SHIFT              (8U)
/*! INSRC - Input Source
 *  0b0..Pin
 *  0b1..Shifter N+1 Output
 */
#define FLEXIO_SHIFTCFG_INSRC(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK)

#define FLEXIO_SHIFTCFG_LATST_MASK               (0x200U)
#define FLEXIO_SHIFTCFG_LATST_SHIFT              (9U)
/*! LATST - Late Store
 *  0b0..Shift register stores the pre-shift register state.
 *  0b1..Shift register stores the post-shift register state.
 */
#define FLEXIO_SHIFTCFG_LATST(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_LATST_SHIFT)) & FLEXIO_SHIFTCFG_LATST_MASK)

#define FLEXIO_SHIFTCFG_SSIZE_MASK               (0x1000U)
#define FLEXIO_SHIFTCFG_SSIZE_SHIFT              (12U)
/*! SSIZE - Shifter Size
 *  0b0..Shift register is 32-bit.
 *  0b1..Shift register is 24-bit.
 */
#define FLEXIO_SHIFTCFG_SSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSIZE_SHIFT)) & FLEXIO_SHIFTCFG_SSIZE_MASK)

#define FLEXIO_SHIFTCFG_PWIDTH_MASK              (0x1F0000U)
#define FLEXIO_SHIFTCFG_PWIDTH_SHIFT             (16U)
/*! PWIDTH - Parallel Width
 */
#define FLEXIO_SHIFTCFG_PWIDTH(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK)
/*! @} */

/* The count of FLEXIO_SHIFTCFG */
#define FLEXIO_SHIFTCFG_COUNT                    (8U)

/*! @name SHIFTBUF - Shifter Buffer N Register */
/*! @{ */

#define FLEXIO_SHIFTBUF_SHIFTBUF_MASK            (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT           (0U)
/*! SHIFTBUF - Shift Buffer
 */
#define FLEXIO_SHIFTBUF_SHIFTBUF(x)              (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK)
/*! @} */

/* The count of FLEXIO_SHIFTBUF */
#define FLEXIO_SHIFTBUF_COUNT                    (8U)

/*! @name SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register */
/*! @{ */

#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK      (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT     (0U)
/*! SHIFTBUFBIS - Shift Buffer
 */
#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)
/*! @} */

/* The count of FLEXIO_SHIFTBUFBIS */
#define FLEXIO_SHIFTBUFBIS_COUNT                 (8U)

/*! @name SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register */
/*! @{ */

#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK      (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT     (0U)
/*! SHIFTBUFBYS - Shift Buffer
 */
#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)
/*! @} */

/* The count of FLEXIO_SHIFTBUFBYS */
#define FLEXIO_SHIFTBUFBYS_COUNT                 (8U)

/*! @name SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register */
/*! @{ */

#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK      (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT     (0U)
/*! SHIFTBUFBBS - Shift Buffer
 */
#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)
/*! @} */

/* The count of FLEXIO_SHIFTBUFBBS */
#define FLEXIO_SHIFTBUFBBS_COUNT                 (8U)

/*! @name TIMCTL - Timer Control N Register */
/*! @{ */

#define FLEXIO_TIMCTL_TIMOD_MASK                 (0x7U)
#define FLEXIO_TIMCTL_TIMOD_SHIFT                (0U)
/*! TIMOD - Timer Mode
 *  0b000..Timer Disabled.
 *  0b001..Dual 8-bit counters baud mode.
 *  0b010..Dual 8-bit counters PWM high mode.
 *  0b011..Single 16-bit counter mode.
 *  0b100..Single 16-bit counter disable mode.
 *  0b101..Dual 8-bit counters word mode.
 *  0b110..Dual 8-bit counters PWM low mode.
 *  0b111..Single 16-bit input capture mode.
 */
#define FLEXIO_TIMCTL_TIMOD(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK)

#define FLEXIO_TIMCTL_ONETIM_MASK                (0x20U)
#define FLEXIO_TIMCTL_ONETIM_SHIFT               (5U)
/*! ONETIM - Timer One Time Operation
 *  0b0..The timer enable event is generated as normal.
 *  0b1..The timer enable event is blocked unless timer status flag is clear.
 */
#define FLEXIO_TIMCTL_ONETIM(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_ONETIM_SHIFT)) & FLEXIO_TIMCTL_ONETIM_MASK)

#define FLEXIO_TIMCTL_PININS_MASK                (0x40U)
#define FLEXIO_TIMCTL_PININS_SHIFT               (6U)
/*! PININS - Timer Pin Input Select
 *  0b0..Timer pin input and output are selected by PINSEL.
 *  0b1..Timer pin input is selected by PINSEL+1, timer pin output remains selected by PINSEL.
 */
#define FLEXIO_TIMCTL_PININS(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PININS_SHIFT)) & FLEXIO_TIMCTL_PININS_MASK)

#define FLEXIO_TIMCTL_PINPOL_MASK                (0x80U)
#define FLEXIO_TIMCTL_PINPOL_SHIFT               (7U)
/*! PINPOL - Timer Pin Polarity
 *  0b0..Pin is active high
 *  0b1..Pin is active low
 */
#define FLEXIO_TIMCTL_PINPOL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK)

#define FLEXIO_TIMCTL_PINSEL_MASK                (0x1F00U)
#define FLEXIO_TIMCTL_PINSEL_SHIFT               (8U)
/*! PINSEL - Timer Pin Select
 */
#define FLEXIO_TIMCTL_PINSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK)

#define FLEXIO_TIMCTL_PINCFG_MASK                (0x30000U)
#define FLEXIO_TIMCTL_PINCFG_SHIFT               (16U)
/*! PINCFG - Timer Pin Configuration
 *  0b00..Timer pin output disabled
 *  0b01..Timer pin open drain or bidirectional output enable
 *  0b10..Timer pin bidirectional output data
 *  0b11..Timer pin output
 */
#define FLEXIO_TIMCTL_PINCFG(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK)

#define FLEXIO_TIMCTL_TRGSRC_MASK                (0x400000U)
#define FLEXIO_TIMCTL_TRGSRC_SHIFT               (22U)
/*! TRGSRC - Trigger Source
 *  0b0..External trigger selected
 *  0b1..Internal trigger selected
 */
#define FLEXIO_TIMCTL_TRGSRC(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK)

#define FLEXIO_TIMCTL_TRGPOL_MASK                (0x800000U)
#define FLEXIO_TIMCTL_TRGPOL_SHIFT               (23U)
/*! TRGPOL - Trigger Polarity
 *  0b0..Trigger active high
 *  0b1..Trigger active low
 */
#define FLEXIO_TIMCTL_TRGPOL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK)

#define FLEXIO_TIMCTL_TRGSEL_MASK                (0x3F000000U)
#define FLEXIO_TIMCTL_TRGSEL_SHIFT               (24U)
/*! TRGSEL - Trigger Select
 */
#define FLEXIO_TIMCTL_TRGSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK)
/*! @} */

/* The count of FLEXIO_TIMCTL */
#define FLEXIO_TIMCTL_COUNT                      (8U)

/*! @name TIMCFG - Timer Configuration N Register */
/*! @{ */

#define FLEXIO_TIMCFG_TSTART_MASK                (0x2U)
#define FLEXIO_TIMCFG_TSTART_SHIFT               (1U)
/*! TSTART - Timer Start Bit
 *  0b0..Start bit disabled
 *  0b1..Start bit enabled
 */
#define FLEXIO_TIMCFG_TSTART(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK)

#define FLEXIO_TIMCFG_TSTOP_MASK                 (0x30U)
#define FLEXIO_TIMCFG_TSTOP_SHIFT                (4U)
/*! TSTOP - Timer Stop Bit
 *  0b00..Stop bit disabled
 *  0b01..Stop bit is enabled on timer compare
 *  0b10..Stop bit is enabled on timer disable
 *  0b11..Stop bit is enabled on timer compare and timer disable
 */
#define FLEXIO_TIMCFG_TSTOP(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK)

#define FLEXIO_TIMCFG_TIMENA_MASK                (0x700U)
#define FLEXIO_TIMCFG_TIMENA_SHIFT               (8U)
/*! TIMENA - Timer Enable
 *  0b000..Timer always enabled
 *  0b001..Timer enabled on Timer N-1 enable
 *  0b010..Timer enabled on Trigger high
 *  0b011..Timer enabled on Trigger high and Pin high
 *  0b100..Timer enabled on Pin rising edge
 *  0b101..Timer enabled on Pin rising edge and Trigger high
 *  0b110..Timer enabled on Trigger rising edge
 *  0b111..Timer enabled on Trigger rising or falling edge
 */
#define FLEXIO_TIMCFG_TIMENA(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK)

#define FLEXIO_TIMCFG_TIMDIS_MASK                (0x7000U)
#define FLEXIO_TIMCFG_TIMDIS_SHIFT               (12U)
/*! TIMDIS - Timer Disable
 *  0b000..Timer never disabled
 *  0b001..Timer disabled on Timer N-1 disable
 *  0b010..Timer disabled on Timer compare (upper 8-bits match and decrement)
 *  0b011..Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low
 *  0b100..Timer disabled on Pin rising or falling edge
 *  0b101..Timer disabled on Pin rising or falling edge provided Trigger is high
 *  0b110..Timer disabled on Trigger falling edge
 *  0b111..Reserved
 */
#define FLEXIO_TIMCFG_TIMDIS(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK)

#define FLEXIO_TIMCFG_TIMRST_MASK                (0x70000U)
#define FLEXIO_TIMCFG_TIMRST_SHIFT               (16U)
/*! TIMRST - Timer Reset
 *  0b000..Timer never reset
 *  0b001..Timer reset on Timer Output high.
 *  0b010..Timer reset on Timer Pin equal to Timer Output
 *  0b011..Timer reset on Timer Trigger equal to Timer Output
 *  0b100..Timer reset on Timer Pin rising edge
 *  0b101..Reserved
 *  0b110..Timer reset on Trigger rising edge
 *  0b111..Timer reset on Trigger rising or falling edge
 */
#define FLEXIO_TIMCFG_TIMRST(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK)

#define FLEXIO_TIMCFG_TIMDEC_MASK                (0x700000U)
#define FLEXIO_TIMCFG_TIMDEC_SHIFT               (20U)
/*! TIMDEC - Timer Decrement
 *  0b000..Decrement counter on FlexIO clock, Shift clock equals Timer output.
 *  0b001..Decrement counter on Trigger input (both edges), Shift clock equals Timer output.
 *  0b010..Decrement counter on Pin input (both edges), Shift clock equals Pin input.
 *  0b011..Decrement counter on Trigger input (both edges), Shift clock equals Trigger input.
 *  0b100..Decrement counter on FlexIO clock divided by 16, Shift clock equals Timer output.
 *  0b101..Decrement counter on FlexIO clock divided by 256, Shift clock equals Timer output.
 *  0b110..Decrement counter on Pin input (rising edge), Shift clock equals Pin input.
 *  0b111..Decrement counter on Trigger input (rising edge), Shift clock equals Trigger input.
 */
#define FLEXIO_TIMCFG_TIMDEC(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK)

#define FLEXIO_TIMCFG_TIMOUT_MASK                (0x3000000U)
#define FLEXIO_TIMCFG_TIMOUT_SHIFT               (24U)
/*! TIMOUT - Timer Output
 *  0b00..Timer output is logic one when enabled and is not affected by timer reset
 *  0b01..Timer output is logic zero when enabled and is not affected by timer reset
 *  0b10..Timer output is logic one when enabled and on timer reset
 *  0b11..Timer output is logic zero when enabled and on timer reset
 */
#define FLEXIO_TIMCFG_TIMOUT(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK)
/*! @} */

/* The count of FLEXIO_TIMCFG */
#define FLEXIO_TIMCFG_COUNT                      (8U)

/*! @name TIMCMP - Timer Compare N Register */
/*! @{ */

#define FLEXIO_TIMCMP_CMP_MASK                   (0xFFFFU)
#define FLEXIO_TIMCMP_CMP_SHIFT                  (0U)
/*! CMP - Timer Compare Value
 */
#define FLEXIO_TIMCMP_CMP(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK)
/*! @} */

/* The count of FLEXIO_TIMCMP */
#define FLEXIO_TIMCMP_COUNT                      (8U)

/*! @name SHIFTBUFNBS - Shifter Buffer N Nibble Byte Swapped Register */
/*! @{ */

#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK      (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT     (0U)
/*! SHIFTBUFNBS - Shift Buffer
 */
#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK)
/*! @} */

/* The count of FLEXIO_SHIFTBUFNBS */
#define FLEXIO_SHIFTBUFNBS_COUNT                 (8U)

/*! @name SHIFTBUFHWS - Shifter Buffer N Half Word Swapped Register */
/*! @{ */

#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK      (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT     (0U)
/*! SHIFTBUFHWS - Shift Buffer
 */
#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK)
/*! @} */

/* The count of FLEXIO_SHIFTBUFHWS */
#define FLEXIO_SHIFTBUFHWS_COUNT                 (8U)

/*! @name SHIFTBUFNIS - Shifter Buffer N Nibble Swapped Register */
/*! @{ */

#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK      (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT     (0U)
/*! SHIFTBUFNIS - Shift Buffer
 */
#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK)
/*! @} */

/* The count of FLEXIO_SHIFTBUFNIS */
#define FLEXIO_SHIFTBUFNIS_COUNT                 (8U)

/*! @name SHIFTBUFOES - Shifter Buffer N Odd Even Swapped Register */
/*! @{ */

#define FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK      (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT     (0U)
/*! SHIFTBUFOES - Shift Buffer
 */
#define FLEXIO_SHIFTBUFOES_SHIFTBUFOES(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT)) & FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK)
/*! @} */

/* The count of FLEXIO_SHIFTBUFOES */
#define FLEXIO_SHIFTBUFOES_COUNT                 (8U)

/*! @name SHIFTBUFEOS - Shifter Buffer N Even Odd Swapped Register */
/*! @{ */

#define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK      (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT     (0U)
/*! SHIFTBUFEOS - Shift Buffer
 */
#define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT)) & FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK)
/*! @} */

/* The count of FLEXIO_SHIFTBUFEOS */
#define FLEXIO_SHIFTBUFEOS_COUNT                 (8U)

/*! @name SHIFTBUFHBS - Shifter Buffer N Halfword Byte Swapped Register */
/*! @{ */

#define FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_MASK      (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_SHIFT     (0U)
/*! SHIFTBUFHBS - Shift Buffer
 */
#define FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_SHIFT)) & FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_MASK)
/*! @} */

/* The count of FLEXIO_SHIFTBUFHBS */
#define FLEXIO_SHIFTBUFHBS_COUNT                 (8U)


/*!
 * @}
 */ /* end of group FLEXIO_Register_Masks */


/* FLEXIO - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral FLEXIO0 base address */
  #define FLEXIO0_BASE                             (0x5003A000u)
  /** Peripheral FLEXIO0 base address */
  #define FLEXIO0_BASE_NS                          (0x4003A000u)
  /** Peripheral FLEXIO0 base pointer */
  #define FLEXIO0                                  ((FLEXIO_Type *)FLEXIO0_BASE)
  /** Peripheral FLEXIO0 base pointer */
  #define FLEXIO0_NS                               ((FLEXIO_Type *)FLEXIO0_BASE_NS)
  /** Array initializer of FLEXIO peripheral base addresses */
  #define FLEXIO_BASE_ADDRS                        { FLEXIO0_BASE }
  /** Array initializer of FLEXIO peripheral base pointers */
  #define FLEXIO_BASE_PTRS                         { FLEXIO0 }
  /** Array initializer of FLEXIO peripheral base addresses */
  #define FLEXIO_BASE_ADDRS_NS                     { FLEXIO0_BASE_NS }
  /** Array initializer of FLEXIO peripheral base pointers */
  #define FLEXIO_BASE_PTRS_NS                      { FLEXIO0_NS }
#else
  /** Peripheral FLEXIO0 base address */
  #define FLEXIO0_BASE                             (0x4003A000u)
  /** Peripheral FLEXIO0 base pointer */
  #define FLEXIO0                                  ((FLEXIO_Type *)FLEXIO0_BASE)
  /** Array initializer of FLEXIO peripheral base addresses */
  #define FLEXIO_BASE_ADDRS                        { FLEXIO0_BASE }
  /** Array initializer of FLEXIO peripheral base pointers */
  #define FLEXIO_BASE_PTRS                         { FLEXIO0 }
#endif
/** Interrupt vectors for the FLEXIO peripheral type */
#define FLEXIO_IRQS                              { FLEXIO0_IRQn }

/*!
 * @}
 */ /* end of group FLEXIO_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- FMU Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup FMU_Peripheral_Access_Layer FMU Peripheral Access Layer
 * @{
 */

/** FMU - Register Layout Typedef */
typedef struct {
  __IO uint32_t FSTAT;                             /**< Flash Status Register, offset: 0x0 */
  __IO uint32_t FCNFG;                             /**< Flash Configuration Register, offset: 0x4 */
  __IO uint32_t FCTRL;                             /**< Flash Control Register, offset: 0x8 */
       uint8_t RESERVED_0[4];
  __IO uint32_t FCCOB[8];                          /**< Flash Common Command Object Registers, array offset: 0x10, array step: 0x4 */
} FMU_Type;

/* ----------------------------------------------------------------------------
   -- FMU Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup FMU_Register_Masks FMU Register Masks
 * @{
 */

/*! @name FSTAT - Flash Status Register */
/*! @{ */

#define FMU_FSTAT_FAIL_MASK                      (0x1U)
#define FMU_FSTAT_FAIL_SHIFT                     (0U)
/*! FAIL - Command Fail Flag
 *  0b0..Error not detected
 *  0b1..Error detected
 */
#define FMU_FSTAT_FAIL(x)                        (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_FAIL_SHIFT)) & FMU_FSTAT_FAIL_MASK)

#define FMU_FSTAT_CMDABT_MASK                    (0x4U)
#define FMU_FSTAT_CMDABT_SHIFT                   (2U)
/*! CMDABT - Command Abort Flag
 *  0b0..No command abort detected
 *  0b1..Command abort detected
 */
#define FMU_FSTAT_CMDABT(x)                      (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CMDABT_SHIFT)) & FMU_FSTAT_CMDABT_MASK)

#define FMU_FSTAT_PVIOL_MASK                     (0x10U)
#define FMU_FSTAT_PVIOL_SHIFT                    (4U)
/*! PVIOL - Command Protection Violation Flag
 *  0b0..No protection violation detected
 *  0b1..Protection violation detected
 */
#define FMU_FSTAT_PVIOL(x)                       (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_PVIOL_SHIFT)) & FMU_FSTAT_PVIOL_MASK)

#define FMU_FSTAT_ACCERR_MASK                    (0x20U)
#define FMU_FSTAT_ACCERR_SHIFT                   (5U)
/*! ACCERR - Command Access Error Flag
 *  0b0..No access error detected
 *  0b1..Access error detected
 */
#define FMU_FSTAT_ACCERR(x)                      (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_ACCERR_SHIFT)) & FMU_FSTAT_ACCERR_MASK)

#define FMU_FSTAT_CWSABT_MASK                    (0x40U)
#define FMU_FSTAT_CWSABT_SHIFT                   (6U)
/*! CWSABT - Command Write Sequence Abort Flag
 *  0b0..Command write sequence not aborted
 *  0b1..Command write sequence aborted
 */
#define FMU_FSTAT_CWSABT(x)                      (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CWSABT_SHIFT)) & FMU_FSTAT_CWSABT_MASK)

#define FMU_FSTAT_CCIF_MASK                      (0x80U)
#define FMU_FSTAT_CCIF_SHIFT                     (7U)
/*! CCIF - Command Complete Interrupt Flag
 *  0b0..Flash command, initialization, or power mode recovery in progress
 *  0b1..Flash command, initialization, or power mode recovery has completed
 */
#define FMU_FSTAT_CCIF(x)                        (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CCIF_SHIFT)) & FMU_FSTAT_CCIF_MASK)

#define FMU_FSTAT_CMDPRT_MASK                    (0x300U)
#define FMU_FSTAT_CMDPRT_SHIFT                   (8U)
/*! CMDPRT - Command protection level
 *  0b00..Secure, normal access
 *  0b01..Secure, privileged access
 *  0b10..Nonsecure, normal access
 *  0b11..Nonsecure, privileged access
 */
#define FMU_FSTAT_CMDPRT(x)                      (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CMDPRT_SHIFT)) & FMU_FSTAT_CMDPRT_MASK)

#define FMU_FSTAT_CMDP_MASK                      (0x800U)
#define FMU_FSTAT_CMDP_SHIFT                     (11U)
/*! CMDP - Command protection status flag
 *  0b0..Command protection level and domain ID are stale
 *  0b1..Command protection level (CMDPRT) and domain ID (CMDDID) are set
 */
#define FMU_FSTAT_CMDP(x)                        (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CMDP_SHIFT)) & FMU_FSTAT_CMDP_MASK)

#define FMU_FSTAT_CMDDID_MASK                    (0xF000U)
#define FMU_FSTAT_CMDDID_SHIFT                   (12U)
/*! CMDDID - Command domain ID
 */
#define FMU_FSTAT_CMDDID(x)                      (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CMDDID_SHIFT)) & FMU_FSTAT_CMDDID_MASK)

#define FMU_FSTAT_DFDIF_MASK                     (0x10000U)
#define FMU_FSTAT_DFDIF_SHIFT                    (16U)
/*! DFDIF - Double Bit Fault Detect Interrupt Flag
 *  0b0..Double bit fault not detected during a valid flash read access
 *  0b1..Double bit fault detected (or FCTRL[FDFD] is set) during a valid flash read access
 */
#define FMU_FSTAT_DFDIF(x)                       (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_DFDIF_SHIFT)) & FMU_FSTAT_DFDIF_MASK)

#define FMU_FSTAT_SALV_USED_MASK                 (0x20000U)
#define FMU_FSTAT_SALV_USED_SHIFT                (17U)
/*! SALV_USED - Salvage Used for Erase operation
 *  0b0..Salvage not used during last operation
 *  0b1..Salvage used during the last erase operation
 */
#define FMU_FSTAT_SALV_USED(x)                   (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_SALV_USED_SHIFT)) & FMU_FSTAT_SALV_USED_MASK)

#define FMU_FSTAT_PEWEN_MASK                     (0x3000000U)
#define FMU_FSTAT_PEWEN_SHIFT                    (24U)
/*! PEWEN - Program-Erase Write Enable Control
 *  0b00..Writes are not enabled
 *  0b01..Writes are enabled for one flash or IFR phrase (phrase programming, sector erase)
 *  0b10..Writes are enabled for one flash or IFR page (page programming)
 *  0b11..Reserved
 */
#define FMU_FSTAT_PEWEN(x)                       (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_PEWEN_SHIFT)) & FMU_FSTAT_PEWEN_MASK)

#define FMU_FSTAT_PERDY_MASK                     (0x80000000U)
#define FMU_FSTAT_PERDY_SHIFT                    (31U)
/*! PERDY - Program-Erase Ready Control/Status Flag
 *  0b0..Program or sector erase command operation not stalled
 *  0b1..Program or sector erase command operation ready to execute
 */
#define FMU_FSTAT_PERDY(x)                       (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_PERDY_SHIFT)) & FMU_FSTAT_PERDY_MASK)
/*! @} */

/*! @name FCNFG - Flash Configuration Register */
/*! @{ */

#define FMU_FCNFG_CCIE_MASK                      (0x80U)
#define FMU_FCNFG_CCIE_SHIFT                     (7U)
/*! CCIE - Command Complete Interrupt Enable
 *  0b0..Command complete interrupt disabled
 *  0b1..Command complete interrupt enabled
 */
#define FMU_FCNFG_CCIE(x)                        (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_CCIE_SHIFT)) & FMU_FCNFG_CCIE_MASK)

#define FMU_FCNFG_ERSREQ_MASK                    (0x100U)
#define FMU_FCNFG_ERSREQ_SHIFT                   (8U)
/*! ERSREQ - Mass Erase Request
 *  0b0..No request or request complete
 *  0b1..Request to run the Mass Erase operation
 */
#define FMU_FCNFG_ERSREQ(x)                      (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSREQ_SHIFT)) & FMU_FCNFG_ERSREQ_MASK)

#define FMU_FCNFG_DFDIE_MASK                     (0x10000U)
#define FMU_FCNFG_DFDIE_SHIFT                    (16U)
/*! DFDIE - Double Bit Fault Detect Interrupt Enable
 *  0b0..Double bit fault detect interrupt disabled
 *  0b1..Double bit fault detect interrupt enabled
 */
#define FMU_FCNFG_DFDIE(x)                       (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_DFDIE_SHIFT)) & FMU_FCNFG_DFDIE_MASK)

#define FMU_FCNFG_ERSIEN0_MASK                   (0xF000000U)
#define FMU_FCNFG_ERSIEN0_SHIFT                  (24U)
/*! ERSIEN0 - Erase IFR Sector Enable - Block 0
 *  0b0000..Block 0 IFR Sector X is protected from erase by ERSSCR command
 *  0b0001..Block 0 IFR Sector X is not protected from erase by ERSSCR command
 */
#define FMU_FCNFG_ERSIEN0(x)                     (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSIEN0_SHIFT)) & FMU_FCNFG_ERSIEN0_MASK)

#define FMU_FCNFG_ERSIEN1_MASK                   (0xF0000000U)
#define FMU_FCNFG_ERSIEN1_SHIFT                  (28U)
/*! ERSIEN1 - Erase IFR Sector Enable - Block 1 (for dual block configs)
 *  0b0000..Block 1 IFR Sector X is protected from erase by ERSSCR command
 *  0b0001..Block 1 IFR Sector X is not protected from erase by ERSSCR command
 */
#define FMU_FCNFG_ERSIEN1(x)                     (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSIEN1_SHIFT)) & FMU_FCNFG_ERSIEN1_MASK)
/*! @} */

/*! @name FCTRL - Flash Control Register */
/*! @{ */

#define FMU_FCTRL_RWSC_MASK                      (0xFU)
#define FMU_FCTRL_RWSC_SHIFT                     (0U)
/*! RWSC - Read Wait-State Control
 */
#define FMU_FCTRL_RWSC(x)                        (((uint32_t)(((uint32_t)(x)) << FMU_FCTRL_RWSC_SHIFT)) & FMU_FCTRL_RWSC_MASK)

#define FMU_FCTRL_LSACTIVE_MASK                  (0x100U)
#define FMU_FCTRL_LSACTIVE_SHIFT                 (8U)
/*! LSACTIVE - Low speed active mode
 *  0b0..Full speed active mode requested
 *  0b1..Low speed active mode requested
 */
#define FMU_FCTRL_LSACTIVE(x)                    (((uint32_t)(((uint32_t)(x)) << FMU_FCTRL_LSACTIVE_SHIFT)) & FMU_FCTRL_LSACTIVE_MASK)

#define FMU_FCTRL_FDFD_MASK                      (0x10000U)
#define FMU_FCTRL_FDFD_SHIFT                     (16U)
/*! FDFD - Force Double Bit Fault Detect
 *  0b0..FSTAT[DFDIF] sets only if a double bit fault is detected during a valid flash read access from the platform flash controller
 *  0b1..FSTAT[DFDIF] sets during any valid flash read access from the platform flash controller. An interrupt
 *       request is generated if the DFDIE bit is set.
 */
#define FMU_FCTRL_FDFD(x)                        (((uint32_t)(((uint32_t)(x)) << FMU_FCTRL_FDFD_SHIFT)) & FMU_FCTRL_FDFD_MASK)

#define FMU_FCTRL_ABTREQ_MASK                    (0x1000000U)
#define FMU_FCTRL_ABTREQ_SHIFT                   (24U)
/*! ABTREQ - Abort Request
 *  0b0..No request to abort a command write sequence
 *  0b1..Request to abort a command write sequence
 */
#define FMU_FCTRL_ABTREQ(x)                      (((uint32_t)(((uint32_t)(x)) << FMU_FCTRL_ABTREQ_SHIFT)) & FMU_FCTRL_ABTREQ_MASK)
/*! @} */

/*! @name FCCOB - Flash Common Command Object Registers */
/*! @{ */

#define FMU_FCCOB_CCOBn_MASK                     (0xFFFFFFFFU)
#define FMU_FCCOB_CCOBn_SHIFT                    (0U)
/*! CCOBn - CCOBn
 */
#define FMU_FCCOB_CCOBn(x)                       (((uint32_t)(((uint32_t)(x)) << FMU_FCCOB_CCOBn_SHIFT)) & FMU_FCCOB_CCOBn_MASK)
/*! @} */

/* The count of FMU_FCCOB */
#define FMU_FCCOB_COUNT                          (8U)


/*!
 * @}
 */ /* end of group FMU_Register_Masks */


/* FMU - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral FMU0 base address */
  #define FMU0_BASE                                (0x50020000u)
  /** Peripheral FMU0 base address */
  #define FMU0_BASE_NS                             (0x40020000u)
  /** Peripheral FMU0 base pointer */
  #define FMU0                                     ((FMU_Type *)FMU0_BASE)
  /** Peripheral FMU0 base pointer */
  #define FMU0_NS                                  ((FMU_Type *)FMU0_BASE_NS)
  /** Peripheral RF_FMU base address */
  #define RF_FMU_BASE                              (0x58981000u)
  /** Peripheral RF_FMU base address */
  #define RF_FMU_BASE_NS                           (0x48981000u)
  /** Peripheral RF_FMU base pointer */
  #define RF_FMU                                   ((FMU_Type *)RF_FMU_BASE)
  /** Peripheral RF_FMU base pointer */
  #define RF_FMU_NS                                ((FMU_Type *)RF_FMU_BASE_NS)
  /** Array initializer of FMU peripheral base addresses */
  #define FMU_BASE_ADDRS                           { FMU0_BASE, RF_FMU_BASE }
  /** Array initializer of FMU peripheral base pointers */
  #define FMU_BASE_PTRS                            { FMU0, RF_FMU }
  /** Array initializer of FMU peripheral base addresses */
  #define FMU_BASE_ADDRS_NS                        { FMU0_BASE_NS, RF_FMU_BASE_NS }
  /** Array initializer of FMU peripheral base pointers */
  #define FMU_BASE_PTRS_NS                         { FMU0_NS, RF_FMU_NS }
#else
  /** Peripheral FMU0 base address */
  #define FMU0_BASE                                (0x40020000u)
  /** Peripheral FMU0 base pointer */
  #define FMU0                                     ((FMU_Type *)FMU0_BASE)
  /** Peripheral RF_FMU base address */
  #define RF_FMU_BASE                              (0x48981000u)
  /** Peripheral RF_FMU base pointer */
  #define RF_FMU                                   ((FMU_Type *)RF_FMU_BASE)
  /** Array initializer of FMU peripheral base addresses */
  #define FMU_BASE_ADDRS                           { FMU0_BASE, RF_FMU_BASE }
  /** Array initializer of FMU peripheral base pointers */
  #define FMU_BASE_PTRS                            { FMU0, RF_FMU }
#endif

/*!
 * @}
 */ /* end of group FMU_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- FRO192M Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup FRO192M_Peripheral_Access_Layer FRO192M Peripheral Access Layer
 * @{
 */

/** FRO192M - Register Layout Typedef */
typedef struct {
  __IO uint32_t FROCCSR;                           /**< FRO192 Clock Control Status Register, offset: 0x0 */
  __IO uint32_t FRODIV;                            /**< FRO192 Divide Register, offset: 0x4 */
} FRO192M_Type;

/* ----------------------------------------------------------------------------
   -- FRO192M Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup FRO192M_Register_Masks FRO192M Register Masks
 * @{
 */

/*! @name FROCCSR - FRO192 Clock Control Status Register */
/*! @{ */

#define FRO192M_FROCCSR_FRODIV_MASK              (0x3U)
#define FRO192M_FROCCSR_FRODIV_SHIFT             (0U)
/*! FRODIV - FRO Clock Divide
 *  0b00..Divide by 1
 *  0b01..Divide by 2
 *  0b10..Divide by 3
 *  0b11..Divide by 4
 */
#define FRO192M_FROCCSR_FRODIV(x)                (((uint32_t)(((uint32_t)(x)) << FRO192M_FROCCSR_FRODIV_SHIFT)) & FRO192M_FROCCSR_FRODIV_MASK)

#define FRO192M_FROCCSR_POSTDIV_SEL_MASK         (0x7000U)
#define FRO192M_FROCCSR_POSTDIV_SEL_SHIFT        (12U)
/*! POSTDIV_SEL - Post Divider Clock Select
 *  0b000..FRO 16MHz Range selected.
 *  0b001..FRO 24MHz Range selected
 *  0b010..FRO 32MHz Range selected
 *  0b011..FRO 48MHz Range selected
 *  0b100..FRO 64MHz Range selected
 *  0b101..RESERVED. Not Supported
 *  0b110..RESERVED. Not Supported
 *  0b111..RESERVED. Not Supported
 */
#define FRO192M_FROCCSR_POSTDIV_SEL(x)           (((uint32_t)(((uint32_t)(x)) << FRO192M_FROCCSR_POSTDIV_SEL_SHIFT)) & FRO192M_FROCCSR_POSTDIV_SEL_MASK)

#define FRO192M_FROCCSR_VALID_MASK               (0x1000000U)
#define FRO192M_FROCCSR_VALID_SHIFT              (24U)
/*! VALID - Clock Valid Flag
 *  0b0..FRO192 is not enabled or clock is not valid.
 *  0b1..FRO192 is enabled and output clock is valid.
 */
#define FRO192M_FROCCSR_VALID(x)                 (((uint32_t)(((uint32_t)(x)) << FRO192M_FROCCSR_VALID_SHIFT)) & FRO192M_FROCCSR_VALID_MASK)
/*! @} */

/*! @name FRODIV - FRO192 Divide Register */
/*! @{ */

#define FRO192M_FRODIV_FRODIV_MASK               (0x3U)
#define FRO192M_FRODIV_FRODIV_SHIFT              (0U)
/*! FRODIV - FRO Clock Divide
 *  0b00..Divide by 1
 *  0b01..Divide by 2
 *  0b10..Divide by 3
 *  0b11..Divide by 4
 */
#define FRO192M_FRODIV_FRODIV(x)                 (((uint32_t)(((uint32_t)(x)) << FRO192M_FRODIV_FRODIV_SHIFT)) & FRO192M_FRODIV_FRODIV_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group FRO192M_Register_Masks */


/* FRO192M - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral FRO192M0 base address */
  #define FRO192M0_BASE                            (0x58980000u)
  /** Peripheral FRO192M0 base address */
  #define FRO192M0_BASE_NS                         (0x48980000u)
  /** Peripheral FRO192M0 base pointer */
  #define FRO192M0                                 ((FRO192M_Type *)FRO192M0_BASE)
  /** Peripheral FRO192M0 base pointer */
  #define FRO192M0_NS                              ((FRO192M_Type *)FRO192M0_BASE_NS)
  /** Array initializer of FRO192M peripheral base addresses */
  #define FRO192M_BASE_ADDRS                       { FRO192M0_BASE }
  /** Array initializer of FRO192M peripheral base pointers */
  #define FRO192M_BASE_PTRS                        { FRO192M0 }
  /** Array initializer of FRO192M peripheral base addresses */
  #define FRO192M_BASE_ADDRS_NS                    { FRO192M0_BASE_NS }
  /** Array initializer of FRO192M peripheral base pointers */
  #define FRO192M_BASE_PTRS_NS                     { FRO192M0_NS }
#else
  /** Peripheral FRO192M0 base address */
  #define FRO192M0_BASE                            (0x48980000u)
  /** Peripheral FRO192M0 base pointer */
  #define FRO192M0                                 ((FRO192M_Type *)FRO192M0_BASE)
  /** Array initializer of FRO192M peripheral base addresses */
  #define FRO192M_BASE_ADDRS                       { FRO192M0_BASE }
  /** Array initializer of FRO192M peripheral base pointers */
  #define FRO192M_BASE_PTRS                        { FRO192M0 }
#endif

/*!
 * @}
 */ /* end of group FRO192M_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- GEN4PHY Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup GEN4PHY_Peripheral_Access_Layer GEN4PHY Peripheral Access Layer
 * @{
 */

/** GEN4PHY - Register Layout Typedef */
typedef struct {
  __IO uint32_t FSK_PD_CFG0;                       /**< PHY Uncoded Preamble Detect Config 0, offset: 0x0 */
  __IO uint32_t FSK_PD_CFG1;                       /**< PHY Uncoded Preamble Detect Config 1, offset: 0x4 */
  __IO uint32_t FSK_PD_CFG2;                       /**< PHY Uncoded Preamble Detect Config 2, offset: 0x8 */
  __IO uint32_t FSK_PD_PH[2];                      /**< , array offset: 0xC, array step: 0x4 */
  __I  uint32_t FSK_PD_RO_PH[4];                   /**< , array offset: 0x14, array step: 0x4 */
  __IO uint32_t FSK_CFG0;                          /**< PHY Uncoded Config 0, offset: 0x24 */
  __IO uint32_t FSK_CFG1;                          /**< PHY Uncoded Config 1, offset: 0x28 */
  __IO uint32_t FSK_CFG2;                          /**< PHY Uncoded Config 2, offset: 0x2C */
       uint8_t RESERVED_0[4];
  __IO uint32_t FSK_PT;                            /**< PHY Uncoded Power Threshold Config, offset: 0x34 */
  __IO uint32_t FSK_FAD_CTRL;                      /**< PHY Uncoded FAD Control, offset: 0x38 */
  __IO uint32_t FSK_FAD_CFG;                       /**< PHY Uncoded FAD Config, offset: 0x3C */
  __I  uint32_t FSK_STAT;                          /**< PHY Uncoded Status, offset: 0x40 */
  __IO uint32_t LR_PD_CFG;                         /**< PHY Long Range Preamble Detect Config, offset: 0x44 */
  __IO uint32_t LR_PD_PH[4];                       /**< , array offset: 0x48, array step: 0x4 */
  __I  uint32_t LR_PD_RO_PH[13];                   /**< , array offset: 0x58, array step: 0x4 */
  __IO uint32_t LR_AA_CFG;                         /**< PHY Long Range AA Config, offset: 0x8C */
  __I  uint32_t LR_STAT;                           /**< PHY Long Range Status, offset: 0x90 */
  __IO uint32_t SM_CFG;                            /**< PHY State Machine Config, offset: 0x94 */
  __IO uint32_t MISC;                              /**< PHY Misc Config, offset: 0x98 */
  __I  uint32_t STAT0;                             /**< PHY Status 0, offset: 0x9C */
  __I  uint32_t STAT1;                             /**< PHY Status 1, offset: 0xA0 */
  __I  uint32_t STAT2;                             /**< PHY Status 2, offset: 0xA4 */
  __IO uint32_t PREPHY_MISC;                       /**< PHY PrePHY Misc Config, offset: 0xA8 */
  __IO uint32_t DMD_CTRL0;                         /**< PHY Demodulator Control 0, offset: 0xAC */
  __IO uint32_t DMD_CTRL1;                         /**< PHY Dmodulator Control 1, offset: 0xB0 */
  __IO uint32_t DMD_CTRL2;                         /**< PHY Demodulator Control 2, offset: 0xB4 */
  struct {                                         /* offset: 0xB8, array step: 0xC */
    __IO uint32_t DMD_WAVE_REG0;                     /**< , array offset: 0xB8, array step: 0xC */
    __IO uint32_t DMD_WAVE_REG1;                     /**< , array offset: 0xBC, array step: 0xC */
    __IO uint32_t DMD_WAVE_REG2;                     /**< , array offset: 0xC0, array step: 0xC */
  } DEMOD_WAVE[8];
       uint8_t RESERVED_1[76];
  __IO uint32_t DMDAA_CTRL;                        /**< PHY Demodulator Based SFD Confirmation control register., offset: 0x164 */
  __I  uint32_t RTT_STAT;                          /**< High resolution Time-Of-Flight calculation Status., offset: 0x168 */
  __IO uint32_t RTT_CTRL;                          /**< PHY RTT control register., offset: 0x16C */
  __IO uint32_t RTT_REF;                           /**< PHY RTT reference register., offset: 0x170 */
} GEN4PHY_Type;

/* ----------------------------------------------------------------------------
   -- GEN4PHY Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup GEN4PHY_Register_Masks GEN4PHY Register Masks
 * @{
 */

/*! @name FSK_PD_CFG0 - PHY Uncoded Preamble Detect Config 0 */
/*! @{ */

#define GEN4PHY_FSK_PD_CFG0_PREAMBLE_T_SCALE_MASK (0xFU)
#define GEN4PHY_FSK_PD_CFG0_PREAMBLE_T_SCALE_SHIFT (0U)
/*! PREAMBLE_T_SCALE - Scaling factor used for fractional time estimation during preamble search.
 */
#define GEN4PHY_FSK_PD_CFG0_PREAMBLE_T_SCALE(x)  (((uint32_t)(((uint32_t)(x)) << GEN4PHY_FSK_PD_CFG0_PREAMBLE_T_SCALE_SHIFT)) & GEN4PHY_FSK_PD_CFG0_PREAMBLE_T_SCALE_MASK)

#define GEN4PHY_FSK_PD_CFG0_PD_IIR_ALPHA_MASK    (0xFF00U)
#define GEN4PHY_FSK_PD_CFG0_PD_IIR_ALPHA_SHIFT   (8U)
/*! PD_IIR_ALPHA - Forgetting factor used by the complex correlations smoothing leaky integrator.
 */
#define GEN4PHY_FSK_PD_CFG0_PD_IIR_ALPHA(x)      (((uint32_t)(((uint32_t)(x)) << GEN4PHY_FSK_PD_CFG0_PD_IIR_ALPHA_SHIFT)) & GEN4PHY_FSK_PD_CFG0_PD_IIR_ALPHA_MASK)
/*! @} */

/*! @name FSK_PD_CFG1 - PHY Uncoded Preamble Detect Config 1 */
/*! @{ */

#define GEN4PHY_FSK_PD_CFG1_PREAMBLE_PATTERN_MASK (0xFFU)
#define GEN4PHY_FSK_PD_CFG1_PREAMBLE_PATTERN_SHIFT (0U)
/*! PREAMBLE_PATTERN - 8-bit preamble pattern used in FM-domain preamble detector.
 */
#define GEN4PHY_FSK_PD_CFG1_PREAMBLE_PATTERN(x)  (((uint32_t)(((uint32_t)(x)) << GEN4PHY_FSK_PD_CFG1_PREAMBLE_PATTERN_SHIFT)) & GEN4PHY_FSK_PD_CFG1_PREAMBLE_PATTERN_MASK)
/*! @} */

/*! @name FSK_PD_CFG2 - PHY Uncoded Preamble Detect Config 2 */
/*! @{ */

#define GEN4PHY_FSK_PD_CFG2_PD_THRESH_ACQ_1_3_1M_MASK (0xFFU)
#define GEN4PHY_FSK_PD_CFG2_PD_THRESH_ACQ_1_3_1M_SHIFT (0U)
/*! PD_THRESH_ACQ_1_3_1M - Preamble detect threshold for acq mode 1 and 3 at data rate 1Mbps
 */
#define GEN4PHY_FSK_PD_CFG2_PD_THRESH_ACQ_1_3_1M(x) (((uint32_t)(((uint32_t)(x)) << GEN4PHY_FSK_PD_CFG2_PD_THRESH_ACQ_1_3_1M_SHIFT)) & GEN4PHY_FSK_PD_CFG2_PD_THRESH_ACQ_1_3_1M_MASK)

#define GEN4PHY_FSK_PD_CFG2_PD_THRESH_ACQ_1_3_2M_MASK (0xFF0000U)
#define GEN4PHY_FSK_PD_CFG2_PD_THRESH_ACQ_1_3_2M_SHIFT (16U)
/*! PD_THRESH_ACQ_1_3_2M - Preamble detect threshold for acq mode 1 and 3 at data rate 2Mbps
 */
#define GEN4PHY_FSK_PD_CFG2_PD_THRESH_ACQ_1_3_2M(x) (((uint32_t)(((uint32_t)(x)) << GEN4PHY_FSK_PD_CFG2_PD_THRESH_ACQ_1_3_2M_SHIFT)) & GEN4PHY_FSK_PD_CFG2_PD_THRESH_ACQ_1_3_2M_MASK)
/*! @} */

/*! @name FSK_PD_PH -  */
/*! @{ */

#define GEN4PHY_FSK_PD_PH_REF0_MASK              (0x3FU)
#define GEN4PHY_FSK_PD_PH_REF0_SHIFT             (0U)
/*! REF0 - Uncoded preamble reference waveform sample 4 (sfix6en5)
 */
#define GEN4PHY_FSK_PD_PH_REF0(x)                (((uint32_t)(((uint32_t)(x)) << GEN4PHY_FSK_PD_PH_REF0_SHIFT)) & GEN4PHY_FSK_PD_PH_REF0_MASK)

#define GEN4PHY_FSK_PD_PH_REF1_MASK              (0x3F00U)
#define GEN4PHY_FSK_PD_PH_REF1_SHIFT             (8U)
/*! REF1 - Uncoded preamble reference waveform sample 5 (sfix6en5)
 */
#define GEN4PHY_FSK_PD_PH_REF1(x)                (((uint32_t)(((uint32_t)(x)) << GEN4PHY_FSK_PD_PH_REF1_SHIFT)) & GEN4PHY_FSK_PD_PH_REF1_MASK)

#define GEN4PHY_FSK_PD_PH_REF2_MASK              (0x3F0000U)
#define GEN4PHY_FSK_PD_PH_REF2_SHIFT             (16U)
/*! REF2 - Uncoded preamble reference waveform sample 6 (sfix6en5)
 */
#define GEN4PHY_FSK_PD_PH_REF2(x)                (((uint32_t)(((uint32_t)(x)) << GEN4PHY_FSK_PD_PH_REF2_SHIFT)) & GEN4PHY_FSK_PD_PH_REF2_MASK)

#define GEN4PHY_FSK_PD_PH_REF3_MASK              (0x3F000000U)
#define GEN4PHY_FSK_PD_PH_REF3_SHIFT             (24U)
/*! REF3 - Uncoded preamble reference waveform sample 7 (sfix6en5)
 */
#define GEN4PHY_FSK_PD_PH_REF3(x)                (((uint32_t)(((uint32_t)(x)) << GEN4PHY_FSK_PD_PH_REF3_SHIFT)) & GEN4PHY_FSK_PD_PH_REF3_MASK)
/*! @} */

/* The count of GEN4PHY_FSK_PD_PH */
#define GEN4PHY_FSK_PD_PH_COUNT                  (2U)

/*! @name FSK_PD_RO_PH -  */
/*! @{ */

#define GEN4PHY_FSK_PD_RO_PH_REF0_MASK           (0x3FU)
#define GEN4PHY_FSK_PD_RO_PH_REF0_SHIFT          (0U)
/*! REF0 - Uncoded preamble reference waveform sample 28 (sfix6en5)
 */
#define GEN4PHY_FSK_PD_RO_PH_REF0(x)             (((uint32_t)(((uint32_t)(x)) << GEN4PHY_FSK_PD_RO_PH_REF0_SHIFT)) & GEN4PHY_FSK_PD_RO_PH_REF0_MASK)

#define GEN4PHY_FSK_PD_RO_PH_REF1_MASK           (0x3F00U)
#define GEN4PHY_FSK_PD_RO_PH_REF1_SHIFT          (8U)
/*! REF1 - Uncoded preamble reference waveform sample 29 (sfix6en5)
 */
#define GEN4PHY_FSK_PD_RO_PH_REF1(x)             (((uint32_t)(((uint32_t)(x)) << GEN4PHY_FSK_PD_RO_PH_REF1_SHIFT)) & GEN4PHY_FSK_PD_RO_PH_REF1_MASK)

#define GEN4PHY_FSK_PD_RO_PH_REF2_MASK           (0x3F0000U)
#define GEN4PHY_FSK_PD_RO_PH_REF2_SHIFT          (16U)
/*! REF2 - Uncoded preamble reference waveform sample 30 (sfix6en5)
 */
#define GEN4PHY_FSK_PD_RO_PH_REF2(x)             (((uint32_t)(((uint32_t)(x)) << GEN4PHY_FSK_PD_RO_PH_REF2_SHIFT)) & GEN4PHY_FSK_PD_RO_PH_REF2_MASK)

#define GEN4PHY_FSK_PD_RO_PH_REF3_MASK           (0x3F000000U)
#define GEN4PHY_FSK_PD_RO_PH_REF3_SHIFT          (24U)
/*! REF3 - Uncoded preamble reference waveform sample 31 (sfix6en5)
 */
#define GEN4PHY_FSK_PD_RO_PH_REF3(x)             (((uint32_t)(((uint32_t)(x)) << GEN4PHY_FSK_PD_RO_PH_REF3_SHIFT)) & GEN4PHY_FSK_PD_RO_PH_REF3_MASK)
/*! @} */

/* The count of GEN4PHY_FSK_PD_RO_PH */
#define GEN4PHY_FSK_PD_RO_PH_COUNT               (4U)

/*! @name FSK_CFG0 - PHY Uncoded Config 0 */
/*! @{ */

#define GEN4PHY_FSK_CFG0_AA_OUT_SEL_MASK         (0x2U)
#define GEN4PHY_FSK_CFG0_AA_OUT_SEL_SHIFT        (1U)
/*! AA_OUT_SEL - Specifies which AA bits to be played-back to the LL:
 *  0b0..output the received AA bits
 *  0b1..output the programmed AA bits
 */
#define GEN4PHY_FSK_CFG0_AA_OUT_SEL(x)           (((uint32_t)(((uint32_t)(x)) << GEN4PHY_FSK_CFG0_AA_OUT_SEL_SHIFT)) & GEN4PHY_FSK_CFG0_AA_OUT_SEL_MASK)

#define GEN4PHY_FSK_CFG0_FSK_BIT_INVERT_MASK     (0x4U)
#define GEN4PHY_FSK_CFG0_FSK_BIT_INVERT_SHIFT    (2U)
/*! FSK_BIT_INVERT - This applies at the demodulator, so it affects both AA and the data portions of the packet.
 *  0b0..Normal demodulation
 *  0b1..Invert demodulated bits
 */
#define GEN4PHY_FSK_CFG0_FSK_BIT_INVERT(x)       (((uint32_t)(((uint32_t)(x)) << GEN4PHY_FSK_CFG0_FSK_BIT_INVERT_SHIFT)) & GEN4PHY_FSK_CFG0_FSK_BIT_INVERT_MASK)

#define GEN4PHY_FSK_CFG0_MSK_EN_MASK             (0x20U)
#define GEN4PHY_FSK_CFG0_MSK_EN_SHIFT            (5U)
/*! MSK_EN - Configures PHY for MSK decoding.
 */
#define GEN4PHY_FSK_CFG0_MSK_EN(x)               (((uint32_t)(((uint32_t)(x)) << GEN4PHY_FSK_CFG0_MSK_EN_SHIFT)) & GEN4PHY_FSK_CFG0_MSK_EN_MASK)

#define GEN4PHY_FSK_CFG0_MSK2FSK_SEED_MASK       (0x40U)
#define GEN4PHY_FSK_CFG0_MSK2FSK_SEED_SHIFT      (6U)
/*! MSK2FSK_SEED - Last bit of preamble.
 */
#define GEN4PHY_FSK_CFG0_MSK2FSK_SEED(x)         (((uint32_t)(((uint32_t)(x)) << GEN4PHY_FSK_CFG0_MSK2FSK_SEED_SHIFT)) & GEN4PHY_FSK_CFG0_MSK2FSK_SEED_MASK)

#define GEN4PHY_FSK_CFG0_AA_ACQ_1_2_3_THRESH_1M_MASK (0x1F00U)
#define GEN4PHY_FSK_CFG0_AA_ACQ_1_2_3_THRESH_1M_SHIFT (8U)
/*! AA_ACQ_1_2_3_THRESH_1M - For 1Mbps data rate, Correlation threshold applicable to AA detection; uses ufix5_En5 fixed-point format.
 */
#define GEN4PHY_FSK_CFG0_AA_ACQ_1_2_3_THRESH_1M(x) (((uint32_t)(((uint32_t)(x)) << GEN4PHY_FSK_CFG0_AA_ACQ_1_2_3_THRESH_1M_SHIFT)) & GEN4PHY_FSK_CFG0_AA_ACQ_1_2_3_THRESH_1M_MASK)

#define GEN4PHY_FSK_CFG0_HAMMING_AA_LOW_PWR_MASK (0xF0000U)
#define GEN4PHY_FSK_CFG0_HAMMING_AA_LOW_PWR_SHIFT (16U)
/*! HAMMING_AA_LOW_PWR - Maximum hamming distance from the given AA pattern that may still be
 *    accepted as a match; valid range [0,7]. This threshold value are performed on lower power case.
 */
#define GEN4PHY_FSK_CFG0_HAMMING_AA_LOW_PWR(x)   (((uint32_t)(((uint32_t)(x)) << GEN4PHY_FSK_CFG0_HAMMING_AA_LOW_PWR_SHIFT)) & GEN4PHY_FSK_CFG0_HAMMING_AA_LOW_PWR_MASK)

#define GEN4PHY_FSK_CFG0_BLE_NTW_ADR_THR_MASK    (0x700000U)
#define GEN4PHY_FSK_CFG0_BLE_NTW_ADR_THR_SHIFT   (20U)
/*! BLE_NTW_ADR_THR - Maximum hamming distance from the given AA pattern that may still be accepted
 *    as a match; valid range [0,7]. This threshold value are performed on lower power case.
 */
#define GEN4PHY_FSK_CFG0_BLE_NTW_ADR_THR(x)      (((uint32_t)(((uint32_t)(x)) << GEN4PHY_FSK_CFG0_BLE_NTW_ADR_THR_SHIFT)) & GEN4PHY_FSK_CFG0_BLE_NTW_ADR_THR_MASK)

#define GEN4PHY_FSK_CFG0_AA_ACQ_1_2_3_THRESH_2M_MASK (0x1F000000U)
#define GEN4PHY_FSK_CFG0_AA_ACQ_1_2_3_THRESH_2M_SHIFT (24U)
/*! AA_ACQ_1_2_3_THRESH_2M - For 2Mbps data rate, correlation threshold applicable to AA detection; uses ufix5_En5 fixed-point format.
 */
#define GEN4PHY_FSK_CFG0_AA_ACQ_1_2_3_THRESH_2M(x) (((uint32_t)(((uint32_t)(x)) << GEN4PHY_FSK_CFG0_AA_ACQ_1_2_3_THRESH_2M_SHIFT)) & GEN4PHY_FSK_CFG0_AA_ACQ_1_2_3_THRESH_2M_MASK)
/*! @} */

/*! @name FSK_CFG1 - PHY Uncoded Config 1 */
/*! @{ */

#define GEN4PHY_FSK_CFG1_OVERH_MASK              (0x1FFU)
#define GEN4PHY_FSK_CFG1_OVERH_SHIFT             (0U)
/*! OVERH - Modulation index; represented in ufix9_En6 format.
 */
#define GEN4PHY_FSK_CFG1_OVERH(x)                (((uint32_t)(((uint32_t)(x)) << GEN4PHY_FSK_CFG1_OVERH_SHIFT)) & GEN4PHY_FSK_CFG1_OVERH_MASK)

#define GEN4PHY_FSK_CFG1_OVERH_INV_MASK          (0xFF800U)
#define GEN4PHY_FSK_CFG1_OVERH_INV_SHIFT         (11U)
/*! OVERH_INV - Reciprocal of modulation index; represented in ufix9_En7 format.
 */
#define GEN4PHY_FSK_CFG1_OVERH_INV(x)            (((uint32_t)(((uint32_t)(x)) << GEN4PHY_FSK_CFG1_OVERH_INV_SHIFT)) & GEN4PHY_FSK_CFG1_OVERH_INV_MASK)

#define GEN4PHY_FSK_CFG1_SYNCTSCALE_MASK         (0xF000000U)
#define GEN4PHY_FSK_CFG1_SYNCTSCALE_SHIFT        (24U)
/*! SYNCTSCALE - Scaling factor used for fractional time estimation during AA search; represented in ufix4_En3 format.
 */
#define GEN4PHY_FSK_CFG1_SYNCTSCALE(x)           (((uint32_t)(((uint32_t)(x)) << GEN4PHY_FSK_CFG1_SYNCTSCALE_SHIFT)) & GEN4PHY_FSK_CFG1_SYNCTSCALE_MASK)
/*! @} */

/*! @name FSK_CFG2 - PHY Uncoded Config 2 */
/*! @{ */

#define GEN4PHY_FSK_CFG2_MAG_WIN_MASK            (0xF0000000U)
#define GEN4PHY_FSK_CFG2_MAG_WIN_SHIFT           (28U)
/*! MAG_WIN - Indicates the forgetting factor used in received signal level measurement;
 */
#define GEN4PHY_FSK_CFG2_MAG_WIN(x)              (((uint32_t)(((uint32_t)(x)) << GEN4PHY_FSK_CFG2_MAG_WIN_SHIFT)) & GEN4PHY_FSK_CFG2_MAG_WIN_MASK)
/*! @} */

/*! @name FSK_PT - PHY Uncoded Power Threshold Config */
/*! @{ */

#define GEN4PHY_FSK_PT_AGC_TIMEOUT_MASK          (0xFFFFU)
#define GEN4PHY_FSK_PT_AGC_TIMEOUT_SHIFT         (0U)
/*! AGC_TIMEOUT - Time-out, applicable to special conditioning of signal power detection in the
 *    Power threshold block, after each AGC gain adjustment. It is expressed in number of samples.
 */
#define GEN4PHY_FSK_PT_AGC_TIMEOUT(x)            (((uint32_t)(((uint32_t)(x)) << GEN4PHY_FSK_PT_AGC_TIMEOUT_SHIFT)) & GEN4PHY_FSK_PT_AGC_TIMEOUT_MASK)

#define GEN4PHY_FSK_PT_COND_SIG_PRST_EN_MASK     (0x10000U)
#define GEN4PHY_FSK_PT_COND_SIG_PRST_EN_SHIFT    (16U)
/*! COND_SIG_PRST_EN - Enables special conditioning of signal detection;
 *  0b0..disable.
 *  0b1..enable.
 */
#define GEN4PHY_FSK_PT_COND_SIG_PRST_EN(x)       (((uint32_t)(((uint32_t)(x)) << GEN4PHY_FSK_PT_COND_SIG_PRST_EN_SHIFT)) & GEN4PHY_FSK_PT_COND_SIG_PRST_EN_MASK)

#define GEN4PHY_FSK_PT_COND_AA_BUFF_EN_MASK      (0x20000U)
#define GEN4PHY_FSK_PT_COND_AA_BUFF_EN_SHIFT     (17U)
/*! COND_AA_BUFF_EN - Enables special condition for enabling AA detector buffer;
 *  0b0..disable.
 *  0b1..enable.
 */
#define GEN4PHY_FSK_PT_COND_AA_BUFF_EN(x)        (((uint32_t)(((uint32_t)(x)) << GEN4PHY_FSK_PT_COND_AA_BUFF_EN_SHIFT)) & GEN4PHY_FSK_PT_COND_AA_BUFF_EN_MASK)

#define GEN4PHY_FSK_PT_BYPASS_WITH_RSSI_MASK     (0x40000U)
#define GEN4PHY_FSK_PT_BYPASS_WITH_RSSI_SHIFT    (18U)
/*! BYPASS_WITH_RSSI - Bypass signal power measurement with RSSI measurement;
 *  0b0..no
 *  0b1..yes
 */
#define GEN4PHY_FSK_PT_BYPASS_WITH_RSSI(x)       (((uint32_t)(((uint32_t)(x)) << GEN4PHY_FSK_PT_BYPASS_WITH_RSSI_SHIFT)) & GEN4PHY_FSK_PT_BYPASS_WITH_RSSI_MASK)
/*! @} */

/*! @name FSK_FAD_CTRL - PHY Uncoded FAD Control */
/*! @{ */

#define GEN4PHY_FSK_FAD_CTRL_FAD_EN_MASK         (0x1U)
#define GEN4PHY_FSK_FAD_CTRL_FAD_EN_SHIFT        (0U)
/*! FAD_EN - Enables FAD;
 *  0b0..disable.
 *  0b1..enable.
 */
#define GEN4PHY_FSK_FAD_CTRL_FAD_EN(x)           (((uint32_t)(((uint32_t)(x)) << GEN4PHY_FSK_FAD_CTRL_FAD_EN_SHIFT)) & GEN4PHY_FSK_FAD_CTRL_FAD_EN_MASK)
/*! @} */

/*! @name FSK_FAD_CFG - PHY Uncoded FAD Config */
/*! @{ */

#define GEN4PHY_FSK_FAD_CFG_WIN_FAD_WAIT_SYNCH_MASK (0x7FU)
#define GEN4PHY_FSK_FAD_CFG_WIN_FAD_WAIT_SYNCH_SHIFT (0U)
/*! WIN_FAD_WAIT_SYNCH - Time-window to wait for clean samples, before transitioning to AA search
 *    PHY state, if PD was found after antenna switch (refered to as T3 in the PHY state-machine
 *    section).
 */
#define GEN4PHY_FSK_FAD_CFG_WIN_FAD_WAIT_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << GEN4PHY_FSK_FAD_CFG_WIN_FAD_WAIT_SYNCH_SHIFT)) & GEN4PHY_FSK_FAD_CFG_WIN_FAD_WAIT_SYNCH_MASK)

#define GEN4PHY_FSK_FAD_CFG_WIN_FAD_WAIT_PD_MASK (0x7F00U)
#define GEN4PHY_FSK_FAD_CFG_WIN_FAD_WAIT_PD_SHIFT (8U)
/*! WIN_FAD_WAIT_PD - Time-window to wait for clean samples if PD was not found after antenna switch
 *    (refered to as T2 in the PHY state-machine section).
 */
#define GEN4PHY_FSK_FAD_CFG_WIN_FAD_WAIT_PD(x)   (((uint32_t)(((uint32_t)(x)) << GEN4PHY_FSK_FAD_CFG_WIN_FAD_WAIT_PD_SHIFT)) & GEN4PHY_FSK_FAD_CFG_WIN_FAD_WAIT_PD_MASK)

#define GEN4PHY_FSK_FAD_CFG_WIN_FAD_SEARCH_PD_MASK (0x7F0000U)
#define GEN4PHY_FSK_FAD_CFG_WIN_FAD_SEARCH_PD_SHIFT (16U)
/*! WIN_FAD_SEARCH_PD - Time-window to match preamble pattern on samples coming from the previously
 *    selected antenna (refered to as T1 in the PHY state-machine section).
 */
#define GEN4PHY_FSK_FAD_CFG_WIN_FAD_SEARCH_PD(x) (((uint32_t)(((uint32_t)(x)) << GEN4PHY_FSK_FAD_CFG_WIN_FAD_SEARCH_PD_SHIFT)) & GEN4PHY_FSK_FAD_CFG_WIN_FAD_SEARCH_PD_MASK)

#define GEN4PHY_FSK_FAD_CFG_WIN_SEARCH_PD_MASK   (0x7F000000U)
#define GEN4PHY_FSK_FAD_CFG_WIN_SEARCH_PD_SHIFT  (24U)
/*! WIN_SEARCH_PD - Time-window to match preamble pattern on samples coming from the currently
 *    selected antenna (refered to as T0 in the PHY state-machine section).
 */
#define GEN4PHY_FSK_FAD_CFG_WIN_SEARCH_PD(x)     (((uint32_t)(((uint32_t)(x)) << GEN4PHY_FSK_FAD_CFG_WIN_SEARCH_PD_SHIFT)) & GEN4PHY_FSK_FAD_CFG_WIN_SEARCH_PD_MASK)
/*! @} */

/*! @name FSK_STAT - PHY Uncoded Status */
/*! @{ */

#define GEN4PHY_FSK_STAT_AA_FOUND_MASK           (0x4U)
#define GEN4PHY_FSK_STAT_AA_FOUND_SHIFT          (2U)
/*! AA_FOUND - Indicates that a uncoded AA detect is active.
 */
#define GEN4PHY_FSK_STAT_AA_FOUND(x)             (((uint32_t)(((uint32_t)(x)) << GEN4PHY_FSK_STAT_AA_FOUND_SHIFT)) & GEN4PHY_FSK_STAT_AA_FOUND_MASK)

#define GEN4PHY_FSK_STAT_AA_MATCH_MASK           (0xF0U)
#define GEN4PHY_FSK_STAT_AA_MATCH_SHIFT          (4U)
/*! AA_MATCH - Indicates which non-coded AA has matched. This will clear when the PHY is re-initialized.
 */
#define GEN4PHY_FSK_STAT_AA_MATCH(x)             (((uint32_t)(((uint32_t)(x)) << GEN4PHY_FSK_STAT_AA_MATCH_SHIFT)) & GEN4PHY_FSK_STAT_AA_MATCH_MASK)

#define GEN4PHY_FSK_STAT_HAMM_DIST_MASK          (0x7F00U)
#define GEN4PHY_FSK_STAT_HAMM_DIST_SHIFT         (8U)
/*! HAMM_DIST - Indicates the hamming distance witnessed when AA match occurred.
 */
#define GEN4PHY_FSK_STAT_HAMM_DIST(x)            (((uint32_t)(((uint32_t)(x)) << GEN4PHY_FSK_STAT_HAMM_DIST_SHIFT)) & GEN4PHY_FSK_STAT_HAMM_DIST_MASK)

#define GEN4PHY_FSK_STAT_CORR_MAX_MASK           (0x1F0000U)
#define GEN4PHY_FSK_STAT_CORR_MAX_SHIFT          (16U)
/*! CORR_MAX - Indicates the correlation witnessed when AA match occurred
 */
#define GEN4PHY_FSK_STAT_CORR_MAX(x)             (((uint32_t)(((uint32_t)(x)) << GEN4PHY_FSK_STAT_CORR_MAX_SHIFT)) & GEN4PHY_FSK_STAT_CORR_MAX_MASK)

#define GEN4PHY_FSK_STAT_TOF_OFF_MASK            (0xF0000000U)
#define GEN4PHY_FSK_STAT_TOF_OFF_SHIFT           (28U)
/*! TOF_OFF - Timing offset for use in time-of-flight calculation.
 */
#define GEN4PHY_FSK_STAT_TOF_OFF(x)              (((uint32_t)(((uint32_t)(x)) << GEN4PHY_FSK_STAT_TOF_OFF_SHIFT)) & GEN4PHY_FSK_STAT_TOF_OFF_MASK)
/*! @} */

/*! @name LR_PD_CFG - PHY Long Range Preamble Detect Config */
/*! @{ */

#define GEN4PHY_LR_PD_CFG_CORR_TH_MASK           (0xFFU)
#define GEN4PHY_LR_PD_CFG_CORR_TH_SHIFT          (0U)
/*! CORR_TH - Correlation threshold applicable to preamble detection; uses (0,8,8) fixed-point format.
 */
#define GEN4PHY_LR_PD_CFG_CORR_TH(x)             (((uint32_t)(((uint32_t)(x)) << GEN4PHY_LR_PD_CFG_CORR_TH_SHIFT)) & GEN4PHY_LR_PD_CFG_CORR_TH_MASK)

#define GEN4PHY_LR_PD_CFG_FREQ_TH_MASK           (0x1F00U)
#define GEN4PHY_LR_PD_CFG_FREQ_TH_SHIFT          (8U)
/*! FREQ_TH - Threshold used to compare CFO estimates in the LR preamble detector; uses ufix5_En5 format.
 */
#define GEN4PHY_LR_PD_CFG_FREQ_TH(x)             (((uint32_t)(((uint32_t)(x)) << GEN4PHY_LR_PD_CFG_FREQ_TH_SHIFT)) & GEN4PHY_LR_PD_CFG_FREQ_TH_MASK)

#define GEN4PHY_LR_PD_CFG_NO_PEAKS_MASK          (0x30000U)
#define GEN4PHY_LR_PD_CFG_NO_PEAKS_SHIFT         (16U)
/*! NO_PEAKS - Number of consecutive correlation values that have to exceed the PD correlation
 *    threshold,for the same preamble phase, to assert preamble found;
 *  0b00..2 peaks;
 *  0b01..3 peaks;
 *  0b10..4 peaks;
 *  0b11..5 peaks;
 */
#define GEN4PHY_LR_PD_CFG_NO_PEAKS(x)            (((uint32_t)(((uint32_t)(x)) << GEN4PHY_LR_PD_CFG_NO_PEAKS_SHIFT)) & GEN4PHY_LR_PD_CFG_NO_PEAKS_MASK)
/*! @} */

/*! @name LR_PD_PH -  */
/*! @{ */

#define GEN4PHY_LR_PD_PH_REF0_MASK               (0x3FU)
#define GEN4PHY_LR_PD_PH_REF0_SHIFT              (0U)
/*! REF0 - Long range preamble reference waveform sample 12 (sfix6en5)
 */
#define GEN4PHY_LR_PD_PH_REF0(x)                 (((uint32_t)(((uint32_t)(x)) << GEN4PHY_LR_PD_PH_REF0_SHIFT)) & GEN4PHY_LR_PD_PH_REF0_MASK)

#define GEN4PHY_LR_PD_PH_REF1_MASK               (0x3F00U)
#define GEN4PHY_LR_PD_PH_REF1_SHIFT              (8U)
/*! REF1 - Long range preamble reference waveform sample 13 (sfix6en5)
 */
#define GEN4PHY_LR_PD_PH_REF1(x)                 (((uint32_t)(((uint32_t)(x)) << GEN4PHY_LR_PD_PH_REF1_SHIFT)) & GEN4PHY_LR_PD_PH_REF1_MASK)

#define GEN4PHY_LR_PD_PH_REF2_MASK               (0x3F0000U)
#define GEN4PHY_LR_PD_PH_REF2_SHIFT              (16U)
/*! REF2 - Long range preamble reference waveform sample 14 (sfix6en5)
 */
#define GEN4PHY_LR_PD_PH_REF2(x)                 (((uint32_t)(((uint32_t)(x)) << GEN4PHY_LR_PD_PH_REF2_SHIFT)) & GEN4PHY_LR_PD_PH_REF2_MASK)

#define GEN4PHY_LR_PD_PH_REF3_MASK               (0x3F000000U)
#define GEN4PHY_LR_PD_PH_REF3_SHIFT              (24U)
/*! REF3 - Long range preamble reference waveform sample 15 (sfix6en5)
 */
#define GEN4PHY_LR_PD_PH_REF3(x)                 (((uint32_t)(((uint32_t)(x)) << GEN4PHY_LR_PD_PH_REF3_SHIFT)) & GEN4PHY_LR_PD_PH_REF3_MASK)
/*! @} */

/* The count of GEN4PHY_LR_PD_PH */
#define GEN4PHY_LR_PD_PH_COUNT                   (4U)

/*! @name LR_PD_RO_PH -  */
/*! @{ */

#define GEN4PHY_LR_PD_RO_PH_REF0_MASK            (0x3FU)
#define GEN4PHY_LR_PD_RO_PH_REF0_SHIFT           (0U)
/*! REF0 - Long range preamble reference waveform sample 64 (sfix6en5)
 */
#define GEN4PHY_LR_PD_RO_PH_REF0(x)              (((uint32_t)(((uint32_t)(x)) << GEN4PHY_LR_PD_RO_PH_REF0_SHIFT)) & GEN4PHY_LR_PD_RO_PH_REF0_MASK)

#define GEN4PHY_LR_PD_RO_PH_REF1_MASK            (0x3F00U)
#define GEN4PHY_LR_PD_RO_PH_REF1_SHIFT           (8U)
/*! REF1 - Long range preamble reference waveform sample 65 (sfix6en5)
 */
#define GEN4PHY_LR_PD_RO_PH_REF1(x)              (((uint32_t)(((uint32_t)(x)) << GEN4PHY_LR_PD_RO_PH_REF1_SHIFT)) & GEN4PHY_LR_PD_RO_PH_REF1_MASK)

#define GEN4PHY_LR_PD_RO_PH_REF2_MASK            (0x3F0000U)
#define GEN4PHY_LR_PD_RO_PH_REF2_SHIFT           (16U)
/*! REF2 - Long range preamble reference waveform sample 66 (sfix6en5)
 */
#define GEN4PHY_LR_PD_RO_PH_REF2(x)              (((uint32_t)(((uint32_t)(x)) << GEN4PHY_LR_PD_RO_PH_REF2_SHIFT)) & GEN4PHY_LR_PD_RO_PH_REF2_MASK)

#define GEN4PHY_LR_PD_RO_PH_REF3_MASK            (0x3F000000U)
#define GEN4PHY_LR_PD_RO_PH_REF3_SHIFT           (24U)
/*! REF3 - Long range preamble reference waveform sample 67 (sfix6en5)
 */
#define GEN4PHY_LR_PD_RO_PH_REF3(x)              (((uint32_t)(((uint32_t)(x)) << GEN4PHY_LR_PD_RO_PH_REF3_SHIFT)) & GEN4PHY_LR_PD_RO_PH_REF3_MASK)
/*! @} */

/* The count of GEN4PHY_LR_PD_RO_PH */
#define GEN4PHY_LR_PD_RO_PH_COUNT                (13U)

/*! @name LR_AA_CFG - PHY Long Range AA Config */
/*! @{ */

#define GEN4PHY_LR_AA_CFG_AA_COR_THRESH_MASK     (0xFFU)
#define GEN4PHY_LR_AA_CFG_AA_COR_THRESH_SHIFT    (0U)
/*! AA_COR_THRESH - Threshold use to compare the correlation magnitude in the long-range AA correlator.
 */
#define GEN4PHY_LR_AA_CFG_AA_COR_THRESH(x)       (((uint32_t)(((uint32_t)(x)) << GEN4PHY_LR_AA_CFG_AA_COR_THRESH_SHIFT)) & GEN4PHY_LR_AA_CFG_AA_COR_THRESH_MASK)

#define GEN4PHY_LR_AA_CFG_AA_HAM_THRESH_MASK     (0x3F00U)
#define GEN4PHY_LR_AA_CFG_AA_HAM_THRESH_SHIFT    (8U)
/*! AA_HAM_THRESH - Threshold use to compare the Hamming distance, between reference coded sequence
 *    and received coded sequence, in the long-range AA correlator.
 */
#define GEN4PHY_LR_AA_CFG_AA_HAM_THRESH(x)       (((uint32_t)(((uint32_t)(x)) << GEN4PHY_LR_AA_CFG_AA_HAM_THRESH_SHIFT)) & GEN4PHY_LR_AA_CFG_AA_HAM_THRESH_MASK)

#define GEN4PHY_LR_AA_CFG_ACCESS_ADDR_HAM_MASK   (0x1F0000U)
#define GEN4PHY_LR_AA_CFG_ACCESS_ADDR_HAM_SHIFT  (16U)
/*! ACCESS_ADDR_HAM - Threshold use to compare the Hamming distance, between the reference AA
 *    sequence and the received Viterbi decoded AA sequence.
 */
#define GEN4PHY_LR_AA_CFG_ACCESS_ADDR_HAM(x)     (((uint32_t)(((uint32_t)(x)) << GEN4PHY_LR_AA_CFG_ACCESS_ADDR_HAM_SHIFT)) & GEN4PHY_LR_AA_CFG_ACCESS_ADDR_HAM_MASK)

#define GEN4PHY_LR_AA_CFG_AA_LR_CORR_GAIN_MASK   (0x3F000000U)
#define GEN4PHY_LR_AA_CFG_AA_LR_CORR_GAIN_SHIFT  (24U)
/*! AA_LR_CORR_GAIN - AA correlator gain. Format ufix6en3. This gain is applied to soft bits from
 *    the demodulator before they are used for address search synchronization.
 */
#define GEN4PHY_LR_AA_CFG_AA_LR_CORR_GAIN(x)     (((uint32_t)(((uint32_t)(x)) << GEN4PHY_LR_AA_CFG_AA_LR_CORR_GAIN_SHIFT)) & GEN4PHY_LR_AA_CFG_AA_LR_CORR_GAIN_MASK)
/*! @} */

/*! @name LR_STAT - PHY Long Range Status */
/*! @{ */

#define GEN4PHY_LR_STAT_DECODED_HAMM_DIST_MASK   (0x3FU)
#define GEN4PHY_LR_STAT_DECODED_HAMM_DIST_SHIFT  (0U)
/*! DECODED_HAMM_DIST - Hamming distance between the reference sequence and the Viterbi decoded received sequence
 */
#define GEN4PHY_LR_STAT_DECODED_HAMM_DIST(x)     (((uint32_t)(((uint32_t)(x)) << GEN4PHY_LR_STAT_DECODED_HAMM_DIST_SHIFT)) & GEN4PHY_LR_STAT_DECODED_HAMM_DIST_MASK)

#define GEN4PHY_LR_STAT_AA_FOUND_MASK            (0x40U)
#define GEN4PHY_LR_STAT_AA_FOUND_SHIFT           (6U)
/*! AA_FOUND - Indicates that a AA detect is active for both LR and uncoded.
 */
#define GEN4PHY_LR_STAT_AA_FOUND(x)              (((uint32_t)(((uint32_t)(x)) << GEN4PHY_LR_STAT_AA_FOUND_SHIFT)) & GEN4PHY_LR_STAT_AA_FOUND_MASK)

#define GEN4PHY_LR_STAT_CI_MASK                  (0x80U)
#define GEN4PHY_LR_STAT_CI_SHIFT                 (7U)
/*! CI - CI received.
 */
#define GEN4PHY_LR_STAT_CI(x)                    (((uint32_t)(((uint32_t)(x)) << GEN4PHY_LR_STAT_CI_SHIFT)) & GEN4PHY_LR_STAT_CI_MASK)

#define GEN4PHY_LR_STAT_CODED_HAMM_DIST_MASK     (0x7F00U)
#define GEN4PHY_LR_STAT_CODED_HAMM_DIST_SHIFT    (8U)
/*! CODED_HAMM_DIST - Hamming distance between the coded reference sequence and the coded received sequence.
 */
#define GEN4PHY_LR_STAT_CODED_HAMM_DIST(x)       (((uint32_t)(((uint32_t)(x)) << GEN4PHY_LR_STAT_CODED_HAMM_DIST_SHIFT)) & GEN4PHY_LR_STAT_CODED_HAMM_DIST_MASK)

#define GEN4PHY_LR_STAT_AA_CORR_MAX_MASK         (0xFF0000U)
#define GEN4PHY_LR_STAT_AA_CORR_MAX_SHIFT        (16U)
/*! AA_CORR_MAX - Indicates the AA correlation magnitude witnessed when AA match occurred
 */
#define GEN4PHY_LR_STAT_AA_CORR_MAX(x)           (((uint32_t)(((uint32_t)(x)) << GEN4PHY_LR_STAT_AA_CORR_MAX_SHIFT)) & GEN4PHY_LR_STAT_AA_CORR_MAX_MASK)

#define GEN4PHY_LR_STAT_CMAG_MAX_MASK            (0xFF000000U)
#define GEN4PHY_LR_STAT_CMAG_MAX_SHIFT           (24U)
/*! CMAG_MAX - Indicates the maximum preamble correlation magnitude during preamble found
 */
#define GEN4PHY_LR_STAT_CMAG_MAX(x)              (((uint32_t)(((uint32_t)(x)) << GEN4PHY_LR_STAT_CMAG_MAX_SHIFT)) & GEN4PHY_LR_STAT_CMAG_MAX_MASK)
/*! @} */

/*! @name SM_CFG - PHY State Machine Config */
/*! @{ */

#define GEN4PHY_SM_CFG_ACQ_MODE_MASK             (0x3U)
#define GEN4PHY_SM_CFG_ACQ_MODE_SHIFT            (0U)
/*! ACQ_MODE - Acquisition mode for non-coded reception
 *  0b00..Reserved
 *  0b01..Use preamble and verify a correlation peak, the synch at the symbol rate as symbol timing is established by the preamble acquisition
 *  0b10..Use synch only (which may incorporate part of the preamble)
 *  0b11..Use mainly the sync detection: Use a low threshold on the preamble detector and launch the synch
 *        detection only if the preamble has shown a recent peak
 */
#define GEN4PHY_SM_CFG_ACQ_MODE(x)               (((uint32_t)(((uint32_t)(x)) << GEN4PHY_SM_CFG_ACQ_MODE_SHIFT)) & GEN4PHY_SM_CFG_ACQ_MODE_MASK)

#define GEN4PHY_SM_CFG_EN_PHY_SM_EXT_RST_MASK    (0x4U)
#define GEN4PHY_SM_CFG_EN_PHY_SM_EXT_RST_SHIFT   (2U)
/*! EN_PHY_SM_EXT_RST - Enable PHY state-machine reset on the external reset port; Reserved, should keep 0.
 *  0b0..Reset is not allowed.
 *  0b1..Reset is allowed.
 */
#define GEN4PHY_SM_CFG_EN_PHY_SM_EXT_RST(x)      (((uint32_t)(((uint32_t)(x)) << GEN4PHY_SM_CFG_EN_PHY_SM_EXT_RST_SHIFT)) & GEN4PHY_SM_CFG_EN_PHY_SM_EXT_RST_MASK)

#define GEN4PHY_SM_CFG_AGC_FRZ_ON_PD_FOUND_ACQ1_LR_MASK (0x8U)
#define GEN4PHY_SM_CFG_AGC_FRZ_ON_PD_FOUND_ACQ1_LR_SHIFT (3U)
/*! AGC_FRZ_ON_PD_FOUND_ACQ1_LR - Specfies AGC freeze condition for non-coded acq.1 and Bluetooth LE long range.
 *  0b0..AGC freeze on AA found.
 *  0b1..AGC freeze asserted on PD found.
 */
#define GEN4PHY_SM_CFG_AGC_FRZ_ON_PD_FOUND_ACQ1_LR(x) (((uint32_t)(((uint32_t)(x)) << GEN4PHY_SM_CFG_AGC_FRZ_ON_PD_FOUND_ACQ1_LR_SHIFT)) & GEN4PHY_SM_CFG_AGC_FRZ_ON_PD_FOUND_ACQ1_LR_MASK)

#define GEN4PHY_SM_CFG_PH_BUFF_PTR_SYM_MASK      (0x30U)
#define GEN4PHY_SM_CFG_PH_BUFF_PTR_SYM_SHIFT     (4U)
/*! PH_BUFF_PTR_SYM - Phase buffer size to demodulator, long range only.
 */
#define GEN4PHY_SM_CFG_PH_BUFF_PTR_SYM(x)        (((uint32_t)(((uint32_t)(x)) << GEN4PHY_SM_CFG_PH_BUFF_PTR_SYM_SHIFT)) & GEN4PHY_SM_CFG_PH_BUFF_PTR_SYM_MASK)

#define GEN4PHY_SM_CFG_EARLY_PD_TIMEOUT_MASK     (0x3F00U)
#define GEN4PHY_SM_CFG_EARLY_PD_TIMEOUT_SHIFT    (8U)
/*! EARLY_PD_TIMEOUT - Time-out used to reset the AGC state-machine for the eventuality that an "PD
 *    found early" event occurs but it is not followed by an "PD found" event
 */
#define GEN4PHY_SM_CFG_EARLY_PD_TIMEOUT(x)       (((uint32_t)(((uint32_t)(x)) << GEN4PHY_SM_CFG_EARLY_PD_TIMEOUT_SHIFT)) & GEN4PHY_SM_CFG_EARLY_PD_TIMEOUT_MASK)

#define GEN4PHY_SM_CFG_AA_TIMEOUT_UNCODED_MASK   (0x3FF0000U)
#define GEN4PHY_SM_CFG_AA_TIMEOUT_UNCODED_SHIFT  (16U)
/*! AA_TIMEOUT_UNCODED - Time-out value for access address search for uncoded packets
 */
#define GEN4PHY_SM_CFG_AA_TIMEOUT_UNCODED(x)     (((uint32_t)(((uint32_t)(x)) << GEN4PHY_SM_CFG_AA_TIMEOUT_UNCODED_SHIFT)) & GEN4PHY_SM_CFG_AA_TIMEOUT_UNCODED_MASK)
/*! @} */

/*! @name MISC - PHY Misc Config */
/*! @{ */

#define GEN4PHY_MISC_RSSI_CORR_TH_MASK           (0xFFU)
#define GEN4PHY_MISC_RSSI_CORR_TH_SHIFT          (0U)
/*! RSSI_CORR_TH - Threshold use to compare a correlation magnitude value, computed in the
 *    acquisition block, in order to determine the correlation flag value provided by the PHY to the LQI
 *    computation block. Format is ufix8_En8
 */
#define GEN4PHY_MISC_RSSI_CORR_TH(x)             (((uint32_t)(((uint32_t)(x)) << GEN4PHY_MISC_RSSI_CORR_TH_SHIFT)) & GEN4PHY_MISC_RSSI_CORR_TH_MASK)

#define GEN4PHY_MISC_DMA_PAGE_SEL_MASK           (0x700U)
#define GEN4PHY_MISC_DMA_PAGE_SEL_SHIFT          (8U)
/*! DMA_PAGE_SEL - Select which DMA page is send out
 *  0b000..Select DMA PAGE 0 for M3C with cfo;
 *  0b001..Select DMA PAGE 1 for M3C with magnitude;
 *  0b010..Select DMA PAGE 2 for un-coded;
 *  0b011..Select DMA PAGE 3 for Long Range Preampble Detect;
 *  0b100..Select DMA PAGE 4 for Long Range AA Detect;
 */
#define GEN4PHY_MISC_DMA_PAGE_SEL(x)             (((uint32_t)(((uint32_t)(x)) << GEN4PHY_MISC_DMA_PAGE_SEL_SHIFT)) & GEN4PHY_MISC_DMA_PAGE_SEL_MASK)

#define GEN4PHY_MISC_ECO1_RSVD_MASK              (0xF800U)
#define GEN4PHY_MISC_ECO1_RSVD_SHIFT             (11U)
/*! ECO1_RSVD - Reserved. Must be programed as reset value 0.
 */
#define GEN4PHY_MISC_ECO1_RSVD(x)                (((uint32_t)(((uint32_t)(x)) << GEN4PHY_MISC_ECO1_RSVD_SHIFT)) & GEN4PHY_MISC_ECO1_RSVD_MASK)

#define GEN4PHY_MISC_PHY_CLK_CTRL_MASK           (0x3FF0000U)
#define GEN4PHY_MISC_PHY_CLK_CTRL_SHIFT          (16U)
/*! PHY_CLK_CTRL - Enables various clock gating features. Bits are individually decoded, so any combination is allowable.
 */
#define GEN4PHY_MISC_PHY_CLK_CTRL(x)             (((uint32_t)(((uint32_t)(x)) << GEN4PHY_MISC_PHY_CLK_CTRL_SHIFT)) & GEN4PHY_MISC_PHY_CLK_CTRL_MASK)

#define GEN4PHY_MISC_ECO2_RSVD_MASK              (0x3C000000U)
#define GEN4PHY_MISC_ECO2_RSVD_SHIFT             (26U)
/*! ECO2_RSVD - Reserved
 */
#define GEN4PHY_MISC_ECO2_RSVD(x)                (((uint32_t)(((uint32_t)(x)) << GEN4PHY_MISC_ECO2_RSVD_SHIFT)) & GEN4PHY_MISC_ECO2_RSVD_MASK)

#define GEN4PHY_MISC_DTEST_MUX_EN_MASK           (0x40000000U)
#define GEN4PHY_MISC_DTEST_MUX_EN_SHIFT          (30U)
/*! DTEST_MUX_EN - Reserved. Should be programed as reset value 0.
 */
#define GEN4PHY_MISC_DTEST_MUX_EN(x)             (((uint32_t)(((uint32_t)(x)) << GEN4PHY_MISC_DTEST_MUX_EN_SHIFT)) & GEN4PHY_MISC_DTEST_MUX_EN_MASK)

#define GEN4PHY_MISC_PHY_CLK_ON_MASK             (0x80000000U)
#define GEN4PHY_MISC_PHY_CLK_ON_SHIFT            (31U)
/*! PHY_CLK_ON - Force PHY clock ON
 */
#define GEN4PHY_MISC_PHY_CLK_ON(x)               (((uint32_t)(((uint32_t)(x)) << GEN4PHY_MISC_PHY_CLK_ON_SHIFT)) & GEN4PHY_MISC_PHY_CLK_ON_MASK)
/*! @} */

/*! @name STAT0 - PHY Status 0 */
/*! @{ */

#define GEN4PHY_STAT0_PD_FOUND_MASK              (0x1U)
#define GEN4PHY_STAT0_PD_FOUND_SHIFT             (0U)
/*! PD_FOUND - PD_FOUND for LR or uncoded
 */
#define GEN4PHY_STAT0_PD_FOUND(x)                (((uint32_t)(((uint32_t)(x)) << GEN4PHY_STAT0_PD_FOUND_SHIFT)) & GEN4PHY_STAT0_PD_FOUND_MASK)

#define GEN4PHY_STAT0_LR_DET_FLAG_MASK           (0x2U)
#define GEN4PHY_STAT0_LR_DET_FLAG_SHIFT          (1U)
/*! LR_DET_FLAG - Indicates Bluetooth LE long range was detected
 */
#define GEN4PHY_STAT0_LR_DET_FLAG(x)             (((uint32_t)(((uint32_t)(x)) << GEN4PHY_STAT0_LR_DET_FLAG_SHIFT)) & GEN4PHY_STAT0_LR_DET_FLAG_MASK)

#define GEN4PHY_STAT0_AA_MATCHED_MASK            (0x4U)
#define GEN4PHY_STAT0_AA_MATCHED_SHIFT           (2U)
/*! AA_MATCHED - Indicates AA was matched for LR or uncoded
 */
#define GEN4PHY_STAT0_AA_MATCHED(x)              (((uint32_t)(((uint32_t)(x)) << GEN4PHY_STAT0_AA_MATCHED_SHIFT)) & GEN4PHY_STAT0_AA_MATCHED_MASK)

#define GEN4PHY_STAT0_AA_FOUND_ID_MASK           (0x38U)
#define GEN4PHY_STAT0_AA_FOUND_ID_SHIFT          (3U)
/*! AA_FOUND_ID - Indicates which AA was matched for LR and uncode
 *  0b000..uncoded address 0 matched
 *  0b001..uncoded address 1 matched
 *  0b010..uncoded address 2 matched
 *  0b011..uncoded address 3 matched
 *  0b100..long range address matched
 */
#define GEN4PHY_STAT0_AA_FOUND_ID(x)             (((uint32_t)(((uint32_t)(x)) << GEN4PHY_STAT0_AA_FOUND_ID_SHIFT)) & GEN4PHY_STAT0_AA_FOUND_ID_MASK)

#define GEN4PHY_STAT0_DATA_RATE_MASK             (0xC0U)
#define GEN4PHY_STAT0_DATA_RATE_SHIFT            (6U)
/*! DATA_RATE - Indicates the data rate of received bit
 *  0b00..1Mbps
 *  0b01..2Mbps
 *  0b10..125kbps
 *  0b11..500kbps
 */
#define GEN4PHY_STAT0_DATA_RATE(x)               (((uint32_t)(((uint32_t)(x)) << GEN4PHY_STAT0_DATA_RATE_SHIFT)) & GEN4PHY_STAT0_DATA_RATE_MASK)

#define GEN4PHY_STAT0_FRAC_MASK                  (0x3F00U)
#define GEN4PHY_STAT0_FRAC_SHIFT                 (8U)
/*! FRAC - Indicates the fractional timing estimate determined in the acquisition block. Format is
 *    sfix6_en5(sign extend from sfix3_En2).
 */
#define GEN4PHY_STAT0_FRAC(x)                    (((uint32_t)(((uint32_t)(x)) << GEN4PHY_STAT0_FRAC_SHIFT)) & GEN4PHY_STAT0_FRAC_MASK)

#define GEN4PHY_STAT0_CFO_EST_MASK               (0x3FF0000U)
#define GEN4PHY_STAT0_CFO_EST_SHIFT              (16U)
/*! CFO_EST - Indicates the currently estimated CFO. Format is sfix10_en9(sign extend form sfix8_en9)
 */
#define GEN4PHY_STAT0_CFO_EST(x)                 (((uint32_t)(((uint32_t)(x)) << GEN4PHY_STAT0_CFO_EST_SHIFT)) & GEN4PHY_STAT0_CFO_EST_MASK)
/*! @} */

/*! @name STAT1 - PHY Status 1 */
/*! @{ */

#define GEN4PHY_STAT1_AA_BITS_MASK               (0xFFFFFFFFU)
#define GEN4PHY_STAT1_AA_BITS_SHIFT              (0U)
/*! AA_BITS - AA bits either received or programed
 */
#define GEN4PHY_STAT1_AA_BITS(x)                 (((uint32_t)(((uint32_t)(x)) << GEN4PHY_STAT1_AA_BITS_SHIFT)) & GEN4PHY_STAT1_AA_BITS_MASK)
/*! @} */

/*! @name STAT2 - PHY Status 2 */
/*! @{ */

#define GEN4PHY_STAT2_CNT_ANT_SW_MASK            (0x3U)
#define GEN4PHY_STAT2_CNT_ANT_SW_SHIFT           (0U)
/*! CNT_ANT_SW - Count of uncoded ANT switch event when FAD was enabled.
 */
#define GEN4PHY_STAT2_CNT_ANT_SW(x)              (((uint32_t)(((uint32_t)(x)) << GEN4PHY_STAT2_CNT_ANT_SW_SHIFT)) & GEN4PHY_STAT2_CNT_ANT_SW_MASK)

#define GEN4PHY_STAT2_CNT_UNCAA_TIMEOUT_MASK     (0xCU)
#define GEN4PHY_STAT2_CNT_UNCAA_TIMEOUT_SHIFT    (2U)
/*! CNT_UNCAA_TIMEOUT - Count of uncoded AA search timeout event
 */
#define GEN4PHY_STAT2_CNT_UNCAA_TIMEOUT(x)       (((uint32_t)(((uint32_t)(x)) << GEN4PHY_STAT2_CNT_UNCAA_TIMEOUT_SHIFT)) & GEN4PHY_STAT2_CNT_UNCAA_TIMEOUT_MASK)

#define GEN4PHY_STAT2_CNT_LRAA_TIMEOUT_MASK      (0x30U)
#define GEN4PHY_STAT2_CNT_LRAA_TIMEOUT_SHIFT     (4U)
/*! CNT_LRAA_TIMEOUT - Count of lang range AA search timeout event
 */
#define GEN4PHY_STAT2_CNT_LRAA_TIMEOUT(x)        (((uint32_t)(((uint32_t)(x)) << GEN4PHY_STAT2_CNT_LRAA_TIMEOUT_SHIFT)) & GEN4PHY_STAT2_CNT_LRAA_TIMEOUT_MASK)

#define GEN4PHY_STAT2_CNT_AACI_TIMEOUT_MASK      (0xC0U)
#define GEN4PHY_STAT2_CNT_AACI_TIMEOUT_SHIFT     (6U)
/*! CNT_AACI_TIMEOUT - Count of long range AACI detect timeout event
 */
#define GEN4PHY_STAT2_CNT_AACI_TIMEOUT(x)        (((uint32_t)(((uint32_t)(x)) << GEN4PHY_STAT2_CNT_AACI_TIMEOUT_SHIFT)) & GEN4PHY_STAT2_CNT_AACI_TIMEOUT_MASK)

#define GEN4PHY_STAT2_CNT_AGC_RST_MASK           (0x300U)
#define GEN4PHY_STAT2_CNT_AGC_RST_SHIFT          (8U)
/*! CNT_AGC_RST - Count of AGC soft reset event
 */
#define GEN4PHY_STAT2_CNT_AGC_RST(x)             (((uint32_t)(((uint32_t)(x)) << GEN4PHY_STAT2_CNT_AGC_RST_SHIFT)) & GEN4PHY_STAT2_CNT_AGC_RST_MASK)
/*! @} */

/*! @name PREPHY_MISC - PHY PrePHY Misc Config */
/*! @{ */

#define GEN4PHY_PREPHY_MISC_BUFF_PTR_LR_MASK     (0x1FU)
#define GEN4PHY_PREPHY_MISC_BUFF_PTR_LR_SHIFT    (0U)
/*! BUFF_PTR_LR - Pointer to the PrePHY IQ buffer for the reception of the long-range packets.
 */
#define GEN4PHY_PREPHY_MISC_BUFF_PTR_LR(x)       (((uint32_t)(((uint32_t)(x)) << GEN4PHY_PREPHY_MISC_BUFF_PTR_LR_SHIFT)) & GEN4PHY_PREPHY_MISC_BUFF_PTR_LR_MASK)

#define GEN4PHY_PREPHY_MISC_BUFF_PTR_GFSK_MASK   (0x1F00U)
#define GEN4PHY_PREPHY_MISC_BUFF_PTR_GFSK_SHIFT  (8U)
/*! BUFF_PTR_GFSK - Pointer to the PrePHY IQ buffer for the reception of the uncoded packets.
 */
#define GEN4PHY_PREPHY_MISC_BUFF_PTR_GFSK(x)     (((uint32_t)(((uint32_t)(x)) << GEN4PHY_PREPHY_MISC_BUFF_PTR_GFSK_SHIFT)) & GEN4PHY_PREPHY_MISC_BUFF_PTR_GFSK_MASK)
/*! @} */

/*! @name DMD_CTRL0 - PHY Demodulator Control 0 */
/*! @{ */

#define GEN4PHY_DMD_CTRL0_TED_ACT_WIN_MASK       (0x3U)
#define GEN4PHY_DMD_CTRL0_TED_ACT_WIN_SHIFT      (0U)
/*! TED_ACT_WIN - Active window size for the time tracking mechanism, expressed in symbols.
 */
#define GEN4PHY_DMD_CTRL0_TED_ACT_WIN(x)         (((uint32_t)(((uint32_t)(x)) << GEN4PHY_DMD_CTRL0_TED_ACT_WIN_SHIFT)) & GEN4PHY_DMD_CTRL0_TED_ACT_WIN_MASK)

#define GEN4PHY_DMD_CTRL0_FED_ACT_WIN_MASK       (0x300U)
#define GEN4PHY_DMD_CTRL0_FED_ACT_WIN_SHIFT      (8U)
/*! FED_ACT_WIN - Active window size for the frequency tracking mechanism, expressed in symbols.
 */
#define GEN4PHY_DMD_CTRL0_FED_ACT_WIN(x)         (((uint32_t)(((uint32_t)(x)) << GEN4PHY_DMD_CTRL0_FED_ACT_WIN_SHIFT)) & GEN4PHY_DMD_CTRL0_FED_ACT_WIN_MASK)

#define GEN4PHY_DMD_CTRL0_DREP_SCALE_FREQ_MASK   (0xF0000U)
#define GEN4PHY_DMD_CTRL0_DREP_SCALE_FREQ_SHIFT  (16U)
/*! DREP_SCALE_FREQ - Frequency domain signal scaling factor used by the de-repeater.
 */
#define GEN4PHY_DMD_CTRL0_DREP_SCALE_FREQ(x)     (((uint32_t)(((uint32_t)(x)) << GEN4PHY_DMD_CTRL0_DREP_SCALE_FREQ_SHIFT)) & GEN4PHY_DMD_CTRL0_DREP_SCALE_FREQ_MASK)

#define GEN4PHY_DMD_CTRL0_REPEAT_FACTOR_MASK     (0x700000U)
#define GEN4PHY_DMD_CTRL0_REPEAT_FACTOR_SHIFT    (20U)
/*! REPEAT_FACTOR - Repetition factor used by the de-repeater.
 */
#define GEN4PHY_DMD_CTRL0_REPEAT_FACTOR(x)       (((uint32_t)(((uint32_t)(x)) << GEN4PHY_DMD_CTRL0_REPEAT_FACTOR_SHIFT)) & GEN4PHY_DMD_CTRL0_REPEAT_FACTOR_MASK)

#define GEN4PHY_DMD_CTRL0_FED_ERR_SCALE_MASK     (0x3800000U)
#define GEN4PHY_DMD_CTRL0_FED_ERR_SCALE_SHIFT    (23U)
/*! FED_ERR_SCALE - Scaling factor used by the freqency tracking loop.
 */
#define GEN4PHY_DMD_CTRL0_FED_ERR_SCALE(x)       (((uint32_t)(((uint32_t)(x)) << GEN4PHY_DMD_CTRL0_FED_ERR_SCALE_SHIFT)) & GEN4PHY_DMD_CTRL0_FED_ERR_SCALE_MASK)

#define GEN4PHY_DMD_CTRL0_TERR_TRK_EN_MASK       (0x4000000U)
#define GEN4PHY_DMD_CTRL0_TERR_TRK_EN_SHIFT      (26U)
/*! TERR_TRK_EN - Enables time tracking in the demodulator.
 */
#define GEN4PHY_DMD_CTRL0_TERR_TRK_EN(x)         (((uint32_t)(((uint32_t)(x)) << GEN4PHY_DMD_CTRL0_TERR_TRK_EN_SHIFT)) & GEN4PHY_DMD_CTRL0_TERR_TRK_EN_MASK)

#define GEN4PHY_DMD_CTRL0_FERR_TRK_EN_MASK       (0x8000000U)
#define GEN4PHY_DMD_CTRL0_FERR_TRK_EN_SHIFT      (27U)
/*! FERR_TRK_EN - Enables frequency tracking in the demodulator.
 */
#define GEN4PHY_DMD_CTRL0_FERR_TRK_EN(x)         (((uint32_t)(((uint32_t)(x)) << GEN4PHY_DMD_CTRL0_FERR_TRK_EN_SHIFT)) & GEN4PHY_DMD_CTRL0_FERR_TRK_EN_MASK)

#define GEN4PHY_DMD_CTRL0_DREP_SINE_EN_MASK      (0x10000000U)
#define GEN4PHY_DMD_CTRL0_DREP_SINE_EN_SHIFT     (28U)
/*! DREP_SINE_EN - Flag used to enable the non-linear operation in the de-repeater.
 */
#define GEN4PHY_DMD_CTRL0_DREP_SINE_EN(x)        (((uint32_t)(((uint32_t)(x)) << GEN4PHY_DMD_CTRL0_DREP_SINE_EN_SHIFT)) & GEN4PHY_DMD_CTRL0_DREP_SINE_EN_MASK)

#define GEN4PHY_DMD_CTRL0_DEMOD_MOD_MASK         (0x60000000U)
#define GEN4PHY_DMD_CTRL0_DEMOD_MOD_SHIFT        (29U)
/*! DEMOD_MOD - Determines the number of taps used by the demodulator correlators;
 *  0b00..use 12 taps
 *  0b01..use 4 taps
 *  0b10..use 7 taps
 *  0b11..use 13 taps
 */
#define GEN4PHY_DMD_CTRL0_DEMOD_MOD(x)           (((uint32_t)(((uint32_t)(x)) << GEN4PHY_DMD_CTRL0_DEMOD_MOD_SHIFT)) & GEN4PHY_DMD_CTRL0_DEMOD_MOD_MASK)
/*! @} */

/*! @name DMD_CTRL1 - PHY Dmodulator Control 1 */
/*! @{ */

#define GEN4PHY_DMD_CTRL1_FED_IDLE_WIN_MASK      (0x3FFU)
#define GEN4PHY_DMD_CTRL1_FED_IDLE_WIN_SHIFT     (0U)
/*! FED_IDLE_WIN - Idle window size for the frequency tracking mechanism, expressed in symbols.
 */
#define GEN4PHY_DMD_CTRL1_FED_IDLE_WIN(x)        (((uint32_t)(((uint32_t)(x)) << GEN4PHY_DMD_CTRL1_FED_IDLE_WIN_SHIFT)) & GEN4PHY_DMD_CTRL1_FED_IDLE_WIN_MASK)

#define GEN4PHY_DMD_CTRL1_TED_ERR_SCALE_MASK     (0x3C00U)
#define GEN4PHY_DMD_CTRL1_TED_ERR_SCALE_SHIFT    (10U)
/*! TED_ERR_SCALE - Scaling factor used by the time tracking loop.
 */
#define GEN4PHY_DMD_CTRL1_TED_ERR_SCALE(x)       (((uint32_t)(((uint32_t)(x)) << GEN4PHY_DMD_CTRL1_TED_ERR_SCALE_SHIFT)) & GEN4PHY_DMD_CTRL1_TED_ERR_SCALE_MASK)

#define GEN4PHY_DMD_CTRL1_FED_IMM_MEAS_EN_MASK   (0x8000U)
#define GEN4PHY_DMD_CTRL1_FED_IMM_MEAS_EN_SHIFT  (15U)
/*! FED_IMM_MEAS_EN - Specifies whether the frequency tracking starts with an active window;
 *  0b0..start with idle window
 *  0b1..start with active window
 */
#define GEN4PHY_DMD_CTRL1_FED_IMM_MEAS_EN(x)     (((uint32_t)(((uint32_t)(x)) << GEN4PHY_DMD_CTRL1_FED_IMM_MEAS_EN_SHIFT)) & GEN4PHY_DMD_CTRL1_FED_IMM_MEAS_EN_MASK)

#define GEN4PHY_DMD_CTRL1_TED_IDLE_WIN_MASK      (0x3FF0000U)
#define GEN4PHY_DMD_CTRL1_TED_IDLE_WIN_SHIFT     (16U)
/*! TED_IDLE_WIN - Idle window size for the time tracking mechanism, expressed in symbols.
 */
#define GEN4PHY_DMD_CTRL1_TED_IDLE_WIN(x)        (((uint32_t)(((uint32_t)(x)) << GEN4PHY_DMD_CTRL1_TED_IDLE_WIN_SHIFT)) & GEN4PHY_DMD_CTRL1_TED_IDLE_WIN_MASK)

#define GEN4PHY_DMD_CTRL1_TTRK_INT_RANGE_MASK    (0x3C000000U)
#define GEN4PHY_DMD_CTRL1_TTRK_INT_RANGE_SHIFT   (26U)
/*! TTRK_INT_RANGE - Timing error correction interpolation range, expressed in samples. The value must equal or bigger than 1.
 */
#define GEN4PHY_DMD_CTRL1_TTRK_INT_RANGE(x)      (((uint32_t)(((uint32_t)(x)) << GEN4PHY_DMD_CTRL1_TTRK_INT_RANGE_SHIFT)) & GEN4PHY_DMD_CTRL1_TTRK_INT_RANGE_MASK)

#define GEN4PHY_DMD_CTRL1_TED_IMM_MEAS_EN_MASK   (0x80000000U)
#define GEN4PHY_DMD_CTRL1_TED_IMM_MEAS_EN_SHIFT  (31U)
/*! TED_IMM_MEAS_EN - Specifies whether the time tracking starts with an active window;
 *  0b0..start with idle window
 *  0b1..start with active window
 */
#define GEN4PHY_DMD_CTRL1_TED_IMM_MEAS_EN(x)     (((uint32_t)(((uint32_t)(x)) << GEN4PHY_DMD_CTRL1_TED_IMM_MEAS_EN_SHIFT)) & GEN4PHY_DMD_CTRL1_TED_IMM_MEAS_EN_MASK)
/*! @} */

/*! @name DMD_CTRL2 - PHY Demodulator Control 2 */
/*! @{ */

#define GEN4PHY_DMD_CTRL2_WAIT_DMD_LR_ADJ_MASK   (0xFU)
#define GEN4PHY_DMD_CTRL2_WAIT_DMD_LR_ADJ_SHIFT  (0U)
/*! WAIT_DMD_LR_ADJ - Reserved. Must be programed as reset value 1.
 */
#define GEN4PHY_DMD_CTRL2_WAIT_DMD_LR_ADJ(x)     (((uint32_t)(((uint32_t)(x)) << GEN4PHY_DMD_CTRL2_WAIT_DMD_LR_ADJ_SHIFT)) & GEN4PHY_DMD_CTRL2_WAIT_DMD_LR_ADJ_MASK)

#define GEN4PHY_DMD_CTRL2_WAIT_VIA_AFTER_AA_ADJ_MASK (0xF0U)
#define GEN4PHY_DMD_CTRL2_WAIT_VIA_AFTER_AA_ADJ_SHIFT (4U)
/*! WAIT_VIA_AFTER_AA_ADJ - Reserved. Must be programed as reset value 1.
 */
#define GEN4PHY_DMD_CTRL2_WAIT_VIA_AFTER_AA_ADJ(x) (((uint32_t)(((uint32_t)(x)) << GEN4PHY_DMD_CTRL2_WAIT_VIA_AFTER_AA_ADJ_SHIFT)) & GEN4PHY_DMD_CTRL2_WAIT_VIA_AFTER_AA_ADJ_MASK)

#define GEN4PHY_DMD_CTRL2_WAIT_DMD_CLKEN_ADJ_MASK (0xF00U)
#define GEN4PHY_DMD_CTRL2_WAIT_DMD_CLKEN_ADJ_SHIFT (8U)
/*! WAIT_DMD_CLKEN_ADJ - Reserved. Must be programed as reset value 1.
 */
#define GEN4PHY_DMD_CTRL2_WAIT_DMD_CLKEN_ADJ(x)  (((uint32_t)(((uint32_t)(x)) << GEN4PHY_DMD_CTRL2_WAIT_DMD_CLKEN_ADJ_SHIFT)) & GEN4PHY_DMD_CTRL2_WAIT_DMD_CLKEN_ADJ_MASK)
/*! @} */

/*! @name DMD_WAVE_REG0 -  */
/*! @{ */

#define GEN4PHY_DMD_WAVE_REG0_SMPL0_MASK         (0x3FU)
#define GEN4PHY_DMD_WAVE_REG0_SMPL0_SHIFT        (0U)
/*! SMPL0 - Demodulator waveform 7 sample 0 (sfix6en5)
 */
#define GEN4PHY_DMD_WAVE_REG0_SMPL0(x)           (((uint32_t)(((uint32_t)(x)) << GEN4PHY_DMD_WAVE_REG0_SMPL0_SHIFT)) & GEN4PHY_DMD_WAVE_REG0_SMPL0_MASK)

#define GEN4PHY_DMD_WAVE_REG0_SMPL1_MASK         (0xFC0U)
#define GEN4PHY_DMD_WAVE_REG0_SMPL1_SHIFT        (6U)
/*! SMPL1 - Demodulator waveform 7 sample 1 (sfix6en5)
 */
#define GEN4PHY_DMD_WAVE_REG0_SMPL1(x)           (((uint32_t)(((uint32_t)(x)) << GEN4PHY_DMD_WAVE_REG0_SMPL1_SHIFT)) & GEN4PHY_DMD_WAVE_REG0_SMPL1_MASK)

#define GEN4PHY_DMD_WAVE_REG0_SMPL2_MASK         (0x3F000U)
#define GEN4PHY_DMD_WAVE_REG0_SMPL2_SHIFT        (12U)
/*! SMPL2 - Demodulator waveform 7 sample 2 (sfix6en5)
 */
#define GEN4PHY_DMD_WAVE_REG0_SMPL2(x)           (((uint32_t)(((uint32_t)(x)) << GEN4PHY_DMD_WAVE_REG0_SMPL2_SHIFT)) & GEN4PHY_DMD_WAVE_REG0_SMPL2_MASK)

#define GEN4PHY_DMD_WAVE_REG0_SMPL3_MASK         (0xFC0000U)
#define GEN4PHY_DMD_WAVE_REG0_SMPL3_SHIFT        (18U)
/*! SMPL3 - Demodulator waveform 7 sample 3 (sfix6en5)
 */
#define GEN4PHY_DMD_WAVE_REG0_SMPL3(x)           (((uint32_t)(((uint32_t)(x)) << GEN4PHY_DMD_WAVE_REG0_SMPL3_SHIFT)) & GEN4PHY_DMD_WAVE_REG0_SMPL3_MASK)

#define GEN4PHY_DMD_WAVE_REG0_SMPL4_MASK         (0x3F000000U)
#define GEN4PHY_DMD_WAVE_REG0_SMPL4_SHIFT        (24U)
/*! SMPL4 - Demodulator waveform 7 sample 4 (sfix6en5)
 */
#define GEN4PHY_DMD_WAVE_REG0_SMPL4(x)           (((uint32_t)(((uint32_t)(x)) << GEN4PHY_DMD_WAVE_REG0_SMPL4_SHIFT)) & GEN4PHY_DMD_WAVE_REG0_SMPL4_MASK)
/*! @} */

/* The count of GEN4PHY_DMD_WAVE_REG0 */
#define GEN4PHY_DMD_WAVE_REG0_COUNT              (8U)

/*! @name DMD_WAVE_REG1 -  */
/*! @{ */

#define GEN4PHY_DMD_WAVE_REG1_SMPL5_MASK         (0x3FU)
#define GEN4PHY_DMD_WAVE_REG1_SMPL5_SHIFT        (0U)
/*! SMPL5 - Demodulator waveform 7 sample 5 (sfix6en5)
 */
#define GEN4PHY_DMD_WAVE_REG1_SMPL5(x)           (((uint32_t)(((uint32_t)(x)) << GEN4PHY_DMD_WAVE_REG1_SMPL5_SHIFT)) & GEN4PHY_DMD_WAVE_REG1_SMPL5_MASK)

#define GEN4PHY_DMD_WAVE_REG1_SMPL6_MASK         (0xFC0U)
#define GEN4PHY_DMD_WAVE_REG1_SMPL6_SHIFT        (6U)
/*! SMPL6 - Demodulator waveform 7 sample 6 (sfix6en5)
 */
#define GEN4PHY_DMD_WAVE_REG1_SMPL6(x)           (((uint32_t)(((uint32_t)(x)) << GEN4PHY_DMD_WAVE_REG1_SMPL6_SHIFT)) & GEN4PHY_DMD_WAVE_REG1_SMPL6_MASK)

#define GEN4PHY_DMD_WAVE_REG1_SMPL7_MASK         (0x3F000U)
#define GEN4PHY_DMD_WAVE_REG1_SMPL7_SHIFT        (12U)
/*! SMPL7 - Demodulator waveform 7 sample 7 (sfix6en5)
 */
#define GEN4PHY_DMD_WAVE_REG1_SMPL7(x)           (((uint32_t)(((uint32_t)(x)) << GEN4PHY_DMD_WAVE_REG1_SMPL7_SHIFT)) & GEN4PHY_DMD_WAVE_REG1_SMPL7_MASK)

#define GEN4PHY_DMD_WAVE_REG1_SMPL8_MASK         (0xFC0000U)
#define GEN4PHY_DMD_WAVE_REG1_SMPL8_SHIFT        (18U)
/*! SMPL8 - Demodulator waveform 7 sample 8 (sfix6en5)
 */
#define GEN4PHY_DMD_WAVE_REG1_SMPL8(x)           (((uint32_t)(((uint32_t)(x)) << GEN4PHY_DMD_WAVE_REG1_SMPL8_SHIFT)) & GEN4PHY_DMD_WAVE_REG1_SMPL8_MASK)

#define GEN4PHY_DMD_WAVE_REG1_SMPL9_MASK         (0x3F000000U)
#define GEN4PHY_DMD_WAVE_REG1_SMPL9_SHIFT        (24U)
/*! SMPL9 - Demodulator waveform 7 sample 9 (sfix6en5)
 */
#define GEN4PHY_DMD_WAVE_REG1_SMPL9(x)           (((uint32_t)(((uint32_t)(x)) << GEN4PHY_DMD_WAVE_REG1_SMPL9_SHIFT)) & GEN4PHY_DMD_WAVE_REG1_SMPL9_MASK)
/*! @} */

/* The count of GEN4PHY_DMD_WAVE_REG1 */
#define GEN4PHY_DMD_WAVE_REG1_COUNT              (8U)

/*! @name DMD_WAVE_REG2 -  */
/*! @{ */

#define GEN4PHY_DMD_WAVE_REG2_SMPL10_MASK        (0x3FU)
#define GEN4PHY_DMD_WAVE_REG2_SMPL10_SHIFT       (0U)
/*! SMPL10 - Demodulator waveform 7 sample 10 (sfix6en5)
 */
#define GEN4PHY_DMD_WAVE_REG2_SMPL10(x)          (((uint32_t)(((uint32_t)(x)) << GEN4PHY_DMD_WAVE_REG2_SMPL10_SHIFT)) & GEN4PHY_DMD_WAVE_REG2_SMPL10_MASK)

#define GEN4PHY_DMD_WAVE_REG2_SMPL11_MASK        (0xFC0U)
#define GEN4PHY_DMD_WAVE_REG2_SMPL11_SHIFT       (6U)
/*! SMPL11 - Demodulator waveform 7 sample 11 (sfix6en5)
 */
#define GEN4PHY_DMD_WAVE_REG2_SMPL11(x)          (((uint32_t)(((uint32_t)(x)) << GEN4PHY_DMD_WAVE_REG2_SMPL11_SHIFT)) & GEN4PHY_DMD_WAVE_REG2_SMPL11_MASK)

#define GEN4PHY_DMD_WAVE_REG2_SMPL12_MASK        (0x3F000U)
#define GEN4PHY_DMD_WAVE_REG2_SMPL12_SHIFT       (12U)
/*! SMPL12 - Demodulator waveform 7 sample 12 (sfix6en5)
 */
#define GEN4PHY_DMD_WAVE_REG2_SMPL12(x)          (((uint32_t)(((uint32_t)(x)) << GEN4PHY_DMD_WAVE_REG2_SMPL12_SHIFT)) & GEN4PHY_DMD_WAVE_REG2_SMPL12_MASK)
/*! @} */

/* The count of GEN4PHY_DMD_WAVE_REG2 */
#define GEN4PHY_DMD_WAVE_REG2_COUNT              (8U)

/*! @name DMDAA_CTRL - PHY Demodulator Based SFD Confirmation control register. */
/*! @{ */

#define GEN4PHY_DMDAA_CTRL_DMDAA_HAMM_LP_MASK    (0x7U)
#define GEN4PHY_DMDAA_CTRL_DMDAA_HAMM_LP_SHIFT   (0U)
/*! DMDAA_HAMM_LP - Maximum hamming distance from the given AA pattern that may still be accepted as
 *    a match in low power case; valid range [0,7].
 */
#define GEN4PHY_DMDAA_CTRL_DMDAA_HAMM_LP(x)      (((uint32_t)(((uint32_t)(x)) << GEN4PHY_DMDAA_CTRL_DMDAA_HAMM_LP_SHIFT)) & GEN4PHY_DMDAA_CTRL_DMDAA_HAMM_LP_MASK)

#define GEN4PHY_DMDAA_CTRL_DMDAA_HAMM_HP_MASK    (0x38U)
#define GEN4PHY_DMDAA_CTRL_DMDAA_HAMM_HP_SHIFT   (3U)
/*! DMDAA_HAMM_HP - Maximum hamming distance from the given AA pattern that may still be accepted as
 *    a match in high power case; valid range [0,7].
 */
#define GEN4PHY_DMDAA_CTRL_DMDAA_HAMM_HP(x)      (((uint32_t)(((uint32_t)(x)) << GEN4PHY_DMDAA_CTRL_DMDAA_HAMM_HP_SHIFT)) & GEN4PHY_DMDAA_CTRL_DMDAA_HAMM_HP_MASK)

#define GEN4PHY_DMDAA_CTRL_HIPOW_DIS_OVRD_MASK   (0x40U)
#define GEN4PHY_DMDAA_CTRL_HIPOW_DIS_OVRD_SHIFT  (6U)
/*! HIPOW_DIS_OVRD - Override the feature: disable DMDAA when power sensitivity is higher;
 *  0b0..disable override, DMDAA disabled when power is high
 *  0b1..enable override, DMDAA enabled when power is high
 */
#define GEN4PHY_DMDAA_CTRL_HIPOW_DIS_OVRD(x)     (((uint32_t)(((uint32_t)(x)) << GEN4PHY_DMDAA_CTRL_HIPOW_DIS_OVRD_SHIFT)) & GEN4PHY_DMDAA_CTRL_HIPOW_DIS_OVRD_MASK)

#define GEN4PHY_DMDAA_CTRL_DMDAA_EN_MASK         (0x80U)
#define GEN4PHY_DMDAA_CTRL_DMDAA_EN_SHIFT        (7U)
/*! DMDAA_EN - Enables Demodulator Based SFD Confirmation;
 *  0b0..disable
 *  0b1..enable
 */
#define GEN4PHY_DMDAA_CTRL_DMDAA_EN(x)           (((uint32_t)(((uint32_t)(x)) << GEN4PHY_DMDAA_CTRL_DMDAA_EN_SHIFT)) & GEN4PHY_DMDAA_CTRL_DMDAA_EN_MASK)
/*! @} */

/*! @name RTT_STAT - High resolution Time-Of-Flight calculation Status. */
/*! @{ */

#define GEN4PHY_RTT_STAT_RTT_CFO_MASK            (0xFFFFU)
#define GEN4PHY_RTT_STAT_RTT_CFO_SHIFT           (0U)
/*! RTT_CFO - The high accuracy CFO computed by the HARTT block through the CORDIC algorithm.
 */
#define GEN4PHY_RTT_STAT_RTT_CFO(x)              (((uint32_t)(((uint32_t)(x)) << GEN4PHY_RTT_STAT_RTT_CFO_SHIFT)) & GEN4PHY_RTT_STAT_RTT_CFO_MASK)

#define GEN4PHY_RTT_STAT_RTT_P_DELTA_MASK        (0x3FF0000U)
#define GEN4PHY_RTT_STAT_RTT_P_DELTA_SHIFT       (16U)
/*! RTT_P_DELTA - Difference between the squared correlation magnitude values, pm-pp provided by the HARTT block, format is sfix10En9.
 */
#define GEN4PHY_RTT_STAT_RTT_P_DELTA(x)          (((uint32_t)(((uint32_t)(x)) << GEN4PHY_RTT_STAT_RTT_P_DELTA_SHIFT)) & GEN4PHY_RTT_STAT_RTT_P_DELTA_MASK)

#define GEN4PHY_RTT_STAT_RTT_DIST_SAT_MASK       (0xC000000U)
#define GEN4PHY_RTT_STAT_RTT_DIST_SAT_SHIFT      (26U)
/*! RTT_DIST_SAT - Computed Hamming distance saturated to 2 bits, format is ufix2.
 */
#define GEN4PHY_RTT_STAT_RTT_DIST_SAT(x)         (((uint32_t)(((uint32_t)(x)) << GEN4PHY_RTT_STAT_RTT_DIST_SAT_SHIFT)) & GEN4PHY_RTT_STAT_RTT_DIST_SAT_MASK)

#define GEN4PHY_RTT_STAT_RTT_INT_ADJ_MASK        (0x30000000U)
#define GEN4PHY_RTT_STAT_RTT_INT_ADJ_SHIFT       (28U)
/*! RTT_INT_ADJ - An integer adjustment of the timing which takes a value different of 0 when the
 *    early-late mechanism in the HARTT block chooses a peak different of the one chosen in the
 *    acquisition module (possible values are {-1,0,+1}).
 */
#define GEN4PHY_RTT_STAT_RTT_INT_ADJ(x)          (((uint32_t)(((uint32_t)(x)) << GEN4PHY_RTT_STAT_RTT_INT_ADJ_SHIFT)) & GEN4PHY_RTT_STAT_RTT_INT_ADJ_MASK)

#define GEN4PHY_RTT_STAT_RTT_FOUND_MASK          (0x40000000U)
#define GEN4PHY_RTT_STAT_RTT_FOUND_SHIFT         (30U)
/*! RTT_FOUND - Flag that indicates that the HARTT operation is done and a valid PN pattern was detected.
 */
#define GEN4PHY_RTT_STAT_RTT_FOUND(x)            (((uint32_t)(((uint32_t)(x)) << GEN4PHY_RTT_STAT_RTT_FOUND_SHIFT)) & GEN4PHY_RTT_STAT_RTT_FOUND_MASK)
/*! @} */

/*! @name RTT_CTRL - PHY RTT control register. */
/*! @{ */

#define GEN4PHY_RTT_CTRL_HA_RTT_THRESHOLD_MASK   (0x1FFU)
#define GEN4PHY_RTT_CTRL_HA_RTT_THRESHOLD_SHIFT  (0U)
/*! HA_RTT_THRESHOLD - threshold used to validate a HA RTT result.
 */
#define GEN4PHY_RTT_CTRL_HA_RTT_THRESHOLD(x)     (((uint32_t)(((uint32_t)(x)) << GEN4PHY_RTT_CTRL_HA_RTT_THRESHOLD_SHIFT)) & GEN4PHY_RTT_CTRL_HA_RTT_THRESHOLD_MASK)

#define GEN4PHY_RTT_CTRL_FIRST_PDU_BIT_MASK      (0x1000U)
#define GEN4PHY_RTT_CTRL_FIRST_PDU_BIT_SHIFT     (12U)
/*! FIRST_PDU_BIT - is programmed by software - used for regular packets high accuracy RTT;
 */
#define GEN4PHY_RTT_CTRL_FIRST_PDU_BIT(x)        (((uint32_t)(((uint32_t)(x)) << GEN4PHY_RTT_CTRL_FIRST_PDU_BIT_SHIFT)) & GEN4PHY_RTT_CTRL_FIRST_PDU_BIT_MASK)

#define GEN4PHY_RTT_CTRL_RTT_SEQ_LEN_MASK        (0x2000U)
#define GEN4PHY_RTT_CTRL_RTT_SEQ_LEN_SHIFT       (13U)
/*! RTT_SEQ_LEN - can be either 32 (when 0) or 64 bits (when 1) depending on the RTT configuration;
 */
#define GEN4PHY_RTT_CTRL_RTT_SEQ_LEN(x)          (((uint32_t)(((uint32_t)(x)) << GEN4PHY_RTT_CTRL_RTT_SEQ_LEN_SHIFT)) & GEN4PHY_RTT_CTRL_RTT_SEQ_LEN_MASK)

#define GEN4PHY_RTT_CTRL_OVERRD_PROGR_AA_MASK    (0x4000U)
#define GEN4PHY_RTT_CTRL_OVERRD_PROGR_AA_SHIFT   (14U)
/*! OVERRD_PROGR_AA - Enables overriding the programmed AA bits with the PN sequence used by RTT;
 */
#define GEN4PHY_RTT_CTRL_OVERRD_PROGR_AA(x)      (((uint32_t)(((uint32_t)(x)) << GEN4PHY_RTT_CTRL_OVERRD_PROGR_AA_SHIFT)) & GEN4PHY_RTT_CTRL_OVERRD_PROGR_AA_MASK)

#define GEN4PHY_RTT_CTRL_EN_HIGH_ACC_RTT_MASK    (0x8000U)
#define GEN4PHY_RTT_CTRL_EN_HIGH_ACC_RTT_SHIFT   (15U)
/*! EN_HIGH_ACC_RTT - enables the use of the HA RTT block;
 */
#define GEN4PHY_RTT_CTRL_EN_HIGH_ACC_RTT(x)      (((uint32_t)(((uint32_t)(x)) << GEN4PHY_RTT_CTRL_EN_HIGH_ACC_RTT_SHIFT)) & GEN4PHY_RTT_CTRL_EN_HIGH_ACC_RTT_MASK)
/*! @} */

/*! @name RTT_REF - PHY RTT reference register. */
/*! @{ */

#define GEN4PHY_RTT_REF_FM_REF_010_MASK          (0xFFU)
#define GEN4PHY_RTT_REF_FM_REF_010_SHIFT         (0U)
/*! FM_REF_010 - Contextual values used to derive the FM reference ha_rtt_threshold .
 */
#define GEN4PHY_RTT_REF_FM_REF_010(x)            (((uint32_t)(((uint32_t)(x)) << GEN4PHY_RTT_REF_FM_REF_010_SHIFT)) & GEN4PHY_RTT_REF_FM_REF_010_MASK)

#define GEN4PHY_RTT_REF_FM_REF_110_MASK          (0xFF00U)
#define GEN4PHY_RTT_REF_FM_REF_110_SHIFT         (8U)
/*! FM_REF_110 - Contextual values used to derive the FM reference ha_rtt_threshold .
 */
#define GEN4PHY_RTT_REF_FM_REF_110(x)            (((uint32_t)(((uint32_t)(x)) << GEN4PHY_RTT_REF_FM_REF_110_SHIFT)) & GEN4PHY_RTT_REF_FM_REF_110_MASK)

#define GEN4PHY_RTT_REF_FM_REF_111_MASK          (0xFF0000U)
#define GEN4PHY_RTT_REF_FM_REF_111_SHIFT         (16U)
/*! FM_REF_111 - Contextual values used to derive the FM reference ha_rtt_threshold .
 */
#define GEN4PHY_RTT_REF_FM_REF_111(x)            (((uint32_t)(((uint32_t)(x)) << GEN4PHY_RTT_REF_FM_REF_111_SHIFT)) & GEN4PHY_RTT_REF_FM_REF_111_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group GEN4PHY_Register_Masks */


/* GEN4PHY - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral XCVR_2P4GHZ_PHY base address */
  #define XCVR_2P4GHZ_PHY_BASE                     (0x58A07600u)
  /** Peripheral XCVR_2P4GHZ_PHY base address */
  #define XCVR_2P4GHZ_PHY_BASE_NS                  (0x48A07600u)
  /** Peripheral XCVR_2P4GHZ_PHY base pointer */
  #define XCVR_2P4GHZ_PHY                          ((GEN4PHY_Type *)XCVR_2P4GHZ_PHY_BASE)
  /** Peripheral XCVR_2P4GHZ_PHY base pointer */
  #define XCVR_2P4GHZ_PHY_NS                       ((GEN4PHY_Type *)XCVR_2P4GHZ_PHY_BASE_NS)
  /** Array initializer of GEN4PHY peripheral base addresses */
  #define GEN4PHY_BASE_ADDRS                       { XCVR_2P4GHZ_PHY_BASE }
  /** Array initializer of GEN4PHY peripheral base pointers */
  #define GEN4PHY_BASE_PTRS                        { XCVR_2P4GHZ_PHY }
  /** Array initializer of GEN4PHY peripheral base addresses */
  #define GEN4PHY_BASE_ADDRS_NS                    { XCVR_2P4GHZ_PHY_BASE_NS }
  /** Array initializer of GEN4PHY peripheral base pointers */
  #define GEN4PHY_BASE_PTRS_NS                     { XCVR_2P4GHZ_PHY_NS }
#else
  /** Peripheral XCVR_2P4GHZ_PHY base address */
  #define XCVR_2P4GHZ_PHY_BASE                     (0x48A07600u)
  /** Peripheral XCVR_2P4GHZ_PHY base pointer */
  #define XCVR_2P4GHZ_PHY                          ((GEN4PHY_Type *)XCVR_2P4GHZ_PHY_BASE)
  /** Array initializer of GEN4PHY peripheral base addresses */
  #define GEN4PHY_BASE_ADDRS                       { XCVR_2P4GHZ_PHY_BASE }
  /** Array initializer of GEN4PHY peripheral base pointers */
  #define GEN4PHY_BASE_PTRS                        { XCVR_2P4GHZ_PHY }
#endif

/*!
 * @}
 */ /* end of group GEN4PHY_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- GENFSK Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup GENFSK_Peripheral_Access_Layer GENFSK Peripheral Access Layer
 * @{
 */

/** GENFSK - Register Layout Typedef */
typedef struct {
  __IO uint32_t IRQ_CTRL;                          /**< IRQ CONTROL, offset: 0x0 */
  __I  uint32_t EVENT_TMR;                         /**< EVENT TIMER, offset: 0x4 */
  __IO uint32_t T1_CMP;                            /**< T1 COMPARE, offset: 0x8 */
  __IO uint32_t T2_CMP;                            /**< T2 COMPARE, offset: 0xC */
  __I  uint32_t TIMESTAMP;                         /**< TIMESTAMP, offset: 0x10 */
  __IO uint32_t XCVR_CTRL;                         /**< TRANSCEIVER CONTROL, offset: 0x14 */
  __I  uint32_t XCVR_STS;                          /**< TRANSCEIVER STATUS, offset: 0x18 */
  __IO uint32_t XCVR_CFG;                          /**< TRANSCEIVER CONFIGURATION, offset: 0x1C */
  __IO uint32_t CHANNEL_NUM0;                      /**< CHANNEL NUMBER 0, offset: 0x20 */
  __IO uint32_t TX_POWER;                          /**< TRANSMIT POWER, offset: 0x24 */
  __IO uint32_t NTW_ADR_CTRL;                      /**< NETWORK ADDRESS CONTROL, offset: 0x28 */
  __IO uint32_t NTW_ADR_0;                         /**< NETWORK ADDRESS 0, offset: 0x2C */
  __IO uint32_t NTW_ADR_1;                         /**< NETWORK ADDRESS 1, offset: 0x30 */
  __IO uint32_t NTW_ADR_2;                         /**< NETWORK ADDRESS 2, offset: 0x34 */
  __IO uint32_t NTW_ADR_3;                         /**< NETWORK ADDRESS 3, offset: 0x38 */
  __IO uint32_t RX_WATERMARK;                      /**< RECEIVE WATERMARK, offset: 0x3C */
  __IO uint32_t DSM_CTRL;                          /**< DSM CONTROL, offset: 0x40 */
  __I  uint32_t PART_ID;                           /**< PART ID, offset: 0x44 */
  __IO uint32_t SLOT_PRELOAD;                      /**< SLOT PRELOAD, offset: 0x48 */
  __IO uint32_t SLOT_TIME;                         /**< SLOT TIME, offset: 0x4C */
  __IO uint32_t TURNAROUND_TIME;                   /**< TURNAROUND TIME, offset: 0x50 */
  __IO uint32_t ACKDELAY;                          /**< ACK DELAY, offset: 0x54 */
  __IO uint32_t RXDELAY;                           /**< RX DELAY, offset: 0x58 */
  __IO uint32_t TXDELAY;                           /**< TX DELAY, offset: 0x5C */
  __IO uint32_t PACKET_CFG;                        /**< PACKET CONFIGURATION, offset: 0x60 */
  __IO uint32_t H0_CFG;                            /**< H0 CONFIGURATION, offset: 0x64 */
  __IO uint32_t H1_CFG;                            /**< H1 CONFIGURATION, offset: 0x68 */
  __IO uint32_t CRC_CFG;                           /**< CRC CONFIGURATION, offset: 0x6C */
  __IO uint32_t LENGTH_ADJ;                        /**< LENGTH ADJUSTMENT, offset: 0x70 */
  __I  uint32_t TIMESTAMP_RX_DONE;                 /**< TIMESTAMP_RX_DONE, offset: 0x74 */
  __I  uint32_t TIMESTAMP_TX_DONE;                 /**< TIMESTAMP_TX_DONE, offset: 0x78 */
  __IO uint32_t MULT_PKT_CTRL;                     /**< MULT_PKT_CTRL, offset: 0x7C */
  __IO uint32_t RPA_WL_STATUS;                     /**< RPA AND WHITE LIST STATUS, offset: 0x80 */
  __IO uint32_t LENGTH_MAX;                        /**< MAXIMUM LENGTH, offset: 0x84 */
  __O  uint32_t EVENT_TMR_LD;                      /**< EVENT TIMER LOAD, offset: 0x88 */
  __O  uint32_t EVENT_TMR_ADD;                     /**< EVENT TIMER ADD, offset: 0x8C */
  __IO uint32_t ENH_FEATURE;                       /**< ENHANCED FEATURES, offset: 0x90 */
  __IO uint32_t RX_FRAME_FILTER;                   /**< RECEIVE FRAME FILTER, offset: 0x94 */
  __IO uint32_t FILTERFAIL_CODE;                   /**< FILTER FAIL CODE, offset: 0x98 */
  union {                                          /* offset: 0x9C */
    __IO uint32_t LENIENCY_LSB;                      /**< LENIENCY LSB, offset: 0x9C */
    __IO uint32_t RPA_CTRL;                          /**< RPA CONTROL, offset: 0x9C */
  };
  union {                                          /* offset: 0xA0 */
    __IO uint32_t LENIENCY_MSB;                      /**< LENIENCY MSB, offset: 0xA0 */
    __IO uint32_t WL_CTRL;                           /**< WHITE LIST CONTROL, offset: 0xA0 */
  };
  __IO uint32_t DUAL_PAN_CTRL;                     /**< DUAL PAN CONTROL, offset: 0xA4 */
  union {                                          /* offset: 0xA8 */
    __IO uint32_t GTM_PDU;                           /**< GTM MODE PDU, offset: 0xA8 */
    __IO uint32_t MACSHORTADDRS1;                    /**< MAC SHORT ADDRESS FOR PAN1, offset: 0xA8 */
    __IO uint32_t WL_VALID_ENTRY1;                   /**< VALID ENTRY OF WHITE LIST 1, offset: 0xA8 */
  };
  union {                                          /* offset: 0xAC */
    __IO uint32_t DIRECT_PEER_ADDR_LSB;              /**< DIRECT_PEER_ADDR[31:0], offset: 0xAC */
    __IO uint32_t GTM_CFG;                           /**< GTM MODE CONFIGURATION, offset: 0xAC */
    __IO uint32_t MACLONGADDRS1_LSB;                 /**< MAC LONG ADDRESS 1 LSB, offset: 0xAC */
  };
  union {                                          /* offset: 0xB0 */
    __IO uint32_t DIRECT_PEER_ADDR_MSB;              /**< DIRECT_PEER_ADDR[47:32], offset: 0xB0 */
    __IO uint32_t GTM_IPD;                           /**< GTM MODE INTER-PACKET DURATION, offset: 0xB0 */
    __IO uint32_t MACLONGADDRS1_MSB;                 /**< MAC LONG ADDRESS 1 MSB, offset: 0xB0 */
  };
  __IO uint32_t CHANNEL_NUM1;                      /**< CHANNEL NUMBER 1, offset: 0xB4 */
  union {                                          /* offset: 0xB8 */
    __IO uint32_t MACSHORTADDRS0;                    /**< MAC SHORT ADDRESS 0, offset: 0xB8 */
    __IO uint32_t WL_VALID_ENTRY0;                   /**< VALID ENTRY OF WHITE LIST 0, offset: 0xB8 */
  };
  union {                                          /* offset: 0xBC */
    __IO uint32_t GTM_FIRST_SFD2WD;                  /**< GTM MODE TIME OF FIRST SFD FOUND TO FORCE RX WARMDOWN, offset: 0xBC */
    __IO uint32_t MACLONGADDRS0_LSB;                 /**< MAC LONG ADDRESS 0 LSB, offset: 0xBC */
    __IO uint32_t WL_SEARCH_ADDR_LSB;                /**< WL_SEARCH_ADDR[31:0], offset: 0xBC */
  };
  union {                                          /* offset: 0xC0 */
    __IO uint32_t GTM_RX_RECYCLE_TIME;               /**< GTM MODE RX RECYCLE TIME, offset: 0xC0 */
    __IO uint32_t MACLONGADDRS0_MSB;                 /**< MAC LONG ADDRESS 0 MSB, offset: 0xC0 */
    __IO uint32_t WL_SEARCH_ADDR_MSB;                /**< WL_SEARCH_ADDR[47:32], offset: 0xC0 */
  };
  __IO uint32_t CCA_LQI_CTRL;                      /**< CCA AND LQI CONTROL, offset: 0xC4 */
  __I  uint32_t WARMUP_TIME;                       /**< TX/RX WARMUP TIME, offset: 0xC8 */
  __IO uint32_t RXEN_DLY;                          /**< RX_EN Delay Time, offset: 0xCC */
       uint8_t RESERVED_0[4];
  __IO uint32_t SAM_CTRL;                          /**< SAM CONTROL, offset: 0xD4 */
  __IO uint32_t SAM_TABLE;                         /**< SOURCE ADDRESS MANAGEMENT TABLE, offset: 0xD8 */
  __I  uint32_t SAM_MATCH;                         /**< SOURCE ADDRESS MANAGEMENT MATCH, offset: 0xDC */
  __I  uint32_t SAM_FREE_IDX;                      /**< SAM FREE INDEX, offset: 0xE0 */
  __IO uint32_t MISC1;                             /**< MISCELLANEOUS(1), offset: 0xE4 */
  __I  uint32_t SEQ_STS;                           /**< SEQUENCE STATUS, offset: 0xE8 */
  __IO uint32_t PHR_MISC;                          /**< PHR MISCELLANEOUS, offset: 0xEC */
  __IO uint32_t GTM_CTRL;                          /**< GTM CONTROL, offset: 0xF0 */
  __I  uint32_t GTM_BAD_CNT;                       /**< GTM BAD PACKET COUNTER, offset: 0xF4 */
  __I  uint32_t GTM_GOOD_CNT;                      /**< GTM GOOD PACKET COUNTER, offset: 0xF8 */
  __I  uint32_t GTM_PKT_CNT;                       /**< GTM PACKET COUNTER, offset: 0xFC */
  __IO uint32_t COEX_CTRL;                         /**< COEXISTENCE CONTROL, offset: 0x100 */
  __IO uint32_t COEX_PRIORITY;                     /**< COEXISTENCE PRIORITY, offset: 0x104 */
  __IO uint32_t IRQ_CTRL2;                         /**< IRQ CONTROL 2, offset: 0x108 */
} GENFSK_Type;

/* ----------------------------------------------------------------------------
   -- GENFSK Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup GENFSK_Register_Masks GENFSK Register Masks
 * @{
 */

/*! @name IRQ_CTRL - IRQ CONTROL */
/*! @{ */

#define GENFSK_IRQ_CTRL_SEQ_END_IRQ_MASK         (0x1U)
#define GENFSK_IRQ_CTRL_SEQ_END_IRQ_SHIFT        (0U)
/*! SEQ_END_IRQ - Sequence End Interrupt
 *  0b0..Sequence End Interrupt is not asserted.
 *  0b1..Sequence End Interrupt is asserted.
 */
#define GENFSK_IRQ_CTRL_SEQ_END_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_SEQ_END_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_SEQ_END_IRQ_MASK)

#define GENFSK_IRQ_CTRL_TX_IRQ_MASK              (0x2U)
#define GENFSK_IRQ_CTRL_TX_IRQ_SHIFT             (1U)
/*! TX_IRQ - TX Interrupt
 *  0b0..TX Interrupt is not asserted.
 *  0b1..TX Interrupt is asserted.
 */
#define GENFSK_IRQ_CTRL_TX_IRQ(x)                (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_TX_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_TX_IRQ_MASK)

#define GENFSK_IRQ_CTRL_RX_IRQ_MASK              (0x4U)
#define GENFSK_IRQ_CTRL_RX_IRQ_SHIFT             (2U)
/*! RX_IRQ - RX Interrupt
 *  0b0..RX Interrupt is not asserted.
 *  0b1..RX Interrupt is asserted.
 */
#define GENFSK_IRQ_CTRL_RX_IRQ(x)                (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_RX_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_RX_IRQ_MASK)

#define GENFSK_IRQ_CTRL_NTW_ADR_IRQ_MASK         (0x8U)
#define GENFSK_IRQ_CTRL_NTW_ADR_IRQ_SHIFT        (3U)
/*! NTW_ADR_IRQ - Network Address Match Interrupt
 *  0b0..Network Address Match Interrupt is not asserted.
 *  0b1..Network Address Match Interrupt is asserted.
 */
#define GENFSK_IRQ_CTRL_NTW_ADR_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_NTW_ADR_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_NTW_ADR_IRQ_MASK)

#define GENFSK_IRQ_CTRL_T1_IRQ_MASK              (0x10U)
#define GENFSK_IRQ_CTRL_T1_IRQ_SHIFT             (4U)
/*! T1_IRQ - Timer1 (T1) Compare Interrupt
 *  0b0..Timer1 (T1) Compare Interrupt is not asserted.
 *  0b1..Timer1 (T1) Compare Interrupt is asserted.
 */
#define GENFSK_IRQ_CTRL_T1_IRQ(x)                (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_T1_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_T1_IRQ_MASK)

#define GENFSK_IRQ_CTRL_T2_IRQ_MASK              (0x20U)
#define GENFSK_IRQ_CTRL_T2_IRQ_SHIFT             (5U)
/*! T2_IRQ - Timer2 (T2) Compare Interrupt
 *  0b0..Timer2 (T2) Compare Interrupt is not asserted.
 *  0b1..Timer2 (T2) Compare Interrupt is asserted.
 */
#define GENFSK_IRQ_CTRL_T2_IRQ(x)                (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_T2_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_T2_IRQ_MASK)

#define GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_MASK      (0x40U)
#define GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_SHIFT     (6U)
/*! PLL_UNLOCK_IRQ - PLL Unlock Interrupt
 *  0b0..PLL Unlock Interrupt is not asserted.
 *  0b1..PLL Unlock Interrupt is asserted.
 */
#define GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_MASK)

#define GENFSK_IRQ_CTRL_WAKE_IRQ_MASK            (0x80U)
#define GENFSK_IRQ_CTRL_WAKE_IRQ_SHIFT           (7U)
/*! WAKE_IRQ - Wake Interrrupt
 *  0b0..Wake Interrupt is not asserted.
 *  0b1..Wake Interrupt is asserted.
 */
#define GENFSK_IRQ_CTRL_WAKE_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_WAKE_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_WAKE_IRQ_MASK)

#define GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_MASK    (0x100U)
#define GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_SHIFT   (8U)
/*! RX_WATERMARK_IRQ - RX Watermark Interrupt
 *  0b0..RX Watermark Interrupt is not asserted.
 *  0b1..RX Watermark Interrupt is asserted.
 */
#define GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_MASK)

#define GENFSK_IRQ_CTRL_TSM_IRQ_MASK             (0x200U)
#define GENFSK_IRQ_CTRL_TSM_IRQ_SHIFT            (9U)
/*! TSM_IRQ - TSM Interrupt
 *  0b0..TSM0_IRQ and TSM1_IRQ are both clear.
 *  0b1..Indicates TSM0_IRQ or TSM1_IRQ is set in XCVR_STATUS.
 */
#define GENFSK_IRQ_CTRL_TSM_IRQ(x)               (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_TSM_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_TSM_IRQ_MASK)

#define GENFSK_IRQ_CTRL_CRC_VALID_MASK           (0x400U)
#define GENFSK_IRQ_CTRL_CRC_VALID_SHIFT          (10U)
/*! CRC_VALID - CRC Valid
 */
#define GENFSK_IRQ_CTRL_CRC_VALID(x)             (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_CRC_VALID_SHIFT)) & GENFSK_IRQ_CTRL_CRC_VALID_MASK)

#define GENFSK_IRQ_CTRL_ACK_IRQ_MASK             (0x800U)
#define GENFSK_IRQ_CTRL_ACK_IRQ_SHIFT            (11U)
/*! ACK_IRQ - Auto ACK Interrupt
 *  0b0..Auto ACK Interrupt is not asserted.
 *  0b1..Auto ACK Interrupt is asserted.
 */
#define GENFSK_IRQ_CTRL_ACK_IRQ(x)               (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_ACK_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_ACK_IRQ_MASK)

#define GENFSK_IRQ_CTRL_PHRFFAIL_IRQ_MASK        (0x1000U)
#define GENFSK_IRQ_CTRL_PHRFFAIL_IRQ_SHIFT       (12U)
/*! PHRFFAIL_IRQ - Received Frame PHR Fail Interrupt
 *  0b0..Received frame PHR Fail Interrupt is not asserted.
 *  0b1..Received frame PHR Fail Interrupt is asserted.
 */
#define GENFSK_IRQ_CTRL_PHRFFAIL_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_PHRFFAIL_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_PHRFFAIL_IRQ_MASK)

#define GENFSK_IRQ_CTRL_FILTERFAIL_IRQ_MASK      (0x2000U)
#define GENFSK_IRQ_CTRL_FILTERFAIL_IRQ_SHIFT     (13U)
/*! FILTERFAIL_IRQ - Received Frame Filter Fail Interrupt
 *  0b0..A Filter Fail Interrupt has not occurred.
 *  0b1..A Filter Fail Interrupt has occurred.
 */
#define GENFSK_IRQ_CTRL_FILTERFAIL_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_FILTERFAIL_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_FILTERFAIL_IRQ_MASK)

#define GENFSK_IRQ_CTRL_CCA_IRQ_MASK             (0x4000U)
#define GENFSK_IRQ_CTRL_CCA_IRQ_SHIFT            (14U)
/*! CCA_IRQ - CCA Interrupt
 *  0b0..A CCA Interrupt has not occurred
 *  0b1..A CCA Interrupt has occurred
 */
#define GENFSK_IRQ_CTRL_CCA_IRQ(x)               (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_CCA_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_CCA_IRQ_MASK)

#define GENFSK_IRQ_CTRL_MS_IRQ_MASK              (0x8000U)
#define GENFSK_IRQ_CTRL_MS_IRQ_SHIFT             (15U)
/*! MS_IRQ - Mode Switch Interrupt
 *  0b0..A Mode Switch frame is not received
 *  0b1..A Mode Switch frame is received
 */
#define GENFSK_IRQ_CTRL_MS_IRQ(x)                (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_MS_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_MS_IRQ_MASK)

#define GENFSK_IRQ_CTRL_SEQ_END_IRQ_EN_MASK      (0x10000U)
#define GENFSK_IRQ_CTRL_SEQ_END_IRQ_EN_SHIFT     (16U)
/*! SEQ_END_IRQ_EN - SEQ_END_IRQ Enable
 *  0b0..Sequence End Interrupt is not enabled.
 *  0b1..Sequence End Interrupt is enabled.
 */
#define GENFSK_IRQ_CTRL_SEQ_END_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_SEQ_END_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_SEQ_END_IRQ_EN_MASK)

#define GENFSK_IRQ_CTRL_TX_IRQ_EN_MASK           (0x20000U)
#define GENFSK_IRQ_CTRL_TX_IRQ_EN_SHIFT          (17U)
/*! TX_IRQ_EN - TX_IRQ Enable
 *  0b0..TX Interrupt is not enabled.
 *  0b1..TX Interrupt is enabled.
 */
#define GENFSK_IRQ_CTRL_TX_IRQ_EN(x)             (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_TX_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_TX_IRQ_EN_MASK)

#define GENFSK_IRQ_CTRL_RX_IRQ_EN_MASK           (0x40000U)
#define GENFSK_IRQ_CTRL_RX_IRQ_EN_SHIFT          (18U)
/*! RX_IRQ_EN - RX_IRQ Enable
 *  0b0..RX Interrupt is not enabled.
 *  0b1..RX Interrupt is enabled.
 */
#define GENFSK_IRQ_CTRL_RX_IRQ_EN(x)             (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_RX_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_RX_IRQ_EN_MASK)

#define GENFSK_IRQ_CTRL_NTW_ADR_IRQ_EN_MASK      (0x80000U)
#define GENFSK_IRQ_CTRL_NTW_ADR_IRQ_EN_SHIFT     (19U)
/*! NTW_ADR_IRQ_EN - NTW_ADR_IRQ Enable
 *  0b0..Network Address Match Interrupt is not enabled.
 *  0b1..Network Address Match Interrupt is enabled.
 */
#define GENFSK_IRQ_CTRL_NTW_ADR_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_NTW_ADR_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_NTW_ADR_IRQ_EN_MASK)

#define GENFSK_IRQ_CTRL_T1_IRQ_EN_MASK           (0x100000U)
#define GENFSK_IRQ_CTRL_T1_IRQ_EN_SHIFT          (20U)
/*! T1_IRQ_EN - T1_IRQ Enable
 *  0b0..Timer1 (T1) Compare Interrupt is not enabled.
 *  0b1..Timer1 (T1) Compare Interrupt is enabled.
 */
#define GENFSK_IRQ_CTRL_T1_IRQ_EN(x)             (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_T1_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_T1_IRQ_EN_MASK)

#define GENFSK_IRQ_CTRL_T2_IRQ_EN_MASK           (0x200000U)
#define GENFSK_IRQ_CTRL_T2_IRQ_EN_SHIFT          (21U)
/*! T2_IRQ_EN - T2_IRQ Enable
 *  0b0..Timer1 (T2) Compare Interrupt is not enabled.
 *  0b1..Timer1 (T2) Compare Interrupt is enabled.
 */
#define GENFSK_IRQ_CTRL_T2_IRQ_EN(x)             (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_T2_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_T2_IRQ_EN_MASK)

#define GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_EN_MASK   (0x400000U)
#define GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_EN_SHIFT  (22U)
/*! PLL_UNLOCK_IRQ_EN - PLL_UNLOCK_IRQ Enable
 *  0b0..PLL Unlock Interrupt is not enabled.
 *  0b1..PLL Unlock Interrupt is enabled.
 */
#define GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_EN(x)     (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_EN_MASK)

#define GENFSK_IRQ_CTRL_WAKE_IRQ_EN_MASK         (0x800000U)
#define GENFSK_IRQ_CTRL_WAKE_IRQ_EN_SHIFT        (23U)
/*! WAKE_IRQ_EN - WAKE_IRQ Enable
 *  0b0..Wake Interrupt is not enabled.
 *  0b1..Wake Interrupt is enabled.
 */
#define GENFSK_IRQ_CTRL_WAKE_IRQ_EN(x)           (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_WAKE_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_WAKE_IRQ_EN_MASK)

#define GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_EN_MASK (0x1000000U)
#define GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_EN_SHIFT (24U)
/*! RX_WATERMARK_IRQ_EN - RX_WATERMARK_IRQ Enable
 *  0b0..RX Watermark Interrupt is not enabled.
 *  0b1..RX Watermark Interrupt is enabled.
 */
#define GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_EN_MASK)

#define GENFSK_IRQ_CTRL_TSM_IRQ_EN_MASK          (0x2000000U)
#define GENFSK_IRQ_CTRL_TSM_IRQ_EN_SHIFT         (25U)
/*! TSM_IRQ_EN - TSM_IRQ Enable
 *  0b0..TSM Interrupt is not enabled.
 *  0b1..TSM Interrupt is enabled.
 */
#define GENFSK_IRQ_CTRL_TSM_IRQ_EN(x)            (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_TSM_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_TSM_IRQ_EN_MASK)

#define GENFSK_IRQ_CTRL_GENERIC_FSK_IRQ_EN_MASK  (0x4000000U)
#define GENFSK_IRQ_CTRL_GENERIC_FSK_IRQ_EN_SHIFT (26U)
/*! GENERIC_FSK_IRQ_EN - GENERIC_FSK_IRQ Master Enable
 *  0b0..All GENERIC_FSK Interrupts are disabled.
 *  0b1..All GENERIC_FSK Interrupts can be enabled.
 */
#define GENFSK_IRQ_CTRL_GENERIC_FSK_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_GENERIC_FSK_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_GENERIC_FSK_IRQ_EN_MASK)

#define GENFSK_IRQ_CTRL_ACK_IRQ_EN_MASK          (0x8000000U)
#define GENFSK_IRQ_CTRL_ACK_IRQ_EN_SHIFT         (27U)
/*! ACK_IRQ_EN - ACK_IRQ Enable
 *  0b0..Auto ACK Interrupt is not enabled.
 *  0b1..Auto ACK Interrupt is enabled.
 */
#define GENFSK_IRQ_CTRL_ACK_IRQ_EN(x)            (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_ACK_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_ACK_IRQ_EN_MASK)

#define GENFSK_IRQ_CTRL_PHRFAIL_IRQ_EN_MASK      (0x10000000U)
#define GENFSK_IRQ_CTRL_PHRFAIL_IRQ_EN_SHIFT     (28U)
/*! PHRFAIL_IRQ_EN - PHRFAIL_IRQ Enable
 *  0b0..PHRFAIL Interrupt is not enabled.
 *  0b1..PHRFAIL Interrupt is enabled.
 */
#define GENFSK_IRQ_CTRL_PHRFAIL_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_PHRFAIL_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_PHRFAIL_IRQ_EN_MASK)

#define GENFSK_IRQ_CTRL_FILTERFAIL_IRQ_EN_MASK   (0x20000000U)
#define GENFSK_IRQ_CTRL_FILTERFAIL_IRQ_EN_SHIFT  (29U)
/*! FILTERFAIL_IRQ_EN - FILTERFAIL_IRQ Enable
 *  0b0..FILTERFAIL Interrupt is not enabled.
 *  0b1..FILTERFAIL Interrupt is enabled.
 */
#define GENFSK_IRQ_CTRL_FILTERFAIL_IRQ_EN(x)     (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_FILTERFAIL_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_FILTERFAIL_IRQ_EN_MASK)

#define GENFSK_IRQ_CTRL_CCA_IRQ_EN_MASK          (0x40000000U)
#define GENFSK_IRQ_CTRL_CCA_IRQ_EN_SHIFT         (30U)
/*! CCA_IRQ_EN - CCA_IRQ Enable
 *  0b0..CCA Interrupt is not enabled.
 *  0b1..CCA Interrupt is enabled.
 */
#define GENFSK_IRQ_CTRL_CCA_IRQ_EN(x)            (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_CCA_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_CCA_IRQ_EN_MASK)

#define GENFSK_IRQ_CTRL_MS_IRQ_EN_MASK           (0x80000000U)
#define GENFSK_IRQ_CTRL_MS_IRQ_EN_SHIFT          (31U)
/*! MS_IRQ_EN - MS_IRQ Enable
 *  0b0..MS Interrupt is not enabled.
 *  0b1..MS Interrupt is enabled.
 */
#define GENFSK_IRQ_CTRL_MS_IRQ_EN(x)             (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_MS_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_MS_IRQ_EN_MASK)
/*! @} */

/*! @name EVENT_TMR - EVENT TIMER */
/*! @{ */

#define GENFSK_EVENT_TMR_EVENT_TMR_MASK          (0xFFFFFFFFU)
#define GENFSK_EVENT_TMR_EVENT_TMR_SHIFT         (0U)
/*! EVENT_TMR - Event Timer
 */
#define GENFSK_EVENT_TMR_EVENT_TMR(x)            (((uint32_t)(((uint32_t)(x)) << GENFSK_EVENT_TMR_EVENT_TMR_SHIFT)) & GENFSK_EVENT_TMR_EVENT_TMR_MASK)
/*! @} */

/*! @name T1_CMP - T1 COMPARE */
/*! @{ */

#define GENFSK_T1_CMP_T1_CMP_MASK                (0xFFFFFFFFU)
#define GENFSK_T1_CMP_T1_CMP_SHIFT               (0U)
/*! T1_CMP - Timer1 (T1) Compare Value
 */
#define GENFSK_T1_CMP_T1_CMP(x)                  (((uint32_t)(((uint32_t)(x)) << GENFSK_T1_CMP_T1_CMP_SHIFT)) & GENFSK_T1_CMP_T1_CMP_MASK)
/*! @} */

/*! @name T2_CMP - T2 COMPARE */
/*! @{ */

#define GENFSK_T2_CMP_T2_CMP_MASK                (0xFFFFFFFFU)
#define GENFSK_T2_CMP_T2_CMP_SHIFT               (0U)
/*! T2_CMP - Timer2 (T2) Compare Value
 */
#define GENFSK_T2_CMP_T2_CMP(x)                  (((uint32_t)(((uint32_t)(x)) << GENFSK_T2_CMP_T2_CMP_SHIFT)) & GENFSK_T2_CMP_T2_CMP_MASK)
/*! @} */

/*! @name TIMESTAMP - TIMESTAMP */
/*! @{ */

#define GENFSK_TIMESTAMP_TIMESTAMP_MASK          (0xFFFFFFFFU)
#define GENFSK_TIMESTAMP_TIMESTAMP_SHIFT         (0U)
/*! TIMESTAMP - Received Packet Timestamp
 */
#define GENFSK_TIMESTAMP_TIMESTAMP(x)            (((uint32_t)(((uint32_t)(x)) << GENFSK_TIMESTAMP_TIMESTAMP_SHIFT)) & GENFSK_TIMESTAMP_TIMESTAMP_MASK)
/*! @} */

/*! @name XCVR_CTRL - TRANSCEIVER CONTROL */
/*! @{ */

#define GENFSK_XCVR_CTRL_SEQCMD_MASK             (0x1FU)
#define GENFSK_XCVR_CTRL_SEQCMD_SHIFT            (0U)
/*! SEQCMD - Sequence Commands, also named as "XCVSEQ(Transceiver Sequence)"
 *  0b00000..Same as command ABORT
 *  0b00001..TX Start Now
 *  0b00010..TX Start @ T1 Timer Compare Match (EVENT_TMR = T1_CMP)
 *  0b00011..TX Start @ T2 Timer Compare Match (EVENT_TMR = T2_CMP)
 *  0b00100..TX Cancel -- Cancels pending TX events but do not abort a TX-in-progress
 *  0b00101..RX Start Now
 *  0b00110..RX Start @ T1 Timer Compare Match (EVENT_TMR = T1_CMP)
 *  0b00111..RX Start @ T2 Timer Compare Match (EVENT_TMR = T2_CMP)
 *  0b01000..RX Stop @ T1 Timer Compare Match (EVENT_TMR = T1_CMP)
 *  0b01001..RX Stop @ T2 Timer Compare Match (EVENT_TMR = T2_CMP)
 *  0b01010..RX Cancel -- Cancels pending RX events but do not abort a RX-in-progress
 *  0b01011..Abort All - Cancels all pending events and abort any sequence-in-progress
 *  0b01100..TR Start Now
 *  0b01101..TR Start @ T1 Timer Compare Match (EVENT_TMR = T1_CMP)
 *  0b01110..TR Start @ T2 Timer Compare Match (EVENT_TMR = T2_CMP)
 *  0b01111..TR Cancel -- Cancels pending TR events but do not abort a TR-in-progress
 *  0b10000..CCA Start Now
 *  0b10001..CCA Start @ T1 Timer Compare Match (EVENT_TMR = T1_CMP)
 *  0b10010..CCA Start @ T2 Timer Compare Match (EVENT_TMR = T2_CMP)
 *  0b10011..CCA Cancel -- Cancels pending CCA events but do not abort a CCA-in-progress
 */
#define GENFSK_XCVR_CTRL_SEQCMD(x)               (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CTRL_SEQCMD_SHIFT)) & GENFSK_XCVR_CTRL_SEQCMD_MASK)

#define GENFSK_XCVR_CTRL_LENGTH_EXT_MASK         (0x7FF00U)
#define GENFSK_XCVR_CTRL_LENGTH_EXT_SHIFT        (8U)
/*! LENGTH_EXT - Extracted Length Field
 */
#define GENFSK_XCVR_CTRL_LENGTH_EXT(x)           (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CTRL_LENGTH_EXT_SHIFT)) & GENFSK_XCVR_CTRL_LENGTH_EXT_MASK)

#define GENFSK_XCVR_CTRL_CMDDEC_CS_MASK          (0x1F000000U)
#define GENFSK_XCVR_CTRL_CMDDEC_CS_SHIFT         (24U)
/*! CMDDEC_CS - Command Decode
 */
#define GENFSK_XCVR_CTRL_CMDDEC_CS(x)            (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CTRL_CMDDEC_CS_SHIFT)) & GENFSK_XCVR_CTRL_CMDDEC_CS_MASK)

#define GENFSK_XCVR_CTRL_XCVR_BUSY_MASK          (0x80000000U)
#define GENFSK_XCVR_CTRL_XCVR_BUSY_SHIFT         (31U)
/*! XCVR_BUSY - Transceiver Busy
 *  0b0..IDLE
 *  0b1..BUSY
 */
#define GENFSK_XCVR_CTRL_XCVR_BUSY(x)            (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CTRL_XCVR_BUSY_SHIFT)) & GENFSK_XCVR_CTRL_XCVR_BUSY_MASK)
/*! @} */

/*! @name XCVR_STS - TRANSCEIVER STATUS */
/*! @{ */

#define GENFSK_XCVR_STS_LQI_MASK                 (0xFFU)
#define GENFSK_XCVR_STS_LQI_SHIFT                (0U)
/*! LQI - Link Quality Indicator
 */
#define GENFSK_XCVR_STS_LQI(x)                   (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_LQI_SHIFT)) & GENFSK_XCVR_STS_LQI_MASK)

#define GENFSK_XCVR_STS_LQI_VALID_MASK           (0x8000U)
#define GENFSK_XCVR_STS_LQI_VALID_SHIFT          (15U)
/*! LQI_VALID - LQI Valid Indicator
 *  0b0..LQI is not yet valid for RX packet.
 *  0b1..LQI is valid for RX packet.
 */
#define GENFSK_XCVR_STS_LQI_VALID(x)             (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_LQI_VALID_SHIFT)) & GENFSK_XCVR_STS_LQI_VALID_MASK)

#define GENFSK_XCVR_STS_RSSI_MASK                (0xFF0000U)
#define GENFSK_XCVR_STS_RSSI_SHIFT               (16U)
/*! RSSI - RSSI Value
 */
#define GENFSK_XCVR_STS_RSSI(x)                  (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_RSSI_SHIFT)) & GENFSK_XCVR_STS_RSSI_MASK)
/*! @} */

/*! @name XCVR_CFG - TRANSCEIVER CONFIGURATION */
/*! @{ */

#define GENFSK_XCVR_CFG_TX_WHITEN_DIS_MASK       (0x1U)
#define GENFSK_XCVR_CFG_TX_WHITEN_DIS_SHIFT      (0U)
/*! TX_WHITEN_DIS - TX Whitening Disable
 */
#define GENFSK_XCVR_CFG_TX_WHITEN_DIS(x)         (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CFG_TX_WHITEN_DIS_SHIFT)) & GENFSK_XCVR_CFG_TX_WHITEN_DIS_MASK)

#define GENFSK_XCVR_CFG_RX_DEWHITEN_DIS_MASK     (0x2U)
#define GENFSK_XCVR_CFG_RX_DEWHITEN_DIS_SHIFT    (1U)
/*! RX_DEWHITEN_DIS - RX De-Whitening Disable
 */
#define GENFSK_XCVR_CFG_RX_DEWHITEN_DIS(x)       (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CFG_RX_DEWHITEN_DIS_SHIFT)) & GENFSK_XCVR_CFG_RX_DEWHITEN_DIS_MASK)

#define GENFSK_XCVR_CFG_SW_CRC_EN_MASK           (0x4U)
#define GENFSK_XCVR_CFG_SW_CRC_EN_SHIFT          (2U)
/*! SW_CRC_EN - Software CRC Enable
 */
#define GENFSK_XCVR_CFG_SW_CRC_EN(x)             (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CFG_SW_CRC_EN_SHIFT)) & GENFSK_XCVR_CFG_SW_CRC_EN_MASK)

#define GENFSK_XCVR_CFG_STOP_POSTPONE_ON_AA_MASK (0x8U)
#define GENFSK_XCVR_CFG_STOP_POSTPONE_ON_AA_SHIFT (3U)
/*! STOP_POSTPONE_ON_AA - Postpone Stop Command Timeout On Access Address Match Enable
 *  0b0..STOP Abort will occur on RX_STOP_T1 or RX_STOP_T1 Event Timer match, regardless of NTW_ADR_MCH
 *  0b1..STOP Abort will be deferred on RX_STOP_T1 or RX_STOP_T1 Event Timer match, if NTW_ADR_MCH is asserted;
 *       otherwise the RX_STOP Abort will occur immediately
 */
#define GENFSK_XCVR_CFG_STOP_POSTPONE_ON_AA(x)   (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CFG_STOP_POSTPONE_ON_AA_SHIFT)) & GENFSK_XCVR_CFG_STOP_POSTPONE_ON_AA_MASK)

#define GENFSK_XCVR_CFG_PREAMBLE_SZ_MASK         (0x1FF0U)
#define GENFSK_XCVR_CFG_PREAMBLE_SZ_SHIFT        (4U)
/*! PREAMBLE_SZ - Preamble Size
 */
#define GENFSK_XCVR_CFG_PREAMBLE_SZ(x)           (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CFG_PREAMBLE_SZ_SHIFT)) & GENFSK_XCVR_CFG_PREAMBLE_SZ_MASK)

#define GENFSK_XCVR_CFG_GEN_PREAMBLE_MASK        (0xFF0000U)
#define GENFSK_XCVR_CFG_GEN_PREAMBLE_SHIFT       (16U)
/*! GEN_PREAMBLE - Preamble pattern
 */
#define GENFSK_XCVR_CFG_GEN_PREAMBLE(x)          (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CFG_GEN_PREAMBLE_SHIFT)) & GENFSK_XCVR_CFG_GEN_PREAMBLE_MASK)

#define GENFSK_XCVR_CFG_PREAMBLE_SEL_MASK        (0x7000000U)
#define GENFSK_XCVR_CFG_PREAMBLE_SEL_SHIFT       (24U)
/*! PREAMBLE_SEL - Preamble Select
 *  0b000..The controller hardware selects the preamble pattern based on the first transmitted bit of Network
 *         Address, such that the last bit of preamble is the opposite polarity from the first bit of Network Address,
 *         forcing a bit transition at this boundary.
 *  0b001..Preamble is programmed by register GEN_PREAMBLE[7:0]
 *  0b010..Preamble is 0b01
 *  0b011..Preamble is 0b10
 */
#define GENFSK_XCVR_CFG_PREAMBLE_SEL(x)          (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CFG_PREAMBLE_SEL_SHIFT)) & GENFSK_XCVR_CFG_PREAMBLE_SEL_MASK)

#define GENFSK_XCVR_CFG_T1_CMP_EN_MASK           (0x40000000U)
#define GENFSK_XCVR_CFG_T1_CMP_EN_SHIFT          (30U)
/*! T1_CMP_EN - Timer1 (T1) Compare Enable
 */
#define GENFSK_XCVR_CFG_T1_CMP_EN(x)             (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CFG_T1_CMP_EN_SHIFT)) & GENFSK_XCVR_CFG_T1_CMP_EN_MASK)

#define GENFSK_XCVR_CFG_T2_CMP_EN_MASK           (0x80000000U)
#define GENFSK_XCVR_CFG_T2_CMP_EN_SHIFT          (31U)
/*! T2_CMP_EN - Timer2 (T2) Compare Enable
 */
#define GENFSK_XCVR_CFG_T2_CMP_EN(x)             (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CFG_T2_CMP_EN_SHIFT)) & GENFSK_XCVR_CFG_T2_CMP_EN_MASK)
/*! @} */

/*! @name CHANNEL_NUM0 - CHANNEL NUMBER 0 */
/*! @{ */

#define GENFSK_CHANNEL_NUM0_CHANNEL_NUM0_MASK    (0x7FU)
#define GENFSK_CHANNEL_NUM0_CHANNEL_NUM0_SHIFT   (0U)
/*! CHANNEL_NUM0 - Channel Number for PAN0
 */
#define GENFSK_CHANNEL_NUM0_CHANNEL_NUM0(x)      (((uint32_t)(((uint32_t)(x)) << GENFSK_CHANNEL_NUM0_CHANNEL_NUM0_SHIFT)) & GENFSK_CHANNEL_NUM0_CHANNEL_NUM0_MASK)
/*! @} */

/*! @name TX_POWER - TRANSMIT POWER */
/*! @{ */

#define GENFSK_TX_POWER_TX_POWER_MASK            (0x3FU)
#define GENFSK_TX_POWER_TX_POWER_SHIFT           (0U)
/*! TX_POWER - Transmit Power
 */
#define GENFSK_TX_POWER_TX_POWER(x)              (((uint32_t)(((uint32_t)(x)) << GENFSK_TX_POWER_TX_POWER_SHIFT)) & GENFSK_TX_POWER_TX_POWER_MASK)
/*! @} */

/*! @name NTW_ADR_CTRL - NETWORK ADDRESS CONTROL */
/*! @{ */

#define GENFSK_NTW_ADR_CTRL_NTW_ADR_EN_MASK      (0xFU)
#define GENFSK_NTW_ADR_CTRL_NTW_ADR_EN_SHIFT     (0U)
/*! NTW_ADR_EN - Network Address Enable
 *  0b0001..Enable Network Address 0 for correlation
 *  0b0010..Enable Network Address 1 for correlation
 *  0b0100..Enable Network Address 2 for correlation
 *  0b1000..Enable Network Address 3 for correlation
 */
#define GENFSK_NTW_ADR_CTRL_NTW_ADR_EN(x)        (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR_EN_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR_EN_MASK)

#define GENFSK_NTW_ADR_CTRL_NTW_ADR_MCH_MASK     (0xF0U)
#define GENFSK_NTW_ADR_CTRL_NTW_ADR_MCH_SHIFT    (4U)
/*! NTW_ADR_MCH - Network Address Match
 *  0b0001..Network Address 0 has matched
 *  0b0010..Network Address 1 has matched
 *  0b0100..Network Address 2 has matched
 *  0b1000..Network Address 3 has matched
 */
#define GENFSK_NTW_ADR_CTRL_NTW_ADR_MCH(x)       (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR_MCH_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR_MCH_MASK)

#define GENFSK_NTW_ADR_CTRL_NTW_ADR_SZ_MASK      (0x300U)
#define GENFSK_NTW_ADR_CTRL_NTW_ADR_SZ_SHIFT     (8U)
/*! NTW_ADR_SZ - Network Address Size
 *  0b00..Network Address 0/1/2/3 requires a 8-bit correlation
 *  0b01..Network Address 0/1/2/3 requires a 16-bit correlation
 *  0b10..Network Address 0/1/2/3 requires a 24-bit correlation
 *  0b11..Network Address 0/1/2/3 requires a 32-bit correlation
 */
#define GENFSK_NTW_ADR_CTRL_NTW_ADR_SZ(x)        (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR_SZ_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR_SZ_MASK)

#define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR_MASK     (0x70000U)
#define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR_SHIFT    (16U)
/*! NTW_ADR_THR - Network Address Threshold
 */
#define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR(x)       (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR_THR_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR_THR_MASK)
/*! @} */

/*! @name NTW_ADR_0 - NETWORK ADDRESS 0 */
/*! @{ */

#define GENFSK_NTW_ADR_0_NTW_ADR_0_MASK          (0xFFFFFFFFU)
#define GENFSK_NTW_ADR_0_NTW_ADR_0_SHIFT         (0U)
/*! NTW_ADR_0 - Network Address 0
 */
#define GENFSK_NTW_ADR_0_NTW_ADR_0(x)            (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_0_NTW_ADR_0_SHIFT)) & GENFSK_NTW_ADR_0_NTW_ADR_0_MASK)
/*! @} */

/*! @name NTW_ADR_1 - NETWORK ADDRESS 1 */
/*! @{ */

#define GENFSK_NTW_ADR_1_NTW_ADR_1_MASK          (0xFFFFFFFFU)
#define GENFSK_NTW_ADR_1_NTW_ADR_1_SHIFT         (0U)
/*! NTW_ADR_1 - Network Address 1
 */
#define GENFSK_NTW_ADR_1_NTW_ADR_1(x)            (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_1_NTW_ADR_1_SHIFT)) & GENFSK_NTW_ADR_1_NTW_ADR_1_MASK)
/*! @} */

/*! @name NTW_ADR_2 - NETWORK ADDRESS 2 */
/*! @{ */

#define GENFSK_NTW_ADR_2_NTW_ADR_2_MASK          (0xFFFFFFFFU)
#define GENFSK_NTW_ADR_2_NTW_ADR_2_SHIFT         (0U)
/*! NTW_ADR_2 - Network Address 2
 */
#define GENFSK_NTW_ADR_2_NTW_ADR_2(x)            (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_2_NTW_ADR_2_SHIFT)) & GENFSK_NTW_ADR_2_NTW_ADR_2_MASK)
/*! @} */

/*! @name NTW_ADR_3 - NETWORK ADDRESS 3 */
/*! @{ */

#define GENFSK_NTW_ADR_3_NTW_ADR_3_MASK          (0xFFFFFFFFU)
#define GENFSK_NTW_ADR_3_NTW_ADR_3_SHIFT         (0U)
/*! NTW_ADR_3 - Network Address 2
 */
#define GENFSK_NTW_ADR_3_NTW_ADR_3(x)            (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_3_NTW_ADR_3_SHIFT)) & GENFSK_NTW_ADR_3_NTW_ADR_3_MASK)
/*! @} */

/*! @name RX_WATERMARK - RECEIVE WATERMARK */
/*! @{ */

#define GENFSK_RX_WATERMARK_RX_WATERMARK_MASK    (0x1FFFU)
#define GENFSK_RX_WATERMARK_RX_WATERMARK_SHIFT   (0U)
/*! RX_WATERMARK - Receive Watermark
 */
#define GENFSK_RX_WATERMARK_RX_WATERMARK(x)      (((uint32_t)(((uint32_t)(x)) << GENFSK_RX_WATERMARK_RX_WATERMARK_SHIFT)) & GENFSK_RX_WATERMARK_RX_WATERMARK_MASK)

#define GENFSK_RX_WATERMARK_BYTE_COUNTER_MASK    (0x1FFF0000U)
#define GENFSK_RX_WATERMARK_BYTE_COUNTER_SHIFT   (16U)
/*! BYTE_COUNTER - Byte Counter
 */
#define GENFSK_RX_WATERMARK_BYTE_COUNTER(x)      (((uint32_t)(((uint32_t)(x)) << GENFSK_RX_WATERMARK_BYTE_COUNTER_SHIFT)) & GENFSK_RX_WATERMARK_BYTE_COUNTER_MASK)
/*! @} */

/*! @name DSM_CTRL - DSM CONTROL */
/*! @{ */

#define GENFSK_DSM_CTRL_GEN_SLEEP_REQUEST_MASK   (0x1U)
#define GENFSK_DSM_CTRL_GEN_SLEEP_REQUEST_SHIFT  (0U)
/*! GEN_SLEEP_REQUEST - GENERIC_FSK Deep Sleep Mode Request
 */
#define GENFSK_DSM_CTRL_GEN_SLEEP_REQUEST(x)     (((uint32_t)(((uint32_t)(x)) << GENFSK_DSM_CTRL_GEN_SLEEP_REQUEST_SHIFT)) & GENFSK_DSM_CTRL_GEN_SLEEP_REQUEST_MASK)
/*! @} */

/*! @name PART_ID - PART ID */
/*! @{ */

#define GENFSK_PART_ID_PART_ID_MASK              (0xFFU)
#define GENFSK_PART_ID_PART_ID_SHIFT             (0U)
/*! PART_ID - Part ID
 */
#define GENFSK_PART_ID_PART_ID(x)                (((uint32_t)(((uint32_t)(x)) << GENFSK_PART_ID_PART_ID_SHIFT)) & GENFSK_PART_ID_PART_ID_MASK)
/*! @} */

/*! @name SLOT_PRELOAD - SLOT PRELOAD */
/*! @{ */

#define GENFSK_SLOT_PRELOAD_SLOT_PRELOAD_MASK    (0xFFFFU)
#define GENFSK_SLOT_PRELOAD_SLOT_PRELOAD_SHIFT   (0U)
/*! SLOT_PRELOAD - Slotted Mode Preload
 */
#define GENFSK_SLOT_PRELOAD_SLOT_PRELOAD(x)      (((uint32_t)(((uint32_t)(x)) << GENFSK_SLOT_PRELOAD_SLOT_PRELOAD_SHIFT)) & GENFSK_SLOT_PRELOAD_SLOT_PRELOAD_MASK)
/*! @} */

/*! @name SLOT_TIME - SLOT TIME */
/*! @{ */

#define GENFSK_SLOT_TIME_SLOT_TIME_MASK          (0xFFFFU)
#define GENFSK_SLOT_TIME_SLOT_TIME_SHIFT         (0U)
/*! SLOT_TIME - Duration of the Backoff Slot
 */
#define GENFSK_SLOT_TIME_SLOT_TIME(x)            (((uint32_t)(((uint32_t)(x)) << GENFSK_SLOT_TIME_SLOT_TIME_SHIFT)) & GENFSK_SLOT_TIME_SLOT_TIME_MASK)
/*! @} */

/*! @name TURNAROUND_TIME - TURNAROUND TIME */
/*! @{ */

#define GENFSK_TURNAROUND_TIME_TURNAROUND_TIME_MASK (0xFFFFU)
#define GENFSK_TURNAROUND_TIME_TURNAROUND_TIME_SHIFT (0U)
/*! TURNAROUND_TIME - RX-to-TX or TX-to-RX turnaround time
 */
#define GENFSK_TURNAROUND_TIME_TURNAROUND_TIME(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_TURNAROUND_TIME_TURNAROUND_TIME_SHIFT)) & GENFSK_TURNAROUND_TIME_TURNAROUND_TIME_MASK)
/*! @} */

/*! @name ACKDELAY - ACK DELAY */
/*! @{ */

#define GENFSK_ACKDELAY_ACKDELAY_MASK            (0x3FFU)
#define GENFSK_ACKDELAY_ACKDELAY_SHIFT           (0U)
/*! ACKDELAY - ACK Delay
 */
#define GENFSK_ACKDELAY_ACKDELAY(x)              (((uint32_t)(((uint32_t)(x)) << GENFSK_ACKDELAY_ACKDELAY_SHIFT)) & GENFSK_ACKDELAY_ACKDELAY_MASK)
/*! @} */

/*! @name RXDELAY - RX DELAY */
/*! @{ */

#define GENFSK_RXDELAY_RXDELAY_MASK              (0x3FFU)
#define GENFSK_RXDELAY_RXDELAY_SHIFT             (0U)
/*! RXDELAY - RX Delay
 */
#define GENFSK_RXDELAY_RXDELAY(x)                (((uint32_t)(((uint32_t)(x)) << GENFSK_RXDELAY_RXDELAY_SHIFT)) & GENFSK_RXDELAY_RXDELAY_MASK)
/*! @} */

/*! @name TXDELAY - TX DELAY */
/*! @{ */

#define GENFSK_TXDELAY_TXDELAY_MASK              (0x3FFU)
#define GENFSK_TXDELAY_TXDELAY_SHIFT             (0U)
/*! TXDELAY - TX Delay
 */
#define GENFSK_TXDELAY_TXDELAY(x)                (((uint32_t)(((uint32_t)(x)) << GENFSK_TXDELAY_TXDELAY_SHIFT)) & GENFSK_TXDELAY_TXDELAY_MASK)
/*! @} */

/*! @name PACKET_CFG - PACKET CONFIGURATION */
/*! @{ */

#define GENFSK_PACKET_CFG_LENGTH_SZ_MASK         (0x1FU)
#define GENFSK_PACKET_CFG_LENGTH_SZ_SHIFT        (0U)
/*! LENGTH_SZ - LENGTH Size
 */
#define GENFSK_PACKET_CFG_LENGTH_SZ(x)           (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_LENGTH_SZ_SHIFT)) & GENFSK_PACKET_CFG_LENGTH_SZ_MASK)

#define GENFSK_PACKET_CFG_LENGTH_BIT_ORD_MASK    (0x20U)
#define GENFSK_PACKET_CFG_LENGTH_BIT_ORD_SHIFT   (5U)
/*! LENGTH_BIT_ORD - LENGTH Bit Order
 *  0b0..LS Bit First
 *  0b1..MS Bit First
 */
#define GENFSK_PACKET_CFG_LENGTH_BIT_ORD(x)      (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_LENGTH_BIT_ORD_SHIFT)) & GENFSK_PACKET_CFG_LENGTH_BIT_ORD_MASK)

#define GENFSK_PACKET_CFG_SYNC_ADDR_SZ_MASK      (0xC0U)
#define GENFSK_PACKET_CFG_SYNC_ADDR_SZ_SHIFT     (6U)
/*! SYNC_ADDR_SZ - Sync Address Size
 */
#define GENFSK_PACKET_CFG_SYNC_ADDR_SZ(x)        (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_SYNC_ADDR_SZ_SHIFT)) & GENFSK_PACKET_CFG_SYNC_ADDR_SZ_MASK)

#define GENFSK_PACKET_CFG_H0_SZ_MASK             (0x1F0000U)
#define GENFSK_PACKET_CFG_H0_SZ_SHIFT            (16U)
/*! H0_SZ - H0 Size
 */
#define GENFSK_PACKET_CFG_H0_SZ(x)               (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_H0_SZ_SHIFT)) & GENFSK_PACKET_CFG_H0_SZ_MASK)

#define GENFSK_PACKET_CFG_AA_PLAYBACK_CNT_MASK   (0x400000U)
#define GENFSK_PACKET_CFG_AA_PLAYBACK_CNT_SHIFT  (22U)
/*! AA_PLAYBACK_CNT - AA PLAYBACK COUNT
 *  0b0..AA is not through CRC and not playback to Link layer.
 *  0b1..AA is through CRC and palyback to Link Layer.
 */
#define GENFSK_PACKET_CFG_AA_PLAYBACK_CNT(x)     (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_AA_PLAYBACK_CNT_SHIFT)) & GENFSK_PACKET_CFG_AA_PLAYBACK_CNT_MASK)

#define GENFSK_PACKET_CFG_LL_FETCH_AA_MASK       (0x800000U)
#define GENFSK_PACKET_CFG_LL_FETCH_AA_SHIFT      (23U)
/*! LL_FETCH_AA - Link layer fetches AA from PHY
 *  0b0..Link layer does not fetch AA from PHY
 *  0b1..Link layer fetches AA from PHY when AA_PLAYBACK_CNT is 0
 */
#define GENFSK_PACKET_CFG_LL_FETCH_AA(x)         (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_LL_FETCH_AA_SHIFT)) & GENFSK_PACKET_CFG_LL_FETCH_AA_MASK)

#define GENFSK_PACKET_CFG_H1_SZ_MASK             (0x1F000000U)
#define GENFSK_PACKET_CFG_H1_SZ_SHIFT            (24U)
/*! H1_SZ - H1 Size
 */
#define GENFSK_PACKET_CFG_H1_SZ(x)               (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_H1_SZ_SHIFT)) & GENFSK_PACKET_CFG_H1_SZ_MASK)

#define GENFSK_PACKET_CFG_H1_FAIL_MASK           (0x20000000U)
#define GENFSK_PACKET_CFG_H1_FAIL_SHIFT          (29U)
/*! H1_FAIL - H1 Violated Status Bit
 */
#define GENFSK_PACKET_CFG_H1_FAIL(x)             (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_H1_FAIL_SHIFT)) & GENFSK_PACKET_CFG_H1_FAIL_MASK)

#define GENFSK_PACKET_CFG_H0_FAIL_MASK           (0x40000000U)
#define GENFSK_PACKET_CFG_H0_FAIL_SHIFT          (30U)
/*! H0_FAIL - H0 Violated Status Bit
 */
#define GENFSK_PACKET_CFG_H0_FAIL(x)             (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_H0_FAIL_SHIFT)) & GENFSK_PACKET_CFG_H0_FAIL_MASK)

#define GENFSK_PACKET_CFG_LENGTH_FAIL_MASK       (0x80000000U)
#define GENFSK_PACKET_CFG_LENGTH_FAIL_SHIFT      (31U)
/*! LENGTH_FAIL - Maximum Length Violated Status Bit
 */
#define GENFSK_PACKET_CFG_LENGTH_FAIL(x)         (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_LENGTH_FAIL_SHIFT)) & GENFSK_PACKET_CFG_LENGTH_FAIL_MASK)
/*! @} */

/*! @name H0_CFG - H0 CONFIGURATION */
/*! @{ */

#define GENFSK_H0_CFG_H0_MATCH_MASK              (0xFFFFU)
#define GENFSK_H0_CFG_H0_MATCH_SHIFT             (0U)
/*! H0_MATCH - H0 Match Register
 */
#define GENFSK_H0_CFG_H0_MATCH(x)                (((uint32_t)(((uint32_t)(x)) << GENFSK_H0_CFG_H0_MATCH_SHIFT)) & GENFSK_H0_CFG_H0_MATCH_MASK)

#define GENFSK_H0_CFG_H0_MASK_MASK               (0xFFFF0000U)
#define GENFSK_H0_CFG_H0_MASK_SHIFT              (16U)
/*! H0_MASK - H0 Mask Register
 */
#define GENFSK_H0_CFG_H0_MASK(x)                 (((uint32_t)(((uint32_t)(x)) << GENFSK_H0_CFG_H0_MASK_SHIFT)) & GENFSK_H0_CFG_H0_MASK_MASK)
/*! @} */

/*! @name H1_CFG - H1 CONFIGURATION */
/*! @{ */

#define GENFSK_H1_CFG_H1_MATCH_MASK              (0xFFFFU)
#define GENFSK_H1_CFG_H1_MATCH_SHIFT             (0U)
/*! H1_MATCH - H1 Match Register
 */
#define GENFSK_H1_CFG_H1_MATCH(x)                (((uint32_t)(((uint32_t)(x)) << GENFSK_H1_CFG_H1_MATCH_SHIFT)) & GENFSK_H1_CFG_H1_MATCH_MASK)

#define GENFSK_H1_CFG_H1_MASK_MASK               (0xFFFF0000U)
#define GENFSK_H1_CFG_H1_MASK_SHIFT              (16U)
/*! H1_MASK - H1 Mask Register
 */
#define GENFSK_H1_CFG_H1_MASK(x)                 (((uint32_t)(((uint32_t)(x)) << GENFSK_H1_CFG_H1_MASK_SHIFT)) & GENFSK_H1_CFG_H1_MASK_MASK)
/*! @} */

/*! @name CRC_CFG - CRC CONFIGURATION */
/*! @{ */

#define GENFSK_CRC_CFG_CRC_IGNORE_MASK           (0x1000000U)
#define GENFSK_CRC_CFG_CRC_IGNORE_SHIFT          (24U)
/*! CRC_IGNORE - CRC Ignore
 *  0b0..RX_IRQ will not be asserted for a received packet which fails CRC verification.
 *  0b1..RX_IRQ will be asserted even for a received packet which fails CRC verification.
 */
#define GENFSK_CRC_CFG_CRC_IGNORE(x)             (((uint32_t)(((uint32_t)(x)) << GENFSK_CRC_CFG_CRC_IGNORE_SHIFT)) & GENFSK_CRC_CFG_CRC_IGNORE_MASK)

#define GENFSK_CRC_CFG_CRC_VALID_MASK            (0x10000000U)
#define GENFSK_CRC_CFG_CRC_VALID_SHIFT           (28U)
/*! CRC_VALID - CRC Valid
 *  0b0..CRC of RX packet is not valid.
 *  0b1..CRC of RX packet is valid.
 */
#define GENFSK_CRC_CFG_CRC_VALID(x)              (((uint32_t)(((uint32_t)(x)) << GENFSK_CRC_CFG_CRC_VALID_SHIFT)) & GENFSK_CRC_CFG_CRC_VALID_MASK)
/*! @} */

/*! @name LENGTH_ADJ - LENGTH ADJUSTMENT */
/*! @{ */

#define GENFSK_LENGTH_ADJ_LENGTH_ADJ_MASK        (0x7FFU)
#define GENFSK_LENGTH_ADJ_LENGTH_ADJ_SHIFT       (0U)
/*! LENGTH_ADJ - Length Adjustment
 */
#define GENFSK_LENGTH_ADJ_LENGTH_ADJ(x)          (((uint32_t)(((uint32_t)(x)) << GENFSK_LENGTH_ADJ_LENGTH_ADJ_SHIFT)) & GENFSK_LENGTH_ADJ_LENGTH_ADJ_MASK)
/*! @} */

/*! @name TIMESTAMP_RX_DONE - TIMESTAMP_RX_DONE */
/*! @{ */

#define GENFSK_TIMESTAMP_RX_DONE_TIMESTAMP_RX_DONE_MASK (0xFFFFFFFFU)
#define GENFSK_TIMESTAMP_RX_DONE_TIMESTAMP_RX_DONE_SHIFT (0U)
/*! TIMESTAMP_RX_DONE - Received Packet Timestamp. Captured at Rx done.
 */
#define GENFSK_TIMESTAMP_RX_DONE_TIMESTAMP_RX_DONE(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_TIMESTAMP_RX_DONE_TIMESTAMP_RX_DONE_SHIFT)) & GENFSK_TIMESTAMP_RX_DONE_TIMESTAMP_RX_DONE_MASK)
/*! @} */

/*! @name TIMESTAMP_TX_DONE - TIMESTAMP_TX_DONE */
/*! @{ */

#define GENFSK_TIMESTAMP_TX_DONE_TIMESTAMP_TX_DONE_MASK (0xFFFFFFFFU)
#define GENFSK_TIMESTAMP_TX_DONE_TIMESTAMP_TX_DONE_SHIFT (0U)
/*! TIMESTAMP_TX_DONE - Received Packet Timestamp. Captured at Tx done.
 */
#define GENFSK_TIMESTAMP_TX_DONE_TIMESTAMP_TX_DONE(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_TIMESTAMP_TX_DONE_TIMESTAMP_TX_DONE_SHIFT)) & GENFSK_TIMESTAMP_TX_DONE_TIMESTAMP_TX_DONE_MASK)
/*! @} */

/*! @name MULT_PKT_CTRL - MULT_PKT_CTRL */
/*! @{ */

#define GENFSK_MULT_PKT_CTRL_SEG_SZ_MASK         (0xFU)
#define GENFSK_MULT_PKT_CTRL_SEG_SZ_SHIFT        (0U)
/*! SEG_SZ - RAM Segment Size
 */
#define GENFSK_MULT_PKT_CTRL_SEG_SZ(x)           (((uint32_t)(((uint32_t)(x)) << GENFSK_MULT_PKT_CTRL_SEG_SZ_SHIFT)) & GENFSK_MULT_PKT_CTRL_SEG_SZ_MASK)

#define GENFSK_MULT_PKT_CTRL_PKT_INDEX_MASK      (0x7F00U)
#define GENFSK_MULT_PKT_CTRL_PKT_INDEX_SHIFT     (8U)
/*! PKT_INDEX - Packet Index
 */
#define GENFSK_MULT_PKT_CTRL_PKT_INDEX(x)        (((uint32_t)(((uint32_t)(x)) << GENFSK_MULT_PKT_CTRL_PKT_INDEX_SHIFT)) & GENFSK_MULT_PKT_CTRL_PKT_INDEX_MASK)

#define GENFSK_MULT_PKT_CTRL_SEG_BASE_ADDR_MASK  (0xFFF0000U)
#define GENFSK_MULT_PKT_CTRL_SEG_BASE_ADDR_SHIFT (16U)
/*! SEG_BASE_ADDR - Segment Offset Address
 */
#define GENFSK_MULT_PKT_CTRL_SEG_BASE_ADDR(x)    (((uint32_t)(((uint32_t)(x)) << GENFSK_MULT_PKT_CTRL_SEG_BASE_ADDR_SHIFT)) & GENFSK_MULT_PKT_CTRL_SEG_BASE_ADDR_MASK)

#define GENFSK_MULT_PKT_CTRL_RESET_PKT_IDX_MASK  (0x40000000U)
#define GENFSK_MULT_PKT_CTRL_RESET_PKT_IDX_SHIFT (30U)
/*! RESET_PKT_IDX - Reset the PKT_INDEX to zero
 */
#define GENFSK_MULT_PKT_CTRL_RESET_PKT_IDX(x)    (((uint32_t)(((uint32_t)(x)) << GENFSK_MULT_PKT_CTRL_RESET_PKT_IDX_SHIFT)) & GENFSK_MULT_PKT_CTRL_RESET_PKT_IDX_MASK)

#define GENFSK_MULT_PKT_CTRL_MULT_PKT_EN_MASK    (0x80000000U)
#define GENFSK_MULT_PKT_CTRL_MULT_PKT_EN_SHIFT   (31U)
/*! MULT_PKT_EN - Enable to send or receive multiple packets
 *  0b0..Send or receive multiple packets is not enabled.
 *  0b1..Send or receive multiple packets is enabled.
 */
#define GENFSK_MULT_PKT_CTRL_MULT_PKT_EN(x)      (((uint32_t)(((uint32_t)(x)) << GENFSK_MULT_PKT_CTRL_MULT_PKT_EN_SHIFT)) & GENFSK_MULT_PKT_CTRL_MULT_PKT_EN_MASK)
/*! @} */

/*! @name RPA_WL_STATUS - RPA AND WHITE LIST STATUS */
/*! @{ */

#define GENFSK_RPA_WL_STATUS_WL_MATCH_INDEX_MASK (0x3FU)
#define GENFSK_RPA_WL_STATUS_WL_MATCH_INDEX_SHIFT (0U)
/*! WL_MATCH_INDEX - The matched white list index of the identity address resolved(RPA is enabled)
 *    or peer address received(RPA is not enabled)
 */
#define GENFSK_RPA_WL_STATUS_WL_MATCH_INDEX(x)   (((uint32_t)(((uint32_t)(x)) << GENFSK_RPA_WL_STATUS_WL_MATCH_INDEX_SHIFT)) & GENFSK_RPA_WL_STATUS_WL_MATCH_INDEX_MASK)

#define GENFSK_RPA_WL_STATUS_PEER_RESOLVED_INDEX_MASK (0xF0000U)
#define GENFSK_RPA_WL_STATUS_PEER_RESOLVED_INDEX_SHIFT (16U)
/*! PEER_RESOLVED_INDEX - The matched RPA index of peer address
 */
#define GENFSK_RPA_WL_STATUS_PEER_RESOLVED_INDEX(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_RPA_WL_STATUS_PEER_RESOLVED_INDEX_SHIFT)) & GENFSK_RPA_WL_STATUS_PEER_RESOLVED_INDEX_MASK)

#define GENFSK_RPA_WL_STATUS_LOCAL_RESOLVED_INDEX_MASK (0xF000000U)
#define GENFSK_RPA_WL_STATUS_LOCAL_RESOLVED_INDEX_SHIFT (24U)
/*! LOCAL_RESOLVED_INDEX - The matched RPA index of local address
 */
#define GENFSK_RPA_WL_STATUS_LOCAL_RESOLVED_INDEX(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_RPA_WL_STATUS_LOCAL_RESOLVED_INDEX_SHIFT)) & GENFSK_RPA_WL_STATUS_LOCAL_RESOLVED_INDEX_MASK)

#define GENFSK_RPA_WL_STATUS_SEARCH_WL_MASK      (0x80000000U)
#define GENFSK_RPA_WL_STATUS_SEARCH_WL_SHIFT     (31U)
/*! SEARCH_WL - Search Identity Address in White List
 */
#define GENFSK_RPA_WL_STATUS_SEARCH_WL(x)        (((uint32_t)(((uint32_t)(x)) << GENFSK_RPA_WL_STATUS_SEARCH_WL_SHIFT)) & GENFSK_RPA_WL_STATUS_SEARCH_WL_MASK)
/*! @} */

/*! @name LENGTH_MAX - MAXIMUM LENGTH */
/*! @{ */

#define GENFSK_LENGTH_MAX_LENGTH_MAX_MASK        (0x7F0000U)
#define GENFSK_LENGTH_MAX_LENGTH_MAX_SHIFT       (16U)
/*! LENGTH_MAX - Maximum Length for Received Packets
 */
#define GENFSK_LENGTH_MAX_LENGTH_MAX(x)          (((uint32_t)(((uint32_t)(x)) << GENFSK_LENGTH_MAX_LENGTH_MAX_SHIFT)) & GENFSK_LENGTH_MAX_LENGTH_MAX_MASK)

#define GENFSK_LENGTH_MAX_REC_BAD_PKT_MASK       (0x800000U)
#define GENFSK_LENGTH_MAX_REC_BAD_PKT_SHIFT      (23U)
/*! REC_BAD_PKT - Receive Bad Packets
 *  0b0..packets which fail H0, H1, or LENGTH_MAX result in an automatic recycle after the header is received and parsed
 *  0b1..packets which fail H0, H1, or LENGTH_MAX are received in their entirety
 */
#define GENFSK_LENGTH_MAX_REC_BAD_PKT(x)         (((uint32_t)(((uint32_t)(x)) << GENFSK_LENGTH_MAX_REC_BAD_PKT_SHIFT)) & GENFSK_LENGTH_MAX_REC_BAD_PKT_MASK)
/*! @} */

/*! @name EVENT_TMR_LD - EVENT TIMER LOAD */
/*! @{ */

#define GENFSK_EVENT_TMR_LD_EVENT_TMR_LD_MASK    (0xFFFFFFFFU)
#define GENFSK_EVENT_TMR_LD_EVENT_TMR_LD_SHIFT   (0U)
/*! EVENT_TMR_LD - Event Timer Load
 */
#define GENFSK_EVENT_TMR_LD_EVENT_TMR_LD(x)      (((uint32_t)(((uint32_t)(x)) << GENFSK_EVENT_TMR_LD_EVENT_TMR_LD_SHIFT)) & GENFSK_EVENT_TMR_LD_EVENT_TMR_LD_MASK)
/*! @} */

/*! @name EVENT_TMR_ADD - EVENT TIMER ADD */
/*! @{ */

#define GENFSK_EVENT_TMR_ADD_EVENT_TMR_ADD_MASK  (0xFFFFFFFFU)
#define GENFSK_EVENT_TMR_ADD_EVENT_TMR_ADD_SHIFT (0U)
/*! EVENT_TMR_ADD - Event Timer Add
 */
#define GENFSK_EVENT_TMR_ADD_EVENT_TMR_ADD(x)    (((uint32_t)(((uint32_t)(x)) << GENFSK_EVENT_TMR_ADD_EVENT_TMR_ADD_SHIFT)) & GENFSK_EVENT_TMR_ADD_EVENT_TMR_ADD_MASK)
/*! @} */

/*! @name ENH_FEATURE - ENHANCED FEATURES */
/*! @{ */

#define GENFSK_ENH_FEATURE_GENLL_MODE_MASK       (0xFU)
#define GENFSK_ENH_FEATURE_GENLL_MODE_SHIFT      (0U)
/*! GENLL_MODE - Linklayer Mode Select
 *  0b0000..GLL Mode
 *  0b0001..PAN Mode
 *  0b0010..FAN Mode
 *  0b0011..Hybrid Dual PAN Mode
 *  0b0100..Reserved
 *  0b0101..Reserved
 *  0b0110..FCP Mode
 *  0b0111..Reserved
 *  0b1000..Reserved
 *  0b1001..Bluetooth LE Uncoded Mode
 *  0b1010..Bluetooth LE LR Mode
 *  0b1011..Bluetooth LE Concurrent Mode (RX configuration only; TX uses either Bluetooth LE UNCODED or Bluetooth LE LR configuration)
 *  0b1100..Reserved
 *  0b1101..Reserved
 *  0b1110..Reserved
 *  0b1111..GTM Mode
 */
#define GENFSK_ENH_FEATURE_GENLL_MODE(x)         (((uint32_t)(((uint32_t)(x)) << GENFSK_ENH_FEATURE_GENLL_MODE_SHIFT)) & GENFSK_ENH_FEATURE_GENLL_MODE_MASK)

#define GENFSK_ENH_FEATURE_SEL_RXIRQ_MASK        (0x20U)
#define GENFSK_ENH_FEATURE_SEL_RXIRQ_SHIFT       (5U)
/*! SEL_RXIRQ - Select the RX IRQ assert time
 *  0b0..RX_IRQ is asserted at the end of RX_PKT state.
 *  0b1..RX_IRQ is asserted at the end of RXEN_DLY state. This to be used for delaying RX_IRQ to accept TERM2 bits
 *       in Bluetooth LE-LR and CTE bits as needed.
 */
#define GENFSK_ENH_FEATURE_SEL_RXIRQ(x)          (((uint32_t)(((uint32_t)(x)) << GENFSK_ENH_FEATURE_SEL_RXIRQ_SHIFT)) & GENFSK_ENH_FEATURE_SEL_RXIRQ_MASK)

#define GENFSK_ENH_FEATURE_DATARATE_CONFIG_SEL_MASK (0x40U)
#define GENFSK_ENH_FEATURE_DATARATE_CONFIG_SEL_SHIFT (6U)
/*! DATARATE_CONFIG_SEL - Select the data rate configuration bank
 *  0b0..Select the data rate as per configuration bank 0
 *  0b1..Select the data rate as per configuration bank 1
 */
#define GENFSK_ENH_FEATURE_DATARATE_CONFIG_SEL(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_ENH_FEATURE_DATARATE_CONFIG_SEL_SHIFT)) & GENFSK_ENH_FEATURE_DATARATE_CONFIG_SEL_MASK)

#define GENFSK_ENH_FEATURE_STAY_IN_RX_MASK       (0x80U)
#define GENFSK_ENH_FEATURE_STAY_IN_RX_SHIFT      (7U)
/*! STAY_IN_RX - Stay in receive
 *  0b0..Linklayer will warmdown after an RX_IRQ
 *  0b1..Linklayer will recycle and stay in receive even after an RX_IRQ.
 */
#define GENFSK_ENH_FEATURE_STAY_IN_RX(x)         (((uint32_t)(((uint32_t)(x)) << GENFSK_ENH_FEATURE_STAY_IN_RX_SHIFT)) & GENFSK_ENH_FEATURE_STAY_IN_RX_MASK)

#define GENFSK_ENH_FEATURE_PHR_TYPE_MASK         (0x700U)
#define GENFSK_ENH_FEATURE_PHR_TYPE_SHIFT        (8U)
/*! PHR_TYPE - PHR Type
 *  0b000..The packet type is GFSK
 *  0b001..The packet type is MSK
 *  0b010..The packet type is SUN FSK
 *  0b011..The packet type is LECIM FSK
 */
#define GENFSK_ENH_FEATURE_PHR_TYPE(x)           (((uint32_t)(((uint32_t)(x)) << GENFSK_ENH_FEATURE_PHR_TYPE_SHIFT)) & GENFSK_ENH_FEATURE_PHR_TYPE_MASK)

#define GENFSK_ENH_FEATURE_SW_BUILD_ACK_MASK     (0x800U)
#define GENFSK_ENH_FEATURE_SW_BUILD_ACK_SHIFT    (11U)
/*! SW_BUILD_ACK - Software builds the ACK packet in RAM
 *  0b0..Hardware builds part of or the whole of the auto ACK frame
 *  0b1..Software builds the whole auto ACK frame in RAM.
 */
#define GENFSK_ENH_FEATURE_SW_BUILD_ACK(x)       (((uint32_t)(((uint32_t)(x)) << GENFSK_ENH_FEATURE_SW_BUILD_ACK_SHIFT)) & GENFSK_ENH_FEATURE_SW_BUILD_ACK_MASK)

#define GENFSK_ENH_FEATURE_ACKBUF_SEL_MASK       (0x1000U)
#define GENFSK_ENH_FEATURE_ACKBUF_SEL_SHIFT      (12U)
/*! ACKBUF_SEL - ACK frame is in 64-byte dedicated RAM or TX buffer RAM
 *  0b0..ACK frame is in 64-byte dedicated RAM
 *  0b1..ACK frame is in TX buffer RAM
 */
#define GENFSK_ENH_FEATURE_ACKBUF_SEL(x)         (((uint32_t)(((uint32_t)(x)) << GENFSK_ENH_FEATURE_ACKBUF_SEL_SHIFT)) & GENFSK_ENH_FEATURE_ACKBUF_SEL_MASK)

#define GENFSK_ENH_FEATURE_AUTOACK_MASK          (0x2000U)
#define GENFSK_ENH_FEATURE_AUTOACK_SHIFT         (13U)
/*! AUTOACK - Auto Acknowledge Enable
 *  0b0..sequence manager will not follow a receive frame with a Tx Ack frame, under any conditions; the
 *       autosequence will terminate after the receive frame.
 *  0b1..sequence manager will follow a receive frame with an automatic hardware-generated Tx Ack frame, assuming other necessary conditions are met.
 */
#define GENFSK_ENH_FEATURE_AUTOACK(x)            (((uint32_t)(((uint32_t)(x)) << GENFSK_ENH_FEATURE_AUTOACK_SHIFT)) & GENFSK_ENH_FEATURE_AUTOACK_MASK)

#define GENFSK_ENH_FEATURE_RXACKRQD_MASK         (0x4000U)
#define GENFSK_ENH_FEATURE_RXACKRQD_SHIFT        (14U)
/*! RXACKRQD - Receive Acknowledge Frame required
 *  0b0..An ordinary receive frame (any type of frame) follows the transmit frame.
 *  0b1..A receive Ack frame is expected to follow the transmit frame (non-Ack frames are rejected).
 */
#define GENFSK_ENH_FEATURE_RXACKRQD(x)           (((uint32_t)(((uint32_t)(x)) << GENFSK_ENH_FEATURE_RXACKRQD_SHIFT)) & GENFSK_ENH_FEATURE_RXACKRQD_MASK)

#define GENFSK_ENH_FEATURE_SLOTTED_MASK          (0x8000U)
#define GENFSK_ENH_FEATURE_SLOTTED_SHIFT         (15U)
/*! SLOTTED - Slotted Mode
 */
#define GENFSK_ENH_FEATURE_SLOTTED(x)            (((uint32_t)(((uint32_t)(x)) << GENFSK_ENH_FEATURE_SLOTTED_SHIFT)) & GENFSK_ENH_FEATURE_SLOTTED_MASK)

#define GENFSK_ENH_FEATURE_LENGTH_ACK_MASK       (0x7FF0000U)
#define GENFSK_ENH_FEATURE_LENGTH_ACK_SHIFT      (16U)
/*! LENGTH_ACK - Length of the ACK frame(or part of the ACK frame) in RAM
 */
#define GENFSK_ENH_FEATURE_LENGTH_ACK(x)         (((uint32_t)(((uint32_t)(x)) << GENFSK_ENH_FEATURE_LENGTH_ACK_SHIFT)) & GENFSK_ENH_FEATURE_LENGTH_ACK_MASK)

#define GENFSK_ENH_FEATURE_BLE_V5P1_CTE_EN_MASK  (0x80000000U)
#define GENFSK_ENH_FEATURE_BLE_V5P1_CTE_EN_SHIFT (31U)
/*! BLE_V5P1_CTE_EN - Bluetooth LE version 5.1 CTE feature enable
 *  0b0..Do not support Bluetooth LE version 5.1 CTE feature.
 *  0b1..Support Bluetooth LE version 5.1 CTE feature, which means the link layer hardware can parse the CTE field
 *       length and extend the RX_EN signal accordingly.
 */
#define GENFSK_ENH_FEATURE_BLE_V5P1_CTE_EN(x)    (((uint32_t)(((uint32_t)(x)) << GENFSK_ENH_FEATURE_BLE_V5P1_CTE_EN_SHIFT)) & GENFSK_ENH_FEATURE_BLE_V5P1_CTE_EN_MASK)
/*! @} */

/*! @name RX_FRAME_FILTER - RECEIVE FRAME FILTER */
/*! @{ */

#define GENFSK_RX_FRAME_FILTER_BEACON_FT_MASK    (0x1U)
#define GENFSK_RX_FRAME_FILTER_BEACON_FT_SHIFT   (0U)
/*! BEACON_FT - Beacon Frame Type Enable
 *  0b0..reject all Beacon frames
 *  0b1..Beacon frame type enabled.
 */
#define GENFSK_RX_FRAME_FILTER_BEACON_FT(x)      (((uint32_t)(((uint32_t)(x)) << GENFSK_RX_FRAME_FILTER_BEACON_FT_SHIFT)) & GENFSK_RX_FRAME_FILTER_BEACON_FT_MASK)

#define GENFSK_RX_FRAME_FILTER_DATA_FT_MASK      (0x2U)
#define GENFSK_RX_FRAME_FILTER_DATA_FT_SHIFT     (1U)
/*! DATA_FT - Data Frame Type Enable
 *  0b0..reject all Beacon frames
 *  0b1..Data frame type enabled.
 */
#define GENFSK_RX_FRAME_FILTER_DATA_FT(x)        (((uint32_t)(((uint32_t)(x)) << GENFSK_RX_FRAME_FILTER_DATA_FT_SHIFT)) & GENFSK_RX_FRAME_FILTER_DATA_FT_MASK)

#define GENFSK_RX_FRAME_FILTER_ACK_FT_MASK       (0x4U)
#define GENFSK_RX_FRAME_FILTER_ACK_FT_SHIFT      (2U)
/*! ACK_FT - Ack Frame Type Enable
 *  0b0..reject all Acknowledge frames
 *  0b1..Acknowledge frame type enabled.
 */
#define GENFSK_RX_FRAME_FILTER_ACK_FT(x)         (((uint32_t)(((uint32_t)(x)) << GENFSK_RX_FRAME_FILTER_ACK_FT_SHIFT)) & GENFSK_RX_FRAME_FILTER_ACK_FT_MASK)

#define GENFSK_RX_FRAME_FILTER_CMD_FT_MASK       (0x8U)
#define GENFSK_RX_FRAME_FILTER_CMD_FT_SHIFT      (3U)
/*! CMD_FT - MAC Command Frame Type Enable
 *  0b0..reject all MAC Command frames
 *  0b1..MAC Command frame type enabled.
 */
#define GENFSK_RX_FRAME_FILTER_CMD_FT(x)         (((uint32_t)(((uint32_t)(x)) << GENFSK_RX_FRAME_FILTER_CMD_FT_SHIFT)) & GENFSK_RX_FRAME_FILTER_CMD_FT_MASK)

#define GENFSK_RX_FRAME_FILTER_LLDN_FT_MASK      (0x10U)
#define GENFSK_RX_FRAME_FILTER_LLDN_FT_SHIFT     (4U)
/*! LLDN_FT - LLDN Frame Type Enable
 *  0b0..reject all LLDN frames
 *  0b1..LLDN frame type enabled (Frame Type 4).
 */
#define GENFSK_RX_FRAME_FILTER_LLDN_FT(x)        (((uint32_t)(((uint32_t)(x)) << GENFSK_RX_FRAME_FILTER_LLDN_FT_SHIFT)) & GENFSK_RX_FRAME_FILTER_LLDN_FT_MASK)

#define GENFSK_RX_FRAME_FILTER_MULTIPURPOSE_FT_MASK (0x20U)
#define GENFSK_RX_FRAME_FILTER_MULTIPURPOSE_FT_SHIFT (5U)
/*! MULTIPURPOSE_FT - Multipurpose Frame Type Enable
 *  0b0..reject all Multipurpose frames
 *  0b1..Multipurpose frame type enabled (Frame Type 5).
 */
#define GENFSK_RX_FRAME_FILTER_MULTIPURPOSE_FT(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_RX_FRAME_FILTER_MULTIPURPOSE_FT_SHIFT)) & GENFSK_RX_FRAME_FILTER_MULTIPURPOSE_FT_MASK)

#define GENFSK_RX_FRAME_FILTER_FRAGMENT_FT_MASK  (0x40U)
#define GENFSK_RX_FRAME_FILTER_FRAGMENT_FT_SHIFT (6U)
/*! FRAGMENT_FT - Fragment Frame Type Enable
 *  0b0..reject all Fragment frames
 *  0b1..Fragment frame type enabled (Frame Type 6).
 */
#define GENFSK_RX_FRAME_FILTER_FRAGMENT_FT(x)    (((uint32_t)(((uint32_t)(x)) << GENFSK_RX_FRAME_FILTER_FRAGMENT_FT_SHIFT)) & GENFSK_RX_FRAME_FILTER_FRAGMENT_FT_MASK)

#define GENFSK_RX_FRAME_FILTER_EXTENDED_FT_MASK  (0x80U)
#define GENFSK_RX_FRAME_FILTER_EXTENDED_FT_SHIFT (7U)
/*! EXTENDED_FT - Extended Frame Type Enable
 *  0b0..reject all Extended frames
 *  0b1..Extended frame type enabled (Frame Type 7).
 */
#define GENFSK_RX_FRAME_FILTER_EXTENDED_FT(x)    (((uint32_t)(((uint32_t)(x)) << GENFSK_RX_FRAME_FILTER_EXTENDED_FT_SHIFT)) & GENFSK_RX_FRAME_FILTER_EXTENDED_FT_MASK)

#define GENFSK_RX_FRAME_FILTER_NS_FT_MASK        (0x100U)
#define GENFSK_RX_FRAME_FILTER_NS_FT_SHIFT       (8U)
/*! NS_FT - "Not Specified" Frame Type Enable
 *  0b0..reject all "Not Specified" frames
 *  0b1..Not-specified (reserved) frame type enabled. Applies to Frame Type 6. No packet filtering is performed,
 *       except for frame length checking (FrameLength>=5 and FrameLength<=127). No AUTOACK is transmitted for this
 *       Frame Type
 */
#define GENFSK_RX_FRAME_FILTER_NS_FT(x)          (((uint32_t)(((uint32_t)(x)) << GENFSK_RX_FRAME_FILTER_NS_FT_SHIFT)) & GENFSK_RX_FRAME_FILTER_NS_FT_MASK)

#define GENFSK_RX_FRAME_FILTER_FRM_VER_FILTER_MASK (0x1E00U)
#define GENFSK_RX_FRAME_FILTER_FRM_VER_FILTER_SHIFT (9U)
/*! FRM_VER_FILTER - Frame Version selector.
 */
#define GENFSK_RX_FRAME_FILTER_FRM_VER_FILTER(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_RX_FRAME_FILTER_FRM_VER_FILTER_SHIFT)) & GENFSK_RX_FRAME_FILTER_FRM_VER_FILTER_MASK)

#define GENFSK_RX_FRAME_FILTER_EXTENDED_FCS_CHK_MASK (0x8000U)
#define GENFSK_RX_FRAME_FILTER_EXTENDED_FCS_CHK_SHIFT (15U)
/*! EXTENDED_FCS_CHK - Verify FCS on Frame Type Extended
 *  0b0..Packet Processor will not check FCS for Frame Type EXTENDED (default)
 *  0b1..Packet Processor will check FCS at end-of-packet based on packet length derived from PHR, for Frame Type EXTENDED
 */
#define GENFSK_RX_FRAME_FILTER_EXTENDED_FCS_CHK(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_RX_FRAME_FILTER_EXTENDED_FCS_CHK_SHIFT)) & GENFSK_RX_FRAME_FILTER_EXTENDED_FCS_CHK_MASK)

#define GENFSK_RX_FRAME_FILTER_FV2_BEACON_RECD_MASK (0x10000U)
#define GENFSK_RX_FRAME_FILTER_FV2_BEACON_RECD_SHIFT (16U)
/*! FV2_BEACON_RECD - Frame Version 2 Beacon Packet Received
 *  0b0..The last packet received was not Frame Type Beacon with Frame Version 2
 *  0b1..The last packet received was Frame Type Beacon with Frame Version 2, and FRM_VER_FILTER[2]=1 to allow such packets
 */
#define GENFSK_RX_FRAME_FILTER_FV2_BEACON_RECD(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_RX_FRAME_FILTER_FV2_BEACON_RECD_SHIFT)) & GENFSK_RX_FRAME_FILTER_FV2_BEACON_RECD_MASK)

#define GENFSK_RX_FRAME_FILTER_FV2_DATA_RECD_MASK (0x20000U)
#define GENFSK_RX_FRAME_FILTER_FV2_DATA_RECD_SHIFT (17U)
/*! FV2_DATA_RECD - Frame Version 2 Data Packet Received
 *  0b0..The last packet received was not Frame Type Data with Frame Version 2
 *  0b1..The last packet received was Frame Type Data with Frame Version 2, and FRM_VER_FILTER[2]=1 to allow such packets
 */
#define GENFSK_RX_FRAME_FILTER_FV2_DATA_RECD(x)  (((uint32_t)(((uint32_t)(x)) << GENFSK_RX_FRAME_FILTER_FV2_DATA_RECD_SHIFT)) & GENFSK_RX_FRAME_FILTER_FV2_DATA_RECD_MASK)

#define GENFSK_RX_FRAME_FILTER_FV2_ACK_RECD_MASK (0x40000U)
#define GENFSK_RX_FRAME_FILTER_FV2_ACK_RECD_SHIFT (18U)
/*! FV2_ACK_RECD - Frame Version 2 Acknowledge Packet Received
 *  0b0..The last packet received was not Frame Type Ack with Frame Version 2
 *  0b1..The last packet received was Frame Type Ack with Frame Version 2, and FRM_VER_FILTER[2]=1 to allow such packets
 */
#define GENFSK_RX_FRAME_FILTER_FV2_ACK_RECD(x)   (((uint32_t)(((uint32_t)(x)) << GENFSK_RX_FRAME_FILTER_FV2_ACK_RECD_SHIFT)) & GENFSK_RX_FRAME_FILTER_FV2_ACK_RECD_MASK)

#define GENFSK_RX_FRAME_FILTER_FV2_CMD_RECD_MASK (0x80000U)
#define GENFSK_RX_FRAME_FILTER_FV2_CMD_RECD_SHIFT (19U)
/*! FV2_CMD_RECD - Frame Version 2 MAC Command Packet Received
 *  0b0..The last packet received was not Frame Type MAC Command with Frame Version 2
 *  0b1..The last packet received was Frame Type MAC Command with Frame Version 2, and FRM_VER_FILTER[2]=1 to allow such packets
 */
#define GENFSK_RX_FRAME_FILTER_FV2_CMD_RECD(x)   (((uint32_t)(((uint32_t)(x)) << GENFSK_RX_FRAME_FILTER_FV2_CMD_RECD_SHIFT)) & GENFSK_RX_FRAME_FILTER_FV2_CMD_RECD_MASK)

#define GENFSK_RX_FRAME_FILTER_LLDN_RECD_MASK    (0x100000U)
#define GENFSK_RX_FRAME_FILTER_LLDN_RECD_SHIFT   (20U)
/*! LLDN_RECD - LLDN Packet Received
 *  0b0..The last packet received was not Frame Type LLDN
 *  0b1..The last packet received was Frame Type LLDN, and LLDN_FT=1 to allow such packets.
 */
#define GENFSK_RX_FRAME_FILTER_LLDN_RECD(x)      (((uint32_t)(((uint32_t)(x)) << GENFSK_RX_FRAME_FILTER_LLDN_RECD_SHIFT)) & GENFSK_RX_FRAME_FILTER_LLDN_RECD_MASK)

#define GENFSK_RX_FRAME_FILTER_MULTIPURPOSE_RECD_MASK (0x200000U)
#define GENFSK_RX_FRAME_FILTER_MULTIPURPOSE_RECD_SHIFT (21U)
/*! MULTIPURPOSE_RECD - Multipurpose Packet Received
 *  0b0..last packet received was not Frame Type MULTIPURPOSE
 *  0b1..The last packet received was Frame Type MULTIPURPOSE, and MULTIPURPOSE_FT=1 to allow such packets.
 */
#define GENFSK_RX_FRAME_FILTER_MULTIPURPOSE_RECD(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_RX_FRAME_FILTER_MULTIPURPOSE_RECD_SHIFT)) & GENFSK_RX_FRAME_FILTER_MULTIPURPOSE_RECD_MASK)

#define GENFSK_RX_FRAME_FILTER_FRAGMENT_RECD_MASK (0x400000U)
#define GENFSK_RX_FRAME_FILTER_FRAGMENT_RECD_SHIFT (22U)
/*! FRAGMENT_RECD - Fragment Packet Received
 *  0b0..last packet received was not Frame Type FRAGMENT
 *  0b1..The last packet received was Frame Type FRAGMENT, and FRAGMENT_FT=1 to allow such packets.
 */
#define GENFSK_RX_FRAME_FILTER_FRAGMENT_RECD(x)  (((uint32_t)(((uint32_t)(x)) << GENFSK_RX_FRAME_FILTER_FRAGMENT_RECD_SHIFT)) & GENFSK_RX_FRAME_FILTER_FRAGMENT_RECD_MASK)

#define GENFSK_RX_FRAME_FILTER_EXTENDED_RECD_MASK (0x800000U)
#define GENFSK_RX_FRAME_FILTER_EXTENDED_RECD_SHIFT (23U)
/*! EXTENDED_RECD - Extended Packet Received
 *  0b0..The last packet received was not Frame Type EXTENDED
 *  0b1..The last packet received was Frame Type EXTENDED, and EXTENDED_FT=1 to allow such packets.
 */
#define GENFSK_RX_FRAME_FILTER_EXTENDED_RECD(x)  (((uint32_t)(((uint32_t)(x)) << GENFSK_RX_FRAME_FILTER_EXTENDED_RECD_SHIFT)) & GENFSK_RX_FRAME_FILTER_EXTENDED_RECD_MASK)

#define GENFSK_RX_FRAME_FILTER_RXCYC_SEL_MASK    (0x10000000U)
#define GENFSK_RX_FRAME_FILTER_RXCYC_SEL_SHIFT   (28U)
/*! RXCYC_SEL - Rx Recycle Time Select
 *  0b0..Recycle when fail happens.
 *  0b1..Recycle when Rx done and fail happens.
 */
#define GENFSK_RX_FRAME_FILTER_RXCYC_SEL(x)      (((uint32_t)(((uint32_t)(x)) << GENFSK_RX_FRAME_FILTER_RXCYC_SEL_SHIFT)) & GENFSK_RX_FRAME_FILTER_RXCYC_SEL_MASK)

#define GENFSK_RX_FRAME_FILTER_FILTER_FAIL_IGNORE_MASK (0x20000000U)
#define GENFSK_RX_FRAME_FILTER_FILTER_FAIL_IGNORE_SHIFT (29U)
/*! FILTER_FAIL_IGNORE - Filter Fail Ignore
 *  0b0..RX_IRQ will not be asserted when filter fail.
 *  0b1..RX_IRQ will be asserted when filter fail.
 */
#define GENFSK_RX_FRAME_FILTER_FILTER_FAIL_IGNORE(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_RX_FRAME_FILTER_FILTER_FAIL_IGNORE_SHIFT)) & GENFSK_RX_FRAME_FILTER_FILTER_FAIL_IGNORE_MASK)

#define GENFSK_RX_FRAME_FILTER_PROMISCUOUS_MASK  (0x40000000U)
#define GENFSK_RX_FRAME_FILTER_PROMISCUOUS_SHIFT (30U)
/*! PROMISCUOUS - Promiscuous Mode Enable
 *  0b0..normal mode
 *  0b1..all packet filtering except frame length checking (FrameLength>=5) is bypassed.
 */
#define GENFSK_RX_FRAME_FILTER_PROMISCUOUS(x)    (((uint32_t)(((uint32_t)(x)) << GENFSK_RX_FRAME_FILTER_PROMISCUOUS_SHIFT)) & GENFSK_RX_FRAME_FILTER_PROMISCUOUS_MASK)

#define GENFSK_RX_FRAME_FILTER_ENH_PKT_STATUS_MASK (0x80000000U)
#define GENFSK_RX_FRAME_FILTER_ENH_PKT_STATUS_SHIFT (31U)
/*! ENH_PKT_STATUS - Enhanced Packet Status
 *  0b0..The last packet received was not 2015-compliant
 *  0b1..The last packet received was 2015-compliant (RX_FRAME_FILTER register should be queried for additional status bits)
 */
#define GENFSK_RX_FRAME_FILTER_ENH_PKT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_RX_FRAME_FILTER_ENH_PKT_STATUS_SHIFT)) & GENFSK_RX_FRAME_FILTER_ENH_PKT_STATUS_MASK)
/*! @} */

/*! @name FILTERFAIL_CODE - FILTER FAIL CODE */
/*! @{ */

#define GENFSK_FILTERFAIL_CODE_FILTERFAIL_CODE_PAN_MASK (0x3FFU)
#define GENFSK_FILTERFAIL_CODE_FILTERFAIL_CODE_PAN_SHIFT (0U)
/*! FILTERFAIL_CODE_PAN - Filter Fail Code When in PAN Mode
 */
#define GENFSK_FILTERFAIL_CODE_FILTERFAIL_CODE_PAN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_FILTERFAIL_CODE_FILTERFAIL_CODE_PAN_SHIFT)) & GENFSK_FILTERFAIL_CODE_FILTERFAIL_CODE_PAN_MASK)

#define GENFSK_FILTERFAIL_CODE_FILTERFAIL_CODE_FAN_MASK (0x30000U)
#define GENFSK_FILTERFAIL_CODE_FILTERFAIL_CODE_FAN_SHIFT (16U)
/*! FILTERFAIL_CODE_FAN - Filter Fail Code When in FAN Mode
 */
#define GENFSK_FILTERFAIL_CODE_FILTERFAIL_CODE_FAN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_FILTERFAIL_CODE_FILTERFAIL_CODE_FAN_SHIFT)) & GENFSK_FILTERFAIL_CODE_FILTERFAIL_CODE_FAN_MASK)

#define GENFSK_FILTERFAIL_CODE_FILTERFAIL_PAN_SEL_MASK (0x40000000U)
#define GENFSK_FILTERFAIL_CODE_FILTERFAIL_PAN_SEL_SHIFT (30U)
/*! FILTERFAIL_PAN_SEL - PAN Selector for Filter Fail Code
 *  0b0..FILTERFAIL_CODE_PAN/FILTERFAIL_CODE_FAN will report the FILTERFAIL status of PAN0
 *  0b1..FILTERFAIL_CODE_PAN/FILTERFAIL_CODE_FAN will report the FILTERFAIL status of PAN1
 */
#define GENFSK_FILTERFAIL_CODE_FILTERFAIL_PAN_SEL(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_FILTERFAIL_CODE_FILTERFAIL_PAN_SEL_SHIFT)) & GENFSK_FILTERFAIL_CODE_FILTERFAIL_PAN_SEL_MASK)

#define GENFSK_FILTERFAIL_CODE_FILTERFAIL_FLAG_SEL_MASK (0x80000000U)
#define GENFSK_FILTERFAIL_CODE_FILTERFAIL_FLAG_SEL_SHIFT (31U)
/*! FILTERFAIL_FLAG_SEL - Consolidated Filter Fail Flag
 */
#define GENFSK_FILTERFAIL_CODE_FILTERFAIL_FLAG_SEL(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_FILTERFAIL_CODE_FILTERFAIL_FLAG_SEL_SHIFT)) & GENFSK_FILTERFAIL_CODE_FILTERFAIL_FLAG_SEL_MASK)
/*! @} */

/*! @name LENIENCY_LSB - LENIENCY LSB */
/*! @{ */

#define GENFSK_LENIENCY_LSB_LENIENCY_LSB_MASK    (0xFFFFFFFFU)
#define GENFSK_LENIENCY_LSB_LENIENCY_LSB_SHIFT   (0U)
/*! LENIENCY_LSB - Leniency LSB Register
 */
#define GENFSK_LENIENCY_LSB_LENIENCY_LSB(x)      (((uint32_t)(((uint32_t)(x)) << GENFSK_LENIENCY_LSB_LENIENCY_LSB_SHIFT)) & GENFSK_LENIENCY_LSB_LENIENCY_LSB_MASK)
/*! @} */

/*! @name RPA_CTRL - RPA CONTROL */
/*! @{ */

#define GENFSK_RPA_CTRL_RPA_VALID_ENTRY_MASK     (0xFFU)
#define GENFSK_RPA_CTRL_RPA_VALID_ENTRY_SHIFT    (0U)
#define GENFSK_RPA_CTRL_RPA_VALID_ENTRY(x)       (((uint32_t)(((uint32_t)(x)) << GENFSK_RPA_CTRL_RPA_VALID_ENTRY_SHIFT)) & GENFSK_RPA_CTRL_RPA_VALID_ENTRY_MASK)

#define GENFSK_RPA_CTRL_IGNORE_RPA_FAIL_MASK     (0x8000000U)
#define GENFSK_RPA_CTRL_IGNORE_RPA_FAIL_SHIFT    (27U)
/*! IGNORE_RPA_FAIL
 *  0b0..link layer aborts the Rx process when LOCAL_RPA_FAIL_IRQ or PEER_RPA_FAIL_IRQ
 *  0b1..link layer ignores LOCAL_RPA_FAIL_IRQ and PEER_RPA_FAIL_IRQ.
 */
#define GENFSK_RPA_CTRL_IGNORE_RPA_FAIL(x)       (((uint32_t)(((uint32_t)(x)) << GENFSK_RPA_CTRL_IGNORE_RPA_FAIL_SHIFT)) & GENFSK_RPA_CTRL_IGNORE_RPA_FAIL_MASK)

#define GENFSK_RPA_CTRL_IGNORE_DIRECT_FAIL_MASK  (0x10000000U)
#define GENFSK_RPA_CTRL_IGNORE_DIRECT_FAIL_SHIFT (28U)
/*! IGNORE_DIRECT_FAIL
 *  0b0..link layer aborts the Rx process when DIRECT_ID_FAIL_IRQ
 *  0b1..link layer ignores DIRECT_ID_FAIL_IRQ.
 */
#define GENFSK_RPA_CTRL_IGNORE_DIRECT_FAIL(x)    (((uint32_t)(((uint32_t)(x)) << GENFSK_RPA_CTRL_IGNORE_DIRECT_FAIL_SHIFT)) & GENFSK_RPA_CTRL_IGNORE_DIRECT_FAIL_MASK)

#define GENFSK_RPA_CTRL_ADV_DIRECT_IND_SENT_MASK (0x20000000U)
#define GENFSK_RPA_CTRL_ADV_DIRECT_IND_SENT_SHIFT (29U)
#define GENFSK_RPA_CTRL_ADV_DIRECT_IND_SENT(x)   (((uint32_t)(((uint32_t)(x)) << GENFSK_RPA_CTRL_ADV_DIRECT_IND_SENT_SHIFT)) & GENFSK_RPA_CTRL_ADV_DIRECT_IND_SENT_MASK)

#define GENFSK_RPA_CTRL_RPA_EN_MASK              (0x40000000U)
#define GENFSK_RPA_CTRL_RPA_EN_SHIFT             (30U)
/*! RPA_EN
 *  0b0..The RPA check is disabled.
 *  0b1..The RPA check is enabled.
 */
#define GENFSK_RPA_CTRL_RPA_EN(x)                (((uint32_t)(((uint32_t)(x)) << GENFSK_RPA_CTRL_RPA_EN_SHIFT)) & GENFSK_RPA_CTRL_RPA_EN_MASK)

#define GENFSK_RPA_CTRL_ADV_CHANNEL_EN_MASK      (0x80000000U)
#define GENFSK_RPA_CTRL_ADV_CHANNEL_EN_SHIFT     (31U)
/*! ADV_CHANNEL_EN
 *  0b0..The packet to be received is in Data Channel PDU.
 *  0b1..The packet to be received is in Advertising Channel PDU.
 */
#define GENFSK_RPA_CTRL_ADV_CHANNEL_EN(x)        (((uint32_t)(((uint32_t)(x)) << GENFSK_RPA_CTRL_ADV_CHANNEL_EN_SHIFT)) & GENFSK_RPA_CTRL_ADV_CHANNEL_EN_MASK)
/*! @} */

/*! @name LENIENCY_MSB - LENIENCY MSB */
/*! @{ */

#define GENFSK_LENIENCY_MSB_LENIENCY_MSB_MASK    (0x1FFFU)
#define GENFSK_LENIENCY_MSB_LENIENCY_MSB_SHIFT   (0U)
/*! LENIENCY_MSB - Leniency MSB Register
 */
#define GENFSK_LENIENCY_MSB_LENIENCY_MSB(x)      (((uint32_t)(((uint32_t)(x)) << GENFSK_LENIENCY_MSB_LENIENCY_MSB_SHIFT)) & GENFSK_LENIENCY_MSB_LENIENCY_MSB_MASK)
/*! @} */

/*! @name WL_CTRL - WHITE LIST CONTROL */
/*! @{ */

#define GENFSK_WL_CTRL_WL_EN_MASK                (0x1U)
#define GENFSK_WL_CTRL_WL_EN_SHIFT               (0U)
/*! WL_EN
 *  0b0..White list search is not enabled
 *  0b1..White list search is enabled
 */
#define GENFSK_WL_CTRL_WL_EN(x)                  (((uint32_t)(((uint32_t)(x)) << GENFSK_WL_CTRL_WL_EN_SHIFT)) & GENFSK_WL_CTRL_WL_EN_MASK)

#define GENFSK_WL_CTRL_WL_SEL_MASK               (0x2U)
#define GENFSK_WL_CTRL_WL_SEL_SHIFT              (1U)
/*! WL_SEL
 *  0b0..Select white list 0
 *  0b1..Select white list 1
 */
#define GENFSK_WL_CTRL_WL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << GENFSK_WL_CTRL_WL_SEL_SHIFT)) & GENFSK_WL_CTRL_WL_SEL_MASK)

#define GENFSK_WL_CTRL_IGNORE_WL_FAIL_MASK       (0x8U)
#define GENFSK_WL_CTRL_IGNORE_WL_FAIL_SHIFT      (3U)
/*! IGNORE_WL_FAIL
 *  0b0..link layer aborts the Rx process when WL_FAIL_IRQ
 *  0b1..link layer ignores WL_FAIL_IRQ.
 */
#define GENFSK_WL_CTRL_IGNORE_WL_FAIL(x)         (((uint32_t)(((uint32_t)(x)) << GENFSK_WL_CTRL_IGNORE_WL_FAIL_SHIFT)) & GENFSK_WL_CTRL_IGNORE_WL_FAIL_MASK)
/*! @} */

/*! @name DUAL_PAN_CTRL - DUAL PAN CONTROL */
/*! @{ */

#define GENFSK_DUAL_PAN_CTRL_ACTIVE_NETWORK_MASK (0x1U)
#define GENFSK_DUAL_PAN_CTRL_ACTIVE_NETWORK_SHIFT (0U)
/*! ACTIVE_NETWORK - Active Network Selector
 *  0b0..Select PAN0
 *  0b1..Select PAN1
 */
#define GENFSK_DUAL_PAN_CTRL_ACTIVE_NETWORK(x)   (((uint32_t)(((uint32_t)(x)) << GENFSK_DUAL_PAN_CTRL_ACTIVE_NETWORK_SHIFT)) & GENFSK_DUAL_PAN_CTRL_ACTIVE_NETWORK_MASK)

#define GENFSK_DUAL_PAN_CTRL_DUAL_PAN_AUTO_MASK  (0x2U)
#define GENFSK_DUAL_PAN_CTRL_DUAL_PAN_AUTO_SHIFT (1U)
/*! DUAL_PAN_AUTO - Activates automatic Dual PAN operating mode
 */
#define GENFSK_DUAL_PAN_CTRL_DUAL_PAN_AUTO(x)    (((uint32_t)(((uint32_t)(x)) << GENFSK_DUAL_PAN_CTRL_DUAL_PAN_AUTO_SHIFT)) & GENFSK_DUAL_PAN_CTRL_DUAL_PAN_AUTO_MASK)

#define GENFSK_DUAL_PAN_CTRL_CURRENT_NETWORK_MASK (0x4U)
#define GENFSK_DUAL_PAN_CTRL_CURRENT_NETWORK_SHIFT (2U)
/*! CURRENT_NETWORK - Indicates which PAN is currently selected by hardware
 *  0b0..PAN0 is selected
 *  0b1..PAN1 is selected
 */
#define GENFSK_DUAL_PAN_CTRL_CURRENT_NETWORK(x)  (((uint32_t)(((uint32_t)(x)) << GENFSK_DUAL_PAN_CTRL_CURRENT_NETWORK_SHIFT)) & GENFSK_DUAL_PAN_CTRL_CURRENT_NETWORK_MASK)

#define GENFSK_DUAL_PAN_CTRL_DUAL_PAN_DWELL_MASK (0xFF00U)
#define GENFSK_DUAL_PAN_CTRL_DUAL_PAN_DWELL_SHIFT (8U)
/*! DUAL_PAN_DWELL - Dual PAN Channel Frequency Dwell Time
 */
#define GENFSK_DUAL_PAN_CTRL_DUAL_PAN_DWELL(x)   (((uint32_t)(((uint32_t)(x)) << GENFSK_DUAL_PAN_CTRL_DUAL_PAN_DWELL_SHIFT)) & GENFSK_DUAL_PAN_CTRL_DUAL_PAN_DWELL_MASK)

#define GENFSK_DUAL_PAN_CTRL_DUAL_PAN_REMAIN_MASK (0x3F0000U)
#define GENFSK_DUAL_PAN_CTRL_DUAL_PAN_REMAIN_SHIFT (16U)
/*! DUAL_PAN_REMAIN - Time Remaining before next PAN switch in auto Dual PAN mode
 */
#define GENFSK_DUAL_PAN_CTRL_DUAL_PAN_REMAIN(x)  (((uint32_t)(((uint32_t)(x)) << GENFSK_DUAL_PAN_CTRL_DUAL_PAN_REMAIN_SHIFT)) & GENFSK_DUAL_PAN_CTRL_DUAL_PAN_REMAIN_MASK)

#define GENFSK_DUAL_PAN_CTRL_MODE_PAN0_MASK      (0x1000000U)
#define GENFSK_DUAL_PAN_CTRL_MODE_PAN0_SHIFT     (24U)
/*! MODE_PAN0 - PAN0 Mode Select
 *  0b0..PAN0 is in PAN mode
 *  0b1..PAN0 is in FAN mode
 */
#define GENFSK_DUAL_PAN_CTRL_MODE_PAN0(x)        (((uint32_t)(((uint32_t)(x)) << GENFSK_DUAL_PAN_CTRL_MODE_PAN0_SHIFT)) & GENFSK_DUAL_PAN_CTRL_MODE_PAN0_MASK)

#define GENFSK_DUAL_PAN_CTRL_MODE_PAN1_MASK      (0x2000000U)
#define GENFSK_DUAL_PAN_CTRL_MODE_PAN1_SHIFT     (25U)
/*! MODE_PAN1 - PAN1 Mode Select
 *  0b0..PAN1 is in PAN mode
 *  0b1..PAN1 is in FAN mode
 */
#define GENFSK_DUAL_PAN_CTRL_MODE_PAN1(x)        (((uint32_t)(((uint32_t)(x)) << GENFSK_DUAL_PAN_CTRL_MODE_PAN1_SHIFT)) & GENFSK_DUAL_PAN_CTRL_MODE_PAN1_MASK)

#define GENFSK_DUAL_PAN_CTRL_DP_CHAN_OVRD_EN_MASK (0x4000000U)
#define GENFSK_DUAL_PAN_CTRL_DP_CHAN_OVRD_EN_SHIFT (26U)
/*! DP_CHAN_OVRD_EN - Dual PAN Channel Override Enable
 */
#define GENFSK_DUAL_PAN_CTRL_DP_CHAN_OVRD_EN(x)  (((uint32_t)(((uint32_t)(x)) << GENFSK_DUAL_PAN_CTRL_DP_CHAN_OVRD_EN_SHIFT)) & GENFSK_DUAL_PAN_CTRL_DP_CHAN_OVRD_EN_MASK)

#define GENFSK_DUAL_PAN_CTRL_DP_CHAN_OVRD_SEL_MASK (0x8000000U)
#define GENFSK_DUAL_PAN_CTRL_DP_CHAN_OVRD_SEL_SHIFT (27U)
/*! DP_CHAN_OVRD_SEL - Dual PAN Channel Override Selector
 */
#define GENFSK_DUAL_PAN_CTRL_DP_CHAN_OVRD_SEL(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_DUAL_PAN_CTRL_DP_CHAN_OVRD_SEL_SHIFT)) & GENFSK_DUAL_PAN_CTRL_DP_CHAN_OVRD_SEL_MASK)

#define GENFSK_DUAL_PAN_CTRL_PANCORDNTR0_MASK    (0x10000000U)
#define GENFSK_DUAL_PAN_CTRL_PANCORDNTR0_SHIFT   (28U)
/*! PANCORDNTR0 - Device is a PAN Coordinator on PAN0
 */
#define GENFSK_DUAL_PAN_CTRL_PANCORDNTR0(x)      (((uint32_t)(((uint32_t)(x)) << GENFSK_DUAL_PAN_CTRL_PANCORDNTR0_SHIFT)) & GENFSK_DUAL_PAN_CTRL_PANCORDNTR0_MASK)

#define GENFSK_DUAL_PAN_CTRL_PANCORDNTR1_MASK    (0x20000000U)
#define GENFSK_DUAL_PAN_CTRL_PANCORDNTR1_SHIFT   (29U)
/*! PANCORDNTR1 - Device is a PAN Coordinator on PAN1
 */
#define GENFSK_DUAL_PAN_CTRL_PANCORDNTR1(x)      (((uint32_t)(((uint32_t)(x)) << GENFSK_DUAL_PAN_CTRL_PANCORDNTR1_SHIFT)) & GENFSK_DUAL_PAN_CTRL_PANCORDNTR1_MASK)

#define GENFSK_DUAL_PAN_CTRL_RECD_ON_PAN0_MASK   (0x40000000U)
#define GENFSK_DUAL_PAN_CTRL_RECD_ON_PAN0_SHIFT  (30U)
/*! RECD_ON_PAN0 - Last Packet was Received on PAN0
 */
#define GENFSK_DUAL_PAN_CTRL_RECD_ON_PAN0(x)     (((uint32_t)(((uint32_t)(x)) << GENFSK_DUAL_PAN_CTRL_RECD_ON_PAN0_SHIFT)) & GENFSK_DUAL_PAN_CTRL_RECD_ON_PAN0_MASK)

#define GENFSK_DUAL_PAN_CTRL_RECD_ON_PAN1_MASK   (0x80000000U)
#define GENFSK_DUAL_PAN_CTRL_RECD_ON_PAN1_SHIFT  (31U)
/*! RECD_ON_PAN1 - Last Packet was Received on PAN1
 */
#define GENFSK_DUAL_PAN_CTRL_RECD_ON_PAN1(x)     (((uint32_t)(((uint32_t)(x)) << GENFSK_DUAL_PAN_CTRL_RECD_ON_PAN1_SHIFT)) & GENFSK_DUAL_PAN_CTRL_RECD_ON_PAN1_MASK)
/*! @} */

/*! @name GTM_PDU - GTM MODE PDU */
/*! @{ */

#define GENFSK_GTM_PDU_GTM_PDU_MASK              (0xFFFFFFFFU)
#define GENFSK_GTM_PDU_GTM_PDU_SHIFT             (0U)
/*! GTM_PDU - GTM MODE PDU
 */
#define GENFSK_GTM_PDU_GTM_PDU(x)                (((uint32_t)(((uint32_t)(x)) << GENFSK_GTM_PDU_GTM_PDU_SHIFT)) & GENFSK_GTM_PDU_GTM_PDU_MASK)
/*! @} */

/*! @name MACSHORTADDRS1 - MAC SHORT ADDRESS FOR PAN1 */
/*! @{ */

#define GENFSK_MACSHORTADDRS1_MACPANID1_MASK     (0xFFFFU)
#define GENFSK_MACSHORTADDRS1_MACPANID1_SHIFT    (0U)
/*! MACPANID1 - MAC PAN ID for PAN1
 */
#define GENFSK_MACSHORTADDRS1_MACPANID1(x)       (((uint32_t)(((uint32_t)(x)) << GENFSK_MACSHORTADDRS1_MACPANID1_SHIFT)) & GENFSK_MACSHORTADDRS1_MACPANID1_MASK)

#define GENFSK_MACSHORTADDRS1_MACSHORTADDRS1_MASK (0xFFFF0000U)
#define GENFSK_MACSHORTADDRS1_MACSHORTADDRS1_SHIFT (16U)
/*! MACSHORTADDRS1 - MAC SHORT ADDRESS for PAN1
 */
#define GENFSK_MACSHORTADDRS1_MACSHORTADDRS1(x)  (((uint32_t)(((uint32_t)(x)) << GENFSK_MACSHORTADDRS1_MACSHORTADDRS1_SHIFT)) & GENFSK_MACSHORTADDRS1_MACSHORTADDRS1_MASK)
/*! @} */

/*! @name WL_VALID_ENTRY1 - VALID ENTRY OF WHITE LIST 1 */
/*! @{ */

#define GENFSK_WL_VALID_ENTRY1_WL_VALID_ENTRY1_MASK (0xFFFFFFFFU)
#define GENFSK_WL_VALID_ENTRY1_WL_VALID_ENTRY1_SHIFT (0U)
#define GENFSK_WL_VALID_ENTRY1_WL_VALID_ENTRY1(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_WL_VALID_ENTRY1_WL_VALID_ENTRY1_SHIFT)) & GENFSK_WL_VALID_ENTRY1_WL_VALID_ENTRY1_MASK)
/*! @} */

/*! @name DIRECT_PEER_ADDR_LSB - DIRECT_PEER_ADDR[31:0] */
/*! @{ */

#define GENFSK_DIRECT_PEER_ADDR_LSB_DIRECT_PEER_ADDR_LSB_MASK (0xFFFFFFFFU)
#define GENFSK_DIRECT_PEER_ADDR_LSB_DIRECT_PEER_ADDR_LSB_SHIFT (0U)
#define GENFSK_DIRECT_PEER_ADDR_LSB_DIRECT_PEER_ADDR_LSB(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_DIRECT_PEER_ADDR_LSB_DIRECT_PEER_ADDR_LSB_SHIFT)) & GENFSK_DIRECT_PEER_ADDR_LSB_DIRECT_PEER_ADDR_LSB_MASK)
/*! @} */

/*! @name GTM_CFG - GTM MODE CONFIGURATION */
/*! @{ */

#define GENFSK_GTM_CFG_GTM_PKT_NUM_MASK          (0xFFFU)
#define GENFSK_GTM_CFG_GTM_PKT_NUM_SHIFT         (0U)
/*! GTM_PKT_NUM - GTM MODE PACKET NUMBER
 */
#define GENFSK_GTM_CFG_GTM_PKT_NUM(x)            (((uint32_t)(((uint32_t)(x)) << GENFSK_GTM_CFG_GTM_PKT_NUM_SHIFT)) & GENFSK_GTM_CFG_GTM_PKT_NUM_MASK)

#define GENFSK_GTM_CFG_GTM_PDU_TYPE_MASK         (0xF000000U)
#define GENFSK_GTM_CFG_GTM_PDU_TYPE_SHIFT        (24U)
/*! GTM_PDU_TYPE - GTM MODE PDU TYPE SELECTION
 *  0b0000..PRBS9 Sequence
 *  0b0001..Programmable 8-bit Pattern (from register GTM_PDU[7:0], reused from MACSHORTADDRS1[7:0])
 *  0b0010..PRBS-13 Sequence
 *  0b0011..PRBS-15 Sequence
 *  0b0100..Programmable 32-bit Pattern (from register GTM_PDU[31:0], reused from {MACSHORTADDRS1,MACPANID1})
 *  0b0101..Programmable packet from Packet RAM (in this case, PKT_LEN is ignored)
 */
#define GENFSK_GTM_CFG_GTM_PDU_TYPE(x)           (((uint32_t)(((uint32_t)(x)) << GENFSK_GTM_CFG_GTM_PDU_TYPE_SHIFT)) & GENFSK_GTM_CFG_GTM_PDU_TYPE_MASK)

#define GENFSK_GTM_CFG_GTM_IPD_CHECK_DIS_MASK    (0x40000000U)
#define GENFSK_GTM_CFG_GTM_IPD_CHECK_DIS_SHIFT   (30U)
/*! GTM_IPD_CHECK_DIS - GTM MODE INTER-PACKET DURATION CHECK DISABLE
 */
#define GENFSK_GTM_CFG_GTM_IPD_CHECK_DIS(x)      (((uint32_t)(((uint32_t)(x)) << GENFSK_GTM_CFG_GTM_IPD_CHECK_DIS_SHIFT)) & GENFSK_GTM_CFG_GTM_IPD_CHECK_DIS_MASK)

#define GENFSK_GTM_CFG_GTM_PKT_COUNT_CHECK_DIS_MASK (0x80000000U)
#define GENFSK_GTM_CFG_GTM_PKT_COUNT_CHECK_DIS_SHIFT (31U)
/*! GTM_PKT_COUNT_CHECK_DIS - GTM MODE PACKET NUMBER CHECK DISABLE
 */
#define GENFSK_GTM_CFG_GTM_PKT_COUNT_CHECK_DIS(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_GTM_CFG_GTM_PKT_COUNT_CHECK_DIS_SHIFT)) & GENFSK_GTM_CFG_GTM_PKT_COUNT_CHECK_DIS_MASK)
/*! @} */

/*! @name MACLONGADDRS1_LSB - MAC LONG ADDRESS 1 LSB */
/*! @{ */

#define GENFSK_MACLONGADDRS1_LSB_MACLONGADDRS1_LSB_MASK (0xFFFFFFFFU)
#define GENFSK_MACLONGADDRS1_LSB_MACLONGADDRS1_LSB_SHIFT (0U)
/*! MACLONGADDRS1_LSB - MAC LONG ADDRESS for PAN1 LSB
 */
#define GENFSK_MACLONGADDRS1_LSB_MACLONGADDRS1_LSB(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_MACLONGADDRS1_LSB_MACLONGADDRS1_LSB_SHIFT)) & GENFSK_MACLONGADDRS1_LSB_MACLONGADDRS1_LSB_MASK)
/*! @} */

/*! @name DIRECT_PEER_ADDR_MSB - DIRECT_PEER_ADDR[47:32] */
/*! @{ */

#define GENFSK_DIRECT_PEER_ADDR_MSB_DIRECT_PEER_ADDR_MSB_MASK (0xFFFFU)
#define GENFSK_DIRECT_PEER_ADDR_MSB_DIRECT_PEER_ADDR_MSB_SHIFT (0U)
#define GENFSK_DIRECT_PEER_ADDR_MSB_DIRECT_PEER_ADDR_MSB(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_DIRECT_PEER_ADDR_MSB_DIRECT_PEER_ADDR_MSB_SHIFT)) & GENFSK_DIRECT_PEER_ADDR_MSB_DIRECT_PEER_ADDR_MSB_MASK)

#define GENFSK_DIRECT_PEER_ADDR_MSB_DIRECT_PEER_ADDR_TYPE_MASK (0x80000000U)
#define GENFSK_DIRECT_PEER_ADDR_MSB_DIRECT_PEER_ADDR_TYPE_SHIFT (31U)
/*! DIRECT_PEER_ADDR_TYPE
 *  0b0..Direct peer device address type is public.
 *  0b1..Direct peer device address type is random.
 */
#define GENFSK_DIRECT_PEER_ADDR_MSB_DIRECT_PEER_ADDR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_DIRECT_PEER_ADDR_MSB_DIRECT_PEER_ADDR_TYPE_SHIFT)) & GENFSK_DIRECT_PEER_ADDR_MSB_DIRECT_PEER_ADDR_TYPE_MASK)
/*! @} */

/*! @name GTM_IPD - GTM MODE INTER-PACKET DURATION */
/*! @{ */

#define GENFSK_GTM_IPD_GTM_IPD_MASK              (0xFFFFFU)
#define GENFSK_GTM_IPD_GTM_IPD_SHIFT             (0U)
/*! GTM_IPD - GTM MODE INTER-PACKET DURATION
 */
#define GENFSK_GTM_IPD_GTM_IPD(x)                (((uint32_t)(((uint32_t)(x)) << GENFSK_GTM_IPD_GTM_IPD_SHIFT)) & GENFSK_GTM_IPD_GTM_IPD_MASK)
/*! @} */

/*! @name MACLONGADDRS1_MSB - MAC LONG ADDRESS 1 MSB */
/*! @{ */

#define GENFSK_MACLONGADDRS1_MSB_MACLONGADDRS1_MSB_MASK (0xFFFFFFFFU)
#define GENFSK_MACLONGADDRS1_MSB_MACLONGADDRS1_MSB_SHIFT (0U)
/*! MACLONGADDRS1_MSB - MAC LONG ADDRESS for PAN1 MSB
 */
#define GENFSK_MACLONGADDRS1_MSB_MACLONGADDRS1_MSB(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_MACLONGADDRS1_MSB_MACLONGADDRS1_MSB_SHIFT)) & GENFSK_MACLONGADDRS1_MSB_MACLONGADDRS1_MSB_MASK)
/*! @} */

/*! @name CHANNEL_NUM1 - CHANNEL NUMBER 1 */
/*! @{ */

#define GENFSK_CHANNEL_NUM1_CHANNEL_NUM1_MASK    (0x7FU)
#define GENFSK_CHANNEL_NUM1_CHANNEL_NUM1_SHIFT   (0U)
/*! CHANNEL_NUM1 - Channel Number for PAN1
 */
#define GENFSK_CHANNEL_NUM1_CHANNEL_NUM1(x)      (((uint32_t)(((uint32_t)(x)) << GENFSK_CHANNEL_NUM1_CHANNEL_NUM1_SHIFT)) & GENFSK_CHANNEL_NUM1_CHANNEL_NUM1_MASK)
/*! @} */

/*! @name MACSHORTADDRS0 - MAC SHORT ADDRESS 0 */
/*! @{ */

#define GENFSK_MACSHORTADDRS0_MACPANID0_MASK     (0xFFFFU)
#define GENFSK_MACSHORTADDRS0_MACPANID0_SHIFT    (0U)
/*! MACPANID0 - MAC PAN ID for PAN0
 */
#define GENFSK_MACSHORTADDRS0_MACPANID0(x)       (((uint32_t)(((uint32_t)(x)) << GENFSK_MACSHORTADDRS0_MACPANID0_SHIFT)) & GENFSK_MACSHORTADDRS0_MACPANID0_MASK)

#define GENFSK_MACSHORTADDRS0_MACSHORTADDRS0_MASK (0xFFFF0000U)
#define GENFSK_MACSHORTADDRS0_MACSHORTADDRS0_SHIFT (16U)
/*! MACSHORTADDRS0 - MAC SHORT ADDRESS FOR PAN0
 */
#define GENFSK_MACSHORTADDRS0_MACSHORTADDRS0(x)  (((uint32_t)(((uint32_t)(x)) << GENFSK_MACSHORTADDRS0_MACSHORTADDRS0_SHIFT)) & GENFSK_MACSHORTADDRS0_MACSHORTADDRS0_MASK)
/*! @} */

/*! @name WL_VALID_ENTRY0 - VALID ENTRY OF WHITE LIST 0 */
/*! @{ */

#define GENFSK_WL_VALID_ENTRY0_WL_VALID_ENTRY0_MASK (0xFFFFFFFFU)
#define GENFSK_WL_VALID_ENTRY0_WL_VALID_ENTRY0_SHIFT (0U)
#define GENFSK_WL_VALID_ENTRY0_WL_VALID_ENTRY0(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_WL_VALID_ENTRY0_WL_VALID_ENTRY0_SHIFT)) & GENFSK_WL_VALID_ENTRY0_WL_VALID_ENTRY0_MASK)
/*! @} */

/*! @name GTM_FIRST_SFD2WD - GTM MODE TIME OF FIRST SFD FOUND TO FORCE RX WARMDOWN */
/*! @{ */

#define GENFSK_GTM_FIRST_SFD2WD_GTM_FIRST_SFD2WD_MASK (0xFFFFFU)
#define GENFSK_GTM_FIRST_SFD2WD_GTM_FIRST_SFD2WD_SHIFT (0U)
/*! GTM_FIRST_SFD2WD - GTM MODE TIME OF FIRST SFD FOUND TO FORCE RX WARMDOWN
 */
#define GENFSK_GTM_FIRST_SFD2WD_GTM_FIRST_SFD2WD(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_GTM_FIRST_SFD2WD_GTM_FIRST_SFD2WD_SHIFT)) & GENFSK_GTM_FIRST_SFD2WD_GTM_FIRST_SFD2WD_MASK)
/*! @} */

/*! @name MACLONGADDRS0_LSB - MAC LONG ADDRESS 0 LSB */
/*! @{ */

#define GENFSK_MACLONGADDRS0_LSB_MACLONGADDRS0_LSB_MASK (0xFFFFFFFFU)
#define GENFSK_MACLONGADDRS0_LSB_MACLONGADDRS0_LSB_SHIFT (0U)
/*! MACLONGADDRS0_LSB - MAC LONG ADDRESS for PAN0 LSB
 */
#define GENFSK_MACLONGADDRS0_LSB_MACLONGADDRS0_LSB(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_MACLONGADDRS0_LSB_MACLONGADDRS0_LSB_SHIFT)) & GENFSK_MACLONGADDRS0_LSB_MACLONGADDRS0_LSB_MASK)
/*! @} */

/*! @name WL_SEARCH_ADDR_LSB - WL_SEARCH_ADDR[31:0] */
/*! @{ */

#define GENFSK_WL_SEARCH_ADDR_LSB_WL_SEARCH_ADDR_LSB_MASK (0xFFFFFFFFU)
#define GENFSK_WL_SEARCH_ADDR_LSB_WL_SEARCH_ADDR_LSB_SHIFT (0U)
#define GENFSK_WL_SEARCH_ADDR_LSB_WL_SEARCH_ADDR_LSB(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_WL_SEARCH_ADDR_LSB_WL_SEARCH_ADDR_LSB_SHIFT)) & GENFSK_WL_SEARCH_ADDR_LSB_WL_SEARCH_ADDR_LSB_MASK)
/*! @} */

/*! @name GTM_RX_RECYCLE_TIME - GTM MODE RX RECYCLE TIME */
/*! @{ */

#define GENFSK_GTM_RX_RECYCLE_TIME_GTM_RX_RECYCLE_TIME_MASK (0xFFFFFU)
#define GENFSK_GTM_RX_RECYCLE_TIME_GTM_RX_RECYCLE_TIME_SHIFT (0U)
/*! GTM_RX_RECYCLE_TIME - GTM MODE RX RECYCLE TIME
 */
#define GENFSK_GTM_RX_RECYCLE_TIME_GTM_RX_RECYCLE_TIME(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_GTM_RX_RECYCLE_TIME_GTM_RX_RECYCLE_TIME_SHIFT)) & GENFSK_GTM_RX_RECYCLE_TIME_GTM_RX_RECYCLE_TIME_MASK)
/*! @} */

/*! @name MACLONGADDRS0_MSB - MAC LONG ADDRESS 0 MSB */
/*! @{ */

#define GENFSK_MACLONGADDRS0_MSB_MACLONGADDRS0_MSB_MASK (0xFFFFFFFFU)
#define GENFSK_MACLONGADDRS0_MSB_MACLONGADDRS0_MSB_SHIFT (0U)
/*! MACLONGADDRS0_MSB - MAC LONG ADDRESS for PAN0 MSB
 */
#define GENFSK_MACLONGADDRS0_MSB_MACLONGADDRS0_MSB(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_MACLONGADDRS0_MSB_MACLONGADDRS0_MSB_SHIFT)) & GENFSK_MACLONGADDRS0_MSB_MACLONGADDRS0_MSB_MASK)
/*! @} */

/*! @name WL_SEARCH_ADDR_MSB - WL_SEARCH_ADDR[47:32] */
/*! @{ */

#define GENFSK_WL_SEARCH_ADDR_MSB_WL_SEARCH_ADDR_MSB_MASK (0xFFFFU)
#define GENFSK_WL_SEARCH_ADDR_MSB_WL_SEARCH_ADDR_MSB_SHIFT (0U)
#define GENFSK_WL_SEARCH_ADDR_MSB_WL_SEARCH_ADDR_MSB(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_WL_SEARCH_ADDR_MSB_WL_SEARCH_ADDR_MSB_SHIFT)) & GENFSK_WL_SEARCH_ADDR_MSB_WL_SEARCH_ADDR_MSB_MASK)

#define GENFSK_WL_SEARCH_ADDR_MSB_WL_SEARCH_ADDR_TYPE_MASK (0x80000000U)
#define GENFSK_WL_SEARCH_ADDR_MSB_WL_SEARCH_ADDR_TYPE_SHIFT (31U)
/*! WL_SEARCH_ADDR_TYPE
 *  0b0..The address type is public.
 *  0b1..The address type is random.
 */
#define GENFSK_WL_SEARCH_ADDR_MSB_WL_SEARCH_ADDR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_WL_SEARCH_ADDR_MSB_WL_SEARCH_ADDR_TYPE_SHIFT)) & GENFSK_WL_SEARCH_ADDR_MSB_WL_SEARCH_ADDR_TYPE_MASK)
/*! @} */

/*! @name CCA_LQI_CTRL - CCA AND LQI CONTROL */
/*! @{ */

#define GENFSK_CCA_LQI_CTRL_CCABFRTX_MASK        (0x1U)
#define GENFSK_CCA_LQI_CTRL_CCABFRTX_SHIFT       (0U)
/*! CCABFRTX - CCA Before TX
 *  0b0..no CCA required, transmit operation begins immediately.
 *  0b1..at least one CCA measurement is required prior to the transmit operation (see also SLOTTED).
 */
#define GENFSK_CCA_LQI_CTRL_CCABFRTX(x)          (((uint32_t)(((uint32_t)(x)) << GENFSK_CCA_LQI_CTRL_CCABFRTX_SHIFT)) & GENFSK_CCA_LQI_CTRL_CCABFRTX_MASK)

#define GENFSK_CCA_LQI_CTRL_SIMUL_CCA_RX_MASK    (0x2U)
#define GENFSK_CCA_LQI_CTRL_SIMUL_CCA_RX_SHIFT   (1U)
/*! SIMUL_CCA_RX - Simultaneous CCA and Receive Enable
 *  0b0..Packets can't be received during CCA measurement
 *  0b1..Packet reception is enabled during CCA measurement if preamble and SFD are detected
 */
#define GENFSK_CCA_LQI_CTRL_SIMUL_CCA_RX(x)      (((uint32_t)(((uint32_t)(x)) << GENFSK_CCA_LQI_CTRL_SIMUL_CCA_RX_SHIFT)) & GENFSK_CCA_LQI_CTRL_SIMUL_CCA_RX_MASK)

#define GENFSK_CCA_LQI_CTRL_CCA_MASK             (0x80U)
#define GENFSK_CCA_LQI_CTRL_CCA_SHIFT            (7U)
/*! CCA - CCA Status
 *  0b0..IDLE
 *  0b1..BUSY
 */
#define GENFSK_CCA_LQI_CTRL_CCA(x)               (((uint32_t)(((uint32_t)(x)) << GENFSK_CCA_LQI_CTRL_CCA_SHIFT)) & GENFSK_CCA_LQI_CTRL_CCA_MASK)

#define GENFSK_CCA_LQI_CTRL_CCA1_THRESH_MASK     (0xFF00U)
#define GENFSK_CCA_LQI_CTRL_CCA1_THRESH_SHIFT    (8U)
/*! CCA1_THRESH - CCA Mode 1 Threshold
 */
#define GENFSK_CCA_LQI_CTRL_CCA1_THRESH(x)       (((uint32_t)(((uint32_t)(x)) << GENFSK_CCA_LQI_CTRL_CCA1_THRESH_SHIFT)) & GENFSK_CCA_LQI_CTRL_CCA1_THRESH_MASK)

#define GENFSK_CCA_LQI_CTRL_CCA1_ED_FNL_MASK     (0xFF0000U)
#define GENFSK_CCA_LQI_CTRL_CCA1_ED_FNL_SHIFT    (16U)
/*! CCA1_ED_FNL - Final Result for CCA Mode 1 and Energy Detect
 */
#define GENFSK_CCA_LQI_CTRL_CCA1_ED_FNL(x)       (((uint32_t)(((uint32_t)(x)) << GENFSK_CCA_LQI_CTRL_CCA1_ED_FNL_SHIFT)) & GENFSK_CCA_LQI_CTRL_CCA1_ED_FNL_MASK)
/*! @} */

/*! @name WARMUP_TIME - TX/RX WARMUP TIME */
/*! @{ */

#define GENFSK_WARMUP_TIME_RX_WARMUP_MASK        (0xFFU)
#define GENFSK_WARMUP_TIME_RX_WARMUP_SHIFT       (0U)
/*! RX_WARMUP - Receive Warmup Time
 */
#define GENFSK_WARMUP_TIME_RX_WARMUP(x)          (((uint32_t)(((uint32_t)(x)) << GENFSK_WARMUP_TIME_RX_WARMUP_SHIFT)) & GENFSK_WARMUP_TIME_RX_WARMUP_MASK)

#define GENFSK_WARMUP_TIME_TX_WARMUP_MASK        (0xFF0000U)
#define GENFSK_WARMUP_TIME_TX_WARMUP_SHIFT       (16U)
/*! TX_WARMUP - Transmit Warmup Time
 */
#define GENFSK_WARMUP_TIME_TX_WARMUP(x)          (((uint32_t)(((uint32_t)(x)) << GENFSK_WARMUP_TIME_TX_WARMUP_SHIFT)) & GENFSK_WARMUP_TIME_TX_WARMUP_MASK)
/*! @} */

/*! @name RXEN_DLY - RX_EN Delay Time */
/*! @{ */

#define GENFSK_RXEN_DLY_RXEN_DLY_MASK            (0x3FFU)
#define GENFSK_RXEN_DLY_RXEN_DLY_SHIFT           (0U)
#define GENFSK_RXEN_DLY_RXEN_DLY(x)              (((uint32_t)(((uint32_t)(x)) << GENFSK_RXEN_DLY_RXEN_DLY_SHIFT)) & GENFSK_RXEN_DLY_RXEN_DLY_MASK)

#define GENFSK_RXEN_DLY_RXEN_DLY_OVERRIDE_MASK   (0x80000000U)
#define GENFSK_RXEN_DLY_RXEN_DLY_OVERRIDE_SHIFT  (31U)
/*! RXEN_DLY_OVERRIDE
 *  0b0..For Bluetooth LE case, RX_EN signal will delay to de-assert accroding to the length of TERM2 or CTE(when
 *       BLE_V5P1_CTE_EN is enabled) field parsed by hardware
 *  0b1..For all receive case, RX_EN signal will delay to de-assert accroding to register RXEN_DLY[9:0].
 */
#define GENFSK_RXEN_DLY_RXEN_DLY_OVERRIDE(x)     (((uint32_t)(((uint32_t)(x)) << GENFSK_RXEN_DLY_RXEN_DLY_OVERRIDE_SHIFT)) & GENFSK_RXEN_DLY_RXEN_DLY_OVERRIDE_MASK)
/*! @} */

/*! @name SAM_CTRL - SAM CONTROL */
/*! @{ */

#define GENFSK_SAM_CTRL_SAP0_EN_MASK             (0x1U)
#define GENFSK_SAM_CTRL_SAP0_EN_SHIFT            (0U)
/*! SAP0_EN - Enables SAP0 Partition of the SAM Table
 *  0b0..Disables SAP0 Partition
 *  0b1..Enables SAP0 Partition
 */
#define GENFSK_SAM_CTRL_SAP0_EN(x)               (((uint32_t)(((uint32_t)(x)) << GENFSK_SAM_CTRL_SAP0_EN_SHIFT)) & GENFSK_SAM_CTRL_SAP0_EN_MASK)

#define GENFSK_SAM_CTRL_SAA0_EN_MASK             (0x2U)
#define GENFSK_SAM_CTRL_SAA0_EN_SHIFT            (1U)
/*! SAA0_EN - Enables SAA0 Partition of the SAM Table
 *  0b0..Disables SAA0 Partition
 *  0b1..Enables SAA0 Partition
 */
#define GENFSK_SAM_CTRL_SAA0_EN(x)               (((uint32_t)(((uint32_t)(x)) << GENFSK_SAM_CTRL_SAA0_EN_SHIFT)) & GENFSK_SAM_CTRL_SAA0_EN_MASK)

#define GENFSK_SAM_CTRL_SAP1_EN_MASK             (0x4U)
#define GENFSK_SAM_CTRL_SAP1_EN_SHIFT            (2U)
/*! SAP1_EN - Enables SAP1 Partition of the SAM Table
 *  0b0..Disables SAP1 Partition
 *  0b1..Enables SAP1 Partition
 */
#define GENFSK_SAM_CTRL_SAP1_EN(x)               (((uint32_t)(((uint32_t)(x)) << GENFSK_SAM_CTRL_SAP1_EN_SHIFT)) & GENFSK_SAM_CTRL_SAP1_EN_MASK)

#define GENFSK_SAM_CTRL_SAA1_EN_MASK             (0x8U)
#define GENFSK_SAM_CTRL_SAA1_EN_SHIFT            (3U)
/*! SAA1_EN - Enables SAA1 Partition of the SAM Table
 *  0b0..Disables SAA1 Partition
 *  0b1..Enables SAA1 Partition
 */
#define GENFSK_SAM_CTRL_SAA1_EN(x)               (((uint32_t)(((uint32_t)(x)) << GENFSK_SAM_CTRL_SAA1_EN_SHIFT)) & GENFSK_SAM_CTRL_SAA1_EN_MASK)

#define GENFSK_SAM_CTRL_SAA0_START_MASK          (0xFF00U)
#define GENFSK_SAM_CTRL_SAA0_START_SHIFT         (8U)
/*! SAA0_START - First Index of SAA0 partition
 */
#define GENFSK_SAM_CTRL_SAA0_START(x)            (((uint32_t)(((uint32_t)(x)) << GENFSK_SAM_CTRL_SAA0_START_SHIFT)) & GENFSK_SAM_CTRL_SAA0_START_MASK)

#define GENFSK_SAM_CTRL_SAP1_START_MASK          (0xFF0000U)
#define GENFSK_SAM_CTRL_SAP1_START_SHIFT         (16U)
/*! SAP1_START - First Index of SAP1 partition
 */
#define GENFSK_SAM_CTRL_SAP1_START(x)            (((uint32_t)(((uint32_t)(x)) << GENFSK_SAM_CTRL_SAP1_START_SHIFT)) & GENFSK_SAM_CTRL_SAP1_START_MASK)

#define GENFSK_SAM_CTRL_SAA1_START_MASK          (0xFF000000U)
#define GENFSK_SAM_CTRL_SAA1_START_SHIFT         (24U)
/*! SAA1_START - First Index of SAA1 partition
 */
#define GENFSK_SAM_CTRL_SAA1_START(x)            (((uint32_t)(((uint32_t)(x)) << GENFSK_SAM_CTRL_SAA1_START_SHIFT)) & GENFSK_SAM_CTRL_SAA1_START_MASK)
/*! @} */

/*! @name SAM_TABLE - SOURCE ADDRESS MANAGEMENT TABLE */
/*! @{ */

#define GENFSK_SAM_TABLE_SAM_INDEX_MASK          (0x7FU)
#define GENFSK_SAM_TABLE_SAM_INDEX_SHIFT         (0U)
/*! SAM_INDEX - Contains the SAM table index to be enabled or invalidated
 */
#define GENFSK_SAM_TABLE_SAM_INDEX(x)            (((uint32_t)(((uint32_t)(x)) << GENFSK_SAM_TABLE_SAM_INDEX_SHIFT)) & GENFSK_SAM_TABLE_SAM_INDEX_MASK)

#define GENFSK_SAM_TABLE_SAM_INDEX_WR_MASK       (0x80U)
#define GENFSK_SAM_TABLE_SAM_INDEX_WR_SHIFT      (7U)
/*! SAM_INDEX_WR - Enables SAM Table Contents to be updated
 */
#define GENFSK_SAM_TABLE_SAM_INDEX_WR(x)         (((uint32_t)(((uint32_t)(x)) << GENFSK_SAM_TABLE_SAM_INDEX_WR_SHIFT)) & GENFSK_SAM_TABLE_SAM_INDEX_WR_MASK)

#define GENFSK_SAM_TABLE_SAM_CHECKSUM_MASK       (0xFFFF00U)
#define GENFSK_SAM_TABLE_SAM_CHECKSUM_SHIFT      (8U)
/*! SAM_CHECKSUM - Software-computed source address checksum, to be installed into a table index
 */
#define GENFSK_SAM_TABLE_SAM_CHECKSUM(x)         (((uint32_t)(((uint32_t)(x)) << GENFSK_SAM_TABLE_SAM_CHECKSUM_SHIFT)) & GENFSK_SAM_TABLE_SAM_CHECKSUM_MASK)

#define GENFSK_SAM_TABLE_SAM_INDEX_INV_MASK      (0x1000000U)
#define GENFSK_SAM_TABLE_SAM_INDEX_INV_SHIFT     (24U)
/*! SAM_INDEX_INV - Invalidate the SAM table index selected by SAM_INDEX
 */
#define GENFSK_SAM_TABLE_SAM_INDEX_INV(x)        (((uint32_t)(((uint32_t)(x)) << GENFSK_SAM_TABLE_SAM_INDEX_INV_SHIFT)) & GENFSK_SAM_TABLE_SAM_INDEX_INV_MASK)

#define GENFSK_SAM_TABLE_SAM_INDEX_EN_MASK       (0x2000000U)
#define GENFSK_SAM_TABLE_SAM_INDEX_EN_SHIFT      (25U)
/*! SAM_INDEX_EN - Enable the SAM table index selected by SAM_INDEX
 */
#define GENFSK_SAM_TABLE_SAM_INDEX_EN(x)         (((uint32_t)(((uint32_t)(x)) << GENFSK_SAM_TABLE_SAM_INDEX_EN_SHIFT)) & GENFSK_SAM_TABLE_SAM_INDEX_EN_MASK)

#define GENFSK_SAM_TABLE_ACK_FRM_PND_MASK        (0x4000000U)
#define GENFSK_SAM_TABLE_ACK_FRM_PND_SHIFT       (26U)
/*! ACK_FRM_PND - State of AutoTxAck FramePending field when SAM Accelleration is Disabled
 */
#define GENFSK_SAM_TABLE_ACK_FRM_PND(x)          (((uint32_t)(((uint32_t)(x)) << GENFSK_SAM_TABLE_ACK_FRM_PND_SHIFT)) & GENFSK_SAM_TABLE_ACK_FRM_PND_MASK)

#define GENFSK_SAM_TABLE_ACK_FRM_PND_CTRL_MASK   (0x8000000U)
#define GENFSK_SAM_TABLE_ACK_FRM_PND_CTRL_SHIFT  (27U)
/*! ACK_FRM_PND_CTRL - Manual Control for AutoTxAck FramePending field
 *  0b0..the FramePending field of the Frame Control Field of the next automatic TX acknowledge packet is determined by hardware
 *  0b1..the FramePending field of the Frame Control Field of the next automatic TX acknowledge packet tracks ACK_FRM_PEND
 */
#define GENFSK_SAM_TABLE_ACK_FRM_PND_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << GENFSK_SAM_TABLE_ACK_FRM_PND_CTRL_SHIFT)) & GENFSK_SAM_TABLE_ACK_FRM_PND_CTRL_MASK)

#define GENFSK_SAM_TABLE_FIND_FREE_IDX_MASK      (0x10000000U)
#define GENFSK_SAM_TABLE_FIND_FREE_IDX_SHIFT     (28U)
/*! FIND_FREE_IDX - Find First Free Index
 */
#define GENFSK_SAM_TABLE_FIND_FREE_IDX(x)        (((uint32_t)(((uint32_t)(x)) << GENFSK_SAM_TABLE_FIND_FREE_IDX_SHIFT)) & GENFSK_SAM_TABLE_FIND_FREE_IDX_MASK)

#define GENFSK_SAM_TABLE_INVALIDATE_ALL_MASK     (0x20000000U)
#define GENFSK_SAM_TABLE_INVALIDATE_ALL_SHIFT    (29U)
/*! INVALIDATE_ALL - Invalidate Entire SAM Table
 */
#define GENFSK_SAM_TABLE_INVALIDATE_ALL(x)       (((uint32_t)(((uint32_t)(x)) << GENFSK_SAM_TABLE_INVALIDATE_ALL_SHIFT)) & GENFSK_SAM_TABLE_INVALIDATE_ALL_MASK)

#define GENFSK_SAM_TABLE_SRCADDR_MASK            (0x40000000U)
#define GENFSK_SAM_TABLE_SRCADDR_SHIFT           (30U)
/*! SRCADDR - Source Address Match Status
 */
#define GENFSK_SAM_TABLE_SRCADDR(x)              (((uint32_t)(((uint32_t)(x)) << GENFSK_SAM_TABLE_SRCADDR_SHIFT)) & GENFSK_SAM_TABLE_SRCADDR_MASK)

#define GENFSK_SAM_TABLE_SAM_BUSY_MASK           (0x80000000U)
#define GENFSK_SAM_TABLE_SAM_BUSY_SHIFT          (31U)
/*! SAM_BUSY - SAM Table Update Status Bit
 */
#define GENFSK_SAM_TABLE_SAM_BUSY(x)             (((uint32_t)(((uint32_t)(x)) << GENFSK_SAM_TABLE_SAM_BUSY_SHIFT)) & GENFSK_SAM_TABLE_SAM_BUSY_MASK)
/*! @} */

/*! @name SAM_MATCH - SOURCE ADDRESS MANAGEMENT MATCH */
/*! @{ */

#define GENFSK_SAM_MATCH_SAP0_MATCH_MASK         (0x7FU)
#define GENFSK_SAM_MATCH_SAP0_MATCH_SHIFT        (0U)
/*! SAP0_MATCH - Index in the SAP0 Partition of the SAM Table corresponding to the first checksum match
 */
#define GENFSK_SAM_MATCH_SAP0_MATCH(x)           (((uint32_t)(((uint32_t)(x)) << GENFSK_SAM_MATCH_SAP0_MATCH_SHIFT)) & GENFSK_SAM_MATCH_SAP0_MATCH_MASK)

#define GENFSK_SAM_MATCH_SAP0_ADDR_PRESENT_MASK  (0x80U)
#define GENFSK_SAM_MATCH_SAP0_ADDR_PRESENT_SHIFT (7U)
/*! SAP0_ADDR_PRESENT - A Checksum Match is Present in the SAP0 Partition of the SAM Table
 */
#define GENFSK_SAM_MATCH_SAP0_ADDR_PRESENT(x)    (((uint32_t)(((uint32_t)(x)) << GENFSK_SAM_MATCH_SAP0_ADDR_PRESENT_SHIFT)) & GENFSK_SAM_MATCH_SAP0_ADDR_PRESENT_MASK)

#define GENFSK_SAM_MATCH_SAA0_MATCH_MASK         (0x7F00U)
#define GENFSK_SAM_MATCH_SAA0_MATCH_SHIFT        (8U)
/*! SAA0_MATCH - Index in the SAA0 Partition of the SAM Table corresponding to the first checksum match
 */
#define GENFSK_SAM_MATCH_SAA0_MATCH(x)           (((uint32_t)(((uint32_t)(x)) << GENFSK_SAM_MATCH_SAA0_MATCH_SHIFT)) & GENFSK_SAM_MATCH_SAA0_MATCH_MASK)

#define GENFSK_SAM_MATCH_SAA0_ADDR_ABSENT_MASK   (0x8000U)
#define GENFSK_SAM_MATCH_SAA0_ADDR_ABSENT_SHIFT  (15U)
/*! SAA0_ADDR_ABSENT - A Checksum Match is Absent in the SAA0 Partition of the SAM Table
 */
#define GENFSK_SAM_MATCH_SAA0_ADDR_ABSENT(x)     (((uint32_t)(((uint32_t)(x)) << GENFSK_SAM_MATCH_SAA0_ADDR_ABSENT_SHIFT)) & GENFSK_SAM_MATCH_SAA0_ADDR_ABSENT_MASK)

#define GENFSK_SAM_MATCH_SAP1_MATCH_MASK         (0x7F0000U)
#define GENFSK_SAM_MATCH_SAP1_MATCH_SHIFT        (16U)
/*! SAP1_MATCH - Index in the SAP1 Partition of the SAM Table corresponding to the first checksum match
 */
#define GENFSK_SAM_MATCH_SAP1_MATCH(x)           (((uint32_t)(((uint32_t)(x)) << GENFSK_SAM_MATCH_SAP1_MATCH_SHIFT)) & GENFSK_SAM_MATCH_SAP1_MATCH_MASK)

#define GENFSK_SAM_MATCH_SAP1_ADDR_PRESENT_MASK  (0x800000U)
#define GENFSK_SAM_MATCH_SAP1_ADDR_PRESENT_SHIFT (23U)
/*! SAP1_ADDR_PRESENT - A Checksum Match is Present in the SAP1 Partition of the SAM Table
 */
#define GENFSK_SAM_MATCH_SAP1_ADDR_PRESENT(x)    (((uint32_t)(((uint32_t)(x)) << GENFSK_SAM_MATCH_SAP1_ADDR_PRESENT_SHIFT)) & GENFSK_SAM_MATCH_SAP1_ADDR_PRESENT_MASK)

#define GENFSK_SAM_MATCH_SAA1_MATCH_MASK         (0x7F000000U)
#define GENFSK_SAM_MATCH_SAA1_MATCH_SHIFT        (24U)
/*! SAA1_MATCH - Index in the SAA1 Partition of the SAM Table corresponding to the first checksum match
 */
#define GENFSK_SAM_MATCH_SAA1_MATCH(x)           (((uint32_t)(((uint32_t)(x)) << GENFSK_SAM_MATCH_SAA1_MATCH_SHIFT)) & GENFSK_SAM_MATCH_SAA1_MATCH_MASK)

#define GENFSK_SAM_MATCH_SAA1_ADDR_ABSENT_MASK   (0x80000000U)
#define GENFSK_SAM_MATCH_SAA1_ADDR_ABSENT_SHIFT  (31U)
/*! SAA1_ADDR_ABSENT - A Checksum Match is Absent in the SAP1 Partition of the SAM Table
 */
#define GENFSK_SAM_MATCH_SAA1_ADDR_ABSENT(x)     (((uint32_t)(((uint32_t)(x)) << GENFSK_SAM_MATCH_SAA1_ADDR_ABSENT_SHIFT)) & GENFSK_SAM_MATCH_SAA1_ADDR_ABSENT_MASK)
/*! @} */

/*! @name SAM_FREE_IDX - SAM FREE INDEX */
/*! @{ */

#define GENFSK_SAM_FREE_IDX_SAP0_1ST_FREE_IDX_MASK (0xFFU)
#define GENFSK_SAM_FREE_IDX_SAP0_1ST_FREE_IDX_SHIFT (0U)
/*! SAP0_1ST_FREE_IDX - First non-enabled (invalid) index in the SAP0 partition
 */
#define GENFSK_SAM_FREE_IDX_SAP0_1ST_FREE_IDX(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_SAM_FREE_IDX_SAP0_1ST_FREE_IDX_SHIFT)) & GENFSK_SAM_FREE_IDX_SAP0_1ST_FREE_IDX_MASK)

#define GENFSK_SAM_FREE_IDX_SAA0_1ST_FREE_IDX_MASK (0xFF00U)
#define GENFSK_SAM_FREE_IDX_SAA0_1ST_FREE_IDX_SHIFT (8U)
/*! SAA0_1ST_FREE_IDX - First non-enabled (invalid) index in the SAA0 partition
 */
#define GENFSK_SAM_FREE_IDX_SAA0_1ST_FREE_IDX(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_SAM_FREE_IDX_SAA0_1ST_FREE_IDX_SHIFT)) & GENFSK_SAM_FREE_IDX_SAA0_1ST_FREE_IDX_MASK)

#define GENFSK_SAM_FREE_IDX_SAP1_1ST_FREE_IDX_MASK (0xFF0000U)
#define GENFSK_SAM_FREE_IDX_SAP1_1ST_FREE_IDX_SHIFT (16U)
/*! SAP1_1ST_FREE_IDX - First non-enabled (invalid) index in the SAP1 partition
 */
#define GENFSK_SAM_FREE_IDX_SAP1_1ST_FREE_IDX(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_SAM_FREE_IDX_SAP1_1ST_FREE_IDX_SHIFT)) & GENFSK_SAM_FREE_IDX_SAP1_1ST_FREE_IDX_MASK)

#define GENFSK_SAM_FREE_IDX_SAA1_1ST_FREE_IDX_MASK (0xFF000000U)
#define GENFSK_SAM_FREE_IDX_SAA1_1ST_FREE_IDX_SHIFT (24U)
/*! SAA1_1ST_FREE_IDX - First non-enabled (invalid) index in the SAA1 partition
 */
#define GENFSK_SAM_FREE_IDX_SAA1_1ST_FREE_IDX(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_SAM_FREE_IDX_SAA1_1ST_FREE_IDX_SHIFT)) & GENFSK_SAM_FREE_IDX_SAA1_1ST_FREE_IDX_MASK)
/*! @} */

/*! @name MISC1 - MISCELLANEOUS(1) */
/*! @{ */

#define GENFSK_MISC1_SRC_ADDR_CHECKSUM_MASK      (0xFFFFU)
#define GENFSK_MISC1_SRC_ADDR_CHECKSUM_SHIFT     (0U)
/*! SRC_ADDR_CHECKSUM - Hardware-computed received source address checksum
 */
#define GENFSK_MISC1_SRC_ADDR_CHECKSUM(x)        (((uint32_t)(((uint32_t)(x)) << GENFSK_MISC1_SRC_ADDR_CHECKSUM_SHIFT)) & GENFSK_MISC1_SRC_ADDR_CHECKSUM_MASK)

#define GENFSK_MISC1_SW_ABORTED_MASK             (0x10000U)
#define GENFSK_MISC1_SW_ABORTED_SHIFT            (16U)
/*! SW_ABORTED - Autosequence has terminated due to a Software abort.
 */
#define GENFSK_MISC1_SW_ABORTED(x)               (((uint32_t)(((uint32_t)(x)) << GENFSK_MISC1_SW_ABORTED_SHIFT)) & GENFSK_MISC1_SW_ABORTED_MASK)

#define GENFSK_MISC1_PLL_ABORTED_MASK            (0x20000U)
#define GENFSK_MISC1_PLL_ABORTED_SHIFT           (17U)
/*! PLL_ABORTED - Autosequence has terminated due to an PLL unlock event.
 */
#define GENFSK_MISC1_PLL_ABORTED(x)              (((uint32_t)(((uint32_t)(x)) << GENFSK_MISC1_PLL_ABORTED_SHIFT)) & GENFSK_MISC1_PLL_ABORTED_MASK)

#define GENFSK_MISC1_EXT_ABORTED_MASK            (0x40000U)
#define GENFSK_MISC1_EXT_ABORTED_SHIFT           (18U)
/*! EXT_ABORTED - Autosequence has terminated due to a Wake-On-Radio command
 */
#define GENFSK_MISC1_EXT_ABORTED(x)              (((uint32_t)(((uint32_t)(x)) << GENFSK_MISC1_EXT_ABORTED_SHIFT)) & GENFSK_MISC1_EXT_ABORTED_MASK)

#define GENFSK_MISC1_ARB_GRANT_DEASSERTION_ABORTED_MASK (0x80000U)
#define GENFSK_MISC1_ARB_GRANT_DEASSERTION_ABORTED_SHIFT (19U)
/*! ARB_GRANT_DEASSERTION_ABORTED - Autosequence has terminated due to an arb_grant deassertion event
 */
#define GENFSK_MISC1_ARB_GRANT_DEASSERTION_ABORTED(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_MISC1_ARB_GRANT_DEASSERTION_ABORTED_SHIFT)) & GENFSK_MISC1_ARB_GRANT_DEASSERTION_ABORTED_MASK)

#define GENFSK_MISC1_FAST_TX_WU_OVRD_MASK        (0x10000000U)
#define GENFSK_MISC1_FAST_TX_WU_OVRD_SHIFT       (28U)
/*! FAST_TX_WU_OVRD - FAST_TX_WU override
 *  0b0..If TSM enables Fast Warmup Capability, LL will request it when TX in RT or (CCA+TX)
 *  0b1..If TSM enables Fast Warmup Capability, LL will request it at every TX. User should insure channel is not changed since last sequence.
 */
#define GENFSK_MISC1_FAST_TX_WU_OVRD(x)          (((uint32_t)(((uint32_t)(x)) << GENFSK_MISC1_FAST_TX_WU_OVRD_SHIFT)) & GENFSK_MISC1_FAST_TX_WU_OVRD_MASK)

#define GENFSK_MISC1_FAST_RX_WU_OVRD_MASK        (0x20000000U)
#define GENFSK_MISC1_FAST_RX_WU_OVRD_SHIFT       (29U)
/*! FAST_RX_WU_OVRD - FAST_RX_WU override
 *  0b0..If TSM enables Fast Warmup Capability, LL will request it when RX in TR
 *  0b1..If TSM enables Fast Warmup Capability, LL will request it at every RX. User should insure channel is not changed since last sequence.
 */
#define GENFSK_MISC1_FAST_RX_WU_OVRD(x)          (((uint32_t)(((uint32_t)(x)) << GENFSK_MISC1_FAST_RX_WU_OVRD_SHIFT)) & GENFSK_MISC1_FAST_RX_WU_OVRD_MASK)

#define GENFSK_MISC1_PI_MASK                     (0x40000000U)
#define GENFSK_MISC1_PI_SHIFT                    (30U)
/*! PI - Poll Indication
 *  0b0..the received packet was not a data request
 *  0b1..the received packet was a data request, regardless of whether a Source Address table match occurred, or
 *       whether Source Address Management is enabled or not
 */
#define GENFSK_MISC1_PI(x)                       (((uint32_t)(((uint32_t)(x)) << GENFSK_MISC1_PI_SHIFT)) & GENFSK_MISC1_PI_MASK)

#define GENFSK_MISC1_RX_FRM_PEND_MASK            (0x80000000U)
#define GENFSK_MISC1_RX_FRM_PEND_SHIFT           (31U)
/*! RX_FRM_PEND - RX Frame Pending
 */
#define GENFSK_MISC1_RX_FRM_PEND(x)              (((uint32_t)(((uint32_t)(x)) << GENFSK_MISC1_RX_FRM_PEND_SHIFT)) & GENFSK_MISC1_RX_FRM_PEND_MASK)
/*! @} */

/*! @name SEQ_STS - SEQUENCE STATUS */
/*! @{ */

#define GENFSK_SEQ_STS_TX_START_T1_PEND_MASK     (0x1U)
#define GENFSK_SEQ_STS_TX_START_T1_PEND_SHIFT    (0U)
/*! TX_START_T1_PEND - TX T1 Start Pending Status
 */
#define GENFSK_SEQ_STS_TX_START_T1_PEND(x)       (((uint32_t)(((uint32_t)(x)) << GENFSK_SEQ_STS_TX_START_T1_PEND_SHIFT)) & GENFSK_SEQ_STS_TX_START_T1_PEND_MASK)

#define GENFSK_SEQ_STS_TX_START_T2_PEND_MASK     (0x2U)
#define GENFSK_SEQ_STS_TX_START_T2_PEND_SHIFT    (1U)
/*! TX_START_T2_PEND - TX T2 Start Pending Status
 */
#define GENFSK_SEQ_STS_TX_START_T2_PEND(x)       (((uint32_t)(((uint32_t)(x)) << GENFSK_SEQ_STS_TX_START_T2_PEND_SHIFT)) & GENFSK_SEQ_STS_TX_START_T2_PEND_MASK)

#define GENFSK_SEQ_STS_TX_IN_WARMUP_MASK         (0x4U)
#define GENFSK_SEQ_STS_TX_IN_WARMUP_SHIFT        (2U)
/*! TX_IN_WARMUP - TX Warmup Status
 */
#define GENFSK_SEQ_STS_TX_IN_WARMUP(x)           (((uint32_t)(((uint32_t)(x)) << GENFSK_SEQ_STS_TX_IN_WARMUP_SHIFT)) & GENFSK_SEQ_STS_TX_IN_WARMUP_MASK)

#define GENFSK_SEQ_STS_TX_IN_PROGRESS_MASK       (0x8U)
#define GENFSK_SEQ_STS_TX_IN_PROGRESS_SHIFT      (3U)
/*! TX_IN_PROGRESS - TX in Progress Status
 */
#define GENFSK_SEQ_STS_TX_IN_PROGRESS(x)         (((uint32_t)(((uint32_t)(x)) << GENFSK_SEQ_STS_TX_IN_PROGRESS_SHIFT)) & GENFSK_SEQ_STS_TX_IN_PROGRESS_MASK)

#define GENFSK_SEQ_STS_TX_IN_WARMDN_MASK         (0x10U)
#define GENFSK_SEQ_STS_TX_IN_WARMDN_SHIFT        (4U)
/*! TX_IN_WARMDN - TX Warmdown Status
 */
#define GENFSK_SEQ_STS_TX_IN_WARMDN(x)           (((uint32_t)(((uint32_t)(x)) << GENFSK_SEQ_STS_TX_IN_WARMDN_SHIFT)) & GENFSK_SEQ_STS_TX_IN_WARMDN_MASK)

#define GENFSK_SEQ_STS_RX_START_T1_PEND_MASK     (0x20U)
#define GENFSK_SEQ_STS_RX_START_T1_PEND_SHIFT    (5U)
/*! RX_START_T1_PEND - RX T1 Start Pending Status
 */
#define GENFSK_SEQ_STS_RX_START_T1_PEND(x)       (((uint32_t)(((uint32_t)(x)) << GENFSK_SEQ_STS_RX_START_T1_PEND_SHIFT)) & GENFSK_SEQ_STS_RX_START_T1_PEND_MASK)

#define GENFSK_SEQ_STS_RX_START_T2_PEND_MASK     (0x40U)
#define GENFSK_SEQ_STS_RX_START_T2_PEND_SHIFT    (6U)
/*! RX_START_T2_PEND - RX T2 Start Pending Status
 */
#define GENFSK_SEQ_STS_RX_START_T2_PEND(x)       (((uint32_t)(((uint32_t)(x)) << GENFSK_SEQ_STS_RX_START_T2_PEND_SHIFT)) & GENFSK_SEQ_STS_RX_START_T2_PEND_MASK)

#define GENFSK_SEQ_STS_RX_STOP_T1_PEND_MASK      (0x80U)
#define GENFSK_SEQ_STS_RX_STOP_T1_PEND_SHIFT     (7U)
/*! RX_STOP_T1_PEND - RX T1 Stop Pending Status
 */
#define GENFSK_SEQ_STS_RX_STOP_T1_PEND(x)        (((uint32_t)(((uint32_t)(x)) << GENFSK_SEQ_STS_RX_STOP_T1_PEND_SHIFT)) & GENFSK_SEQ_STS_RX_STOP_T1_PEND_MASK)

#define GENFSK_SEQ_STS_RX_STOP_T2_PEND_MASK      (0x100U)
#define GENFSK_SEQ_STS_RX_STOP_T2_PEND_SHIFT     (8U)
/*! RX_STOP_T2_PEND - RX T2 Start Pending Status
 */
#define GENFSK_SEQ_STS_RX_STOP_T2_PEND(x)        (((uint32_t)(((uint32_t)(x)) << GENFSK_SEQ_STS_RX_STOP_T2_PEND_SHIFT)) & GENFSK_SEQ_STS_RX_STOP_T2_PEND_MASK)

#define GENFSK_SEQ_STS_RX_IN_WARMUP_MASK         (0x200U)
#define GENFSK_SEQ_STS_RX_IN_WARMUP_SHIFT        (9U)
/*! RX_IN_WARMUP - RX Warmup Status
 */
#define GENFSK_SEQ_STS_RX_IN_WARMUP(x)           (((uint32_t)(((uint32_t)(x)) << GENFSK_SEQ_STS_RX_IN_WARMUP_SHIFT)) & GENFSK_SEQ_STS_RX_IN_WARMUP_MASK)

#define GENFSK_SEQ_STS_RX_IN_SEARCH_MASK         (0x400U)
#define GENFSK_SEQ_STS_RX_IN_SEARCH_SHIFT        (10U)
/*! RX_IN_SEARCH - RX Search Status
 */
#define GENFSK_SEQ_STS_RX_IN_SEARCH(x)           (((uint32_t)(((uint32_t)(x)) << GENFSK_SEQ_STS_RX_IN_SEARCH_SHIFT)) & GENFSK_SEQ_STS_RX_IN_SEARCH_MASK)

#define GENFSK_SEQ_STS_RX_IN_PROGRESS_MASK       (0x800U)
#define GENFSK_SEQ_STS_RX_IN_PROGRESS_SHIFT      (11U)
/*! RX_IN_PROGRESS - RX in Progress Status
 */
#define GENFSK_SEQ_STS_RX_IN_PROGRESS(x)         (((uint32_t)(((uint32_t)(x)) << GENFSK_SEQ_STS_RX_IN_PROGRESS_SHIFT)) & GENFSK_SEQ_STS_RX_IN_PROGRESS_MASK)

#define GENFSK_SEQ_STS_RX_IN_WARMDN_MASK         (0x1000U)
#define GENFSK_SEQ_STS_RX_IN_WARMDN_SHIFT        (12U)
/*! RX_IN_WARMDN - RX Warmdown Status
 */
#define GENFSK_SEQ_STS_RX_IN_WARMDN(x)           (((uint32_t)(((uint32_t)(x)) << GENFSK_SEQ_STS_RX_IN_WARMDN_SHIFT)) & GENFSK_SEQ_STS_RX_IN_WARMDN_MASK)

#define GENFSK_SEQ_STS_TR_START_T1_PEND_MASK     (0x2000U)
#define GENFSK_SEQ_STS_TR_START_T1_PEND_SHIFT    (13U)
/*! TR_START_T1_PEND - TR T1 Start Pending Status
 */
#define GENFSK_SEQ_STS_TR_START_T1_PEND(x)       (((uint32_t)(((uint32_t)(x)) << GENFSK_SEQ_STS_TR_START_T1_PEND_SHIFT)) & GENFSK_SEQ_STS_TR_START_T1_PEND_MASK)

#define GENFSK_SEQ_STS_TR_START_T2_PEND_MASK     (0x4000U)
#define GENFSK_SEQ_STS_TR_START_T2_PEND_SHIFT    (14U)
/*! TR_START_T2_PEND - TR T2 Start Pending Status
 */
#define GENFSK_SEQ_STS_TR_START_T2_PEND(x)       (((uint32_t)(((uint32_t)(x)) << GENFSK_SEQ_STS_TR_START_T2_PEND_SHIFT)) & GENFSK_SEQ_STS_TR_START_T2_PEND_MASK)

#define GENFSK_SEQ_STS_CCA_START_T1_PEND_MASK    (0x8000U)
#define GENFSK_SEQ_STS_CCA_START_T1_PEND_SHIFT   (15U)
/*! CCA_START_T1_PEND - CCA T1 Start Pending Status
 */
#define GENFSK_SEQ_STS_CCA_START_T1_PEND(x)      (((uint32_t)(((uint32_t)(x)) << GENFSK_SEQ_STS_CCA_START_T1_PEND_SHIFT)) & GENFSK_SEQ_STS_CCA_START_T1_PEND_MASK)

#define GENFSK_SEQ_STS_CCA_START_T2_PEND_MASK    (0x10000U)
#define GENFSK_SEQ_STS_CCA_START_T2_PEND_SHIFT   (16U)
/*! CCA_START_T2_PEND - CCA T2 Start Pending Status
 */
#define GENFSK_SEQ_STS_CCA_START_T2_PEND(x)      (((uint32_t)(((uint32_t)(x)) << GENFSK_SEQ_STS_CCA_START_T2_PEND_SHIFT)) & GENFSK_SEQ_STS_CCA_START_T2_PEND_MASK)

#define GENFSK_SEQ_STS_SEQ_T_STATUS_MASK         (0x1F000000U)
#define GENFSK_SEQ_STS_SEQ_T_STATUS_SHIFT        (24U)
/*! SEQ_T_STATUS - Status of the just-completed or ongoing Sequence T or Sequence TR
 */
#define GENFSK_SEQ_STS_SEQ_T_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << GENFSK_SEQ_STS_SEQ_T_STATUS_SHIFT)) & GENFSK_SEQ_STS_SEQ_T_STATUS_MASK)
/*! @} */

/*! @name PHR_MISC - PHR MISCELLANEOUS */
/*! @{ */

#define GENFSK_PHR_MISC_SUNFSK_MS_MASK           (0x1U)
#define GENFSK_PHR_MISC_SUNFSK_MS_SHIFT          (0U)
/*! SUNFSK_MS - Mode Switch Bit
 */
#define GENFSK_PHR_MISC_SUNFSK_MS(x)             (((uint32_t)(((uint32_t)(x)) << GENFSK_PHR_MISC_SUNFSK_MS_SHIFT)) & GENFSK_PHR_MISC_SUNFSK_MS_MASK)

#define GENFSK_PHR_MISC_SUNFSK_MSP_MASK          (0x6U)
#define GENFSK_PHR_MISC_SUNFSK_MSP_SHIFT         (1U)
/*! SUNFSK_MSP - Mode Switch Parameter Bit
 */
#define GENFSK_PHR_MISC_SUNFSK_MSP(x)            (((uint32_t)(((uint32_t)(x)) << GENFSK_PHR_MISC_SUNFSK_MSP_SHIFT)) & GENFSK_PHR_MISC_SUNFSK_MSP_MASK)

#define GENFSK_PHR_MISC_SUNFSK_FEC_MASK          (0x8U)
#define GENFSK_PHR_MISC_SUNFSK_FEC_SHIFT         (3U)
/*! SUNFSK_FEC - New Mode FEC Bit
 */
#define GENFSK_PHR_MISC_SUNFSK_FEC(x)            (((uint32_t)(((uint32_t)(x)) << GENFSK_PHR_MISC_SUNFSK_FEC_SHIFT)) & GENFSK_PHR_MISC_SUNFSK_FEC_MASK)

#define GENFSK_PHR_MISC_SUNFSK_NM_MASK           (0x7F0U)
#define GENFSK_PHR_MISC_SUNFSK_NM_SHIFT          (4U)
/*! SUNFSK_NM - New Mode Bit
 */
#define GENFSK_PHR_MISC_SUNFSK_NM(x)             (((uint32_t)(((uint32_t)(x)) << GENFSK_PHR_MISC_SUNFSK_NM_SHIFT)) & GENFSK_PHR_MISC_SUNFSK_NM_MASK)

#define GENFSK_PHR_MISC_PHR_FAIL_IGNORE_MASK     (0x1000000U)
#define GENFSK_PHR_MISC_PHR_FAIL_IGNORE_SHIFT    (24U)
/*! PHR_FAIL_IGNORE - Ignore PHR Fail
 */
#define GENFSK_PHR_MISC_PHR_FAIL_IGNORE(x)       (((uint32_t)(((uint32_t)(x)) << GENFSK_PHR_MISC_PHR_FAIL_IGNORE_SHIFT)) & GENFSK_PHR_MISC_PHR_FAIL_IGNORE_MASK)
/*! @} */

/*! @name GTM_CTRL - GTM CONTROL */
/*! @{ */

#define GENFSK_GTM_CTRL_GTM_IN_RX_MASK           (0x1U)
#define GENFSK_GTM_CTRL_GTM_IN_RX_SHIFT          (0U)
/*! GTM_IN_RX - Enable GTM Receive Mode
 *  0b0..GTM receive mode is not enabled.
 *  0b1..GTM receive mode is enabled.
 */
#define GENFSK_GTM_CTRL_GTM_IN_RX(x)             (((uint32_t)(((uint32_t)(x)) << GENFSK_GTM_CTRL_GTM_IN_RX_SHIFT)) & GENFSK_GTM_CTRL_GTM_IN_RX_MASK)

#define GENFSK_GTM_CTRL_GTM_IN_TX_MASK           (0x2U)
#define GENFSK_GTM_CTRL_GTM_IN_TX_SHIFT          (1U)
/*! GTM_IN_TX - Enable GTM Transmit Mode
 *  0b0..GTM transmit mode is not enabled.
 *  0b1..GTM transmit mode is enabled.
 */
#define GENFSK_GTM_CTRL_GTM_IN_TX(x)             (((uint32_t)(((uint32_t)(x)) << GENFSK_GTM_CTRL_GTM_IN_TX_SHIFT)) & GENFSK_GTM_CTRL_GTM_IN_TX_MASK)
/*! @} */

/*! @name GTM_BAD_CNT - GTM BAD PACKET COUNTER */
/*! @{ */

#define GENFSK_GTM_BAD_CNT_GTM_BAD_PKT_COUNT_MASK (0x1FFFU)
#define GENFSK_GTM_BAD_CNT_GTM_BAD_PKT_COUNT_SHIFT (0U)
/*! GTM_BAD_PKT_COUNT - GTM Bad Packet Counter
 */
#define GENFSK_GTM_BAD_CNT_GTM_BAD_PKT_COUNT(x)  (((uint32_t)(((uint32_t)(x)) << GENFSK_GTM_BAD_CNT_GTM_BAD_PKT_COUNT_SHIFT)) & GENFSK_GTM_BAD_CNT_GTM_BAD_PKT_COUNT_MASK)
/*! @} */

/*! @name GTM_GOOD_CNT - GTM GOOD PACKET COUNTER */
/*! @{ */

#define GENFSK_GTM_GOOD_CNT_GTM_GOOD_PKT_COUNT_MASK (0x1FFFU)
#define GENFSK_GTM_GOOD_CNT_GTM_GOOD_PKT_COUNT_SHIFT (0U)
/*! GTM_GOOD_PKT_COUNT - GTM Good Packet Counter
 */
#define GENFSK_GTM_GOOD_CNT_GTM_GOOD_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_GTM_GOOD_CNT_GTM_GOOD_PKT_COUNT_SHIFT)) & GENFSK_GTM_GOOD_CNT_GTM_GOOD_PKT_COUNT_MASK)
/*! @} */

/*! @name GTM_PKT_CNT - GTM PACKET COUNTER */
/*! @{ */

#define GENFSK_GTM_PKT_CNT_GTM_PKT_COUNT_MASK    (0x1FFFU)
#define GENFSK_GTM_PKT_CNT_GTM_PKT_COUNT_SHIFT   (0U)
/*! GTM_PKT_COUNT - GTM Packet Counter
 */
#define GENFSK_GTM_PKT_CNT_GTM_PKT_COUNT(x)      (((uint32_t)(((uint32_t)(x)) << GENFSK_GTM_PKT_CNT_GTM_PKT_COUNT_SHIFT)) & GENFSK_GTM_PKT_CNT_GTM_PKT_COUNT_MASK)
/*! @} */

/*! @name COEX_CTRL - COEXISTENCE CONTROL */
/*! @{ */

#define GENFSK_COEX_CTRL_COEX_EN_MASK            (0x1U)
#define GENFSK_COEX_CTRL_COEX_EN_SHIFT           (0U)
/*! COEX_EN - Coexistence Enable
 *  0b0..Coexistence function is disabled.
 *  0b1..Coexistence function is enabled.
 */
#define GENFSK_COEX_CTRL_COEX_EN(x)              (((uint32_t)(((uint32_t)(x)) << GENFSK_COEX_CTRL_COEX_EN_SHIFT)) & GENFSK_COEX_CTRL_COEX_EN_MASK)

#define GENFSK_COEX_CTRL_COEX_REQ_DELAY_EN_MASK  (0x2U)
#define GENFSK_COEX_CTRL_COEX_REQ_DELAY_EN_SHIFT (1U)
/*! COEX_REQ_DELAY_EN - Coexistence Request Delay Enable
 *  0b0..arb_request is not delayed during R sequence.
 *  0b1..arb_request is delayed until preamble or Access Address is detected during R sequence.
 */
#define GENFSK_COEX_CTRL_COEX_REQ_DELAY_EN(x)    (((uint32_t)(((uint32_t)(x)) << GENFSK_COEX_CTRL_COEX_REQ_DELAY_EN_SHIFT)) & GENFSK_COEX_CTRL_COEX_REQ_DELAY_EN_MASK)

#define GENFSK_COEX_CTRL_COEX_REQ_ON_PD_MASK     (0x4U)
#define GENFSK_COEX_CTRL_COEX_REQ_ON_PD_SHIFT    (2U)
/*! COEX_REQ_ON_PD - Coexistence Request on Preamble detected
 *  0b0..arb_request is delayed until Access Address is detected during R sequence.
 *  0b1..arb_request is delayed until preamble is detected during R sequence.
 */
#define GENFSK_COEX_CTRL_COEX_REQ_ON_PD(x)       (((uint32_t)(((uint32_t)(x)) << GENFSK_COEX_CTRL_COEX_REQ_ON_PD_SHIFT)) & GENFSK_COEX_CTRL_COEX_REQ_ON_PD_MASK)

#define GENFSK_COEX_CTRL_COEX_TIMEOUT_MASK       (0xFF00U)
#define GENFSK_COEX_CTRL_COEX_TIMEOUT_SHIFT      (8U)
/*! COEX_TIMEOUT - Coexistence timeout value
 */
#define GENFSK_COEX_CTRL_COEX_TIMEOUT(x)         (((uint32_t)(((uint32_t)(x)) << GENFSK_COEX_CTRL_COEX_TIMEOUT_SHIFT)) & GENFSK_COEX_CTRL_COEX_TIMEOUT_MASK)
/*! @} */

/*! @name COEX_PRIORITY - COEXISTENCE PRIORITY */
/*! @{ */

#define GENFSK_COEX_PRIORITY_PRIORITY_T_MASK     (0x3U)
#define GENFSK_COEX_PRIORITY_PRIORITY_T_SHIFT    (0U)
/*! PRIORITY_T - PRIORITY_T
 */
#define GENFSK_COEX_PRIORITY_PRIORITY_T(x)       (((uint32_t)(((uint32_t)(x)) << GENFSK_COEX_PRIORITY_PRIORITY_T_SHIFT)) & GENFSK_COEX_PRIORITY_PRIORITY_T_MASK)

#define GENFSK_COEX_PRIORITY_PRIORITY_R_PRE_MASK (0xCU)
#define GENFSK_COEX_PRIORITY_PRIORITY_R_PRE_SHIFT (2U)
/*! PRIORITY_R_PRE - PRIORITY_R_PRE
 */
#define GENFSK_COEX_PRIORITY_PRIORITY_R_PRE(x)   (((uint32_t)(((uint32_t)(x)) << GENFSK_COEX_PRIORITY_PRIORITY_R_PRE_SHIFT)) & GENFSK_COEX_PRIORITY_PRIORITY_R_PRE_MASK)

#define GENFSK_COEX_PRIORITY_PRIORITY_R_PKT_MASK (0x30U)
#define GENFSK_COEX_PRIORITY_PRIORITY_R_PKT_SHIFT (4U)
/*! PRIORITY_R_PKT - PRIORITY_R_PKT
 */
#define GENFSK_COEX_PRIORITY_PRIORITY_R_PKT(x)   (((uint32_t)(((uint32_t)(x)) << GENFSK_COEX_PRIORITY_PRIORITY_R_PKT_SHIFT)) & GENFSK_COEX_PRIORITY_PRIORITY_R_PKT_MASK)

#define GENFSK_COEX_PRIORITY_PRIORITY_TACK_MASK  (0xC0U)
#define GENFSK_COEX_PRIORITY_PRIORITY_TACK_SHIFT (6U)
/*! PRIORITY_TACK - PRIORITY_TACK
 */
#define GENFSK_COEX_PRIORITY_PRIORITY_TACK(x)    (((uint32_t)(((uint32_t)(x)) << GENFSK_COEX_PRIORITY_PRIORITY_TACK_SHIFT)) & GENFSK_COEX_PRIORITY_PRIORITY_TACK_MASK)

#define GENFSK_COEX_PRIORITY_PRIORITY_CCA_MASK   (0x300U)
#define GENFSK_COEX_PRIORITY_PRIORITY_CCA_SHIFT  (8U)
/*! PRIORITY_CCA - PRIORITY_CCA
 */
#define GENFSK_COEX_PRIORITY_PRIORITY_CCA(x)     (((uint32_t)(((uint32_t)(x)) << GENFSK_COEX_PRIORITY_PRIORITY_CCA_SHIFT)) & GENFSK_COEX_PRIORITY_PRIORITY_CCA_MASK)

#define GENFSK_COEX_PRIORITY_PRIORITY_CTX_MASK   (0x3000U)
#define GENFSK_COEX_PRIORITY_PRIORITY_CTX_SHIFT  (12U)
/*! PRIORITY_CTX - PRIORITY_CT
 */
#define GENFSK_COEX_PRIORITY_PRIORITY_CTX(x)     (((uint32_t)(((uint32_t)(x)) << GENFSK_COEX_PRIORITY_PRIORITY_CTX_SHIFT)) & GENFSK_COEX_PRIORITY_PRIORITY_CTX_MASK)

#define GENFSK_COEX_PRIORITY_PRIORITY_RACK_PRE_MASK (0xC000U)
#define GENFSK_COEX_PRIORITY_PRIORITY_RACK_PRE_SHIFT (14U)
/*! PRIORITY_RACK_PRE - PRIORITY_RACK_PRE
 */
#define GENFSK_COEX_PRIORITY_PRIORITY_RACK_PRE(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_COEX_PRIORITY_PRIORITY_RACK_PRE_SHIFT)) & GENFSK_COEX_PRIORITY_PRIORITY_RACK_PRE_MASK)

#define GENFSK_COEX_PRIORITY_PRIORITY_RACK_PKT_MASK (0x30000U)
#define GENFSK_COEX_PRIORITY_PRIORITY_RACK_PKT_SHIFT (16U)
/*! PRIORITY_RACK_PKT - PRIORITY_RACK_PKT
 */
#define GENFSK_COEX_PRIORITY_PRIORITY_RACK_PKT(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_COEX_PRIORITY_PRIORITY_RACK_PKT_SHIFT)) & GENFSK_COEX_PRIORITY_PRIORITY_RACK_PKT_MASK)

#define GENFSK_COEX_PRIORITY_PRIORITY_OVRD_MASK  (0x60000000U)
#define GENFSK_COEX_PRIORITY_PRIORITY_OVRD_SHIFT (29U)
/*! PRIORITY_OVRD - PRIORITY_OVRD
 */
#define GENFSK_COEX_PRIORITY_PRIORITY_OVRD(x)    (((uint32_t)(((uint32_t)(x)) << GENFSK_COEX_PRIORITY_PRIORITY_OVRD_SHIFT)) & GENFSK_COEX_PRIORITY_PRIORITY_OVRD_MASK)

#define GENFSK_COEX_PRIORITY_PRIORITY_OVRD_EN_MASK (0x80000000U)
#define GENFSK_COEX_PRIORITY_PRIORITY_OVRD_EN_SHIFT (31U)
/*! PRIORITY_OVRD_EN - PRIORITY_OVRD_EN
 *  0b0..Disable overriding PRIORITY value.
 *  0b1..Enable overriding PRIORITY value.
 */
#define GENFSK_COEX_PRIORITY_PRIORITY_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_COEX_PRIORITY_PRIORITY_OVRD_EN_SHIFT)) & GENFSK_COEX_PRIORITY_PRIORITY_OVRD_EN_MASK)
/*! @} */

/*! @name IRQ_CTRL2 - IRQ CONTROL 2 */
/*! @{ */

#define GENFSK_IRQ_CTRL2_ARB_GRANT_DEASSERTION_IRQ_MASK (0x1U)
#define GENFSK_IRQ_CTRL2_ARB_GRANT_DEASSERTION_IRQ_SHIFT (0U)
/*! ARB_GRANT_DEASSERTION_IRQ - arb_grant Deassertion IRQ
 *  0b0..An arb_grant Deassertion Interrupt has not occurred
 *  0b1..An arb_grant Deassertion Interrupt has occurred
 */
#define GENFSK_IRQ_CTRL2_ARB_GRANT_DEASSERTION_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL2_ARB_GRANT_DEASSERTION_IRQ_SHIFT)) & GENFSK_IRQ_CTRL2_ARB_GRANT_DEASSERTION_IRQ_MASK)

#define GENFSK_IRQ_CTRL2_COEX_TIMEOUT_IRQ_MASK   (0x2U)
#define GENFSK_IRQ_CTRL2_COEX_TIMEOUT_IRQ_SHIFT  (1U)
/*! COEX_TIMEOUT_IRQ - Coexistence Timeout Interrupt
 */
#define GENFSK_IRQ_CTRL2_COEX_TIMEOUT_IRQ(x)     (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL2_COEX_TIMEOUT_IRQ_SHIFT)) & GENFSK_IRQ_CTRL2_COEX_TIMEOUT_IRQ_MASK)

#define GENFSK_IRQ_CTRL2_EVENT_TIMER_OVER_FLOW_IRQ_MASK (0x4U)
#define GENFSK_IRQ_CTRL2_EVENT_TIMER_OVER_FLOW_IRQ_SHIFT (2U)
/*! EVENT_TIMER_OVER_FLOW_IRQ - Event Timer Overflow Interrupt
 */
#define GENFSK_IRQ_CTRL2_EVENT_TIMER_OVER_FLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL2_EVENT_TIMER_OVER_FLOW_IRQ_SHIFT)) & GENFSK_IRQ_CTRL2_EVENT_TIMER_OVER_FLOW_IRQ_MASK)

#define GENFSK_IRQ_CTRL2_WL_FAIL_IRQ_MASK        (0x8U)
#define GENFSK_IRQ_CTRL2_WL_FAIL_IRQ_SHIFT       (3U)
/*! WL_FAIL_IRQ - White List Check Fail Interrupt
 */
#define GENFSK_IRQ_CTRL2_WL_FAIL_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL2_WL_FAIL_IRQ_SHIFT)) & GENFSK_IRQ_CTRL2_WL_FAIL_IRQ_MASK)

#define GENFSK_IRQ_CTRL2_DIRECT_ID_FAIL_IRQ_MASK (0x10U)
#define GENFSK_IRQ_CTRL2_DIRECT_ID_FAIL_IRQ_SHIFT (4U)
/*! DIRECT_ID_FAIL_IRQ - Direct Case Check Fail Interrupt
 */
#define GENFSK_IRQ_CTRL2_DIRECT_ID_FAIL_IRQ(x)   (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL2_DIRECT_ID_FAIL_IRQ_SHIFT)) & GENFSK_IRQ_CTRL2_DIRECT_ID_FAIL_IRQ_MASK)

#define GENFSK_IRQ_CTRL2_PEER_RPA_FAIL_IRQ_MASK  (0x20U)
#define GENFSK_IRQ_CTRL2_PEER_RPA_FAIL_IRQ_SHIFT (5U)
/*! PEER_RPA_FAIL_IRQ - Peer RPA Check Fail Interrupt
 */
#define GENFSK_IRQ_CTRL2_PEER_RPA_FAIL_IRQ(x)    (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL2_PEER_RPA_FAIL_IRQ_SHIFT)) & GENFSK_IRQ_CTRL2_PEER_RPA_FAIL_IRQ_MASK)

#define GENFSK_IRQ_CTRL2_LOCAL_RPA_FAIL_IRQ_MASK (0x40U)
#define GENFSK_IRQ_CTRL2_LOCAL_RPA_FAIL_IRQ_SHIFT (6U)
/*! LOCAL_RPA_FAIL_IRQ - Local RPA Check Fail Interrupt
 */
#define GENFSK_IRQ_CTRL2_LOCAL_RPA_FAIL_IRQ(x)   (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL2_LOCAL_RPA_FAIL_IRQ_SHIFT)) & GENFSK_IRQ_CTRL2_LOCAL_RPA_FAIL_IRQ_MASK)

#define GENFSK_IRQ_CTRL2_ARB_GRANT_DEASSERTION_IRQ_EN_MASK (0x10000U)
#define GENFSK_IRQ_CTRL2_ARB_GRANT_DEASSERTION_IRQ_EN_SHIFT (16U)
/*! ARB_GRANT_DEASSERTION_IRQ_EN - arb_grant Deassertion Interrupt enable
 *  0b1..allows arb_grant deassertion event to generate an interrupt
 *  0b0..An arb_grant deassertion event will set the ARB_GRANT_DEASSERTION_IRQ status bit, but no interrupt is not generated
 */
#define GENFSK_IRQ_CTRL2_ARB_GRANT_DEASSERTION_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL2_ARB_GRANT_DEASSERTION_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL2_ARB_GRANT_DEASSERTION_IRQ_EN_MASK)

#define GENFSK_IRQ_CTRL2_COEX_TIMEOUT_IRQ_EN_MASK (0x20000U)
#define GENFSK_IRQ_CTRL2_COEX_TIMEOUT_IRQ_EN_SHIFT (17U)
/*! COEX_TIMEOUT_IRQ_EN - Coexistence Timeout Interrupt enable bit
 *  0b1..allows interrupt when coexistence timeout
 *  0b0..Interrupt generation is disabled, but a COEX_TIMEOUT_IRQ flag can be set
 */
#define GENFSK_IRQ_CTRL2_COEX_TIMEOUT_IRQ_EN(x)  (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL2_COEX_TIMEOUT_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL2_COEX_TIMEOUT_IRQ_EN_MASK)

#define GENFSK_IRQ_CTRL2_EVENT_TIMER_OVER_FLOW_IRQ_EN_MASK (0x40000U)
#define GENFSK_IRQ_CTRL2_EVENT_TIMER_OVER_FLOW_IRQ_EN_SHIFT (18U)
/*! EVENT_TIMER_OVER_FLOW_IRQ_EN - Event Timer Overflow Interrupt enable bit
 *  0b1..allows interrupt when Event Timer overflow
 *  0b0..Interrupt generation is disabled, but an EVENT_TIMER_OVER_FLOW_IRQ flag can be set
 */
#define GENFSK_IRQ_CTRL2_EVENT_TIMER_OVER_FLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL2_EVENT_TIMER_OVER_FLOW_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL2_EVENT_TIMER_OVER_FLOW_IRQ_EN_MASK)

#define GENFSK_IRQ_CTRL2_WL_FAIL_IRQ_EN_MASK     (0x80000U)
#define GENFSK_IRQ_CTRL2_WL_FAIL_IRQ_EN_SHIFT    (19U)
/*! WL_FAIL_IRQ_EN
 *  0b0..WL_FAIL Interrupt is not enabled.
 *  0b1..WL_FAIL Interrupt is enabled.
 */
#define GENFSK_IRQ_CTRL2_WL_FAIL_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL2_WL_FAIL_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL2_WL_FAIL_IRQ_EN_MASK)

#define GENFSK_IRQ_CTRL2_DIRECT_ID_FAIL_IRQ_EN_MASK (0x100000U)
#define GENFSK_IRQ_CTRL2_DIRECT_ID_FAIL_IRQ_EN_SHIFT (20U)
/*! DIRECT_ID_FAIL_IRQ_EN
 *  0b0..DIRECT_ID_FAIL Interrupt is not enabled.
 *  0b1..DIRECT_ID_FAIL Interrupt is enabled.
 */
#define GENFSK_IRQ_CTRL2_DIRECT_ID_FAIL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL2_DIRECT_ID_FAIL_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL2_DIRECT_ID_FAIL_IRQ_EN_MASK)

#define GENFSK_IRQ_CTRL2_PEER_RPA_FAIL_IRQ_EN_MASK (0x200000U)
#define GENFSK_IRQ_CTRL2_PEER_RPA_FAIL_IRQ_EN_SHIFT (21U)
/*! PEER_RPA_FAIL_IRQ_EN
 *  0b0..PEER_RPA_FAIL Interrupt is not enabled.
 *  0b1..PEER_RPA_FAIL Interrupt is enabled.
 */
#define GENFSK_IRQ_CTRL2_PEER_RPA_FAIL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL2_PEER_RPA_FAIL_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL2_PEER_RPA_FAIL_IRQ_EN_MASK)

#define GENFSK_IRQ_CTRL2_LOCAL_RPA_FAIL_IRQ_EN_MASK (0x400000U)
#define GENFSK_IRQ_CTRL2_LOCAL_RPA_FAIL_IRQ_EN_SHIFT (22U)
/*! LOCAL_RPA_FAIL_IRQ_EN
 *  0b0..LOCAL_RPA_FAIL Interrupt is not enabled.
 *  0b1..LOCAL_RPA_FAIL Interrupt is enabled.
 */
#define GENFSK_IRQ_CTRL2_LOCAL_RPA_FAIL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL2_LOCAL_RPA_FAIL_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL2_LOCAL_RPA_FAIL_IRQ_EN_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group GENFSK_Register_Masks */


/* GENFSK - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral GENFSK base address */
  #define GENFSK_BASE                              (0x58A02000u)
  /** Peripheral GENFSK base address */
  #define GENFSK_BASE_NS                           (0x48A02000u)
  /** Peripheral GENFSK base pointer */
  #define GENFSK                                   ((GENFSK_Type *)GENFSK_BASE)
  /** Peripheral GENFSK base pointer */
  #define GENFSK_NS                                ((GENFSK_Type *)GENFSK_BASE_NS)
  /** Array initializer of GENFSK peripheral base addresses */
  #define GENFSK_BASE_ADDRS                        { GENFSK_BASE }
  /** Array initializer of GENFSK peripheral base pointers */
  #define GENFSK_BASE_PTRS                         { GENFSK }
  /** Array initializer of GENFSK peripheral base addresses */
  #define GENFSK_BASE_ADDRS_NS                     { GENFSK_BASE_NS }
  /** Array initializer of GENFSK peripheral base pointers */
  #define GENFSK_BASE_PTRS_NS                      { GENFSK_NS }
#else
  /** Peripheral GENFSK base address */
  #define GENFSK_BASE                              (0x48A02000u)
  /** Peripheral GENFSK base pointer */
  #define GENFSK                                   ((GENFSK_Type *)GENFSK_BASE)
  /** Array initializer of GENFSK peripheral base addresses */
  #define GENFSK_BASE_ADDRS                        { GENFSK_BASE }
  /** Array initializer of GENFSK peripheral base pointers */
  #define GENFSK_BASE_PTRS                         { GENFSK }
#endif

/*!
 * @}
 */ /* end of group GENFSK_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- GPIO Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
 * @{
 */

/** GPIO - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
  __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
       uint8_t RESERVED_0[4];
  __IO uint32_t LOCK;                              /**< Lock, offset: 0xC */
  __IO uint32_t PCNS;                              /**< Pin Control Non-Secure, offset: 0x10 */
  __IO uint32_t ICNS;                              /**< Interrupt Control Non-Secure, offset: 0x14 */
  __IO uint32_t PCNP;                              /**< Pin Control Non-Privilege, offset: 0x18 */
  __IO uint32_t ICNP;                              /**< Interrupt Control Non-Privilege, offset: 0x1C */
       uint8_t RESERVED_1[32];
  __IO uint32_t PDOR;                              /**< Port Data Output Register, offset: 0x40 */
  __O  uint32_t PSOR;                              /**< Port Set Output Register, offset: 0x44 */
  __O  uint32_t PCOR;                              /**< Port Clear Output Register, offset: 0x48 */
  __O  uint32_t PTOR;                              /**< Port Toggle Output Register, offset: 0x4C */
  __I  uint32_t PDIR;                              /**< Port Data Input Register, offset: 0x50 */
  __IO uint32_t PDDR;                              /**< Port Data Direction Register, offset: 0x54 */
  __IO uint32_t PIDR;                              /**< Port Input Disable Register, offset: 0x58 */
       uint8_t RESERVED_2[4];
  __IO uint8_t PDR[32];                            /**< Pin Data Register a, array offset: 0x60, array step: 0x1 */
  __IO uint32_t ICR[32];                           /**< Interrupt Control Register 0..Interrupt Control Register 31, array offset: 0x80, array step: 0x4 */
  __O  uint32_t GICLR;                             /**< Global Interrupt Control Low Register, offset: 0x100 */
  __O  uint32_t GICHR;                             /**< Global Interrupt Control High Register, offset: 0x104 */
       uint8_t RESERVED_3[24];
  __IO uint32_t ISFR[2];                           /**< Interrupt Status Flag Register, array offset: 0x120, array step: 0x4 */
} GPIO_Type;

/* ----------------------------------------------------------------------------
   -- GPIO Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup GPIO_Register_Masks GPIO Register Masks
 * @{
 */

/*! @name VERID - Version ID */
/*! @{ */

#define GPIO_VERID_FEATURE_MASK                  (0xFFFFU)
#define GPIO_VERID_FEATURE_SHIFT                 (0U)
/*! FEATURE - Feature Specification Number
 *  0b0000000000000000..Basic implementation.
 *  0b0000000000000001..Protection registers implemented.
 */
#define GPIO_VERID_FEATURE(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_VERID_FEATURE_SHIFT)) & GPIO_VERID_FEATURE_MASK)

#define GPIO_VERID_MINOR_MASK                    (0xFF0000U)
#define GPIO_VERID_MINOR_SHIFT                   (16U)
/*! MINOR - Minor Version Number
 */
#define GPIO_VERID_MINOR(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_VERID_MINOR_SHIFT)) & GPIO_VERID_MINOR_MASK)

#define GPIO_VERID_MAJOR_MASK                    (0xFF000000U)
#define GPIO_VERID_MAJOR_SHIFT                   (24U)
/*! MAJOR - Major Version Number
 */
#define GPIO_VERID_MAJOR(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_VERID_MAJOR_SHIFT)) & GPIO_VERID_MAJOR_MASK)
/*! @} */

/*! @name PARAM - Parameter */
/*! @{ */

#define GPIO_PARAM_IRQNUM_MASK                   (0xFU)
#define GPIO_PARAM_IRQNUM_SHIFT                  (0U)
/*! IRQNUM - Interrupt Number
 */
#define GPIO_PARAM_IRQNUM(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_PARAM_IRQNUM_SHIFT)) & GPIO_PARAM_IRQNUM_MASK)
/*! @} */

/*! @name LOCK - Lock */
/*! @{ */

#define GPIO_LOCK_PCNS_MASK                      (0x1U)
#define GPIO_LOCK_PCNS_SHIFT                     (0U)
/*! PCNS - Lock PCNS
 *  0b0..PCNS register is writable by software in Secure-Privilege state.
 *  0b1..PCNS register is not writable until the next reset.
 */
#define GPIO_LOCK_PCNS(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_LOCK_PCNS_SHIFT)) & GPIO_LOCK_PCNS_MASK)

#define GPIO_LOCK_ICNS_MASK                      (0x2U)
#define GPIO_LOCK_ICNS_SHIFT                     (1U)
/*! ICNS - Lock ICNS
 *  0b0..ICNS register is writable by software in Secure-Privilege state.
 *  0b1..ICNS register is not writable until the next reset.
 */
#define GPIO_LOCK_ICNS(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_LOCK_ICNS_SHIFT)) & GPIO_LOCK_ICNS_MASK)

#define GPIO_LOCK_PCNP_MASK                      (0x4U)
#define GPIO_LOCK_PCNP_SHIFT                     (2U)
/*! PCNP - Lock PCNP
 *  0b0..PCNP register is writable by software in Secure-Privilege state.
 *  0b1..PCNP register is not writable until the next reset.
 */
#define GPIO_LOCK_PCNP(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_LOCK_PCNP_SHIFT)) & GPIO_LOCK_PCNP_MASK)

#define GPIO_LOCK_ICNP_MASK                      (0x8U)
#define GPIO_LOCK_ICNP_SHIFT                     (3U)
/*! ICNP - Lock ICNP
 *  0b0..ICNP register is writable by software in Secure-Privilege state.
 *  0b1..ICNP register is not writable until the next reset.
 */
#define GPIO_LOCK_ICNP(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_LOCK_ICNP_SHIFT)) & GPIO_LOCK_ICNP_MASK)
/*! @} */

/*! @name PCNS - Pin Control Non-Secure */
/*! @{ */

#define GPIO_PCNS_NSE0_MASK                      (0x1U)
#define GPIO_PCNS_NSE0_SHIFT                     (0U)
/*! NSE0 - Non-Secure Enable
 *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
 *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
 *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define GPIO_PCNS_NSE0(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE0_SHIFT)) & GPIO_PCNS_NSE0_MASK)

#define GPIO_PCNS_NSE1_MASK                      (0x2U)
#define GPIO_PCNS_NSE1_SHIFT                     (1U)
/*! NSE1 - Non-Secure Enable
 *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
 *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
 *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define GPIO_PCNS_NSE1(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE1_SHIFT)) & GPIO_PCNS_NSE1_MASK)

#define GPIO_PCNS_NSE2_MASK                      (0x4U)
#define GPIO_PCNS_NSE2_SHIFT                     (2U)
/*! NSE2 - Non-Secure Enable
 *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
 *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
 *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define GPIO_PCNS_NSE2(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE2_SHIFT)) & GPIO_PCNS_NSE2_MASK)

#define GPIO_PCNS_NSE3_MASK                      (0x8U)
#define GPIO_PCNS_NSE3_SHIFT                     (3U)
/*! NSE3 - Non-Secure Enable
 *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
 *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
 *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define GPIO_PCNS_NSE3(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE3_SHIFT)) & GPIO_PCNS_NSE3_MASK)

#define GPIO_PCNS_NSE4_MASK                      (0x10U)
#define GPIO_PCNS_NSE4_SHIFT                     (4U)
/*! NSE4 - Non-Secure Enable
 *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
 *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
 *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define GPIO_PCNS_NSE4(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE4_SHIFT)) & GPIO_PCNS_NSE4_MASK)

#define GPIO_PCNS_NSE5_MASK                      (0x20U)
#define GPIO_PCNS_NSE5_SHIFT                     (5U)
/*! NSE5 - Non-Secure Enable
 *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
 *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
 *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define GPIO_PCNS_NSE5(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE5_SHIFT)) & GPIO_PCNS_NSE5_MASK)

#define GPIO_PCNS_NSE6_MASK                      (0x40U)
#define GPIO_PCNS_NSE6_SHIFT                     (6U)
/*! NSE6 - Non-Secure Enable
 *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
 *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
 *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define GPIO_PCNS_NSE6(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE6_SHIFT)) & GPIO_PCNS_NSE6_MASK)

#define GPIO_PCNS_NSE7_MASK                      (0x80U)
#define GPIO_PCNS_NSE7_SHIFT                     (7U)
/*! NSE7 - Non-Secure Enable
 *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
 *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
 *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define GPIO_PCNS_NSE7(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE7_SHIFT)) & GPIO_PCNS_NSE7_MASK)

#define GPIO_PCNS_NSE8_MASK                      (0x100U)
#define GPIO_PCNS_NSE8_SHIFT                     (8U)
/*! NSE8 - Non-Secure Enable
 *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
 *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
 *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define GPIO_PCNS_NSE8(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE8_SHIFT)) & GPIO_PCNS_NSE8_MASK)

#define GPIO_PCNS_NSE9_MASK                      (0x200U)
#define GPIO_PCNS_NSE9_SHIFT                     (9U)
/*! NSE9 - Non-Secure Enable
 *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
 *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
 *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define GPIO_PCNS_NSE9(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE9_SHIFT)) & GPIO_PCNS_NSE9_MASK)

#define GPIO_PCNS_NSE10_MASK                     (0x400U)
#define GPIO_PCNS_NSE10_SHIFT                    (10U)
/*! NSE10 - Non-Secure Enable
 *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
 *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
 *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define GPIO_PCNS_NSE10(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE10_SHIFT)) & GPIO_PCNS_NSE10_MASK)

#define GPIO_PCNS_NSE11_MASK                     (0x800U)
#define GPIO_PCNS_NSE11_SHIFT                    (11U)
/*! NSE11 - Non-Secure Enable
 *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
 *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
 *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define GPIO_PCNS_NSE11(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE11_SHIFT)) & GPIO_PCNS_NSE11_MASK)

#define GPIO_PCNS_NSE12_MASK                     (0x1000U)
#define GPIO_PCNS_NSE12_SHIFT                    (12U)
/*! NSE12 - Non-Secure Enable
 *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
 *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
 *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define GPIO_PCNS_NSE12(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE12_SHIFT)) & GPIO_PCNS_NSE12_MASK)

#define GPIO_PCNS_NSE13_MASK                     (0x2000U)
#define GPIO_PCNS_NSE13_SHIFT                    (13U)
/*! NSE13 - Non-Secure Enable
 *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
 *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
 *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define GPIO_PCNS_NSE13(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE13_SHIFT)) & GPIO_PCNS_NSE13_MASK)

#define GPIO_PCNS_NSE14_MASK                     (0x4000U)
#define GPIO_PCNS_NSE14_SHIFT                    (14U)
/*! NSE14 - Non-Secure Enable
 *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
 *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
 *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define GPIO_PCNS_NSE14(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE14_SHIFT)) & GPIO_PCNS_NSE14_MASK)

#define GPIO_PCNS_NSE15_MASK                     (0x8000U)
#define GPIO_PCNS_NSE15_SHIFT                    (15U)
/*! NSE15 - Non-Secure Enable
 *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
 *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
 *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define GPIO_PCNS_NSE15(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE15_SHIFT)) & GPIO_PCNS_NSE15_MASK)

#define GPIO_PCNS_NSE16_MASK                     (0x10000U)
#define GPIO_PCNS_NSE16_SHIFT                    (16U)
/*! NSE16 - Non-Secure Enable
 *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
 *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
 *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define GPIO_PCNS_NSE16(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE16_SHIFT)) & GPIO_PCNS_NSE16_MASK)

#define GPIO_PCNS_NSE17_MASK                     (0x20000U)
#define GPIO_PCNS_NSE17_SHIFT                    (17U)
/*! NSE17 - Non-Secure Enable
 *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
 *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
 *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define GPIO_PCNS_NSE17(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE17_SHIFT)) & GPIO_PCNS_NSE17_MASK)

#define GPIO_PCNS_NSE18_MASK                     (0x40000U)
#define GPIO_PCNS_NSE18_SHIFT                    (18U)
/*! NSE18 - Non-Secure Enable
 *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
 *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
 *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define GPIO_PCNS_NSE18(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE18_SHIFT)) & GPIO_PCNS_NSE18_MASK)

#define GPIO_PCNS_NSE19_MASK                     (0x80000U)
#define GPIO_PCNS_NSE19_SHIFT                    (19U)
/*! NSE19 - Non-Secure Enable
 *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
 *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
 *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define GPIO_PCNS_NSE19(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE19_SHIFT)) & GPIO_PCNS_NSE19_MASK)

#define GPIO_PCNS_NSE20_MASK                     (0x100000U)
#define GPIO_PCNS_NSE20_SHIFT                    (20U)
/*! NSE20 - Non-Secure Enable
 *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
 *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
 *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define GPIO_PCNS_NSE20(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE20_SHIFT)) & GPIO_PCNS_NSE20_MASK)

#define GPIO_PCNS_NSE21_MASK                     (0x200000U)
#define GPIO_PCNS_NSE21_SHIFT                    (21U)
/*! NSE21 - Non-Secure Enable
 *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
 *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
 *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define GPIO_PCNS_NSE21(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE21_SHIFT)) & GPIO_PCNS_NSE21_MASK)

#define GPIO_PCNS_NSE22_MASK                     (0x400000U)
#define GPIO_PCNS_NSE22_SHIFT                    (22U)
/*! NSE22 - Non-Secure Enable
 *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
 *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
 *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define GPIO_PCNS_NSE22(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE22_SHIFT)) & GPIO_PCNS_NSE22_MASK)

#define GPIO_PCNS_NSE23_MASK                     (0x800000U)
#define GPIO_PCNS_NSE23_SHIFT                    (23U)
/*! NSE23 - Non-Secure Enable
 *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
 *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
 *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define GPIO_PCNS_NSE23(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE23_SHIFT)) & GPIO_PCNS_NSE23_MASK)

#define GPIO_PCNS_NSE24_MASK                     (0x1000000U)
#define GPIO_PCNS_NSE24_SHIFT                    (24U)
/*! NSE24 - Non-Secure Enable
 *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
 *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
 *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define GPIO_PCNS_NSE24(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE24_SHIFT)) & GPIO_PCNS_NSE24_MASK)

#define GPIO_PCNS_NSE25_MASK                     (0x2000000U)
#define GPIO_PCNS_NSE25_SHIFT                    (25U)
/*! NSE25 - Non-Secure Enable
 *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
 *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
 *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define GPIO_PCNS_NSE25(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE25_SHIFT)) & GPIO_PCNS_NSE25_MASK)

#define GPIO_PCNS_NSE26_MASK                     (0x4000000U)
#define GPIO_PCNS_NSE26_SHIFT                    (26U)
/*! NSE26 - Non-Secure Enable
 *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
 *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
 *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define GPIO_PCNS_NSE26(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE26_SHIFT)) & GPIO_PCNS_NSE26_MASK)

#define GPIO_PCNS_NSE27_MASK                     (0x8000000U)
#define GPIO_PCNS_NSE27_SHIFT                    (27U)
/*! NSE27 - Non-Secure Enable
 *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
 *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
 *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define GPIO_PCNS_NSE27(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE27_SHIFT)) & GPIO_PCNS_NSE27_MASK)

#define GPIO_PCNS_NSE28_MASK                     (0x10000000U)
#define GPIO_PCNS_NSE28_SHIFT                    (28U)
/*! NSE28 - Non-Secure Enable
 *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
 *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
 *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define GPIO_PCNS_NSE28(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE28_SHIFT)) & GPIO_PCNS_NSE28_MASK)

#define GPIO_PCNS_NSE29_MASK                     (0x20000000U)
#define GPIO_PCNS_NSE29_SHIFT                    (29U)
/*! NSE29 - Non-Secure Enable
 *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
 *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
 *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define GPIO_PCNS_NSE29(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE29_SHIFT)) & GPIO_PCNS_NSE29_MASK)

#define GPIO_PCNS_NSE30_MASK                     (0x40000000U)
#define GPIO_PCNS_NSE30_SHIFT                    (30U)
/*! NSE30 - Non-Secure Enable
 *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
 *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
 *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define GPIO_PCNS_NSE30(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE30_SHIFT)) & GPIO_PCNS_NSE30_MASK)

#define GPIO_PCNS_NSE31_MASK                     (0x80000000U)
#define GPIO_PCNS_NSE31_SHIFT                    (31U)
/*! NSE31 - Non-Secure Enable
 *  0b0..The pin is configured for Secure access. Read or write access to the corresponding pin's registers and
 *       bit fields is only allowed by software in Secure state. When the corresponding pin's registers are accessed
 *       by software in Non-Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 *  0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin's registers
 *       and bit fields is only allowed by software in Non-Secure state. When the corresponding pin's registers are
 *       accessed by software in Secure state, all bits in the registers related to that pin are read zero and write
 *       ignored.
 */
#define GPIO_PCNS_NSE31(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE31_SHIFT)) & GPIO_PCNS_NSE31_MASK)
/*! @} */

/*! @name ICNS - Interrupt Control Non-Secure */
/*! @{ */

#define GPIO_ICNS_NSE0_MASK                      (0x1U)
#define GPIO_ICNS_NSE0_SHIFT                     (0U)
/*! NSE0 - Non-Secure Enable
 *  0b0..The interrupt or DMA request or output trigger is configured for Secure access. Only software in Secure
 *       state can configure a pin to use the corresponding interrupt or DMA request or output trigger or
 *       reconfigure a pin that is already configured to use the corresponding interrupt or DMA request or output trigger.
 *  0b1..The interrupt or DMA request or trigger output is configured for Non-Secure access. Only software in
 *       Non-Secure state can configure a pin to use the corresponding interrupt or DMA request or output trigger or
 *       reconfigure a pin that is already configured to use the corresponding interrupt or DMA request or output
 *       trigger.
 */
#define GPIO_ICNS_NSE0(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICNS_NSE0_SHIFT)) & GPIO_ICNS_NSE0_MASK)

#define GPIO_ICNS_NSE1_MASK                      (0x2U)
#define GPIO_ICNS_NSE1_SHIFT                     (1U)
/*! NSE1 - Non-Secure Enable
 *  0b0..The interrupt or DMA request or output trigger is configured for Secure access. Only software in Secure
 *       state can configure a pin to use the corresponding interrupt or DMA request or output trigger or
 *       reconfigure a pin that is already configured to use the corresponding interrupt or DMA request or output trigger.
 *  0b1..The interrupt or DMA request or trigger output is configured for Non-Secure access. Only software in
 *       Non-Secure state can configure a pin to use the corresponding interrupt or DMA request or output trigger or
 *       reconfigure a pin that is already configured to use the corresponding interrupt or DMA request or output
 *       trigger.
 */
#define GPIO_ICNS_NSE1(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICNS_NSE1_SHIFT)) & GPIO_ICNS_NSE1_MASK)
/*! @} */

/*! @name PCNP - Pin Control Non-Privilege */
/*! @{ */

#define GPIO_PCNP_NPE0_MASK                      (0x1U)
#define GPIO_PCNP_NPE0_SHIFT                     (0U)
/*! NPE0 - Non-Privilege Enable
 *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both Privilege or Non-Privilege state.
 */
#define GPIO_PCNP_NPE0(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE0_SHIFT)) & GPIO_PCNP_NPE0_MASK)

#define GPIO_PCNP_NPE1_MASK                      (0x2U)
#define GPIO_PCNP_NPE1_SHIFT                     (1U)
/*! NPE1 - Non-Privilege Enable
 *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both Privilege or Non-Privilege state.
 */
#define GPIO_PCNP_NPE1(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE1_SHIFT)) & GPIO_PCNP_NPE1_MASK)

#define GPIO_PCNP_NPE2_MASK                      (0x4U)
#define GPIO_PCNP_NPE2_SHIFT                     (2U)
/*! NPE2 - Non-Privilege Enable
 *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both Privilege or Non-Privilege state.
 */
#define GPIO_PCNP_NPE2(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE2_SHIFT)) & GPIO_PCNP_NPE2_MASK)

#define GPIO_PCNP_NPE3_MASK                      (0x8U)
#define GPIO_PCNP_NPE3_SHIFT                     (3U)
/*! NPE3 - Non-Privilege Enable
 *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both Privilege or Non-Privilege state.
 */
#define GPIO_PCNP_NPE3(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE3_SHIFT)) & GPIO_PCNP_NPE3_MASK)

#define GPIO_PCNP_NPE4_MASK                      (0x10U)
#define GPIO_PCNP_NPE4_SHIFT                     (4U)
/*! NPE4 - Non-Privilege Enable
 *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both Privilege or Non-Privilege state.
 */
#define GPIO_PCNP_NPE4(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE4_SHIFT)) & GPIO_PCNP_NPE4_MASK)

#define GPIO_PCNP_NPE5_MASK                      (0x20U)
#define GPIO_PCNP_NPE5_SHIFT                     (5U)
/*! NPE5 - Non-Privilege Enable
 *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both Privilege or Non-Privilege state.
 */
#define GPIO_PCNP_NPE5(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE5_SHIFT)) & GPIO_PCNP_NPE5_MASK)

#define GPIO_PCNP_NPE6_MASK                      (0x40U)
#define GPIO_PCNP_NPE6_SHIFT                     (6U)
/*! NPE6 - Non-Privilege Enable
 *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both Privilege or Non-Privilege state.
 */
#define GPIO_PCNP_NPE6(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE6_SHIFT)) & GPIO_PCNP_NPE6_MASK)

#define GPIO_PCNP_NPE7_MASK                      (0x80U)
#define GPIO_PCNP_NPE7_SHIFT                     (7U)
/*! NPE7 - Non-Privilege Enable
 *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both Privilege or Non-Privilege state.
 */
#define GPIO_PCNP_NPE7(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE7_SHIFT)) & GPIO_PCNP_NPE7_MASK)

#define GPIO_PCNP_NPE8_MASK                      (0x100U)
#define GPIO_PCNP_NPE8_SHIFT                     (8U)
/*! NPE8 - Non-Privilege Enable
 *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both Privilege or Non-Privilege state.
 */
#define GPIO_PCNP_NPE8(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE8_SHIFT)) & GPIO_PCNP_NPE8_MASK)

#define GPIO_PCNP_NPE9_MASK                      (0x200U)
#define GPIO_PCNP_NPE9_SHIFT                     (9U)
/*! NPE9 - Non-Privilege Enable
 *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both Privilege or Non-Privilege state.
 */
#define GPIO_PCNP_NPE9(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE9_SHIFT)) & GPIO_PCNP_NPE9_MASK)

#define GPIO_PCNP_NPE10_MASK                     (0x400U)
#define GPIO_PCNP_NPE10_SHIFT                    (10U)
/*! NPE10 - Non-Privilege Enable
 *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both Privilege or Non-Privilege state.
 */
#define GPIO_PCNP_NPE10(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE10_SHIFT)) & GPIO_PCNP_NPE10_MASK)

#define GPIO_PCNP_NPE11_MASK                     (0x800U)
#define GPIO_PCNP_NPE11_SHIFT                    (11U)
/*! NPE11 - Non-Privilege Enable
 *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both Privilege or Non-Privilege state.
 */
#define GPIO_PCNP_NPE11(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE11_SHIFT)) & GPIO_PCNP_NPE11_MASK)

#define GPIO_PCNP_NPE12_MASK                     (0x1000U)
#define GPIO_PCNP_NPE12_SHIFT                    (12U)
/*! NPE12 - Non-Privilege Enable
 *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both Privilege or Non-Privilege state.
 */
#define GPIO_PCNP_NPE12(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE12_SHIFT)) & GPIO_PCNP_NPE12_MASK)

#define GPIO_PCNP_NPE13_MASK                     (0x2000U)
#define GPIO_PCNP_NPE13_SHIFT                    (13U)
/*! NPE13 - Non-Privilege Enable
 *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both Privilege or Non-Privilege state.
 */
#define GPIO_PCNP_NPE13(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE13_SHIFT)) & GPIO_PCNP_NPE13_MASK)

#define GPIO_PCNP_NPE14_MASK                     (0x4000U)
#define GPIO_PCNP_NPE14_SHIFT                    (14U)
/*! NPE14 - Non-Privilege Enable
 *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both Privilege or Non-Privilege state.
 */
#define GPIO_PCNP_NPE14(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE14_SHIFT)) & GPIO_PCNP_NPE14_MASK)

#define GPIO_PCNP_NPE15_MASK                     (0x8000U)
#define GPIO_PCNP_NPE15_SHIFT                    (15U)
/*! NPE15 - Non-Privilege Enable
 *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both Privilege or Non-Privilege state.
 */
#define GPIO_PCNP_NPE15(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE15_SHIFT)) & GPIO_PCNP_NPE15_MASK)

#define GPIO_PCNP_NPE16_MASK                     (0x10000U)
#define GPIO_PCNP_NPE16_SHIFT                    (16U)
/*! NPE16 - Non-Privilege Enable
 *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both Privilege or Non-Privilege state.
 */
#define GPIO_PCNP_NPE16(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE16_SHIFT)) & GPIO_PCNP_NPE16_MASK)

#define GPIO_PCNP_NPE17_MASK                     (0x20000U)
#define GPIO_PCNP_NPE17_SHIFT                    (17U)
/*! NPE17 - Non-Privilege Enable
 *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both Privilege or Non-Privilege state.
 */
#define GPIO_PCNP_NPE17(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE17_SHIFT)) & GPIO_PCNP_NPE17_MASK)

#define GPIO_PCNP_NPE18_MASK                     (0x40000U)
#define GPIO_PCNP_NPE18_SHIFT                    (18U)
/*! NPE18 - Non-Privilege Enable
 *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both Privilege or Non-Privilege state.
 */
#define GPIO_PCNP_NPE18(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE18_SHIFT)) & GPIO_PCNP_NPE18_MASK)

#define GPIO_PCNP_NPE19_MASK                     (0x80000U)
#define GPIO_PCNP_NPE19_SHIFT                    (19U)
/*! NPE19 - Non-Privilege Enable
 *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both Privilege or Non-Privilege state.
 */
#define GPIO_PCNP_NPE19(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE19_SHIFT)) & GPIO_PCNP_NPE19_MASK)

#define GPIO_PCNP_NPE20_MASK                     (0x100000U)
#define GPIO_PCNP_NPE20_SHIFT                    (20U)
/*! NPE20 - Non-Privilege Enable
 *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both Privilege or Non-Privilege state.
 */
#define GPIO_PCNP_NPE20(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE20_SHIFT)) & GPIO_PCNP_NPE20_MASK)

#define GPIO_PCNP_NPE21_MASK                     (0x200000U)
#define GPIO_PCNP_NPE21_SHIFT                    (21U)
/*! NPE21 - Non-Privilege Enable
 *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both Privilege or Non-Privilege state.
 */
#define GPIO_PCNP_NPE21(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE21_SHIFT)) & GPIO_PCNP_NPE21_MASK)

#define GPIO_PCNP_NPE22_MASK                     (0x400000U)
#define GPIO_PCNP_NPE22_SHIFT                    (22U)
/*! NPE22 - Non-Privilege Enable
 *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both Privilege or Non-Privilege state.
 */
#define GPIO_PCNP_NPE22(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE22_SHIFT)) & GPIO_PCNP_NPE22_MASK)

#define GPIO_PCNP_NPE23_MASK                     (0x800000U)
#define GPIO_PCNP_NPE23_SHIFT                    (23U)
/*! NPE23 - Non-Privilege Enable
 *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both Privilege or Non-Privilege state.
 */
#define GPIO_PCNP_NPE23(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE23_SHIFT)) & GPIO_PCNP_NPE23_MASK)

#define GPIO_PCNP_NPE24_MASK                     (0x1000000U)
#define GPIO_PCNP_NPE24_SHIFT                    (24U)
/*! NPE24 - Non-Privilege Enable
 *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both Privilege or Non-Privilege state.
 */
#define GPIO_PCNP_NPE24(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE24_SHIFT)) & GPIO_PCNP_NPE24_MASK)

#define GPIO_PCNP_NPE25_MASK                     (0x2000000U)
#define GPIO_PCNP_NPE25_SHIFT                    (25U)
/*! NPE25 - Non-Privilege Enable
 *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both Privilege or Non-Privilege state.
 */
#define GPIO_PCNP_NPE25(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE25_SHIFT)) & GPIO_PCNP_NPE25_MASK)

#define GPIO_PCNP_NPE26_MASK                     (0x4000000U)
#define GPIO_PCNP_NPE26_SHIFT                    (26U)
/*! NPE26 - Non-Privilege Enable
 *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both Privilege or Non-Privilege state.
 */
#define GPIO_PCNP_NPE26(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE26_SHIFT)) & GPIO_PCNP_NPE26_MASK)

#define GPIO_PCNP_NPE27_MASK                     (0x8000000U)
#define GPIO_PCNP_NPE27_SHIFT                    (27U)
/*! NPE27 - Non-Privilege Enable
 *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both Privilege or Non-Privilege state.
 */
#define GPIO_PCNP_NPE27(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE27_SHIFT)) & GPIO_PCNP_NPE27_MASK)

#define GPIO_PCNP_NPE28_MASK                     (0x10000000U)
#define GPIO_PCNP_NPE28_SHIFT                    (28U)
/*! NPE28 - Non-Privilege Enable
 *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both Privilege or Non-Privilege state.
 */
#define GPIO_PCNP_NPE28(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE28_SHIFT)) & GPIO_PCNP_NPE28_MASK)

#define GPIO_PCNP_NPE29_MASK                     (0x20000000U)
#define GPIO_PCNP_NPE29_SHIFT                    (29U)
/*! NPE29 - Non-Privilege Enable
 *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both Privilege or Non-Privilege state.
 */
#define GPIO_PCNP_NPE29(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE29_SHIFT)) & GPIO_PCNP_NPE29_MASK)

#define GPIO_PCNP_NPE30_MASK                     (0x40000000U)
#define GPIO_PCNP_NPE30_SHIFT                    (30U)
/*! NPE30 - Non-Privilege Enable
 *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both Privilege or Non-Privilege state.
 */
#define GPIO_PCNP_NPE30(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE30_SHIFT)) & GPIO_PCNP_NPE30_MASK)

#define GPIO_PCNP_NPE31_MASK                     (0x80000000U)
#define GPIO_PCNP_NPE31_SHIFT                    (31U)
/*! NPE31 - Non-Privilege Enable
 *  0b0..The pin is configured for Privilege access. Write access to the corresponding pin's registers and bit
 *       fields is allowed only by software in Privilege state. When the corresponding pin's registers and bit fields
 *       are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO are readable
 *       but write ignored.
 *  0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding pin's registers
 *       is allowed by software in both Privilege or Non-Privilege state.
 */
#define GPIO_PCNP_NPE31(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE31_SHIFT)) & GPIO_PCNP_NPE31_MASK)
/*! @} */

/*! @name ICNP - Interrupt Control Non-Privilege */
/*! @{ */

#define GPIO_ICNP_NPE0_MASK                      (0x1U)
#define GPIO_ICNP_NPE0_SHIFT                     (0U)
/*! NPE0 - Non-Privilege Enable
 *  0b0..The pin is configured for Privilege access. Only software in Privilege state can configure a pin to use
 *       the corresponding interrupt/DMA request/trigger output or reconfigure a pin that is already configured to
 *       use the corresponding interrupt/DMA request/trigger output.
 *  0b1..The pin is configured for Non-Privilege access. Software in either Privilege or Non-Privilege state can
 *       configure a pin to use the corresponding interrupt/DMA request/trigger output or reconfigure a pin that is
 *       already configured to use the corresponding interrupt/DMA request/trigger output.
 */
#define GPIO_ICNP_NPE0(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICNP_NPE0_SHIFT)) & GPIO_ICNP_NPE0_MASK)

#define GPIO_ICNP_NPE1_MASK                      (0x2U)
#define GPIO_ICNP_NPE1_SHIFT                     (1U)
/*! NPE1 - Non-Privilege Enable
 *  0b0..The pin is configured for Privilege access. Only software in Privilege state can configure a pin to use
 *       the corresponding interrupt/DMA request/trigger output or reconfigure a pin that is already configured to
 *       use the corresponding interrupt/DMA request/trigger output.
 *  0b1..The pin is configured for Non-Privilege access. Software in either Privilege or Non-Privilege state can
 *       configure a pin to use the corresponding interrupt/DMA request/trigger output or reconfigure a pin that is
 *       already configured to use the corresponding interrupt/DMA request/trigger output.
 */
#define GPIO_ICNP_NPE1(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICNP_NPE1_SHIFT)) & GPIO_ICNP_NPE1_MASK)
/*! @} */

/*! @name PDOR - Port Data Output Register */
/*! @{ */

#define GPIO_PDOR_PDO0_MASK                      (0x1U)
#define GPIO_PDOR_PDO0_SHIFT                     (0U)
/*! PDO0 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define GPIO_PDOR_PDO0(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO0_SHIFT)) & GPIO_PDOR_PDO0_MASK)

#define GPIO_PDOR_PDO1_MASK                      (0x2U)
#define GPIO_PDOR_PDO1_SHIFT                     (1U)
/*! PDO1 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define GPIO_PDOR_PDO1(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO1_SHIFT)) & GPIO_PDOR_PDO1_MASK)

#define GPIO_PDOR_PDO2_MASK                      (0x4U)
#define GPIO_PDOR_PDO2_SHIFT                     (2U)
/*! PDO2 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define GPIO_PDOR_PDO2(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO2_SHIFT)) & GPIO_PDOR_PDO2_MASK)

#define GPIO_PDOR_PDO3_MASK                      (0x8U)
#define GPIO_PDOR_PDO3_SHIFT                     (3U)
/*! PDO3 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define GPIO_PDOR_PDO3(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO3_SHIFT)) & GPIO_PDOR_PDO3_MASK)

#define GPIO_PDOR_PDO4_MASK                      (0x10U)
#define GPIO_PDOR_PDO4_SHIFT                     (4U)
/*! PDO4 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define GPIO_PDOR_PDO4(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO4_SHIFT)) & GPIO_PDOR_PDO4_MASK)

#define GPIO_PDOR_PDO5_MASK                      (0x20U)
#define GPIO_PDOR_PDO5_SHIFT                     (5U)
/*! PDO5 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define GPIO_PDOR_PDO5(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO5_SHIFT)) & GPIO_PDOR_PDO5_MASK)

#define GPIO_PDOR_PDO6_MASK                      (0x40U)
#define GPIO_PDOR_PDO6_SHIFT                     (6U)
/*! PDO6 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define GPIO_PDOR_PDO6(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO6_SHIFT)) & GPIO_PDOR_PDO6_MASK)

#define GPIO_PDOR_PDO7_MASK                      (0x80U)
#define GPIO_PDOR_PDO7_SHIFT                     (7U)
/*! PDO7 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define GPIO_PDOR_PDO7(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO7_SHIFT)) & GPIO_PDOR_PDO7_MASK)

#define GPIO_PDOR_PDO8_MASK                      (0x100U)
#define GPIO_PDOR_PDO8_SHIFT                     (8U)
/*! PDO8 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define GPIO_PDOR_PDO8(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO8_SHIFT)) & GPIO_PDOR_PDO8_MASK)

#define GPIO_PDOR_PDO9_MASK                      (0x200U)
#define GPIO_PDOR_PDO9_SHIFT                     (9U)
/*! PDO9 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define GPIO_PDOR_PDO9(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO9_SHIFT)) & GPIO_PDOR_PDO9_MASK)

#define GPIO_PDOR_PDO10_MASK                     (0x400U)
#define GPIO_PDOR_PDO10_SHIFT                    (10U)
/*! PDO10 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define GPIO_PDOR_PDO10(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO10_SHIFT)) & GPIO_PDOR_PDO10_MASK)

#define GPIO_PDOR_PDO11_MASK                     (0x800U)
#define GPIO_PDOR_PDO11_SHIFT                    (11U)
/*! PDO11 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define GPIO_PDOR_PDO11(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO11_SHIFT)) & GPIO_PDOR_PDO11_MASK)

#define GPIO_PDOR_PDO12_MASK                     (0x1000U)
#define GPIO_PDOR_PDO12_SHIFT                    (12U)
/*! PDO12 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define GPIO_PDOR_PDO12(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO12_SHIFT)) & GPIO_PDOR_PDO12_MASK)

#define GPIO_PDOR_PDO13_MASK                     (0x2000U)
#define GPIO_PDOR_PDO13_SHIFT                    (13U)
/*! PDO13 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define GPIO_PDOR_PDO13(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO13_SHIFT)) & GPIO_PDOR_PDO13_MASK)

#define GPIO_PDOR_PDO14_MASK                     (0x4000U)
#define GPIO_PDOR_PDO14_SHIFT                    (14U)
/*! PDO14 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define GPIO_PDOR_PDO14(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO14_SHIFT)) & GPIO_PDOR_PDO14_MASK)

#define GPIO_PDOR_PDO15_MASK                     (0x8000U)
#define GPIO_PDOR_PDO15_SHIFT                    (15U)
/*! PDO15 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define GPIO_PDOR_PDO15(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO15_SHIFT)) & GPIO_PDOR_PDO15_MASK)

#define GPIO_PDOR_PDO16_MASK                     (0x10000U)
#define GPIO_PDOR_PDO16_SHIFT                    (16U)
/*! PDO16 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define GPIO_PDOR_PDO16(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO16_SHIFT)) & GPIO_PDOR_PDO16_MASK)

#define GPIO_PDOR_PDO17_MASK                     (0x20000U)
#define GPIO_PDOR_PDO17_SHIFT                    (17U)
/*! PDO17 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define GPIO_PDOR_PDO17(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO17_SHIFT)) & GPIO_PDOR_PDO17_MASK)

#define GPIO_PDOR_PDO18_MASK                     (0x40000U)
#define GPIO_PDOR_PDO18_SHIFT                    (18U)
/*! PDO18 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define GPIO_PDOR_PDO18(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO18_SHIFT)) & GPIO_PDOR_PDO18_MASK)

#define GPIO_PDOR_PDO19_MASK                     (0x80000U)
#define GPIO_PDOR_PDO19_SHIFT                    (19U)
/*! PDO19 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define GPIO_PDOR_PDO19(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO19_SHIFT)) & GPIO_PDOR_PDO19_MASK)

#define GPIO_PDOR_PDO20_MASK                     (0x100000U)
#define GPIO_PDOR_PDO20_SHIFT                    (20U)
/*! PDO20 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define GPIO_PDOR_PDO20(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO20_SHIFT)) & GPIO_PDOR_PDO20_MASK)

#define GPIO_PDOR_PDO21_MASK                     (0x200000U)
#define GPIO_PDOR_PDO21_SHIFT                    (21U)
/*! PDO21 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define GPIO_PDOR_PDO21(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO21_SHIFT)) & GPIO_PDOR_PDO21_MASK)

#define GPIO_PDOR_PDO22_MASK                     (0x400000U)
#define GPIO_PDOR_PDO22_SHIFT                    (22U)
/*! PDO22 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define GPIO_PDOR_PDO22(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO22_SHIFT)) & GPIO_PDOR_PDO22_MASK)

#define GPIO_PDOR_PDO23_MASK                     (0x800000U)
#define GPIO_PDOR_PDO23_SHIFT                    (23U)
/*! PDO23 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define GPIO_PDOR_PDO23(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO23_SHIFT)) & GPIO_PDOR_PDO23_MASK)

#define GPIO_PDOR_PDO24_MASK                     (0x1000000U)
#define GPIO_PDOR_PDO24_SHIFT                    (24U)
/*! PDO24 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define GPIO_PDOR_PDO24(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO24_SHIFT)) & GPIO_PDOR_PDO24_MASK)

#define GPIO_PDOR_PDO25_MASK                     (0x2000000U)
#define GPIO_PDOR_PDO25_SHIFT                    (25U)
/*! PDO25 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define GPIO_PDOR_PDO25(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO25_SHIFT)) & GPIO_PDOR_PDO25_MASK)

#define GPIO_PDOR_PDO26_MASK                     (0x4000000U)
#define GPIO_PDOR_PDO26_SHIFT                    (26U)
/*! PDO26 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define GPIO_PDOR_PDO26(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO26_SHIFT)) & GPIO_PDOR_PDO26_MASK)

#define GPIO_PDOR_PDO27_MASK                     (0x8000000U)
#define GPIO_PDOR_PDO27_SHIFT                    (27U)
/*! PDO27 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define GPIO_PDOR_PDO27(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO27_SHIFT)) & GPIO_PDOR_PDO27_MASK)

#define GPIO_PDOR_PDO28_MASK                     (0x10000000U)
#define GPIO_PDOR_PDO28_SHIFT                    (28U)
/*! PDO28 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define GPIO_PDOR_PDO28(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO28_SHIFT)) & GPIO_PDOR_PDO28_MASK)

#define GPIO_PDOR_PDO29_MASK                     (0x20000000U)
#define GPIO_PDOR_PDO29_SHIFT                    (29U)
/*! PDO29 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define GPIO_PDOR_PDO29(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO29_SHIFT)) & GPIO_PDOR_PDO29_MASK)

#define GPIO_PDOR_PDO30_MASK                     (0x40000000U)
#define GPIO_PDOR_PDO30_SHIFT                    (30U)
/*! PDO30 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define GPIO_PDOR_PDO30(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO30_SHIFT)) & GPIO_PDOR_PDO30_MASK)

#define GPIO_PDOR_PDO31_MASK                     (0x80000000U)
#define GPIO_PDOR_PDO31_SHIFT                    (31U)
/*! PDO31 - Port Data Output
 *  0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
 *  0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
 */
#define GPIO_PDOR_PDO31(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO31_SHIFT)) & GPIO_PDOR_PDO31_MASK)
/*! @} */

/*! @name PSOR - Port Set Output Register */
/*! @{ */

#define GPIO_PSOR_PTSO0_MASK                     (0x1U)
#define GPIO_PSOR_PTSO0_SHIFT                    (0U)
/*! PTSO0 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define GPIO_PSOR_PTSO0(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO0_SHIFT)) & GPIO_PSOR_PTSO0_MASK)

#define GPIO_PSOR_PTSO1_MASK                     (0x2U)
#define GPIO_PSOR_PTSO1_SHIFT                    (1U)
/*! PTSO1 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define GPIO_PSOR_PTSO1(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO1_SHIFT)) & GPIO_PSOR_PTSO1_MASK)

#define GPIO_PSOR_PTSO2_MASK                     (0x4U)
#define GPIO_PSOR_PTSO2_SHIFT                    (2U)
/*! PTSO2 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define GPIO_PSOR_PTSO2(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO2_SHIFT)) & GPIO_PSOR_PTSO2_MASK)

#define GPIO_PSOR_PTSO3_MASK                     (0x8U)
#define GPIO_PSOR_PTSO3_SHIFT                    (3U)
/*! PTSO3 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define GPIO_PSOR_PTSO3(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO3_SHIFT)) & GPIO_PSOR_PTSO3_MASK)

#define GPIO_PSOR_PTSO4_MASK                     (0x10U)
#define GPIO_PSOR_PTSO4_SHIFT                    (4U)
/*! PTSO4 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define GPIO_PSOR_PTSO4(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO4_SHIFT)) & GPIO_PSOR_PTSO4_MASK)

#define GPIO_PSOR_PTSO5_MASK                     (0x20U)
#define GPIO_PSOR_PTSO5_SHIFT                    (5U)
/*! PTSO5 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define GPIO_PSOR_PTSO5(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO5_SHIFT)) & GPIO_PSOR_PTSO5_MASK)

#define GPIO_PSOR_PTSO6_MASK                     (0x40U)
#define GPIO_PSOR_PTSO6_SHIFT                    (6U)
/*! PTSO6 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define GPIO_PSOR_PTSO6(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO6_SHIFT)) & GPIO_PSOR_PTSO6_MASK)

#define GPIO_PSOR_PTSO7_MASK                     (0x80U)
#define GPIO_PSOR_PTSO7_SHIFT                    (7U)
/*! PTSO7 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define GPIO_PSOR_PTSO7(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO7_SHIFT)) & GPIO_PSOR_PTSO7_MASK)

#define GPIO_PSOR_PTSO8_MASK                     (0x100U)
#define GPIO_PSOR_PTSO8_SHIFT                    (8U)
/*! PTSO8 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define GPIO_PSOR_PTSO8(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO8_SHIFT)) & GPIO_PSOR_PTSO8_MASK)

#define GPIO_PSOR_PTSO9_MASK                     (0x200U)
#define GPIO_PSOR_PTSO9_SHIFT                    (9U)
/*! PTSO9 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define GPIO_PSOR_PTSO9(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO9_SHIFT)) & GPIO_PSOR_PTSO9_MASK)

#define GPIO_PSOR_PTSO10_MASK                    (0x400U)
#define GPIO_PSOR_PTSO10_SHIFT                   (10U)
/*! PTSO10 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define GPIO_PSOR_PTSO10(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO10_SHIFT)) & GPIO_PSOR_PTSO10_MASK)

#define GPIO_PSOR_PTSO11_MASK                    (0x800U)
#define GPIO_PSOR_PTSO11_SHIFT                   (11U)
/*! PTSO11 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define GPIO_PSOR_PTSO11(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO11_SHIFT)) & GPIO_PSOR_PTSO11_MASK)

#define GPIO_PSOR_PTSO12_MASK                    (0x1000U)
#define GPIO_PSOR_PTSO12_SHIFT                   (12U)
/*! PTSO12 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define GPIO_PSOR_PTSO12(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO12_SHIFT)) & GPIO_PSOR_PTSO12_MASK)

#define GPIO_PSOR_PTSO13_MASK                    (0x2000U)
#define GPIO_PSOR_PTSO13_SHIFT                   (13U)
/*! PTSO13 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define GPIO_PSOR_PTSO13(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO13_SHIFT)) & GPIO_PSOR_PTSO13_MASK)

#define GPIO_PSOR_PTSO14_MASK                    (0x4000U)
#define GPIO_PSOR_PTSO14_SHIFT                   (14U)
/*! PTSO14 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define GPIO_PSOR_PTSO14(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO14_SHIFT)) & GPIO_PSOR_PTSO14_MASK)

#define GPIO_PSOR_PTSO15_MASK                    (0x8000U)
#define GPIO_PSOR_PTSO15_SHIFT                   (15U)
/*! PTSO15 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define GPIO_PSOR_PTSO15(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO15_SHIFT)) & GPIO_PSOR_PTSO15_MASK)

#define GPIO_PSOR_PTSO16_MASK                    (0x10000U)
#define GPIO_PSOR_PTSO16_SHIFT                   (16U)
/*! PTSO16 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define GPIO_PSOR_PTSO16(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO16_SHIFT)) & GPIO_PSOR_PTSO16_MASK)

#define GPIO_PSOR_PTSO17_MASK                    (0x20000U)
#define GPIO_PSOR_PTSO17_SHIFT                   (17U)
/*! PTSO17 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define GPIO_PSOR_PTSO17(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO17_SHIFT)) & GPIO_PSOR_PTSO17_MASK)

#define GPIO_PSOR_PTSO18_MASK                    (0x40000U)
#define GPIO_PSOR_PTSO18_SHIFT                   (18U)
/*! PTSO18 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define GPIO_PSOR_PTSO18(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO18_SHIFT)) & GPIO_PSOR_PTSO18_MASK)

#define GPIO_PSOR_PTSO19_MASK                    (0x80000U)
#define GPIO_PSOR_PTSO19_SHIFT                   (19U)
/*! PTSO19 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define GPIO_PSOR_PTSO19(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO19_SHIFT)) & GPIO_PSOR_PTSO19_MASK)

#define GPIO_PSOR_PTSO20_MASK                    (0x100000U)
#define GPIO_PSOR_PTSO20_SHIFT                   (20U)
/*! PTSO20 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define GPIO_PSOR_PTSO20(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO20_SHIFT)) & GPIO_PSOR_PTSO20_MASK)

#define GPIO_PSOR_PTSO21_MASK                    (0x200000U)
#define GPIO_PSOR_PTSO21_SHIFT                   (21U)
/*! PTSO21 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define GPIO_PSOR_PTSO21(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO21_SHIFT)) & GPIO_PSOR_PTSO21_MASK)

#define GPIO_PSOR_PTSO22_MASK                    (0x400000U)
#define GPIO_PSOR_PTSO22_SHIFT                   (22U)
/*! PTSO22 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define GPIO_PSOR_PTSO22(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO22_SHIFT)) & GPIO_PSOR_PTSO22_MASK)

#define GPIO_PSOR_PTSO23_MASK                    (0x800000U)
#define GPIO_PSOR_PTSO23_SHIFT                   (23U)
/*! PTSO23 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define GPIO_PSOR_PTSO23(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO23_SHIFT)) & GPIO_PSOR_PTSO23_MASK)

#define GPIO_PSOR_PTSO24_MASK                    (0x1000000U)
#define GPIO_PSOR_PTSO24_SHIFT                   (24U)
/*! PTSO24 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define GPIO_PSOR_PTSO24(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO24_SHIFT)) & GPIO_PSOR_PTSO24_MASK)

#define GPIO_PSOR_PTSO25_MASK                    (0x2000000U)
#define GPIO_PSOR_PTSO25_SHIFT                   (25U)
/*! PTSO25 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define GPIO_PSOR_PTSO25(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO25_SHIFT)) & GPIO_PSOR_PTSO25_MASK)

#define GPIO_PSOR_PTSO26_MASK                    (0x4000000U)
#define GPIO_PSOR_PTSO26_SHIFT                   (26U)
/*! PTSO26 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define GPIO_PSOR_PTSO26(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO26_SHIFT)) & GPIO_PSOR_PTSO26_MASK)

#define GPIO_PSOR_PTSO27_MASK                    (0x8000000U)
#define GPIO_PSOR_PTSO27_SHIFT                   (27U)
/*! PTSO27 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define GPIO_PSOR_PTSO27(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO27_SHIFT)) & GPIO_PSOR_PTSO27_MASK)

#define GPIO_PSOR_PTSO28_MASK                    (0x10000000U)
#define GPIO_PSOR_PTSO28_SHIFT                   (28U)
/*! PTSO28 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define GPIO_PSOR_PTSO28(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO28_SHIFT)) & GPIO_PSOR_PTSO28_MASK)

#define GPIO_PSOR_PTSO29_MASK                    (0x20000000U)
#define GPIO_PSOR_PTSO29_SHIFT                   (29U)
/*! PTSO29 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define GPIO_PSOR_PTSO29(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO29_SHIFT)) & GPIO_PSOR_PTSO29_MASK)

#define GPIO_PSOR_PTSO30_MASK                    (0x40000000U)
#define GPIO_PSOR_PTSO30_SHIFT                   (30U)
/*! PTSO30 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define GPIO_PSOR_PTSO30(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO30_SHIFT)) & GPIO_PSOR_PTSO30_MASK)

#define GPIO_PSOR_PTSO31_MASK                    (0x80000000U)
#define GPIO_PSOR_PTSO31_SHIFT                   (31U)
/*! PTSO31 - Port Set Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to logic 1.
 */
#define GPIO_PSOR_PTSO31(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO31_SHIFT)) & GPIO_PSOR_PTSO31_MASK)
/*! @} */

/*! @name PCOR - Port Clear Output Register */
/*! @{ */

#define GPIO_PCOR_PTCO0_MASK                     (0x1U)
#define GPIO_PCOR_PTCO0_SHIFT                    (0U)
/*! PTCO0 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define GPIO_PCOR_PTCO0(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO0_SHIFT)) & GPIO_PCOR_PTCO0_MASK)

#define GPIO_PCOR_PTCO1_MASK                     (0x2U)
#define GPIO_PCOR_PTCO1_SHIFT                    (1U)
/*! PTCO1 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define GPIO_PCOR_PTCO1(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO1_SHIFT)) & GPIO_PCOR_PTCO1_MASK)

#define GPIO_PCOR_PTCO2_MASK                     (0x4U)
#define GPIO_PCOR_PTCO2_SHIFT                    (2U)
/*! PTCO2 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define GPIO_PCOR_PTCO2(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO2_SHIFT)) & GPIO_PCOR_PTCO2_MASK)

#define GPIO_PCOR_PTCO3_MASK                     (0x8U)
#define GPIO_PCOR_PTCO3_SHIFT                    (3U)
/*! PTCO3 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define GPIO_PCOR_PTCO3(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO3_SHIFT)) & GPIO_PCOR_PTCO3_MASK)

#define GPIO_PCOR_PTCO4_MASK                     (0x10U)
#define GPIO_PCOR_PTCO4_SHIFT                    (4U)
/*! PTCO4 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define GPIO_PCOR_PTCO4(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO4_SHIFT)) & GPIO_PCOR_PTCO4_MASK)

#define GPIO_PCOR_PTCO5_MASK                     (0x20U)
#define GPIO_PCOR_PTCO5_SHIFT                    (5U)
/*! PTCO5 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define GPIO_PCOR_PTCO5(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO5_SHIFT)) & GPIO_PCOR_PTCO5_MASK)

#define GPIO_PCOR_PTCO6_MASK                     (0x40U)
#define GPIO_PCOR_PTCO6_SHIFT                    (6U)
/*! PTCO6 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define GPIO_PCOR_PTCO6(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO6_SHIFT)) & GPIO_PCOR_PTCO6_MASK)

#define GPIO_PCOR_PTCO7_MASK                     (0x80U)
#define GPIO_PCOR_PTCO7_SHIFT                    (7U)
/*! PTCO7 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define GPIO_PCOR_PTCO7(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO7_SHIFT)) & GPIO_PCOR_PTCO7_MASK)

#define GPIO_PCOR_PTCO8_MASK                     (0x100U)
#define GPIO_PCOR_PTCO8_SHIFT                    (8U)
/*! PTCO8 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define GPIO_PCOR_PTCO8(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO8_SHIFT)) & GPIO_PCOR_PTCO8_MASK)

#define GPIO_PCOR_PTCO9_MASK                     (0x200U)
#define GPIO_PCOR_PTCO9_SHIFT                    (9U)
/*! PTCO9 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define GPIO_PCOR_PTCO9(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO9_SHIFT)) & GPIO_PCOR_PTCO9_MASK)

#define GPIO_PCOR_PTCO10_MASK                    (0x400U)
#define GPIO_PCOR_PTCO10_SHIFT                   (10U)
/*! PTCO10 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define GPIO_PCOR_PTCO10(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO10_SHIFT)) & GPIO_PCOR_PTCO10_MASK)

#define GPIO_PCOR_PTCO11_MASK                    (0x800U)
#define GPIO_PCOR_PTCO11_SHIFT                   (11U)
/*! PTCO11 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define GPIO_PCOR_PTCO11(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO11_SHIFT)) & GPIO_PCOR_PTCO11_MASK)

#define GPIO_PCOR_PTCO12_MASK                    (0x1000U)
#define GPIO_PCOR_PTCO12_SHIFT                   (12U)
/*! PTCO12 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define GPIO_PCOR_PTCO12(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO12_SHIFT)) & GPIO_PCOR_PTCO12_MASK)

#define GPIO_PCOR_PTCO13_MASK                    (0x2000U)
#define GPIO_PCOR_PTCO13_SHIFT                   (13U)
/*! PTCO13 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define GPIO_PCOR_PTCO13(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO13_SHIFT)) & GPIO_PCOR_PTCO13_MASK)

#define GPIO_PCOR_PTCO14_MASK                    (0x4000U)
#define GPIO_PCOR_PTCO14_SHIFT                   (14U)
/*! PTCO14 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define GPIO_PCOR_PTCO14(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO14_SHIFT)) & GPIO_PCOR_PTCO14_MASK)

#define GPIO_PCOR_PTCO15_MASK                    (0x8000U)
#define GPIO_PCOR_PTCO15_SHIFT                   (15U)
/*! PTCO15 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define GPIO_PCOR_PTCO15(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO15_SHIFT)) & GPIO_PCOR_PTCO15_MASK)

#define GPIO_PCOR_PTCO16_MASK                    (0x10000U)
#define GPIO_PCOR_PTCO16_SHIFT                   (16U)
/*! PTCO16 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define GPIO_PCOR_PTCO16(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO16_SHIFT)) & GPIO_PCOR_PTCO16_MASK)

#define GPIO_PCOR_PTCO17_MASK                    (0x20000U)
#define GPIO_PCOR_PTCO17_SHIFT                   (17U)
/*! PTCO17 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define GPIO_PCOR_PTCO17(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO17_SHIFT)) & GPIO_PCOR_PTCO17_MASK)

#define GPIO_PCOR_PTCO18_MASK                    (0x40000U)
#define GPIO_PCOR_PTCO18_SHIFT                   (18U)
/*! PTCO18 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define GPIO_PCOR_PTCO18(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO18_SHIFT)) & GPIO_PCOR_PTCO18_MASK)

#define GPIO_PCOR_PTCO19_MASK                    (0x80000U)
#define GPIO_PCOR_PTCO19_SHIFT                   (19U)
/*! PTCO19 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define GPIO_PCOR_PTCO19(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO19_SHIFT)) & GPIO_PCOR_PTCO19_MASK)

#define GPIO_PCOR_PTCO20_MASK                    (0x100000U)
#define GPIO_PCOR_PTCO20_SHIFT                   (20U)
/*! PTCO20 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define GPIO_PCOR_PTCO20(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO20_SHIFT)) & GPIO_PCOR_PTCO20_MASK)

#define GPIO_PCOR_PTCO21_MASK                    (0x200000U)
#define GPIO_PCOR_PTCO21_SHIFT                   (21U)
/*! PTCO21 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define GPIO_PCOR_PTCO21(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO21_SHIFT)) & GPIO_PCOR_PTCO21_MASK)

#define GPIO_PCOR_PTCO22_MASK                    (0x400000U)
#define GPIO_PCOR_PTCO22_SHIFT                   (22U)
/*! PTCO22 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define GPIO_PCOR_PTCO22(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO22_SHIFT)) & GPIO_PCOR_PTCO22_MASK)

#define GPIO_PCOR_PTCO23_MASK                    (0x800000U)
#define GPIO_PCOR_PTCO23_SHIFT                   (23U)
/*! PTCO23 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define GPIO_PCOR_PTCO23(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO23_SHIFT)) & GPIO_PCOR_PTCO23_MASK)

#define GPIO_PCOR_PTCO24_MASK                    (0x1000000U)
#define GPIO_PCOR_PTCO24_SHIFT                   (24U)
/*! PTCO24 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define GPIO_PCOR_PTCO24(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO24_SHIFT)) & GPIO_PCOR_PTCO24_MASK)

#define GPIO_PCOR_PTCO25_MASK                    (0x2000000U)
#define GPIO_PCOR_PTCO25_SHIFT                   (25U)
/*! PTCO25 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define GPIO_PCOR_PTCO25(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO25_SHIFT)) & GPIO_PCOR_PTCO25_MASK)

#define GPIO_PCOR_PTCO26_MASK                    (0x4000000U)
#define GPIO_PCOR_PTCO26_SHIFT                   (26U)
/*! PTCO26 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define GPIO_PCOR_PTCO26(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO26_SHIFT)) & GPIO_PCOR_PTCO26_MASK)

#define GPIO_PCOR_PTCO27_MASK                    (0x8000000U)
#define GPIO_PCOR_PTCO27_SHIFT                   (27U)
/*! PTCO27 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define GPIO_PCOR_PTCO27(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO27_SHIFT)) & GPIO_PCOR_PTCO27_MASK)

#define GPIO_PCOR_PTCO28_MASK                    (0x10000000U)
#define GPIO_PCOR_PTCO28_SHIFT                   (28U)
/*! PTCO28 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define GPIO_PCOR_PTCO28(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO28_SHIFT)) & GPIO_PCOR_PTCO28_MASK)

#define GPIO_PCOR_PTCO29_MASK                    (0x20000000U)
#define GPIO_PCOR_PTCO29_SHIFT                   (29U)
/*! PTCO29 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define GPIO_PCOR_PTCO29(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO29_SHIFT)) & GPIO_PCOR_PTCO29_MASK)

#define GPIO_PCOR_PTCO30_MASK                    (0x40000000U)
#define GPIO_PCOR_PTCO30_SHIFT                   (30U)
/*! PTCO30 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define GPIO_PCOR_PTCO30(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO30_SHIFT)) & GPIO_PCOR_PTCO30_MASK)

#define GPIO_PCOR_PTCO31_MASK                    (0x80000000U)
#define GPIO_PCOR_PTCO31_SHIFT                   (31U)
/*! PTCO31 - Port Clear Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is cleared to logic 0.
 */
#define GPIO_PCOR_PTCO31(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO31_SHIFT)) & GPIO_PCOR_PTCO31_MASK)
/*! @} */

/*! @name PTOR - Port Toggle Output Register */
/*! @{ */

#define GPIO_PTOR_PTTO0_MASK                     (0x1U)
#define GPIO_PTOR_PTTO0_SHIFT                    (0U)
/*! PTTO0 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
 */
#define GPIO_PTOR_PTTO0(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO0_SHIFT)) & GPIO_PTOR_PTTO0_MASK)

#define GPIO_PTOR_PTTO1_MASK                     (0x2U)
#define GPIO_PTOR_PTTO1_SHIFT                    (1U)
/*! PTTO1 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
 */
#define GPIO_PTOR_PTTO1(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO1_SHIFT)) & GPIO_PTOR_PTTO1_MASK)

#define GPIO_PTOR_PTTO2_MASK                     (0x4U)
#define GPIO_PTOR_PTTO2_SHIFT                    (2U)
/*! PTTO2 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
 */
#define GPIO_PTOR_PTTO2(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO2_SHIFT)) & GPIO_PTOR_PTTO2_MASK)

#define GPIO_PTOR_PTTO3_MASK                     (0x8U)
#define GPIO_PTOR_PTTO3_SHIFT                    (3U)
/*! PTTO3 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
 */
#define GPIO_PTOR_PTTO3(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO3_SHIFT)) & GPIO_PTOR_PTTO3_MASK)

#define GPIO_PTOR_PTTO4_MASK                     (0x10U)
#define GPIO_PTOR_PTTO4_SHIFT                    (4U)
/*! PTTO4 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
 */
#define GPIO_PTOR_PTTO4(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO4_SHIFT)) & GPIO_PTOR_PTTO4_MASK)

#define GPIO_PTOR_PTTO5_MASK                     (0x20U)
#define GPIO_PTOR_PTTO5_SHIFT                    (5U)
/*! PTTO5 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
 */
#define GPIO_PTOR_PTTO5(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO5_SHIFT)) & GPIO_PTOR_PTTO5_MASK)

#define GPIO_PTOR_PTTO6_MASK                     (0x40U)
#define GPIO_PTOR_PTTO6_SHIFT                    (6U)
/*! PTTO6 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
 */
#define GPIO_PTOR_PTTO6(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO6_SHIFT)) & GPIO_PTOR_PTTO6_MASK)

#define GPIO_PTOR_PTTO7_MASK                     (0x80U)
#define GPIO_PTOR_PTTO7_SHIFT                    (7U)
/*! PTTO7 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
 */
#define GPIO_PTOR_PTTO7(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO7_SHIFT)) & GPIO_PTOR_PTTO7_MASK)

#define GPIO_PTOR_PTTO8_MASK                     (0x100U)
#define GPIO_PTOR_PTTO8_SHIFT                    (8U)
/*! PTTO8 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
 */
#define GPIO_PTOR_PTTO8(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO8_SHIFT)) & GPIO_PTOR_PTTO8_MASK)

#define GPIO_PTOR_PTTO9_MASK                     (0x200U)
#define GPIO_PTOR_PTTO9_SHIFT                    (9U)
/*! PTTO9 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
 */
#define GPIO_PTOR_PTTO9(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO9_SHIFT)) & GPIO_PTOR_PTTO9_MASK)

#define GPIO_PTOR_PTTO10_MASK                    (0x400U)
#define GPIO_PTOR_PTTO10_SHIFT                   (10U)
/*! PTTO10 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
 */
#define GPIO_PTOR_PTTO10(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO10_SHIFT)) & GPIO_PTOR_PTTO10_MASK)

#define GPIO_PTOR_PTTO11_MASK                    (0x800U)
#define GPIO_PTOR_PTTO11_SHIFT                   (11U)
/*! PTTO11 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
 */
#define GPIO_PTOR_PTTO11(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO11_SHIFT)) & GPIO_PTOR_PTTO11_MASK)

#define GPIO_PTOR_PTTO12_MASK                    (0x1000U)
#define GPIO_PTOR_PTTO12_SHIFT                   (12U)
/*! PTTO12 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
 */
#define GPIO_PTOR_PTTO12(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO12_SHIFT)) & GPIO_PTOR_PTTO12_MASK)

#define GPIO_PTOR_PTTO13_MASK                    (0x2000U)
#define GPIO_PTOR_PTTO13_SHIFT                   (13U)
/*! PTTO13 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
 */
#define GPIO_PTOR_PTTO13(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO13_SHIFT)) & GPIO_PTOR_PTTO13_MASK)

#define GPIO_PTOR_PTTO14_MASK                    (0x4000U)
#define GPIO_PTOR_PTTO14_SHIFT                   (14U)
/*! PTTO14 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
 */
#define GPIO_PTOR_PTTO14(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO14_SHIFT)) & GPIO_PTOR_PTTO14_MASK)

#define GPIO_PTOR_PTTO15_MASK                    (0x8000U)
#define GPIO_PTOR_PTTO15_SHIFT                   (15U)
/*! PTTO15 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
 */
#define GPIO_PTOR_PTTO15(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO15_SHIFT)) & GPIO_PTOR_PTTO15_MASK)

#define GPIO_PTOR_PTTO16_MASK                    (0x10000U)
#define GPIO_PTOR_PTTO16_SHIFT                   (16U)
/*! PTTO16 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
 */
#define GPIO_PTOR_PTTO16(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO16_SHIFT)) & GPIO_PTOR_PTTO16_MASK)

#define GPIO_PTOR_PTTO17_MASK                    (0x20000U)
#define GPIO_PTOR_PTTO17_SHIFT                   (17U)
/*! PTTO17 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
 */
#define GPIO_PTOR_PTTO17(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO17_SHIFT)) & GPIO_PTOR_PTTO17_MASK)

#define GPIO_PTOR_PTTO18_MASK                    (0x40000U)
#define GPIO_PTOR_PTTO18_SHIFT                   (18U)
/*! PTTO18 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
 */
#define GPIO_PTOR_PTTO18(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO18_SHIFT)) & GPIO_PTOR_PTTO18_MASK)

#define GPIO_PTOR_PTTO19_MASK                    (0x80000U)
#define GPIO_PTOR_PTTO19_SHIFT                   (19U)
/*! PTTO19 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
 */
#define GPIO_PTOR_PTTO19(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO19_SHIFT)) & GPIO_PTOR_PTTO19_MASK)

#define GPIO_PTOR_PTTO20_MASK                    (0x100000U)
#define GPIO_PTOR_PTTO20_SHIFT                   (20U)
/*! PTTO20 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
 */
#define GPIO_PTOR_PTTO20(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO20_SHIFT)) & GPIO_PTOR_PTTO20_MASK)

#define GPIO_PTOR_PTTO21_MASK                    (0x200000U)
#define GPIO_PTOR_PTTO21_SHIFT                   (21U)
/*! PTTO21 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
 */
#define GPIO_PTOR_PTTO21(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO21_SHIFT)) & GPIO_PTOR_PTTO21_MASK)

#define GPIO_PTOR_PTTO22_MASK                    (0x400000U)
#define GPIO_PTOR_PTTO22_SHIFT                   (22U)
/*! PTTO22 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
 */
#define GPIO_PTOR_PTTO22(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO22_SHIFT)) & GPIO_PTOR_PTTO22_MASK)

#define GPIO_PTOR_PTTO23_MASK                    (0x800000U)
#define GPIO_PTOR_PTTO23_SHIFT                   (23U)
/*! PTTO23 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
 */
#define GPIO_PTOR_PTTO23(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO23_SHIFT)) & GPIO_PTOR_PTTO23_MASK)

#define GPIO_PTOR_PTTO24_MASK                    (0x1000000U)
#define GPIO_PTOR_PTTO24_SHIFT                   (24U)
/*! PTTO24 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
 */
#define GPIO_PTOR_PTTO24(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO24_SHIFT)) & GPIO_PTOR_PTTO24_MASK)

#define GPIO_PTOR_PTTO25_MASK                    (0x2000000U)
#define GPIO_PTOR_PTTO25_SHIFT                   (25U)
/*! PTTO25 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
 */
#define GPIO_PTOR_PTTO25(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO25_SHIFT)) & GPIO_PTOR_PTTO25_MASK)

#define GPIO_PTOR_PTTO26_MASK                    (0x4000000U)
#define GPIO_PTOR_PTTO26_SHIFT                   (26U)
/*! PTTO26 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
 */
#define GPIO_PTOR_PTTO26(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO26_SHIFT)) & GPIO_PTOR_PTTO26_MASK)

#define GPIO_PTOR_PTTO27_MASK                    (0x8000000U)
#define GPIO_PTOR_PTTO27_SHIFT                   (27U)
/*! PTTO27 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
 */
#define GPIO_PTOR_PTTO27(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO27_SHIFT)) & GPIO_PTOR_PTTO27_MASK)

#define GPIO_PTOR_PTTO28_MASK                    (0x10000000U)
#define GPIO_PTOR_PTTO28_SHIFT                   (28U)
/*! PTTO28 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
 */
#define GPIO_PTOR_PTTO28(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO28_SHIFT)) & GPIO_PTOR_PTTO28_MASK)

#define GPIO_PTOR_PTTO29_MASK                    (0x20000000U)
#define GPIO_PTOR_PTTO29_SHIFT                   (29U)
/*! PTTO29 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
 */
#define GPIO_PTOR_PTTO29(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO29_SHIFT)) & GPIO_PTOR_PTTO29_MASK)

#define GPIO_PTOR_PTTO30_MASK                    (0x40000000U)
#define GPIO_PTOR_PTTO30_SHIFT                   (30U)
/*! PTTO30 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
 */
#define GPIO_PTOR_PTTO30(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO30_SHIFT)) & GPIO_PTOR_PTTO30_MASK)

#define GPIO_PTOR_PTTO31_MASK                    (0x80000000U)
#define GPIO_PTOR_PTTO31_SHIFT                   (31U)
/*! PTTO31 - Port Toggle Output
 *  0b0..Corresponding field of PDOR[PDOn] does not change.
 *  0b1..Corresponding field of PDOR[PDOn] is set to the inverse of its current logic state.
 */
#define GPIO_PTOR_PTTO31(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO31_SHIFT)) & GPIO_PTOR_PTTO31_MASK)
/*! @} */

/*! @name PDIR - Port Data Input Register */
/*! @{ */

#define GPIO_PDIR_PDI0_MASK                      (0x1U)
#define GPIO_PDIR_PDI0_SHIFT                     (0U)
/*! PDI0 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define GPIO_PDIR_PDI0(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI0_SHIFT)) & GPIO_PDIR_PDI0_MASK)

#define GPIO_PDIR_PDI1_MASK                      (0x2U)
#define GPIO_PDIR_PDI1_SHIFT                     (1U)
/*! PDI1 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define GPIO_PDIR_PDI1(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI1_SHIFT)) & GPIO_PDIR_PDI1_MASK)

#define GPIO_PDIR_PDI2_MASK                      (0x4U)
#define GPIO_PDIR_PDI2_SHIFT                     (2U)
/*! PDI2 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define GPIO_PDIR_PDI2(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI2_SHIFT)) & GPIO_PDIR_PDI2_MASK)

#define GPIO_PDIR_PDI3_MASK                      (0x8U)
#define GPIO_PDIR_PDI3_SHIFT                     (3U)
/*! PDI3 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define GPIO_PDIR_PDI3(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI3_SHIFT)) & GPIO_PDIR_PDI3_MASK)

#define GPIO_PDIR_PDI4_MASK                      (0x10U)
#define GPIO_PDIR_PDI4_SHIFT                     (4U)
/*! PDI4 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define GPIO_PDIR_PDI4(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI4_SHIFT)) & GPIO_PDIR_PDI4_MASK)

#define GPIO_PDIR_PDI5_MASK                      (0x20U)
#define GPIO_PDIR_PDI5_SHIFT                     (5U)
/*! PDI5 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define GPIO_PDIR_PDI5(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI5_SHIFT)) & GPIO_PDIR_PDI5_MASK)

#define GPIO_PDIR_PDI6_MASK                      (0x40U)
#define GPIO_PDIR_PDI6_SHIFT                     (6U)
/*! PDI6 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define GPIO_PDIR_PDI6(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI6_SHIFT)) & GPIO_PDIR_PDI6_MASK)

#define GPIO_PDIR_PDI7_MASK                      (0x80U)
#define GPIO_PDIR_PDI7_SHIFT                     (7U)
/*! PDI7 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define GPIO_PDIR_PDI7(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI7_SHIFT)) & GPIO_PDIR_PDI7_MASK)

#define GPIO_PDIR_PDI8_MASK                      (0x100U)
#define GPIO_PDIR_PDI8_SHIFT                     (8U)
/*! PDI8 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define GPIO_PDIR_PDI8(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI8_SHIFT)) & GPIO_PDIR_PDI8_MASK)

#define GPIO_PDIR_PDI9_MASK                      (0x200U)
#define GPIO_PDIR_PDI9_SHIFT                     (9U)
/*! PDI9 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define GPIO_PDIR_PDI9(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI9_SHIFT)) & GPIO_PDIR_PDI9_MASK)

#define GPIO_PDIR_PDI10_MASK                     (0x400U)
#define GPIO_PDIR_PDI10_SHIFT                    (10U)
/*! PDI10 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define GPIO_PDIR_PDI10(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI10_SHIFT)) & GPIO_PDIR_PDI10_MASK)

#define GPIO_PDIR_PDI11_MASK                     (0x800U)
#define GPIO_PDIR_PDI11_SHIFT                    (11U)
/*! PDI11 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define GPIO_PDIR_PDI11(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI11_SHIFT)) & GPIO_PDIR_PDI11_MASK)

#define GPIO_PDIR_PDI12_MASK                     (0x1000U)
#define GPIO_PDIR_PDI12_SHIFT                    (12U)
/*! PDI12 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define GPIO_PDIR_PDI12(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI12_SHIFT)) & GPIO_PDIR_PDI12_MASK)

#define GPIO_PDIR_PDI13_MASK                     (0x2000U)
#define GPIO_PDIR_PDI13_SHIFT                    (13U)
/*! PDI13 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define GPIO_PDIR_PDI13(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI13_SHIFT)) & GPIO_PDIR_PDI13_MASK)

#define GPIO_PDIR_PDI14_MASK                     (0x4000U)
#define GPIO_PDIR_PDI14_SHIFT                    (14U)
/*! PDI14 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define GPIO_PDIR_PDI14(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI14_SHIFT)) & GPIO_PDIR_PDI14_MASK)

#define GPIO_PDIR_PDI15_MASK                     (0x8000U)
#define GPIO_PDIR_PDI15_SHIFT                    (15U)
/*! PDI15 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define GPIO_PDIR_PDI15(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI15_SHIFT)) & GPIO_PDIR_PDI15_MASK)

#define GPIO_PDIR_PDI16_MASK                     (0x10000U)
#define GPIO_PDIR_PDI16_SHIFT                    (16U)
/*! PDI16 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define GPIO_PDIR_PDI16(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI16_SHIFT)) & GPIO_PDIR_PDI16_MASK)

#define GPIO_PDIR_PDI17_MASK                     (0x20000U)
#define GPIO_PDIR_PDI17_SHIFT                    (17U)
/*! PDI17 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define GPIO_PDIR_PDI17(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI17_SHIFT)) & GPIO_PDIR_PDI17_MASK)

#define GPIO_PDIR_PDI18_MASK                     (0x40000U)
#define GPIO_PDIR_PDI18_SHIFT                    (18U)
/*! PDI18 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define GPIO_PDIR_PDI18(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI18_SHIFT)) & GPIO_PDIR_PDI18_MASK)

#define GPIO_PDIR_PDI19_MASK                     (0x80000U)
#define GPIO_PDIR_PDI19_SHIFT                    (19U)
/*! PDI19 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define GPIO_PDIR_PDI19(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI19_SHIFT)) & GPIO_PDIR_PDI19_MASK)

#define GPIO_PDIR_PDI20_MASK                     (0x100000U)
#define GPIO_PDIR_PDI20_SHIFT                    (20U)
/*! PDI20 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define GPIO_PDIR_PDI20(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI20_SHIFT)) & GPIO_PDIR_PDI20_MASK)

#define GPIO_PDIR_PDI21_MASK                     (0x200000U)
#define GPIO_PDIR_PDI21_SHIFT                    (21U)
/*! PDI21 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define GPIO_PDIR_PDI21(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI21_SHIFT)) & GPIO_PDIR_PDI21_MASK)

#define GPIO_PDIR_PDI22_MASK                     (0x400000U)
#define GPIO_PDIR_PDI22_SHIFT                    (22U)
/*! PDI22 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define GPIO_PDIR_PDI22(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI22_SHIFT)) & GPIO_PDIR_PDI22_MASK)

#define GPIO_PDIR_PDI23_MASK                     (0x800000U)
#define GPIO_PDIR_PDI23_SHIFT                    (23U)
/*! PDI23 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define GPIO_PDIR_PDI23(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI23_SHIFT)) & GPIO_PDIR_PDI23_MASK)

#define GPIO_PDIR_PDI24_MASK                     (0x1000000U)
#define GPIO_PDIR_PDI24_SHIFT                    (24U)
/*! PDI24 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define GPIO_PDIR_PDI24(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI24_SHIFT)) & GPIO_PDIR_PDI24_MASK)

#define GPIO_PDIR_PDI25_MASK                     (0x2000000U)
#define GPIO_PDIR_PDI25_SHIFT                    (25U)
/*! PDI25 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define GPIO_PDIR_PDI25(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI25_SHIFT)) & GPIO_PDIR_PDI25_MASK)

#define GPIO_PDIR_PDI26_MASK                     (0x4000000U)
#define GPIO_PDIR_PDI26_SHIFT                    (26U)
/*! PDI26 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define GPIO_PDIR_PDI26(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI26_SHIFT)) & GPIO_PDIR_PDI26_MASK)

#define GPIO_PDIR_PDI27_MASK                     (0x8000000U)
#define GPIO_PDIR_PDI27_SHIFT                    (27U)
/*! PDI27 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define GPIO_PDIR_PDI27(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI27_SHIFT)) & GPIO_PDIR_PDI27_MASK)

#define GPIO_PDIR_PDI28_MASK                     (0x10000000U)
#define GPIO_PDIR_PDI28_SHIFT                    (28U)
/*! PDI28 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define GPIO_PDIR_PDI28(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI28_SHIFT)) & GPIO_PDIR_PDI28_MASK)

#define GPIO_PDIR_PDI29_MASK                     (0x20000000U)
#define GPIO_PDIR_PDI29_SHIFT                    (29U)
/*! PDI29 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define GPIO_PDIR_PDI29(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI29_SHIFT)) & GPIO_PDIR_PDI29_MASK)

#define GPIO_PDIR_PDI30_MASK                     (0x40000000U)
#define GPIO_PDIR_PDI30_SHIFT                    (30U)
/*! PDI30 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define GPIO_PDIR_PDI30(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI30_SHIFT)) & GPIO_PDIR_PDI30_MASK)

#define GPIO_PDIR_PDI31_MASK                     (0x80000000U)
#define GPIO_PDIR_PDI31_SHIFT                    (31U)
/*! PDI31 - Port Data Input
 *  0b0..Pin logic level is logic 0, or is not configured for use by digital function.
 *  0b1..Pin logic level is logic 1.
 */
#define GPIO_PDIR_PDI31(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI31_SHIFT)) & GPIO_PDIR_PDI31_MASK)
/*! @} */

/*! @name PDDR - Port Data Direction Register */
/*! @{ */

#define GPIO_PDDR_PDD0_MASK                      (0x1U)
#define GPIO_PDDR_PDD0_SHIFT                     (0U)
/*! PDD0 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input for the GPIO function.
 *  0b1..Pin is configured as general-purpose output for the GPIO function.
 */
#define GPIO_PDDR_PDD0(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD0_SHIFT)) & GPIO_PDDR_PDD0_MASK)

#define GPIO_PDDR_PDD1_MASK                      (0x2U)
#define GPIO_PDDR_PDD1_SHIFT                     (1U)
/*! PDD1 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input for the GPIO function.
 *  0b1..Pin is configured as general-purpose output for the GPIO function.
 */
#define GPIO_PDDR_PDD1(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD1_SHIFT)) & GPIO_PDDR_PDD1_MASK)

#define GPIO_PDDR_PDD2_MASK                      (0x4U)
#define GPIO_PDDR_PDD2_SHIFT                     (2U)
/*! PDD2 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input for the GPIO function.
 *  0b1..Pin is configured as general-purpose output for the GPIO function.
 */
#define GPIO_PDDR_PDD2(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD2_SHIFT)) & GPIO_PDDR_PDD2_MASK)

#define GPIO_PDDR_PDD3_MASK                      (0x8U)
#define GPIO_PDDR_PDD3_SHIFT                     (3U)
/*! PDD3 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input for the GPIO function.
 *  0b1..Pin is configured as general-purpose output for the GPIO function.
 */
#define GPIO_PDDR_PDD3(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD3_SHIFT)) & GPIO_PDDR_PDD3_MASK)

#define GPIO_PDDR_PDD4_MASK                      (0x10U)
#define GPIO_PDDR_PDD4_SHIFT                     (4U)
/*! PDD4 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input for the GPIO function.
 *  0b1..Pin is configured as general-purpose output for the GPIO function.
 */
#define GPIO_PDDR_PDD4(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD4_SHIFT)) & GPIO_PDDR_PDD4_MASK)

#define GPIO_PDDR_PDD5_MASK                      (0x20U)
#define GPIO_PDDR_PDD5_SHIFT                     (5U)
/*! PDD5 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input for the GPIO function.
 *  0b1..Pin is configured as general-purpose output for the GPIO function.
 */
#define GPIO_PDDR_PDD5(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD5_SHIFT)) & GPIO_PDDR_PDD5_MASK)

#define GPIO_PDDR_PDD6_MASK                      (0x40U)
#define GPIO_PDDR_PDD6_SHIFT                     (6U)
/*! PDD6 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input for the GPIO function.
 *  0b1..Pin is configured as general-purpose output for the GPIO function.
 */
#define GPIO_PDDR_PDD6(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD6_SHIFT)) & GPIO_PDDR_PDD6_MASK)

#define GPIO_PDDR_PDD7_MASK                      (0x80U)
#define GPIO_PDDR_PDD7_SHIFT                     (7U)
/*! PDD7 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input for the GPIO function.
 *  0b1..Pin is configured as general-purpose output for the GPIO function.
 */
#define GPIO_PDDR_PDD7(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD7_SHIFT)) & GPIO_PDDR_PDD7_MASK)

#define GPIO_PDDR_PDD8_MASK                      (0x100U)
#define GPIO_PDDR_PDD8_SHIFT                     (8U)
/*! PDD8 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input for the GPIO function.
 *  0b1..Pin is configured as general-purpose output for the GPIO function.
 */
#define GPIO_PDDR_PDD8(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD8_SHIFT)) & GPIO_PDDR_PDD8_MASK)

#define GPIO_PDDR_PDD9_MASK                      (0x200U)
#define GPIO_PDDR_PDD9_SHIFT                     (9U)
/*! PDD9 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input for the GPIO function.
 *  0b1..Pin is configured as general-purpose output for the GPIO function.
 */
#define GPIO_PDDR_PDD9(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD9_SHIFT)) & GPIO_PDDR_PDD9_MASK)

#define GPIO_PDDR_PDD10_MASK                     (0x400U)
#define GPIO_PDDR_PDD10_SHIFT                    (10U)
/*! PDD10 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input for the GPIO function.
 *  0b1..Pin is configured as general-purpose output for the GPIO function.
 */
#define GPIO_PDDR_PDD10(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD10_SHIFT)) & GPIO_PDDR_PDD10_MASK)

#define GPIO_PDDR_PDD11_MASK                     (0x800U)
#define GPIO_PDDR_PDD11_SHIFT                    (11U)
/*! PDD11 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input for the GPIO function.
 *  0b1..Pin is configured as general-purpose output for the GPIO function.
 */
#define GPIO_PDDR_PDD11(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD11_SHIFT)) & GPIO_PDDR_PDD11_MASK)

#define GPIO_PDDR_PDD12_MASK                     (0x1000U)
#define GPIO_PDDR_PDD12_SHIFT                    (12U)
/*! PDD12 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input for the GPIO function.
 *  0b1..Pin is configured as general-purpose output for the GPIO function.
 */
#define GPIO_PDDR_PDD12(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD12_SHIFT)) & GPIO_PDDR_PDD12_MASK)

#define GPIO_PDDR_PDD13_MASK                     (0x2000U)
#define GPIO_PDDR_PDD13_SHIFT                    (13U)
/*! PDD13 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input for the GPIO function.
 *  0b1..Pin is configured as general-purpose output for the GPIO function.
 */
#define GPIO_PDDR_PDD13(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD13_SHIFT)) & GPIO_PDDR_PDD13_MASK)

#define GPIO_PDDR_PDD14_MASK                     (0x4000U)
#define GPIO_PDDR_PDD14_SHIFT                    (14U)
/*! PDD14 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input for the GPIO function.
 *  0b1..Pin is configured as general-purpose output for the GPIO function.
 */
#define GPIO_PDDR_PDD14(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD14_SHIFT)) & GPIO_PDDR_PDD14_MASK)

#define GPIO_PDDR_PDD15_MASK                     (0x8000U)
#define GPIO_PDDR_PDD15_SHIFT                    (15U)
/*! PDD15 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input for the GPIO function.
 *  0b1..Pin is configured as general-purpose output for the GPIO function.
 */
#define GPIO_PDDR_PDD15(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD15_SHIFT)) & GPIO_PDDR_PDD15_MASK)

#define GPIO_PDDR_PDD16_MASK                     (0x10000U)
#define GPIO_PDDR_PDD16_SHIFT                    (16U)
/*! PDD16 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input for the GPIO function.
 *  0b1..Pin is configured as general-purpose output for the GPIO function.
 */
#define GPIO_PDDR_PDD16(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD16_SHIFT)) & GPIO_PDDR_PDD16_MASK)

#define GPIO_PDDR_PDD17_MASK                     (0x20000U)
#define GPIO_PDDR_PDD17_SHIFT                    (17U)
/*! PDD17 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input for the GPIO function.
 *  0b1..Pin is configured as general-purpose output for the GPIO function.
 */
#define GPIO_PDDR_PDD17(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD17_SHIFT)) & GPIO_PDDR_PDD17_MASK)

#define GPIO_PDDR_PDD18_MASK                     (0x40000U)
#define GPIO_PDDR_PDD18_SHIFT                    (18U)
/*! PDD18 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input for the GPIO function.
 *  0b1..Pin is configured as general-purpose output for the GPIO function.
 */
#define GPIO_PDDR_PDD18(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD18_SHIFT)) & GPIO_PDDR_PDD18_MASK)

#define GPIO_PDDR_PDD19_MASK                     (0x80000U)
#define GPIO_PDDR_PDD19_SHIFT                    (19U)
/*! PDD19 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input for the GPIO function.
 *  0b1..Pin is configured as general-purpose output for the GPIO function.
 */
#define GPIO_PDDR_PDD19(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD19_SHIFT)) & GPIO_PDDR_PDD19_MASK)

#define GPIO_PDDR_PDD20_MASK                     (0x100000U)
#define GPIO_PDDR_PDD20_SHIFT                    (20U)
/*! PDD20 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input for the GPIO function.
 *  0b1..Pin is configured as general-purpose output for the GPIO function.
 */
#define GPIO_PDDR_PDD20(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD20_SHIFT)) & GPIO_PDDR_PDD20_MASK)

#define GPIO_PDDR_PDD21_MASK                     (0x200000U)
#define GPIO_PDDR_PDD21_SHIFT                    (21U)
/*! PDD21 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input for the GPIO function.
 *  0b1..Pin is configured as general-purpose output for the GPIO function.
 */
#define GPIO_PDDR_PDD21(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD21_SHIFT)) & GPIO_PDDR_PDD21_MASK)

#define GPIO_PDDR_PDD22_MASK                     (0x400000U)
#define GPIO_PDDR_PDD22_SHIFT                    (22U)
/*! PDD22 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input for the GPIO function.
 *  0b1..Pin is configured as general-purpose output for the GPIO function.
 */
#define GPIO_PDDR_PDD22(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD22_SHIFT)) & GPIO_PDDR_PDD22_MASK)

#define GPIO_PDDR_PDD23_MASK                     (0x800000U)
#define GPIO_PDDR_PDD23_SHIFT                    (23U)
/*! PDD23 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input for the GPIO function.
 *  0b1..Pin is configured as general-purpose output for the GPIO function.
 */
#define GPIO_PDDR_PDD23(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD23_SHIFT)) & GPIO_PDDR_PDD23_MASK)

#define GPIO_PDDR_PDD24_MASK                     (0x1000000U)
#define GPIO_PDDR_PDD24_SHIFT                    (24U)
/*! PDD24 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input for the GPIO function.
 *  0b1..Pin is configured as general-purpose output for the GPIO function.
 */
#define GPIO_PDDR_PDD24(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD24_SHIFT)) & GPIO_PDDR_PDD24_MASK)

#define GPIO_PDDR_PDD25_MASK                     (0x2000000U)
#define GPIO_PDDR_PDD25_SHIFT                    (25U)
/*! PDD25 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input for the GPIO function.
 *  0b1..Pin is configured as general-purpose output for the GPIO function.
 */
#define GPIO_PDDR_PDD25(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD25_SHIFT)) & GPIO_PDDR_PDD25_MASK)

#define GPIO_PDDR_PDD26_MASK                     (0x4000000U)
#define GPIO_PDDR_PDD26_SHIFT                    (26U)
/*! PDD26 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input for the GPIO function.
 *  0b1..Pin is configured as general-purpose output for the GPIO function.
 */
#define GPIO_PDDR_PDD26(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD26_SHIFT)) & GPIO_PDDR_PDD26_MASK)

#define GPIO_PDDR_PDD27_MASK                     (0x8000000U)
#define GPIO_PDDR_PDD27_SHIFT                    (27U)
/*! PDD27 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input for the GPIO function.
 *  0b1..Pin is configured as general-purpose output for the GPIO function.
 */
#define GPIO_PDDR_PDD27(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD27_SHIFT)) & GPIO_PDDR_PDD27_MASK)

#define GPIO_PDDR_PDD28_MASK                     (0x10000000U)
#define GPIO_PDDR_PDD28_SHIFT                    (28U)
/*! PDD28 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input for the GPIO function.
 *  0b1..Pin is configured as general-purpose output for the GPIO function.
 */
#define GPIO_PDDR_PDD28(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD28_SHIFT)) & GPIO_PDDR_PDD28_MASK)

#define GPIO_PDDR_PDD29_MASK                     (0x20000000U)
#define GPIO_PDDR_PDD29_SHIFT                    (29U)
/*! PDD29 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input for the GPIO function.
 *  0b1..Pin is configured as general-purpose output for the GPIO function.
 */
#define GPIO_PDDR_PDD29(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD29_SHIFT)) & GPIO_PDDR_PDD29_MASK)

#define GPIO_PDDR_PDD30_MASK                     (0x40000000U)
#define GPIO_PDDR_PDD30_SHIFT                    (30U)
/*! PDD30 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input for the GPIO function.
 *  0b1..Pin is configured as general-purpose output for the GPIO function.
 */
#define GPIO_PDDR_PDD30(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD30_SHIFT)) & GPIO_PDDR_PDD30_MASK)

#define GPIO_PDDR_PDD31_MASK                     (0x80000000U)
#define GPIO_PDDR_PDD31_SHIFT                    (31U)
/*! PDD31 - Port Data Direction
 *  0b0..Pin is configured as general-purpose input for the GPIO function.
 *  0b1..Pin is configured as general-purpose output for the GPIO function.
 */
#define GPIO_PDDR_PDD31(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD31_SHIFT)) & GPIO_PDDR_PDD31_MASK)
/*! @} */

/*! @name PIDR - Port Input Disable Register */
/*! @{ */

#define GPIO_PIDR_PID0_MASK                      (0x1U)
#define GPIO_PIDR_PID0_SHIFT                     (0U)
/*! PID0 - Port Input Disable
 *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
 *  0b1..Pin is disabled for general-purpose input.
 */
#define GPIO_PIDR_PID0(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID0_SHIFT)) & GPIO_PIDR_PID0_MASK)

#define GPIO_PIDR_PID1_MASK                      (0x2U)
#define GPIO_PIDR_PID1_SHIFT                     (1U)
/*! PID1 - Port Input Disable
 *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
 *  0b1..Pin is disabled for general-purpose input.
 */
#define GPIO_PIDR_PID1(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID1_SHIFT)) & GPIO_PIDR_PID1_MASK)

#define GPIO_PIDR_PID2_MASK                      (0x4U)
#define GPIO_PIDR_PID2_SHIFT                     (2U)
/*! PID2 - Port Input Disable
 *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
 *  0b1..Pin is disabled for general-purpose input.
 */
#define GPIO_PIDR_PID2(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID2_SHIFT)) & GPIO_PIDR_PID2_MASK)

#define GPIO_PIDR_PID3_MASK                      (0x8U)
#define GPIO_PIDR_PID3_SHIFT                     (3U)
/*! PID3 - Port Input Disable
 *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
 *  0b1..Pin is disabled for general-purpose input.
 */
#define GPIO_PIDR_PID3(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID3_SHIFT)) & GPIO_PIDR_PID3_MASK)

#define GPIO_PIDR_PID4_MASK                      (0x10U)
#define GPIO_PIDR_PID4_SHIFT                     (4U)
/*! PID4 - Port Input Disable
 *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
 *  0b1..Pin is disabled for general-purpose input.
 */
#define GPIO_PIDR_PID4(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID4_SHIFT)) & GPIO_PIDR_PID4_MASK)

#define GPIO_PIDR_PID5_MASK                      (0x20U)
#define GPIO_PIDR_PID5_SHIFT                     (5U)
/*! PID5 - Port Input Disable
 *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
 *  0b1..Pin is disabled for general-purpose input.
 */
#define GPIO_PIDR_PID5(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID5_SHIFT)) & GPIO_PIDR_PID5_MASK)

#define GPIO_PIDR_PID6_MASK                      (0x40U)
#define GPIO_PIDR_PID6_SHIFT                     (6U)
/*! PID6 - Port Input Disable
 *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
 *  0b1..Pin is disabled for general-purpose input.
 */
#define GPIO_PIDR_PID6(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID6_SHIFT)) & GPIO_PIDR_PID6_MASK)

#define GPIO_PIDR_PID7_MASK                      (0x80U)
#define GPIO_PIDR_PID7_SHIFT                     (7U)
/*! PID7 - Port Input Disable
 *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
 *  0b1..Pin is disabled for general-purpose input.
 */
#define GPIO_PIDR_PID7(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID7_SHIFT)) & GPIO_PIDR_PID7_MASK)

#define GPIO_PIDR_PID8_MASK                      (0x100U)
#define GPIO_PIDR_PID8_SHIFT                     (8U)
/*! PID8 - Port Input Disable
 *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
 *  0b1..Pin is disabled for general-purpose input.
 */
#define GPIO_PIDR_PID8(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID8_SHIFT)) & GPIO_PIDR_PID8_MASK)

#define GPIO_PIDR_PID9_MASK                      (0x200U)
#define GPIO_PIDR_PID9_SHIFT                     (9U)
/*! PID9 - Port Input Disable
 *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
 *  0b1..Pin is disabled for general-purpose input.
 */
#define GPIO_PIDR_PID9(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID9_SHIFT)) & GPIO_PIDR_PID9_MASK)

#define GPIO_PIDR_PID10_MASK                     (0x400U)
#define GPIO_PIDR_PID10_SHIFT                    (10U)
/*! PID10 - Port Input Disable
 *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
 *  0b1..Pin is disabled for general-purpose input.
 */
#define GPIO_PIDR_PID10(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID10_SHIFT)) & GPIO_PIDR_PID10_MASK)

#define GPIO_PIDR_PID11_MASK                     (0x800U)
#define GPIO_PIDR_PID11_SHIFT                    (11U)
/*! PID11 - Port Input Disable
 *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
 *  0b1..Pin is disabled for general-purpose input.
 */
#define GPIO_PIDR_PID11(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID11_SHIFT)) & GPIO_PIDR_PID11_MASK)

#define GPIO_PIDR_PID12_MASK                     (0x1000U)
#define GPIO_PIDR_PID12_SHIFT                    (12U)
/*! PID12 - Port Input Disable
 *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
 *  0b1..Pin is disabled for general-purpose input.
 */
#define GPIO_PIDR_PID12(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID12_SHIFT)) & GPIO_PIDR_PID12_MASK)

#define GPIO_PIDR_PID13_MASK                     (0x2000U)
#define GPIO_PIDR_PID13_SHIFT                    (13U)
/*! PID13 - Port Input Disable
 *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
 *  0b1..Pin is disabled for general-purpose input.
 */
#define GPIO_PIDR_PID13(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID13_SHIFT)) & GPIO_PIDR_PID13_MASK)

#define GPIO_PIDR_PID14_MASK                     (0x4000U)
#define GPIO_PIDR_PID14_SHIFT                    (14U)
/*! PID14 - Port Input Disable
 *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
 *  0b1..Pin is disabled for general-purpose input.
 */
#define GPIO_PIDR_PID14(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID14_SHIFT)) & GPIO_PIDR_PID14_MASK)

#define GPIO_PIDR_PID15_MASK                     (0x8000U)
#define GPIO_PIDR_PID15_SHIFT                    (15U)
/*! PID15 - Port Input Disable
 *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
 *  0b1..Pin is disabled for general-purpose input.
 */
#define GPIO_PIDR_PID15(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID15_SHIFT)) & GPIO_PIDR_PID15_MASK)

#define GPIO_PIDR_PID16_MASK                     (0x10000U)
#define GPIO_PIDR_PID16_SHIFT                    (16U)
/*! PID16 - Port Input Disable
 *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
 *  0b1..Pin is disabled for general-purpose input.
 */
#define GPIO_PIDR_PID16(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID16_SHIFT)) & GPIO_PIDR_PID16_MASK)

#define GPIO_PIDR_PID17_MASK                     (0x20000U)
#define GPIO_PIDR_PID17_SHIFT                    (17U)
/*! PID17 - Port Input Disable
 *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
 *  0b1..Pin is disabled for general-purpose input.
 */
#define GPIO_PIDR_PID17(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID17_SHIFT)) & GPIO_PIDR_PID17_MASK)

#define GPIO_PIDR_PID18_MASK                     (0x40000U)
#define GPIO_PIDR_PID18_SHIFT                    (18U)
/*! PID18 - Port Input Disable
 *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
 *  0b1..Pin is disabled for general-purpose input.
 */
#define GPIO_PIDR_PID18(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID18_SHIFT)) & GPIO_PIDR_PID18_MASK)

#define GPIO_PIDR_PID19_MASK                     (0x80000U)
#define GPIO_PIDR_PID19_SHIFT                    (19U)
/*! PID19 - Port Input Disable
 *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
 *  0b1..Pin is disabled for general-purpose input.
 */
#define GPIO_PIDR_PID19(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID19_SHIFT)) & GPIO_PIDR_PID19_MASK)

#define GPIO_PIDR_PID20_MASK                     (0x100000U)
#define GPIO_PIDR_PID20_SHIFT                    (20U)
/*! PID20 - Port Input Disable
 *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
 *  0b1..Pin is disabled for general-purpose input.
 */
#define GPIO_PIDR_PID20(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID20_SHIFT)) & GPIO_PIDR_PID20_MASK)

#define GPIO_PIDR_PID21_MASK                     (0x200000U)
#define GPIO_PIDR_PID21_SHIFT                    (21U)
/*! PID21 - Port Input Disable
 *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
 *  0b1..Pin is disabled for general-purpose input.
 */
#define GPIO_PIDR_PID21(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID21_SHIFT)) & GPIO_PIDR_PID21_MASK)

#define GPIO_PIDR_PID22_MASK                     (0x400000U)
#define GPIO_PIDR_PID22_SHIFT                    (22U)
/*! PID22 - Port Input Disable
 *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
 *  0b1..Pin is disabled for general-purpose input.
 */
#define GPIO_PIDR_PID22(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID22_SHIFT)) & GPIO_PIDR_PID22_MASK)

#define GPIO_PIDR_PID23_MASK                     (0x800000U)
#define GPIO_PIDR_PID23_SHIFT                    (23U)
/*! PID23 - Port Input Disable
 *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
 *  0b1..Pin is disabled for general-purpose input.
 */
#define GPIO_PIDR_PID23(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID23_SHIFT)) & GPIO_PIDR_PID23_MASK)

#define GPIO_PIDR_PID24_MASK                     (0x1000000U)
#define GPIO_PIDR_PID24_SHIFT                    (24U)
/*! PID24 - Port Input Disable
 *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
 *  0b1..Pin is disabled for general-purpose input.
 */
#define GPIO_PIDR_PID24(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID24_SHIFT)) & GPIO_PIDR_PID24_MASK)

#define GPIO_PIDR_PID25_MASK                     (0x2000000U)
#define GPIO_PIDR_PID25_SHIFT                    (25U)
/*! PID25 - Port Input Disable
 *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
 *  0b1..Pin is disabled for general-purpose input.
 */
#define GPIO_PIDR_PID25(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID25_SHIFT)) & GPIO_PIDR_PID25_MASK)

#define GPIO_PIDR_PID26_MASK                     (0x4000000U)
#define GPIO_PIDR_PID26_SHIFT                    (26U)
/*! PID26 - Port Input Disable
 *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
 *  0b1..Pin is disabled for general-purpose input.
 */
#define GPIO_PIDR_PID26(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID26_SHIFT)) & GPIO_PIDR_PID26_MASK)

#define GPIO_PIDR_PID27_MASK                     (0x8000000U)
#define GPIO_PIDR_PID27_SHIFT                    (27U)
/*! PID27 - Port Input Disable
 *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
 *  0b1..Pin is disabled for general-purpose input.
 */
#define GPIO_PIDR_PID27(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID27_SHIFT)) & GPIO_PIDR_PID27_MASK)

#define GPIO_PIDR_PID28_MASK                     (0x10000000U)
#define GPIO_PIDR_PID28_SHIFT                    (28U)
/*! PID28 - Port Input Disable
 *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
 *  0b1..Pin is disabled for general-purpose input.
 */
#define GPIO_PIDR_PID28(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID28_SHIFT)) & GPIO_PIDR_PID28_MASK)

#define GPIO_PIDR_PID29_MASK                     (0x20000000U)
#define GPIO_PIDR_PID29_SHIFT                    (29U)
/*! PID29 - Port Input Disable
 *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
 *  0b1..Pin is disabled for general-purpose input.
 */
#define GPIO_PIDR_PID29(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID29_SHIFT)) & GPIO_PIDR_PID29_MASK)

#define GPIO_PIDR_PID30_MASK                     (0x40000000U)
#define GPIO_PIDR_PID30_SHIFT                    (30U)
/*! PID30 - Port Input Disable
 *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
 *  0b1..Pin is disabled for general-purpose input.
 */
#define GPIO_PIDR_PID30(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID30_SHIFT)) & GPIO_PIDR_PID30_MASK)

#define GPIO_PIDR_PID31_MASK                     (0x80000000U)
#define GPIO_PIDR_PID31_SHIFT                    (31U)
/*! PID31 - Port Input Disable
 *  0b0..Pin is configured for general-purpose input provided, the pin is configured for any digital function.
 *  0b1..Pin is disabled for general-purpose input.
 */
#define GPIO_PIDR_PID31(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID31_SHIFT)) & GPIO_PIDR_PID31_MASK)
/*! @} */

/*! @name PDR - Pin Data Register a */
/*! @{ */

#define GPIO_PDR_PD_MASK                         (0x1U)
#define GPIO_PDR_PD_SHIFT                        (0U)
/*! PD - Pin Data (input and output)
 *  0b0..Pin logic level is logic zero or not configured for use by digital function.
 *  0b1..Pin logic level is logic one.
 */
#define GPIO_PDR_PD(x)                           (((uint8_t)(((uint8_t)(x)) << GPIO_PDR_PD_SHIFT)) & GPIO_PDR_PD_MASK)
/*! @} */

/* The count of GPIO_PDR */
#define GPIO_PDR_COUNT                           (32U)

/*! @name ICR - Interrupt Control Register 0..Interrupt Control Register 31 */
/*! @{ */

#define GPIO_ICR_IRQC_MASK                       (0xF0000U)
#define GPIO_ICR_IRQC_SHIFT                      (16U)
/*! IRQC - Interrupt Configuration
 *  0b0000..Interrupt Status Flag (ISF) is disabled.
 *  0b0001..ISF flag and DMA request on rising edge.
 *  0b0010..ISF flag and DMA request on falling edge.
 *  0b0011..ISF flag and DMA request on either edge.
 *  0b0100..Reserved.
 *  0b0101..ISF flag sets on rising edge.
 *  0b0110..ISF flag sets on falling edge.
 *  0b0111..ISF flag sets on either edge.
 *  0b1000..ISF flag and Interrupt when logic 0.
 *  0b1001..ISF flag and Interrupt on rising-edge.
 *  0b1010..ISF flag and Interrupt on falling-edge.
 *  0b1011..ISF flag and Interrupt on either edge.
 *  0b1100..ISF flag and Interrupt when logic 1.
 *  0b1101..Enable active high trigger output, ISF flag on rising edge. Pin state is ORed with other enabled
 *          triggers to generate the output trigger, for use by other peripherals.
 *  0b1110..Enable active low trigger output, ISF flag on falling edge. Pin state is inverted and ORed with other
 *          enabled triggers to generate the output trigger, for use by other peripherals.
 *  0b1111..Reserved.
 */
#define GPIO_ICR_IRQC(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_ICR_IRQC_SHIFT)) & GPIO_ICR_IRQC_MASK)

#define GPIO_ICR_IRQS_MASK                       (0x100000U)
#define GPIO_ICR_IRQS_SHIFT                      (20U)
/*! IRQS - Interrupt Select
 *  0b0..Interrupt/DMA request/trigger output 0.
 *  0b1..Interrupt/DMA request/trigger output 1.
 */
#define GPIO_ICR_IRQS(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_ICR_IRQS_SHIFT)) & GPIO_ICR_IRQS_MASK)

#define GPIO_ICR_LK_MASK                         (0x800000U)
#define GPIO_ICR_LK_SHIFT                        (23U)
/*! LK - Lock Register
 *  0b0..Interrupt configuration by ICR[23:0] is not locked and can be updated.
 *  0b1..Interrupt configuration by ICR[23:0] is locked and cannot be updated until next system reset.
 */
#define GPIO_ICR_LK(x)                           (((uint32_t)(((uint32_t)(x)) << GPIO_ICR_LK_SHIFT)) & GPIO_ICR_LK_MASK)

#define GPIO_ICR_ISF_MASK                        (0x1000000U)
#define GPIO_ICR_ISF_SHIFT                       (24U)
/*! ISF - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected.
 *  0b1..Configured interrupt is detected. If the pin is configured to generate a DMA request, then the
 *       corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the
 *       flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive
 *       interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
 */
#define GPIO_ICR_ISF(x)                          (((uint32_t)(((uint32_t)(x)) << GPIO_ICR_ISF_SHIFT)) & GPIO_ICR_ISF_MASK)
/*! @} */

/* The count of GPIO_ICR */
#define GPIO_ICR_COUNT                           (32U)

/*! @name GICLR - Global Interrupt Control Low Register */
/*! @{ */

#define GPIO_GICLR_GIWE0_MASK                    (0x1U)
#define GPIO_GICLR_GIWE0_SHIFT                   (0U)
/*! GIWE0 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define GPIO_GICLR_GIWE0(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE0_SHIFT)) & GPIO_GICLR_GIWE0_MASK)

#define GPIO_GICLR_GIWE1_MASK                    (0x2U)
#define GPIO_GICLR_GIWE1_SHIFT                   (1U)
/*! GIWE1 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define GPIO_GICLR_GIWE1(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE1_SHIFT)) & GPIO_GICLR_GIWE1_MASK)

#define GPIO_GICLR_GIWE2_MASK                    (0x4U)
#define GPIO_GICLR_GIWE2_SHIFT                   (2U)
/*! GIWE2 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define GPIO_GICLR_GIWE2(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE2_SHIFT)) & GPIO_GICLR_GIWE2_MASK)

#define GPIO_GICLR_GIWE3_MASK                    (0x8U)
#define GPIO_GICLR_GIWE3_SHIFT                   (3U)
/*! GIWE3 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define GPIO_GICLR_GIWE3(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE3_SHIFT)) & GPIO_GICLR_GIWE3_MASK)

#define GPIO_GICLR_GIWE4_MASK                    (0x10U)
#define GPIO_GICLR_GIWE4_SHIFT                   (4U)
/*! GIWE4 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define GPIO_GICLR_GIWE4(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE4_SHIFT)) & GPIO_GICLR_GIWE4_MASK)

#define GPIO_GICLR_GIWE5_MASK                    (0x20U)
#define GPIO_GICLR_GIWE5_SHIFT                   (5U)
/*! GIWE5 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define GPIO_GICLR_GIWE5(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE5_SHIFT)) & GPIO_GICLR_GIWE5_MASK)

#define GPIO_GICLR_GIWE6_MASK                    (0x40U)
#define GPIO_GICLR_GIWE6_SHIFT                   (6U)
/*! GIWE6 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define GPIO_GICLR_GIWE6(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE6_SHIFT)) & GPIO_GICLR_GIWE6_MASK)

#define GPIO_GICLR_GIWE7_MASK                    (0x80U)
#define GPIO_GICLR_GIWE7_SHIFT                   (7U)
/*! GIWE7 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define GPIO_GICLR_GIWE7(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE7_SHIFT)) & GPIO_GICLR_GIWE7_MASK)

#define GPIO_GICLR_GIWE8_MASK                    (0x100U)
#define GPIO_GICLR_GIWE8_SHIFT                   (8U)
/*! GIWE8 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define GPIO_GICLR_GIWE8(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE8_SHIFT)) & GPIO_GICLR_GIWE8_MASK)

#define GPIO_GICLR_GIWE9_MASK                    (0x200U)
#define GPIO_GICLR_GIWE9_SHIFT                   (9U)
/*! GIWE9 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define GPIO_GICLR_GIWE9(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE9_SHIFT)) & GPIO_GICLR_GIWE9_MASK)

#define GPIO_GICLR_GIWE10_MASK                   (0x400U)
#define GPIO_GICLR_GIWE10_SHIFT                  (10U)
/*! GIWE10 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define GPIO_GICLR_GIWE10(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE10_SHIFT)) & GPIO_GICLR_GIWE10_MASK)

#define GPIO_GICLR_GIWE11_MASK                   (0x800U)
#define GPIO_GICLR_GIWE11_SHIFT                  (11U)
/*! GIWE11 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define GPIO_GICLR_GIWE11(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE11_SHIFT)) & GPIO_GICLR_GIWE11_MASK)

#define GPIO_GICLR_GIWE12_MASK                   (0x1000U)
#define GPIO_GICLR_GIWE12_SHIFT                  (12U)
/*! GIWE12 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define GPIO_GICLR_GIWE12(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE12_SHIFT)) & GPIO_GICLR_GIWE12_MASK)

#define GPIO_GICLR_GIWE13_MASK                   (0x2000U)
#define GPIO_GICLR_GIWE13_SHIFT                  (13U)
/*! GIWE13 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define GPIO_GICLR_GIWE13(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE13_SHIFT)) & GPIO_GICLR_GIWE13_MASK)

#define GPIO_GICLR_GIWE14_MASK                   (0x4000U)
#define GPIO_GICLR_GIWE14_SHIFT                  (14U)
/*! GIWE14 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define GPIO_GICLR_GIWE14(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE14_SHIFT)) & GPIO_GICLR_GIWE14_MASK)

#define GPIO_GICLR_GIWE15_MASK                   (0x8000U)
#define GPIO_GICLR_GIWE15_SHIFT                  (15U)
/*! GIWE15 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define GPIO_GICLR_GIWE15(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE15_SHIFT)) & GPIO_GICLR_GIWE15_MASK)

#define GPIO_GICLR_GIWD_MASK                     (0xFFFF0000U)
#define GPIO_GICLR_GIWD_SHIFT                    (16U)
/*! GIWD - Global Interrupt Write Data
 */
#define GPIO_GICLR_GIWD(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWD_SHIFT)) & GPIO_GICLR_GIWD_MASK)
/*! @} */

/*! @name GICHR - Global Interrupt Control High Register */
/*! @{ */

#define GPIO_GICHR_GIWE16_MASK                   (0x1U)
#define GPIO_GICHR_GIWE16_SHIFT                  (0U)
/*! GIWE16 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define GPIO_GICHR_GIWE16(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE16_SHIFT)) & GPIO_GICHR_GIWE16_MASK)

#define GPIO_GICHR_GIWE17_MASK                   (0x2U)
#define GPIO_GICHR_GIWE17_SHIFT                  (1U)
/*! GIWE17 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define GPIO_GICHR_GIWE17(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE17_SHIFT)) & GPIO_GICHR_GIWE17_MASK)

#define GPIO_GICHR_GIWE18_MASK                   (0x4U)
#define GPIO_GICHR_GIWE18_SHIFT                  (2U)
/*! GIWE18 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define GPIO_GICHR_GIWE18(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE18_SHIFT)) & GPIO_GICHR_GIWE18_MASK)

#define GPIO_GICHR_GIWE19_MASK                   (0x8U)
#define GPIO_GICHR_GIWE19_SHIFT                  (3U)
/*! GIWE19 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define GPIO_GICHR_GIWE19(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE19_SHIFT)) & GPIO_GICHR_GIWE19_MASK)

#define GPIO_GICHR_GIWE20_MASK                   (0x10U)
#define GPIO_GICHR_GIWE20_SHIFT                  (4U)
/*! GIWE20 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define GPIO_GICHR_GIWE20(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE20_SHIFT)) & GPIO_GICHR_GIWE20_MASK)

#define GPIO_GICHR_GIWE21_MASK                   (0x20U)
#define GPIO_GICHR_GIWE21_SHIFT                  (5U)
/*! GIWE21 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define GPIO_GICHR_GIWE21(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE21_SHIFT)) & GPIO_GICHR_GIWE21_MASK)

#define GPIO_GICHR_GIWE22_MASK                   (0x40U)
#define GPIO_GICHR_GIWE22_SHIFT                  (6U)
/*! GIWE22 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define GPIO_GICHR_GIWE22(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE22_SHIFT)) & GPIO_GICHR_GIWE22_MASK)

#define GPIO_GICHR_GIWE23_MASK                   (0x80U)
#define GPIO_GICHR_GIWE23_SHIFT                  (7U)
/*! GIWE23 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define GPIO_GICHR_GIWE23(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE23_SHIFT)) & GPIO_GICHR_GIWE23_MASK)

#define GPIO_GICHR_GIWE24_MASK                   (0x100U)
#define GPIO_GICHR_GIWE24_SHIFT                  (8U)
/*! GIWE24 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define GPIO_GICHR_GIWE24(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE24_SHIFT)) & GPIO_GICHR_GIWE24_MASK)

#define GPIO_GICHR_GIWE25_MASK                   (0x200U)
#define GPIO_GICHR_GIWE25_SHIFT                  (9U)
/*! GIWE25 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define GPIO_GICHR_GIWE25(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE25_SHIFT)) & GPIO_GICHR_GIWE25_MASK)

#define GPIO_GICHR_GIWE26_MASK                   (0x400U)
#define GPIO_GICHR_GIWE26_SHIFT                  (10U)
/*! GIWE26 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define GPIO_GICHR_GIWE26(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE26_SHIFT)) & GPIO_GICHR_GIWE26_MASK)

#define GPIO_GICHR_GIWE27_MASK                   (0x800U)
#define GPIO_GICHR_GIWE27_SHIFT                  (11U)
/*! GIWE27 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define GPIO_GICHR_GIWE27(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE27_SHIFT)) & GPIO_GICHR_GIWE27_MASK)

#define GPIO_GICHR_GIWE28_MASK                   (0x1000U)
#define GPIO_GICHR_GIWE28_SHIFT                  (12U)
/*! GIWE28 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define GPIO_GICHR_GIWE28(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE28_SHIFT)) & GPIO_GICHR_GIWE28_MASK)

#define GPIO_GICHR_GIWE29_MASK                   (0x2000U)
#define GPIO_GICHR_GIWE29_SHIFT                  (13U)
/*! GIWE29 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define GPIO_GICHR_GIWE29(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE29_SHIFT)) & GPIO_GICHR_GIWE29_MASK)

#define GPIO_GICHR_GIWE30_MASK                   (0x4000U)
#define GPIO_GICHR_GIWE30_SHIFT                  (14U)
/*! GIWE30 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define GPIO_GICHR_GIWE30(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE30_SHIFT)) & GPIO_GICHR_GIWE30_MASK)

#define GPIO_GICHR_GIWE31_MASK                   (0x8000U)
#define GPIO_GICHR_GIWE31_SHIFT                  (15U)
/*! GIWE31 - Global Interrupt Write Enable
 *  0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in GIWD.
 *  0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
 */
#define GPIO_GICHR_GIWE31(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE31_SHIFT)) & GPIO_GICHR_GIWE31_MASK)

#define GPIO_GICHR_GIWD_MASK                     (0xFFFF0000U)
#define GPIO_GICHR_GIWD_SHIFT                    (16U)
/*! GIWD - Global Interrupt Write Data
 */
#define GPIO_GICHR_GIWD(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWD_SHIFT)) & GPIO_GICHR_GIWD_MASK)
/*! @} */

/*! @name ISFR - Interrupt Status Flag Register */
/*! @{ */

#define GPIO_ISFR_ISF0_MASK                      (0x1U)
#define GPIO_ISFR_ISF0_SHIFT                     (0U)
/*! ISF0 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define GPIO_ISFR_ISF0(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF0_SHIFT)) & GPIO_ISFR_ISF0_MASK)

#define GPIO_ISFR_ISF1_MASK                      (0x2U)
#define GPIO_ISFR_ISF1_SHIFT                     (1U)
/*! ISF1 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define GPIO_ISFR_ISF1(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF1_SHIFT)) & GPIO_ISFR_ISF1_MASK)

#define GPIO_ISFR_ISF2_MASK                      (0x4U)
#define GPIO_ISFR_ISF2_SHIFT                     (2U)
/*! ISF2 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define GPIO_ISFR_ISF2(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF2_SHIFT)) & GPIO_ISFR_ISF2_MASK)

#define GPIO_ISFR_ISF3_MASK                      (0x8U)
#define GPIO_ISFR_ISF3_SHIFT                     (3U)
/*! ISF3 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define GPIO_ISFR_ISF3(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF3_SHIFT)) & GPIO_ISFR_ISF3_MASK)

#define GPIO_ISFR_ISF4_MASK                      (0x10U)
#define GPIO_ISFR_ISF4_SHIFT                     (4U)
/*! ISF4 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define GPIO_ISFR_ISF4(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF4_SHIFT)) & GPIO_ISFR_ISF4_MASK)

#define GPIO_ISFR_ISF5_MASK                      (0x20U)
#define GPIO_ISFR_ISF5_SHIFT                     (5U)
/*! ISF5 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define GPIO_ISFR_ISF5(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF5_SHIFT)) & GPIO_ISFR_ISF5_MASK)

#define GPIO_ISFR_ISF6_MASK                      (0x40U)
#define GPIO_ISFR_ISF6_SHIFT                     (6U)
/*! ISF6 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define GPIO_ISFR_ISF6(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF6_SHIFT)) & GPIO_ISFR_ISF6_MASK)

#define GPIO_ISFR_ISF7_MASK                      (0x80U)
#define GPIO_ISFR_ISF7_SHIFT                     (7U)
/*! ISF7 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define GPIO_ISFR_ISF7(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF7_SHIFT)) & GPIO_ISFR_ISF7_MASK)

#define GPIO_ISFR_ISF8_MASK                      (0x100U)
#define GPIO_ISFR_ISF8_SHIFT                     (8U)
/*! ISF8 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define GPIO_ISFR_ISF8(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF8_SHIFT)) & GPIO_ISFR_ISF8_MASK)

#define GPIO_ISFR_ISF9_MASK                      (0x200U)
#define GPIO_ISFR_ISF9_SHIFT                     (9U)
/*! ISF9 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define GPIO_ISFR_ISF9(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF9_SHIFT)) & GPIO_ISFR_ISF9_MASK)

#define GPIO_ISFR_ISF10_MASK                     (0x400U)
#define GPIO_ISFR_ISF10_SHIFT                    (10U)
/*! ISF10 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define GPIO_ISFR_ISF10(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF10_SHIFT)) & GPIO_ISFR_ISF10_MASK)

#define GPIO_ISFR_ISF11_MASK                     (0x800U)
#define GPIO_ISFR_ISF11_SHIFT                    (11U)
/*! ISF11 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define GPIO_ISFR_ISF11(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF11_SHIFT)) & GPIO_ISFR_ISF11_MASK)

#define GPIO_ISFR_ISF12_MASK                     (0x1000U)
#define GPIO_ISFR_ISF12_SHIFT                    (12U)
/*! ISF12 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define GPIO_ISFR_ISF12(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF12_SHIFT)) & GPIO_ISFR_ISF12_MASK)

#define GPIO_ISFR_ISF13_MASK                     (0x2000U)
#define GPIO_ISFR_ISF13_SHIFT                    (13U)
/*! ISF13 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define GPIO_ISFR_ISF13(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF13_SHIFT)) & GPIO_ISFR_ISF13_MASK)

#define GPIO_ISFR_ISF14_MASK                     (0x4000U)
#define GPIO_ISFR_ISF14_SHIFT                    (14U)
/*! ISF14 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define GPIO_ISFR_ISF14(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF14_SHIFT)) & GPIO_ISFR_ISF14_MASK)

#define GPIO_ISFR_ISF15_MASK                     (0x8000U)
#define GPIO_ISFR_ISF15_SHIFT                    (15U)
/*! ISF15 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define GPIO_ISFR_ISF15(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF15_SHIFT)) & GPIO_ISFR_ISF15_MASK)

#define GPIO_ISFR_ISF16_MASK                     (0x10000U)
#define GPIO_ISFR_ISF16_SHIFT                    (16U)
/*! ISF16 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define GPIO_ISFR_ISF16(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF16_SHIFT)) & GPIO_ISFR_ISF16_MASK)

#define GPIO_ISFR_ISF17_MASK                     (0x20000U)
#define GPIO_ISFR_ISF17_SHIFT                    (17U)
/*! ISF17 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define GPIO_ISFR_ISF17(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF17_SHIFT)) & GPIO_ISFR_ISF17_MASK)

#define GPIO_ISFR_ISF18_MASK                     (0x40000U)
#define GPIO_ISFR_ISF18_SHIFT                    (18U)
/*! ISF18 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define GPIO_ISFR_ISF18(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF18_SHIFT)) & GPIO_ISFR_ISF18_MASK)

#define GPIO_ISFR_ISF19_MASK                     (0x80000U)
#define GPIO_ISFR_ISF19_SHIFT                    (19U)
/*! ISF19 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define GPIO_ISFR_ISF19(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF19_SHIFT)) & GPIO_ISFR_ISF19_MASK)

#define GPIO_ISFR_ISF20_MASK                     (0x100000U)
#define GPIO_ISFR_ISF20_SHIFT                    (20U)
/*! ISF20 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define GPIO_ISFR_ISF20(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF20_SHIFT)) & GPIO_ISFR_ISF20_MASK)

#define GPIO_ISFR_ISF21_MASK                     (0x200000U)
#define GPIO_ISFR_ISF21_SHIFT                    (21U)
/*! ISF21 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define GPIO_ISFR_ISF21(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF21_SHIFT)) & GPIO_ISFR_ISF21_MASK)

#define GPIO_ISFR_ISF22_MASK                     (0x400000U)
#define GPIO_ISFR_ISF22_SHIFT                    (22U)
/*! ISF22 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define GPIO_ISFR_ISF22(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF22_SHIFT)) & GPIO_ISFR_ISF22_MASK)

#define GPIO_ISFR_ISF23_MASK                     (0x800000U)
#define GPIO_ISFR_ISF23_SHIFT                    (23U)
/*! ISF23 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define GPIO_ISFR_ISF23(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF23_SHIFT)) & GPIO_ISFR_ISF23_MASK)

#define GPIO_ISFR_ISF24_MASK                     (0x1000000U)
#define GPIO_ISFR_ISF24_SHIFT                    (24U)
/*! ISF24 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define GPIO_ISFR_ISF24(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF24_SHIFT)) & GPIO_ISFR_ISF24_MASK)

#define GPIO_ISFR_ISF25_MASK                     (0x2000000U)
#define GPIO_ISFR_ISF25_SHIFT                    (25U)
/*! ISF25 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define GPIO_ISFR_ISF25(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF25_SHIFT)) & GPIO_ISFR_ISF25_MASK)

#define GPIO_ISFR_ISF26_MASK                     (0x4000000U)
#define GPIO_ISFR_ISF26_SHIFT                    (26U)
/*! ISF26 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define GPIO_ISFR_ISF26(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF26_SHIFT)) & GPIO_ISFR_ISF26_MASK)

#define GPIO_ISFR_ISF27_MASK                     (0x8000000U)
#define GPIO_ISFR_ISF27_SHIFT                    (27U)
/*! ISF27 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define GPIO_ISFR_ISF27(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF27_SHIFT)) & GPIO_ISFR_ISF27_MASK)

#define GPIO_ISFR_ISF28_MASK                     (0x10000000U)
#define GPIO_ISFR_ISF28_SHIFT                    (28U)
/*! ISF28 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define GPIO_ISFR_ISF28(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF28_SHIFT)) & GPIO_ISFR_ISF28_MASK)

#define GPIO_ISFR_ISF29_MASK                     (0x20000000U)
#define GPIO_ISFR_ISF29_SHIFT                    (29U)
/*! ISF29 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define GPIO_ISFR_ISF29(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF29_SHIFT)) & GPIO_ISFR_ISF29_MASK)

#define GPIO_ISFR_ISF30_MASK                     (0x40000000U)
#define GPIO_ISFR_ISF30_SHIFT                    (30U)
/*! ISF30 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define GPIO_ISFR_ISF30(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF30_SHIFT)) & GPIO_ISFR_ISF30_MASK)

#define GPIO_ISFR_ISF31_MASK                     (0x80000000U)
#define GPIO_ISFR_ISF31_SHIFT                    (31U)
/*! ISF31 - Interrupt Status Flag
 *  0b0..Configured interrupt is not detected on the pin of the same number.
 *  0b1..Configured interrupt is detected on the pin of the same number. If the pin is configured to generate a
 *       DMA request, then the corresponding flag will be cleared automatically at the completion of the requested
 *       DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is
 *       configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately
 *       after it is cleared.
 */
#define GPIO_ISFR_ISF31(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF31_SHIFT)) & GPIO_ISFR_ISF31_MASK)
/*! @} */

/* The count of GPIO_ISFR */
#define GPIO_ISFR_COUNT                          (2U)


/*!
 * @}
 */ /* end of group GPIO_Register_Masks */


/* GPIO - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral GPIOA base address */
  #define GPIOA_BASE                               (0x58010000u)
  /** Peripheral GPIOA base address */
  #define GPIOA_BASE_NS                            (0x48010000u)
  /** Peripheral GPIOA base pointer */
  #define GPIOA                                    ((GPIO_Type *)GPIOA_BASE)
  /** Peripheral GPIOA base pointer */
  #define GPIOA_NS                                 ((GPIO_Type *)GPIOA_BASE_NS)
  /** Peripheral GPIOB base address */
  #define GPIOB_BASE                               (0x58020000u)
  /** Peripheral GPIOB base address */
  #define GPIOB_BASE_NS                            (0x48020000u)
  /** Peripheral GPIOB base pointer */
  #define GPIOB                                    ((GPIO_Type *)GPIOB_BASE)
  /** Peripheral GPIOB base pointer */
  #define GPIOB_NS                                 ((GPIO_Type *)GPIOB_BASE_NS)
  /** Peripheral GPIOC base address */
  #define GPIOC_BASE                               (0x58030000u)
  /** Peripheral GPIOC base address */
  #define GPIOC_BASE_NS                            (0x48030000u)
  /** Peripheral GPIOC base pointer */
  #define GPIOC                                    ((GPIO_Type *)GPIOC_BASE)
  /** Peripheral GPIOC base pointer */
  #define GPIOC_NS                                 ((GPIO_Type *)GPIOC_BASE_NS)
  /** Peripheral GPIOD base address */
  #define GPIOD_BASE                               (0x50046000u)
  /** Peripheral GPIOD base address */
  #define GPIOD_BASE_NS                            (0x40046000u)
  /** Peripheral GPIOD base pointer */
  #define GPIOD                                    ((GPIO_Type *)GPIOD_BASE)
  /** Peripheral GPIOD base pointer */
  #define GPIOD_NS                                 ((GPIO_Type *)GPIOD_BASE_NS)
  /** Array initializer of GPIO peripheral base addresses */
  #define GPIO_BASE_ADDRS                          { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE }
  /** Array initializer of GPIO peripheral base pointers */
  #define GPIO_BASE_PTRS                           { GPIOA, GPIOB, GPIOC, GPIOD }
  /** Array initializer of GPIO peripheral base addresses */
  #define GPIO_BASE_ADDRS_NS                       { GPIOA_BASE_NS, GPIOB_BASE_NS, GPIOC_BASE_NS, GPIOD_BASE_NS }
  /** Array initializer of GPIO peripheral base pointers */
  #define GPIO_BASE_PTRS_NS                        { GPIOA_NS, GPIOB_NS, GPIOC_NS, GPIOD_NS }
#else
  /** Peripheral GPIOA base address */
  #define GPIOA_BASE                               (0x48010000u)
  /** Peripheral GPIOA base pointer */
  #define GPIOA                                    ((GPIO_Type *)GPIOA_BASE)
  /** Peripheral GPIOB base address */
  #define GPIOB_BASE                               (0x48020000u)
  /** Peripheral GPIOB base pointer */
  #define GPIOB                                    ((GPIO_Type *)GPIOB_BASE)
  /** Peripheral GPIOC base address */
  #define GPIOC_BASE                               (0x48030000u)
  /** Peripheral GPIOC base pointer */
  #define GPIOC                                    ((GPIO_Type *)GPIOC_BASE)
  /** Peripheral GPIOD base address */
  #define GPIOD_BASE                               (0x40046000u)
  /** Peripheral GPIOD base pointer */
  #define GPIOD                                    ((GPIO_Type *)GPIOD_BASE)
  /** Array initializer of GPIO peripheral base addresses */
  #define GPIO_BASE_ADDRS                          { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE }
  /** Array initializer of GPIO peripheral base pointers */
  #define GPIO_BASE_PTRS                           { GPIOA, GPIOB, GPIOC, GPIOD }
#endif
/* Interrupt vectors for the GPIO peripheral type when IRQS of ICR register is set to 0 */
#define GPIO_IRQS   {GPIOA_INT0_IRQn, GPIOB_INT0_IRQn, GPIOC_INT0_IRQn, GPIOD_INT0_IRQn}
/* Interrupt vectors for the GPIO peripheral type when IRQS of ICR register is set to 1 */
#define GPIO_IRQS_1 {GPIOA_INT1_IRQn, GPIOB_INT1_IRQn, GPIOC_INT1_IRQn, GPIOD_INT1_IRQn}


/*!
 * @}
 */ /* end of group GPIO_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- I3C Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup I3C_Peripheral_Access_Layer I3C Peripheral Access Layer
 * @{
 */

/** I3C - Register Layout Typedef */
typedef struct {
  __IO uint32_t MCONFIG;                           /**< Master Configuration Register, offset: 0x0 */
  __IO uint32_t SCONFIG;                           /**< Slave Configuration Register, offset: 0x4 */
  __IO uint32_t SSTATUS;                           /**< Slave Status Register, offset: 0x8 */
  __IO uint32_t SCTRL;                             /**< Slave Control Register, offset: 0xC */
  __IO uint32_t SINTSET;                           /**< Slave Interrupt Set Register, offset: 0x10 */
  __IO uint32_t SINTCLR;                           /**< Slave Interrupt Clear Register, offset: 0x14 */
  __I  uint32_t SINTMASKED;                        /**< Slave Interrupt Mask Register, offset: 0x18 */
  __IO uint32_t SERRWARN;                          /**< Slave Errors and Warnings Register, offset: 0x1C */
  __IO uint32_t SDMACTRL;                          /**< Slave DMA Control Register, offset: 0x20 */
       uint8_t RESERVED_0[8];
  __IO uint32_t SDATACTRL;                         /**< Slave Data Control Register, offset: 0x2C */
  __O  uint32_t SWDATAB;                           /**< Slave Write Data Byte Register, offset: 0x30 */
  __O  uint32_t SWDATABE;                          /**< Slave Write Data Byte End, offset: 0x34 */
  __O  uint32_t SWDATAH;                           /**< Slave Write Data Half-word Register, offset: 0x38 */
  __O  uint32_t SWDATAHE;                          /**< Slave Write Data Half-word End Register, offset: 0x3C */
  __I  uint32_t SRDATAB;                           /**< Slave Read Data Byte Register, offset: 0x40 */
       uint8_t RESERVED_1[4];
  __I  uint32_t SRDATAH;                           /**< Slave Read Data Half-word Register, offset: 0x48 */
       uint8_t RESERVED_2[20];
  __I  uint32_t SCAPABILITIES;                     /**< Slave Capabilities Register, offset: 0x60 */
  __IO uint32_t SDYNADDR;                          /**< Slave Dynamic Address Register, offset: 0x64 */
  __IO uint32_t SMAXLIMITS;                        /**< Slave Maximum Limits Register, offset: 0x68 */
  __IO uint32_t SIDPARTNO;                         /**< Slave ID Part Number Register, offset: 0x6C */
  __IO uint32_t SIDEXT;                            /**< Slave ID Extension Register, offset: 0x70 */
  __IO uint32_t SVENDORID;                         /**< Slave Vendor ID Register, offset: 0x74 */
  __IO uint32_t STCCLOCK;                          /**< Slave Time Control Clock Register, offset: 0x78 */
  __I  uint32_t SMSGMAPADDR;                       /**< Slave Message-Mapped Address Register, offset: 0x7C */
       uint8_t RESERVED_3[4];
  __IO uint32_t MCTRL;                             /**< Master Main Control Register, offset: 0x84 */
  __IO uint32_t MSTATUS;                           /**< Master Status Register, offset: 0x88 */
  __IO uint32_t MIBIRULES;                         /**< Master In-band Interrupt Registry and Rules Register, offset: 0x8C */
  __IO uint32_t MINTSET;                           /**< Master Interrupt Set Register, offset: 0x90 */
  __O  uint32_t MINTCLR;                           /**< Master Interrupt Clear Register, offset: 0x94 */
  __I  uint32_t MINTMASKED;                        /**< Master Interrupt Mask Register, offset: 0x98 */
  __IO uint32_t MERRWARN;                          /**< Master Errors and Warnings Register, offset: 0x9C */
  __IO uint32_t MDMACTRL;                          /**< Master DMA Control Register, offset: 0xA0 */
       uint8_t RESERVED_4[8];
  __IO uint32_t MDATACTRL;                         /**< Master Data Control Register, offset: 0xAC */
  __O  uint32_t MWDATAB;                           /**< Master Write Data Byte Register, offset: 0xB0 */
  __O  uint32_t MWDATABE;                          /**< Master Write Data Byte End Register, offset: 0xB4 */
  __O  uint32_t MWDATAH;                           /**< Master Write Data Half-word Register, offset: 0xB8 */
  __O  uint32_t MWDATAHE;                          /**< Master Write Data Byte End Register, offset: 0xBC */
  __I  uint32_t MRDATAB;                           /**< Master Read Data Byte Register, offset: 0xC0 */
       uint8_t RESERVED_5[4];
  __I  uint32_t MRDATAH;                           /**< Master Read Data Half-word Register, offset: 0xC8 */
  __O  uint32_t MWDATAB1;                          /**< Write Byte Data 1 (to bus), offset: 0xCC */
  union {                                          /* offset: 0xD0 */
    __O  uint32_t MWMSG_SDR_CONTROL;                 /**< Master Write Message in SDR mode, offset: 0xD0 */
    __O  uint32_t MWMSG_SDR_DATA;                    /**< Master Write Message Data in SDR mode, offset: 0xD0 */
  };
  __I  uint32_t MRMSG_SDR;                         /**< Master Read Message in SDR mode, offset: 0xD4 */
  union {                                          /* offset: 0xD8 */
    __O  uint32_t MWMSG_DDR_CONTROL;                 /**< Master Write Message in DDR mode, offset: 0xD8 */
    __O  uint32_t MWMSG_DDR_DATA;                    /**< Master Write Message Data in DDR mode, offset: 0xD8 */
  };
  __IO uint32_t MRMSG_DDR;                         /**< Master Read Message in DDR mode, offset: 0xDC */
       uint8_t RESERVED_6[4];
  __IO uint32_t MDYNADDR;                          /**< Master Dynamic Address Register, offset: 0xE4 */
       uint8_t RESERVED_7[3860];
  __I  uint32_t SID;                               /**< Slave Module ID, offset: 0xFFC */
} I3C_Type;

/* ----------------------------------------------------------------------------
   -- I3C Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup I3C_Register_Masks I3C Register Masks
 * @{
 */

/*! @name MCONFIG - Master Configuration Register */
/*! @{ */

#define I3C_MCONFIG_MSTENA_MASK                  (0x3U)
#define I3C_MCONFIG_MSTENA_SHIFT                 (0U)
/*! MSTENA - Master enable
 *  0b00..MASTER_OFF
 *  0b01..MASTER_ON
 *  0b10..MASTER_CAPABLE
 *  0b11..
 */
#define I3C_MCONFIG_MSTENA(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_MSTENA_SHIFT)) & I3C_MCONFIG_MSTENA_MASK)

#define I3C_MCONFIG_DISTO_MASK                   (0x8U)
#define I3C_MCONFIG_DISTO_SHIFT                  (3U)
/*! DISTO - Disable Timeout
 */
#define I3C_MCONFIG_DISTO(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_DISTO_SHIFT)) & I3C_MCONFIG_DISTO_MASK)

#define I3C_MCONFIG_HKEEP_MASK                   (0x30U)
#define I3C_MCONFIG_HKEEP_SHIFT                  (4U)
/*! HKEEP - High-Keeper
 *  0b00..NONE
 *  0b01..WIRED_IN
 *  0b10..PASSIVE_SDA
 *  0b11..PASSIVE_ON_SDA_SCL
 */
#define I3C_MCONFIG_HKEEP(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_HKEEP_SHIFT)) & I3C_MCONFIG_HKEEP_MASK)

#define I3C_MCONFIG_ODSTOP_MASK                  (0x40U)
#define I3C_MCONFIG_ODSTOP_SHIFT                 (6U)
/*! ODSTOP - Open drain stop
 */
#define I3C_MCONFIG_ODSTOP(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODSTOP_SHIFT)) & I3C_MCONFIG_ODSTOP_MASK)

#define I3C_MCONFIG_PPBAUD_MASK                  (0xF00U)
#define I3C_MCONFIG_PPBAUD_SHIFT                 (8U)
/*! PPBAUD - Push-pull baud rate
 */
#define I3C_MCONFIG_PPBAUD(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPBAUD_SHIFT)) & I3C_MCONFIG_PPBAUD_MASK)

#define I3C_MCONFIG_PPLOW_MASK                   (0xF000U)
#define I3C_MCONFIG_PPLOW_SHIFT                  (12U)
/*! PPLOW - Push-Pull low
 */
#define I3C_MCONFIG_PPLOW(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPLOW_SHIFT)) & I3C_MCONFIG_PPLOW_MASK)

#define I3C_MCONFIG_ODBAUD_MASK                  (0xFF0000U)
#define I3C_MCONFIG_ODBAUD_SHIFT                 (16U)
/*! ODBAUD - Open drain baud rate
 */
#define I3C_MCONFIG_ODBAUD(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODBAUD_SHIFT)) & I3C_MCONFIG_ODBAUD_MASK)

#define I3C_MCONFIG_ODHPP_MASK                   (0x1000000U)
#define I3C_MCONFIG_ODHPP_SHIFT                  (24U)
/*! ODHPP - Open drain high push-pull
 */
#define I3C_MCONFIG_ODHPP(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODHPP_SHIFT)) & I3C_MCONFIG_ODHPP_MASK)

#define I3C_MCONFIG_SKEW_MASK                    (0xE000000U)
#define I3C_MCONFIG_SKEW_SHIFT                   (25U)
/*! SKEW - Skew
 */
#define I3C_MCONFIG_SKEW(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_SKEW_SHIFT)) & I3C_MCONFIG_SKEW_MASK)

#define I3C_MCONFIG_I2CBAUD_MASK                 (0xF0000000U)
#define I3C_MCONFIG_I2CBAUD_SHIFT                (28U)
/*! I2CBAUD - I2C baud rate
 */
#define I3C_MCONFIG_I2CBAUD(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_I2CBAUD_SHIFT)) & I3C_MCONFIG_I2CBAUD_MASK)
/*! @} */

/*! @name SCONFIG - Slave Configuration Register */
/*! @{ */

#define I3C_SCONFIG_SLVENA_MASK                  (0x1U)
#define I3C_SCONFIG_SLVENA_SHIFT                 (0U)
/*! SLVENA - Slave enable
 */
#define I3C_SCONFIG_SLVENA(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SLVENA_SHIFT)) & I3C_SCONFIG_SLVENA_MASK)

#define I3C_SCONFIG_NACK_MASK                    (0x2U)
#define I3C_SCONFIG_NACK_SHIFT                   (1U)
/*! NACK - Not acknowledge
 */
#define I3C_SCONFIG_NACK(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_NACK_SHIFT)) & I3C_SCONFIG_NACK_MASK)

#define I3C_SCONFIG_MATCHSS_MASK                 (0x4U)
#define I3C_SCONFIG_MATCHSS_SHIFT                (2U)
/*! MATCHSS - Match START or STOP
 */
#define I3C_SCONFIG_MATCHSS(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_MATCHSS_SHIFT)) & I3C_SCONFIG_MATCHSS_MASK)

#define I3C_SCONFIG_S0IGNORE_MASK                (0x8U)
#define I3C_SCONFIG_S0IGNORE_SHIFT               (3U)
/*! S0IGNORE - S0/S1 errors ignore
 */
#define I3C_SCONFIG_S0IGNORE(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_S0IGNORE_SHIFT)) & I3C_SCONFIG_S0IGNORE_MASK)

#define I3C_SCONFIG_DDROK_MASK                   (0x10U)
#define I3C_SCONFIG_DDROK_SHIFT                  (4U)
/*! DDROK - Double Data Rate OK
 */
#define I3C_SCONFIG_DDROK(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_DDROK_SHIFT)) & I3C_SCONFIG_DDROK_MASK)

#define I3C_SCONFIG_IDRAND_MASK                  (0x100U)
#define I3C_SCONFIG_IDRAND_SHIFT                 (8U)
/*! IDRAND - ID random
 */
#define I3C_SCONFIG_IDRAND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_IDRAND_SHIFT)) & I3C_SCONFIG_IDRAND_MASK)

#define I3C_SCONFIG_OFFLINE_MASK                 (0x200U)
#define I3C_SCONFIG_OFFLINE_SHIFT                (9U)
/*! OFFLINE - Offline
 */
#define I3C_SCONFIG_OFFLINE(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_OFFLINE_SHIFT)) & I3C_SCONFIG_OFFLINE_MASK)

#define I3C_SCONFIG_BAMATCH_MASK                 (0xFF0000U)
#define I3C_SCONFIG_BAMATCH_SHIFT                (16U)
/*! BAMATCH - Bus available match
 */
#define I3C_SCONFIG_BAMATCH(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_BAMATCH_SHIFT)) & I3C_SCONFIG_BAMATCH_MASK)

#define I3C_SCONFIG_SADDR_MASK                   (0xFE000000U)
#define I3C_SCONFIG_SADDR_SHIFT                  (25U)
/*! SADDR - Static address
 */
#define I3C_SCONFIG_SADDR(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SADDR_SHIFT)) & I3C_SCONFIG_SADDR_MASK)
/*! @} */

/*! @name SSTATUS - Slave Status Register */
/*! @{ */

#define I3C_SSTATUS_STNOTSTOP_MASK               (0x1U)
#define I3C_SSTATUS_STNOTSTOP_SHIFT              (0U)
/*! STNOTSTOP - Status not stop
 */
#define I3C_SSTATUS_STNOTSTOP(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STNOTSTOP_SHIFT)) & I3C_SSTATUS_STNOTSTOP_MASK)

#define I3C_SSTATUS_STMSG_MASK                   (0x2U)
#define I3C_SSTATUS_STMSG_SHIFT                  (1U)
/*! STMSG - Status message
 */
#define I3C_SSTATUS_STMSG(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STMSG_SHIFT)) & I3C_SSTATUS_STMSG_MASK)

#define I3C_SSTATUS_STCCCH_MASK                  (0x4U)
#define I3C_SSTATUS_STCCCH_SHIFT                 (2U)
/*! STCCCH - Status Common Command Code Handler
 */
#define I3C_SSTATUS_STCCCH(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STCCCH_SHIFT)) & I3C_SSTATUS_STCCCH_MASK)

#define I3C_SSTATUS_STREQRD_MASK                 (0x8U)
#define I3C_SSTATUS_STREQRD_SHIFT                (3U)
/*! STREQRD - Status required
 */
#define I3C_SSTATUS_STREQRD(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STREQRD_SHIFT)) & I3C_SSTATUS_STREQRD_MASK)

#define I3C_SSTATUS_STREQWR_MASK                 (0x10U)
#define I3C_SSTATUS_STREQWR_SHIFT                (4U)
/*! STREQWR - Status request write
 */
#define I3C_SSTATUS_STREQWR(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STREQWR_SHIFT)) & I3C_SSTATUS_STREQWR_MASK)

#define I3C_SSTATUS_STDAA_MASK                   (0x20U)
#define I3C_SSTATUS_STDAA_SHIFT                  (5U)
/*! STDAA - Status Dynamic Address Assignment
 */
#define I3C_SSTATUS_STDAA(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STDAA_SHIFT)) & I3C_SSTATUS_STDAA_MASK)

#define I3C_SSTATUS_STHDR_MASK                   (0x40U)
#define I3C_SSTATUS_STHDR_SHIFT                  (6U)
/*! STHDR - Status High Data Rate
 */
#define I3C_SSTATUS_STHDR(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STHDR_SHIFT)) & I3C_SSTATUS_STHDR_MASK)

#define I3C_SSTATUS_START_MASK                   (0x100U)
#define I3C_SSTATUS_START_SHIFT                  (8U)
/*! START - Start
 */
#define I3C_SSTATUS_START(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_START_SHIFT)) & I3C_SSTATUS_START_MASK)

#define I3C_SSTATUS_MATCHED_MASK                 (0x200U)
#define I3C_SSTATUS_MATCHED_SHIFT                (9U)
/*! MATCHED - Matched
 */
#define I3C_SSTATUS_MATCHED(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_MATCHED_SHIFT)) & I3C_SSTATUS_MATCHED_MASK)

#define I3C_SSTATUS_STOP_MASK                    (0x400U)
#define I3C_SSTATUS_STOP_SHIFT                   (10U)
/*! STOP - Stop
 */
#define I3C_SSTATUS_STOP(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STOP_SHIFT)) & I3C_SSTATUS_STOP_MASK)

#define I3C_SSTATUS_RX_PEND_MASK                 (0x800U)
#define I3C_SSTATUS_RX_PEND_SHIFT                (11U)
/*! RX_PEND - Received message pending
 */
#define I3C_SSTATUS_RX_PEND(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_RX_PEND_SHIFT)) & I3C_SSTATUS_RX_PEND_MASK)

#define I3C_SSTATUS_TXNOTFULL_MASK               (0x1000U)
#define I3C_SSTATUS_TXNOTFULL_SHIFT              (12U)
/*! TXNOTFULL - Transmit buffer is not full
 */
#define I3C_SSTATUS_TXNOTFULL(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_TXNOTFULL_SHIFT)) & I3C_SSTATUS_TXNOTFULL_MASK)

#define I3C_SSTATUS_DACHG_MASK                   (0x2000U)
#define I3C_SSTATUS_DACHG_SHIFT                  (13U)
/*! DACHG - DACHG
 */
#define I3C_SSTATUS_DACHG(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_DACHG_SHIFT)) & I3C_SSTATUS_DACHG_MASK)

#define I3C_SSTATUS_CCC_MASK                     (0x4000U)
#define I3C_SSTATUS_CCC_SHIFT                    (14U)
/*! CCC - Common Command Code
 */
#define I3C_SSTATUS_CCC(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_CCC_SHIFT)) & I3C_SSTATUS_CCC_MASK)

#define I3C_SSTATUS_ERRWARN_MASK                 (0x8000U)
#define I3C_SSTATUS_ERRWARN_SHIFT                (15U)
/*! ERRWARN - Error warning
 */
#define I3C_SSTATUS_ERRWARN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_ERRWARN_SHIFT)) & I3C_SSTATUS_ERRWARN_MASK)

#define I3C_SSTATUS_HDRMATCH_MASK                (0x10000U)
#define I3C_SSTATUS_HDRMATCH_SHIFT               (16U)
/*! HDRMATCH - High Data Rate command match
 */
#define I3C_SSTATUS_HDRMATCH(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_HDRMATCH_SHIFT)) & I3C_SSTATUS_HDRMATCH_MASK)

#define I3C_SSTATUS_CHANDLED_MASK                (0x20000U)
#define I3C_SSTATUS_CHANDLED_SHIFT               (17U)
/*! CHANDLED - Common-Command-Code handled
 */
#define I3C_SSTATUS_CHANDLED(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_CHANDLED_SHIFT)) & I3C_SSTATUS_CHANDLED_MASK)

#define I3C_SSTATUS_EVENT_MASK                   (0x40000U)
#define I3C_SSTATUS_EVENT_SHIFT                  (18U)
/*! EVENT - Event
 */
#define I3C_SSTATUS_EVENT(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_EVENT_SHIFT)) & I3C_SSTATUS_EVENT_MASK)

#define I3C_SSTATUS_EVDET_MASK                   (0x300000U)
#define I3C_SSTATUS_EVDET_SHIFT                  (20U)
/*! EVDET - Event details
 *  0b00..NONE
 *  0b01..NO_REQUEST
 *  0b10..NACKED
 *  0b11..ACKED
 */
#define I3C_SSTATUS_EVDET(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_EVDET_SHIFT)) & I3C_SSTATUS_EVDET_MASK)

#define I3C_SSTATUS_IBIDIS_MASK                  (0x1000000U)
#define I3C_SSTATUS_IBIDIS_SHIFT                 (24U)
/*! IBIDIS - In-Band Interrupts are disabled
 */
#define I3C_SSTATUS_IBIDIS(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_IBIDIS_SHIFT)) & I3C_SSTATUS_IBIDIS_MASK)

#define I3C_SSTATUS_MRDIS_MASK                   (0x2000000U)
#define I3C_SSTATUS_MRDIS_SHIFT                  (25U)
/*! MRDIS - Master requests are disabled
 */
#define I3C_SSTATUS_MRDIS(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_MRDIS_SHIFT)) & I3C_SSTATUS_MRDIS_MASK)

#define I3C_SSTATUS_HJDIS_MASK                   (0x8000000U)
#define I3C_SSTATUS_HJDIS_SHIFT                  (27U)
/*! HJDIS - Hot-Join is disabled
 */
#define I3C_SSTATUS_HJDIS(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_HJDIS_SHIFT)) & I3C_SSTATUS_HJDIS_MASK)

#define I3C_SSTATUS_ACTSTATE_MASK                (0x30000000U)
#define I3C_SSTATUS_ACTSTATE_SHIFT               (28U)
/*! ACTSTATE - Activity state from Common Command Codes (CCC)
 *  0b00..NO_LATENCY
 *  0b01..LATENCY_1MS
 *  0b10..LATENCY_100MS
 *  0b11..LATENCY_10S
 */
#define I3C_SSTATUS_ACTSTATE(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_ACTSTATE_SHIFT)) & I3C_SSTATUS_ACTSTATE_MASK)

#define I3C_SSTATUS_TIMECTRL_MASK                (0xC0000000U)
#define I3C_SSTATUS_TIMECTRL_SHIFT               (30U)
/*! TIMECTRL - Time control
 *  0b00..NO_TIME_CONTROL
 *  0b01..
 *  0b10..ASYNC_MODE
 *  0b11..
 */
#define I3C_SSTATUS_TIMECTRL(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_TIMECTRL_SHIFT)) & I3C_SSTATUS_TIMECTRL_MASK)
/*! @} */

/*! @name SCTRL - Slave Control Register */
/*! @{ */

#define I3C_SCTRL_EVENT_MASK                     (0x3U)
#define I3C_SCTRL_EVENT_SHIFT                    (0U)
/*! EVENT - EVENT
 *  0b00..NORMAL_MODE
 *  0b01..IBI
 *  0b10..MASTER_REQUEST
 *  0b11..HOT_JOIN_REQUEST
 */
#define I3C_SCTRL_EVENT(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_EVENT_SHIFT)) & I3C_SCTRL_EVENT_MASK)

#define I3C_SCTRL_IBIDATA_MASK                   (0xFF00U)
#define I3C_SCTRL_IBIDATA_SHIFT                  (8U)
/*! IBIDATA - In-Band Interrupt Data
 */
#define I3C_SCTRL_IBIDATA(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_IBIDATA_SHIFT)) & I3C_SCTRL_IBIDATA_MASK)

#define I3C_SCTRL_PENDINT_MASK                   (0xF0000U)
#define I3C_SCTRL_PENDINT_SHIFT                  (16U)
/*! PENDINT - Pending interrupt
 */
#define I3C_SCTRL_PENDINT(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_PENDINT_SHIFT)) & I3C_SCTRL_PENDINT_MASK)

#define I3C_SCTRL_ACTSTATE_MASK                  (0x300000U)
#define I3C_SCTRL_ACTSTATE_SHIFT                 (20U)
/*! ACTSTATE - Activity state (of slave)
 */
#define I3C_SCTRL_ACTSTATE(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_ACTSTATE_SHIFT)) & I3C_SCTRL_ACTSTATE_MASK)

#define I3C_SCTRL_VENDINFO_MASK                  (0xFF000000U)
#define I3C_SCTRL_VENDINFO_SHIFT                 (24U)
/*! VENDINFO - Vendor information
 */
#define I3C_SCTRL_VENDINFO(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_VENDINFO_SHIFT)) & I3C_SCTRL_VENDINFO_MASK)
/*! @} */

/*! @name SINTSET - Slave Interrupt Set Register */
/*! @{ */

#define I3C_SINTSET_START_MASK                   (0x100U)
#define I3C_SINTSET_START_SHIFT                  (8U)
/*! START - Start interrupt enable
 */
#define I3C_SINTSET_START(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_START_SHIFT)) & I3C_SINTSET_START_MASK)

#define I3C_SINTSET_MATCHED_MASK                 (0x200U)
#define I3C_SINTSET_MATCHED_SHIFT                (9U)
/*! MATCHED - Match interrupt enable
 */
#define I3C_SINTSET_MATCHED(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_MATCHED_SHIFT)) & I3C_SINTSET_MATCHED_MASK)

#define I3C_SINTSET_STOP_MASK                    (0x400U)
#define I3C_SINTSET_STOP_SHIFT                   (10U)
/*! STOP - Stop interrupt enable
 */
#define I3C_SINTSET_STOP(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_STOP_SHIFT)) & I3C_SINTSET_STOP_MASK)

#define I3C_SINTSET_RXPEND_MASK                  (0x800U)
#define I3C_SINTSET_RXPEND_SHIFT                 (11U)
/*! RXPEND - Receive interrupt enable
 */
#define I3C_SINTSET_RXPEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_RXPEND_SHIFT)) & I3C_SINTSET_RXPEND_MASK)

#define I3C_SINTSET_TXSEND_MASK                  (0x1000U)
#define I3C_SINTSET_TXSEND_SHIFT                 (12U)
/*! TXSEND - Transmit interrupt enable
 */
#define I3C_SINTSET_TXSEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_TXSEND_SHIFT)) & I3C_SINTSET_TXSEND_MASK)

#define I3C_SINTSET_DACHG_MASK                   (0x2000U)
#define I3C_SINTSET_DACHG_SHIFT                  (13U)
/*! DACHG - Dynamic address change interrupt enable
 */
#define I3C_SINTSET_DACHG(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_DACHG_SHIFT)) & I3C_SINTSET_DACHG_MASK)

#define I3C_SINTSET_CCC_MASK                     (0x4000U)
#define I3C_SINTSET_CCC_SHIFT                    (14U)
/*! CCC - Common Command Code (CCC) (that was not handled by I3C module) interrupt enable
 */
#define I3C_SINTSET_CCC(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_CCC_SHIFT)) & I3C_SINTSET_CCC_MASK)

#define I3C_SINTSET_ERRWARN_MASK                 (0x8000U)
#define I3C_SINTSET_ERRWARN_SHIFT                (15U)
/*! ERRWARN - Error/warning interrupt enable
 */
#define I3C_SINTSET_ERRWARN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_ERRWARN_SHIFT)) & I3C_SINTSET_ERRWARN_MASK)

#define I3C_SINTSET_DDRMATCHED_MASK              (0x10000U)
#define I3C_SINTSET_DDRMATCHED_SHIFT             (16U)
/*! DDRMATCHED - Double Data Rate (DDR) interrupt enable
 */
#define I3C_SINTSET_DDRMATCHED(x)                (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_DDRMATCHED_SHIFT)) & I3C_SINTSET_DDRMATCHED_MASK)

#define I3C_SINTSET_CHANDLED_MASK                (0x20000U)
#define I3C_SINTSET_CHANDLED_SHIFT               (17U)
/*! CHANDLED - Common Command Code (CCC) (that was handled by I3C module) interrupt enable
 */
#define I3C_SINTSET_CHANDLED(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_CHANDLED_SHIFT)) & I3C_SINTSET_CHANDLED_MASK)

#define I3C_SINTSET_EVENT_MASK                   (0x40000U)
#define I3C_SINTSET_EVENT_SHIFT                  (18U)
/*! EVENT - Event interrupt enable
 */
#define I3C_SINTSET_EVENT(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_EVENT_SHIFT)) & I3C_SINTSET_EVENT_MASK)
/*! @} */

/*! @name SINTCLR - Slave Interrupt Clear Register */
/*! @{ */

#define I3C_SINTCLR_START_MASK                   (0x100U)
#define I3C_SINTCLR_START_SHIFT                  (8U)
/*! START - START interrupt enable clear
 */
#define I3C_SINTCLR_START(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_START_SHIFT)) & I3C_SINTCLR_START_MASK)

#define I3C_SINTCLR_MATCHED_MASK                 (0x200U)
#define I3C_SINTCLR_MATCHED_SHIFT                (9U)
/*! MATCHED - MATCHED interrupt enable clear
 */
#define I3C_SINTCLR_MATCHED(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_MATCHED_SHIFT)) & I3C_SINTCLR_MATCHED_MASK)

#define I3C_SINTCLR_STOP_MASK                    (0x400U)
#define I3C_SINTCLR_STOP_SHIFT                   (10U)
/*! STOP - STOP interrupt enable clear
 */
#define I3C_SINTCLR_STOP(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_STOP_SHIFT)) & I3C_SINTCLR_STOP_MASK)

#define I3C_SINTCLR_RXPEND_MASK                  (0x800U)
#define I3C_SINTCLR_RXPEND_SHIFT                 (11U)
/*! RXPEND - RXPEND interrupt enable clear
 */
#define I3C_SINTCLR_RXPEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_RXPEND_SHIFT)) & I3C_SINTCLR_RXPEND_MASK)

#define I3C_SINTCLR_TXSEND_MASK                  (0x1000U)
#define I3C_SINTCLR_TXSEND_SHIFT                 (12U)
/*! TXSEND - TXSEND interrupt enable clear
 */
#define I3C_SINTCLR_TXSEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_TXSEND_SHIFT)) & I3C_SINTCLR_TXSEND_MASK)

#define I3C_SINTCLR_DACHG_MASK                   (0x2000U)
#define I3C_SINTCLR_DACHG_SHIFT                  (13U)
/*! DACHG - DACHG interrupt enable clear
 */
#define I3C_SINTCLR_DACHG(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_DACHG_SHIFT)) & I3C_SINTCLR_DACHG_MASK)

#define I3C_SINTCLR_CCC_MASK                     (0x4000U)
#define I3C_SINTCLR_CCC_SHIFT                    (14U)
/*! CCC - CCC interrupt enable clear
 */
#define I3C_SINTCLR_CCC(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_CCC_SHIFT)) & I3C_SINTCLR_CCC_MASK)

#define I3C_SINTCLR_ERRWARN_MASK                 (0x8000U)
#define I3C_SINTCLR_ERRWARN_SHIFT                (15U)
/*! ERRWARN - ERRWARN interrupt enable clear
 */
#define I3C_SINTCLR_ERRWARN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_ERRWARN_SHIFT)) & I3C_SINTCLR_ERRWARN_MASK)

#define I3C_SINTCLR_DDRMATCHED_MASK              (0x10000U)
#define I3C_SINTCLR_DDRMATCHED_SHIFT             (16U)
/*! DDRMATCHED - DDRMATCHED interrupt enable clear
 */
#define I3C_SINTCLR_DDRMATCHED(x)                (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_DDRMATCHED_SHIFT)) & I3C_SINTCLR_DDRMATCHED_MASK)

#define I3C_SINTCLR_CHANDLED_MASK                (0x20000U)
#define I3C_SINTCLR_CHANDLED_SHIFT               (17U)
/*! CHANDLED - CHANDLED interrupt enable clear
 */
#define I3C_SINTCLR_CHANDLED(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_CHANDLED_SHIFT)) & I3C_SINTCLR_CHANDLED_MASK)

#define I3C_SINTCLR_EVENT_MASK                   (0x40000U)
#define I3C_SINTCLR_EVENT_SHIFT                  (18U)
/*! EVENT - EVENT interrupt enable clear
 */
#define I3C_SINTCLR_EVENT(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_EVENT_SHIFT)) & I3C_SINTCLR_EVENT_MASK)
/*! @} */

/*! @name SINTMASKED - Slave Interrupt Mask Register */
/*! @{ */

#define I3C_SINTMASKED_START_MASK                (0x100U)
#define I3C_SINTMASKED_START_SHIFT               (8U)
/*! START - START interrupt mask
 */
#define I3C_SINTMASKED_START(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_START_SHIFT)) & I3C_SINTMASKED_START_MASK)

#define I3C_SINTMASKED_MATCHED_MASK              (0x200U)
#define I3C_SINTMASKED_MATCHED_SHIFT             (9U)
/*! MATCHED - MATCHED interrupt mask
 */
#define I3C_SINTMASKED_MATCHED(x)                (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_MATCHED_SHIFT)) & I3C_SINTMASKED_MATCHED_MASK)

#define I3C_SINTMASKED_STOP_MASK                 (0x400U)
#define I3C_SINTMASKED_STOP_SHIFT                (10U)
/*! STOP - STOP interrupt mask
 */
#define I3C_SINTMASKED_STOP(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_STOP_SHIFT)) & I3C_SINTMASKED_STOP_MASK)

#define I3C_SINTMASKED_RXPEND_MASK               (0x800U)
#define I3C_SINTMASKED_RXPEND_SHIFT              (11U)
/*! RXPEND - RXPEND interrupt mask
 */
#define I3C_SINTMASKED_RXPEND(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_RXPEND_SHIFT)) & I3C_SINTMASKED_RXPEND_MASK)

#define I3C_SINTMASKED_TXSEND_MASK               (0x1000U)
#define I3C_SINTMASKED_TXSEND_SHIFT              (12U)
/*! TXSEND - TXSEND interrupt mask
 */
#define I3C_SINTMASKED_TXSEND(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_TXSEND_SHIFT)) & I3C_SINTMASKED_TXSEND_MASK)

#define I3C_SINTMASKED_DACHG_MASK                (0x2000U)
#define I3C_SINTMASKED_DACHG_SHIFT               (13U)
/*! DACHG - DACHG interrupt mask
 */
#define I3C_SINTMASKED_DACHG(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_DACHG_SHIFT)) & I3C_SINTMASKED_DACHG_MASK)

#define I3C_SINTMASKED_CCC_MASK                  (0x4000U)
#define I3C_SINTMASKED_CCC_SHIFT                 (14U)
/*! CCC - CCC interrupt mask
 */
#define I3C_SINTMASKED_CCC(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_CCC_SHIFT)) & I3C_SINTMASKED_CCC_MASK)

#define I3C_SINTMASKED_ERRWARN_MASK              (0x8000U)
#define I3C_SINTMASKED_ERRWARN_SHIFT             (15U)
/*! ERRWARN - ERRWARN interrupt mask
 */
#define I3C_SINTMASKED_ERRWARN(x)                (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_ERRWARN_SHIFT)) & I3C_SINTMASKED_ERRWARN_MASK)

#define I3C_SINTMASKED_DDRMATCHED_MASK           (0x10000U)
#define I3C_SINTMASKED_DDRMATCHED_SHIFT          (16U)
/*! DDRMATCHED - DDRMATCHED interrupt mask
 */
#define I3C_SINTMASKED_DDRMATCHED(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_DDRMATCHED_SHIFT)) & I3C_SINTMASKED_DDRMATCHED_MASK)

#define I3C_SINTMASKED_CHANDLED_MASK             (0x20000U)
#define I3C_SINTMASKED_CHANDLED_SHIFT            (17U)
/*! CHANDLED - CHANDLED interrupt mask
 */
#define I3C_SINTMASKED_CHANDLED(x)               (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_CHANDLED_SHIFT)) & I3C_SINTMASKED_CHANDLED_MASK)

#define I3C_SINTMASKED_EVENT_MASK                (0x40000U)
#define I3C_SINTMASKED_EVENT_SHIFT               (18U)
/*! EVENT - EVENT interrupt mask
 */
#define I3C_SINTMASKED_EVENT(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_EVENT_SHIFT)) & I3C_SINTMASKED_EVENT_MASK)
/*! @} */

/*! @name SERRWARN - Slave Errors and Warnings Register */
/*! @{ */

#define I3C_SERRWARN_ORUN_MASK                   (0x1U)
#define I3C_SERRWARN_ORUN_SHIFT                  (0U)
/*! ORUN - Overrun error
 */
#define I3C_SERRWARN_ORUN(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_ORUN_SHIFT)) & I3C_SERRWARN_ORUN_MASK)

#define I3C_SERRWARN_URUN_MASK                   (0x2U)
#define I3C_SERRWARN_URUN_SHIFT                  (1U)
/*! URUN - Underrun error
 */
#define I3C_SERRWARN_URUN(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUN_SHIFT)) & I3C_SERRWARN_URUN_MASK)

#define I3C_SERRWARN_URUNNACK_MASK               (0x4U)
#define I3C_SERRWARN_URUNNACK_SHIFT              (2U)
/*! URUNNACK - Underrun and Not Acknowledged (NACKed) error
 */
#define I3C_SERRWARN_URUNNACK(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUNNACK_SHIFT)) & I3C_SERRWARN_URUNNACK_MASK)

#define I3C_SERRWARN_TERM_MASK                   (0x8U)
#define I3C_SERRWARN_TERM_SHIFT                  (3U)
/*! TERM - Terminated error
 */
#define I3C_SERRWARN_TERM(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_TERM_SHIFT)) & I3C_SERRWARN_TERM_MASK)

#define I3C_SERRWARN_INVSTART_MASK               (0x10U)
#define I3C_SERRWARN_INVSTART_SHIFT              (4U)
/*! INVSTART - Invalid start error
 */
#define I3C_SERRWARN_INVSTART(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_INVSTART_SHIFT)) & I3C_SERRWARN_INVSTART_MASK)

#define I3C_SERRWARN_SPAR_MASK                   (0x100U)
#define I3C_SERRWARN_SPAR_SHIFT                  (8U)
/*! SPAR - SDR parity error
 */
#define I3C_SERRWARN_SPAR(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_SPAR_SHIFT)) & I3C_SERRWARN_SPAR_MASK)

#define I3C_SERRWARN_HPAR_MASK                   (0x200U)
#define I3C_SERRWARN_HPAR_SHIFT                  (9U)
/*! HPAR - HDR parity error
 */
#define I3C_SERRWARN_HPAR(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_HPAR_SHIFT)) & I3C_SERRWARN_HPAR_MASK)

#define I3C_SERRWARN_HCRC_MASK                   (0x400U)
#define I3C_SERRWARN_HCRC_SHIFT                  (10U)
/*! HCRC - HDR-DDR CRC error
 */
#define I3C_SERRWARN_HCRC(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_HCRC_SHIFT)) & I3C_SERRWARN_HCRC_MASK)

#define I3C_SERRWARN_S0S1_MASK                   (0x800U)
#define I3C_SERRWARN_S0S1_SHIFT                  (11U)
/*! S0S1 - S0 or S1 error
 */
#define I3C_SERRWARN_S0S1(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_S0S1_SHIFT)) & I3C_SERRWARN_S0S1_MASK)

#define I3C_SERRWARN_OREAD_MASK                  (0x10000U)
#define I3C_SERRWARN_OREAD_SHIFT                 (16U)
/*! OREAD - Over-read error
 */
#define I3C_SERRWARN_OREAD(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OREAD_SHIFT)) & I3C_SERRWARN_OREAD_MASK)

#define I3C_SERRWARN_OWRITE_MASK                 (0x20000U)
#define I3C_SERRWARN_OWRITE_SHIFT                (17U)
/*! OWRITE - Over-write error
 */
#define I3C_SERRWARN_OWRITE(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OWRITE_SHIFT)) & I3C_SERRWARN_OWRITE_MASK)
/*! @} */

/*! @name SDMACTRL - Slave DMA Control Register */
/*! @{ */

#define I3C_SDMACTRL_DMAFB_MASK                  (0x3U)
#define I3C_SDMACTRL_DMAFB_SHIFT                 (0U)
/*! DMAFB - DMA Read (From-bus) trigger
 *  0b00..DMA not used
 *  0b01..DMA is enabled for 1 frame
 *  0b10..DMA enable
 */
#define I3C_SDMACTRL_DMAFB(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMAFB_SHIFT)) & I3C_SDMACTRL_DMAFB_MASK)

#define I3C_SDMACTRL_DMATB_MASK                  (0xCU)
#define I3C_SDMACTRL_DMATB_SHIFT                 (2U)
/*! DMATB - DMA Write (To-bus) trigger
 *  0b00..NOT_USED
 *  0b01..ENABLE_ONE_FRAME
 *  0b10..ENABLE
 */
#define I3C_SDMACTRL_DMATB(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMATB_SHIFT)) & I3C_SDMACTRL_DMATB_MASK)

#define I3C_SDMACTRL_DMAWIDTH_MASK               (0x30U)
#define I3C_SDMACTRL_DMAWIDTH_SHIFT              (4U)
/*! DMAWIDTH - Width of DMA operations
 *  0b00..BYTE
 *  0b01..BYTE_AGAIN
 *  0b10..HALF_WORD: Half word (16 bits). This will make sure that 2 bytes are free/available in the FIFO.
 *  0b11..
 */
#define I3C_SDMACTRL_DMAWIDTH(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMAWIDTH_SHIFT)) & I3C_SDMACTRL_DMAWIDTH_MASK)
/*! @} */

/*! @name SDATACTRL - Slave Data Control Register */
/*! @{ */

#define I3C_SDATACTRL_FLUSHTB_MASK               (0x1U)
#define I3C_SDATACTRL_FLUSHTB_SHIFT              (0U)
/*! FLUSHTB - Flush the to-bus buffer/FIFO
 */
#define I3C_SDATACTRL_FLUSHTB(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_FLUSHTB_SHIFT)) & I3C_SDATACTRL_FLUSHTB_MASK)

#define I3C_SDATACTRL_FLUSHFB_MASK               (0x2U)
#define I3C_SDATACTRL_FLUSHFB_SHIFT              (1U)
/*! FLUSHFB - Flushes the from-bus buffer/FIFO
 */
#define I3C_SDATACTRL_FLUSHFB(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_FLUSHFB_SHIFT)) & I3C_SDATACTRL_FLUSHFB_MASK)

#define I3C_SDATACTRL_UNLOCK_MASK                (0x8U)
#define I3C_SDATACTRL_UNLOCK_SHIFT               (3U)
/*! UNLOCK - Unlock
 */
#define I3C_SDATACTRL_UNLOCK(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_UNLOCK_SHIFT)) & I3C_SDATACTRL_UNLOCK_MASK)

#define I3C_SDATACTRL_TXTRIG_MASK                (0x30U)
#define I3C_SDATACTRL_TXTRIG_SHIFT               (4U)
/*! TXTRIG - Trigger level for TX FIFO emptiness
 *  0b00..Trigger on empty
 *  0b01..Trigger on ¼ full or less
 *  0b10..Trigger on .5 full or less
 *  0b11..Trigger on 1 less than full or less (Default)
 */
#define I3C_SDATACTRL_TXTRIG(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXTRIG_SHIFT)) & I3C_SDATACTRL_TXTRIG_MASK)

#define I3C_SDATACTRL_RXTRIG_MASK                (0xC0U)
#define I3C_SDATACTRL_RXTRIG_SHIFT               (6U)
/*! RXTRIG - Trigger level for RX FIFO fullness
 *  0b00..Trigger on not empty
 *  0b01..Trigger on ¼ or more full
 *  0b10..Trigger on .5 or more full
 *  0b11..Trigger on 3/4 or more full
 */
#define I3C_SDATACTRL_RXTRIG(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXTRIG_SHIFT)) & I3C_SDATACTRL_RXTRIG_MASK)

#define I3C_SDATACTRL_TXCOUNT_MASK               (0x1F0000U)
#define I3C_SDATACTRL_TXCOUNT_SHIFT              (16U)
/*! TXCOUNT - Count of bytes in TX
 */
#define I3C_SDATACTRL_TXCOUNT(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXCOUNT_SHIFT)) & I3C_SDATACTRL_TXCOUNT_MASK)

#define I3C_SDATACTRL_RXCOUNT_MASK               (0x1F000000U)
#define I3C_SDATACTRL_RXCOUNT_SHIFT              (24U)
/*! RXCOUNT - Count of bytes in RX
 */
#define I3C_SDATACTRL_RXCOUNT(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXCOUNT_SHIFT)) & I3C_SDATACTRL_RXCOUNT_MASK)

#define I3C_SDATACTRL_TXFULL_MASK                (0x40000000U)
#define I3C_SDATACTRL_TXFULL_SHIFT               (30U)
/*! TXFULL - TX is full
 *  0b1..TX is full
 *  0b0..TX is not full
 */
#define I3C_SDATACTRL_TXFULL(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXFULL_SHIFT)) & I3C_SDATACTRL_TXFULL_MASK)

#define I3C_SDATACTRL_RXEMPTY_MASK               (0x80000000U)
#define I3C_SDATACTRL_RXEMPTY_SHIFT              (31U)
/*! RXEMPTY - RX is empty
 *  0b1..RX is empty
 *  0b0..RX is not empty
 */
#define I3C_SDATACTRL_RXEMPTY(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXEMPTY_SHIFT)) & I3C_SDATACTRL_RXEMPTY_MASK)
/*! @} */

/*! @name SWDATAB - Slave Write Data Byte Register */
/*! @{ */

#define I3C_SWDATAB_DATA_MASK                    (0xFFU)
#define I3C_SWDATAB_DATA_SHIFT                   (0U)
/*! DATA - The data byte to send to the master
 */
#define I3C_SWDATAB_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_DATA_SHIFT)) & I3C_SWDATAB_DATA_MASK)

#define I3C_SWDATAB_END_MASK                     (0x100U)
#define I3C_SWDATAB_END_SHIFT                    (8U)
/*! END - End
 */
#define I3C_SWDATAB_END(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_END_SHIFT)) & I3C_SWDATAB_END_MASK)

#define I3C_SWDATAB_END_ALSO_MASK                (0x10000U)
#define I3C_SWDATAB_END_ALSO_SHIFT               (16U)
/*! END_ALSO - End also
 */
#define I3C_SWDATAB_END_ALSO(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_END_ALSO_SHIFT)) & I3C_SWDATAB_END_ALSO_MASK)
/*! @} */

/*! @name SWDATABE - Slave Write Data Byte End */
/*! @{ */

#define I3C_SWDATABE_DATA_MASK                   (0xFFU)
#define I3C_SWDATABE_DATA_SHIFT                  (0U)
/*! DATA - The data byte to send to the master
 */
#define I3C_SWDATABE_DATA(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SWDATABE_DATA_SHIFT)) & I3C_SWDATABE_DATA_MASK)
/*! @} */

/*! @name SWDATAH - Slave Write Data Half-word Register */
/*! @{ */

#define I3C_SWDATAH_DATA0_MASK                   (0xFFU)
#define I3C_SWDATAH_DATA0_SHIFT                  (0U)
/*! DATA0 - The 1st byte to send to the master
 */
#define I3C_SWDATAH_DATA0(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_DATA0_SHIFT)) & I3C_SWDATAH_DATA0_MASK)

#define I3C_SWDATAH_DATA1_MASK                   (0xFF00U)
#define I3C_SWDATAH_DATA1_SHIFT                  (8U)
/*! DATA1 - The 2nd byte to send to the master
 */
#define I3C_SWDATAH_DATA1(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_DATA1_SHIFT)) & I3C_SWDATAH_DATA1_MASK)

#define I3C_SWDATAH_END_MASK                     (0x10000U)
#define I3C_SWDATAH_END_SHIFT                    (16U)
/*! END - End of message
 */
#define I3C_SWDATAH_END(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_END_SHIFT)) & I3C_SWDATAH_END_MASK)
/*! @} */

/*! @name SWDATAHE - Slave Write Data Half-word End Register */
/*! @{ */

#define I3C_SWDATAHE_DATA0_MASK                  (0xFFU)
#define I3C_SWDATAHE_DATA0_SHIFT                 (0U)
/*! DATA0 - The 1st byte to send to the master
 */
#define I3C_SWDATAHE_DATA0(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAHE_DATA0_SHIFT)) & I3C_SWDATAHE_DATA0_MASK)

#define I3C_SWDATAHE_DATA1_MASK                  (0xFF00U)
#define I3C_SWDATAHE_DATA1_SHIFT                 (8U)
/*! DATA1 - The 2nd byte to send to the master
 */
#define I3C_SWDATAHE_DATA1(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAHE_DATA1_SHIFT)) & I3C_SWDATAHE_DATA1_MASK)
/*! @} */

/*! @name SRDATAB - Slave Read Data Byte Register */
/*! @{ */

#define I3C_SRDATAB_DATA0_MASK                   (0xFFU)
#define I3C_SRDATAB_DATA0_SHIFT                  (0U)
/*! DATA0 - Byte read from the master
 */
#define I3C_SRDATAB_DATA0(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAB_DATA0_SHIFT)) & I3C_SRDATAB_DATA0_MASK)
/*! @} */

/*! @name SRDATAH - Slave Read Data Half-word Register */
/*! @{ */

#define I3C_SRDATAH_LSB_MASK                     (0xFFU)
#define I3C_SRDATAH_LSB_SHIFT                    (0U)
/*! LSB - The 1st byte read from the slave
 */
#define I3C_SRDATAH_LSB(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAH_LSB_SHIFT)) & I3C_SRDATAH_LSB_MASK)

#define I3C_SRDATAH_MSB_MASK                     (0xFF00U)
#define I3C_SRDATAH_MSB_SHIFT                    (8U)
/*! MSB - The 2nd byte read from the slave
 */
#define I3C_SRDATAH_MSB(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAH_MSB_SHIFT)) & I3C_SRDATAH_MSB_MASK)
/*! @} */

/*! @name SCAPABILITIES - Slave Capabilities Register */
/*! @{ */

#define I3C_SCAPABILITIES_IDENA_MASK             (0x3U)
#define I3C_SCAPABILITIES_IDENA_SHIFT            (0U)
/*! IDENA - ID 48b handler
 *  0b00..APPLICATION
 *  0b01..HW
 *  0b10..HW_BUT
 *  0b11..PARTNO
 */
#define I3C_SCAPABILITIES_IDENA(x)               (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IDENA_SHIFT)) & I3C_SCAPABILITIES_IDENA_MASK)

#define I3C_SCAPABILITIES_IDREG_MASK             (0x3CU)
#define I3C_SCAPABILITIES_IDREG_SHIFT            (2U)
/*! IDREG - ID register
 */
#define I3C_SCAPABILITIES_IDREG(x)               (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IDREG_SHIFT)) & I3C_SCAPABILITIES_IDREG_MASK)

#define I3C_SCAPABILITIES_HDRSUPP_MASK           (0x1C0U)
#define I3C_SCAPABILITIES_HDRSUPP_SHIFT          (6U)
/*! HDRSUPP - HDR support
 */
#define I3C_SCAPABILITIES_HDRSUPP(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_HDRSUPP_SHIFT)) & I3C_SCAPABILITIES_HDRSUPP_MASK)

#define I3C_SCAPABILITIES_MASTER_MASK            (0x200U)
#define I3C_SCAPABILITIES_MASTER_SHIFT           (9U)
/*! MASTER - Master
 *  0b0..MASTERNOTSUPPORTED
 *  0b1..MASTERSUPPORTED
 */
#define I3C_SCAPABILITIES_MASTER(x)              (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_MASTER_SHIFT)) & I3C_SCAPABILITIES_MASTER_MASK)

#define I3C_SCAPABILITIES_SADDR_MASK             (0xC00U)
#define I3C_SCAPABILITIES_SADDR_SHIFT            (10U)
/*! SADDR - Static address
 *  0b00..NO_STATIC
 *  0b01..STATIC
 *  0b10..HW_CONTROL
 *  0b11..CONFIG
 */
#define I3C_SCAPABILITIES_SADDR(x)               (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_SADDR_SHIFT)) & I3C_SCAPABILITIES_SADDR_MASK)

#define I3C_SCAPABILITIES_CCCHANDLE_MASK         (0xF000U)
#define I3C_SCAPABILITIES_CCCHANDLE_SHIFT        (12U)
/*! CCCHANDLE - Common Command Codes (CCC) handling
 */
#define I3C_SCAPABILITIES_CCCHANDLE(x)           (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_CCCHANDLE_SHIFT)) & I3C_SCAPABILITIES_CCCHANDLE_MASK)

#define I3C_SCAPABILITIES_IBI_MR_HJ_MASK         (0x1F0000U)
#define I3C_SCAPABILITIES_IBI_MR_HJ_SHIFT        (16U)
/*! IBI_MR_HJ - In-Band Interrupts, Master Requests, Hot Join events
 */
#define I3C_SCAPABILITIES_IBI_MR_HJ(x)           (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IBI_MR_HJ_SHIFT)) & I3C_SCAPABILITIES_IBI_MR_HJ_MASK)

#define I3C_SCAPABILITIES_TIMECTRL_MASK          (0x200000U)
#define I3C_SCAPABILITIES_TIMECTRL_SHIFT         (21U)
/*! TIMECTRL - Time control
 *  0b0..NO_TIME_CONTROL_TYPE
 *  0b1..NO_TIME_CONTROL_TYPE
 */
#define I3C_SCAPABILITIES_TIMECTRL(x)            (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_TIMECTRL_SHIFT)) & I3C_SCAPABILITIES_TIMECTRL_MASK)

#define I3C_SCAPABILITIES_EXTFIFO_MASK           (0x3800000U)
#define I3C_SCAPABILITIES_EXTFIFO_SHIFT          (23U)
/*! EXTFIFO - External FIFO
 *  0b000..NO_EXT_FIFO
 *  0b001..STD_EXT_FIFO:
 *  0b010..REQUEST_EXT_FIFO
 *  0b011..
 */
#define I3C_SCAPABILITIES_EXTFIFO(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_EXTFIFO_SHIFT)) & I3C_SCAPABILITIES_EXTFIFO_MASK)

#define I3C_SCAPABILITIES_FIFOTX_MASK            (0xC000000U)
#define I3C_SCAPABILITIES_FIFOTX_SHIFT           (26U)
/*! FIFOTX - FIFO transmit
 *  0b00..FIFO_2BYTE
 *  0b01..FIFO_4BYTE
 *  0b10..FIFO_8BYTE
 *  0b11..FIFO_16BYTE
 */
#define I3C_SCAPABILITIES_FIFOTX(x)              (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_FIFOTX_SHIFT)) & I3C_SCAPABILITIES_FIFOTX_MASK)

#define I3C_SCAPABILITIES_FIFORX_MASK            (0x30000000U)
#define I3C_SCAPABILITIES_FIFORX_SHIFT           (28U)
/*! FIFORX - FIFO receive
 *  0b00..FIFO_2BYTE
 *  0b01..FIFO_4BYTE
 *  0b10..FIFO_8BYTE
 *  0b11..FIFO_16BYTE
 */
#define I3C_SCAPABILITIES_FIFORX(x)              (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_FIFORX_SHIFT)) & I3C_SCAPABILITIES_FIFORX_MASK)

#define I3C_SCAPABILITIES_INT_MASK               (0x40000000U)
#define I3C_SCAPABILITIES_INT_SHIFT              (30U)
/*! INT - Interrupt
 *  0b1..Interrupts are supported.
 *  0b0..Interrupts are not supported
 */
#define I3C_SCAPABILITIES_INT(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_INT_SHIFT)) & I3C_SCAPABILITIES_INT_MASK)

#define I3C_SCAPABILITIES_DMA_MASK               (0x80000000U)
#define I3C_SCAPABILITIES_DMA_SHIFT              (31U)
/*! DMA - DMA
 *  0b1..DMA is supported
 *  0b0..DMA is not supported
 */
#define I3C_SCAPABILITIES_DMA(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_DMA_SHIFT)) & I3C_SCAPABILITIES_DMA_MASK)
/*! @} */

/*! @name SDYNADDR - Slave Dynamic Address Register */
/*! @{ */

#define I3C_SDYNADDR_DAVALID_MASK                (0x1U)
#define I3C_SDYNADDR_DAVALID_SHIFT               (0U)
/*! DAVALID - DAVALID
 *  0b0..DANOTASSIGNED
 *  0b1..DAASSIGNED
 */
#define I3C_SDYNADDR_DAVALID(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_DAVALID_SHIFT)) & I3C_SDYNADDR_DAVALID_MASK)

#define I3C_SDYNADDR_DADDR_MASK                  (0xFEU)
#define I3C_SDYNADDR_DADDR_SHIFT                 (1U)
/*! DADDR - Dynamic address
 */
#define I3C_SDYNADDR_DADDR(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_DADDR_SHIFT)) & I3C_SDYNADDR_DADDR_MASK)

#define I3C_SDYNADDR_MAPIDX_MASK                 (0xF00U)
#define I3C_SDYNADDR_MAPIDX_SHIFT                (8U)
/*! MAPIDX - Mapped Dynamic Address
 */
#define I3C_SDYNADDR_MAPIDX(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_MAPIDX_SHIFT)) & I3C_SDYNADDR_MAPIDX_MASK)

#define I3C_SDYNADDR_MAPSA_MASK                  (0x1000U)
#define I3C_SDYNADDR_MAPSA_SHIFT                 (12U)
/*! MAPSA - Map a Static Address
 */
#define I3C_SDYNADDR_MAPSA(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_MAPSA_SHIFT)) & I3C_SDYNADDR_MAPSA_MASK)

#define I3C_SDYNADDR_KEY_MASK                    (0xFFFF0000U)
#define I3C_SDYNADDR_KEY_SHIFT                   (16U)
/*! KEY - Key
 */
#define I3C_SDYNADDR_KEY(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_KEY_SHIFT)) & I3C_SDYNADDR_KEY_MASK)
/*! @} */

/*! @name SMAXLIMITS - Slave Maximum Limits Register */
/*! @{ */

#define I3C_SMAXLIMITS_MAXRD_MASK                (0xFFFU)
#define I3C_SMAXLIMITS_MAXRD_SHIFT               (0U)
/*! MAXRD - Maximum read length
 */
#define I3C_SMAXLIMITS_MAXRD(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SMAXLIMITS_MAXRD_SHIFT)) & I3C_SMAXLIMITS_MAXRD_MASK)

#define I3C_SMAXLIMITS_MAXWR_MASK                (0xFFF0000U)
#define I3C_SMAXLIMITS_MAXWR_SHIFT               (16U)
/*! MAXWR - Maximum write length
 */
#define I3C_SMAXLIMITS_MAXWR(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SMAXLIMITS_MAXWR_SHIFT)) & I3C_SMAXLIMITS_MAXWR_MASK)
/*! @} */

/*! @name SIDPARTNO - Slave ID Part Number Register */
/*! @{ */

#define I3C_SIDPARTNO_PARTNO_MASK                (0xFFFFFFFFU)
#define I3C_SIDPARTNO_PARTNO_SHIFT               (0U)
/*! PARTNO - Part number
 */
#define I3C_SIDPARTNO_PARTNO(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SIDPARTNO_PARTNO_SHIFT)) & I3C_SIDPARTNO_PARTNO_MASK)
/*! @} */

/*! @name SIDEXT - Slave ID Extension Register */
/*! @{ */

#define I3C_SIDEXT_DCR_MASK                      (0xFF00U)
#define I3C_SIDEXT_DCR_SHIFT                     (8U)
/*! DCR - Device Characteristic Register
 */
#define I3C_SIDEXT_DCR(x)                        (((uint32_t)(((uint32_t)(x)) << I3C_SIDEXT_DCR_SHIFT)) & I3C_SIDEXT_DCR_MASK)

#define I3C_SIDEXT_BCR_MASK                      (0xFF0000U)
#define I3C_SIDEXT_BCR_SHIFT                     (16U)
/*! BCR - Bus Characteristics Register
 */
#define I3C_SIDEXT_BCR(x)                        (((uint32_t)(((uint32_t)(x)) << I3C_SIDEXT_BCR_SHIFT)) & I3C_SIDEXT_BCR_MASK)
/*! @} */

/*! @name SVENDORID - Slave Vendor ID Register */
/*! @{ */

#define I3C_SVENDORID_VID_MASK                   (0x7FFFU)
#define I3C_SVENDORID_VID_SHIFT                  (0U)
/*! VID - Vendor ID
 */
#define I3C_SVENDORID_VID(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SVENDORID_VID_SHIFT)) & I3C_SVENDORID_VID_MASK)
/*! @} */

/*! @name STCCLOCK - Slave Time Control Clock Register */
/*! @{ */

#define I3C_STCCLOCK_ACCURACY_MASK               (0xFFU)
#define I3C_STCCLOCK_ACCURACY_SHIFT              (0U)
/*! ACCURACY - Clock accuracy
 */
#define I3C_STCCLOCK_ACCURACY(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_STCCLOCK_ACCURACY_SHIFT)) & I3C_STCCLOCK_ACCURACY_MASK)

#define I3C_STCCLOCK_FREQ_MASK                   (0xFF00U)
#define I3C_STCCLOCK_FREQ_SHIFT                  (8U)
/*! FREQ - Clock frequency
 */
#define I3C_STCCLOCK_FREQ(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_STCCLOCK_FREQ_SHIFT)) & I3C_STCCLOCK_FREQ_MASK)
/*! @} */

/*! @name SMSGMAPADDR - Slave Message-Mapped Address Register */
/*! @{ */

#define I3C_SMSGMAPADDR_MAPLAST_MASK             (0xFU)
#define I3C_SMSGMAPADDR_MAPLAST_SHIFT            (0U)
/*! MAPLAST - Matched address index
 */
#define I3C_SMSGMAPADDR_MAPLAST(x)               (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLAST_SHIFT)) & I3C_SMSGMAPADDR_MAPLAST_MASK)

#define I3C_SMSGMAPADDR_MAPLASTM1_MASK           (0xF00U)
#define I3C_SMSGMAPADDR_MAPLASTM1_SHIFT          (8U)
/*! MAPLASTM1 - Previous match index 1
 */
#define I3C_SMSGMAPADDR_MAPLASTM1(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLASTM1_SHIFT)) & I3C_SMSGMAPADDR_MAPLASTM1_MASK)

#define I3C_SMSGMAPADDR_MAPLASTM2_MASK           (0xF0000U)
#define I3C_SMSGMAPADDR_MAPLASTM2_SHIFT          (16U)
/*! MAPLASTM2 - Previous match index 2
 */
#define I3C_SMSGMAPADDR_MAPLASTM2(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLASTM2_SHIFT)) & I3C_SMSGMAPADDR_MAPLASTM2_MASK)
/*! @} */

/*! @name MCTRL - Master Main Control Register */
/*! @{ */

#define I3C_MCTRL_REQUEST_MASK                   (0x7U)
#define I3C_MCTRL_REQUEST_SHIFT                  (0U)
/*! REQUEST - Request
 *  0b000..NONE
 *  0b001..EMITSTARTADDR
 *  0b010..EMITSTOP
 *  0b011..IBIACKNACK
 *  0b100..PROCESSDAA
 *  0b101..
 *  0b110..FORCEEXIT and IBHR
 *  0b111..AUTOIBI
 */
#define I3C_MCTRL_REQUEST(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_REQUEST_SHIFT)) & I3C_MCTRL_REQUEST_MASK)

#define I3C_MCTRL_TYPE_MASK                      (0x30U)
#define I3C_MCTRL_TYPE_SHIFT                     (4U)
/*! TYPE - Bus type with START
 *  0b00..I3C
 *  0b01..I2C
 *  0b10..DDR
 *  0b11..For ForcedExit, this is forced IBHR.
 */
#define I3C_MCTRL_TYPE(x)                        (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_TYPE_SHIFT)) & I3C_MCTRL_TYPE_MASK)

#define I3C_MCTRL_IBIRESP_MASK                   (0xC0U)
#define I3C_MCTRL_IBIRESP_SHIFT                  (6U)
/*! IBIRESP - In-Band Interrupt (IBI) response
 *  0b00..ACK
 *  0b01..NACK
 *  0b10..ACK_WITH_MANDATORY
 *  0b11..MANUAL
 */
#define I3C_MCTRL_IBIRESP(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_IBIRESP_SHIFT)) & I3C_MCTRL_IBIRESP_MASK)

#define I3C_MCTRL_DIR_MASK                       (0x100U)
#define I3C_MCTRL_DIR_SHIFT                      (8U)
/*! DIR - DIR
 *  0b0..DIRWRITE: Write
 *  0b1..DIRREAD: Read
 */
#define I3C_MCTRL_DIR(x)                         (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_DIR_SHIFT)) & I3C_MCTRL_DIR_MASK)

#define I3C_MCTRL_ADDR_MASK                      (0xFE00U)
#define I3C_MCTRL_ADDR_SHIFT                     (9U)
/*! ADDR - ADDR
 */
#define I3C_MCTRL_ADDR(x)                        (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_ADDR_SHIFT)) & I3C_MCTRL_ADDR_MASK)

#define I3C_MCTRL_RDTERM_MASK                    (0xFF0000U)
#define I3C_MCTRL_RDTERM_SHIFT                   (16U)
/*! RDTERM - Read terminate
 */
#define I3C_MCTRL_RDTERM(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_RDTERM_SHIFT)) & I3C_MCTRL_RDTERM_MASK)
/*! @} */

/*! @name MSTATUS - Master Status Register */
/*! @{ */

#define I3C_MSTATUS_STATE_MASK                   (0x7U)
#define I3C_MSTATUS_STATE_SHIFT                  (0U)
/*! STATE - State of the master
 *  0b000..IDLE
 *  0b001..SLVREQ
 *  0b010..MSGSDR
 *  0b011..NORMACT
 *  0b100..MSGDDR
 *  0b101..DAA
 *  0b110..IBIACK
 *  0b111..IBIRCV
 */
#define I3C_MSTATUS_STATE(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_STATE_SHIFT)) & I3C_MSTATUS_STATE_MASK)

#define I3C_MSTATUS_BETWEEN_MASK                 (0x10U)
#define I3C_MSTATUS_BETWEEN_SHIFT                (4U)
/*! BETWEEN - Between
 *  0b0..Inactive
 *  0b1..Active
 */
#define I3C_MSTATUS_BETWEEN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_BETWEEN_SHIFT)) & I3C_MSTATUS_BETWEEN_MASK)

#define I3C_MSTATUS_NACKED_MASK                  (0x20U)
#define I3C_MSTATUS_NACKED_SHIFT                 (5U)
/*! NACKED - Not acknowledged
 */
#define I3C_MSTATUS_NACKED(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_NACKED_SHIFT)) & I3C_MSTATUS_NACKED_MASK)

#define I3C_MSTATUS_IBITYPE_MASK                 (0xC0U)
#define I3C_MSTATUS_IBITYPE_SHIFT                (6U)
/*! IBITYPE - In-Band Interrupt (IBI) type
 *  0b00..NONE
 *  0b01..IBI
 *  0b10..MR
 *  0b11..HJ
 */
#define I3C_MSTATUS_IBITYPE(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBITYPE_SHIFT)) & I3C_MSTATUS_IBITYPE_MASK)

#define I3C_MSTATUS_SLVSTART_MASK                (0x100U)
#define I3C_MSTATUS_SLVSTART_SHIFT               (8U)
/*! SLVSTART - Slave start
 */
#define I3C_MSTATUS_SLVSTART(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_SLVSTART_SHIFT)) & I3C_MSTATUS_SLVSTART_MASK)

#define I3C_MSTATUS_MCTRLDONE_MASK               (0x200U)
#define I3C_MSTATUS_MCTRLDONE_SHIFT              (9U)
/*! MCTRLDONE - Master control done
 */
#define I3C_MSTATUS_MCTRLDONE(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_MCTRLDONE_SHIFT)) & I3C_MSTATUS_MCTRLDONE_MASK)

#define I3C_MSTATUS_COMPLETE_MASK                (0x400U)
#define I3C_MSTATUS_COMPLETE_SHIFT               (10U)
/*! COMPLETE - COMPLETE
 */
#define I3C_MSTATUS_COMPLETE(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_COMPLETE_SHIFT)) & I3C_MSTATUS_COMPLETE_MASK)

#define I3C_MSTATUS_RXPEND_MASK                  (0x800U)
#define I3C_MSTATUS_RXPEND_SHIFT                 (11U)
/*! RXPEND - RXPEND
 */
#define I3C_MSTATUS_RXPEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_RXPEND_SHIFT)) & I3C_MSTATUS_RXPEND_MASK)

#define I3C_MSTATUS_TXNOTFULL_MASK               (0x1000U)
#define I3C_MSTATUS_TXNOTFULL_SHIFT              (12U)
/*! TXNOTFULL - TX buffer/FIFO not yet full
 */
#define I3C_MSTATUS_TXNOTFULL(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_TXNOTFULL_SHIFT)) & I3C_MSTATUS_TXNOTFULL_MASK)

#define I3C_MSTATUS_IBIWON_MASK                  (0x2000U)
#define I3C_MSTATUS_IBIWON_SHIFT                 (13U)
/*! IBIWON - In-Band Interrupt (IBI) won
 */
#define I3C_MSTATUS_IBIWON(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBIWON_SHIFT)) & I3C_MSTATUS_IBIWON_MASK)

#define I3C_MSTATUS_ERRWARN_MASK                 (0x8000U)
#define I3C_MSTATUS_ERRWARN_SHIFT                (15U)
/*! ERRWARN - Error or warning
 */
#define I3C_MSTATUS_ERRWARN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_ERRWARN_SHIFT)) & I3C_MSTATUS_ERRWARN_MASK)

#define I3C_MSTATUS_NOWMASTER_MASK               (0x80000U)
#define I3C_MSTATUS_NOWMASTER_SHIFT              (19U)
/*! NOWMASTER - Now master (now this module is a master)
 */
#define I3C_MSTATUS_NOWMASTER(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_NOWMASTER_SHIFT)) & I3C_MSTATUS_NOWMASTER_MASK)

#define I3C_MSTATUS_IBIADDR_MASK                 (0x7F000000U)
#define I3C_MSTATUS_IBIADDR_SHIFT                (24U)
/*! IBIADDR - IBI address
 */
#define I3C_MSTATUS_IBIADDR(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBIADDR_SHIFT)) & I3C_MSTATUS_IBIADDR_MASK)
/*! @} */

/*! @name MIBIRULES - Master In-band Interrupt Registry and Rules Register */
/*! @{ */

#define I3C_MIBIRULES_ADDR0_MASK                 (0x3FU)
#define I3C_MIBIRULES_ADDR0_SHIFT                (0U)
/*! ADDR0 - ADDR0
 */
#define I3C_MIBIRULES_ADDR0(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR0_SHIFT)) & I3C_MIBIRULES_ADDR0_MASK)

#define I3C_MIBIRULES_ADDR1_MASK                 (0xFC0U)
#define I3C_MIBIRULES_ADDR1_SHIFT                (6U)
/*! ADDR1 - ADDR1
 */
#define I3C_MIBIRULES_ADDR1(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR1_SHIFT)) & I3C_MIBIRULES_ADDR1_MASK)

#define I3C_MIBIRULES_ADDR2_MASK                 (0x3F000U)
#define I3C_MIBIRULES_ADDR2_SHIFT                (12U)
/*! ADDR2 - ADDR2
 */
#define I3C_MIBIRULES_ADDR2(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR2_SHIFT)) & I3C_MIBIRULES_ADDR2_MASK)

#define I3C_MIBIRULES_ADDR3_MASK                 (0xFC0000U)
#define I3C_MIBIRULES_ADDR3_SHIFT                (18U)
/*! ADDR3 - ADDR3
 */
#define I3C_MIBIRULES_ADDR3(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR3_SHIFT)) & I3C_MIBIRULES_ADDR3_MASK)

#define I3C_MIBIRULES_ADDR4_MASK                 (0x3F000000U)
#define I3C_MIBIRULES_ADDR4_SHIFT                (24U)
/*! ADDR4 - ADDR4
 */
#define I3C_MIBIRULES_ADDR4(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR4_SHIFT)) & I3C_MIBIRULES_ADDR4_MASK)

#define I3C_MIBIRULES_MSB0_MASK                  (0x40000000U)
#define I3C_MIBIRULES_MSB0_SHIFT                 (30U)
/*! MSB0 - Set Most Significant address Bit to 0
 */
#define I3C_MIBIRULES_MSB0(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_MSB0_SHIFT)) & I3C_MIBIRULES_MSB0_MASK)

#define I3C_MIBIRULES_NOBYTE_MASK                (0x80000000U)
#define I3C_MIBIRULES_NOBYTE_SHIFT               (31U)
/*! NOBYTE - No IBI byte
 */
#define I3C_MIBIRULES_NOBYTE(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_NOBYTE_SHIFT)) & I3C_MIBIRULES_NOBYTE_MASK)
/*! @} */

/*! @name MINTSET - Master Interrupt Set Register */
/*! @{ */

#define I3C_MINTSET_SLVSTART_MASK                (0x100U)
#define I3C_MINTSET_SLVSTART_SHIFT               (8U)
/*! SLVSTART - Slave start interrupt enable
 */
#define I3C_MINTSET_SLVSTART(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_SLVSTART_SHIFT)) & I3C_MINTSET_SLVSTART_MASK)

#define I3C_MINTSET_MCTRLDONE_MASK               (0x200U)
#define I3C_MINTSET_MCTRLDONE_SHIFT              (9U)
/*! MCTRLDONE - Master control done interrupt enable
 */
#define I3C_MINTSET_MCTRLDONE(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_MCTRLDONE_SHIFT)) & I3C_MINTSET_MCTRLDONE_MASK)

#define I3C_MINTSET_COMPLETE_MASK                (0x400U)
#define I3C_MINTSET_COMPLETE_SHIFT               (10U)
/*! COMPLETE - Completed message interrupt enable
 */
#define I3C_MINTSET_COMPLETE(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_COMPLETE_SHIFT)) & I3C_MINTSET_COMPLETE_MASK)

#define I3C_MINTSET_RXPEND_MASK                  (0x800U)
#define I3C_MINTSET_RXPEND_SHIFT                 (11U)
/*! RXPEND - RX pending interrupt enable
 */
#define I3C_MINTSET_RXPEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_RXPEND_SHIFT)) & I3C_MINTSET_RXPEND_MASK)

#define I3C_MINTSET_TXNOTFULL_MASK               (0x1000U)
#define I3C_MINTSET_TXNOTFULL_SHIFT              (12U)
/*! TXNOTFULL - TX buffer/FIFO is not full interrupt enable
 */
#define I3C_MINTSET_TXNOTFULL(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_TXNOTFULL_SHIFT)) & I3C_MINTSET_TXNOTFULL_MASK)

#define I3C_MINTSET_IBIWON_MASK                  (0x2000U)
#define I3C_MINTSET_IBIWON_SHIFT                 (13U)
/*! IBIWON - In-Band Interrupt (IBI) won interrupt enable
 */
#define I3C_MINTSET_IBIWON(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_IBIWON_SHIFT)) & I3C_MINTSET_IBIWON_MASK)

#define I3C_MINTSET_ERRWARN_MASK                 (0x8000U)
#define I3C_MINTSET_ERRWARN_SHIFT                (15U)
/*! ERRWARN - Error or warning (ERRWARN) interrupt enable
 */
#define I3C_MINTSET_ERRWARN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_ERRWARN_SHIFT)) & I3C_MINTSET_ERRWARN_MASK)

#define I3C_MINTSET_NOWMASTER_MASK               (0x80000U)
#define I3C_MINTSET_NOWMASTER_SHIFT              (19U)
/*! NOWMASTER - Now master (now this I3C module is a master) interrupt enable
 */
#define I3C_MINTSET_NOWMASTER(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_NOWMASTER_SHIFT)) & I3C_MINTSET_NOWMASTER_MASK)
/*! @} */

/*! @name MINTCLR - Master Interrupt Clear Register */
/*! @{ */

#define I3C_MINTCLR_SLVSTART_MASK                (0x100U)
#define I3C_MINTCLR_SLVSTART_SHIFT               (8U)
/*! SLVSTART - SLVSTART interrupt enable clear
 */
#define I3C_MINTCLR_SLVSTART(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_SLVSTART_SHIFT)) & I3C_MINTCLR_SLVSTART_MASK)

#define I3C_MINTCLR_MCTRLDONE_MASK               (0x200U)
#define I3C_MINTCLR_MCTRLDONE_SHIFT              (9U)
/*! MCTRLDONE - MCTRLDONE interrupt enable clear
 */
#define I3C_MINTCLR_MCTRLDONE(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_MCTRLDONE_SHIFT)) & I3C_MINTCLR_MCTRLDONE_MASK)

#define I3C_MINTCLR_COMPLETE_MASK                (0x400U)
#define I3C_MINTCLR_COMPLETE_SHIFT               (10U)
/*! COMPLETE - COMPLETE interrupt enable clear
 */
#define I3C_MINTCLR_COMPLETE(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_COMPLETE_SHIFT)) & I3C_MINTCLR_COMPLETE_MASK)

#define I3C_MINTCLR_RXPEND_MASK                  (0x800U)
#define I3C_MINTCLR_RXPEND_SHIFT                 (11U)
/*! RXPEND - RXPEND interrupt enable clear
 */
#define I3C_MINTCLR_RXPEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_RXPEND_SHIFT)) & I3C_MINTCLR_RXPEND_MASK)

#define I3C_MINTCLR_TXNOTFULL_MASK               (0x1000U)
#define I3C_MINTCLR_TXNOTFULL_SHIFT              (12U)
/*! TXNOTFULL - TXNOTFULL interrupt enable clear
 */
#define I3C_MINTCLR_TXNOTFULL(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_TXNOTFULL_SHIFT)) & I3C_MINTCLR_TXNOTFULL_MASK)

#define I3C_MINTCLR_IBIWON_MASK                  (0x2000U)
#define I3C_MINTCLR_IBIWON_SHIFT                 (13U)
/*! IBIWON - IBIWON interrupt enable clear
 */
#define I3C_MINTCLR_IBIWON(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_IBIWON_SHIFT)) & I3C_MINTCLR_IBIWON_MASK)

#define I3C_MINTCLR_ERRWARN_MASK                 (0x8000U)
#define I3C_MINTCLR_ERRWARN_SHIFT                (15U)
/*! ERRWARN - ERRWARN interrupt enable clear
 */
#define I3C_MINTCLR_ERRWARN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_ERRWARN_SHIFT)) & I3C_MINTCLR_ERRWARN_MASK)

#define I3C_MINTCLR_NOWMASTER_MASK               (0x80000U)
#define I3C_MINTCLR_NOWMASTER_SHIFT              (19U)
/*! NOWMASTER - NOWMASTER interrupt enable clear
 */
#define I3C_MINTCLR_NOWMASTER(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_NOWMASTER_SHIFT)) & I3C_MINTCLR_NOWMASTER_MASK)
/*! @} */

/*! @name MINTMASKED - Master Interrupt Mask Register */
/*! @{ */

#define I3C_MINTMASKED_SLVSTART_MASK             (0x100U)
#define I3C_MINTMASKED_SLVSTART_SHIFT            (8U)
/*! SLVSTART - SLVSTART interrupt mask
 */
#define I3C_MINTMASKED_SLVSTART(x)               (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_SLVSTART_SHIFT)) & I3C_MINTMASKED_SLVSTART_MASK)

#define I3C_MINTMASKED_MCTRLDONE_MASK            (0x200U)
#define I3C_MINTMASKED_MCTRLDONE_SHIFT           (9U)
/*! MCTRLDONE - MCTRLDONE interrupt mask
 */
#define I3C_MINTMASKED_MCTRLDONE(x)              (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_MCTRLDONE_SHIFT)) & I3C_MINTMASKED_MCTRLDONE_MASK)

#define I3C_MINTMASKED_COMPLETE_MASK             (0x400U)
#define I3C_MINTMASKED_COMPLETE_SHIFT            (10U)
/*! COMPLETE - COMPLETE interrupt mask
 */
#define I3C_MINTMASKED_COMPLETE(x)               (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_COMPLETE_SHIFT)) & I3C_MINTMASKED_COMPLETE_MASK)

#define I3C_MINTMASKED_RXPEND_MASK               (0x800U)
#define I3C_MINTMASKED_RXPEND_SHIFT              (11U)
/*! RXPEND - RXPEND interrupt mask
 */
#define I3C_MINTMASKED_RXPEND(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_RXPEND_SHIFT)) & I3C_MINTMASKED_RXPEND_MASK)

#define I3C_MINTMASKED_TXNOTFULL_MASK            (0x1000U)
#define I3C_MINTMASKED_TXNOTFULL_SHIFT           (12U)
/*! TXNOTFULL - TXNOTFULL interrupt mask
 */
#define I3C_MINTMASKED_TXNOTFULL(x)              (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_TXNOTFULL_SHIFT)) & I3C_MINTMASKED_TXNOTFULL_MASK)

#define I3C_MINTMASKED_IBIWON_MASK               (0x2000U)
#define I3C_MINTMASKED_IBIWON_SHIFT              (13U)
/*! IBIWON - IBIWON interrupt mask
 */
#define I3C_MINTMASKED_IBIWON(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_IBIWON_SHIFT)) & I3C_MINTMASKED_IBIWON_MASK)

#define I3C_MINTMASKED_ERRWARN_MASK              (0x8000U)
#define I3C_MINTMASKED_ERRWARN_SHIFT             (15U)
/*! ERRWARN - ERRWARN interrupt mask
 */
#define I3C_MINTMASKED_ERRWARN(x)                (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_ERRWARN_SHIFT)) & I3C_MINTMASKED_ERRWARN_MASK)

#define I3C_MINTMASKED_NOWMASTER_MASK            (0x80000U)
#define I3C_MINTMASKED_NOWMASTER_SHIFT           (19U)
/*! NOWMASTER - NOWMASTER interrupt mask
 */
#define I3C_MINTMASKED_NOWMASTER(x)              (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_NOWMASTER_SHIFT)) & I3C_MINTMASKED_NOWMASTER_MASK)
/*! @} */

/*! @name MERRWARN - Master Errors and Warnings Register */
/*! @{ */

#define I3C_MERRWARN_NACK_MASK                   (0x4U)
#define I3C_MERRWARN_NACK_SHIFT                  (2U)
/*! NACK - Not acknowledge (NACK) error
 */
#define I3C_MERRWARN_NACK(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_NACK_SHIFT)) & I3C_MERRWARN_NACK_MASK)

#define I3C_MERRWARN_WRABT_MASK                  (0x8U)
#define I3C_MERRWARN_WRABT_SHIFT                 (3U)
/*! WRABT - WRABT (Write abort) error
 */
#define I3C_MERRWARN_WRABT(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_WRABT_SHIFT)) & I3C_MERRWARN_WRABT_MASK)

#define I3C_MERRWARN_TERM_MASK                   (0x10U)
#define I3C_MERRWARN_TERM_SHIFT                  (4U)
/*! TERM - Terminate error
 */
#define I3C_MERRWARN_TERM(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_TERM_SHIFT)) & I3C_MERRWARN_TERM_MASK)

#define I3C_MERRWARN_HPAR_MASK                   (0x200U)
#define I3C_MERRWARN_HPAR_SHIFT                  (9U)
/*! HPAR - High data rate parity
 */
#define I3C_MERRWARN_HPAR(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_HPAR_SHIFT)) & I3C_MERRWARN_HPAR_MASK)

#define I3C_MERRWARN_HCRC_MASK                   (0x400U)
#define I3C_MERRWARN_HCRC_SHIFT                  (10U)
/*! HCRC - High data rate CRC error
 */
#define I3C_MERRWARN_HCRC(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_HCRC_SHIFT)) & I3C_MERRWARN_HCRC_MASK)

#define I3C_MERRWARN_OREAD_MASK                  (0x10000U)
#define I3C_MERRWARN_OREAD_SHIFT                 (16U)
/*! OREAD - Over-read error
 */
#define I3C_MERRWARN_OREAD(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OREAD_SHIFT)) & I3C_MERRWARN_OREAD_MASK)

#define I3C_MERRWARN_OWRITE_MASK                 (0x20000U)
#define I3C_MERRWARN_OWRITE_SHIFT                (17U)
/*! OWRITE - Over-write error
 */
#define I3C_MERRWARN_OWRITE(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OWRITE_SHIFT)) & I3C_MERRWARN_OWRITE_MASK)

#define I3C_MERRWARN_MSGERR_MASK                 (0x40000U)
#define I3C_MERRWARN_MSGERR_SHIFT                (18U)
/*! MSGERR - Message error
 */
#define I3C_MERRWARN_MSGERR(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_MSGERR_SHIFT)) & I3C_MERRWARN_MSGERR_MASK)

#define I3C_MERRWARN_INVREQ_MASK                 (0x80000U)
#define I3C_MERRWARN_INVREQ_SHIFT                (19U)
/*! INVREQ - Invalid request error
 */
#define I3C_MERRWARN_INVREQ(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_INVREQ_SHIFT)) & I3C_MERRWARN_INVREQ_MASK)

#define I3C_MERRWARN_TIMEOUT_MASK                (0x100000U)
#define I3C_MERRWARN_TIMEOUT_SHIFT               (20U)
/*! TIMEOUT - TIMEOUT error
 */
#define I3C_MERRWARN_TIMEOUT(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_TIMEOUT_SHIFT)) & I3C_MERRWARN_TIMEOUT_MASK)
/*! @} */

/*! @name MDMACTRL - Master DMA Control Register */
/*! @{ */

#define I3C_MDMACTRL_DMAFB_MASK                  (0x3U)
#define I3C_MDMACTRL_DMAFB_SHIFT                 (0U)
/*! DMAFB - DMA from bus
 *  0b00..NOT_USED. DMA is not used
 *  0b01..ENABLE_ONE_FRAME
 *  0b10..ENABLE
 */
#define I3C_MDMACTRL_DMAFB(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMAFB_SHIFT)) & I3C_MDMACTRL_DMAFB_MASK)

#define I3C_MDMACTRL_DMATB_MASK                  (0xCU)
#define I3C_MDMACTRL_DMATB_SHIFT                 (2U)
/*! DMATB - DMA to bus
 *  0b00..NOT_USED. DMA is not used
 *  0b01..ENABLE_ONE_FRAME
 *  0b10..ENABLE
 */
#define I3C_MDMACTRL_DMATB(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMATB_SHIFT)) & I3C_MDMACTRL_DMATB_MASK)

#define I3C_MDMACTRL_DMAWIDTH_MASK               (0x30U)
#define I3C_MDMACTRL_DMAWIDTH_SHIFT              (4U)
/*! DMAWIDTH - DMA width
 *  0b00..BYTE
 *  0b01..BYTE_AGAIN
 *  0b10..HALF_WORD
 *  0b11..
 */
#define I3C_MDMACTRL_DMAWIDTH(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMAWIDTH_SHIFT)) & I3C_MDMACTRL_DMAWIDTH_MASK)
/*! @} */

/*! @name MDATACTRL - Master Data Control Register */
/*! @{ */

#define I3C_MDATACTRL_FLUSHTB_MASK               (0x1U)
#define I3C_MDATACTRL_FLUSHTB_SHIFT              (0U)
/*! FLUSHTB - Flush to-bus buffer/FIFO
 */
#define I3C_MDATACTRL_FLUSHTB(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_FLUSHTB_SHIFT)) & I3C_MDATACTRL_FLUSHTB_MASK)

#define I3C_MDATACTRL_FLUSHFB_MASK               (0x2U)
#define I3C_MDATACTRL_FLUSHFB_SHIFT              (1U)
/*! FLUSHFB - Flush from-bus buffer/FIFO
 */
#define I3C_MDATACTRL_FLUSHFB(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_FLUSHFB_SHIFT)) & I3C_MDATACTRL_FLUSHFB_MASK)

#define I3C_MDATACTRL_UNLOCK_MASK                (0x4U)
#define I3C_MDATACTRL_UNLOCK_SHIFT               (2U)
/*! UNLOCK - Unlock
 */
#define I3C_MDATACTRL_UNLOCK(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_UNLOCK_SHIFT)) & I3C_MDATACTRL_UNLOCK_MASK)

#define I3C_MDATACTRL_TXTRIG_MASK                (0x30U)
#define I3C_MDATACTRL_TXTRIG_SHIFT               (4U)
/*! TXTRIG - TX trigger level
 */
#define I3C_MDATACTRL_TXTRIG(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXTRIG_SHIFT)) & I3C_MDATACTRL_TXTRIG_MASK)

#define I3C_MDATACTRL_RXTRIG_MASK                (0xC0U)
#define I3C_MDATACTRL_RXTRIG_SHIFT               (6U)
/*! RXTRIG - RX trigger level
 */
#define I3C_MDATACTRL_RXTRIG(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXTRIG_SHIFT)) & I3C_MDATACTRL_RXTRIG_MASK)

#define I3C_MDATACTRL_TXCOUNT_MASK               (0x1F0000U)
#define I3C_MDATACTRL_TXCOUNT_SHIFT              (16U)
/*! TXCOUNT - TX byte count
 */
#define I3C_MDATACTRL_TXCOUNT(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXCOUNT_SHIFT)) & I3C_MDATACTRL_TXCOUNT_MASK)

#define I3C_MDATACTRL_RXCOUNT_MASK               (0x1F000000U)
#define I3C_MDATACTRL_RXCOUNT_SHIFT              (24U)
/*! RXCOUNT - RX byte count
 */
#define I3C_MDATACTRL_RXCOUNT(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXCOUNT_SHIFT)) & I3C_MDATACTRL_RXCOUNT_MASK)

#define I3C_MDATACTRL_TXFULL_MASK                (0x40000000U)
#define I3C_MDATACTRL_TXFULL_SHIFT               (30U)
/*! TXFULL - TX is full
 */
#define I3C_MDATACTRL_TXFULL(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXFULL_SHIFT)) & I3C_MDATACTRL_TXFULL_MASK)

#define I3C_MDATACTRL_RXEMPTY_MASK               (0x80000000U)
#define I3C_MDATACTRL_RXEMPTY_SHIFT              (31U)
/*! RXEMPTY - RX is empty
 */
#define I3C_MDATACTRL_RXEMPTY(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXEMPTY_SHIFT)) & I3C_MDATACTRL_RXEMPTY_MASK)
/*! @} */

/*! @name MWDATAB - Master Write Data Byte Register */
/*! @{ */

#define I3C_MWDATAB_VALUE_MASK                   (0xFFU)
#define I3C_MWDATAB_VALUE_SHIFT                  (0U)
/*! VALUE - Data byte
 */
#define I3C_MWDATAB_VALUE(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_VALUE_SHIFT)) & I3C_MWDATAB_VALUE_MASK)

#define I3C_MWDATAB_END_MASK                     (0x100U)
#define I3C_MWDATAB_END_SHIFT                    (8U)
/*! END - End of message
 */
#define I3C_MWDATAB_END(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_END_SHIFT)) & I3C_MWDATAB_END_MASK)

#define I3C_MWDATAB_END_ALSO_MASK                (0x10000U)
#define I3C_MWDATAB_END_ALSO_SHIFT               (16U)
/*! END_ALSO - End of message also
 */
#define I3C_MWDATAB_END_ALSO(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_END_ALSO_SHIFT)) & I3C_MWDATAB_END_ALSO_MASK)
/*! @} */

/*! @name MWDATABE - Master Write Data Byte End Register */
/*! @{ */

#define I3C_MWDATABE_VALUE_MASK                  (0xFFU)
#define I3C_MWDATABE_VALUE_SHIFT                 (0U)
/*! VALUE - Data
 */
#define I3C_MWDATABE_VALUE(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MWDATABE_VALUE_SHIFT)) & I3C_MWDATABE_VALUE_MASK)
/*! @} */

/*! @name MWDATAH - Master Write Data Half-word Register */
/*! @{ */

#define I3C_MWDATAH_DATA0_MASK                   (0xFFU)
#define I3C_MWDATAH_DATA0_SHIFT                  (0U)
/*! DATA0 - Data byte 0
 */
#define I3C_MWDATAH_DATA0(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_DATA0_SHIFT)) & I3C_MWDATAH_DATA0_MASK)

#define I3C_MWDATAH_DATA1_MASK                   (0xFF00U)
#define I3C_MWDATAH_DATA1_SHIFT                  (8U)
/*! DATA1 - Data byte 1
 */
#define I3C_MWDATAH_DATA1(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_DATA1_SHIFT)) & I3C_MWDATAH_DATA1_MASK)

#define I3C_MWDATAH_END_MASK                     (0x10000U)
#define I3C_MWDATAH_END_SHIFT                    (16U)
/*! END - End of message
 */
#define I3C_MWDATAH_END(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_END_SHIFT)) & I3C_MWDATAH_END_MASK)
/*! @} */

/*! @name MWDATAHE - Master Write Data Byte End Register */
/*! @{ */

#define I3C_MWDATAHE_DATA0_MASK                  (0xFFU)
#define I3C_MWDATAHE_DATA0_SHIFT                 (0U)
/*! DATA0 - DATA 0
 */
#define I3C_MWDATAHE_DATA0(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAHE_DATA0_SHIFT)) & I3C_MWDATAHE_DATA0_MASK)

#define I3C_MWDATAHE_DATA1_MASK                  (0xFF00U)
#define I3C_MWDATAHE_DATA1_SHIFT                 (8U)
/*! DATA1 - DATA 1
 */
#define I3C_MWDATAHE_DATA1(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAHE_DATA1_SHIFT)) & I3C_MWDATAHE_DATA1_MASK)
/*! @} */

/*! @name MRDATAB - Master Read Data Byte Register */
/*! @{ */

#define I3C_MRDATAB_VALUE_MASK                   (0xFFU)
#define I3C_MRDATAB_VALUE_SHIFT                  (0U)
/*! VALUE - VALUE
 */
#define I3C_MRDATAB_VALUE(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAB_VALUE_SHIFT)) & I3C_MRDATAB_VALUE_MASK)
/*! @} */

/*! @name MRDATAH - Master Read Data Half-word Register */
/*! @{ */

#define I3C_MRDATAH_LSB_MASK                     (0xFFU)
#define I3C_MRDATAH_LSB_SHIFT                    (0U)
/*! LSB - LSB
 */
#define I3C_MRDATAH_LSB(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAH_LSB_SHIFT)) & I3C_MRDATAH_LSB_MASK)

#define I3C_MRDATAH_MSB_MASK                     (0xFF00U)
#define I3C_MRDATAH_MSB_SHIFT                    (8U)
/*! MSB - MSB
 */
#define I3C_MRDATAH_MSB(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAH_MSB_SHIFT)) & I3C_MRDATAH_MSB_MASK)
/*! @} */

/*! @name MWDATAB1 - Write Byte Data 1 (to bus) */
/*! @{ */

#define I3C_MWDATAB1_VALUE_MASK                  (0xFFU)
#define I3C_MWDATAB1_VALUE_SHIFT                 (0U)
/*! VALUE - Value
 */
#define I3C_MWDATAB1_VALUE(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB1_VALUE_SHIFT)) & I3C_MWDATAB1_VALUE_MASK)
/*! @} */

/*! @name MWMSG_SDR_CONTROL - Master Write Message in SDR mode */
/*! @{ */

#define I3C_MWMSG_SDR_CONTROL_DIR_MASK           (0x1U)
#define I3C_MWMSG_SDR_CONTROL_DIR_SHIFT          (0U)
/*! DIR - Direction
 *  0b0..Write
 *  0b1..Read
 */
#define I3C_MWMSG_SDR_CONTROL_DIR(x)             (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_DIR_SHIFT)) & I3C_MWMSG_SDR_CONTROL_DIR_MASK)

#define I3C_MWMSG_SDR_CONTROL_ADDR_MASK          (0xFEU)
#define I3C_MWMSG_SDR_CONTROL_ADDR_SHIFT         (1U)
/*! ADDR - Address to be written to
 */
#define I3C_MWMSG_SDR_CONTROL_ADDR(x)            (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_ADDR_SHIFT)) & I3C_MWMSG_SDR_CONTROL_ADDR_MASK)

#define I3C_MWMSG_SDR_CONTROL_END_MASK           (0x100U)
#define I3C_MWMSG_SDR_CONTROL_END_SHIFT          (8U)
/*! END - End of SDR message
 */
#define I3C_MWMSG_SDR_CONTROL_END(x)             (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_END_SHIFT)) & I3C_MWMSG_SDR_CONTROL_END_MASK)

#define I3C_MWMSG_SDR_CONTROL_I2C_MASK           (0x400U)
#define I3C_MWMSG_SDR_CONTROL_I2C_SHIFT          (10U)
/*! I2C - I2C
 *  0b0..I3C message
 *  0b1..I2C message
 */
#define I3C_MWMSG_SDR_CONTROL_I2C(x)             (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_I2C_SHIFT)) & I3C_MWMSG_SDR_CONTROL_I2C_MASK)

#define I3C_MWMSG_SDR_CONTROL_LEN_MASK           (0xF800U)
#define I3C_MWMSG_SDR_CONTROL_LEN_SHIFT          (11U)
/*! LEN - Length
 */
#define I3C_MWMSG_SDR_CONTROL_LEN(x)             (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_LEN_SHIFT)) & I3C_MWMSG_SDR_CONTROL_LEN_MASK)
/*! @} */

/*! @name MWMSG_SDR_DATA - Master Write Message Data in SDR mode */
/*! @{ */

#define I3C_MWMSG_SDR_DATA_DATA16B_MASK          (0xFFFFU)
#define I3C_MWMSG_SDR_DATA_DATA16B_SHIFT         (0U)
/*! DATA16B - Data
 */
#define I3C_MWMSG_SDR_DATA_DATA16B(x)            (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_DATA_DATA16B_SHIFT)) & I3C_MWMSG_SDR_DATA_DATA16B_MASK)

#define I3C_MWMSG_SDR_DATA_END_MASK              (0x10000U)
#define I3C_MWMSG_SDR_DATA_END_SHIFT             (16U)
/*! END - End of message
 */
#define I3C_MWMSG_SDR_DATA_END(x)                (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_DATA_END_SHIFT)) & I3C_MWMSG_SDR_DATA_END_MASK)
/*! @} */

/*! @name MRMSG_SDR - Master Read Message in SDR mode */
/*! @{ */

#define I3C_MRMSG_SDR_DATA_MASK                  (0xFFFFU)
#define I3C_MRMSG_SDR_DATA_SHIFT                 (0U)
/*! DATA - Data
 */
#define I3C_MRMSG_SDR_DATA(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MRMSG_SDR_DATA_SHIFT)) & I3C_MRMSG_SDR_DATA_MASK)
/*! @} */

/*! @name MWMSG_DDR_CONTROL - Master Write Message in DDR mode */
/*! @{ */

#define I3C_MWMSG_DDR_CONTROL_LEN_MASK           (0x3FFU)
#define I3C_MWMSG_DDR_CONTROL_LEN_SHIFT          (0U)
/*! LEN - Length of message
 */
#define I3C_MWMSG_DDR_CONTROL_LEN(x)             (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL_LEN_SHIFT)) & I3C_MWMSG_DDR_CONTROL_LEN_MASK)

#define I3C_MWMSG_DDR_CONTROL_END_MASK           (0x4000U)
#define I3C_MWMSG_DDR_CONTROL_END_SHIFT          (14U)
/*! END - End of message
 */
#define I3C_MWMSG_DDR_CONTROL_END(x)             (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL_END_SHIFT)) & I3C_MWMSG_DDR_CONTROL_END_MASK)
/*! @} */

/*! @name MWMSG_DDR_DATA - Master Write Message Data in DDR mode */
/*! @{ */

#define I3C_MWMSG_DDR_DATA_DATA16B_MASK          (0xFFFFU)
#define I3C_MWMSG_DDR_DATA_DATA16B_SHIFT         (0U)
/*! DATA16B - Data
 */
#define I3C_MWMSG_DDR_DATA_DATA16B(x)            (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_DATA_DATA16B_SHIFT)) & I3C_MWMSG_DDR_DATA_DATA16B_MASK)

#define I3C_MWMSG_DDR_DATA_END_MASK              (0x10000U)
#define I3C_MWMSG_DDR_DATA_END_SHIFT             (16U)
/*! END - End of message
 */
#define I3C_MWMSG_DDR_DATA_END(x)                (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_DATA_END_SHIFT)) & I3C_MWMSG_DDR_DATA_END_MASK)
/*! @} */

/*! @name MRMSG_DDR - Master Read Message in DDR mode */
/*! @{ */

#define I3C_MRMSG_DDR_DATA_MASK                  (0xFFFFU)
#define I3C_MRMSG_DDR_DATA_SHIFT                 (0U)
/*! DATA - Data
 */
#define I3C_MRMSG_DDR_DATA(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MRMSG_DDR_DATA_SHIFT)) & I3C_MRMSG_DDR_DATA_MASK)

#define I3C_MRMSG_DDR_CLEN_MASK                  (0x3FF0000U)
#define I3C_MRMSG_DDR_CLEN_SHIFT                 (16U)
/*! CLEN - Current length
 */
#define I3C_MRMSG_DDR_CLEN(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MRMSG_DDR_CLEN_SHIFT)) & I3C_MRMSG_DDR_CLEN_MASK)
/*! @} */

/*! @name MDYNADDR - Master Dynamic Address Register */
/*! @{ */

#define I3C_MDYNADDR_DAVALID_MASK                (0x1U)
#define I3C_MDYNADDR_DAVALID_SHIFT               (0U)
/*! DAVALID - Dynamic address valid
 */
#define I3C_MDYNADDR_DAVALID(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MDYNADDR_DAVALID_SHIFT)) & I3C_MDYNADDR_DAVALID_MASK)

#define I3C_MDYNADDR_DADDR_MASK                  (0xFEU)
#define I3C_MDYNADDR_DADDR_SHIFT                 (1U)
/*! DADDR - Dynamic address
 */
#define I3C_MDYNADDR_DADDR(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MDYNADDR_DADDR_SHIFT)) & I3C_MDYNADDR_DADDR_MASK)
/*! @} */

/*! @name SID - Slave Module ID */
/*! @{ */

#define I3C_SID_ID_MASK                          (0xFFFFFFFFU)
#define I3C_SID_ID_SHIFT                         (0U)
/*! ID - ID
 */
#define I3C_SID_ID(x)                            (((uint32_t)(((uint32_t)(x)) << I3C_SID_ID_SHIFT)) & I3C_SID_ID_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group I3C_Register_Masks */


/* I3C - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral I3C base address */
  #define I3C_BASE                                 (0x50035000u)
  /** Peripheral I3C base address */
  #define I3C_BASE_NS                              (0x40035000u)
  /** Peripheral I3C base pointer */
  #define I3C                                      ((I3C_Type *)I3C_BASE)
  /** Peripheral I3C base pointer */
  #define I3C_NS                                   ((I3C_Type *)I3C_BASE_NS)
  /** Array initializer of I3C peripheral base addresses */
  #define I3C_BASE_ADDRS                           { I3C_BASE }
  /** Array initializer of I3C peripheral base pointers */
  #define I3C_BASE_PTRS                            { I3C }
  /** Array initializer of I3C peripheral base addresses */
  #define I3C_BASE_ADDRS_NS                        { I3C_BASE_NS }
  /** Array initializer of I3C peripheral base pointers */
  #define I3C_BASE_PTRS_NS                         { I3C_NS }
#else
  /** Peripheral I3C base address */
  #define I3C_BASE                                 (0x40035000u)
  /** Peripheral I3C base pointer */
  #define I3C                                      ((I3C_Type *)I3C_BASE)
  /** Array initializer of I3C peripheral base addresses */
  #define I3C_BASE_ADDRS                           { I3C_BASE }
  /** Array initializer of I3C peripheral base pointers */
  #define I3C_BASE_PTRS                            { I3C }
#endif
/** Interrupt vectors for the I3C peripheral type */
#define I3C_IRQS                                 { I3C0_IRQn }

/*!
 * @}
 */ /* end of group I3C_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LPCMP Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LPCMP_Peripheral_Access_Layer LPCMP Peripheral Access Layer
 * @{
 */

/** LPCMP - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
  __IO uint32_t CCR0;                              /**< Comparator Control Register 0, offset: 0x8 */
  __IO uint32_t CCR1;                              /**< Comparator Control Register 1, offset: 0xC */
  __IO uint32_t CCR2;                              /**< Comparator Control Register 2, offset: 0x10 */
       uint8_t RESERVED_0[4];
  __IO uint32_t DCR;                               /**< DAC Control Register, offset: 0x18 */
  __IO uint32_t IER;                               /**< Interrupt Enable Register, offset: 0x1C */
  __IO uint32_t CSR;                               /**< Comparator Status Register, offset: 0x20 */
} LPCMP_Type;

/* ----------------------------------------------------------------------------
   -- LPCMP Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LPCMP_Register_Masks LPCMP Register Masks
 * @{
 */

/*! @name VERID - Version ID Register */
/*! @{ */

#define LPCMP_VERID_FEATURE_MASK                 (0xFFFFU)
#define LPCMP_VERID_FEATURE_SHIFT                (0U)
/*! FEATURE - Feature Specification Number
 *  0b0000000000000001..Round robin feature
 */
#define LPCMP_VERID_FEATURE(x)                   (((uint32_t)(((uint32_t)(x)) << LPCMP_VERID_FEATURE_SHIFT)) & LPCMP_VERID_FEATURE_MASK)

#define LPCMP_VERID_MINOR_MASK                   (0xFF0000U)
#define LPCMP_VERID_MINOR_SHIFT                  (16U)
/*! MINOR - Minor Version Number
 */
#define LPCMP_VERID_MINOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPCMP_VERID_MINOR_SHIFT)) & LPCMP_VERID_MINOR_MASK)

#define LPCMP_VERID_MAJOR_MASK                   (0xFF000000U)
#define LPCMP_VERID_MAJOR_SHIFT                  (24U)
/*! MAJOR - Major Version Number
 */
#define LPCMP_VERID_MAJOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPCMP_VERID_MAJOR_SHIFT)) & LPCMP_VERID_MAJOR_MASK)
/*! @} */

/*! @name PARAM - Parameter Register */
/*! @{ */

#define LPCMP_PARAM_DAC_RES_MASK                 (0xFU)
#define LPCMP_PARAM_DAC_RES_SHIFT                (0U)
/*! DAC_RES - DAC Resolution
 *  0b0000..4 bit DAC
 *  0b0001..6 bit DAC
 *  0b0010..8 bit DAC
 *  0b0011..10 bit DAC
 *  0b0100..12 bit DAC
 *  0b0101..14 bit DAC
 *  0b0110..16 bit DAC
 */
#define LPCMP_PARAM_DAC_RES(x)                   (((uint32_t)(((uint32_t)(x)) << LPCMP_PARAM_DAC_RES_SHIFT)) & LPCMP_PARAM_DAC_RES_MASK)
/*! @} */

/*! @name CCR0 - Comparator Control Register 0 */
/*! @{ */

#define LPCMP_CCR0_CMP_EN_MASK                   (0x1U)
#define LPCMP_CCR0_CMP_EN_SHIFT                  (0U)
/*! CMP_EN - Comparator Enable
 *  0b0..Disable (The analog logic remains off and consumes no power.)
 *  0b1..Enable
 */
#define LPCMP_CCR0_CMP_EN(x)                     (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR0_CMP_EN_SHIFT)) & LPCMP_CCR0_CMP_EN_MASK)

#define LPCMP_CCR0_CMP_STOP_EN_MASK              (0x2U)
#define LPCMP_CCR0_CMP_STOP_EN_SHIFT             (1U)
/*! CMP_STOP_EN - Comparator Sleep Mode Enable
 *  0b0..Disable the analog comparator regardless of CMP_EN.
 *  0b1..Allow the analog comparator to be enabled by CMP_EN.
 */
#define LPCMP_CCR0_CMP_STOP_EN(x)                (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR0_CMP_STOP_EN_SHIFT)) & LPCMP_CCR0_CMP_STOP_EN_MASK)
/*! @} */

/*! @name CCR1 - Comparator Control Register 1 */
/*! @{ */

#define LPCMP_CCR1_WINDOW_EN_MASK                (0x1U)
#define LPCMP_CCR1_WINDOW_EN_SHIFT               (0U)
/*! WINDOW_EN - Windowing Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPCMP_CCR1_WINDOW_EN(x)                  (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_WINDOW_EN_SHIFT)) & LPCMP_CCR1_WINDOW_EN_MASK)

#define LPCMP_CCR1_SAMPLE_EN_MASK                (0x2U)
#define LPCMP_CCR1_SAMPLE_EN_SHIFT               (1U)
/*! SAMPLE_EN - Sampling Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPCMP_CCR1_SAMPLE_EN(x)                  (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_SAMPLE_EN_SHIFT)) & LPCMP_CCR1_SAMPLE_EN_MASK)

#define LPCMP_CCR1_DMA_EN_MASK                   (0x4U)
#define LPCMP_CCR1_DMA_EN_SHIFT                  (2U)
/*! DMA_EN - DMA Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPCMP_CCR1_DMA_EN(x)                     (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_DMA_EN_SHIFT)) & LPCMP_CCR1_DMA_EN_MASK)

#define LPCMP_CCR1_COUT_INV_MASK                 (0x8U)
#define LPCMP_CCR1_COUT_INV_SHIFT                (3U)
/*! COUT_INV - Comparator Invert
 *  0b0..Do not invert
 *  0b1..Invert
 */
#define LPCMP_CCR1_COUT_INV(x)                   (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUT_INV_SHIFT)) & LPCMP_CCR1_COUT_INV_MASK)

#define LPCMP_CCR1_COUT_SEL_MASK                 (0x10U)
#define LPCMP_CCR1_COUT_SEL_SHIFT                (4U)
/*! COUT_SEL - Comparator Output Select
 *  0b0..Use COUT (filtered)
 *  0b1..Use COUTA (unfiltered)
 */
#define LPCMP_CCR1_COUT_SEL(x)                   (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUT_SEL_SHIFT)) & LPCMP_CCR1_COUT_SEL_MASK)

#define LPCMP_CCR1_COUT_PEN_MASK                 (0x20U)
#define LPCMP_CCR1_COUT_PEN_SHIFT                (5U)
/*! COUT_PEN - Comparator Output Pin Enable
 *  0b0..Not available
 *  0b1..Available
 */
#define LPCMP_CCR1_COUT_PEN(x)                   (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUT_PEN_SHIFT)) & LPCMP_CCR1_COUT_PEN_MASK)

#define LPCMP_CCR1_COUTA_OWEN_MASK               (0x40U)
#define LPCMP_CCR1_COUTA_OWEN_SHIFT              (6U)
/*! COUTA_OWEN - COUTA_OW Enable
 *  0b0..COUTA holds the last sampled value
 *  0b1..COUTA is defined by the COUTA_OW bit
 */
#define LPCMP_CCR1_COUTA_OWEN(x)                 (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUTA_OWEN_SHIFT)) & LPCMP_CCR1_COUTA_OWEN_MASK)

#define LPCMP_CCR1_COUTA_OW_MASK                 (0x80U)
#define LPCMP_CCR1_COUTA_OW_SHIFT                (7U)
/*! COUTA_OW - COUTA Output Level for Closed Window
 *  0b0..COUTA is 0
 *  0b1..COUTA is 1
 */
#define LPCMP_CCR1_COUTA_OW(x)                   (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUTA_OW_SHIFT)) & LPCMP_CCR1_COUTA_OW_MASK)

#define LPCMP_CCR1_WINDOW_INV_MASK               (0x100U)
#define LPCMP_CCR1_WINDOW_INV_SHIFT              (8U)
/*! WINDOW_INV - WINDOW/SAMPLE Signal Invert
 *  0b0..Do not invert
 *  0b1..Invert
 */
#define LPCMP_CCR1_WINDOW_INV(x)                 (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_WINDOW_INV_SHIFT)) & LPCMP_CCR1_WINDOW_INV_MASK)

#define LPCMP_CCR1_WINDOW_CLS_MASK               (0x200U)
#define LPCMP_CCR1_WINDOW_CLS_SHIFT              (9U)
/*! WINDOW_CLS - CMPO Event Window Close
 *  0b0..CMPO event cannot close the window
 *  0b1..CMPO event can close the window
 */
#define LPCMP_CCR1_WINDOW_CLS(x)                 (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_WINDOW_CLS_SHIFT)) & LPCMP_CCR1_WINDOW_CLS_MASK)

#define LPCMP_CCR1_EVT_SEL_MASK                  (0xC00U)
#define LPCMP_CCR1_EVT_SEL_SHIFT                 (10U)
/*! EVT_SEL - CMPO Event Select
 *  0b00..Rising edge
 *  0b01..Falling edge
 *  0b1x..Both edges
 */
#define LPCMP_CCR1_EVT_SEL(x)                    (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_EVT_SEL_SHIFT)) & LPCMP_CCR1_EVT_SEL_MASK)

#define LPCMP_CCR1_FILT_CNT_MASK                 (0x70000U)
#define LPCMP_CCR1_FILT_CNT_SHIFT                (16U)
/*! FILT_CNT - Filter Sample Count
 *  0b000..Filter is bypassed: COUT = COUTA
 *  0b001..1 consecutive sample (Comparator output is simply sampled.)
 *  0b010..2 consecutive samples
 *  0b011..3 consecutive samples
 *  0b100..4 consecutive samples
 *  0b101..5 consecutive samples
 *  0b110..6 consecutive samples
 *  0b111..7 consecutive samples
 */
#define LPCMP_CCR1_FILT_CNT(x)                   (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_FILT_CNT_SHIFT)) & LPCMP_CCR1_FILT_CNT_MASK)

#define LPCMP_CCR1_FILT_PER_MASK                 (0xFF000000U)
#define LPCMP_CCR1_FILT_PER_SHIFT                (24U)
/*! FILT_PER - Filter Sample Period
 */
#define LPCMP_CCR1_FILT_PER(x)                   (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_FILT_PER_SHIFT)) & LPCMP_CCR1_FILT_PER_MASK)
/*! @} */

/*! @name CCR2 - Comparator Control Register 2 */
/*! @{ */

#define LPCMP_CCR2_CMP_HPMD_MASK                 (0x1U)
#define LPCMP_CCR2_CMP_HPMD_SHIFT                (0U)
/*! CMP_HPMD - CMP High Power Mode Select
 *  0b0..Low power(speed) comparison mode
 *  0b1..High power(speed) comparison mode
 */
#define LPCMP_CCR2_CMP_HPMD(x)                   (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_CMP_HPMD_SHIFT)) & LPCMP_CCR2_CMP_HPMD_MASK)

#define LPCMP_CCR2_CMP_NPMD_MASK                 (0x2U)
#define LPCMP_CCR2_CMP_NPMD_SHIFT                (1U)
/*! CMP_NPMD - CMP Nano Power Mode Select
 *  0b0..Disable (Mode is determined by CMP_HPMD.)
 *  0b1..Enable
 */
#define LPCMP_CCR2_CMP_NPMD(x)                   (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_CMP_NPMD_SHIFT)) & LPCMP_CCR2_CMP_NPMD_MASK)

#define LPCMP_CCR2_HYSTCTR_MASK                  (0x30U)
#define LPCMP_CCR2_HYSTCTR_SHIFT                 (4U)
/*! HYSTCTR - Comparator Hysteresis Control
 *  0b00..Level 0
 *  0b01..Level 1
 *  0b10..Level 2
 *  0b11..Level 3
 */
#define LPCMP_CCR2_HYSTCTR(x)                    (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_HYSTCTR_SHIFT)) & LPCMP_CCR2_HYSTCTR_MASK)

#define LPCMP_CCR2_PSEL_MASK                     (0x70000U)
#define LPCMP_CCR2_PSEL_SHIFT                    (16U)
/*! PSEL - Plus Input MUX Select
 *  0b000..Input 0p
 *  0b001..Input 1p
 *  0b010..Input 2p
 *  0b011..Input 3p
 *  0b100..Input 4p
 *  0b101..Input 5p
 *  0b110..Reserved
 *  0b111..Internal DAC output
 */
#define LPCMP_CCR2_PSEL(x)                       (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_PSEL_SHIFT)) & LPCMP_CCR2_PSEL_MASK)

#define LPCMP_CCR2_MSEL_MASK                     (0x700000U)
#define LPCMP_CCR2_MSEL_SHIFT                    (20U)
/*! MSEL - Minus Input MUX Select
 *  0b000..Input 0m
 *  0b001..Input 1m
 *  0b010..Input 2m
 *  0b011..Input 3m
 *  0b100..Input 4m
 *  0b101..Input 5m
 *  0b110..Reserved
 *  0b111..Internal DAC output
 */
#define LPCMP_CCR2_MSEL(x)                       (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_MSEL_SHIFT)) & LPCMP_CCR2_MSEL_MASK)
/*! @} */

/*! @name DCR - DAC Control Register */
/*! @{ */

#define LPCMP_DCR_DAC_EN_MASK                    (0x1U)
#define LPCMP_DCR_DAC_EN_SHIFT                   (0U)
/*! DAC_EN - DAC Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPCMP_DCR_DAC_EN(x)                      (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_DAC_EN_SHIFT)) & LPCMP_DCR_DAC_EN_MASK)

#define LPCMP_DCR_DAC_HPMD_MASK                  (0x2U)
#define LPCMP_DCR_DAC_HPMD_SHIFT                 (1U)
/*! DAC_HPMD - DAC High Power Mode Select
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPCMP_DCR_DAC_HPMD(x)                    (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_DAC_HPMD_SHIFT)) & LPCMP_DCR_DAC_HPMD_MASK)

#define LPCMP_DCR_VRSEL_MASK                     (0x100U)
#define LPCMP_DCR_VRSEL_SHIFT                    (8U)
/*! VRSEL - DAC Reference High Voltage Source Select
 *  0b0..vrefh0
 *  0b1..vrefh1
 */
#define LPCMP_DCR_VRSEL(x)                       (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_VRSEL_SHIFT)) & LPCMP_DCR_VRSEL_MASK)

#define LPCMP_DCR_DAC_DATA_MASK                  (0xFF0000U)
#define LPCMP_DCR_DAC_DATA_SHIFT                 (16U)
/*! DAC_DATA - DAC Output Voltage Select
 */
#define LPCMP_DCR_DAC_DATA(x)                    (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_DAC_DATA_SHIFT)) & LPCMP_DCR_DAC_DATA_MASK)
/*! @} */

/*! @name IER - Interrupt Enable Register */
/*! @{ */

#define LPCMP_IER_CFR_IE_MASK                    (0x1U)
#define LPCMP_IER_CFR_IE_SHIFT                   (0U)
/*! CFR_IE - Comparator Flag Rising Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable: Assert an interrupt when CFR is set.
 */
#define LPCMP_IER_CFR_IE(x)                      (((uint32_t)(((uint32_t)(x)) << LPCMP_IER_CFR_IE_SHIFT)) & LPCMP_IER_CFR_IE_MASK)

#define LPCMP_IER_CFF_IE_MASK                    (0x2U)
#define LPCMP_IER_CFF_IE_SHIFT                   (1U)
/*! CFF_IE - Comparator Flag Falling Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable: Assert an interrupt when CFF is set.
 */
#define LPCMP_IER_CFF_IE(x)                      (((uint32_t)(((uint32_t)(x)) << LPCMP_IER_CFF_IE_SHIFT)) & LPCMP_IER_CFF_IE_MASK)
/*! @} */

/*! @name CSR - Comparator Status Register */
/*! @{ */

#define LPCMP_CSR_CFR_MASK                       (0x1U)
#define LPCMP_CSR_CFR_SHIFT                      (0U)
/*! CFR - Analog Comparator Flag Rising
 *  0b0..Not detected
 *  0b1..Detected
 */
#define LPCMP_CSR_CFR(x)                         (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_CFR_SHIFT)) & LPCMP_CSR_CFR_MASK)

#define LPCMP_CSR_CFF_MASK                       (0x2U)
#define LPCMP_CSR_CFF_SHIFT                      (1U)
/*! CFF - Analog Comparator Flag Falling
 *  0b0..Not detected
 *  0b1..Detected
 */
#define LPCMP_CSR_CFF(x)                         (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_CFF_SHIFT)) & LPCMP_CSR_CFF_MASK)

#define LPCMP_CSR_COUT_MASK                      (0x100U)
#define LPCMP_CSR_COUT_SHIFT                     (8U)
/*! COUT - Analog Comparator Output
 */
#define LPCMP_CSR_COUT(x)                        (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_COUT_SHIFT)) & LPCMP_CSR_COUT_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LPCMP_Register_Masks */


/* LPCMP - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral LPCMP0 base address */
  #define LPCMP0_BASE                              (0x50048000u)
  /** Peripheral LPCMP0 base address */
  #define LPCMP0_BASE_NS                           (0x40048000u)
  /** Peripheral LPCMP0 base pointer */
  #define LPCMP0                                   ((LPCMP_Type *)LPCMP0_BASE)
  /** Peripheral LPCMP0 base pointer */
  #define LPCMP0_NS                                ((LPCMP_Type *)LPCMP0_BASE_NS)
  /** Peripheral LPCMP1 base address */
  #define LPCMP1_BASE                              (0x50049000u)
  /** Peripheral LPCMP1 base address */
  #define LPCMP1_BASE_NS                           (0x40049000u)
  /** Peripheral LPCMP1 base pointer */
  #define LPCMP1                                   ((LPCMP_Type *)LPCMP1_BASE)
  /** Peripheral LPCMP1 base pointer */
  #define LPCMP1_NS                                ((LPCMP_Type *)LPCMP1_BASE_NS)
  /** Array initializer of LPCMP peripheral base addresses */
  #define LPCMP_BASE_ADDRS                         { LPCMP0_BASE, LPCMP1_BASE }
  /** Array initializer of LPCMP peripheral base pointers */
  #define LPCMP_BASE_PTRS                          { LPCMP0, LPCMP1 }
  /** Array initializer of LPCMP peripheral base addresses */
  #define LPCMP_BASE_ADDRS_NS                      { LPCMP0_BASE_NS, LPCMP1_BASE_NS }
  /** Array initializer of LPCMP peripheral base pointers */
  #define LPCMP_BASE_PTRS_NS                       { LPCMP0_NS, LPCMP1_NS }
#else
  /** Peripheral LPCMP0 base address */
  #define LPCMP0_BASE                              (0x40048000u)
  /** Peripheral LPCMP0 base pointer */
  #define LPCMP0                                   ((LPCMP_Type *)LPCMP0_BASE)
  /** Peripheral LPCMP1 base address */
  #define LPCMP1_BASE                              (0x40049000u)
  /** Peripheral LPCMP1 base pointer */
  #define LPCMP1                                   ((LPCMP_Type *)LPCMP1_BASE)
  /** Array initializer of LPCMP peripheral base addresses */
  #define LPCMP_BASE_ADDRS                         { LPCMP0_BASE, LPCMP1_BASE }
  /** Array initializer of LPCMP peripheral base pointers */
  #define LPCMP_BASE_PTRS                          { LPCMP0, LPCMP1 }
#endif

/*!
 * @}
 */ /* end of group LPCMP_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LPI2C Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer
 * @{
 */

/** LPI2C - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
  __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
       uint8_t RESERVED_0[8];
  __IO uint32_t MCR;                               /**< Master Control, offset: 0x10 */
  __IO uint32_t MSR;                               /**< Master Status, offset: 0x14 */
  __IO uint32_t MIER;                              /**< Master Interrupt Enable, offset: 0x18 */
  __IO uint32_t MDER;                              /**< Master DMA Enable, offset: 0x1C */
  __IO uint32_t MCFGR0;                            /**< Master Configuration 0, offset: 0x20 */
  __IO uint32_t MCFGR1;                            /**< Master Configuration 1, offset: 0x24 */
  __IO uint32_t MCFGR2;                            /**< Master Configuration 2, offset: 0x28 */
  __IO uint32_t MCFGR3;                            /**< Master Configuration 3, offset: 0x2C */
       uint8_t RESERVED_1[16];
  __IO uint32_t MDMR;                              /**< Master Data Match, offset: 0x40 */
       uint8_t RESERVED_2[4];
  __IO uint32_t MCCR0;                             /**< Master Clock Configuration 0, offset: 0x48 */
       uint8_t RESERVED_3[4];
  __IO uint32_t MCCR1;                             /**< Master Clock Configuration 1, offset: 0x50 */
       uint8_t RESERVED_4[4];
  __IO uint32_t MFCR;                              /**< Master FIFO Control, offset: 0x58 */
  __I  uint32_t MFSR;                              /**< Master FIFO Status, offset: 0x5C */
  __O  uint32_t MTDR;                              /**< Master Transmit Data, offset: 0x60 */
       uint8_t RESERVED_5[12];
  __I  uint32_t MRDR;                              /**< Master Receive Data, offset: 0x70 */
       uint8_t RESERVED_6[4];
  __I  uint32_t MRDROR;                            /**< Master Receive Data Read Only, offset: 0x78 */
       uint8_t RESERVED_7[148];
  __IO uint32_t SCR;                               /**< Slave Control, offset: 0x110 */
  __IO uint32_t SSR;                               /**< Slave Status, offset: 0x114 */
  __IO uint32_t SIER;                              /**< Slave Interrupt Enable, offset: 0x118 */
  __IO uint32_t SDER;                              /**< Slave DMA Enable, offset: 0x11C */
  __IO uint32_t SCFGR0;                            /**< Slave Configuration 0, offset: 0x120 */
  __IO uint32_t SCFGR1;                            /**< Slave Configuration 1, offset: 0x124 */
  __IO uint32_t SCFGR2;                            /**< Slave Configuration 2, offset: 0x128 */
       uint8_t RESERVED_8[20];
  __IO uint32_t SAMR;                              /**< Slave Address Match, offset: 0x140 */
       uint8_t RESERVED_9[12];
  __I  uint32_t SASR;                              /**< Slave Address Status, offset: 0x150 */
  __IO uint32_t STAR;                              /**< Slave Transmit ACK, offset: 0x154 */
       uint8_t RESERVED_10[8];
  __O  uint32_t STDR;                              /**< Slave Transmit Data, offset: 0x160 */
       uint8_t RESERVED_11[12];
  __I  uint32_t SRDR;                              /**< Slave Receive Data, offset: 0x170 */
       uint8_t RESERVED_12[4];
  __I  uint32_t SRDROR;                            /**< Slave Receive Data Read Only, offset: 0x178 */
} LPI2C_Type;

/* ----------------------------------------------------------------------------
   -- LPI2C Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LPI2C_Register_Masks LPI2C Register Masks
 * @{
 */

/*! @name VERID - Version ID */
/*! @{ */

#define LPI2C_VERID_FEATURE_MASK                 (0xFFFFU)
#define LPI2C_VERID_FEATURE_SHIFT                (0U)
/*! FEATURE - Feature Specification Number
 *  0b0000000000000010..Master only, with standard feature set
 *  0b0000000000000011..Master and slave, with standard feature set
 */
#define LPI2C_VERID_FEATURE(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK)

#define LPI2C_VERID_MINOR_MASK                   (0xFF0000U)
#define LPI2C_VERID_MINOR_SHIFT                  (16U)
/*! MINOR - Minor Version Number
 */
#define LPI2C_VERID_MINOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK)

#define LPI2C_VERID_MAJOR_MASK                   (0xFF000000U)
#define LPI2C_VERID_MAJOR_SHIFT                  (24U)
/*! MAJOR - Major Version Number
 */
#define LPI2C_VERID_MAJOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK)
/*! @} */

/*! @name PARAM - Parameter */
/*! @{ */

#define LPI2C_PARAM_MTXFIFO_MASK                 (0xFU)
#define LPI2C_PARAM_MTXFIFO_SHIFT                (0U)
/*! MTXFIFO - Master Transmit FIFO Size
 */
#define LPI2C_PARAM_MTXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK)

#define LPI2C_PARAM_MRXFIFO_MASK                 (0xF00U)
#define LPI2C_PARAM_MRXFIFO_SHIFT                (8U)
/*! MRXFIFO - Master Receive FIFO Size
 */
#define LPI2C_PARAM_MRXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK)
/*! @} */

/*! @name MCR - Master Control */
/*! @{ */

#define LPI2C_MCR_MEN_MASK                       (0x1U)
#define LPI2C_MCR_MEN_SHIFT                      (0U)
/*! MEN - Master Enable
 *  0b0..Master logic is disabled
 *  0b1..Master logic is enabled
 */
#define LPI2C_MCR_MEN(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK)

#define LPI2C_MCR_RST_MASK                       (0x2U)
#define LPI2C_MCR_RST_SHIFT                      (1U)
/*! RST - Software Reset
 *  0b0..Master logic is not reset
 *  0b1..Master logic is reset
 */
#define LPI2C_MCR_RST(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK)

#define LPI2C_MCR_DOZEN_MASK                     (0x4U)
#define LPI2C_MCR_DOZEN_SHIFT                    (2U)
/*! DOZEN - Doze mode enable
 *  0b0..Master is enabled in Doze mode
 *  0b1..Master is disabled in Doze mode
 */
#define LPI2C_MCR_DOZEN(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK)

#define LPI2C_MCR_DBGEN_MASK                     (0x8U)
#define LPI2C_MCR_DBGEN_SHIFT                    (3U)
/*! DBGEN - Debug Enable
 *  0b0..Master is disabled in debug mode
 *  0b1..Master is enabled in debug mode
 */
#define LPI2C_MCR_DBGEN(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK)

#define LPI2C_MCR_RTF_MASK                       (0x100U)
#define LPI2C_MCR_RTF_SHIFT                      (8U)
/*! RTF - Reset Transmit FIFO
 *  0b0..No effect
 *  0b1..Transmit FIFO is reset
 */
#define LPI2C_MCR_RTF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK)

#define LPI2C_MCR_RRF_MASK                       (0x200U)
#define LPI2C_MCR_RRF_SHIFT                      (9U)
/*! RRF - Reset Receive FIFO
 *  0b0..No effect
 *  0b1..Receive FIFO is reset
 */
#define LPI2C_MCR_RRF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK)
/*! @} */

/*! @name MSR - Master Status */
/*! @{ */

#define LPI2C_MSR_TDF_MASK                       (0x1U)
#define LPI2C_MSR_TDF_SHIFT                      (0U)
/*! TDF - Transmit Data Flag
 *  0b0..Transmit data is not requested
 *  0b1..Transmit data is requested
 */
#define LPI2C_MSR_TDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK)

#define LPI2C_MSR_RDF_MASK                       (0x2U)
#define LPI2C_MSR_RDF_SHIFT                      (1U)
/*! RDF - Receive Data Flag
 *  0b0..Receive Data is not ready
 *  0b1..Receive data is ready
 */
#define LPI2C_MSR_RDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK)

#define LPI2C_MSR_EPF_MASK                       (0x100U)
#define LPI2C_MSR_EPF_SHIFT                      (8U)
/*! EPF - End Packet Flag
 *  0b0..Master has not generated a STOP or Repeated START condition
 *  0b1..Master has generated a STOP or Repeated START condition
 */
#define LPI2C_MSR_EPF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK)

#define LPI2C_MSR_SDF_MASK                       (0x200U)
#define LPI2C_MSR_SDF_SHIFT                      (9U)
/*! SDF - STOP Detect Flag
 *  0b0..Master has not generated a STOP condition
 *  0b1..Master has generated a STOP condition
 */
#define LPI2C_MSR_SDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK)

#define LPI2C_MSR_NDF_MASK                       (0x400U)
#define LPI2C_MSR_NDF_SHIFT                      (10U)
/*! NDF - NACK Detect Flag
 *  0b0..Unexpected NACK was not detected
 *  0b1..Unexpected NACK was detected
 */
#define LPI2C_MSR_NDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK)

#define LPI2C_MSR_ALF_MASK                       (0x800U)
#define LPI2C_MSR_ALF_SHIFT                      (11U)
/*! ALF - Arbitration Lost Flag
 *  0b0..Master has not lost arbitration
 *  0b1..Master has lost arbitration
 */
#define LPI2C_MSR_ALF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK)

#define LPI2C_MSR_FEF_MASK                       (0x1000U)
#define LPI2C_MSR_FEF_SHIFT                      (12U)
/*! FEF - FIFO Error Flag
 *  0b0..No error
 *  0b1..Master sending or receiving data without a START condition
 */
#define LPI2C_MSR_FEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK)

#define LPI2C_MSR_PLTF_MASK                      (0x2000U)
#define LPI2C_MSR_PLTF_SHIFT                     (13U)
/*! PLTF - Pin Low Timeout Flag
 *  0b0..Pin low timeout has not occurred or is disabled
 *  0b1..Pin low timeout has occurred
 */
#define LPI2C_MSR_PLTF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK)

#define LPI2C_MSR_DMF_MASK                       (0x4000U)
#define LPI2C_MSR_DMF_SHIFT                      (14U)
/*! DMF - Data Match Flag
 *  0b0..Have not received matching data
 *  0b1..Have received matching data
 */
#define LPI2C_MSR_DMF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK)

#define LPI2C_MSR_STF_MASK                       (0x8000U)
#define LPI2C_MSR_STF_SHIFT                      (15U)
/*! STF - START Flag
 *  0b0..START condition not detected.
 *  0b1..START condition detected.
 */
#define LPI2C_MSR_STF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_STF_SHIFT)) & LPI2C_MSR_STF_MASK)

#define LPI2C_MSR_MBF_MASK                       (0x1000000U)
#define LPI2C_MSR_MBF_SHIFT                      (24U)
/*! MBF - Master Busy Flag
 *  0b0..I2C Master is idle
 *  0b1..I2C Master is busy
 */
#define LPI2C_MSR_MBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK)

#define LPI2C_MSR_BBF_MASK                       (0x2000000U)
#define LPI2C_MSR_BBF_SHIFT                      (25U)
/*! BBF - Bus Busy Flag
 *  0b0..I2C Bus is idle
 *  0b1..I2C Bus is busy
 */
#define LPI2C_MSR_BBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK)
/*! @} */

/*! @name MIER - Master Interrupt Enable */
/*! @{ */

#define LPI2C_MIER_TDIE_MASK                     (0x1U)
#define LPI2C_MIER_TDIE_SHIFT                    (0U)
/*! TDIE - Transmit Data Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_MIER_TDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK)

#define LPI2C_MIER_RDIE_MASK                     (0x2U)
#define LPI2C_MIER_RDIE_SHIFT                    (1U)
/*! RDIE - Receive Data Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_MIER_RDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK)

#define LPI2C_MIER_EPIE_MASK                     (0x100U)
#define LPI2C_MIER_EPIE_SHIFT                    (8U)
/*! EPIE - End Packet Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_MIER_EPIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK)

#define LPI2C_MIER_SDIE_MASK                     (0x200U)
#define LPI2C_MIER_SDIE_SHIFT                    (9U)
/*! SDIE - STOP Detect Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_MIER_SDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK)

#define LPI2C_MIER_NDIE_MASK                     (0x400U)
#define LPI2C_MIER_NDIE_SHIFT                    (10U)
/*! NDIE - NACK Detect Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_MIER_NDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK)

#define LPI2C_MIER_ALIE_MASK                     (0x800U)
#define LPI2C_MIER_ALIE_SHIFT                    (11U)
/*! ALIE - Arbitration Lost Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_MIER_ALIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK)

#define LPI2C_MIER_FEIE_MASK                     (0x1000U)
#define LPI2C_MIER_FEIE_SHIFT                    (12U)
/*! FEIE - FIFO Error Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_MIER_FEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK)

#define LPI2C_MIER_PLTIE_MASK                    (0x2000U)
#define LPI2C_MIER_PLTIE_SHIFT                   (13U)
/*! PLTIE - Pin Low Timeout Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_MIER_PLTIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK)

#define LPI2C_MIER_DMIE_MASK                     (0x4000U)
#define LPI2C_MIER_DMIE_SHIFT                    (14U)
/*! DMIE - Data Match Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_MIER_DMIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK)

#define LPI2C_MIER_STIE_MASK                     (0x8000U)
#define LPI2C_MIER_STIE_SHIFT                    (15U)
/*! STIE - START Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_MIER_STIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_STIE_SHIFT)) & LPI2C_MIER_STIE_MASK)
/*! @} */

/*! @name MDER - Master DMA Enable */
/*! @{ */

#define LPI2C_MDER_TDDE_MASK                     (0x1U)
#define LPI2C_MDER_TDDE_SHIFT                    (0U)
/*! TDDE - Transmit Data DMA Enable
 *  0b0..DMA request is disabled
 *  0b1..DMA request is enabled
 */
#define LPI2C_MDER_TDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK)

#define LPI2C_MDER_RDDE_MASK                     (0x2U)
#define LPI2C_MDER_RDDE_SHIFT                    (1U)
/*! RDDE - Receive Data DMA Enable
 *  0b0..DMA request is disabled
 *  0b1..DMA request is enabled
 */
#define LPI2C_MDER_RDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK)
/*! @} */

/*! @name MCFGR0 - Master Configuration 0 */
/*! @{ */

#define LPI2C_MCFGR0_HREN_MASK                   (0x1U)
#define LPI2C_MCFGR0_HREN_SHIFT                  (0U)
/*! HREN - Host Request Enable
 *  0b0..Host request input is disabled
 *  0b1..Host request input is enabled
 */
#define LPI2C_MCFGR0_HREN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK)

#define LPI2C_MCFGR0_HRPOL_MASK                  (0x2U)
#define LPI2C_MCFGR0_HRPOL_SHIFT                 (1U)
/*! HRPOL - Host Request Polarity
 *  0b0..Active low
 *  0b1..Active high
 */
#define LPI2C_MCFGR0_HRPOL(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK)

#define LPI2C_MCFGR0_HRSEL_MASK                  (0x4U)
#define LPI2C_MCFGR0_HRSEL_SHIFT                 (2U)
/*! HRSEL - Host Request Select
 *  0b0..
 *  0b1..Host request input is input trigger
 */
#define LPI2C_MCFGR0_HRSEL(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK)

#define LPI2C_MCFGR0_CIRFIFO_MASK                (0x100U)
#define LPI2C_MCFGR0_CIRFIFO_SHIFT               (8U)
/*! CIRFIFO - Circular FIFO Enable
 *  0b0..Circular FIFO is disabled
 *  0b1..Circular FIFO is enabled
 */
#define LPI2C_MCFGR0_CIRFIFO(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK)

#define LPI2C_MCFGR0_RDMO_MASK                   (0x200U)
#define LPI2C_MCFGR0_RDMO_SHIFT                  (9U)
/*! RDMO - Receive Data Match Only
 *  0b0..Received data is stored in the receive FIFO
 *  0b1..Received data is discarded unless the the Data Match Flag (MSR[DMF]) is set
 */
#define LPI2C_MCFGR0_RDMO(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK)

#define LPI2C_MCFGR0_RELAX_MASK                  (0x10000U)
#define LPI2C_MCFGR0_RELAX_SHIFT                 (16U)
/*! RELAX - Relaxed Mode
 *  0b0..Normal transfer
 *  0b1..Relaxed transfer
 */
#define LPI2C_MCFGR0_RELAX(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RELAX_SHIFT)) & LPI2C_MCFGR0_RELAX_MASK)

#define LPI2C_MCFGR0_ABORT_MASK                  (0x20000U)
#define LPI2C_MCFGR0_ABORT_SHIFT                 (17U)
/*! ABORT - Abort Transfer
 *  0b0..Normal transfer
 *  0b1..Abort existing transfer and do not start new transfer
 */
#define LPI2C_MCFGR0_ABORT(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_ABORT_SHIFT)) & LPI2C_MCFGR0_ABORT_MASK)
/*! @} */

/*! @name MCFGR1 - Master Configuration 1 */
/*! @{ */

#define LPI2C_MCFGR1_PRESCALE_MASK               (0x7U)
#define LPI2C_MCFGR1_PRESCALE_SHIFT              (0U)
/*! PRESCALE - Prescaler
 *  0b000..Divide by 1
 *  0b001..Divide by 2
 *  0b010..Divide by 4
 *  0b011..Divide by 8
 *  0b100..Divide by 16
 *  0b101..Divide by 32
 *  0b110..Divide by 64
 *  0b111..Divide by 128
 */
#define LPI2C_MCFGR1_PRESCALE(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK)

#define LPI2C_MCFGR1_AUTOSTOP_MASK               (0x100U)
#define LPI2C_MCFGR1_AUTOSTOP_SHIFT              (8U)
/*! AUTOSTOP - Automatic STOP Generation
 *  0b0..No effect
 *  0b1..STOP condition is automatically generated whenever the transmit FIFO is empty and the LPI2C master is busy
 */
#define LPI2C_MCFGR1_AUTOSTOP(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK)

#define LPI2C_MCFGR1_IGNACK_MASK                 (0x200U)
#define LPI2C_MCFGR1_IGNACK_SHIFT                (9U)
/*! IGNACK - Ignore NACK
 *  0b0..No effect
 *  0b1..LPI2C Master treats a received NACK as if it (NACK) was an ACK and the NACK Detect Flag is never set.
 */
#define LPI2C_MCFGR1_IGNACK(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK)

#define LPI2C_MCFGR1_TIMECFG_MASK                (0x400U)
#define LPI2C_MCFGR1_TIMECFG_SHIFT               (10U)
/*! TIMECFG - Timeout Configuration
 *  0b0..MSR[PLTF] sets if SCL is low for longer than the configured timeout
 *  0b1..MSR[PLTF] sets if either SCL or SDA is low for longer than the configured timeout
 */
#define LPI2C_MCFGR1_TIMECFG(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK)

#define LPI2C_MCFGR1_STOPCFG_MASK                (0x800U)
#define LPI2C_MCFGR1_STOPCFG_SHIFT               (11U)
/*! STOPCFG - STOP Configuration
 *  0b0..MSR[SDF] asserts on any STOP condition generated by LPI2C master.
 *  0b1..MSR[SDF] asserts on last STOP condition before LPI2C master is idle (that is, the transmit FIFO is empty at the time of the STOP condition).
 */
#define LPI2C_MCFGR1_STOPCFG(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_STOPCFG_SHIFT)) & LPI2C_MCFGR1_STOPCFG_MASK)

#define LPI2C_MCFGR1_STARTCFG_MASK               (0x1000U)
#define LPI2C_MCFGR1_STARTCFG_SHIFT              (12U)
/*! STARTCFG - START Configuration
 *  0b0..MSR[STF] asserts on START condition provided both I2C bus and LPI2C master are idle (that is, any
 *       non-repeated START condition initiated by any other master on the bus but not the LPI2C master).
 *  0b1..MSR[STF] asserts on START condition provided I2C bus is idle (that is, any non-repeated START condition
 *       initiated by any master on the bus including the LPI2C master).
 */
#define LPI2C_MCFGR1_STARTCFG(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_STARTCFG_SHIFT)) & LPI2C_MCFGR1_STARTCFG_MASK)

#define LPI2C_MCFGR1_MATCFG_MASK                 (0x70000U)
#define LPI2C_MCFGR1_MATCFG_SHIFT                (16U)
/*! MATCFG - Match Configuration
 *  0b000..Match is disabled
 *  0b001..Reserved
 *  0b010..Match is enabled (1st data word equals MDMR[MATCH0] OR MDMR[MATCH1])
 *  0b011..Match is enabled (any data word equals MDMR[MATCH0] OR MDMR[MATCH1])
 *  0b100..Match is enabled (1st data word equals MDMR[MATCH0] AND 2nd data word equals MDMR[MATCH1)
 *  0b101..Match is enabled (any data word equals MDMR[MATCH0] AND next data word equals MDMR[MATCH1)
 *  0b110..Match is enabled (1st data word AND MDMR[MATCH1] equals MDMR[MATCH0] AND MDMR[MATCH1])
 *  0b111..Match is enabled (any data word AND MDMR[MATCH1] equals MDMR[MATCH0] AND MDMR[MATCH1])
 */
#define LPI2C_MCFGR1_MATCFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK)

#define LPI2C_MCFGR1_PINCFG_MASK                 (0x7000000U)
#define LPI2C_MCFGR1_PINCFG_SHIFT                (24U)
/*! PINCFG - Pin Configuration
 *  0b000..2-pin open drain mode
 *  0b001..2-pin output only mode (ultra-fast mode)
 *  0b010..2-pin push-pull mode
 *  0b011..4-pin push-pull mode
 *  0b100..2-pin open drain mode with separate LPI2C slave
 *  0b101..2-pin output only mode (ultra-fast mode) with separate LPI2C slave
 *  0b110..2-pin push-pull mode with separate LPI2C slave
 *  0b111..4-pin push-pull mode (inverted outputs)
 */
#define LPI2C_MCFGR1_PINCFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK)

#define LPI2C_MCFGR1_FRCHS_MASK                  (0x8000000U)
#define LPI2C_MCFGR1_FRCHS_SHIFT                 (27U)
/*! FRCHS - Force HS-mode
 *  0b0..No effect
 *  0b1..LPI2C pin state forced into HS-mode.
 */
#define LPI2C_MCFGR1_FRCHS(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_FRCHS_SHIFT)) & LPI2C_MCFGR1_FRCHS_MASK)
/*! @} */

/*! @name MCFGR2 - Master Configuration 2 */
/*! @{ */

#define LPI2C_MCFGR2_BUSIDLE_MASK                (0xFFFU)
#define LPI2C_MCFGR2_BUSIDLE_SHIFT               (0U)
/*! BUSIDLE - Bus Idle Timeout
 */
#define LPI2C_MCFGR2_BUSIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK)

#define LPI2C_MCFGR2_FILTSCL_MASK                (0xF0000U)
#define LPI2C_MCFGR2_FILTSCL_SHIFT               (16U)
/*! FILTSCL - Glitch Filter SCL
 */
#define LPI2C_MCFGR2_FILTSCL(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK)

#define LPI2C_MCFGR2_FILTSDA_MASK                (0xF000000U)
#define LPI2C_MCFGR2_FILTSDA_SHIFT               (24U)
/*! FILTSDA - Glitch Filter SDA
 */
#define LPI2C_MCFGR2_FILTSDA(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK)
/*! @} */

/*! @name MCFGR3 - Master Configuration 3 */
/*! @{ */

#define LPI2C_MCFGR3_PINLOW_MASK                 (0xFFF00U)
#define LPI2C_MCFGR3_PINLOW_SHIFT                (8U)
/*! PINLOW - Pin Low Timeout
 */
#define LPI2C_MCFGR3_PINLOW(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK)
/*! @} */

/*! @name MDMR - Master Data Match */
/*! @{ */

#define LPI2C_MDMR_MATCH0_MASK                   (0xFFU)
#define LPI2C_MDMR_MATCH0_SHIFT                  (0U)
/*! MATCH0 - Match 0 Value
 */
#define LPI2C_MDMR_MATCH0(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK)

#define LPI2C_MDMR_MATCH1_MASK                   (0xFF0000U)
#define LPI2C_MDMR_MATCH1_SHIFT                  (16U)
/*! MATCH1 - Match 1 Value
 */
#define LPI2C_MDMR_MATCH1(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK)
/*! @} */

/*! @name MCCR0 - Master Clock Configuration 0 */
/*! @{ */

#define LPI2C_MCCR0_CLKLO_MASK                   (0x3FU)
#define LPI2C_MCCR0_CLKLO_SHIFT                  (0U)
/*! CLKLO - Clock Low Period
 */
#define LPI2C_MCCR0_CLKLO(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK)

#define LPI2C_MCCR0_CLKHI_MASK                   (0x3F00U)
#define LPI2C_MCCR0_CLKHI_SHIFT                  (8U)
/*! CLKHI - Clock High Period
 */
#define LPI2C_MCCR0_CLKHI(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK)

#define LPI2C_MCCR0_SETHOLD_MASK                 (0x3F0000U)
#define LPI2C_MCCR0_SETHOLD_SHIFT                (16U)
/*! SETHOLD - Setup Hold Delay
 */
#define LPI2C_MCCR0_SETHOLD(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK)

#define LPI2C_MCCR0_DATAVD_MASK                  (0x3F000000U)
#define LPI2C_MCCR0_DATAVD_SHIFT                 (24U)
/*! DATAVD - Data Valid Delay
 */
#define LPI2C_MCCR0_DATAVD(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK)
/*! @} */

/*! @name MCCR1 - Master Clock Configuration 1 */
/*! @{ */

#define LPI2C_MCCR1_CLKLO_MASK                   (0x3FU)
#define LPI2C_MCCR1_CLKLO_SHIFT                  (0U)
/*! CLKLO - Clock Low Period
 */
#define LPI2C_MCCR1_CLKLO(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK)

#define LPI2C_MCCR1_CLKHI_MASK                   (0x3F00U)
#define LPI2C_MCCR1_CLKHI_SHIFT                  (8U)
/*! CLKHI - Clock High Period
 */
#define LPI2C_MCCR1_CLKHI(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK)

#define LPI2C_MCCR1_SETHOLD_MASK                 (0x3F0000U)
#define LPI2C_MCCR1_SETHOLD_SHIFT                (16U)
/*! SETHOLD - Setup Hold Delay
 */
#define LPI2C_MCCR1_SETHOLD(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK)

#define LPI2C_MCCR1_DATAVD_MASK                  (0x3F000000U)
#define LPI2C_MCCR1_DATAVD_SHIFT                 (24U)
/*! DATAVD - Data Valid Delay
 */
#define LPI2C_MCCR1_DATAVD(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK)
/*! @} */

/*! @name MFCR - Master FIFO Control */
/*! @{ */

#define LPI2C_MFCR_TXWATER_MASK                  (0x3U)
#define LPI2C_MFCR_TXWATER_SHIFT                 (0U)
/*! TXWATER - Transmit FIFO Watermark
 */
#define LPI2C_MFCR_TXWATER(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK)

#define LPI2C_MFCR_RXWATER_MASK                  (0x30000U)
#define LPI2C_MFCR_RXWATER_SHIFT                 (16U)
/*! RXWATER - Receive FIFO Watermark
 */
#define LPI2C_MFCR_RXWATER(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK)
/*! @} */

/*! @name MFSR - Master FIFO Status */
/*! @{ */

#define LPI2C_MFSR_TXCOUNT_MASK                  (0x7U)
#define LPI2C_MFSR_TXCOUNT_SHIFT                 (0U)
/*! TXCOUNT - Transmit FIFO Count
 */
#define LPI2C_MFSR_TXCOUNT(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK)

#define LPI2C_MFSR_RXCOUNT_MASK                  (0x70000U)
#define LPI2C_MFSR_RXCOUNT_SHIFT                 (16U)
/*! RXCOUNT - Receive FIFO Count
 */
#define LPI2C_MFSR_RXCOUNT(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK)
/*! @} */

/*! @name MTDR - Master Transmit Data */
/*! @{ */

#define LPI2C_MTDR_DATA_MASK                     (0xFFU)
#define LPI2C_MTDR_DATA_SHIFT                    (0U)
/*! DATA - Transmit Data
 */
#define LPI2C_MTDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK)

#define LPI2C_MTDR_CMD_MASK                      (0x700U)
#define LPI2C_MTDR_CMD_SHIFT                     (8U)
/*! CMD - Command Data
 *  0b000..Transmit DATA[7:0]
 *  0b001..Receive (DATA[7:0] + 1) bytes
 *  0b010..Generate STOP condition
 *  0b011..Receive and discard (DATA[7:0] + 1) bytes
 *  0b100..Generate (repeated) START and transmit address in DATA[7:0]
 *  0b101..Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned.
 *  0b110..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode
 *  0b111..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a NACK to be returned.
 */
#define LPI2C_MTDR_CMD(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK)
/*! @} */

/*! @name MRDR - Master Receive Data */
/*! @{ */

#define LPI2C_MRDR_DATA_MASK                     (0xFFU)
#define LPI2C_MRDR_DATA_SHIFT                    (0U)
/*! DATA - Receive Data
 */
#define LPI2C_MRDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK)

#define LPI2C_MRDR_RXEMPTY_MASK                  (0x4000U)
#define LPI2C_MRDR_RXEMPTY_SHIFT                 (14U)
/*! RXEMPTY - Receive Empty
 *  0b0..Receive FIFO is not empty
 *  0b1..Receive FIFO is empty
 */
#define LPI2C_MRDR_RXEMPTY(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK)
/*! @} */

/*! @name MRDROR - Master Receive Data Read Only */
/*! @{ */

#define LPI2C_MRDROR_DATA_MASK                   (0xFFU)
#define LPI2C_MRDROR_DATA_SHIFT                  (0U)
/*! DATA - Receive Data
 */
#define LPI2C_MRDROR_DATA(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDROR_DATA_SHIFT)) & LPI2C_MRDROR_DATA_MASK)

#define LPI2C_MRDROR_RXEMPTY_MASK                (0x4000U)
#define LPI2C_MRDROR_RXEMPTY_SHIFT               (14U)
/*! RXEMPTY - RX Empty
 *  0b0..Receive FIFO is not empty
 *  0b1..Receive FIFO is empty
 */
#define LPI2C_MRDROR_RXEMPTY(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDROR_RXEMPTY_SHIFT)) & LPI2C_MRDROR_RXEMPTY_MASK)
/*! @} */

/*! @name SCR - Slave Control */
/*! @{ */

#define LPI2C_SCR_SEN_MASK                       (0x1U)
#define LPI2C_SCR_SEN_SHIFT                      (0U)
/*! SEN - Slave Enable
 *  0b0..I2C Slave mode is disabled
 *  0b1..I2C Slave mode is enabled
 */
#define LPI2C_SCR_SEN(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK)

#define LPI2C_SCR_RST_MASK                       (0x2U)
#define LPI2C_SCR_RST_SHIFT                      (1U)
/*! RST - Software Reset
 *  0b0..Slave mode logic is not reset
 *  0b1..Slave mode logic is reset
 */
#define LPI2C_SCR_RST(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK)

#define LPI2C_SCR_FILTEN_MASK                    (0x10U)
#define LPI2C_SCR_FILTEN_SHIFT                   (4U)
/*! FILTEN - Filter Enable
 *  0b0..Disable digital filter and output delay counter for slave mode
 *  0b1..Enable digital filter and output delay counter for slave mode
 */
#define LPI2C_SCR_FILTEN(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK)

#define LPI2C_SCR_FILTDZ_MASK                    (0x20U)
#define LPI2C_SCR_FILTDZ_SHIFT                   (5U)
/*! FILTDZ - Filter Doze Enable
 *  0b0..Filter remains enabled in Doze mode
 *  0b1..Filter is disabled in Doze mode
 */
#define LPI2C_SCR_FILTDZ(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK)

#define LPI2C_SCR_RTF_MASK                       (0x100U)
#define LPI2C_SCR_RTF_SHIFT                      (8U)
/*! RTF - Reset Transmit FIFO
 *  0b0..No effect
 *  0b1..Transmit Data Register is now empty
 */
#define LPI2C_SCR_RTF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK)

#define LPI2C_SCR_RRF_MASK                       (0x200U)
#define LPI2C_SCR_RRF_SHIFT                      (9U)
/*! RRF - Reset Receive FIFO
 *  0b0..No effect
 *  0b1..Receive Data Register is now empty
 */
#define LPI2C_SCR_RRF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK)
/*! @} */

/*! @name SSR - Slave Status */
/*! @{ */

#define LPI2C_SSR_TDF_MASK                       (0x1U)
#define LPI2C_SSR_TDF_SHIFT                      (0U)
/*! TDF - Transmit Data Flag
 *  0b0..Transmit data not requested
 *  0b1..Transmit data is requested
 */
#define LPI2C_SSR_TDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK)

#define LPI2C_SSR_RDF_MASK                       (0x2U)
#define LPI2C_SSR_RDF_SHIFT                      (1U)
/*! RDF - Receive Data Flag
 *  0b0..Receive data is not ready
 *  0b1..Receive data is ready
 */
#define LPI2C_SSR_RDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK)

#define LPI2C_SSR_AVF_MASK                       (0x4U)
#define LPI2C_SSR_AVF_SHIFT                      (2U)
/*! AVF - Address Valid Flag
 *  0b0..Address Status Register is not valid
 *  0b1..Address Status Register is valid
 */
#define LPI2C_SSR_AVF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK)

#define LPI2C_SSR_TAF_MASK                       (0x8U)
#define LPI2C_SSR_TAF_SHIFT                      (3U)
/*! TAF - Transmit ACK Flag
 *  0b0..Transmit ACK/NACK is not required
 *  0b1..Transmit ACK/NACK is required
 */
#define LPI2C_SSR_TAF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK)

#define LPI2C_SSR_RSF_MASK                       (0x100U)
#define LPI2C_SSR_RSF_SHIFT                      (8U)
/*! RSF - Repeated Start Flag
 *  0b0..Slave has not detected a Repeated START condition
 *  0b1..Slave has detected a Repeated START condition
 */
#define LPI2C_SSR_RSF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK)

#define LPI2C_SSR_SDF_MASK                       (0x200U)
#define LPI2C_SSR_SDF_SHIFT                      (9U)
/*! SDF - STOP Detect Flag
 *  0b0..Slave has not detected a STOP condition
 *  0b1..Slave has detected a STOP condition
 */
#define LPI2C_SSR_SDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK)

#define LPI2C_SSR_BEF_MASK                       (0x400U)
#define LPI2C_SSR_BEF_SHIFT                      (10U)
/*! BEF - Bit Error Flag
 *  0b0..Slave has not detected a bit error
 *  0b1..Slave has detected a bit error
 */
#define LPI2C_SSR_BEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK)

#define LPI2C_SSR_FEF_MASK                       (0x800U)
#define LPI2C_SSR_FEF_SHIFT                      (11U)
/*! FEF - FIFO Error Flag
 *  0b0..FIFO underflow or overflow was not detected
 *  0b1..FIFO underflow or overflow was detected
 */
#define LPI2C_SSR_FEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK)

#define LPI2C_SSR_AM0F_MASK                      (0x1000U)
#define LPI2C_SSR_AM0F_SHIFT                     (12U)
/*! AM0F - Address Match 0 Flag
 *  0b0..Have not received an ADDR0 matching address
 *  0b1..Have received an ADDR0 matching address
 */
#define LPI2C_SSR_AM0F(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK)

#define LPI2C_SSR_AM1F_MASK                      (0x2000U)
#define LPI2C_SSR_AM1F_SHIFT                     (13U)
/*! AM1F - Address Match 1 Flag
 *  0b0..Have not received an ADDR1 or ADDR0/ADDR1 range matching address
 *  0b1..Have received an ADDR1 or ADDR0/ADDR1 range matching address
 */
#define LPI2C_SSR_AM1F(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK)

#define LPI2C_SSR_GCF_MASK                       (0x4000U)
#define LPI2C_SSR_GCF_SHIFT                      (14U)
/*! GCF - General Call Flag
 *  0b0..Slave has not detected the General Call Address or the General Call Address is disabled
 *  0b1..Slave has detected the General Call Address
 */
#define LPI2C_SSR_GCF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK)

#define LPI2C_SSR_SARF_MASK                      (0x8000U)
#define LPI2C_SSR_SARF_SHIFT                     (15U)
/*! SARF - SMBus Alert Response Flag
 *  0b0..SMBus Alert Response is disabled or not detected
 *  0b1..SMBus Alert Response is enabled and detected
 */
#define LPI2C_SSR_SARF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK)

#define LPI2C_SSR_SBF_MASK                       (0x1000000U)
#define LPI2C_SSR_SBF_SHIFT                      (24U)
/*! SBF - Slave Busy Flag
 *  0b0..I2C Slave is idle
 *  0b1..I2C Slave is busy
 */
#define LPI2C_SSR_SBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK)

#define LPI2C_SSR_BBF_MASK                       (0x2000000U)
#define LPI2C_SSR_BBF_SHIFT                      (25U)
/*! BBF - Bus Busy Flag
 *  0b0..I2C Bus is idle
 *  0b1..I2C Bus is busy
 */
#define LPI2C_SSR_BBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK)
/*! @} */

/*! @name SIER - Slave Interrupt Enable */
/*! @{ */

#define LPI2C_SIER_TDIE_MASK                     (0x1U)
#define LPI2C_SIER_TDIE_SHIFT                    (0U)
/*! TDIE - Transmit Data Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_SIER_TDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK)

#define LPI2C_SIER_RDIE_MASK                     (0x2U)
#define LPI2C_SIER_RDIE_SHIFT                    (1U)
/*! RDIE - Receive Data Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_SIER_RDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK)

#define LPI2C_SIER_AVIE_MASK                     (0x4U)
#define LPI2C_SIER_AVIE_SHIFT                    (2U)
/*! AVIE - Address Valid Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_SIER_AVIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK)

#define LPI2C_SIER_TAIE_MASK                     (0x8U)
#define LPI2C_SIER_TAIE_SHIFT                    (3U)
/*! TAIE - Transmit ACK Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_SIER_TAIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK)

#define LPI2C_SIER_RSIE_MASK                     (0x100U)
#define LPI2C_SIER_RSIE_SHIFT                    (8U)
/*! RSIE - Repeated Start Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_SIER_RSIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK)

#define LPI2C_SIER_SDIE_MASK                     (0x200U)
#define LPI2C_SIER_SDIE_SHIFT                    (9U)
/*! SDIE - STOP Detect Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_SIER_SDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK)

#define LPI2C_SIER_BEIE_MASK                     (0x400U)
#define LPI2C_SIER_BEIE_SHIFT                    (10U)
/*! BEIE - Bit Error Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_SIER_BEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK)

#define LPI2C_SIER_FEIE_MASK                     (0x800U)
#define LPI2C_SIER_FEIE_SHIFT                    (11U)
/*! FEIE - FIFO Error Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_SIER_FEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK)

#define LPI2C_SIER_AM0IE_MASK                    (0x1000U)
#define LPI2C_SIER_AM0IE_SHIFT                   (12U)
/*! AM0IE - Address Match 0 Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_SIER_AM0IE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK)

#define LPI2C_SIER_AM1IE_MASK                    (0x2000U)
#define LPI2C_SIER_AM1IE_SHIFT                   (13U)
/*! AM1IE - Address Match 1 Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_SIER_AM1IE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1IE_SHIFT)) & LPI2C_SIER_AM1IE_MASK)

#define LPI2C_SIER_GCIE_MASK                     (0x4000U)
#define LPI2C_SIER_GCIE_SHIFT                    (14U)
/*! GCIE - General Call Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_SIER_GCIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK)

#define LPI2C_SIER_SARIE_MASK                    (0x8000U)
#define LPI2C_SIER_SARIE_SHIFT                   (15U)
/*! SARIE - SMBus Alert Response Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPI2C_SIER_SARIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK)
/*! @} */

/*! @name SDER - Slave DMA Enable */
/*! @{ */

#define LPI2C_SDER_TDDE_MASK                     (0x1U)
#define LPI2C_SDER_TDDE_SHIFT                    (0U)
/*! TDDE - Transmit Data DMA Enable
 *  0b0..DMA request is disabled
 *  0b1..DMA request is enabled
 */
#define LPI2C_SDER_TDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK)

#define LPI2C_SDER_RDDE_MASK                     (0x2U)
#define LPI2C_SDER_RDDE_SHIFT                    (1U)
/*! RDDE - Receive Data DMA Enable
 *  0b0..DMA request is disabled
 *  0b1..DMA request is enabled
 */
#define LPI2C_SDER_RDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK)

#define LPI2C_SDER_AVDE_MASK                     (0x4U)
#define LPI2C_SDER_AVDE_SHIFT                    (2U)
/*! AVDE - Address Valid DMA Enable
 *  0b0..DMA request is disabled
 *  0b1..DMA request is enabled
 */
#define LPI2C_SDER_AVDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK)

#define LPI2C_SDER_RSDE_MASK                     (0x100U)
#define LPI2C_SDER_RSDE_SHIFT                    (8U)
/*! RSDE - Repeated Start DMA Enable
 *  0b0..DMA request is disabled
 *  0b1..DMA request is enabled
 */
#define LPI2C_SDER_RSDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RSDE_SHIFT)) & LPI2C_SDER_RSDE_MASK)

#define LPI2C_SDER_SDDE_MASK                     (0x200U)
#define LPI2C_SDER_SDDE_SHIFT                    (9U)
/*! SDDE - Stop Detect DMA Enable
 *  0b0..DMA request is disabled
 *  0b1..DMA request is enabled
 */
#define LPI2C_SDER_SDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_SDDE_SHIFT)) & LPI2C_SDER_SDDE_MASK)
/*! @} */

/*! @name SCFGR0 - Slave Configuration 0 */
/*! @{ */

#define LPI2C_SCFGR0_RDREQ_MASK                  (0x1U)
#define LPI2C_SCFGR0_RDREQ_SHIFT                 (0U)
/*! RDREQ - Read Request
 *  0b0..Read Request is disabled
 *  0b1..Read Request is enabled
 */
#define LPI2C_SCFGR0_RDREQ(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR0_RDREQ_SHIFT)) & LPI2C_SCFGR0_RDREQ_MASK)

#define LPI2C_SCFGR0_RDACK_MASK                  (0x2U)
#define LPI2C_SCFGR0_RDACK_SHIFT                 (1U)
/*! RDACK - Read Acknowledge
 *  0b0..Read Request not acknowledged
 *  0b1..Read Request acknowledged
 */
#define LPI2C_SCFGR0_RDACK(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR0_RDACK_SHIFT)) & LPI2C_SCFGR0_RDACK_MASK)
/*! @} */

/*! @name SCFGR1 - Slave Configuration 1 */
/*! @{ */

#define LPI2C_SCFGR1_ADRSTALL_MASK               (0x1U)
#define LPI2C_SCFGR1_ADRSTALL_SHIFT              (0U)
/*! ADRSTALL - Address SCL Stall
 *  0b0..Clock stretching is disabled
 *  0b1..Clock stretching is enabled
 */
#define LPI2C_SCFGR1_ADRSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK)

#define LPI2C_SCFGR1_RXSTALL_MASK                (0x2U)
#define LPI2C_SCFGR1_RXSTALL_SHIFT               (1U)
/*! RXSTALL - RX SCL Stall
 *  0b0..Clock stretching is disabled
 *  0b1..Clock stretching is enabled
 */
#define LPI2C_SCFGR1_RXSTALL(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK)

#define LPI2C_SCFGR1_TXDSTALL_MASK               (0x4U)
#define LPI2C_SCFGR1_TXDSTALL_SHIFT              (2U)
/*! TXDSTALL - TX Data SCL Stall
 *  0b0..Clock stretching is disabled
 *  0b1..Clock stretching is enabled
 */
#define LPI2C_SCFGR1_TXDSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK)

#define LPI2C_SCFGR1_ACKSTALL_MASK               (0x8U)
#define LPI2C_SCFGR1_ACKSTALL_SHIFT              (3U)
/*! ACKSTALL - ACK SCL Stall
 *  0b0..Clock stretching is disabled
 *  0b1..Clock stretching is enabled
 */
#define LPI2C_SCFGR1_ACKSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK)

#define LPI2C_SCFGR1_RXNACK_MASK                 (0x10U)
#define LPI2C_SCFGR1_RXNACK_SHIFT                (4U)
/*! RXNACK - Receive NACK
 *  0b0..ACK/NACK always set by TXNACK
 *  0b1..NACK always generated on address overrun or receive data overrun, otherwise ACK/NACK set by TXNACK.
 */
#define LPI2C_SCFGR1_RXNACK(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXNACK_SHIFT)) & LPI2C_SCFGR1_RXNACK_MASK)

#define LPI2C_SCFGR1_GCEN_MASK                   (0x100U)
#define LPI2C_SCFGR1_GCEN_SHIFT                  (8U)
/*! GCEN - General Call Enable
 *  0b0..General Call address is disabled
 *  0b1..General Call address is enabled
 */
#define LPI2C_SCFGR1_GCEN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK)

#define LPI2C_SCFGR1_SAEN_MASK                   (0x200U)
#define LPI2C_SCFGR1_SAEN_SHIFT                  (9U)
/*! SAEN - SMBus Alert Enable
 *  0b0..Disables match on SMBus Alert
 *  0b1..Enables match on SMBus Alert
 */
#define LPI2C_SCFGR1_SAEN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK)

#define LPI2C_SCFGR1_TXCFG_MASK                  (0x400U)
#define LPI2C_SCFGR1_TXCFG_SHIFT                 (10U)
/*! TXCFG - Transmit Flag Configuration
 *  0b0..Transmit Data Flag only asserts during a slave-transmit transfer when the Transmit Data register is empty
 *  0b1..Transmit Data Flag asserts whenever the Transmit Data register is empty
 */
#define LPI2C_SCFGR1_TXCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK)

#define LPI2C_SCFGR1_RXCFG_MASK                  (0x800U)
#define LPI2C_SCFGR1_RXCFG_SHIFT                 (11U)
/*! RXCFG - Receive Data Configuration
 *  0b0..Reading the Receive Data register returns received data and clears the Receive Data flag.
 *  0b1..Reading the Receive Data register when the Address Valid flag (SSR[AVF]) is set, returns the Address
 *       Status register and clear the Address Valid flag. Reading the Receive Data register when the Address Valid
 *       flag is clear, returns received data and clears the Receive Data flag (MSR[RDF]).
 */
#define LPI2C_SCFGR1_RXCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK)

#define LPI2C_SCFGR1_IGNACK_MASK                 (0x1000U)
#define LPI2C_SCFGR1_IGNACK_SHIFT                (12U)
/*! IGNACK - Ignore NACK
 *  0b0..Slave ends transfer when NACK is detected
 *  0b1..Slave does not end transfer when NACK detected
 */
#define LPI2C_SCFGR1_IGNACK(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK)

#define LPI2C_SCFGR1_HSMEN_MASK                  (0x2000U)
#define LPI2C_SCFGR1_HSMEN_SHIFT                 (13U)
/*! HSMEN - High Speed Mode Enable
 *  0b0..Disables detection of HS-mode master code
 *  0b1..Enables detection of HS-mode master code
 */
#define LPI2C_SCFGR1_HSMEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK)

#define LPI2C_SCFGR1_ADDRCFG_MASK                (0x70000U)
#define LPI2C_SCFGR1_ADDRCFG_SHIFT               (16U)
/*! ADDRCFG - Address Configuration
 *  0b000..Address match 0 (7-bit)
 *  0b001..Address match 0 (10-bit)
 *  0b010..Address match 0 (7-bit) or Address match 1 (7-bit)
 *  0b011..Address match 0 (10-bit) or Address match 1 (10-bit)
 *  0b100..Address match 0 (7-bit) or Address match 1 (10-bit)
 *  0b101..Address match 0 (10-bit) or Address match 1 (7-bit)
 *  0b110..From Address match 0 (7-bit) to Address match 1 (7-bit)
 *  0b111..From Address match 0 (10-bit) to Address match 1 (10-bit)
 */
#define LPI2C_SCFGR1_ADDRCFG(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK)

#define LPI2C_SCFGR1_RXALL_MASK                  (0x1000000U)
#define LPI2C_SCFGR1_RXALL_SHIFT                 (24U)
/*! RXALL - Receive All
 *  0b0..Receive all disabled
 *  0b1..Receive all enabled
 */
#define LPI2C_SCFGR1_RXALL(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXALL_SHIFT)) & LPI2C_SCFGR1_RXALL_MASK)

#define LPI2C_SCFGR1_RSCFG_MASK                  (0x2000000U)
#define LPI2C_SCFGR1_RSCFG_SHIFT                 (25U)
/*! RSCFG - Repeated Start Configuration
 *  0b0..Any Repeated START condition following an address match
 *  0b1..Any Repeated START condition
 */
#define LPI2C_SCFGR1_RSCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RSCFG_SHIFT)) & LPI2C_SCFGR1_RSCFG_MASK)

#define LPI2C_SCFGR1_SDCFG_MASK                  (0x4000000U)
#define LPI2C_SCFGR1_SDCFG_SHIFT                 (26U)
/*! SDCFG - Stop Detect Configuration
 *  0b0..Any STOP condition following an address match
 *  0b1..Any STOP condition
 */
#define LPI2C_SCFGR1_SDCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SDCFG_SHIFT)) & LPI2C_SCFGR1_SDCFG_MASK)
/*! @} */

/*! @name SCFGR2 - Slave Configuration 2 */
/*! @{ */

#define LPI2C_SCFGR2_CLKHOLD_MASK                (0xFU)
#define LPI2C_SCFGR2_CLKHOLD_SHIFT               (0U)
/*! CLKHOLD - Clock Hold Time
 */
#define LPI2C_SCFGR2_CLKHOLD(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK)

#define LPI2C_SCFGR2_DATAVD_MASK                 (0x3F00U)
#define LPI2C_SCFGR2_DATAVD_SHIFT                (8U)
/*! DATAVD - Data Valid Delay
 */
#define LPI2C_SCFGR2_DATAVD(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK)

#define LPI2C_SCFGR2_FILTSCL_MASK                (0xF0000U)
#define LPI2C_SCFGR2_FILTSCL_SHIFT               (16U)
/*! FILTSCL - Glitch Filter SCL
 */
#define LPI2C_SCFGR2_FILTSCL(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK)

#define LPI2C_SCFGR2_FILTSDA_MASK                (0xF000000U)
#define LPI2C_SCFGR2_FILTSDA_SHIFT               (24U)
/*! FILTSDA - Glitch Filter SDA
 */
#define LPI2C_SCFGR2_FILTSDA(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK)
/*! @} */

/*! @name SAMR - Slave Address Match */
/*! @{ */

#define LPI2C_SAMR_ADDR0_MASK                    (0x7FEU)
#define LPI2C_SAMR_ADDR0_SHIFT                   (1U)
/*! ADDR0 - Address 0 Value
 */
#define LPI2C_SAMR_ADDR0(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK)

#define LPI2C_SAMR_ADDR1_MASK                    (0x7FE0000U)
#define LPI2C_SAMR_ADDR1_SHIFT                   (17U)
/*! ADDR1 - Address 1 Value
 */
#define LPI2C_SAMR_ADDR1(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK)
/*! @} */

/*! @name SASR - Slave Address Status */
/*! @{ */

#define LPI2C_SASR_RADDR_MASK                    (0x7FFU)
#define LPI2C_SASR_RADDR_SHIFT                   (0U)
/*! RADDR - Received Address
 */
#define LPI2C_SASR_RADDR(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK)

#define LPI2C_SASR_ANV_MASK                      (0x4000U)
#define LPI2C_SASR_ANV_SHIFT                     (14U)
/*! ANV - Address Not Valid
 *  0b0..Received Address (RADDR) is valid
 *  0b1..Received Address (RADDR) is not valid
 */
#define LPI2C_SASR_ANV(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK)
/*! @} */

/*! @name STAR - Slave Transmit ACK */
/*! @{ */

#define LPI2C_STAR_TXNACK_MASK                   (0x1U)
#define LPI2C_STAR_TXNACK_SHIFT                  (0U)
/*! TXNACK - Transmit NACK
 *  0b0..Write a Transmit ACK for each received word
 *  0b1..Write a Transmit NACK for each received word
 */
#define LPI2C_STAR_TXNACK(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK)
/*! @} */

/*! @name STDR - Slave Transmit Data */
/*! @{ */

#define LPI2C_STDR_DATA_MASK                     (0xFFU)
#define LPI2C_STDR_DATA_SHIFT                    (0U)
/*! DATA - Transmit Data
 */
#define LPI2C_STDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK)
/*! @} */

/*! @name SRDR - Slave Receive Data */
/*! @{ */

#define LPI2C_SRDR_DATA_MASK                     (0xFFU)
#define LPI2C_SRDR_DATA_SHIFT                    (0U)
/*! DATA - Receive Data
 */
#define LPI2C_SRDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK)

#define LPI2C_SRDR_RADDR_MASK                    (0x700U)
#define LPI2C_SRDR_RADDR_SHIFT                   (8U)
/*! RADDR - Received Address
 */
#define LPI2C_SRDR_RADDR(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RADDR_SHIFT)) & LPI2C_SRDR_RADDR_MASK)

#define LPI2C_SRDR_RXEMPTY_MASK                  (0x4000U)
#define LPI2C_SRDR_RXEMPTY_SHIFT                 (14U)
/*! RXEMPTY - Receive Empty
 *  0b0..The Receive Data Register is not empty
 *  0b1..The Receive Data Register is empty
 */
#define LPI2C_SRDR_RXEMPTY(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK)

#define LPI2C_SRDR_SOF_MASK                      (0x8000U)
#define LPI2C_SRDR_SOF_SHIFT                     (15U)
/*! SOF - Start Of Frame
 *  0b0..Indicates this is not the first data word since a (repeated) START or STOP condition
 *  0b1..Indicates this is the first data word since a (repeated) START or STOP condition
 */
#define LPI2C_SRDR_SOF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK)
/*! @} */

/*! @name SRDROR - Slave Receive Data Read Only */
/*! @{ */

#define LPI2C_SRDROR_DATA_MASK                   (0xFFU)
#define LPI2C_SRDROR_DATA_SHIFT                  (0U)
/*! DATA - Receive Data
 */
#define LPI2C_SRDROR_DATA(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_DATA_SHIFT)) & LPI2C_SRDROR_DATA_MASK)

#define LPI2C_SRDROR_RADDR_MASK                  (0x700U)
#define LPI2C_SRDROR_RADDR_SHIFT                 (8U)
/*! RADDR - Received Address
 */
#define LPI2C_SRDROR_RADDR(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_RADDR_SHIFT)) & LPI2C_SRDROR_RADDR_MASK)

#define LPI2C_SRDROR_RXEMPTY_MASK                (0x4000U)
#define LPI2C_SRDROR_RXEMPTY_SHIFT               (14U)
/*! RXEMPTY - RX Empty
 *  0b0..The Receive Data Register is not empty
 *  0b1..The Receive Data Register is empty
 */
#define LPI2C_SRDROR_RXEMPTY(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_RXEMPTY_SHIFT)) & LPI2C_SRDROR_RXEMPTY_MASK)

#define LPI2C_SRDROR_SOF_MASK                    (0x8000U)
#define LPI2C_SRDROR_SOF_SHIFT                   (15U)
/*! SOF - Start Of Frame
 *  0b0..Indicates this is not the first data word since a (repeated) START or STOP condition
 *  0b1..Indicates this is the first data word since a (repeated) START or STOP condition
 */
#define LPI2C_SRDROR_SOF(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_SOF_SHIFT)) & LPI2C_SRDROR_SOF_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LPI2C_Register_Masks */


/* LPI2C - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral LPI2C0 base address */
  #define LPI2C0_BASE                              (0x50033000u)
  /** Peripheral LPI2C0 base address */
  #define LPI2C0_BASE_NS                           (0x40033000u)
  /** Peripheral LPI2C0 base pointer */
  #define LPI2C0                                   ((LPI2C_Type *)LPI2C0_BASE)
  /** Peripheral LPI2C0 base pointer */
  #define LPI2C0_NS                                ((LPI2C_Type *)LPI2C0_BASE_NS)
  /** Peripheral LPI2C1 base address */
  #define LPI2C1_BASE                              (0x50034000u)
  /** Peripheral LPI2C1 base address */
  #define LPI2C1_BASE_NS                           (0x40034000u)
  /** Peripheral LPI2C1 base pointer */
  #define LPI2C1                                   ((LPI2C_Type *)LPI2C1_BASE)
  /** Peripheral LPI2C1 base pointer */
  #define LPI2C1_NS                                ((LPI2C_Type *)LPI2C1_BASE_NS)
  /** Array initializer of LPI2C peripheral base addresses */
  #define LPI2C_BASE_ADDRS                         { LPI2C0_BASE, LPI2C1_BASE }
  /** Array initializer of LPI2C peripheral base pointers */
  #define LPI2C_BASE_PTRS                          { LPI2C0, LPI2C1 }
  /** Array initializer of LPI2C peripheral base addresses */
  #define LPI2C_BASE_ADDRS_NS                      { LPI2C0_BASE_NS, LPI2C1_BASE_NS }
  /** Array initializer of LPI2C peripheral base pointers */
  #define LPI2C_BASE_PTRS_NS                       { LPI2C0_NS, LPI2C1_NS }
#else
  /** Peripheral LPI2C0 base address */
  #define LPI2C0_BASE                              (0x40033000u)
  /** Peripheral LPI2C0 base pointer */
  #define LPI2C0                                   ((LPI2C_Type *)LPI2C0_BASE)
  /** Peripheral LPI2C1 base address */
  #define LPI2C1_BASE                              (0x40034000u)
  /** Peripheral LPI2C1 base pointer */
  #define LPI2C1                                   ((LPI2C_Type *)LPI2C1_BASE)
  /** Array initializer of LPI2C peripheral base addresses */
  #define LPI2C_BASE_ADDRS                         { LPI2C0_BASE, LPI2C1_BASE }
  /** Array initializer of LPI2C peripheral base pointers */
  #define LPI2C_BASE_PTRS                          { LPI2C0, LPI2C1 }
#endif
/** Interrupt vectors for the LPI2C peripheral type */
#define LPI2C_IRQS                               { LPI2C0_IRQn, LPI2C1_IRQn }

/*!
 * @}
 */ /* end of group LPI2C_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LPIT Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LPIT_Peripheral_Access_Layer LPIT Peripheral Access Layer
 * @{
 */

/** LPIT - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
  __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
  __IO uint32_t MCR;                               /**< Module Control, offset: 0x8 */
  __IO uint32_t MSR;                               /**< Module Status, offset: 0xC */
  __IO uint32_t MIER;                              /**< Module Interrupt Enable, offset: 0x10 */
  __IO uint32_t SETTEN;                            /**< Set Timer Enable, offset: 0x14 */
  __O  uint32_t CLRTEN;                            /**< Clear Timer Enable, offset: 0x18 */
       uint8_t RESERVED_0[4];
  struct {                                         /* offset: 0x20, array step: 0x10 */
    __IO uint32_t TVAL;                              /**< Timer Value, array offset: 0x20, array step: 0x10 */
    __I  uint32_t CVAL;                              /**< Current Timer Value, array offset: 0x24, array step: 0x10 */
    __IO uint32_t TCTRL;                             /**< Timer Control, array offset: 0x28, array step: 0x10 */
         uint8_t RESERVED_0[4];
  } CHANNEL[4];
} LPIT_Type;

/* ----------------------------------------------------------------------------
   -- LPIT Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LPIT_Register_Masks LPIT Register Masks
 * @{
 */

/*! @name VERID - Version ID */
/*! @{ */

#define LPIT_VERID_FEATURE_MASK                  (0xFFFFU)
#define LPIT_VERID_FEATURE_SHIFT                 (0U)
/*! FEATURE - Feature Number
 */
#define LPIT_VERID_FEATURE(x)                    (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_FEATURE_SHIFT)) & LPIT_VERID_FEATURE_MASK)

#define LPIT_VERID_MINOR_MASK                    (0xFF0000U)
#define LPIT_VERID_MINOR_SHIFT                   (16U)
/*! MINOR - Minor Version Number
 */
#define LPIT_VERID_MINOR(x)                      (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_MINOR_SHIFT)) & LPIT_VERID_MINOR_MASK)

#define LPIT_VERID_MAJOR_MASK                    (0xFF000000U)
#define LPIT_VERID_MAJOR_SHIFT                   (24U)
/*! MAJOR - Major Version Number
 */
#define LPIT_VERID_MAJOR(x)                      (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_MAJOR_SHIFT)) & LPIT_VERID_MAJOR_MASK)
/*! @} */

/*! @name PARAM - Parameter */
/*! @{ */

#define LPIT_PARAM_CHANNEL_MASK                  (0xFFU)
#define LPIT_PARAM_CHANNEL_SHIFT                 (0U)
/*! CHANNEL - Number of Timer Channels
 */
#define LPIT_PARAM_CHANNEL(x)                    (((uint32_t)(((uint32_t)(x)) << LPIT_PARAM_CHANNEL_SHIFT)) & LPIT_PARAM_CHANNEL_MASK)

#define LPIT_PARAM_EXT_TRIG_MASK                 (0xFF00U)
#define LPIT_PARAM_EXT_TRIG_SHIFT                (8U)
/*! EXT_TRIG - Number of External Trigger Inputs
 */
#define LPIT_PARAM_EXT_TRIG(x)                   (((uint32_t)(((uint32_t)(x)) << LPIT_PARAM_EXT_TRIG_SHIFT)) & LPIT_PARAM_EXT_TRIG_MASK)
/*! @} */

/*! @name MCR - Module Control */
/*! @{ */

#define LPIT_MCR_M_CEN_MASK                      (0x1U)
#define LPIT_MCR_M_CEN_SHIFT                     (0U)
/*! M_CEN - Module Clock Enable
 *  0b0..Disable peripheral clock to timers
 *  0b1..Enable peripheral clock to timers
 */
#define LPIT_MCR_M_CEN(x)                        (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_M_CEN_SHIFT)) & LPIT_MCR_M_CEN_MASK)

#define LPIT_MCR_SW_RST_MASK                     (0x2U)
#define LPIT_MCR_SW_RST_SHIFT                    (1U)
/*! SW_RST - Software Reset
 *  0b0..Timer channels and registers are not reset
 *  0b1..Reset timer channels and registers
 */
#define LPIT_MCR_SW_RST(x)                       (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_SW_RST_SHIFT)) & LPIT_MCR_SW_RST_MASK)

#define LPIT_MCR_DOZE_EN_MASK                    (0x4U)
#define LPIT_MCR_DOZE_EN_SHIFT                   (2U)
/*! DOZE_EN - DOZE Mode Enable
 *  0b0..Stop timer channels in DOZE mode
 *  0b1..Allow timer channels to continue to run in DOZE mode
 */
#define LPIT_MCR_DOZE_EN(x)                      (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_DOZE_EN_SHIFT)) & LPIT_MCR_DOZE_EN_MASK)

#define LPIT_MCR_DBG_EN_MASK                     (0x8U)
#define LPIT_MCR_DBG_EN_SHIFT                    (3U)
/*! DBG_EN - Debug Mode Enable
 *  0b0..Stop timer channels in Debug mode
 *  0b1..Allow timer channels to continue to run in Debug mode
 */
#define LPIT_MCR_DBG_EN(x)                       (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_DBG_EN_SHIFT)) & LPIT_MCR_DBG_EN_MASK)
/*! @} */

/*! @name MSR - Module Status */
/*! @{ */

#define LPIT_MSR_TIF0_MASK                       (0x1U)
#define LPIT_MSR_TIF0_SHIFT                      (0U)
/*! TIF0 - Channel 0 Timer Interrupt Flag
 *  0b0..Timer has not timed out
 *  0b1..Timeout has occurred (timer has timed out)
 */
#define LPIT_MSR_TIF0(x)                         (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF0_SHIFT)) & LPIT_MSR_TIF0_MASK)

#define LPIT_MSR_TIF1_MASK                       (0x2U)
#define LPIT_MSR_TIF1_SHIFT                      (1U)
/*! TIF1 - Channel 1 Timer Interrupt Flag
 *  0b0..Timer has not timed out
 *  0b1..Timeout has occurred (timer has timed out)
 */
#define LPIT_MSR_TIF1(x)                         (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF1_SHIFT)) & LPIT_MSR_TIF1_MASK)

#define LPIT_MSR_TIF2_MASK                       (0x4U)
#define LPIT_MSR_TIF2_SHIFT                      (2U)
/*! TIF2 - Channel 2 Timer Interrupt Flag
 *  0b0..Timer has not timed out
 *  0b1..Timeout has occurred (timer has timed out)
 */
#define LPIT_MSR_TIF2(x)                         (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF2_SHIFT)) & LPIT_MSR_TIF2_MASK)

#define LPIT_MSR_TIF3_MASK                       (0x8U)
#define LPIT_MSR_TIF3_SHIFT                      (3U)
/*! TIF3 - Channel 3 Timer Interrupt Flag
 *  0b0..Timer has not timed out
 *  0b1..Timeout has occurred (timer has timed out)
 */
#define LPIT_MSR_TIF3(x)                         (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF3_SHIFT)) & LPIT_MSR_TIF3_MASK)
/*! @} */

/*! @name MIER - Module Interrupt Enable */
/*! @{ */

#define LPIT_MIER_TIE0_MASK                      (0x1U)
#define LPIT_MIER_TIE0_SHIFT                     (0U)
/*! TIE0 - Channel 0 Timer Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPIT_MIER_TIE0(x)                        (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE0_SHIFT)) & LPIT_MIER_TIE0_MASK)

#define LPIT_MIER_TIE1_MASK                      (0x2U)
#define LPIT_MIER_TIE1_SHIFT                     (1U)
/*! TIE1 - Channel 1 Timer Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPIT_MIER_TIE1(x)                        (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE1_SHIFT)) & LPIT_MIER_TIE1_MASK)

#define LPIT_MIER_TIE2_MASK                      (0x4U)
#define LPIT_MIER_TIE2_SHIFT                     (2U)
/*! TIE2 - Channel 2 Timer Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPIT_MIER_TIE2(x)                        (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE2_SHIFT)) & LPIT_MIER_TIE2_MASK)

#define LPIT_MIER_TIE3_MASK                      (0x8U)
#define LPIT_MIER_TIE3_SHIFT                     (3U)
/*! TIE3 - Channel 3 Timer Interrupt Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPIT_MIER_TIE3(x)                        (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE3_SHIFT)) & LPIT_MIER_TIE3_MASK)
/*! @} */

/*! @name SETTEN - Set Timer Enable */
/*! @{ */

#define LPIT_SETTEN_SET_T_EN_0_MASK              (0x1U)
#define LPIT_SETTEN_SET_T_EN_0_SHIFT             (0U)
/*! SET_T_EN_0 - Set Timer 0 Enable
 *  0b0..No effect
 *  0b1..Enables Timer Channel 0
 */
#define LPIT_SETTEN_SET_T_EN_0(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_0_SHIFT)) & LPIT_SETTEN_SET_T_EN_0_MASK)

#define LPIT_SETTEN_SET_T_EN_1_MASK              (0x2U)
#define LPIT_SETTEN_SET_T_EN_1_SHIFT             (1U)
/*! SET_T_EN_1 - Set Timer 1 Enable
 *  0b0..No Effect
 *  0b1..Enables Timer Channel 1
 */
#define LPIT_SETTEN_SET_T_EN_1(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_1_SHIFT)) & LPIT_SETTEN_SET_T_EN_1_MASK)

#define LPIT_SETTEN_SET_T_EN_2_MASK              (0x4U)
#define LPIT_SETTEN_SET_T_EN_2_SHIFT             (2U)
/*! SET_T_EN_2 - Set Timer 2 Enable
 *  0b0..No Effect
 *  0b1..Enables Timer Channel 2
 */
#define LPIT_SETTEN_SET_T_EN_2(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_2_SHIFT)) & LPIT_SETTEN_SET_T_EN_2_MASK)

#define LPIT_SETTEN_SET_T_EN_3_MASK              (0x8U)
#define LPIT_SETTEN_SET_T_EN_3_SHIFT             (3U)
/*! SET_T_EN_3 - Set Timer 3 Enable
 *  0b0..No effect
 *  0b1..Enables Timer Channel 3
 */
#define LPIT_SETTEN_SET_T_EN_3(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_3_SHIFT)) & LPIT_SETTEN_SET_T_EN_3_MASK)
/*! @} */

/*! @name CLRTEN - Clear Timer Enable */
/*! @{ */

#define LPIT_CLRTEN_CLR_T_EN_0_MASK              (0x1U)
#define LPIT_CLRTEN_CLR_T_EN_0_SHIFT             (0U)
/*! CLR_T_EN_0 - Clear Timer 0 Enable
 *  0b0..No action
 *  0b1..Clear the Timer Enable bit (TCTRL0[T_EN]) for Timer Channel 0
 */
#define LPIT_CLRTEN_CLR_T_EN_0(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_0_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_0_MASK)

#define LPIT_CLRTEN_CLR_T_EN_1_MASK              (0x2U)
#define LPIT_CLRTEN_CLR_T_EN_1_SHIFT             (1U)
/*! CLR_T_EN_1 - Clear Timer 1 Enable
 *  0b0..No Action
 *  0b1..Clear the Timer Enable bit (TCTRL1[T_EN]) for Timer Channel 1
 */
#define LPIT_CLRTEN_CLR_T_EN_1(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_1_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_1_MASK)

#define LPIT_CLRTEN_CLR_T_EN_2_MASK              (0x4U)
#define LPIT_CLRTEN_CLR_T_EN_2_SHIFT             (2U)
/*! CLR_T_EN_2 - Clear Timer 2 Enable
 *  0b0..No Action
 *  0b1..Clear the Timer Enable bit (TCTRL2[T_EN]) for Timer Channel 2
 */
#define LPIT_CLRTEN_CLR_T_EN_2(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_2_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_2_MASK)

#define LPIT_CLRTEN_CLR_T_EN_3_MASK              (0x8U)
#define LPIT_CLRTEN_CLR_T_EN_3_SHIFT             (3U)
/*! CLR_T_EN_3 - Clear Timer 3 Enable
 *  0b0..No Action
 *  0b1..Clear the Timer Enable bit (TCTRL3[T_EN]) for Timer Channel 3
 */
#define LPIT_CLRTEN_CLR_T_EN_3(x)                (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_3_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_3_MASK)
/*! @} */

/*! @name TVAL - Timer Value */
/*! @{ */

#define LPIT_TVAL_TMR_VAL_MASK                   (0xFFFFFFFFU)
#define LPIT_TVAL_TMR_VAL_SHIFT                  (0U)
/*! TMR_VAL - Timer Value
 *  0b00000000000000000000000000000000, 0b00000000000000000000000000000001..Invalid load value in compare mode
 *  0b00000000000000000000000000000010-0b11111111111111111111111111111111..In compare mode: the value to be loaded; in capture mode, the value of the timer
 */
#define LPIT_TVAL_TMR_VAL(x)                     (((uint32_t)(((uint32_t)(x)) << LPIT_TVAL_TMR_VAL_SHIFT)) & LPIT_TVAL_TMR_VAL_MASK)
/*! @} */

/* The count of LPIT_TVAL */
#define LPIT_TVAL_COUNT                          (4U)

/*! @name CVAL - Current Timer Value */
/*! @{ */

#define LPIT_CVAL_TMR_CUR_VAL_MASK               (0xFFFFFFFFU)
#define LPIT_CVAL_TMR_CUR_VAL_SHIFT              (0U)
/*! TMR_CUR_VAL - Current Timer Value
 */
#define LPIT_CVAL_TMR_CUR_VAL(x)                 (((uint32_t)(((uint32_t)(x)) << LPIT_CVAL_TMR_CUR_VAL_SHIFT)) & LPIT_CVAL_TMR_CUR_VAL_MASK)
/*! @} */

/* The count of LPIT_CVAL */
#define LPIT_CVAL_COUNT                          (4U)

/*! @name TCTRL - Timer Control */
/*! @{ */

#define LPIT_TCTRL_T_EN_MASK                     (0x1U)
#define LPIT_TCTRL_T_EN_SHIFT                    (0U)
/*! T_EN - Timer Enable
 *  0b0..Timer Channel is disabled
 *  0b1..Timer Channel is enabled
 */
#define LPIT_TCTRL_T_EN(x)                       (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_T_EN_SHIFT)) & LPIT_TCTRL_T_EN_MASK)

#define LPIT_TCTRL_CHAIN_MASK                    (0x2U)
#define LPIT_TCTRL_CHAIN_SHIFT                   (1U)
/*! CHAIN - Chain Channel
 *  0b0..Channel Chaining is disabled. The channel timer runs independently.
 *  0b1..Channel Chaining is enabled. The timer decrements on the previous channel's timeout.
 */
#define LPIT_TCTRL_CHAIN(x)                      (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_CHAIN_SHIFT)) & LPIT_TCTRL_CHAIN_MASK)

#define LPIT_TCTRL_MODE_MASK                     (0xCU)
#define LPIT_TCTRL_MODE_SHIFT                    (2U)
/*! MODE - Timer Operation Mode
 *  0b00..32-bit Periodic Counter
 *  0b01..Dual 16-bit Periodic Counter
 *  0b10..32-bit Trigger Accumulator
 *  0b11..32-bit Trigger Input Capture
 */
#define LPIT_TCTRL_MODE(x)                       (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_MODE_SHIFT)) & LPIT_TCTRL_MODE_MASK)

#define LPIT_TCTRL_TSOT_MASK                     (0x10000U)
#define LPIT_TCTRL_TSOT_SHIFT                    (16U)
/*! TSOT - Timer Start On Trigger
 *  0b0..Timer starts to decrement immediately based on the restart condition (controlled by the Timer Stop On Interrupt bit (TSOI))
 *  0b1..Timer starts to decrement when a rising edge on a selected trigger is detected
 */
#define LPIT_TCTRL_TSOT(x)                       (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TSOT_SHIFT)) & LPIT_TCTRL_TSOT_MASK)

#define LPIT_TCTRL_TSOI_MASK                     (0x20000U)
#define LPIT_TCTRL_TSOI_SHIFT                    (17U)
/*! TSOI - Timer Stop On Interrupt
 *  0b0..The channel timer does not stop after timeout
 *  0b1..The channel timer will stop after a timeout, and the channel timer will restart based on Timer Start On
 *       Trigger bit (TSOT). When TSOT = 0, the channel timer will restart after a rising edge on the Timer Enable
 *       bit (T_EN) is detected (which means that the timer channel is disabled and then enabled). When TSOT = 1,
 *       the channel timer will restart after a rising edge on the selected trigger is detected.
 */
#define LPIT_TCTRL_TSOI(x)                       (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TSOI_SHIFT)) & LPIT_TCTRL_TSOI_MASK)

#define LPIT_TCTRL_TROT_MASK                     (0x40000U)
#define LPIT_TCTRL_TROT_SHIFT                    (18U)
/*! TROT - Timer Reload On Trigger
 *  0b0..Timer will not reload on the selected trigger
 *  0b1..Timer will reload on the selected trigger
 */
#define LPIT_TCTRL_TROT(x)                       (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TROT_SHIFT)) & LPIT_TCTRL_TROT_MASK)

#define LPIT_TCTRL_TRG_SRC_MASK                  (0x800000U)
#define LPIT_TCTRL_TRG_SRC_SHIFT                 (23U)
/*! TRG_SRC - Trigger Source
 *  0b0..Selects external triggers
 *  0b1..Selects internal triggers
 */
#define LPIT_TCTRL_TRG_SRC(x)                    (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TRG_SRC_SHIFT)) & LPIT_TCTRL_TRG_SRC_MASK)

#define LPIT_TCTRL_TRG_SEL_MASK                  (0xF000000U)
#define LPIT_TCTRL_TRG_SEL_SHIFT                 (24U)
/*! TRG_SEL - Trigger Select
 *  0b0000-0b0011..Timer channel 0 - 3 trigger source is selected
 *  0b0100-0b1111..Reserved
 */
#define LPIT_TCTRL_TRG_SEL(x)                    (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TRG_SEL_SHIFT)) & LPIT_TCTRL_TRG_SEL_MASK)
/*! @} */

/* The count of LPIT_TCTRL */
#define LPIT_TCTRL_COUNT                         (4U)


/*!
 * @}
 */ /* end of group LPIT_Register_Masks */


/* LPIT - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral LPIT0 base address */
  #define LPIT0_BASE                               (0x5002F000u)
  /** Peripheral LPIT0 base address */
  #define LPIT0_BASE_NS                            (0x4002F000u)
  /** Peripheral LPIT0 base pointer */
  #define LPIT0                                    ((LPIT_Type *)LPIT0_BASE)
  /** Peripheral LPIT0 base pointer */
  #define LPIT0_NS                                 ((LPIT_Type *)LPIT0_BASE_NS)
  /** Array initializer of LPIT peripheral base addresses */
  #define LPIT_BASE_ADDRS                          { LPIT0_BASE }
  /** Array initializer of LPIT peripheral base pointers */
  #define LPIT_BASE_PTRS                           { LPIT0 }
  /** Array initializer of LPIT peripheral base addresses */
  #define LPIT_BASE_ADDRS_NS                       { LPIT0_BASE_NS }
  /** Array initializer of LPIT peripheral base pointers */
  #define LPIT_BASE_PTRS_NS                        { LPIT0_NS }
#else
  /** Peripheral LPIT0 base address */
  #define LPIT0_BASE                               (0x4002F000u)
  /** Peripheral LPIT0 base pointer */
  #define LPIT0                                    ((LPIT_Type *)LPIT0_BASE)
  /** Array initializer of LPIT peripheral base addresses */
  #define LPIT_BASE_ADDRS                          { LPIT0_BASE }
  /** Array initializer of LPIT peripheral base pointers */
  #define LPIT_BASE_PTRS                           { LPIT0 }
#endif
/** Interrupt vectors for the LPIT peripheral type */
#define LPIT_IRQS                                { { LPIT0_IRQn, LPIT0_IRQn, LPIT0_IRQn, LPIT0_IRQn } }

/*!
 * @}
 */ /* end of group LPIT_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LPSPI Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LPSPI_Peripheral_Access_Layer LPSPI Peripheral Access Layer
 * @{
 */

/** LPSPI - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
  __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
       uint8_t RESERVED_0[8];
  __IO uint32_t CR;                                /**< Control, offset: 0x10 */
  __IO uint32_t SR;                                /**< Status, offset: 0x14 */
  __IO uint32_t IER;                               /**< Interrupt Enable, offset: 0x18 */
  __IO uint32_t DER;                               /**< DMA Enable, offset: 0x1C */
  __IO uint32_t CFGR0;                             /**< Configuration 0, offset: 0x20 */
  __IO uint32_t CFGR1;                             /**< Configuration 1, offset: 0x24 */
       uint8_t RESERVED_1[8];
  __IO uint32_t DMR0;                              /**< Data Match 0, offset: 0x30 */
  __IO uint32_t DMR1;                              /**< Data Match 1, offset: 0x34 */
       uint8_t RESERVED_2[8];
  __IO uint32_t CCR;                               /**< Clock Configuration, offset: 0x40 */
  __IO uint32_t CCR1;                              /**< Clock Configuration 1, offset: 0x44 */
       uint8_t RESERVED_3[16];
  __IO uint32_t FCR;                               /**< FIFO Control, offset: 0x58 */
  __I  uint32_t FSR;                               /**< FIFO Status, offset: 0x5C */
  __IO uint32_t TCR;                               /**< Transmit Command, offset: 0x60 */
  __O  uint32_t TDR;                               /**< Transmit Data, offset: 0x64 */
       uint8_t RESERVED_4[8];
  __I  uint32_t RSR;                               /**< Receive Status, offset: 0x70 */
  __I  uint32_t RDR;                               /**< Receive Data, offset: 0x74 */
  __I  uint32_t RDROR;                             /**< Receive Data Read Only, offset: 0x78 */
       uint8_t RESERVED_5[896];
  __O  uint32_t TCBR;                              /**< Transmit Command Burst, offset: 0x3FC */
  __O  uint32_t TDBR[128];                         /**< Transmit Data Burst, array offset: 0x400, array step: 0x4 */
  __I  uint32_t RDBR[128];                         /**< Receive Data Burst, array offset: 0x600, array step: 0x4 */
} LPSPI_Type;

/* ----------------------------------------------------------------------------
   -- LPSPI Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LPSPI_Register_Masks LPSPI Register Masks
 * @{
 */

/*! @name VERID - Version ID */
/*! @{ */

#define LPSPI_VERID_FEATURE_MASK                 (0xFFFFU)
#define LPSPI_VERID_FEATURE_SHIFT                (0U)
/*! FEATURE - Module Identification Number
 *  0b0000000000000100..Standard feature set supporting a 32-bit shift register.
 *  *..
 */
#define LPSPI_VERID_FEATURE(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK)

#define LPSPI_VERID_MINOR_MASK                   (0xFF0000U)
#define LPSPI_VERID_MINOR_SHIFT                  (16U)
/*! MINOR - Minor Version Number
 */
#define LPSPI_VERID_MINOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK)

#define LPSPI_VERID_MAJOR_MASK                   (0xFF000000U)
#define LPSPI_VERID_MAJOR_SHIFT                  (24U)
/*! MAJOR - Major Version Number
 */
#define LPSPI_VERID_MAJOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK)
/*! @} */

/*! @name PARAM - Parameter */
/*! @{ */

#define LPSPI_PARAM_TXFIFO_MASK                  (0xFFU)
#define LPSPI_PARAM_TXFIFO_SHIFT                 (0U)
/*! TXFIFO - Transmit FIFO Size
 */
#define LPSPI_PARAM_TXFIFO(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK)

#define LPSPI_PARAM_RXFIFO_MASK                  (0xFF00U)
#define LPSPI_PARAM_RXFIFO_SHIFT                 (8U)
/*! RXFIFO - Receive FIFO Size
 */
#define LPSPI_PARAM_RXFIFO(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK)

#define LPSPI_PARAM_PCSNUM_MASK                  (0xFF0000U)
#define LPSPI_PARAM_PCSNUM_SHIFT                 (16U)
/*! PCSNUM - PCS Number
 */
#define LPSPI_PARAM_PCSNUM(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK)
/*! @} */

/*! @name CR - Control */
/*! @{ */

#define LPSPI_CR_MEN_MASK                        (0x1U)
#define LPSPI_CR_MEN_SHIFT                       (0U)
/*! MEN - Module Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPSPI_CR_MEN(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK)

#define LPSPI_CR_RST_MASK                        (0x2U)
#define LPSPI_CR_RST_SHIFT                       (1U)
/*! RST - Software Reset
 *  0b0..Not reset
 *  0b1..Reset
 */
#define LPSPI_CR_RST(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK)

#define LPSPI_CR_DOZEN_MASK                      (0x4U)
#define LPSPI_CR_DOZEN_SHIFT                     (2U)
/*! DOZEN - Doze Mode Enable
 *  0b0..Enable
 *  0b1..Disable
 */
#define LPSPI_CR_DOZEN(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK)

#define LPSPI_CR_DBGEN_MASK                      (0x8U)
#define LPSPI_CR_DBGEN_SHIFT                     (3U)
/*! DBGEN - Debug Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPSPI_CR_DBGEN(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK)

#define LPSPI_CR_RTF_MASK                        (0x100U)
#define LPSPI_CR_RTF_SHIFT                       (8U)
/*! RTF - Reset Transmit FIFO
 *  0b0..No effect
 *  0b1..Reset
 */
#define LPSPI_CR_RTF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK)

#define LPSPI_CR_RRF_MASK                        (0x200U)
#define LPSPI_CR_RRF_SHIFT                       (9U)
/*! RRF - Reset Receive FIFO
 *  0b0..No effect
 *  0b1..Reset
 */
#define LPSPI_CR_RRF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK)
/*! @} */

/*! @name SR - Status */
/*! @{ */

#define LPSPI_SR_TDF_MASK                        (0x1U)
#define LPSPI_SR_TDF_SHIFT                       (0U)
/*! TDF - Transmit Data Flag
 *  0b0..Transmit data not requested
 *  0b1..Transmit data is requested
 */
#define LPSPI_SR_TDF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK)

#define LPSPI_SR_RDF_MASK                        (0x2U)
#define LPSPI_SR_RDF_SHIFT                       (1U)
/*! RDF - Receive Data Flag
 *  0b0..Receive data not ready
 *  0b1..Receive data is ready
 */
#define LPSPI_SR_RDF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK)

#define LPSPI_SR_WCF_MASK                        (0x100U)
#define LPSPI_SR_WCF_SHIFT                       (8U)
/*! WCF - Word Complete Flag
 *  0b0..Not complete
 *  0b1..Complete
 */
#define LPSPI_SR_WCF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK)

#define LPSPI_SR_FCF_MASK                        (0x200U)
#define LPSPI_SR_FCF_SHIFT                       (9U)
/*! FCF - Frame Complete Flag
 *  0b0..Not complete
 *  0b1..Complete
 */
#define LPSPI_SR_FCF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK)

#define LPSPI_SR_TCF_MASK                        (0x400U)
#define LPSPI_SR_TCF_SHIFT                       (10U)
/*! TCF - Transfer Complete Flag
 *  0b0..Not complete
 *  0b1..Complete
 */
#define LPSPI_SR_TCF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK)

#define LPSPI_SR_TEF_MASK                        (0x800U)
#define LPSPI_SR_TEF_SHIFT                       (11U)
/*! TEF - Transmit Error Flag
 *  0b0..No underrun
 *  0b1..Underrun
 */
#define LPSPI_SR_TEF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK)

#define LPSPI_SR_REF_MASK                        (0x1000U)
#define LPSPI_SR_REF_SHIFT                       (12U)
/*! REF - Receive Error Flag
 *  0b0..No overflow
 *  0b1..Overflow
 */
#define LPSPI_SR_REF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK)

#define LPSPI_SR_DMF_MASK                        (0x2000U)
#define LPSPI_SR_DMF_SHIFT                       (13U)
/*! DMF - Data Match Flag
 *  0b0..No match
 *  0b1..Match
 */
#define LPSPI_SR_DMF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK)

#define LPSPI_SR_MBF_MASK                        (0x1000000U)
#define LPSPI_SR_MBF_SHIFT                       (24U)
/*! MBF - Module Busy Flag
 *  0b0..LPSPI is idle
 *  0b1..LPSPI is busy
 */
#define LPSPI_SR_MBF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK)
/*! @} */

/*! @name IER - Interrupt Enable */
/*! @{ */

#define LPSPI_IER_TDIE_MASK                      (0x1U)
#define LPSPI_IER_TDIE_SHIFT                     (0U)
/*! TDIE - Transmit Data Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPSPI_IER_TDIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK)

#define LPSPI_IER_RDIE_MASK                      (0x2U)
#define LPSPI_IER_RDIE_SHIFT                     (1U)
/*! RDIE - Receive Data Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPSPI_IER_RDIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK)

#define LPSPI_IER_WCIE_MASK                      (0x100U)
#define LPSPI_IER_WCIE_SHIFT                     (8U)
/*! WCIE - Word Complete Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPSPI_IER_WCIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK)

#define LPSPI_IER_FCIE_MASK                      (0x200U)
#define LPSPI_IER_FCIE_SHIFT                     (9U)
/*! FCIE - Frame Complete Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPSPI_IER_FCIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK)

#define LPSPI_IER_TCIE_MASK                      (0x400U)
#define LPSPI_IER_TCIE_SHIFT                     (10U)
/*! TCIE - Transfer Complete Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPSPI_IER_TCIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK)

#define LPSPI_IER_TEIE_MASK                      (0x800U)
#define LPSPI_IER_TEIE_SHIFT                     (11U)
/*! TEIE - Transmit Error Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPSPI_IER_TEIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK)

#define LPSPI_IER_REIE_MASK                      (0x1000U)
#define LPSPI_IER_REIE_SHIFT                     (12U)
/*! REIE - Receive Error Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPSPI_IER_REIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK)

#define LPSPI_IER_DMIE_MASK                      (0x2000U)
#define LPSPI_IER_DMIE_SHIFT                     (13U)
/*! DMIE - Data Match Interrupt Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPSPI_IER_DMIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK)
/*! @} */

/*! @name DER - DMA Enable */
/*! @{ */

#define LPSPI_DER_TDDE_MASK                      (0x1U)
#define LPSPI_DER_TDDE_SHIFT                     (0U)
/*! TDDE - Transmit Data DMA Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPSPI_DER_TDDE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK)

#define LPSPI_DER_RDDE_MASK                      (0x2U)
#define LPSPI_DER_RDDE_SHIFT                     (1U)
/*! RDDE - Receive Data DMA Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPSPI_DER_RDDE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK)

#define LPSPI_DER_FCDE_MASK                      (0x200U)
#define LPSPI_DER_FCDE_SHIFT                     (9U)
/*! FCDE - Frame Complete DMA Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPSPI_DER_FCDE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_FCDE_SHIFT)) & LPSPI_DER_FCDE_MASK)
/*! @} */

/*! @name CFGR0 - Configuration 0 */
/*! @{ */

#define LPSPI_CFGR0_HREN_MASK                    (0x1U)
#define LPSPI_CFGR0_HREN_SHIFT                   (0U)
/*! HREN - Host Request Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPSPI_CFGR0_HREN(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK)

#define LPSPI_CFGR0_HRPOL_MASK                   (0x2U)
#define LPSPI_CFGR0_HRPOL_SHIFT                  (1U)
/*! HRPOL - Host Request Polarity
 *  0b0..Active high
 *  0b1..Active low
 */
#define LPSPI_CFGR0_HRPOL(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)

#define LPSPI_CFGR0_HRSEL_MASK                   (0x4U)
#define LPSPI_CFGR0_HRSEL_SHIFT                  (2U)
/*! HRSEL - Host Request Select
 *  0b0..HREQ pin
 *  0b1..Input trigger
 */
#define LPSPI_CFGR0_HRSEL(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK)

#define LPSPI_CFGR0_HRDIR_MASK                   (0x8U)
#define LPSPI_CFGR0_HRDIR_SHIFT                  (3U)
/*! HRDIR - Host Request Direction
 *  0b0..Input
 *  0b1..Output
 */
#define LPSPI_CFGR0_HRDIR(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRDIR_SHIFT)) & LPSPI_CFGR0_HRDIR_MASK)

#define LPSPI_CFGR0_CIRFIFO_MASK                 (0x100U)
#define LPSPI_CFGR0_CIRFIFO_SHIFT                (8U)
/*! CIRFIFO - Circular FIFO Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPSPI_CFGR0_CIRFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK)

#define LPSPI_CFGR0_RDMO_MASK                    (0x200U)
#define LPSPI_CFGR0_RDMO_SHIFT                   (9U)
/*! RDMO - Receive Data Match Only
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPSPI_CFGR0_RDMO(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK)
/*! @} */

/*! @name CFGR1 - Configuration 1 */
/*! @{ */

#define LPSPI_CFGR1_MASTER_MASK                  (0x1U)
#define LPSPI_CFGR1_MASTER_SHIFT                 (0U)
/*! MASTER - Master Mode
 *  0b0..Slave mode
 *  0b1..Master mode
 */
#define LPSPI_CFGR1_MASTER(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)

#define LPSPI_CFGR1_SAMPLE_MASK                  (0x2U)
#define LPSPI_CFGR1_SAMPLE_SHIFT                 (1U)
/*! SAMPLE - Sample Point
 *  0b0..SCK edge
 *  0b1..Delayed SCK edge
 */
#define LPSPI_CFGR1_SAMPLE(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK)

#define LPSPI_CFGR1_AUTOPCS_MASK                 (0x4U)
#define LPSPI_CFGR1_AUTOPCS_SHIFT                (2U)
/*! AUTOPCS - Automatic PCS
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPSPI_CFGR1_AUTOPCS(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK)

#define LPSPI_CFGR1_NOSTALL_MASK                 (0x8U)
#define LPSPI_CFGR1_NOSTALL_SHIFT                (3U)
/*! NOSTALL - No Stall
 *  0b0..Disable
 *  0b1..Enable
 */
#define LPSPI_CFGR1_NOSTALL(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK)

#define LPSPI_CFGR1_PARTIAL_MASK                 (0x10U)
#define LPSPI_CFGR1_PARTIAL_SHIFT                (4U)
/*! PARTIAL - Partial Enable
 *  0b0..Discard
 *  0b1..Store
 */
#define LPSPI_CFGR1_PARTIAL(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PARTIAL_SHIFT)) & LPSPI_CFGR1_PARTIAL_MASK)

#define LPSPI_CFGR1_PCSPOL_MASK                  (0xF00U)
#define LPSPI_CFGR1_PCSPOL_SHIFT                 (8U)
/*! PCSPOL - Peripheral Chip Select Polarity
 */
#define LPSPI_CFGR1_PCSPOL(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)

#define LPSPI_CFGR1_MATCFG_MASK                  (0x70000U)
#define LPSPI_CFGR1_MATCFG_SHIFT                 (16U)
/*! MATCFG - Match Configuration
 *  0b000..Match is disabled
 *  0b001..
 *  0b010..Match first data word with compare word
 *  0b011..Match any data word with compare word
 *  0b100..Sequential match, first data word
 *  0b101..Sequential match, any data word
 *  0b110..Match first data word (masked) with compare word (masked)
 *  0b111..Match any data word (masked) with compare word (masked)
 */
#define LPSPI_CFGR1_MATCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)

#define LPSPI_CFGR1_PINCFG_MASK                  (0x3000000U)
#define LPSPI_CFGR1_PINCFG_SHIFT                 (24U)
/*! PINCFG - Pin Configuration
 *  0b00..SIN is used for input data; SOUT is used for output data.
 *  0b01..SIN is used for both input and output data. Only half-duplex serial transfers are supported.
 *  0b10..SOUT is used for both input and output data. Only half-duplex serial transfers are supported.
 *  0b11..SOUT is used for input data; SIN is used for output data.
 */
#define LPSPI_CFGR1_PINCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK)

#define LPSPI_CFGR1_OUTCFG_MASK                  (0x4000000U)
#define LPSPI_CFGR1_OUTCFG_SHIFT                 (26U)
/*! OUTCFG - Output Configuration
 *  0b0..Output data retains last value.
 *  0b1..Output data is 3-stated.
 */
#define LPSPI_CFGR1_OUTCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK)

#define LPSPI_CFGR1_PCSCFG_MASK                  (0x8000000U)
#define LPSPI_CFGR1_PCSCFG_SHIFT                 (27U)
/*! PCSCFG - Peripheral Chip Select Configuration
 *  0b0..PCS[3:2] are configured for chip select function
 *  0b1..PCS[3:2] are configured for half-duplex 4-bit transfers (PCS[3:2] = DATA[3:2])
 */
#define LPSPI_CFGR1_PCSCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK)
/*! @} */

/*! @name DMR0 - Data Match 0 */
/*! @{ */

#define LPSPI_DMR0_MATCH0_MASK                   (0xFFFFFFFFU)
#define LPSPI_DMR0_MATCH0_SHIFT                  (0U)
/*! MATCH0 - Match 0 Value
 */
#define LPSPI_DMR0_MATCH0(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK)
/*! @} */

/*! @name DMR1 - Data Match 1 */
/*! @{ */

#define LPSPI_DMR1_MATCH1_MASK                   (0xFFFFFFFFU)
#define LPSPI_DMR1_MATCH1_SHIFT                  (0U)
/*! MATCH1 - Match 1 Value
 */
#define LPSPI_DMR1_MATCH1(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK)
/*! @} */

/*! @name CCR - Clock Configuration */
/*! @{ */

#define LPSPI_CCR_SCKDIV_MASK                    (0xFFU)
#define LPSPI_CCR_SCKDIV_SHIFT                   (0U)
/*! SCKDIV - SCK Divider
 */
#define LPSPI_CCR_SCKDIV(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK)

#define LPSPI_CCR_DBT_MASK                       (0xFF00U)
#define LPSPI_CCR_DBT_SHIFT                      (8U)
/*! DBT - Delay Between Transfers
 */
#define LPSPI_CCR_DBT(x)                         (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK)

#define LPSPI_CCR_PCSSCK_MASK                    (0xFF0000U)
#define LPSPI_CCR_PCSSCK_SHIFT                   (16U)
/*! PCSSCK - PCS-to-SCK Delay
 */
#define LPSPI_CCR_PCSSCK(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK)

#define LPSPI_CCR_SCKPCS_MASK                    (0xFF000000U)
#define LPSPI_CCR_SCKPCS_SHIFT                   (24U)
/*! SCKPCS - SCK-to-PCS Delay
 */
#define LPSPI_CCR_SCKPCS(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK)
/*! @} */

/*! @name CCR1 - Clock Configuration 1 */
/*! @{ */

#define LPSPI_CCR1_SCKSET_MASK                   (0xFFU)
#define LPSPI_CCR1_SCKSET_SHIFT                  (0U)
/*! SCKSET - SCK Setup
 */
#define LPSPI_CCR1_SCKSET(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKSET_SHIFT)) & LPSPI_CCR1_SCKSET_MASK)

#define LPSPI_CCR1_SCKHLD_MASK                   (0xFF00U)
#define LPSPI_CCR1_SCKHLD_SHIFT                  (8U)
/*! SCKHLD - SCK Hold
 */
#define LPSPI_CCR1_SCKHLD(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKHLD_SHIFT)) & LPSPI_CCR1_SCKHLD_MASK)

#define LPSPI_CCR1_PCSPCS_MASK                   (0xFF0000U)
#define LPSPI_CCR1_PCSPCS_SHIFT                  (16U)
/*! PCSPCS - PCS to PCS delay
 */
#define LPSPI_CCR1_PCSPCS(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_PCSPCS_SHIFT)) & LPSPI_CCR1_PCSPCS_MASK)

#define LPSPI_CCR1_SCKSCK_MASK                   (0xFF000000U)
#define LPSPI_CCR1_SCKSCK_SHIFT                  (24U)
/*! SCKSCK - SCK Inter-Frame Delay
 */
#define LPSPI_CCR1_SCKSCK(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKSCK_SHIFT)) & LPSPI_CCR1_SCKSCK_MASK)
/*! @} */

/*! @name FCR - FIFO Control */
/*! @{ */

#define LPSPI_FCR_TXWATER_MASK                   (0x7U)
#define LPSPI_FCR_TXWATER_SHIFT                  (0U)
/*! TXWATER - Transmit FIFO Watermark
 */
#define LPSPI_FCR_TXWATER(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK)

#define LPSPI_FCR_RXWATER_MASK                   (0x70000U)
#define LPSPI_FCR_RXWATER_SHIFT                  (16U)
/*! RXWATER - Receive FIFO Watermark
 */
#define LPSPI_FCR_RXWATER(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK)
/*! @} */

/*! @name FSR - FIFO Status */
/*! @{ */

#define LPSPI_FSR_TXCOUNT_MASK                   (0xFU)
#define LPSPI_FSR_TXCOUNT_SHIFT                  (0U)
/*! TXCOUNT - Transmit FIFO Count
 */
#define LPSPI_FSR_TXCOUNT(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK)

#define LPSPI_FSR_RXCOUNT_MASK                   (0xF0000U)
#define LPSPI_FSR_RXCOUNT_SHIFT                  (16U)
/*! RXCOUNT - Receive FIFO Count
 */
#define LPSPI_FSR_RXCOUNT(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK)
/*! @} */

/*! @name TCR - Transmit Command */
/*! @{ */

#define LPSPI_TCR_FRAMESZ_MASK                   (0xFFFU)
#define LPSPI_TCR_FRAMESZ_SHIFT                  (0U)
/*! FRAMESZ - Frame Size
 */
#define LPSPI_TCR_FRAMESZ(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK)

#define LPSPI_TCR_WIDTH_MASK                     (0x30000U)
#define LPSPI_TCR_WIDTH_SHIFT                    (16U)
/*! WIDTH - Transfer Width
 *  0b00..1-bit transfer
 *  0b01..2-bit transfer
 *  0b10..4-bit transfer
 *  0b11..Reserved
 */
#define LPSPI_TCR_WIDTH(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK)

#define LPSPI_TCR_TXMSK_MASK                     (0x40000U)
#define LPSPI_TCR_TXMSK_SHIFT                    (18U)
/*! TXMSK - Transmit Data Mask
 *  0b0..Normal transfer
 *  0b1..Mask transmit data
 */
#define LPSPI_TCR_TXMSK(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK)

#define LPSPI_TCR_RXMSK_MASK                     (0x80000U)
#define LPSPI_TCR_RXMSK_SHIFT                    (19U)
/*! RXMSK - Receive Data Mask
 *  0b0..Normal transfer
 *  0b1..Receive data is masked
 */
#define LPSPI_TCR_RXMSK(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK)

#define LPSPI_TCR_CONTC_MASK                     (0x100000U)
#define LPSPI_TCR_CONTC_SHIFT                    (20U)
/*! CONTC - Continuing Command
 *  0b0..Command word for start of new transfer
 *  0b1..Command word for continuing transfer
 */
#define LPSPI_TCR_CONTC(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK)

#define LPSPI_TCR_CONT_MASK                      (0x200000U)
#define LPSPI_TCR_CONT_SHIFT                     (21U)
/*! CONT - Continuous Transfer
 *  0b0..Continuous transfer is disabled
 *  0b1..Continuous transfer is enabled
 */
#define LPSPI_TCR_CONT(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK)

#define LPSPI_TCR_BYSW_MASK                      (0x400000U)
#define LPSPI_TCR_BYSW_SHIFT                     (22U)
/*! BYSW - Byte Swap
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define LPSPI_TCR_BYSW(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK)

#define LPSPI_TCR_LSBF_MASK                      (0x800000U)
#define LPSPI_TCR_LSBF_SHIFT                     (23U)
/*! LSBF - LSB First
 *  0b0..Data is transferred MSB first
 *  0b1..Data is transferred LSB first
 */
#define LPSPI_TCR_LSBF(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK)

#define LPSPI_TCR_PCS_MASK                       (0x3000000U)
#define LPSPI_TCR_PCS_SHIFT                      (24U)
/*! PCS - Peripheral Chip Select
 *  0b00..Transfer using PCS[0]
 *  0b01..Transfer using PCS[1]
 *  0b10..Transfer using PCS[2]
 *  0b11..Transfer using PCS[3]
 */
#define LPSPI_TCR_PCS(x)                         (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK)

#define LPSPI_TCR_PRESCALE_MASK                  (0x38000000U)
#define LPSPI_TCR_PRESCALE_SHIFT                 (27U)
/*! PRESCALE - Prescaler Value
 *  0b000..Divide by 1
 *  0b001..Divide by 2
 *  0b010..Divide by 4
 *  0b011..Divide by 8
 *  0b100..Divide by 16
 *  0b101..Divide by 32
 *  0b110..Divide by 64
 *  0b111..Divide by 128
 */
#define LPSPI_TCR_PRESCALE(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK)

#define LPSPI_TCR_CPHA_MASK                      (0x40000000U)
#define LPSPI_TCR_CPHA_SHIFT                     (30U)
/*! CPHA - Clock Phase
 *  0b0..Captured
 *  0b1..Changed
 */
#define LPSPI_TCR_CPHA(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK)

#define LPSPI_TCR_CPOL_MASK                      (0x80000000U)
#define LPSPI_TCR_CPOL_SHIFT                     (31U)
/*! CPOL - Clock Polarity
 *  0b0..Inactive low
 *  0b1..Inactive high
 */
#define LPSPI_TCR_CPOL(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK)
/*! @} */

/*! @name TDR - Transmit Data */
/*! @{ */

#define LPSPI_TDR_DATA_MASK                      (0xFFFFFFFFU)
#define LPSPI_TDR_DATA_SHIFT                     (0U)
/*! DATA - Transmit Data
 */
#define LPSPI_TDR_DATA(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK)
/*! @} */

/*! @name RSR - Receive Status */
/*! @{ */

#define LPSPI_RSR_SOF_MASK                       (0x1U)
#define LPSPI_RSR_SOF_SHIFT                      (0U)
/*! SOF - Start Of Frame
 *  0b0..Subsequent data word
 *  0b1..First data word
 */
#define LPSPI_RSR_SOF(x)                         (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK)

#define LPSPI_RSR_RXEMPTY_MASK                   (0x2U)
#define LPSPI_RSR_RXEMPTY_SHIFT                  (1U)
/*! RXEMPTY - RX FIFO Empty
 *  0b0..Not empty
 *  0b1..Empty
 */
#define LPSPI_RSR_RXEMPTY(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK)
/*! @} */

/*! @name RDR - Receive Data */
/*! @{ */

#define LPSPI_RDR_DATA_MASK                      (0xFFFFFFFFU)
#define LPSPI_RDR_DATA_SHIFT                     (0U)
/*! DATA - Receive Data
 */
#define LPSPI_RDR_DATA(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK)
/*! @} */

/*! @name RDROR - Receive Data Read Only */
/*! @{ */

#define LPSPI_RDROR_DATA_MASK                    (0xFFFFFFFFU)
#define LPSPI_RDROR_DATA_SHIFT                   (0U)
/*! DATA - Receive Data
 */
#define LPSPI_RDROR_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_RDROR_DATA_SHIFT)) & LPSPI_RDROR_DATA_MASK)
/*! @} */

/*! @name TCBR - Transmit Command Burst */
/*! @{ */

#define LPSPI_TCBR_DATA_MASK                     (0xFFFFFFFFU)
#define LPSPI_TCBR_DATA_SHIFT                    (0U)
/*! DATA - Command Data
 */
#define LPSPI_TCBR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCBR_DATA_SHIFT)) & LPSPI_TCBR_DATA_MASK)
/*! @} */

/*! @name TDBR - Transmit Data Burst */
/*! @{ */

#define LPSPI_TDBR_DATA_MASK                     (0xFFFFFFFFU)
#define LPSPI_TDBR_DATA_SHIFT                    (0U)
/*! DATA - Data
 */
#define LPSPI_TDBR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TDBR_DATA_SHIFT)) & LPSPI_TDBR_DATA_MASK)
/*! @} */

/* The count of LPSPI_TDBR */
#define LPSPI_TDBR_COUNT                         (128U)

/*! @name RDBR - Receive Data Burst */
/*! @{ */

#define LPSPI_RDBR_DATA_MASK                     (0xFFFFFFFFU)
#define LPSPI_RDBR_DATA_SHIFT                    (0U)
/*! DATA - Data
 */
#define LPSPI_RDBR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_RDBR_DATA_SHIFT)) & LPSPI_RDBR_DATA_MASK)
/*! @} */

/* The count of LPSPI_RDBR */
#define LPSPI_RDBR_COUNT                         (128U)


/*!
 * @}
 */ /* end of group LPSPI_Register_Masks */


/* LPSPI - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral LPSPI0 base address */
  #define LPSPI0_BASE                              (0x50036000u)
  /** Peripheral LPSPI0 base address */
  #define LPSPI0_BASE_NS                           (0x40036000u)
  /** Peripheral LPSPI0 base pointer */
  #define LPSPI0                                   ((LPSPI_Type *)LPSPI0_BASE)
  /** Peripheral LPSPI0 base pointer */
  #define LPSPI0_NS                                ((LPSPI_Type *)LPSPI0_BASE_NS)
  /** Peripheral LPSPI1 base address */
  #define LPSPI1_BASE                              (0x50037000u)
  /** Peripheral LPSPI1 base address */
  #define LPSPI1_BASE_NS                           (0x40037000u)
  /** Peripheral LPSPI1 base pointer */
  #define LPSPI1                                   ((LPSPI_Type *)LPSPI1_BASE)
  /** Peripheral LPSPI1 base pointer */
  #define LPSPI1_NS                                ((LPSPI_Type *)LPSPI1_BASE_NS)
  /** Array initializer of LPSPI peripheral base addresses */
  #define LPSPI_BASE_ADDRS                         { LPSPI0_BASE, LPSPI1_BASE }
  /** Array initializer of LPSPI peripheral base pointers */
  #define LPSPI_BASE_PTRS                          { LPSPI0, LPSPI1 }
  /** Array initializer of LPSPI peripheral base addresses */
  #define LPSPI_BASE_ADDRS_NS                      { LPSPI0_BASE_NS, LPSPI1_BASE_NS }
  /** Array initializer of LPSPI peripheral base pointers */
  #define LPSPI_BASE_PTRS_NS                       { LPSPI0_NS, LPSPI1_NS }
#else
  /** Peripheral LPSPI0 base address */
  #define LPSPI0_BASE                              (0x40036000u)
  /** Peripheral LPSPI0 base pointer */
  #define LPSPI0                                   ((LPSPI_Type *)LPSPI0_BASE)
  /** Peripheral LPSPI1 base address */
  #define LPSPI1_BASE                              (0x40037000u)
  /** Peripheral LPSPI1 base pointer */
  #define LPSPI1                                   ((LPSPI_Type *)LPSPI1_BASE)
  /** Array initializer of LPSPI peripheral base addresses */
  #define LPSPI_BASE_ADDRS                         { LPSPI0_BASE, LPSPI1_BASE }
  /** Array initializer of LPSPI peripheral base pointers */
  #define LPSPI_BASE_PTRS                          { LPSPI0, LPSPI1 }
#endif
/** Interrupt vectors for the LPSPI peripheral type */
#define LPSPI_IRQS                               { LPSPI0_IRQn, LPSPI1_IRQn }

/*!
 * @}
 */ /* end of group LPSPI_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LPTMR Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
 * @{
 */

/** LPTMR - Register Layout Typedef */
typedef struct {
  __IO uint32_t CSR;                               /**< Control Status Register, offset: 0x0 */
  __IO uint32_t PSR;                               /**< Prescale and Glitch Filter Register, offset: 0x4 */
  __IO uint32_t CMR;                               /**< Compare Register, offset: 0x8 */
  __IO uint32_t CNR;                               /**< Counter Register, offset: 0xC */
} LPTMR_Type;

/* ----------------------------------------------------------------------------
   -- LPTMR Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
 * @{
 */

/*! @name CSR - Control Status Register */
/*! @{ */

#define LPTMR_CSR_TEN_MASK                       (0x1U)
#define LPTMR_CSR_TEN_SHIFT                      (0U)
/*! TEN - Timer Enable
 *  0b0..LPTMR is disabled and internal logic is reset.
 *  0b1..LPTMR is enabled.
 */
#define LPTMR_CSR_TEN(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)

#define LPTMR_CSR_TMS_MASK                       (0x2U)
#define LPTMR_CSR_TMS_SHIFT                      (1U)
/*! TMS - Timer Mode Select
 *  0b0..Time Counter mode.
 *  0b1..Pulse Counter mode.
 */
#define LPTMR_CSR_TMS(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)

#define LPTMR_CSR_TFC_MASK                       (0x4U)
#define LPTMR_CSR_TFC_SHIFT                      (2U)
/*! TFC - Timer Free-Running Counter
 *  0b0..CNR is reset whenever TCF is set.
 *  0b1..CNR is reset on overflow.
 */
#define LPTMR_CSR_TFC(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)

#define LPTMR_CSR_TPP_MASK                       (0x8U)
#define LPTMR_CSR_TPP_SHIFT                      (3U)
/*! TPP - Timer Pin Polarity
 *  0b0..Pulse Counter input source is active-high, and the CNR increments on the rising-edge.
 *  0b1..Pulse Counter input source is active-low, and the CNR increments on the falling-edge.
 */
#define LPTMR_CSR_TPP(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)

#define LPTMR_CSR_TPS_MASK                       (0x30U)
#define LPTMR_CSR_TPS_SHIFT                      (4U)
/*! TPS - Timer Pin Select
 *  0b00..Pulse counter input 0 is selected.
 *  0b01..Pulse counter input 1 is selected.
 *  0b10..Pulse counter input 2 is selected.
 *  0b11..Pulse counter input 3 is selected.
 */
#define LPTMR_CSR_TPS(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)

#define LPTMR_CSR_TIE_MASK                       (0x40U)
#define LPTMR_CSR_TIE_SHIFT                      (6U)
/*! TIE - Timer Interrupt Enable
 *  0b0..Timer interrupt disabled.
 *  0b1..Timer interrupt enabled.
 */
#define LPTMR_CSR_TIE(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)

#define LPTMR_CSR_TCF_MASK                       (0x80U)
#define LPTMR_CSR_TCF_SHIFT                      (7U)
/*! TCF - Timer Compare Flag
 *  0b0..The value of CNR is not equal to CMR + 1.
 *  0b1..The value of CNR is equal to CMR + 1.
 */
#define LPTMR_CSR_TCF(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)

#define LPTMR_CSR_TDRE_MASK                      (0x100U)
#define LPTMR_CSR_TDRE_SHIFT                     (8U)
/*! TDRE - Timer DMA Request Enable
 *  0b0..Timer DMA Request disabled.
 *  0b1..Timer DMA Request enabled.
 */
#define LPTMR_CSR_TDRE(x)                        (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TDRE_SHIFT)) & LPTMR_CSR_TDRE_MASK)
/*! @} */

/*! @name PSR - Prescale and Glitch Filter Register */
/*! @{ */

#define LPTMR_PSR_PCS_MASK                       (0x3U)
#define LPTMR_PSR_PCS_SHIFT                      (0U)
/*! PCS - Prescaler/Glitch Filter Clock Select
 *  0b00..Prescaler/glitch filter clock 0 selected.
 *  0b01..Prescaler/glitch filter clock 1 selected.
 *  0b10..Prescaler/glitch filter clock 2 selected.
 *  0b11..Prescaler/glitch filter clock 3 selected.
 */
#define LPTMR_PSR_PCS(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)

#define LPTMR_PSR_PBYP_MASK                      (0x4U)
#define LPTMR_PSR_PBYP_SHIFT                     (2U)
/*! PBYP - Prescaler/Glitch Filter Bypass
 *  0b0..Prescaler/glitch filter is enabled.
 *  0b1..Prescaler/glitch filter is bypassed.
 */
#define LPTMR_PSR_PBYP(x)                        (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)

#define LPTMR_PSR_PRESCALE_MASK                  (0x78U)
#define LPTMR_PSR_PRESCALE_SHIFT                 (3U)
/*! PRESCALE - Prescale/Glitch Filter Value
 *  0b0000..Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration.
 *  0b0001..Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges.
 *  0b0010..Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges.
 *  0b0011..Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges.
 *  0b0100..Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges.
 *  0b0101..Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges.
 *  0b0110..Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges.
 *  0b0111..Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges.
 *  0b1000..Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges.
 *  0b1001..Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges.
 *  0b1010..Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges.
 *  0b1011..Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges.
 *  0b1100..Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges.
 *  0b1101..Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges.
 *  0b1110..Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges.
 *  0b1111..Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges.
 */
#define LPTMR_PSR_PRESCALE(x)                    (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
/*! @} */

/*! @name CMR - Compare Register */
/*! @{ */

#define LPTMR_CMR_COMPARE_MASK                   (0xFFFFFFFFU)
#define LPTMR_CMR_COMPARE_SHIFT                  (0U)
/*! COMPARE - Compare Value
 */
#define LPTMR_CMR_COMPARE(x)                     (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
/*! @} */

/*! @name CNR - Counter Register */
/*! @{ */

#define LPTMR_CNR_COUNTER_MASK                   (0xFFFFFFFFU)
#define LPTMR_CNR_COUNTER_SHIFT                  (0U)
/*! COUNTER - Counter Value
 */
#define LPTMR_CNR_COUNTER(x)                     (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LPTMR_Register_Masks */


/* LPTMR - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral LPTMR0 base address */
  #define LPTMR0_BASE                              (0x5002D000u)
  /** Peripheral LPTMR0 base address */
  #define LPTMR0_BASE_NS                           (0x4002D000u)
  /** Peripheral LPTMR0 base pointer */
  #define LPTMR0                                   ((LPTMR_Type *)LPTMR0_BASE)
  /** Peripheral LPTMR0 base pointer */
  #define LPTMR0_NS                                ((LPTMR_Type *)LPTMR0_BASE_NS)
  /** Peripheral LPTMR1 base address */
  #define LPTMR1_BASE                              (0x5002E000u)
  /** Peripheral LPTMR1 base address */
  #define LPTMR1_BASE_NS                           (0x4002E000u)
  /** Peripheral LPTMR1 base pointer */
  #define LPTMR1                                   ((LPTMR_Type *)LPTMR1_BASE)
  /** Peripheral LPTMR1 base pointer */
  #define LPTMR1_NS                                ((LPTMR_Type *)LPTMR1_BASE_NS)
  /** Array initializer of LPTMR peripheral base addresses */
  #define LPTMR_BASE_ADDRS                         { LPTMR0_BASE, LPTMR1_BASE }
  /** Array initializer of LPTMR peripheral base pointers */
  #define LPTMR_BASE_PTRS                          { LPTMR0, LPTMR1 }
  /** Array initializer of LPTMR peripheral base addresses */
  #define LPTMR_BASE_ADDRS_NS                      { LPTMR0_BASE_NS, LPTMR1_BASE_NS }
  /** Array initializer of LPTMR peripheral base pointers */
  #define LPTMR_BASE_PTRS_NS                       { LPTMR0_NS, LPTMR1_NS }
#else
  /** Peripheral LPTMR0 base address */
  #define LPTMR0_BASE                              (0x4002D000u)
  /** Peripheral LPTMR0 base pointer */
  #define LPTMR0                                   ((LPTMR_Type *)LPTMR0_BASE)
  /** Peripheral LPTMR1 base address */
  #define LPTMR1_BASE                              (0x4002E000u)
  /** Peripheral LPTMR1 base pointer */
  #define LPTMR1                                   ((LPTMR_Type *)LPTMR1_BASE)
  /** Array initializer of LPTMR peripheral base addresses */
  #define LPTMR_BASE_ADDRS                         { LPTMR0_BASE, LPTMR1_BASE }
  /** Array initializer of LPTMR peripheral base pointers */
  #define LPTMR_BASE_PTRS                          { LPTMR0, LPTMR1 }
#endif
/** Interrupt vectors for the LPTMR peripheral type */
#define LPTMR_IRQS                               { LPTMR0_IRQn, LPTMR1_IRQn }

/*!
 * @}
 */ /* end of group LPTMR_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LPUART Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
 * @{
 */

/** LPUART - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
  __IO uint32_t GLOBAL;                            /**< LPUART Global Register, offset: 0x8 */
  __IO uint32_t PINCFG;                            /**< LPUART Pin Configuration Register, offset: 0xC */
  __IO uint32_t BAUD;                              /**< LPUART Baud Rate Register, offset: 0x10 */
  __IO uint32_t STAT;                              /**< LPUART Status Register, offset: 0x14 */
  __IO uint32_t CTRL;                              /**< LPUART Control Register, offset: 0x18 */
  __IO uint32_t DATA;                              /**< LPUART Data Register, offset: 0x1C */
  __IO uint32_t MATCH;                             /**< LPUART Match Address Register, offset: 0x20 */
  __IO uint32_t MODIR;                             /**< LPUART Modem IrDA Register, offset: 0x24 */
  __IO uint32_t FIFO;                              /**< LPUART FIFO Register, offset: 0x28 */
  __IO uint32_t WATER;                             /**< LPUART Watermark Register, offset: 0x2C */
  __I  uint32_t DATARO;                            /**< Data read-only Register, offset: 0x30 */
} LPUART_Type;

/* ----------------------------------------------------------------------------
   -- LPUART Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LPUART_Register_Masks LPUART Register Masks
 * @{
 */

/*! @name VERID - Version ID Register */
/*! @{ */

#define LPUART_VERID_FEATURE_MASK                (0xFFFFU)
#define LPUART_VERID_FEATURE_SHIFT               (0U)
/*! FEATURE - Feature Identification Number
 *  0b0000000000000001..Standard feature set.
 *  0b0000000000000011..Standard feature set with MODEM/IrDA support.
 */
#define LPUART_VERID_FEATURE(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK)

#define LPUART_VERID_MINOR_MASK                  (0xFF0000U)
#define LPUART_VERID_MINOR_SHIFT                 (16U)
/*! MINOR - Minor Version Number
 */
#define LPUART_VERID_MINOR(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK)

#define LPUART_VERID_MAJOR_MASK                  (0xFF000000U)
#define LPUART_VERID_MAJOR_SHIFT                 (24U)
/*! MAJOR - Major Version Number
 */
#define LPUART_VERID_MAJOR(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK)
/*! @} */

/*! @name PARAM - Parameter Register */
/*! @{ */

#define LPUART_PARAM_TXFIFO_MASK                 (0xFFU)
#define LPUART_PARAM_TXFIFO_SHIFT                (0U)
/*! TXFIFO - Transmit FIFO Size
 */
#define LPUART_PARAM_TXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK)

#define LPUART_PARAM_RXFIFO_MASK                 (0xFF00U)
#define LPUART_PARAM_RXFIFO_SHIFT                (8U)
/*! RXFIFO - Receive FIFO Size
 */
#define LPUART_PARAM_RXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK)
/*! @} */

/*! @name GLOBAL - LPUART Global Register */
/*! @{ */

#define LPUART_GLOBAL_RST_MASK                   (0x2U)
#define LPUART_GLOBAL_RST_SHIFT                  (1U)
/*! RST - Software Reset
 *  0b0..Module is not reset.
 *  0b1..Module is reset.
 */
#define LPUART_GLOBAL_RST(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK)
/*! @} */

/*! @name PINCFG - LPUART Pin Configuration Register */
/*! @{ */

#define LPUART_PINCFG_TRGSEL_MASK                (0x3U)
#define LPUART_PINCFG_TRGSEL_SHIFT               (0U)
/*! TRGSEL - Trigger Select
 *  0b00..Input trigger is disabled.
 *  0b01..Input trigger is used instead of RXD pin input.
 *  0b10..Input trigger is used instead of CTS_B pin input.
 *  0b11..Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is
 *        internally ANDed with the input trigger.
 */
#define LPUART_PINCFG_TRGSEL(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK)
/*! @} */

/*! @name BAUD - LPUART Baud Rate Register */
/*! @{ */

#define LPUART_BAUD_SBR_MASK                     (0x1FFFU)
#define LPUART_BAUD_SBR_SHIFT                    (0U)
/*! SBR - Baud Rate Modulo Divisor.
 */
#define LPUART_BAUD_SBR(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)

#define LPUART_BAUD_SBNS_MASK                    (0x2000U)
#define LPUART_BAUD_SBNS_SHIFT                   (13U)
/*! SBNS - Stop Bit Number Select
 *  0b0..One stop bit.
 *  0b1..Two stop bits.
 */
#define LPUART_BAUD_SBNS(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)

#define LPUART_BAUD_RXEDGIE_MASK                 (0x4000U)
#define LPUART_BAUD_RXEDGIE_SHIFT                (14U)
/*! RXEDGIE - RX Input Active Edge Interrupt Enable
 *  0b0..Hardware interrupts from STAT[RXEDGIF] are disabled.
 *  0b1..Hardware interrupt is requested when STAT[RXEDGIF] flag is 1.
 */
#define LPUART_BAUD_RXEDGIE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)

#define LPUART_BAUD_LBKDIE_MASK                  (0x8000U)
#define LPUART_BAUD_LBKDIE_SHIFT                 (15U)
/*! LBKDIE - LIN Break Detect Interrupt Enable
 *  0b0..Hardware interrupts from STAT[LBKDIF] flag are disabled (use polling).
 *  0b1..Hardware interrupt is requested when STAT[LBKDIF] flag is 1.
 */
#define LPUART_BAUD_LBKDIE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)

#define LPUART_BAUD_RESYNCDIS_MASK               (0x10000U)
#define LPUART_BAUD_RESYNCDIS_SHIFT              (16U)
/*! RESYNCDIS - Resynchronization Disable
 *  0b0..Resynchronization during received data word is supported.
 *  0b1..Resynchronization during received data word is disabled.
 */
#define LPUART_BAUD_RESYNCDIS(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)

#define LPUART_BAUD_BOTHEDGE_MASK                (0x20000U)
#define LPUART_BAUD_BOTHEDGE_SHIFT               (17U)
/*! BOTHEDGE - Both Edge Sampling
 *  0b0..Receiver samples input data using the rising edge of the baud rate clock.
 *  0b1..Receiver samples input data using the rising and falling edge of the baud rate clock.
 */
#define LPUART_BAUD_BOTHEDGE(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)

#define LPUART_BAUD_MATCFG_MASK                  (0xC0000U)
#define LPUART_BAUD_MATCFG_SHIFT                 (18U)
/*! MATCFG - Match Configuration
 *  0b00..Address Match Wakeup
 *  0b01..Idle Match Wakeup
 *  0b10..Match On and Match Off
 *  0b11..Enables RWU on Data Match and Match On/Off for transmitter CTS input
 */
#define LPUART_BAUD_MATCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)

#define LPUART_BAUD_RIDMAE_MASK                  (0x100000U)
#define LPUART_BAUD_RIDMAE_SHIFT                 (20U)
/*! RIDMAE - Receiver Idle DMA Enable
 *  0b0..DMA request disabled.
 *  0b1..DMA request enabled.
 */
#define LPUART_BAUD_RIDMAE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RIDMAE_SHIFT)) & LPUART_BAUD_RIDMAE_MASK)

#define LPUART_BAUD_RDMAE_MASK                   (0x200000U)
#define LPUART_BAUD_RDMAE_SHIFT                  (21U)
/*! RDMAE - Receiver Full DMA Enable
 *  0b0..DMA request disabled.
 *  0b1..DMA request enabled.
 */
#define LPUART_BAUD_RDMAE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)

#define LPUART_BAUD_TDMAE_MASK                   (0x800000U)
#define LPUART_BAUD_TDMAE_SHIFT                  (23U)
/*! TDMAE - Transmitter DMA Enable
 *  0b0..DMA request disabled.
 *  0b1..DMA request enabled.
 */
#define LPUART_BAUD_TDMAE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)

#define LPUART_BAUD_OSR_MASK                     (0x1F000000U)
#define LPUART_BAUD_OSR_SHIFT                    (24U)
/*! OSR - Oversampling Ratio
 *  0b00000..Writing 0 to this field results in an oversampling ratio of 16
 *  0b00001..Reserved
 *  0b00010..Reserved
 *  0b00011..Oversampling ratio of 4, requires BOTHEDGE to be set.
 *  0b00100..Oversampling ratio of 5, requires BOTHEDGE to be set.
 *  0b00101..Oversampling ratio of 6, requires BOTHEDGE to be set.
 *  0b00110..Oversampling ratio of 7, requires BOTHEDGE to be set.
 *  0b00111..Oversampling ratio of 8.
 *  0b01000..Oversampling ratio of 9.
 *  0b01001..Oversampling ratio of 10.
 *  0b01010..Oversampling ratio of 11.
 *  0b01011..Oversampling ratio of 12.
 *  0b01100..Oversampling ratio of 13.
 *  0b01101..Oversampling ratio of 14.
 *  0b01110..Oversampling ratio of 15.
 *  0b01111..Oversampling ratio of 16.
 *  0b10000..Oversampling ratio of 17.
 *  0b10001..Oversampling ratio of 18.
 *  0b10010..Oversampling ratio of 19.
 *  0b10011..Oversampling ratio of 20.
 *  0b10100..Oversampling ratio of 21.
 *  0b10101..Oversampling ratio of 22.
 *  0b10110..Oversampling ratio of 23.
 *  0b10111..Oversampling ratio of 24.
 *  0b11000..Oversampling ratio of 25.
 *  0b11001..Oversampling ratio of 26.
 *  0b11010..Oversampling ratio of 27.
 *  0b11011..Oversampling ratio of 28.
 *  0b11100..Oversampling ratio of 29.
 *  0b11101..Oversampling ratio of 30.
 *  0b11110..Oversampling ratio of 31.
 *  0b11111..Oversampling ratio of 32.
 */
#define LPUART_BAUD_OSR(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)

#define LPUART_BAUD_M10_MASK                     (0x20000000U)
#define LPUART_BAUD_M10_SHIFT                    (29U)
/*! M10 - 10-bit Mode select
 *  0b0..Receiver and transmitter use 7-bit to 9-bit data characters.
 *  0b1..Receiver and transmitter use 10-bit data characters.
 */
#define LPUART_BAUD_M10(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)

#define LPUART_BAUD_MAEN2_MASK                   (0x40000000U)
#define LPUART_BAUD_MAEN2_SHIFT                  (30U)
/*! MAEN2 - Match Address Mode Enable 2
 *  0b0..Normal operation.
 *  0b1..Enables automatic address matching or data matching mode for MATCH[MA2].
 */
#define LPUART_BAUD_MAEN2(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)

#define LPUART_BAUD_MAEN1_MASK                   (0x80000000U)
#define LPUART_BAUD_MAEN1_SHIFT                  (31U)
/*! MAEN1 - Match Address Mode Enable 1
 *  0b0..Normal operation.
 *  0b1..Enables automatic address matching or data matching mode for MATCH[MA1].
 */
#define LPUART_BAUD_MAEN1(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)
/*! @} */

/*! @name STAT - LPUART Status Register */
/*! @{ */

#define LPUART_STAT_LBKFE_MASK                   (0x1U)
#define LPUART_STAT_LBKFE_SHIFT                  (0U)
/*! LBKFE - LIN Break Flag Enable
 *  0b0..LIN break detect is disabled.
 *  0b1..LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1).
 */
#define LPUART_STAT_LBKFE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKFE_SHIFT)) & LPUART_STAT_LBKFE_MASK)

#define LPUART_STAT_AME_MASK                     (0x2U)
#define LPUART_STAT_AME_SHIFT                    (1U)
/*! AME - Address Mark Enable
 *  0b0..Address mark in character is MSB.
 *  0b1..Address mark in character is last bit before stop bit (or parity bit when enabled) and stored in DATA
 *       register at MSB (or MSB-1 when parity bit enabled).
 */
#define LPUART_STAT_AME(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_AME_SHIFT)) & LPUART_STAT_AME_MASK)

#define LPUART_STAT_MA2F_MASK                    (0x4000U)
#define LPUART_STAT_MA2F_SHIFT                   (14U)
/*! MA2F - Match 2 Flag
 *  0b0..Received data is not equal to MA2
 *  0b1..Received data is equal to MA2
 */
#define LPUART_STAT_MA2F(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)

#define LPUART_STAT_MA1F_MASK                    (0x8000U)
#define LPUART_STAT_MA1F_SHIFT                   (15U)
/*! MA1F - Match 1 Flag
 *  0b0..Received data is not equal to MA1
 *  0b1..Received data is equal to MA1
 */
#define LPUART_STAT_MA1F(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)

#define LPUART_STAT_PF_MASK                      (0x10000U)
#define LPUART_STAT_PF_SHIFT                     (16U)
/*! PF - Parity Error Flag
 *  0b0..No parity error.
 *  0b1..Parity error.
 */
#define LPUART_STAT_PF(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)

#define LPUART_STAT_FE_MASK                      (0x20000U)
#define LPUART_STAT_FE_SHIFT                     (17U)
/*! FE - Framing Error Flag
 *  0b0..No framing error detected. This does not guarantee the framing is correct.
 *  0b1..Framing error.
 */
#define LPUART_STAT_FE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)

#define LPUART_STAT_NF_MASK                      (0x40000U)
#define LPUART_STAT_NF_SHIFT                     (18U)
/*! NF - Noise Flag
 *  0b0..No noise detected.
 *  0b1..Noise detected in the received character in the DATA register.
 */
#define LPUART_STAT_NF(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)

#define LPUART_STAT_OR_MASK                      (0x80000U)
#define LPUART_STAT_OR_SHIFT                     (19U)
/*! OR - Receiver Overrun Flag
 *  0b0..No overrun.
 *  0b1..Receive overrun (new LPUART data lost).
 */
#define LPUART_STAT_OR(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)

#define LPUART_STAT_IDLE_MASK                    (0x100000U)
#define LPUART_STAT_IDLE_SHIFT                   (20U)
/*! IDLE - Idle Line Flag
 *  0b0..No idle line detected.
 *  0b1..Idle line is detected.
 */
#define LPUART_STAT_IDLE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)

#define LPUART_STAT_RDRF_MASK                    (0x200000U)
#define LPUART_STAT_RDRF_SHIFT                   (21U)
/*! RDRF - Receive Data Register Full Flag
 *  0b0..Receive FIFO level is less than watermark.
 *  0b1..Receive FIFO level is equal or greater than watermark.
 */
#define LPUART_STAT_RDRF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)

#define LPUART_STAT_TC_MASK                      (0x400000U)
#define LPUART_STAT_TC_SHIFT                     (22U)
/*! TC - Transmission Complete Flag
 *  0b0..Transmitter active (sending data, a preamble, or a break).
 *  0b1..Transmitter idle (transmission activity complete).
 */
#define LPUART_STAT_TC(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)

#define LPUART_STAT_TDRE_MASK                    (0x800000U)
#define LPUART_STAT_TDRE_SHIFT                   (23U)
/*! TDRE - Transmit Data Register Empty Flag
 *  0b0..Transmit FIFO level is greater than watermark.
 *  0b1..Transmit FIFO level is equal or less than watermark.
 */
#define LPUART_STAT_TDRE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)

#define LPUART_STAT_RAF_MASK                     (0x1000000U)
#define LPUART_STAT_RAF_SHIFT                    (24U)
/*! RAF - Receiver Active Flag
 *  0b0..LPUART receiver idle waiting for a start bit.
 *  0b1..LPUART receiver active (RXD input not idle).
 */
#define LPUART_STAT_RAF(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)

#define LPUART_STAT_LBKDE_MASK                   (0x2000000U)
#define LPUART_STAT_LBKDE_SHIFT                  (25U)
/*! LBKDE - LIN Break Detection Enable
 *  0b0..LIN break detect is disabled, normal break character can be detected.
 *  0b1..LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1).
 */
#define LPUART_STAT_LBKDE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)

#define LPUART_STAT_BRK13_MASK                   (0x4000000U)
#define LPUART_STAT_BRK13_SHIFT                  (26U)
/*! BRK13 - Break Character Generation Length
 *  0b0..Break character is transmitted with length of 9 to 13 bit times.
 *  0b1..Break character is transmitted with length of 12 to 15 bit times.
 */
#define LPUART_STAT_BRK13(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)

#define LPUART_STAT_RWUID_MASK                   (0x8000000U)
#define LPUART_STAT_RWUID_SHIFT                  (27U)
/*! RWUID - Receive Wake Up Idle Detect
 *  0b0..During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle
 *       character. During address match wakeup, the IDLE bit does not set when an address does not match.
 *  0b1..During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During
 *       address match wakeup, the IDLE bit does set when an address does not match.
 */
#define LPUART_STAT_RWUID(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)

#define LPUART_STAT_RXINV_MASK                   (0x10000000U)
#define LPUART_STAT_RXINV_SHIFT                  (28U)
/*! RXINV - Receive Data Inversion
 *  0b0..Receive data not inverted.
 *  0b1..Receive data inverted.
 */
#define LPUART_STAT_RXINV(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)

#define LPUART_STAT_MSBF_MASK                    (0x20000000U)
#define LPUART_STAT_MSBF_SHIFT                   (29U)
/*! MSBF - MSB First
 *  0b0..LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received
 *       after the start bit is identified as bit0.
 *  0b1..MSB (identified as bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit
 *       depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. .
 */
#define LPUART_STAT_MSBF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)

#define LPUART_STAT_RXEDGIF_MASK                 (0x40000000U)
#define LPUART_STAT_RXEDGIF_SHIFT                (30U)
/*! RXEDGIF - RXD Pin Active Edge Interrupt Flag
 *  0b0..No active edge on the receive pin has occurred.
 *  0b1..An active edge on the receive pin has occurred.
 */
#define LPUART_STAT_RXEDGIF(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)

#define LPUART_STAT_LBKDIF_MASK                  (0x80000000U)
#define LPUART_STAT_LBKDIF_SHIFT                 (31U)
/*! LBKDIF - LIN Break Detect Interrupt Flag
 *  0b0..No LIN break character has been detected.
 *  0b1..LIN break character has been detected.
 */
#define LPUART_STAT_LBKDIF(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)
/*! @} */

/*! @name CTRL - LPUART Control Register */
/*! @{ */

#define LPUART_CTRL_PT_MASK                      (0x1U)
#define LPUART_CTRL_PT_SHIFT                     (0U)
/*! PT - Parity Type
 *  0b0..Even parity.
 *  0b1..Odd parity.
 */
#define LPUART_CTRL_PT(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)

#define LPUART_CTRL_PE_MASK                      (0x2U)
#define LPUART_CTRL_PE_SHIFT                     (1U)
/*! PE - Parity Enable
 *  0b0..No hardware parity generation or checking.
 *  0b1..Parity enabled.
 */
#define LPUART_CTRL_PE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)

#define LPUART_CTRL_ILT_MASK                     (0x4U)
#define LPUART_CTRL_ILT_SHIFT                    (2U)
/*! ILT - Idle Line Type Select
 *  0b0..Idle character bit count starts after start bit.
 *  0b1..Idle character bit count starts after stop bit.
 */
#define LPUART_CTRL_ILT(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)

#define LPUART_CTRL_WAKE_MASK                    (0x8U)
#define LPUART_CTRL_WAKE_SHIFT                   (3U)
/*! WAKE - Receiver Wakeup Method Select
 *  0b0..Configures RWU for idle-line wakeup.
 *  0b1..Configures RWU with address-mark wakeup.
 */
#define LPUART_CTRL_WAKE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)

#define LPUART_CTRL_M_MASK                       (0x10U)
#define LPUART_CTRL_M_SHIFT                      (4U)
/*! M - 9-Bit or 8-Bit Mode Select
 *  0b0..Receiver and transmitter use 8-bit data characters.
 *  0b1..Receiver and transmitter use 9-bit data characters.
 */
#define LPUART_CTRL_M(x)                         (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)

#define LPUART_CTRL_RSRC_MASK                    (0x20U)
#define LPUART_CTRL_RSRC_SHIFT                   (5U)
/*! RSRC - Receiver Source Select
 *  0b0..Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the RXD pin.
 *  0b1..Single-wire LPUART mode where the TXD pin is connected to the transmitter output and receiver input.
 */
#define LPUART_CTRL_RSRC(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)

#define LPUART_CTRL_DOZEEN_MASK                  (0x40U)
#define LPUART_CTRL_DOZEEN_SHIFT                 (6U)
/*! DOZEEN - Doze Enable
 *  0b0..LPUART is enabled in Doze mode.
 *  0b1..LPUART is disabled in Doze mode , but remains active when not in Doze mode .
 */
#define LPUART_CTRL_DOZEEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)

#define LPUART_CTRL_LOOPS_MASK                   (0x80U)
#define LPUART_CTRL_LOOPS_SHIFT                  (7U)
/*! LOOPS - Loop Mode Select
 *  0b0..Normal operation - RXD and TXD use separate pins.
 *  0b1..Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit).
 */
#define LPUART_CTRL_LOOPS(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)

#define LPUART_CTRL_IDLECFG_MASK                 (0x700U)
#define LPUART_CTRL_IDLECFG_SHIFT                (8U)
/*! IDLECFG - Idle Configuration
 *  0b000..1 idle character
 *  0b001..2 idle characters
 *  0b010..4 idle characters
 *  0b011..8 idle characters
 *  0b100..16 idle characters
 *  0b101..32 idle characters
 *  0b110..64 idle characters
 *  0b111..128 idle characters
 */
#define LPUART_CTRL_IDLECFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)

#define LPUART_CTRL_M7_MASK                      (0x800U)
#define LPUART_CTRL_M7_SHIFT                     (11U)
/*! M7 - 7-Bit Mode Select
 *  0b0..Receiver and transmitter use 8-bit to 10-bit data characters.
 *  0b1..Receiver and transmitter use 7-bit data characters.
 */
#define LPUART_CTRL_M7(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK)

#define LPUART_CTRL_MA2IE_MASK                   (0x4000U)
#define LPUART_CTRL_MA2IE_SHIFT                  (14U)
/*! MA2IE - Match 2 Interrupt Enable
 *  0b0..MA2F interrupt disabled
 *  0b1..MA2F interrupt enabled
 */
#define LPUART_CTRL_MA2IE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)

#define LPUART_CTRL_MA1IE_MASK                   (0x8000U)
#define LPUART_CTRL_MA1IE_SHIFT                  (15U)
/*! MA1IE - Match 1 Interrupt Enable
 *  0b0..MA1F interrupt disabled
 *  0b1..MA1F interrupt enabled
 */
#define LPUART_CTRL_MA1IE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)

#define LPUART_CTRL_SBK_MASK                     (0x10000U)
#define LPUART_CTRL_SBK_SHIFT                    (16U)
/*! SBK - Send Break
 *  0b0..Normal transmitter operation.
 *  0b1..Queue break character(s) to be sent.
 */
#define LPUART_CTRL_SBK(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)

#define LPUART_CTRL_RWU_MASK                     (0x20000U)
#define LPUART_CTRL_RWU_SHIFT                    (17U)
/*! RWU - Receiver Wakeup Control
 *  0b0..Normal receiver operation.
 *  0b1..LPUART receiver in standby waiting for wakeup condition.
 */
#define LPUART_CTRL_RWU(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)

#define LPUART_CTRL_RE_MASK                      (0x40000U)
#define LPUART_CTRL_RE_SHIFT                     (18U)
/*! RE - Receiver Enable
 *  0b0..Receiver disabled.
 *  0b1..Receiver enabled.
 */
#define LPUART_CTRL_RE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)

#define LPUART_CTRL_TE_MASK                      (0x80000U)
#define LPUART_CTRL_TE_SHIFT                     (19U)
/*! TE - Transmitter Enable
 *  0b0..Transmitter disabled.
 *  0b1..Transmitter enabled.
 */
#define LPUART_CTRL_TE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)

#define LPUART_CTRL_ILIE_MASK                    (0x100000U)
#define LPUART_CTRL_ILIE_SHIFT                   (20U)
/*! ILIE - Idle Line Interrupt Enable
 *  0b0..Hardware interrupts from IDLE disabled; use polling.
 *  0b1..Hardware interrupt is requested when IDLE flag is 1.
 */
#define LPUART_CTRL_ILIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)

#define LPUART_CTRL_RIE_MASK                     (0x200000U)
#define LPUART_CTRL_RIE_SHIFT                    (21U)
/*! RIE - Receiver Interrupt Enable
 *  0b0..Hardware interrupts from RDRF disabled.
 *  0b1..Hardware interrupt is requested when RDRF flag is 1.
 */
#define LPUART_CTRL_RIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)

#define LPUART_CTRL_TCIE_MASK                    (0x400000U)
#define LPUART_CTRL_TCIE_SHIFT                   (22U)
/*! TCIE - Transmission Complete Interrupt Enable for
 *  0b0..Hardware interrupts from TC disabled.
 *  0b1..Hardware interrupt is requested when TC flag is 1.
 */
#define LPUART_CTRL_TCIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)

#define LPUART_CTRL_TIE_MASK                     (0x800000U)
#define LPUART_CTRL_TIE_SHIFT                    (23U)
/*! TIE - Transmit Interrupt Enable
 *  0b0..Hardware interrupts from TDRE disabled.
 *  0b1..Hardware interrupt is requested when TDRE flag is 1.
 */
#define LPUART_CTRL_TIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)

#define LPUART_CTRL_PEIE_MASK                    (0x1000000U)
#define LPUART_CTRL_PEIE_SHIFT                   (24U)
/*! PEIE - Parity Error Interrupt Enable
 *  0b0..PF interrupts disabled; use polling).
 *  0b1..Hardware interrupt is requested when PF is set.
 */
#define LPUART_CTRL_PEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)

#define LPUART_CTRL_FEIE_MASK                    (0x2000000U)
#define LPUART_CTRL_FEIE_SHIFT                   (25U)
/*! FEIE - Framing Error Interrupt Enable
 *  0b0..FE interrupts disabled; use polling.
 *  0b1..Hardware interrupt is requested when FE is set.
 */
#define LPUART_CTRL_FEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)

#define LPUART_CTRL_NEIE_MASK                    (0x4000000U)
#define LPUART_CTRL_NEIE_SHIFT                   (26U)
/*! NEIE - Noise Error Interrupt Enable
 *  0b0..NF interrupts disabled; use polling.
 *  0b1..Hardware interrupt is requested when NF is set.
 */
#define LPUART_CTRL_NEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)

#define LPUART_CTRL_ORIE_MASK                    (0x8000000U)
#define LPUART_CTRL_ORIE_SHIFT                   (27U)
/*! ORIE - Overrun Interrupt Enable
 *  0b0..OR interrupts disabled; use polling.
 *  0b1..Hardware interrupt is requested when OR is set.
 */
#define LPUART_CTRL_ORIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)

#define LPUART_CTRL_TXINV_MASK                   (0x10000000U)
#define LPUART_CTRL_TXINV_SHIFT                  (28U)
/*! TXINV - Transmit Data Inversion
 *  0b0..Transmit data not inverted.
 *  0b1..Transmit data inverted.
 */
#define LPUART_CTRL_TXINV(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)

#define LPUART_CTRL_TXDIR_MASK                   (0x20000000U)
#define LPUART_CTRL_TXDIR_SHIFT                  (29U)
/*! TXDIR - TXD Pin Direction in Single-Wire Mode
 *  0b0..TXD pin is an input in single-wire mode.
 *  0b1..TXD pin is an output in single-wire mode.
 */
#define LPUART_CTRL_TXDIR(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)

#define LPUART_CTRL_R9T8_MASK                    (0x40000000U)
#define LPUART_CTRL_R9T8_SHIFT                   (30U)
/*! R9T8 - Receive Bit 9 / Transmit Bit 8
 */
#define LPUART_CTRL_R9T8(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)

#define LPUART_CTRL_R8T9_MASK                    (0x80000000U)
#define LPUART_CTRL_R8T9_SHIFT                   (31U)
/*! R8T9 - Receive Bit 8 / Transmit Bit 9
 */
#define LPUART_CTRL_R8T9(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)
/*! @} */

/*! @name DATA - LPUART Data Register */
/*! @{ */

#define LPUART_DATA_R0T0_MASK                    (0x1U)
#define LPUART_DATA_R0T0_SHIFT                   (0U)
/*! R0T0 - R0T0
 */
#define LPUART_DATA_R0T0(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)

#define LPUART_DATA_R1T1_MASK                    (0x2U)
#define LPUART_DATA_R1T1_SHIFT                   (1U)
/*! R1T1 - R1T1
 */
#define LPUART_DATA_R1T1(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)

#define LPUART_DATA_R2T2_MASK                    (0x4U)
#define LPUART_DATA_R2T2_SHIFT                   (2U)
/*! R2T2 - R2T2
 */
#define LPUART_DATA_R2T2(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)

#define LPUART_DATA_R3T3_MASK                    (0x8U)
#define LPUART_DATA_R3T3_SHIFT                   (3U)
/*! R3T3 - R3T3
 */
#define LPUART_DATA_R3T3(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)

#define LPUART_DATA_R4T4_MASK                    (0x10U)
#define LPUART_DATA_R4T4_SHIFT                   (4U)
/*! R4T4 - R4T4
 */
#define LPUART_DATA_R4T4(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)

#define LPUART_DATA_R5T5_MASK                    (0x20U)
#define LPUART_DATA_R5T5_SHIFT                   (5U)
/*! R5T5 - R5T5
 */
#define LPUART_DATA_R5T5(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)

#define LPUART_DATA_R6T6_MASK                    (0x40U)
#define LPUART_DATA_R6T6_SHIFT                   (6U)
/*! R6T6 - R6T6
 */
#define LPUART_DATA_R6T6(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)

#define LPUART_DATA_R7T7_MASK                    (0x80U)
#define LPUART_DATA_R7T7_SHIFT                   (7U)
/*! R7T7 - R7T7
 */
#define LPUART_DATA_R7T7(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)

#define LPUART_DATA_R8T8_MASK                    (0x100U)
#define LPUART_DATA_R8T8_SHIFT                   (8U)
/*! R8T8 - R8T8
 */
#define LPUART_DATA_R8T8(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)

#define LPUART_DATA_R9T9_MASK                    (0x200U)
#define LPUART_DATA_R9T9_SHIFT                   (9U)
/*! R9T9 - R9T9
 */
#define LPUART_DATA_R9T9(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)

#define LPUART_DATA_LINBRK_MASK                  (0x400U)
#define LPUART_DATA_LINBRK_SHIFT                 (10U)
/*! LINBRK - LIN Break
 *  0b0..Receiver did not detect LIN break before this character, or LIN break detect circuitry disabled.
 *  0b1..Receiver detected a LIN break before receiving this character.
 */
#define LPUART_DATA_LINBRK(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_LINBRK_SHIFT)) & LPUART_DATA_LINBRK_MASK)

#define LPUART_DATA_IDLINE_MASK                  (0x800U)
#define LPUART_DATA_IDLINE_SHIFT                 (11U)
/*! IDLINE - Idle Line
 *  0b0..Receiver was not idle before receiving this character.
 *  0b1..Receiver was idle before receiving this character.
 */
#define LPUART_DATA_IDLINE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)

#define LPUART_DATA_RXEMPT_MASK                  (0x1000U)
#define LPUART_DATA_RXEMPT_SHIFT                 (12U)
/*! RXEMPT - Receive Buffer Empty
 *  0b0..Receive buffer contains valid data.
 *  0b1..Receive buffer is empty, data returned on read is not valid.
 */
#define LPUART_DATA_RXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)

#define LPUART_DATA_FRETSC_MASK                  (0x2000U)
#define LPUART_DATA_FRETSC_SHIFT                 (13U)
/*! FRETSC - Frame Error / Transmit Special Character
 *  0b0..The dataword is received without a frame error on read, or transmit a normal character on write.
 *  0b1..The dataword is received with a frame error, or transmit an idle or break character on transmit.
 */
#define LPUART_DATA_FRETSC(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)

#define LPUART_DATA_PARITYE_MASK                 (0x4000U)
#define LPUART_DATA_PARITYE_SHIFT                (14U)
/*! PARITYE - Parity Error
 *  0b0..The dataword is received without a parity error.
 *  0b1..The dataword is received with a parity error.
 */
#define LPUART_DATA_PARITYE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)

#define LPUART_DATA_NOISY_MASK                   (0x8000U)
#define LPUART_DATA_NOISY_SHIFT                  (15U)
/*! NOISY - Noisy Data Received
 *  0b0..The dataword is received without noise.
 *  0b1..The data is received with noise.
 */
#define LPUART_DATA_NOISY(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)
/*! @} */

/*! @name MATCH - LPUART Match Address Register */
/*! @{ */

#define LPUART_MATCH_MA1_MASK                    (0x3FFU)
#define LPUART_MATCH_MA1_SHIFT                   (0U)
/*! MA1 - Match Address 1
 */
#define LPUART_MATCH_MA1(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)

#define LPUART_MATCH_MA2_MASK                    (0x3FF0000U)
#define LPUART_MATCH_MA2_SHIFT                   (16U)
/*! MA2 - Match Address 2
 */
#define LPUART_MATCH_MA2(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)
/*! @} */

/*! @name MODIR - LPUART Modem IrDA Register */
/*! @{ */

#define LPUART_MODIR_TXCTSE_MASK                 (0x1U)
#define LPUART_MODIR_TXCTSE_SHIFT                (0U)
/*! TXCTSE - Transmitter clear-to-send enable
 *  0b0..CTS has no effect on the transmitter.
 *  0b1..Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a
 *       character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the
 *       mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent
 *       do not affect its transmission.
 */
#define LPUART_MODIR_TXCTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)

#define LPUART_MODIR_TXRTSE_MASK                 (0x2U)
#define LPUART_MODIR_TXRTSE_SHIFT                (1U)
/*! TXRTSE - Transmitter request-to-send enable
 *  0b0..The transmitter has no effect on RTS.
 *  0b1..When a character is placed into an empty transmit shift register, RTS asserts one bit time before the
 *       start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter FIFO and shift
 *       register are completely sent, including the last stop bit.
 */
#define LPUART_MODIR_TXRTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)

#define LPUART_MODIR_TXRTSPOL_MASK               (0x4U)
#define LPUART_MODIR_TXRTSPOL_SHIFT              (2U)
/*! TXRTSPOL - Transmitter request-to-send polarity
 *  0b0..Transmitter RTS is active low.
 *  0b1..Transmitter RTS is active high.
 */
#define LPUART_MODIR_TXRTSPOL(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)

#define LPUART_MODIR_RXRTSE_MASK                 (0x8U)
#define LPUART_MODIR_RXRTSE_SHIFT                (3U)
/*! RXRTSE - Receiver request-to-send enable
 *  0b0..The receiver has no effect on RTS.
 *  0b1..RTS is deasserted if the receiver data register is full or a start bit has been detected that would cause
 *       the receiver data register to become full. RTS is asserted if the receiver data register is not full and
 *       has not detected a start bit that would cause the receiver data register to become full.
 */
#define LPUART_MODIR_RXRTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)

#define LPUART_MODIR_TXCTSC_MASK                 (0x10U)
#define LPUART_MODIR_TXCTSC_SHIFT                (4U)
/*! TXCTSC - Transmit CTS Configuration
 *  0b0..CTS input is sampled at the start of each character.
 *  0b1..CTS input is sampled when the transmitter is idle.
 */
#define LPUART_MODIR_TXCTSC(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)

#define LPUART_MODIR_TXCTSSRC_MASK               (0x20U)
#define LPUART_MODIR_TXCTSSRC_SHIFT              (5U)
/*! TXCTSSRC - Transmit CTS Source
 *  0b0..CTS input is the CTS_B pin.
 *  0b1..CTS input is an internal connection to the receiver address match result.
 */
#define LPUART_MODIR_TXCTSSRC(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)

#define LPUART_MODIR_RTSWATER_MASK               (0x700U)
#define LPUART_MODIR_RTSWATER_SHIFT              (8U)
/*! RTSWATER - Receive RTS Configuration
 */
#define LPUART_MODIR_RTSWATER(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK)

#define LPUART_MODIR_TNP_MASK                    (0x30000U)
#define LPUART_MODIR_TNP_SHIFT                   (16U)
/*! TNP - Transmitter narrow pulse
 *  0b00..1/OSR.
 *  0b01..2/OSR.
 *  0b10..3/OSR.
 *  0b11..4/OSR.
 */
#define LPUART_MODIR_TNP(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)

#define LPUART_MODIR_IREN_MASK                   (0x40000U)
#define LPUART_MODIR_IREN_SHIFT                  (18U)
/*! IREN - Infrared enable
 *  0b0..IR disabled.
 *  0b1..IR enabled.
 */
#define LPUART_MODIR_IREN(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)
/*! @} */

/*! @name FIFO - LPUART FIFO Register */
/*! @{ */

#define LPUART_FIFO_RXFIFOSIZE_MASK              (0x7U)
#define LPUART_FIFO_RXFIFOSIZE_SHIFT             (0U)
/*! RXFIFOSIZE - Receive FIFO Buffer Depth
 *  0b000..Receive FIFO/Buffer depth = 1 dataword.
 *  0b001..Receive FIFO/Buffer depth = 4 datawords.
 *  0b010..Receive FIFO/Buffer depth = 8 datawords.
 *  0b011..Receive FIFO/Buffer depth = 16 datawords.
 *  0b100..Receive FIFO/Buffer depth = 32 datawords.
 *  0b101..Receive FIFO/Buffer depth = 64 datawords.
 *  0b110..Receive FIFO/Buffer depth = 128 datawords.
 *  0b111..Receive FIFO/Buffer depth = 256 datawords.
 */
#define LPUART_FIFO_RXFIFOSIZE(x)                (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK)

#define LPUART_FIFO_RXFE_MASK                    (0x8U)
#define LPUART_FIFO_RXFE_SHIFT                   (3U)
/*! RXFE - Receive FIFO Enable
 *  0b0..Receive FIFO is not enabled. Buffer depth is 1.
 *  0b1..Receive FIFO is enabled. Buffer depth is indicted by RXFIFOSIZE.
 */
#define LPUART_FIFO_RXFE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK)

#define LPUART_FIFO_TXFIFOSIZE_MASK              (0x70U)
#define LPUART_FIFO_TXFIFOSIZE_SHIFT             (4U)
/*! TXFIFOSIZE - Transmit FIFO Buffer Depth
 *  0b000..Transmit FIFO/Buffer depth = 1 dataword.
 *  0b001..Transmit FIFO/Buffer depth = 4 datawords.
 *  0b010..Transmit FIFO/Buffer depth = 8 datawords.
 *  0b011..Transmit FIFO/Buffer depth = 16 datawords.
 *  0b100..Transmit FIFO/Buffer depth = 32 datawords.
 *  0b101..Transmit FIFO/Buffer depth = 64 datawords.
 *  0b110..Transmit FIFO/Buffer depth = 128 datawords.
 *  0b111..Transmit FIFO/Buffer depth = 256 datawords
 */
#define LPUART_FIFO_TXFIFOSIZE(x)                (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK)

#define LPUART_FIFO_TXFE_MASK                    (0x80U)
#define LPUART_FIFO_TXFE_SHIFT                   (7U)
/*! TXFE - Transmit FIFO Enable
 *  0b0..Transmit FIFO is not enabled. Buffer depth is 1.
 *  0b1..Transmit FIFO is enabled. Buffer depth is indicated by TXFIFOSIZE.
 */
#define LPUART_FIFO_TXFE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK)

#define LPUART_FIFO_RXUFE_MASK                   (0x100U)
#define LPUART_FIFO_RXUFE_SHIFT                  (8U)
/*! RXUFE - Receive FIFO Underflow Interrupt Enable
 *  0b0..RXUF flag does not generate an interrupt to the host.
 *  0b1..RXUF flag generates an interrupt to the host.
 */
#define LPUART_FIFO_RXUFE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK)

#define LPUART_FIFO_TXOFE_MASK                   (0x200U)
#define LPUART_FIFO_TXOFE_SHIFT                  (9U)
/*! TXOFE - Transmit FIFO Overflow Interrupt Enable
 *  0b0..TXOF flag does not generate an interrupt to the host.
 *  0b1..TXOF flag generates an interrupt to the host.
 */
#define LPUART_FIFO_TXOFE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK)

#define LPUART_FIFO_RXIDEN_MASK                  (0x1C00U)
#define LPUART_FIFO_RXIDEN_SHIFT                 (10U)
/*! RXIDEN - Receiver Idle Empty Enable
 *  0b000..Disable RDRF assertion due to partially filled FIFO when receiver is idle.
 *  0b001..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character.
 *  0b010..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters.
 *  0b011..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters.
 *  0b100..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters.
 *  0b101..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters.
 *  0b110..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters.
 *  0b111..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters.
 */
#define LPUART_FIFO_RXIDEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK)

#define LPUART_FIFO_RXFLUSH_MASK                 (0x4000U)
#define LPUART_FIFO_RXFLUSH_SHIFT                (14U)
/*! RXFLUSH - Receive FIFO Flush
 *  0b0..No flush operation occurs.
 *  0b1..All data in the receive FIFO/buffer is cleared out.
 */
#define LPUART_FIFO_RXFLUSH(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK)

#define LPUART_FIFO_TXFLUSH_MASK                 (0x8000U)
#define LPUART_FIFO_TXFLUSH_SHIFT                (15U)
/*! TXFLUSH - Transmit FIFO Flush
 *  0b0..No flush operation occurs.
 *  0b1..All data in the transmit FIFO is cleared out.
 */
#define LPUART_FIFO_TXFLUSH(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK)

#define LPUART_FIFO_RXUF_MASK                    (0x10000U)
#define LPUART_FIFO_RXUF_SHIFT                   (16U)
/*! RXUF - Receiver FIFO Underflow Flag
 *  0b0..No receive FIFO underflow has occurred since the last time the flag was cleared.
 *  0b1..At least one receive FIFO underflow has occurred since the last time the flag was cleared.
 */
#define LPUART_FIFO_RXUF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK)

#define LPUART_FIFO_TXOF_MASK                    (0x20000U)
#define LPUART_FIFO_TXOF_SHIFT                   (17U)
/*! TXOF - Transmitter FIFO Overflow Flag
 *  0b0..No transmit FIFO overflow has occurred since the last time the flag was cleared.
 *  0b1..At least one transmit FIFO overflow has occurred since the last time the flag was cleared.
 */
#define LPUART_FIFO_TXOF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK)

#define LPUART_FIFO_RXEMPT_MASK                  (0x400000U)
#define LPUART_FIFO_RXEMPT_SHIFT                 (22U)
/*! RXEMPT - Receive FIFO/Buffer Empty
 *  0b0..Receive buffer is not empty.
 *  0b1..Receive buffer is empty.
 */
#define LPUART_FIFO_RXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK)

#define LPUART_FIFO_TXEMPT_MASK                  (0x800000U)
#define LPUART_FIFO_TXEMPT_SHIFT                 (23U)
/*! TXEMPT - Transmit FIFO/Buffer Empty
 *  0b0..Transmit buffer is not empty.
 *  0b1..Transmit buffer is empty.
 */
#define LPUART_FIFO_TXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK)
/*! @} */

/*! @name WATER - LPUART Watermark Register */
/*! @{ */

#define LPUART_WATER_TXWATER_MASK                (0x7U)
#define LPUART_WATER_TXWATER_SHIFT               (0U)
/*! TXWATER - Transmit Watermark
 */
#define LPUART_WATER_TXWATER(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK)

#define LPUART_WATER_TXCOUNT_MASK                (0xF00U)
#define LPUART_WATER_TXCOUNT_SHIFT               (8U)
/*! TXCOUNT - Transmit Counter
 */
#define LPUART_WATER_TXCOUNT(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK)

#define LPUART_WATER_RXWATER_MASK                (0x70000U)
#define LPUART_WATER_RXWATER_SHIFT               (16U)
/*! RXWATER - Receive Watermark
 */
#define LPUART_WATER_RXWATER(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK)

#define LPUART_WATER_RXCOUNT_MASK                (0xF000000U)
#define LPUART_WATER_RXCOUNT_SHIFT               (24U)
/*! RXCOUNT - Receive Counter
 */
#define LPUART_WATER_RXCOUNT(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK)
/*! @} */

/*! @name DATARO - Data read-only Register */
/*! @{ */

#define LPUART_DATARO_DATA_MASK                  (0xFFFFU)
#define LPUART_DATARO_DATA_SHIFT                 (0U)
/*! DATA - Receive Data
 */
#define LPUART_DATARO_DATA(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATARO_DATA_SHIFT)) & LPUART_DATARO_DATA_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LPUART_Register_Masks */


/* LPUART - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral LPUART0 base address */
  #define LPUART0_BASE                             (0x50038000u)
  /** Peripheral LPUART0 base address */
  #define LPUART0_BASE_NS                          (0x40038000u)
  /** Peripheral LPUART0 base pointer */
  #define LPUART0                                  ((LPUART_Type *)LPUART0_BASE)
  /** Peripheral LPUART0 base pointer */
  #define LPUART0_NS                               ((LPUART_Type *)LPUART0_BASE_NS)
  /** Peripheral LPUART1 base address */
  #define LPUART1_BASE                             (0x50039000u)
  /** Peripheral LPUART1 base address */
  #define LPUART1_BASE_NS                          (0x40039000u)
  /** Peripheral LPUART1 base pointer */
  #define LPUART1                                  ((LPUART_Type *)LPUART1_BASE)
  /** Peripheral LPUART1 base pointer */
  #define LPUART1_NS                               ((LPUART_Type *)LPUART1_BASE_NS)
  /** Array initializer of LPUART peripheral base addresses */
  #define LPUART_BASE_ADDRS                        { LPUART0_BASE, LPUART1_BASE }
  /** Array initializer of LPUART peripheral base pointers */
  #define LPUART_BASE_PTRS                         { LPUART0, LPUART1 }
  /** Array initializer of LPUART peripheral base addresses */
  #define LPUART_BASE_ADDRS_NS                     { LPUART0_BASE_NS, LPUART1_BASE_NS }
  /** Array initializer of LPUART peripheral base pointers */
  #define LPUART_BASE_PTRS_NS                      { LPUART0_NS, LPUART1_NS }
#else
  /** Peripheral LPUART0 base address */
  #define LPUART0_BASE                             (0x40038000u)
  /** Peripheral LPUART0 base pointer */
  #define LPUART0                                  ((LPUART_Type *)LPUART0_BASE)
  /** Peripheral LPUART1 base address */
  #define LPUART1_BASE                             (0x40039000u)
  /** Peripheral LPUART1 base pointer */
  #define LPUART1                                  ((LPUART_Type *)LPUART1_BASE)
  /** Array initializer of LPUART peripheral base addresses */
  #define LPUART_BASE_ADDRS                        { LPUART0_BASE, LPUART1_BASE }
  /** Array initializer of LPUART peripheral base pointers */
  #define LPUART_BASE_PTRS                         { LPUART0, LPUART1 }
#endif
/** Interrupt vectors for the LPUART peripheral type */
#define LPUART_RX_TX_IRQS                        { LPUART0_IRQn, LPUART1_IRQn }
#define LPUART_ERR_IRQS                          { LPUART0_IRQn, LPUART1_IRQn }

/*!
 * @}
 */ /* end of group LPUART_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LTC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LTC_Peripheral_Access_Layer LTC Peripheral Access Layer
 * @{
 */

/** LTC - Register Layout Typedef */
typedef struct {
  __IO uint32_t MD;                                /**< Mode Register, offset: 0x0 */
       uint8_t RESERVED_0[4];
  __O  uint32_t KS;                                /**< Key Size Register, offset: 0x8 */
       uint8_t RESERVED_1[4];
  __IO uint32_t DS;                                /**< Data Size Register, offset: 0x10 */
       uint8_t RESERVED_2[4];
  __IO uint32_t ICVS;                              /**< ICV Size Register, offset: 0x18 */
       uint8_t RESERVED_3[20];
  __O  uint32_t COM;                               /**< Command Register, offset: 0x30 */
  __IO uint32_t CTL;                               /**< Control Register, offset: 0x34 */
       uint8_t RESERVED_4[8];
  __O  uint32_t CW;                                /**< Clear Written Register, offset: 0x40 */
       uint8_t RESERVED_5[4];
  __IO uint32_t STA;                               /**< Status Register, offset: 0x48 */
  __I  uint32_t ESTA;                              /**< Error Status Register, offset: 0x4C */
       uint8_t RESERVED_6[8];
  __IO uint32_t AADSZ;                             /**< AAD Size Register, offset: 0x58 */
       uint8_t RESERVED_7[164];
  __IO uint32_t CTX[14];                           /**< Context Register, array offset: 0x100, array step: 0x4 */
       uint8_t RESERVED_8[200];
  __IO uint32_t KEY[4];                            /**< Key Registers, array offset: 0x200, array step: 0x4 */
       uint8_t RESERVED_9[736];
  __I  uint32_t VID1;                              /**< Version ID Register, offset: 0x4F0 */
  __I  uint32_t VID2;                              /**< Version ID 2 Register, offset: 0x4F4 */
  __I  uint32_t CHAVID;                            /**< CHA Version ID Register, offset: 0x4F8 */
       uint8_t RESERVED_10[708];
  __I  uint32_t FIFOSTA;                           /**< FIFO Status Register, offset: 0x7C0 */
       uint8_t RESERVED_11[28];
  __O  uint32_t IFIFO;                             /**< Input Data FIFO, offset: 0x7E0 */
       uint8_t RESERVED_12[12];
  __I  uint32_t OFIFO;                             /**< Output Data FIFO, offset: 0x7F0 */
} LTC_Type;

/* ----------------------------------------------------------------------------
   -- LTC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LTC_Register_Masks LTC Register Masks
 * @{
 */

/*! @name MD - Mode Register */
/*! @{ */

#define LTC_MD_ENC_MASK                          (0x1U)
#define LTC_MD_ENC_SHIFT                         (0U)
/*! ENC - Encrypt/Decrypt.
 *  0b0..Decrypt.
 *  0b1..Encrypt.
 */
#define LTC_MD_ENC(x)                            (((uint32_t)(((uint32_t)(x)) << LTC_MD_ENC_SHIFT)) & LTC_MD_ENC_MASK)

#define LTC_MD_ICV_TEST_MASK                     (0x2U)
#define LTC_MD_ICV_TEST_SHIFT                    (1U)
/*! ICV_TEST - ICV Checking / Test AES fault detection.
 */
#define LTC_MD_ICV_TEST(x)                       (((uint32_t)(((uint32_t)(x)) << LTC_MD_ICV_TEST_SHIFT)) & LTC_MD_ICV_TEST_MASK)

#define LTC_MD_AS_MASK                           (0xCU)
#define LTC_MD_AS_SHIFT                          (2U)
/*! AS - Algorithm State
 *  0b00..Update
 *  0b01..Initialize
 *  0b10..Finalize
 *  0b11..Initialize/Finalize
 */
#define LTC_MD_AS(x)                             (((uint32_t)(((uint32_t)(x)) << LTC_MD_AS_SHIFT)) & LTC_MD_AS_MASK)

#define LTC_MD_AAI_MASK                          (0x1FF0U)
#define LTC_MD_AAI_SHIFT                         (4U)
/*! AAI - Additional Algorithm information
 */
#define LTC_MD_AAI(x)                            (((uint32_t)(((uint32_t)(x)) << LTC_MD_AAI_SHIFT)) & LTC_MD_AAI_MASK)

#define LTC_MD_ALG_MASK                          (0xFF0000U)
#define LTC_MD_ALG_SHIFT                         (16U)
/*! ALG - Algorithm
 *  0b00010000..AES
 */
#define LTC_MD_ALG(x)                            (((uint32_t)(((uint32_t)(x)) << LTC_MD_ALG_SHIFT)) & LTC_MD_ALG_MASK)
/*! @} */

/*! @name KS - Key Size Register */
/*! @{ */

#define LTC_KS_KS_MASK                           (0x1FU)
#define LTC_KS_KS_SHIFT                          (0U)
/*! KS - Key Size
 */
#define LTC_KS_KS(x)                             (((uint32_t)(((uint32_t)(x)) << LTC_KS_KS_SHIFT)) & LTC_KS_KS_MASK)
/*! @} */

/*! @name DS - Data Size Register */
/*! @{ */

#define LTC_DS_DS_MASK                           (0xFFFU)
#define LTC_DS_DS_SHIFT                          (0U)
/*! DS - Data Size
 */
#define LTC_DS_DS(x)                             (((uint32_t)(((uint32_t)(x)) << LTC_DS_DS_SHIFT)) & LTC_DS_DS_MASK)
/*! @} */

/*! @name ICVS - ICV Size Register */
/*! @{ */

#define LTC_ICVS_ICVS_MASK                       (0x1FU)
#define LTC_ICVS_ICVS_SHIFT                      (0U)
/*! ICVS - ICV Size, in Bytes
 */
#define LTC_ICVS_ICVS(x)                         (((uint32_t)(((uint32_t)(x)) << LTC_ICVS_ICVS_SHIFT)) & LTC_ICVS_ICVS_MASK)
/*! @} */

/*! @name COM - Command Register */
/*! @{ */

#define LTC_COM_ALL_MASK                         (0x1U)
#define LTC_COM_ALL_SHIFT                        (0U)
/*! ALL - Reset All Internal Logic
 *  0b0..Do Not Reset
 *  0b1..Reset all CHAs in use by this CCB.
 */
#define LTC_COM_ALL(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_COM_ALL_SHIFT)) & LTC_COM_ALL_MASK)

#define LTC_COM_AES_MASK                         (0x2U)
#define LTC_COM_AES_SHIFT                        (1U)
/*! AES - Reset AESA
 *  0b0..Do Not Reset
 *  0b1..Reset AES Accelerator
 */
#define LTC_COM_AES(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_COM_AES_SHIFT)) & LTC_COM_AES_MASK)
/*! @} */

/*! @name CTL - Control Register */
/*! @{ */

#define LTC_CTL_IM_MASK                          (0x1U)
#define LTC_CTL_IM_SHIFT                         (0U)
/*! IM - Interrupt Mask
 *  0b0..Interrupt not masked.
 *  0b1..Interrupt masked
 */
#define LTC_CTL_IM(x)                            (((uint32_t)(((uint32_t)(x)) << LTC_CTL_IM_SHIFT)) & LTC_CTL_IM_MASK)

#define LTC_CTL_IFE_MASK                         (0x100U)
#define LTC_CTL_IFE_SHIFT                        (8U)
/*! IFE - Input FIFO DMA Enable
 *  0b0..DMA Request and Done signals disabled for the Input FIFO.
 *  0b1..DMA Request and Done signals enabled for the Input FIFO.
 */
#define LTC_CTL_IFE(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_CTL_IFE_SHIFT)) & LTC_CTL_IFE_MASK)

#define LTC_CTL_IFR_MASK                         (0x200U)
#define LTC_CTL_IFR_SHIFT                        (9U)
/*! IFR - Input FIFO DMA Request Size
 *  0b0..DMA request size is 1 entry.
 *  0b1..DMA request size is 4 entries.
 */
#define LTC_CTL_IFR(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_CTL_IFR_SHIFT)) & LTC_CTL_IFR_MASK)

#define LTC_CTL_OFE_MASK                         (0x1000U)
#define LTC_CTL_OFE_SHIFT                        (12U)
/*! OFE - Output FIFO DMA Enable
 *  0b0..DMA Request and Done signals disabled for the Output FIFO.
 *  0b1..DMA Request and Done signals enabled for the Output FIFO.
 */
#define LTC_CTL_OFE(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_CTL_OFE_SHIFT)) & LTC_CTL_OFE_MASK)

#define LTC_CTL_OFR_MASK                         (0x2000U)
#define LTC_CTL_OFR_SHIFT                        (13U)
/*! OFR - Output FIFO DMA Request Size
 *  0b0..DMA request size is 1 entry.
 *  0b1..DMA request size is 4 entries.
 */
#define LTC_CTL_OFR(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_CTL_OFR_SHIFT)) & LTC_CTL_OFR_MASK)

#define LTC_CTL_IFS_MASK                         (0x10000U)
#define LTC_CTL_IFS_SHIFT                        (16U)
/*! IFS - Input FIFO Byte Swap
 *  0b0..Do Not Byte Swap Data.
 *  0b1..Byte Swap Data.
 */
#define LTC_CTL_IFS(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_CTL_IFS_SHIFT)) & LTC_CTL_IFS_MASK)

#define LTC_CTL_OFS_MASK                         (0x20000U)
#define LTC_CTL_OFS_SHIFT                        (17U)
/*! OFS - Output FIFO Byte Swap
 *  0b0..Do Not Byte Swap Data.
 *  0b1..Byte Swap Data.
 */
#define LTC_CTL_OFS(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_CTL_OFS_SHIFT)) & LTC_CTL_OFS_MASK)

#define LTC_CTL_KIS_MASK                         (0x100000U)
#define LTC_CTL_KIS_SHIFT                        (20U)
/*! KIS - Key Register Input Byte Swap
 *  0b0..Do Not Byte Swap Data.
 *  0b1..Byte Swap Data.
 */
#define LTC_CTL_KIS(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_CTL_KIS_SHIFT)) & LTC_CTL_KIS_MASK)

#define LTC_CTL_KOS_MASK                         (0x200000U)
#define LTC_CTL_KOS_SHIFT                        (21U)
/*! KOS - Key Register Output Byte Swap
 *  0b0..Do Not Byte Swap Data.
 *  0b1..Byte Swap Data.
 */
#define LTC_CTL_KOS(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_CTL_KOS_SHIFT)) & LTC_CTL_KOS_MASK)

#define LTC_CTL_CIS_MASK                         (0x400000U)
#define LTC_CTL_CIS_SHIFT                        (22U)
/*! CIS - Context Register Input Byte Swap
 *  0b0..Do Not Byte Swap Data.
 *  0b1..Byte Swap Data.
 */
#define LTC_CTL_CIS(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_CTL_CIS_SHIFT)) & LTC_CTL_CIS_MASK)

#define LTC_CTL_COS_MASK                         (0x800000U)
#define LTC_CTL_COS_SHIFT                        (23U)
/*! COS - Context Register Output Byte Swap
 *  0b0..Do Not Byte Swap Data.
 *  0b1..Byte Swap Data.
 */
#define LTC_CTL_COS(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_CTL_COS_SHIFT)) & LTC_CTL_COS_MASK)

#define LTC_CTL_KAL_MASK                         (0x80000000U)
#define LTC_CTL_KAL_SHIFT                        (31U)
/*! KAL - Key Register Access Lock
 *  0b0..Key Register is readable.
 *  0b1..Key Register is not readable.
 */
#define LTC_CTL_KAL(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_CTL_KAL_SHIFT)) & LTC_CTL_KAL_MASK)
/*! @} */

/*! @name CW - Clear Written Register */
/*! @{ */

#define LTC_CW_CM_MASK                           (0x1U)
#define LTC_CW_CM_SHIFT                          (0U)
/*! CM - Clear the Mode Register
 */
#define LTC_CW_CM(x)                             (((uint32_t)(((uint32_t)(x)) << LTC_CW_CM_SHIFT)) & LTC_CW_CM_MASK)

#define LTC_CW_CDS_MASK                          (0x4U)
#define LTC_CW_CDS_SHIFT                         (2U)
/*! CDS - Clear the Data Size Register
 */
#define LTC_CW_CDS(x)                            (((uint32_t)(((uint32_t)(x)) << LTC_CW_CDS_SHIFT)) & LTC_CW_CDS_MASK)

#define LTC_CW_CICV_MASK                         (0x8U)
#define LTC_CW_CICV_SHIFT                        (3U)
/*! CICV - Clear the ICV Size Register
 */
#define LTC_CW_CICV(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_CW_CICV_SHIFT)) & LTC_CW_CICV_MASK)

#define LTC_CW_CCR_MASK                          (0x20U)
#define LTC_CW_CCR_SHIFT                         (5U)
/*! CCR - Clear the Context Register
 */
#define LTC_CW_CCR(x)                            (((uint32_t)(((uint32_t)(x)) << LTC_CW_CCR_SHIFT)) & LTC_CW_CCR_MASK)

#define LTC_CW_CKR_MASK                          (0x40U)
#define LTC_CW_CKR_SHIFT                         (6U)
/*! CKR - Clear the Key Register
 */
#define LTC_CW_CKR(x)                            (((uint32_t)(((uint32_t)(x)) << LTC_CW_CKR_SHIFT)) & LTC_CW_CKR_MASK)

#define LTC_CW_COF_MASK                          (0x40000000U)
#define LTC_CW_COF_SHIFT                         (30U)
/*! COF - Clear Output FIFO
 */
#define LTC_CW_COF(x)                            (((uint32_t)(((uint32_t)(x)) << LTC_CW_COF_SHIFT)) & LTC_CW_COF_MASK)

#define LTC_CW_CIF_MASK                          (0x80000000U)
#define LTC_CW_CIF_SHIFT                         (31U)
/*! CIF - Clear Input FIFO
 */
#define LTC_CW_CIF(x)                            (((uint32_t)(((uint32_t)(x)) << LTC_CW_CIF_SHIFT)) & LTC_CW_CIF_MASK)
/*! @} */

/*! @name STA - Status Register */
/*! @{ */

#define LTC_STA_AB_MASK                          (0x2U)
#define LTC_STA_AB_SHIFT                         (1U)
/*! AB - AESA Busy
 *  0b0..AESA Idle
 *  0b1..AESA Busy.
 */
#define LTC_STA_AB(x)                            (((uint32_t)(((uint32_t)(x)) << LTC_STA_AB_SHIFT)) & LTC_STA_AB_MASK)

#define LTC_STA_DI_MASK                          (0x10000U)
#define LTC_STA_DI_SHIFT                         (16U)
/*! DI - Done Interrupt
 */
#define LTC_STA_DI(x)                            (((uint32_t)(((uint32_t)(x)) << LTC_STA_DI_SHIFT)) & LTC_STA_DI_MASK)

#define LTC_STA_EI_MASK                          (0x100000U)
#define LTC_STA_EI_SHIFT                         (20U)
/*! EI - Error Interrupt
 *  0b0..Not Error.
 *  0b1..Error Interrupt.
 */
#define LTC_STA_EI(x)                            (((uint32_t)(((uint32_t)(x)) << LTC_STA_EI_SHIFT)) & LTC_STA_EI_MASK)
/*! @} */

/*! @name ESTA - Error Status Register */
/*! @{ */

#define LTC_ESTA_ERRID1_MASK                     (0xFU)
#define LTC_ESTA_ERRID1_SHIFT                    (0U)
/*! ERRID1 - Error ID 1
 *  0b0001..Mode Error
 *  0b0010..Data Size Error
 *  0b0011..Key Size Error
 *  0b0110..Data Arrived out of Sequence Error
 *  0b1010..ICV Check Failed
 *  0b1011..Internal Hardware Failure
 *  0b1100..CCM AAD Size Error (either 1. AAD flag in B0 =1 and no AAD type provided, 2. AAD flag in B0 = 0 and
 *          AAD povided, or 3. AAD flag in B0 =1 and not enough AAD provided - expecting more based on AAD size.)
 *  0b1111..Invalid Crypto Engine Selected
 */
#define LTC_ESTA_ERRID1(x)                       (((uint32_t)(((uint32_t)(x)) << LTC_ESTA_ERRID1_SHIFT)) & LTC_ESTA_ERRID1_MASK)

#define LTC_ESTA_CL1_MASK                        (0xF00U)
#define LTC_ESTA_CL1_SHIFT                       (8U)
/*! CL1 - algorithms
 *  0b0000..General Error
 *  0b0001..AES
 */
#define LTC_ESTA_CL1(x)                          (((uint32_t)(((uint32_t)(x)) << LTC_ESTA_CL1_SHIFT)) & LTC_ESTA_CL1_MASK)
/*! @} */

/*! @name AADSZ - AAD Size Register */
/*! @{ */

#define LTC_AADSZ_AADSZ_MASK                     (0xFU)
#define LTC_AADSZ_AADSZ_SHIFT                    (0U)
/*! AADSZ - AAD size in Bytes, mod 16
 */
#define LTC_AADSZ_AADSZ(x)                       (((uint32_t)(((uint32_t)(x)) << LTC_AADSZ_AADSZ_SHIFT)) & LTC_AADSZ_AADSZ_MASK)

#define LTC_AADSZ_AL_MASK                        (0x80000000U)
#define LTC_AADSZ_AL_SHIFT                       (31U)
/*! AL - AAD Last
 */
#define LTC_AADSZ_AL(x)                          (((uint32_t)(((uint32_t)(x)) << LTC_AADSZ_AL_SHIFT)) & LTC_AADSZ_AL_MASK)
/*! @} */

/*! @name CTX - Context Register */
/*! @{ */

#define LTC_CTX_CTX_MASK                         (0xFFFFFFFFU)
#define LTC_CTX_CTX_SHIFT                        (0U)
/*! CTX - CTX
 */
#define LTC_CTX_CTX(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_CTX_CTX_SHIFT)) & LTC_CTX_CTX_MASK)
/*! @} */

/* The count of LTC_CTX */
#define LTC_CTX_COUNT                            (14U)

/*! @name KEY - Key Registers */
/*! @{ */

#define LTC_KEY_KEY_MASK                         (0xFFFFFFFFU)
#define LTC_KEY_KEY_SHIFT                        (0U)
/*! KEY - KEY
 */
#define LTC_KEY_KEY(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_KEY_KEY_SHIFT)) & LTC_KEY_KEY_MASK)
/*! @} */

/* The count of LTC_KEY */
#define LTC_KEY_COUNT                            (4U)

/*! @name VID1 - Version ID Register */
/*! @{ */

#define LTC_VID1_MIN_REV_MASK                    (0xFFU)
#define LTC_VID1_MIN_REV_SHIFT                   (0U)
/*! MIN_REV - Minor revision number.
 */
#define LTC_VID1_MIN_REV(x)                      (((uint32_t)(((uint32_t)(x)) << LTC_VID1_MIN_REV_SHIFT)) & LTC_VID1_MIN_REV_MASK)

#define LTC_VID1_MAJ_REV_MASK                    (0xFF00U)
#define LTC_VID1_MAJ_REV_SHIFT                   (8U)
/*! MAJ_REV - Major revision number.
 */
#define LTC_VID1_MAJ_REV(x)                      (((uint32_t)(((uint32_t)(x)) << LTC_VID1_MAJ_REV_SHIFT)) & LTC_VID1_MAJ_REV_MASK)

#define LTC_VID1_IP_ID_MASK                      (0xFFFF0000U)
#define LTC_VID1_IP_ID_SHIFT                     (16U)
#define LTC_VID1_IP_ID(x)                        (((uint32_t)(((uint32_t)(x)) << LTC_VID1_IP_ID_SHIFT)) & LTC_VID1_IP_ID_MASK)
/*! @} */

/*! @name VID2 - Version ID 2 Register */
/*! @{ */

#define LTC_VID2_ECO_REV_MASK                    (0xFFU)
#define LTC_VID2_ECO_REV_SHIFT                   (0U)
/*! ECO_REV - ECO revision number.
 */
#define LTC_VID2_ECO_REV(x)                      (((uint32_t)(((uint32_t)(x)) << LTC_VID2_ECO_REV_SHIFT)) & LTC_VID2_ECO_REV_MASK)

#define LTC_VID2_ARCH_ERA_MASK                   (0xFF00U)
#define LTC_VID2_ARCH_ERA_SHIFT                  (8U)
/*! ARCH_ERA - Architectural ERA.
 */
#define LTC_VID2_ARCH_ERA(x)                     (((uint32_t)(((uint32_t)(x)) << LTC_VID2_ARCH_ERA_SHIFT)) & LTC_VID2_ARCH_ERA_MASK)
/*! @} */

/*! @name CHAVID - CHA Version ID Register */
/*! @{ */

#define LTC_CHAVID_AESREV_MASK                   (0xFU)
#define LTC_CHAVID_AESREV_SHIFT                  (0U)
/*! AESREV - AES Revision Number
 */
#define LTC_CHAVID_AESREV(x)                     (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_AESREV_SHIFT)) & LTC_CHAVID_AESREV_MASK)

#define LTC_CHAVID_AESVID_MASK                   (0xF0U)
#define LTC_CHAVID_AESVID_SHIFT                  (4U)
/*! AESVID - AES Version ID
 */
#define LTC_CHAVID_AESVID(x)                     (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_AESVID_SHIFT)) & LTC_CHAVID_AESVID_MASK)
/*! @} */

/*! @name FIFOSTA - FIFO Status Register */
/*! @{ */

#define LTC_FIFOSTA_IFL_MASK                     (0x7FU)
#define LTC_FIFOSTA_IFL_SHIFT                    (0U)
/*! IFL - Input FIFO Level
 */
#define LTC_FIFOSTA_IFL(x)                       (((uint32_t)(((uint32_t)(x)) << LTC_FIFOSTA_IFL_SHIFT)) & LTC_FIFOSTA_IFL_MASK)

#define LTC_FIFOSTA_IFF_MASK                     (0x8000U)
#define LTC_FIFOSTA_IFF_SHIFT                    (15U)
/*! IFF - Input FIFO Full
 */
#define LTC_FIFOSTA_IFF(x)                       (((uint32_t)(((uint32_t)(x)) << LTC_FIFOSTA_IFF_SHIFT)) & LTC_FIFOSTA_IFF_MASK)

#define LTC_FIFOSTA_OFL_MASK                     (0x7F0000U)
#define LTC_FIFOSTA_OFL_SHIFT                    (16U)
/*! OFL - Output FIFO Level
 */
#define LTC_FIFOSTA_OFL(x)                       (((uint32_t)(((uint32_t)(x)) << LTC_FIFOSTA_OFL_SHIFT)) & LTC_FIFOSTA_OFL_MASK)

#define LTC_FIFOSTA_OFF_MASK                     (0x80000000U)
#define LTC_FIFOSTA_OFF_SHIFT                    (31U)
/*! OFF - Output FIFO Full
 */
#define LTC_FIFOSTA_OFF(x)                       (((uint32_t)(((uint32_t)(x)) << LTC_FIFOSTA_OFF_SHIFT)) & LTC_FIFOSTA_OFF_MASK)
/*! @} */

/*! @name IFIFO - Input Data FIFO */
/*! @{ */

#define LTC_IFIFO_IFIFO_MASK                     (0xFFFFFFFFU)
#define LTC_IFIFO_IFIFO_SHIFT                    (0U)
/*! IFIFO - IFIFO
 */
#define LTC_IFIFO_IFIFO(x)                       (((uint32_t)(((uint32_t)(x)) << LTC_IFIFO_IFIFO_SHIFT)) & LTC_IFIFO_IFIFO_MASK)
/*! @} */

/*! @name OFIFO - Output Data FIFO */
/*! @{ */

#define LTC_OFIFO_OFIFO_MASK                     (0xFFFFFFFFU)
#define LTC_OFIFO_OFIFO_SHIFT                    (0U)
/*! OFIFO - Output FIFO
 */
#define LTC_OFIFO_OFIFO(x)                       (((uint32_t)(((uint32_t)(x)) << LTC_OFIFO_OFIFO_SHIFT)) & LTC_OFIFO_OFIFO_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LTC_Register_Masks */


/* LTC - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral LTC base address */
  #define LTC_BASE                                 (0x58A06800u)
  /** Peripheral LTC base address */
  #define LTC_BASE_NS                              (0x48A06800u)
  /** Peripheral LTC base pointer */
  #define LTC                                      ((LTC_Type *)LTC_BASE)
  /** Peripheral LTC base pointer */
  #define LTC_NS                                   ((LTC_Type *)LTC_BASE_NS)
  /** Array initializer of LTC peripheral base addresses */
  #define LTC_BASE_ADDRS                           { LTC_BASE }
  /** Array initializer of LTC peripheral base pointers */
  #define LTC_BASE_PTRS                            { LTC }
  /** Array initializer of LTC peripheral base addresses */
  #define LTC_BASE_ADDRS_NS                        { LTC_BASE_NS }
  /** Array initializer of LTC peripheral base pointers */
  #define LTC_BASE_PTRS_NS                         { LTC_NS }
#else
  /** Peripheral LTC base address */
  #define LTC_BASE                                 (0x48A06800u)
  /** Peripheral LTC base pointer */
  #define LTC                                      ((LTC_Type *)LTC_BASE)
  /** Array initializer of LTC peripheral base addresses */
  #define LTC_BASE_ADDRS                           { LTC_BASE }
  /** Array initializer of LTC peripheral base pointers */
  #define LTC_BASE_PTRS                            { LTC }
#endif

/*!
 * @}
 */ /* end of group LTC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- MCM Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
 * @{
 */

/** MCM - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[12];
  __IO uint32_t CPCR;                              /**< Core Platform Control, offset: 0xC */
  __IO uint32_t ISCR;                              /**< Interrupt Status and Control, offset: 0x10 */
       uint8_t RESERVED_1[12];
  __I  uint32_t FADR;                              /**< Write Buffer Fault Address, offset: 0x20 */
  __I  uint32_t FATR;                              /**< Store Buffer Fault Attributes, offset: 0x24 */
  __I  uint32_t FDR;                               /**< Store Buffer Fault Data, offset: 0x28 */
       uint8_t RESERVED_2[8];
  __IO uint32_t CPCR2;                             /**< Core Platform Control 2, offset: 0x34 */
       uint8_t RESERVED_3[976];
  __IO uint32_t LMDR2;                             /**< Local Memory Descriptor 2, offset: 0x408 */
       uint8_t RESERVED_4[116];
  __IO uint32_t LMPECR;                            /**< LMEM Parity Control, offset: 0x480 */
       uint8_t RESERVED_5[4];
  __IO uint32_t LMPEIR;                            /**< LMEM Parity Interrupt, offset: 0x488 */
       uint8_t RESERVED_6[4];
  __I  uint32_t LMFAR;                             /**< LMEM Fault Address, offset: 0x490 */
  __I  uint32_t LMFATR;                            /**< LMEM Fault Attribute, offset: 0x494 */
       uint8_t RESERVED_7[8];
  __I  uint32_t LMFDHR;                            /**< LMEM Fault Data High, offset: 0x4A0 */
  __I  uint32_t LMFDLR;                            /**< LMEM Fault Data Low, offset: 0x4A4 */
} MCM_Type;

/* ----------------------------------------------------------------------------
   -- MCM Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup MCM_Register_Masks MCM Register Masks
 * @{
 */

/*! @name CPCR - Core Platform Control */
/*! @{ */

#define MCM_CPCR_CBRR_MASK                       (0x200U)
#define MCM_CPCR_CBRR_SHIFT                      (9U)
/*! CBRR - Crossbar Round-robin Arbitration Enable
 *  0b0..Fixed-priority arbitration
 *  0b1..Round-robin arbitration
 */
#define MCM_CPCR_CBRR(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_CPCR_CBRR_SHIFT)) & MCM_CPCR_CBRR_MASK)

#define MCM_CPCR_PFLEXSTALL_MASK                 (0x10000U)
#define MCM_CPCR_PFLEXSTALL_SHIFT                (16U)
/*! PFLEXSTALL - Flash Stall Enable
 *  0b0..Flash stall is disabled when flash is busy.
 *  0b1..Flash stall is enabled when flash is busy.
 */
#define MCM_CPCR_PFLEXSTALL(x)                   (((uint32_t)(((uint32_t)(x)) << MCM_CPCR_PFLEXSTALL_SHIFT)) & MCM_CPCR_PFLEXSTALL_MASK)
/*! @} */

/*! @name ISCR - Interrupt Status and Control */
/*! @{ */

#define MCM_ISCR_CWBER_MASK                      (0x10U)
#define MCM_ISCR_CWBER_SHIFT                     (4U)
/*! CWBER - Cache Write Buffer Error Status
 *  0b0..No error
 *  0b1..Error occurred
 */
#define MCM_ISCR_CWBER(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_CWBER_SHIFT)) & MCM_ISCR_CWBER_MASK)

#define MCM_ISCR_CPES_MASK                       (0x20U)
#define MCM_ISCR_CPES_SHIFT                      (5U)
/*! CPES - Cache Parity Error Status
 *  0b0..A cache parity error is not detected.
 *  0b1..A cache parity error is detected.
 */
#define MCM_ISCR_CPES(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_CPES_SHIFT)) & MCM_ISCR_CPES_MASK)

#define MCM_ISCR_FIOC_MASK                       (0x100U)
#define MCM_ISCR_FIOC_SHIFT                      (8U)
/*! FIOC - FPU Invalid Operation Interrupt Status
 *  0b0..No interrupt
 *  0b1..Interrupt occurred
 */
#define MCM_ISCR_FIOC(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK)

#define MCM_ISCR_FDZC_MASK                       (0x200U)
#define MCM_ISCR_FDZC_SHIFT                      (9U)
/*! FDZC - FPU Divide-by-zero Interrupt Status
 *  0b0..No interrupt
 *  0b1..Interrupt occurred
 */
#define MCM_ISCR_FDZC(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK)

#define MCM_ISCR_FOFC_MASK                       (0x400U)
#define MCM_ISCR_FOFC_SHIFT                      (10U)
/*! FOFC - FPU Overflow Interrupt Status
 *  0b0..No interrupt
 *  0b1..Interrupt occurred
 */
#define MCM_ISCR_FOFC(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK)

#define MCM_ISCR_FUFC_MASK                       (0x800U)
#define MCM_ISCR_FUFC_SHIFT                      (11U)
/*! FUFC - FPU Underflow Interrupt status
 *  0b0..No interrupt
 *  0b1..Interrupt occurred
 */
#define MCM_ISCR_FUFC(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK)

#define MCM_ISCR_FIXC_MASK                       (0x1000U)
#define MCM_ISCR_FIXC_SHIFT                      (12U)
/*! FIXC - FPU Inexact Interrupt Status
 *  0b0..No interrupt
 *  0b1..Interrupt occurred
 */
#define MCM_ISCR_FIXC(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK)

#define MCM_ISCR_FIDC_MASK                       (0x8000U)
#define MCM_ISCR_FIDC_SHIFT                      (15U)
/*! FIDC - FPU Input Denormal Interrupt Status
 *  0b0..No interrupt
 *  0b1..Interrupt occurred
 */
#define MCM_ISCR_FIDC(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK)

#define MCM_ISCR_CWBEE_MASK                      (0x100000U)
#define MCM_ISCR_CWBEE_SHIFT                     (20U)
/*! CWBEE - Cache Write Buffer Error Enable
 *  0b0..Disable error interrupt
 *  0b1..Enable error interrupt
 */
#define MCM_ISCR_CWBEE(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_CWBEE_SHIFT)) & MCM_ISCR_CWBEE_MASK)

#define MCM_ISCR_CPEE_MASK                       (0x200000U)
#define MCM_ISCR_CPEE_SHIFT                      (21U)
/*! CPEE - Cache Parity Error Enable
 *  0b0..Disable error interrupt.
 *  0b1..Enable error interrupt.
 */
#define MCM_ISCR_CPEE(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_CPEE_SHIFT)) & MCM_ISCR_CPEE_MASK)

#define MCM_ISCR_FIOCE_MASK                      (0x1000000U)
#define MCM_ISCR_FIOCE_SHIFT                     (24U)
/*! FIOCE - FPU Invalid Operation Interrupt Enable
 *  0b0..Disable interrupt
 *  0b1..Enable interrupt
 */
#define MCM_ISCR_FIOCE(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK)

#define MCM_ISCR_FDZCE_MASK                      (0x2000000U)
#define MCM_ISCR_FDZCE_SHIFT                     (25U)
/*! FDZCE - FPU Divide-by-zero Interrupt Enable
 *  0b0..Disable interrupt
 *  0b1..Enable interrupt
 */
#define MCM_ISCR_FDZCE(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK)

#define MCM_ISCR_FOFCE_MASK                      (0x4000000U)
#define MCM_ISCR_FOFCE_SHIFT                     (26U)
/*! FOFCE - FPU Overflow Interrupt Enable
 *  0b0..Disable interrupt
 *  0b1..Enable interrupt
 */
#define MCM_ISCR_FOFCE(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK)

#define MCM_ISCR_FUFCE_MASK                      (0x8000000U)
#define MCM_ISCR_FUFCE_SHIFT                     (27U)
/*! FUFCE - FPU Underflow Interrupt Enable
 *  0b0..Disable interrupt
 *  0b1..Enable interrupt
 */
#define MCM_ISCR_FUFCE(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK)

#define MCM_ISCR_FIXCE_MASK                      (0x10000000U)
#define MCM_ISCR_FIXCE_SHIFT                     (28U)
/*! FIXCE - FPU Inexact Interrupt Enable
 *  0b0..Disable interrupt
 *  0b1..Enable interrupt
 */
#define MCM_ISCR_FIXCE(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK)

#define MCM_ISCR_FIDCE_MASK                      (0x80000000U)
#define MCM_ISCR_FIDCE_SHIFT                     (31U)
/*! FIDCE - FPU Input Denormal Interrupt Enable
 *  0b0..Disable interrupt
 *  0b1..Enable interrupt
 */
#define MCM_ISCR_FIDCE(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK)
/*! @} */

/*! @name FADR - Write Buffer Fault Address */
/*! @{ */

#define MCM_FADR_ADDRESS_MASK                    (0xFFFFFFFFU)
#define MCM_FADR_ADDRESS_SHIFT                   (0U)
/*! ADDRESS - Fault address
 */
#define MCM_FADR_ADDRESS(x)                      (((uint32_t)(((uint32_t)(x)) << MCM_FADR_ADDRESS_SHIFT)) & MCM_FADR_ADDRESS_MASK)
/*! @} */

/*! @name FATR - Store Buffer Fault Attributes */
/*! @{ */

#define MCM_FATR_BEDA_MASK                       (0x1U)
#define MCM_FATR_BEDA_SHIFT                      (0U)
/*! BEDA - Bus Error Data Access Type
 *  0b0..Instruction
 *  0b1..Data
 */
#define MCM_FATR_BEDA(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEDA_SHIFT)) & MCM_FATR_BEDA_MASK)

#define MCM_FATR_BEMD_MASK                       (0x2U)
#define MCM_FATR_BEMD_SHIFT                      (1U)
/*! BEMD - Bus Error Privilege level
 *  0b0..User mode
 *  0b1..Supervisor/privileged mode
 */
#define MCM_FATR_BEMD(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMD_SHIFT)) & MCM_FATR_BEMD_MASK)

#define MCM_FATR_BESZ_MASK                       (0x30U)
#define MCM_FATR_BESZ_SHIFT                      (4U)
/*! BESZ - Bus Error Size
 *  0b00..8-bit access
 *  0b01..16-bit access
 *  0b10..32-bit access
 *  0b11..Reserved
 */
#define MCM_FATR_BESZ(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BESZ_SHIFT)) & MCM_FATR_BESZ_MASK)

#define MCM_FATR_BEWT_MASK                       (0x80U)
#define MCM_FATR_BEWT_SHIFT                      (7U)
/*! BEWT - Bus Error Write
 *  0b0..Read access
 *  0b1..Write access
 */
#define MCM_FATR_BEWT(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEWT_SHIFT)) & MCM_FATR_BEWT_MASK)

#define MCM_FATR_BEMN_MASK                       (0xF00U)
#define MCM_FATR_BEMN_SHIFT                      (8U)
/*! BEMN - Bus Error Master Number
 */
#define MCM_FATR_BEMN(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMN_SHIFT)) & MCM_FATR_BEMN_MASK)

#define MCM_FATR_BEOVR_MASK                      (0x80000000U)
#define MCM_FATR_BEOVR_SHIFT                     (31U)
/*! BEOVR - Bus Error Overrun
 *  0b0..No bus error overrun
 *  0b1..Bus error overrun occurred. The FADR and FDR registers and the other FATR bits will not be updated to reflect this new bus error.
 */
#define MCM_FATR_BEOVR(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEOVR_SHIFT)) & MCM_FATR_BEOVR_MASK)
/*! @} */

/*! @name FDR - Store Buffer Fault Data */
/*! @{ */

#define MCM_FDR_DATA_MASK                        (0xFFFFFFFFU)
#define MCM_FDR_DATA_SHIFT                       (0U)
/*! DATA - Fault Data
 */
#define MCM_FDR_DATA(x)                          (((uint32_t)(((uint32_t)(x)) << MCM_FDR_DATA_SHIFT)) & MCM_FDR_DATA_MASK)
/*! @} */

/*! @name CPCR2 - Core Platform Control 2 */
/*! @{ */

#define MCM_CPCR2_CCBC_MASK                      (0x1U)
#define MCM_CPCR2_CCBC_SHIFT                     (0U)
/*! CCBC - Clear Code Bus Cache
 *  0b0..No effect
 *  0b1..Clear code bus cache
 */
#define MCM_CPCR2_CCBC(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_CPCR2_CCBC_SHIFT)) & MCM_CPCR2_CCBC_MASK)

#define MCM_CPCR2_DCCWB_MASK                     (0x2U)
#define MCM_CPCR2_DCCWB_SHIFT                    (1U)
/*! DCCWB - Disable Code Cache Write Buffer
 *  0b0..Enable code cache write buffer
 *  0b1..Disable code cache write buffer
 */
#define MCM_CPCR2_DCCWB(x)                       (((uint32_t)(((uint32_t)(x)) << MCM_CPCR2_DCCWB_SHIFT)) & MCM_CPCR2_DCCWB_MASK)

#define MCM_CPCR2_FCCNA_MASK                     (0x4U)
#define MCM_CPCR2_FCCNA_SHIFT                    (2U)
/*! FCCNA - Force Code Cache to No Allocation
 *  0b0..Force code cache to allocation
 *  0b1..Force code cache to no allocation
 */
#define MCM_CPCR2_FCCNA(x)                       (((uint32_t)(((uint32_t)(x)) << MCM_CPCR2_FCCNA_SHIFT)) & MCM_CPCR2_FCCNA_MASK)

#define MCM_CPCR2_DCBC_MASK                      (0x8U)
#define MCM_CPCR2_DCBC_SHIFT                     (3U)
/*! DCBC - Disable Code Bus cache
 *  0b0..Enable code bus cache
 *  0b1..Disable code bus cache
 */
#define MCM_CPCR2_DCBC(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_CPCR2_DCBC_SHIFT)) & MCM_CPCR2_DCBC_MASK)

#define MCM_CPCR2_CBCS_MASK                      (0xF0U)
#define MCM_CPCR2_CBCS_SHIFT                     (4U)
/*! CBCS - Code Bus Cache Size
 *  0b0000..0 KB
 *  0b0001..1 KB
 *  0b0010..2 KB
 *  0b0011..4 KB
 *  0b0100..8 KB
 *  0b0101..16 KB
 *  0b0110..32 KB
 */
#define MCM_CPCR2_CBCS(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_CPCR2_CBCS_SHIFT)) & MCM_CPCR2_CBCS_MASK)

#define MCM_CPCR2_PCCMCTRL_MASK                  (0x10000U)
#define MCM_CPCR2_PCCMCTRL_SHIFT                 (16U)
/*! PCCMCTRL - Bypass Fixed Code Cache Map
 *  0b0..The fixed code cache map is not bypassed
 *  0b1..The fixed code cache map is bypassed
 */
#define MCM_CPCR2_PCCMCTRL(x)                    (((uint32_t)(((uint32_t)(x)) << MCM_CPCR2_PCCMCTRL_SHIFT)) & MCM_CPCR2_PCCMCTRL_MASK)

#define MCM_CPCR2_LCCPWB_MASK                    (0x20000U)
#define MCM_CPCR2_LCCPWB_SHIFT                   (17U)
/*! LCCPWB - Limit Code Cache Peripheral Write Buffering
 *  0b0..Code cache peripheral write buffering is not limited: if write buffer is enabled, bufferable write is buffered.
 *  0b1..Code cache peripheral write buffering is limited: only bufferable and cachable write is buffered.
 */
#define MCM_CPCR2_LCCPWB(x)                      (((uint32_t)(((uint32_t)(x)) << MCM_CPCR2_LCCPWB_SHIFT)) & MCM_CPCR2_LCCPWB_MASK)
/*! @} */

/*! @name LMDR2 - Local Memory Descriptor 2 */
/*! @{ */

#define MCM_LMDR2_PCPME_MASK                     (0x20U)
#define MCM_LMDR2_PCPME_SHIFT                    (5U)
/*! PCPME - PC Parity Enable
 *  0b0..PC parity is disabled.
 *  0b1..PC parity is enabled.
 */
#define MCM_LMDR2_PCPME(x)                       (((uint32_t)(((uint32_t)(x)) << MCM_LMDR2_PCPME_SHIFT)) & MCM_LMDR2_PCPME_MASK)

#define MCM_LMDR2_PCPFE_MASK                     (0x80U)
#define MCM_LMDR2_PCPFE_SHIFT                    (7U)
/*! PCPFE - PC Parity Fault Report Enable
 *  0b0..PC parity fault report is disabled.
 *  0b1..PC parity fault report is enabled.
 */
#define MCM_LMDR2_PCPFE(x)                       (((uint32_t)(((uint32_t)(x)) << MCM_LMDR2_PCPFE_SHIFT)) & MCM_LMDR2_PCPFE_MASK)

#define MCM_LMDR2_MT_MASK                        (0xE000U)
#define MCM_LMDR2_MT_SHIFT                       (13U)
/*! MT - Memory Type
 *  0b000..SRAM_L
 *  0b001..SRAM_U
 *  0b010..PC Cache
 *  0b011..PS Cache
 */
#define MCM_LMDR2_MT(x)                          (((uint32_t)(((uint32_t)(x)) << MCM_LMDR2_MT_SHIFT)) & MCM_LMDR2_MT_MASK)

#define MCM_LMDR2_RO_MASK                        (0x10000U)
#define MCM_LMDR2_RO_SHIFT                       (16U)
/*! RO - Read-Only
 *  0b0..Writes to the corresponding LMDRn[7:0] are allowed.
 *  0b1..Writes to the corresponding LMDRn[7:0] are ignored.
 */
#define MCM_LMDR2_RO(x)                          (((uint32_t)(((uint32_t)(x)) << MCM_LMDR2_RO_SHIFT)) & MCM_LMDR2_RO_MASK)

#define MCM_LMDR2_DPW_MASK                       (0xE0000U)
#define MCM_LMDR2_DPW_SHIFT                      (17U)
/*! DPW - LMEM Data Path Width
 *  0b000-0b001..Reserved
 *  0b010..LMEMn 32-bit wide
 *  0b011..LMEMn 64-bit wide
 *  0b100-0b111..Reserved
 */
#define MCM_LMDR2_DPW(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_LMDR2_DPW_SHIFT)) & MCM_LMDR2_DPW_MASK)

#define MCM_LMDR2_WY_MASK                        (0xF00000U)
#define MCM_LMDR2_WY_SHIFT                       (20U)
/*! WY - Level 1 Cache Ways
 *  0b0000..No Cache
 *  0b0010..2-Way Set Associative
 *  0b0100..4-Way Set Associative
 *  0b1000..8-Way Set Associative
 */
#define MCM_LMDR2_WY(x)                          (((uint32_t)(((uint32_t)(x)) << MCM_LMDR2_WY_SHIFT)) & MCM_LMDR2_WY_MASK)

#define MCM_LMDR2_LMSZ_MASK                      (0xF000000U)
#define MCM_LMDR2_LMSZ_SHIFT                     (24U)
/*! LMSZ - LMEM Size
 *  0b0000..no LMEMn (0 KB)
 *  0b0001..1 KB LMEMn
 *  0b0010..2 KB LMEMn
 *  0b0011..4 KB LMEMn
 *  0b0100..8 KB LMEMn
 *  0b0101..16 KB LMEMn
 *  0b0110..32 KB LMEMn
 *  0b0111..64 KB LMEMn
 *  0b1000..128 KB LMEMn
 *  0b1001..256 KB LMEMn
 *  0b1010..512 KB LMEMn
 *  0b1011..1024 KB LMEMn
 *  0b1100..2048 KB LMEMn
 *  0b1101..4096 KB LMEMn
 *  0b1110..8192 KB LMEMn
 *  0b1111..16384 KB LMEMn
 */
#define MCM_LMDR2_LMSZ(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_LMDR2_LMSZ_SHIFT)) & MCM_LMDR2_LMSZ_MASK)

#define MCM_LMDR2_LMSZH_MASK                     (0x10000000U)
#define MCM_LMDR2_LMSZH_SHIFT                    (28U)
/*! LMSZH - LMEM Size Hole
 *  0b0..LMEMn is a power-of-2 capacity.
 *  0b1..LMEMn is a capacity of 0.75 * LMSZ.
 */
#define MCM_LMDR2_LMSZH(x)                       (((uint32_t)(((uint32_t)(x)) << MCM_LMDR2_LMSZH_SHIFT)) & MCM_LMDR2_LMSZH_MASK)

#define MCM_LMDR2_V_MASK                         (0x80000000U)
#define MCM_LMDR2_V_SHIFT                        (31U)
/*! V - Valid
 *  0b0..LMEMn is not present.
 *  0b1..LMEMn is present.
 */
#define MCM_LMDR2_V(x)                           (((uint32_t)(((uint32_t)(x)) << MCM_LMDR2_V_SHIFT)) & MCM_LMDR2_V_MASK)
/*! @} */

/*! @name LMPECR - LMEM Parity Control */
/*! @{ */

#define MCM_LMPECR_ECPR_MASK                     (0x100000U)
#define MCM_LMPECR_ECPR_SHIFT                    (20U)
/*! ECPR - Enable Cache Parity Reporting
 *  0b0..Cache parity reporting is disabled
 *  0b1..Cache parity reporting is enabled
 */
#define MCM_LMPECR_ECPR(x)                       (((uint32_t)(((uint32_t)(x)) << MCM_LMPECR_ECPR_SHIFT)) & MCM_LMPECR_ECPR_MASK)
/*! @} */

/*! @name LMPEIR - LMEM Parity Interrupt */
/*! @{ */

#define MCM_LMPEIR_PE_MASK                       (0xFF0000U)
#define MCM_LMPEIR_PE_SHIFT                      (16U)
/*! PE - Parity Error
 */
#define MCM_LMPEIR_PE(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_LMPEIR_PE_SHIFT)) & MCM_LMPEIR_PE_MASK)

#define MCM_LMPEIR_PEELOC_MASK                   (0x1F000000U)
#define MCM_LMPEIR_PEELOC_SHIFT                  (24U)
/*! PEELOC - Error Location
 */
#define MCM_LMPEIR_PEELOC(x)                     (((uint32_t)(((uint32_t)(x)) << MCM_LMPEIR_PEELOC_SHIFT)) & MCM_LMPEIR_PEELOC_MASK)

#define MCM_LMPEIR_V_MASK                        (0x80000000U)
#define MCM_LMPEIR_V_SHIFT                       (31U)
/*! V - Valid bit
 */
#define MCM_LMPEIR_V(x)                          (((uint32_t)(((uint32_t)(x)) << MCM_LMPEIR_V_SHIFT)) & MCM_LMPEIR_V_MASK)
/*! @} */

/*! @name LMFAR - LMEM Fault Address */
/*! @{ */

#define MCM_LMFAR_EFADD_MASK                     (0xFFFFFFFFU)
#define MCM_LMFAR_EFADD_SHIFT                    (0U)
/*! EFADD - Fault Address
 */
#define MCM_LMFAR_EFADD(x)                       (((uint32_t)(((uint32_t)(x)) << MCM_LMFAR_EFADD_SHIFT)) & MCM_LMFAR_EFADD_MASK)
/*! @} */

/*! @name LMFATR - LMEM Fault Attribute */
/*! @{ */

#define MCM_LMFATR_PEFPRT_MASK                   (0xFU)
#define MCM_LMFATR_PEFPRT_SHIFT                  (0U)
/*! PEFPRT - Parity Fault Protection Signal
 */
#define MCM_LMFATR_PEFPRT(x)                     (((uint32_t)(((uint32_t)(x)) << MCM_LMFATR_PEFPRT_SHIFT)) & MCM_LMFATR_PEFPRT_MASK)

#define MCM_LMFATR_PEFSIZE_MASK                  (0x70U)
#define MCM_LMFATR_PEFSIZE_SHIFT                 (4U)
/*! PEFSIZE - PEFSIZE
 *  0b000..8-bit access
 *  0b001..16-bit access
 *  0b010..32-bit access
 *  0b011..64-bit access
 *  0b100..Reserved
 *  0b101..Reserved
 *  0b110..Reserved
 *  0b111..Reserved
 */
#define MCM_LMFATR_PEFSIZE(x)                    (((uint32_t)(((uint32_t)(x)) << MCM_LMFATR_PEFSIZE_SHIFT)) & MCM_LMFATR_PEFSIZE_MASK)

#define MCM_LMFATR_PEFW_MASK                     (0x80U)
#define MCM_LMFATR_PEFW_SHIFT                    (7U)
/*! PEFW - Parity Fault Write
 *  0b0..Read fault
 *  0b1..Write fault
 */
#define MCM_LMFATR_PEFW(x)                       (((uint32_t)(((uint32_t)(x)) << MCM_LMFATR_PEFW_SHIFT)) & MCM_LMFATR_PEFW_MASK)

#define MCM_LMFATR_BKD_MASK                      (0x8000U)
#define MCM_LMFATR_BKD_SHIFT                     (15U)
/*! BKD - Backdoor Access
 *  0b0..Core access
 *  0b1..Backdoor access
 */
#define MCM_LMFATR_BKD(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_LMFATR_BKD_SHIFT)) & MCM_LMFATR_BKD_MASK)

#define MCM_LMFATR_PEFSYN_MASK                   (0xFF0000U)
#define MCM_LMFATR_PEFSYN_SHIFT                  (16U)
/*! PEFSYN - Parity Fault Syndrome
 */
#define MCM_LMFATR_PEFSYN(x)                     (((uint32_t)(((uint32_t)(x)) << MCM_LMFATR_PEFSYN_SHIFT)) & MCM_LMFATR_PEFSYN_MASK)

#define MCM_LMFATR_OVR_MASK                      (0x80000000U)
#define MCM_LMFATR_OVR_SHIFT                     (31U)
/*! OVR - Overrun
 *  0b0..There is sigle fault or no fault.
 *  0b1..There are multiple faults
 */
#define MCM_LMFATR_OVR(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_LMFATR_OVR_SHIFT)) & MCM_LMFATR_OVR_MASK)
/*! @} */

/*! @name LMFDHR - LMEM Fault Data High */
/*! @{ */

#define MCM_LMFDHR_PEFDH_MASK                    (0xFFFFFFFFU)
#define MCM_LMFDHR_PEFDH_SHIFT                   (0U)
/*! PEFDH - PEFDH
 */
#define MCM_LMFDHR_PEFDH(x)                      (((uint32_t)(((uint32_t)(x)) << MCM_LMFDHR_PEFDH_SHIFT)) & MCM_LMFDHR_PEFDH_MASK)
/*! @} */

/*! @name LMFDLR - LMEM Fault Data Low */
/*! @{ */

#define MCM_LMFDLR_PEFDL_MASK                    (0xFFFFFFFFU)
#define MCM_LMFDLR_PEFDL_SHIFT                   (0U)
/*! PEFDL - PEFDL
 */
#define MCM_LMFDLR_PEFDL(x)                      (((uint32_t)(((uint32_t)(x)) << MCM_LMFDLR_PEFDL_SHIFT)) & MCM_LMFDLR_PEFDL_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group MCM_Register_Masks */


/* MCM - Peripheral instance base addresses */
/** Peripheral MCM base address */
#define MCM_BASE                                 (0xE0080000u)
/** Peripheral MCM base pointer */
#define MCM                                      ((MCM_Type *)MCM_BASE)
/** Array initializer of MCM peripheral base addresses */
#define MCM_BASE_ADDRS                           { MCM_BASE }
/** Array initializer of MCM peripheral base pointers */
#define MCM_BASE_PTRS                            { MCM }
/** Interrupt vectors for the MCM peripheral type */
#define MCM_IRQS                                 { MCM0_IRQn }

/*!
 * @}
 */ /* end of group MCM_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- MRCC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup MRCC_Peripheral_Access_Layer MRCC Peripheral Access Layer
 * @{
 */

/** MRCC - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[76];
  __IO uint32_t MRCC_EWM0;                         /**< EWM0 Reset and Clock Control, offset: 0x4C */
       uint8_t RESERVED_1[12];
  __IO uint32_t MRCC_SYSPM0;                       /**< SYSPM0 Reset and Clock Control, offset: 0x5C */
       uint8_t RESERVED_2[8];
  __IO uint32_t MRCC_WDOG0;                        /**< WDOG0 Reset and Clock Control, offset: 0x68 */
  __IO uint32_t MRCC_WDOG1;                        /**< WDOG1 Reset and Clock Control, offset: 0x6C */
       uint8_t RESERVED_3[4];
  __IO uint32_t MRCC_SFA0;                         /**< SFA0 Reset and Clock Control, offset: 0x74 */
       uint8_t RESERVED_4[20];
  __IO uint32_t MRCC_CRC0;                         /**< CRC0 Reset and Clock Control, offset: 0x8C */
  __IO uint32_t MRCC_SECSUBSYS;                    /**< ELE Reset and Clock Control, offset: 0x90 */
       uint8_t RESERVED_5[40];
  __IO uint32_t MRCC_LPIT0;                        /**< LPIT0 Reset and Clock Control, offset: 0xBC */
  __IO uint32_t MRCC_TSTMR0;                       /**< TSTMR0 Reset and Clock Control, offset: 0xC0 */
  __IO uint32_t MRCC_TPM0;                         /**< TPM0 Reset and Clock Control, offset: 0xC4 */
  __IO uint32_t MRCC_TPM1;                         /**< TPM1 Reset and Clock Control, offset: 0xC8 */
  __IO uint32_t MRCC_LPI2C0;                       /**< LPI2C0 Reset and Clock Control, offset: 0xCC */
  __IO uint32_t MRCC_LPI2C1;                       /**< LPI2C1 Reset and Clock Control, offset: 0xD0 */
  __IO uint32_t MRCC_I3C0;                         /**< I3C0 Reset and Clock Control, offset: 0xD4 */
  __IO uint32_t MRCC_LPSPI0;                       /**< LPSPI0 Reset and Clock Control, offset: 0xD8 */
  __IO uint32_t MRCC_LPSPI1;                       /**< LPSPI1 Reset and Clock Control, offset: 0xDC */
  __IO uint32_t MRCC_LPUART0;                      /**< LPUART0 Reset and Clock Control, offset: 0xE0 */
  __IO uint32_t MRCC_LPUART1;                      /**< LPUART1 Reset and Clock Control, offset: 0xE4 */
  __IO uint32_t MRCC_FLEXIO0;                      /**< FLEXIO0 Reset and Clock Control, offset: 0xE8 */
  __IO uint32_t MRCC_CAN0;                         /**< CAN0 Reset and Clock Control, offset: 0xEC */
       uint8_t RESERVED_6[12];
  __IO uint32_t MRCC_SEMA0;                        /**< SEMA42 Reset and Clock Control, offset: 0xFC */
       uint8_t RESERVED_7[4];
  __IO uint32_t MRCC_DATA_STREAM_2P4;              /**< DSB Reset and Clock Control, offset: 0x104 */
  __IO uint32_t MRCC_PORTA;                        /**< PORTA Reset and Clock Control, offset: 0x108 */
  __IO uint32_t MRCC_PORTB;                        /**< PORTB Reset and Clock Control, offset: 0x10C */
  __IO uint32_t MRCC_PORTC;                        /**< PORTC Reset and Clock Control, offset: 0x110 */
       uint8_t RESERVED_8[8];
  __IO uint32_t MRCC_LPADC0;                       /**< ADC0 Reset and Clock Control, offset: 0x11C */
  __IO uint32_t MRCC_LPCMP0;                       /**< LPCMP0 Reset and Clock Control, offset: 0x120 */
  __IO uint32_t MRCC_LPCMP1;                       /**< LPCMP1 Reset and Clock Control, offset: 0x124 */
  __IO uint32_t MRCC_VREF0;                        /**< VREF0 Reset and Clock Control, offset: 0x128 */
       uint8_t RESERVED_9[728];
  __IO uint32_t MRCC_GPIOA;                        /**< GPIOA Reset and Clock Control, offset: 0x404 */
  __IO uint32_t MRCC_GPIOB;                        /**< GPIOB Reset and Clock Control, offset: 0x408 */
  __IO uint32_t MRCC_GPIOC;                        /**< GPIOC Reset and Clock Control, offset: 0x40C */
  __IO uint32_t MRCC_DMA0;                         /**< DMA0 Reset and Clock Control, offset: 0x410 */
  __IO uint32_t MRCC_PFLEXNVM;                     /**< FMC-NPX Reset and Clock Control, offset: 0x414 */
       uint8_t RESERVED_10[4];
  __IO uint32_t MRCC_SRAM0;                        /**< CTCM Reset and Clock Control, offset: 0x41C */
  __IO uint32_t MRCC_SRAM1;                        /**< STCM0 Reset and Clock Control, offset: 0x420 */
  __IO uint32_t MRCC_SRAM2;                        /**< STCM1 Reset and Clock Control, offset: 0x424 */
  __IO uint32_t MRCC_SRAM3;                        /**< STCM2 Reset and Clock Control, offset: 0x428 */
} MRCC_Type;

/* ----------------------------------------------------------------------------
   -- MRCC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup MRCC_Register_Masks MRCC Register Masks
 * @{
 */

/*! @name MRCC_EWM0 - EWM0 Reset and Clock Control */
/*! @{ */

#define MRCC_MRCC_EWM0_CC_MASK                   (0x3U)
#define MRCC_MRCC_EWM0_CC_SHIFT                  (0U)
/*! CC - Clock Configuration
 *  0b00..Peripheral clocks are disabled; module does not stall low power mode entry
 *  0b01..Peripheral clocks are enabled; module does not stall low power mode entry
 *  0b10..Reserved
 *  0b11..Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle.
 */
#define MRCC_MRCC_EWM0_CC(x)                     (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_EWM0_CC_SHIFT)) & MRCC_MRCC_EWM0_CC_MASK)

#define MRCC_MRCC_EWM0_RSTB_MASK                 (0x40000000U)
#define MRCC_MRCC_EWM0_RSTB_SHIFT                (30U)
/*! RSTB - Reset Negation
 *  0b0..Module is held in reset
 *  0b1..Module released from reset
 */
#define MRCC_MRCC_EWM0_RSTB(x)                   (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_EWM0_RSTB_SHIFT)) & MRCC_MRCC_EWM0_RSTB_MASK)

#define MRCC_MRCC_EWM0_PR_MASK                   (0x80000000U)
#define MRCC_MRCC_EWM0_PR_SHIFT                  (31U)
/*! PR - Peripheral Present
 *  0b0..Module is not present; writes to this register are ignored
 *  0b1..Module is present
 */
#define MRCC_MRCC_EWM0_PR(x)                     (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_EWM0_PR_SHIFT)) & MRCC_MRCC_EWM0_PR_MASK)
/*! @} */

/*! @name MRCC_SYSPM0 - SYSPM0 Reset and Clock Control */
/*! @{ */

#define MRCC_MRCC_SYSPM0_CC_MASK                 (0x3U)
#define MRCC_MRCC_SYSPM0_CC_SHIFT                (0U)
/*! CC - Clock Configuration
 *  0b00..Peripheral clocks are disabled; module does not stall low power mode entry
 *  0b01..Peripheral clocks are enabled; module does not stall low power mode entry
 *  0b10..Reserved
 *  0b11..Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle.
 */
#define MRCC_MRCC_SYSPM0_CC(x)                   (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_SYSPM0_CC_SHIFT)) & MRCC_MRCC_SYSPM0_CC_MASK)
/*! @} */

/*! @name MRCC_WDOG0 - WDOG0 Reset and Clock Control */
/*! @{ */

#define MRCC_MRCC_WDOG0_CC_MASK                  (0x3U)
#define MRCC_MRCC_WDOG0_CC_SHIFT                 (0U)
/*! CC - Clock Configuration
 *  0b00..Peripheral clocks are disabled; module does not stall low power mode entry
 *  0b01..Peripheral clocks are enabled; module does not stall low power mode entry
 *  0b10..Reserved
 *  0b11..Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle.
 */
#define MRCC_MRCC_WDOG0_CC(x)                    (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_WDOG0_CC_SHIFT)) & MRCC_MRCC_WDOG0_CC_MASK)
/*! @} */

/*! @name MRCC_WDOG1 - WDOG1 Reset and Clock Control */
/*! @{ */

#define MRCC_MRCC_WDOG1_CC_MASK                  (0x3U)
#define MRCC_MRCC_WDOG1_CC_SHIFT                 (0U)
/*! CC - Clock Configuration
 *  0b00..Peripheral clocks are disabled; module does not stall low power mode entry
 *  0b01..Peripheral clocks are enabled; module does not stall low power mode entry
 *  0b10..Reserved
 *  0b11..Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle.
 */
#define MRCC_MRCC_WDOG1_CC(x)                    (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_WDOG1_CC_SHIFT)) & MRCC_MRCC_WDOG1_CC_MASK)
/*! @} */

/*! @name MRCC_SFA0 - SFA0 Reset and Clock Control */
/*! @{ */

#define MRCC_MRCC_SFA0_CC_MASK                   (0x3U)
#define MRCC_MRCC_SFA0_CC_SHIFT                  (0U)
/*! CC - Clock Configuration
 *  0b00..Peripheral clocks are disabled; module does not stall low power mode entry
 *  0b01..Peripheral clocks are enabled; module does not stall low power mode entry
 *  0b10..Reserved
 *  0b11..Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle.
 */
#define MRCC_MRCC_SFA0_CC(x)                     (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_SFA0_CC_SHIFT)) & MRCC_MRCC_SFA0_CC_MASK)

#define MRCC_MRCC_SFA0_RSTB_MASK                 (0x40000000U)
#define MRCC_MRCC_SFA0_RSTB_SHIFT                (30U)
/*! RSTB - Reset Negation
 *  0b0..Module is held in reset
 *  0b1..Module released from reset
 */
#define MRCC_MRCC_SFA0_RSTB(x)                   (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_SFA0_RSTB_SHIFT)) & MRCC_MRCC_SFA0_RSTB_MASK)

#define MRCC_MRCC_SFA0_PR_MASK                   (0x80000000U)
#define MRCC_MRCC_SFA0_PR_SHIFT                  (31U)
/*! PR - Peripheral Present
 *  0b0..Module is not present; writes to this register are ignored
 *  0b1..Module is present
 */
#define MRCC_MRCC_SFA0_PR(x)                     (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_SFA0_PR_SHIFT)) & MRCC_MRCC_SFA0_PR_MASK)
/*! @} */

/*! @name MRCC_CRC0 - CRC0 Reset and Clock Control */
/*! @{ */

#define MRCC_MRCC_CRC0_CC_MASK                   (0x3U)
#define MRCC_MRCC_CRC0_CC_SHIFT                  (0U)
/*! CC - Clock Configuration
 *  0b00..Peripheral clocks are disabled; module does not stall low power mode entry
 *  0b01..Peripheral clocks are enabled; module does not stall low power mode entry
 *  0b10..Reserved
 *  0b11..Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle.
 */
#define MRCC_MRCC_CRC0_CC(x)                     (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CRC0_CC_SHIFT)) & MRCC_MRCC_CRC0_CC_MASK)

#define MRCC_MRCC_CRC0_RSTB_MASK                 (0x40000000U)
#define MRCC_MRCC_CRC0_RSTB_SHIFT                (30U)
/*! RSTB - Reset Negation
 *  0b0..Module is held in reset
 *  0b1..Module released from reset
 */
#define MRCC_MRCC_CRC0_RSTB(x)                   (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CRC0_RSTB_SHIFT)) & MRCC_MRCC_CRC0_RSTB_MASK)

#define MRCC_MRCC_CRC0_PR_MASK                   (0x80000000U)
#define MRCC_MRCC_CRC0_PR_SHIFT                  (31U)
/*! PR - Peripheral Present
 *  0b0..Module is not present; writes to this register are ignored
 *  0b1..Module is present
 */
#define MRCC_MRCC_CRC0_PR(x)                     (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CRC0_PR_SHIFT)) & MRCC_MRCC_CRC0_PR_MASK)
/*! @} */

/*! @name MRCC_SECSUBSYS - ELE Reset and Clock Control */
/*! @{ */

#define MRCC_MRCC_SECSUBSYS_CC_MASK              (0x3U)
#define MRCC_MRCC_SECSUBSYS_CC_SHIFT             (0U)
/*! CC - Clock Configuration
 *  0b00..Peripheral clocks are disabled; module does not stall low power mode entry
 *  0b01..Peripheral clocks are enabled; module does not stall low power mode entry
 *  0b10..Reserved
 *  0b11..Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle.
 */
#define MRCC_MRCC_SECSUBSYS_CC(x)                (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_SECSUBSYS_CC_SHIFT)) & MRCC_MRCC_SECSUBSYS_CC_MASK)

#define MRCC_MRCC_SECSUBSYS_RSTB_MASK            (0x40000000U)
#define MRCC_MRCC_SECSUBSYS_RSTB_SHIFT           (30U)
/*! RSTB - Reset Negation
 *  0b0..Module is held in reset
 *  0b1..Module released from reset
 */
#define MRCC_MRCC_SECSUBSYS_RSTB(x)              (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_SECSUBSYS_RSTB_SHIFT)) & MRCC_MRCC_SECSUBSYS_RSTB_MASK)

#define MRCC_MRCC_SECSUBSYS_PR_MASK              (0x80000000U)
#define MRCC_MRCC_SECSUBSYS_PR_SHIFT             (31U)
/*! PR - Peripheral Present
 *  0b0..Module is not present; writes to this register are ignored
 *  0b1..Module is present
 */
#define MRCC_MRCC_SECSUBSYS_PR(x)                (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_SECSUBSYS_PR_SHIFT)) & MRCC_MRCC_SECSUBSYS_PR_MASK)
/*! @} */

/*! @name MRCC_LPIT0 - LPIT0 Reset and Clock Control */
/*! @{ */

#define MRCC_MRCC_LPIT0_CC_MASK                  (0x3U)
#define MRCC_MRCC_LPIT0_CC_SHIFT                 (0U)
/*! CC - Clock Configuration
 *  0b00..Peripheral clocks are disabled; module does not stall low power mode entry
 *  0b01..Peripheral clocks are enabled; module does not stall low power mode entry
 *  0b10..Reserved
 *  0b11..Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle.
 */
#define MRCC_MRCC_LPIT0_CC(x)                    (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPIT0_CC_SHIFT)) & MRCC_MRCC_LPIT0_CC_MASK)

#define MRCC_MRCC_LPIT0_MUX_MASK                 (0x70U)
#define MRCC_MRCC_LPIT0_MUX_SHIFT                (4U)
/*! MUX - Functional Clock Mux Select
 *  0b100..SOSC-CLK
 *  0b011..FRO-192M
 *  0b010..FRO-6M
 *  0b000..The clock is off
 */
#define MRCC_MRCC_LPIT0_MUX(x)                   (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPIT0_MUX_SHIFT)) & MRCC_MRCC_LPIT0_MUX_MASK)

#define MRCC_MRCC_LPIT0_DIV_MASK                 (0xF00U)
#define MRCC_MRCC_LPIT0_DIV_SHIFT                (8U)
/*! DIV - Functional Clock Divider
 */
#define MRCC_MRCC_LPIT0_DIV(x)                   (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPIT0_DIV_SHIFT)) & MRCC_MRCC_LPIT0_DIV_MASK)

#define MRCC_MRCC_LPIT0_RSTB_MASK                (0x40000000U)
#define MRCC_MRCC_LPIT0_RSTB_SHIFT               (30U)
/*! RSTB - Reset Negation
 *  0b0..Module is held in reset
 *  0b1..Module released from reset
 */
#define MRCC_MRCC_LPIT0_RSTB(x)                  (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPIT0_RSTB_SHIFT)) & MRCC_MRCC_LPIT0_RSTB_MASK)

#define MRCC_MRCC_LPIT0_PR_MASK                  (0x80000000U)
#define MRCC_MRCC_LPIT0_PR_SHIFT                 (31U)
/*! PR - Peripheral Present
 *  0b0..Module is not present; writes to this register are ignored
 *  0b1..Module is present
 */
#define MRCC_MRCC_LPIT0_PR(x)                    (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPIT0_PR_SHIFT)) & MRCC_MRCC_LPIT0_PR_MASK)
/*! @} */

/*! @name MRCC_TSTMR0 - TSTMR0 Reset and Clock Control */
/*! @{ */

#define MRCC_MRCC_TSTMR0_CC_MASK                 (0x3U)
#define MRCC_MRCC_TSTMR0_CC_SHIFT                (0U)
/*! CC - Clock Configuration
 *  0b00..Peripheral clocks are disabled; module does not stall low power mode entry
 *  0b01..Peripheral clocks are enabled; module does not stall low power mode entry
 *  0b10..Reserved
 *  0b11..Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle.
 */
#define MRCC_MRCC_TSTMR0_CC(x)                   (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_TSTMR0_CC_SHIFT)) & MRCC_MRCC_TSTMR0_CC_MASK)
/*! @} */

/*! @name MRCC_TPM0 - TPM0 Reset and Clock Control */
/*! @{ */

#define MRCC_MRCC_TPM0_CC_MASK                   (0x3U)
#define MRCC_MRCC_TPM0_CC_SHIFT                  (0U)
/*! CC - Clock Configuration
 *  0b00..Peripheral clocks are disabled; module does not stall low power mode entry
 *  0b01..Peripheral clocks are enabled; module does not stall low power mode entry
 *  0b10..Peripheral clocks are enabled unless module is idle; low power mode entry stalls until module is idle
 *  0b11..Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle.
 */
#define MRCC_MRCC_TPM0_CC(x)                     (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_TPM0_CC_SHIFT)) & MRCC_MRCC_TPM0_CC_MASK)

#define MRCC_MRCC_TPM0_MUX_MASK                  (0x70U)
#define MRCC_MRCC_TPM0_MUX_SHIFT                 (4U)
/*! MUX - Functional Clock Mux Select
 *  0b101..32K-CLK
 *  0b100..SOSC-CLK
 *  0b011..FRO-192M
 *  0b010..FRO-6M
 *  0b000..The clock is off
 */
#define MRCC_MRCC_TPM0_MUX(x)                    (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_TPM0_MUX_SHIFT)) & MRCC_MRCC_TPM0_MUX_MASK)

#define MRCC_MRCC_TPM0_DIV_MASK                  (0xF00U)
#define MRCC_MRCC_TPM0_DIV_SHIFT                 (8U)
/*! DIV - Functional Clock Divider
 */
#define MRCC_MRCC_TPM0_DIV(x)                    (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_TPM0_DIV_SHIFT)) & MRCC_MRCC_TPM0_DIV_MASK)

#define MRCC_MRCC_TPM0_RSTB_MASK                 (0x40000000U)
#define MRCC_MRCC_TPM0_RSTB_SHIFT                (30U)
/*! RSTB - Reset Negation
 *  0b0..Module is held in reset
 *  0b1..Module released from reset
 */
#define MRCC_MRCC_TPM0_RSTB(x)                   (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_TPM0_RSTB_SHIFT)) & MRCC_MRCC_TPM0_RSTB_MASK)

#define MRCC_MRCC_TPM0_PR_MASK                   (0x80000000U)
#define MRCC_MRCC_TPM0_PR_SHIFT                  (31U)
/*! PR - Peripheral Present
 *  0b0..Module is not present; writes to this register are ignored
 *  0b1..Module is present
 */
#define MRCC_MRCC_TPM0_PR(x)                     (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_TPM0_PR_SHIFT)) & MRCC_MRCC_TPM0_PR_MASK)
/*! @} */

/*! @name MRCC_TPM1 - TPM1 Reset and Clock Control */
/*! @{ */

#define MRCC_MRCC_TPM1_CC_MASK                   (0x3U)
#define MRCC_MRCC_TPM1_CC_SHIFT                  (0U)
/*! CC - Clock Configuration
 *  0b00..Peripheral clocks are disabled; module does not stall low power mode entry
 *  0b01..Peripheral clocks are enabled; module does not stall low power mode entry
 *  0b10..Peripheral clocks are enabled unless module is idle; low power mode entry stalls until module is idle
 *  0b11..Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle.
 */
#define MRCC_MRCC_TPM1_CC(x)                     (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_TPM1_CC_SHIFT)) & MRCC_MRCC_TPM1_CC_MASK)

#define MRCC_MRCC_TPM1_MUX_MASK                  (0x70U)
#define MRCC_MRCC_TPM1_MUX_SHIFT                 (4U)
/*! MUX - Functional Clock Mux Select
 *  0b101..32K-CLK
 *  0b100..SOSC-CLK
 *  0b011..FRO-192M
 *  0b010..FRO-6M
 *  0b000..The clock is off
 */
#define MRCC_MRCC_TPM1_MUX(x)                    (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_TPM1_MUX_SHIFT)) & MRCC_MRCC_TPM1_MUX_MASK)

#define MRCC_MRCC_TPM1_DIV_MASK                  (0xF00U)
#define MRCC_MRCC_TPM1_DIV_SHIFT                 (8U)
/*! DIV - Functional Clock Divider
 */
#define MRCC_MRCC_TPM1_DIV(x)                    (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_TPM1_DIV_SHIFT)) & MRCC_MRCC_TPM1_DIV_MASK)

#define MRCC_MRCC_TPM1_RSTB_MASK                 (0x40000000U)
#define MRCC_MRCC_TPM1_RSTB_SHIFT                (30U)
/*! RSTB - Reset Negation
 *  0b0..Module is held in reset
 *  0b1..Module released from reset
 */
#define MRCC_MRCC_TPM1_RSTB(x)                   (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_TPM1_RSTB_SHIFT)) & MRCC_MRCC_TPM1_RSTB_MASK)

#define MRCC_MRCC_TPM1_PR_MASK                   (0x80000000U)
#define MRCC_MRCC_TPM1_PR_SHIFT                  (31U)
/*! PR - Peripheral Present
 *  0b0..Module is not present; writes to this register are ignored
 *  0b1..Module is present
 */
#define MRCC_MRCC_TPM1_PR(x)                     (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_TPM1_PR_SHIFT)) & MRCC_MRCC_TPM1_PR_MASK)
/*! @} */

/*! @name MRCC_LPI2C0 - LPI2C0 Reset and Clock Control */
/*! @{ */

#define MRCC_MRCC_LPI2C0_CC_MASK                 (0x3U)
#define MRCC_MRCC_LPI2C0_CC_SHIFT                (0U)
/*! CC - Clock Configuration
 *  0b00..Peripheral clocks are disabled; module does not stall low power mode entry
 *  0b01..Peripheral clocks are enabled; module does not stall low power mode entry
 *  0b10..Peripheral clocks are enabled unless module is idle; low power mode entry stalls until module is idle
 *  0b11..Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle.
 */
#define MRCC_MRCC_LPI2C0_CC(x)                   (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C0_CC_SHIFT)) & MRCC_MRCC_LPI2C0_CC_MASK)

#define MRCC_MRCC_LPI2C0_MUX_MASK                (0x70U)
#define MRCC_MRCC_LPI2C0_MUX_SHIFT               (4U)
/*! MUX - Functional Clock Mux Select
 *  0b100..SOSC-CLK
 *  0b011..FRO-192M
 *  0b010..FRO-6M
 *  0b000..The clock is off
 */
#define MRCC_MRCC_LPI2C0_MUX(x)                  (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C0_MUX_SHIFT)) & MRCC_MRCC_LPI2C0_MUX_MASK)

#define MRCC_MRCC_LPI2C0_DIV_MASK                (0xF00U)
#define MRCC_MRCC_LPI2C0_DIV_SHIFT               (8U)
/*! DIV - Functional Clock Divider
 */
#define MRCC_MRCC_LPI2C0_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C0_DIV_SHIFT)) & MRCC_MRCC_LPI2C0_DIV_MASK)

#define MRCC_MRCC_LPI2C0_RSTB_MASK               (0x40000000U)
#define MRCC_MRCC_LPI2C0_RSTB_SHIFT              (30U)
/*! RSTB - Reset Negation
 *  0b0..Module is held in reset
 *  0b1..Module released from reset
 */
#define MRCC_MRCC_LPI2C0_RSTB(x)                 (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C0_RSTB_SHIFT)) & MRCC_MRCC_LPI2C0_RSTB_MASK)

#define MRCC_MRCC_LPI2C0_PR_MASK                 (0x80000000U)
#define MRCC_MRCC_LPI2C0_PR_SHIFT                (31U)
/*! PR - Peripheral Present
 *  0b0..Module is not present; writes to this register are ignored
 *  0b1..Module is present
 */
#define MRCC_MRCC_LPI2C0_PR(x)                   (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C0_PR_SHIFT)) & MRCC_MRCC_LPI2C0_PR_MASK)
/*! @} */

/*! @name MRCC_LPI2C1 - LPI2C1 Reset and Clock Control */
/*! @{ */

#define MRCC_MRCC_LPI2C1_CC_MASK                 (0x3U)
#define MRCC_MRCC_LPI2C1_CC_SHIFT                (0U)
/*! CC - Clock Configuration
 *  0b00..Peripheral clocks are disabled; module does not stall low power mode entry
 *  0b01..Peripheral clocks are enabled; module does not stall low power mode entry
 *  0b10..Peripheral clocks are enabled unless module is idle; low power mode entry stalls until module is idle
 *  0b11..Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle.
 */
#define MRCC_MRCC_LPI2C1_CC(x)                   (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C1_CC_SHIFT)) & MRCC_MRCC_LPI2C1_CC_MASK)

#define MRCC_MRCC_LPI2C1_MUX_MASK                (0x70U)
#define MRCC_MRCC_LPI2C1_MUX_SHIFT               (4U)
/*! MUX - Functional Clock Mux Select
 *  0b100..SOSC-CLK
 *  0b011..FRO-192M
 *  0b010..FRO-6M
 *  0b000..The clock is off
 */
#define MRCC_MRCC_LPI2C1_MUX(x)                  (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C1_MUX_SHIFT)) & MRCC_MRCC_LPI2C1_MUX_MASK)

#define MRCC_MRCC_LPI2C1_DIV_MASK                (0xF00U)
#define MRCC_MRCC_LPI2C1_DIV_SHIFT               (8U)
/*! DIV - Functional Clock Divider
 */
#define MRCC_MRCC_LPI2C1_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C1_DIV_SHIFT)) & MRCC_MRCC_LPI2C1_DIV_MASK)

#define MRCC_MRCC_LPI2C1_RSTB_MASK               (0x40000000U)
#define MRCC_MRCC_LPI2C1_RSTB_SHIFT              (30U)
/*! RSTB - Reset Negation
 *  0b0..Module is held in reset
 *  0b1..Module released from reset
 */
#define MRCC_MRCC_LPI2C1_RSTB(x)                 (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C1_RSTB_SHIFT)) & MRCC_MRCC_LPI2C1_RSTB_MASK)

#define MRCC_MRCC_LPI2C1_PR_MASK                 (0x80000000U)
#define MRCC_MRCC_LPI2C1_PR_SHIFT                (31U)
/*! PR - Peripheral Present
 *  0b0..Module is not present; writes to this register are ignored
 *  0b1..Module is present
 */
#define MRCC_MRCC_LPI2C1_PR(x)                   (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C1_PR_SHIFT)) & MRCC_MRCC_LPI2C1_PR_MASK)
/*! @} */

/*! @name MRCC_I3C0 - I3C0 Reset and Clock Control */
/*! @{ */

#define MRCC_MRCC_I3C0_CC_MASK                   (0x3U)
#define MRCC_MRCC_I3C0_CC_SHIFT                  (0U)
/*! CC - Clock Configuration
 *  0b00..Peripheral clocks are disabled; module does not stall low power mode entry
 *  0b01..Peripheral clocks are enabled; module does not stall low power mode entry
 *  0b10..Reserved
 *  0b11..Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle.
 */
#define MRCC_MRCC_I3C0_CC(x)                     (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_I3C0_CC_SHIFT)) & MRCC_MRCC_I3C0_CC_MASK)

#define MRCC_MRCC_I3C0_MUX_MASK                  (0x70U)
#define MRCC_MRCC_I3C0_MUX_SHIFT                 (4U)
/*! MUX - Functional Clock Mux Select
 *  0b100..SOSC-CLK
 *  0b011..FRO-192M
 *  0b010..FRO-6M
 *  0b000..The clock is off
 */
#define MRCC_MRCC_I3C0_MUX(x)                    (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_I3C0_MUX_SHIFT)) & MRCC_MRCC_I3C0_MUX_MASK)

#define MRCC_MRCC_I3C0_DIV_MASK                  (0xF00U)
#define MRCC_MRCC_I3C0_DIV_SHIFT                 (8U)
/*! DIV - Functional Clock Divider
 */
#define MRCC_MRCC_I3C0_DIV(x)                    (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_I3C0_DIV_SHIFT)) & MRCC_MRCC_I3C0_DIV_MASK)

#define MRCC_MRCC_I3C0_RSTB_MASK                 (0x40000000U)
#define MRCC_MRCC_I3C0_RSTB_SHIFT                (30U)
/*! RSTB - Reset Negation
 *  0b0..Module is held in reset
 *  0b1..Module released from reset
 */
#define MRCC_MRCC_I3C0_RSTB(x)                   (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_I3C0_RSTB_SHIFT)) & MRCC_MRCC_I3C0_RSTB_MASK)

#define MRCC_MRCC_I3C0_PR_MASK                   (0x80000000U)
#define MRCC_MRCC_I3C0_PR_SHIFT                  (31U)
/*! PR - Peripheral Present
 *  0b0..Module is not present; writes to this register are ignored
 *  0b1..Module is present
 */
#define MRCC_MRCC_I3C0_PR(x)                     (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_I3C0_PR_SHIFT)) & MRCC_MRCC_I3C0_PR_MASK)
/*! @} */

/*! @name MRCC_LPSPI0 - LPSPI0 Reset and Clock Control */
/*! @{ */

#define MRCC_MRCC_LPSPI0_CC_MASK                 (0x3U)
#define MRCC_MRCC_LPSPI0_CC_SHIFT                (0U)
/*! CC - Clock Configuration
 *  0b00..Peripheral clocks are disabled; module does not stall low power mode entry
 *  0b01..Peripheral clocks are enabled; module does not stall low power mode entry
 *  0b10..Peripheral clocks are enabled unless module is idle; low power mode entry stalls until module is idle
 *  0b11..Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle.
 */
#define MRCC_MRCC_LPSPI0_CC(x)                   (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI0_CC_SHIFT)) & MRCC_MRCC_LPSPI0_CC_MASK)

#define MRCC_MRCC_LPSPI0_MUX_MASK                (0x70U)
#define MRCC_MRCC_LPSPI0_MUX_SHIFT               (4U)
/*! MUX - Functional Clock Mux Select
 *  0b100..SOSC-CLK
 *  0b011..FRO-192M
 *  0b010..FRO-6M
 *  0b000..The clock is off
 */
#define MRCC_MRCC_LPSPI0_MUX(x)                  (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI0_MUX_SHIFT)) & MRCC_MRCC_LPSPI0_MUX_MASK)

#define MRCC_MRCC_LPSPI0_DIV_MASK                (0xF00U)
#define MRCC_MRCC_LPSPI0_DIV_SHIFT               (8U)
/*! DIV - Functional Clock Divider
 */
#define MRCC_MRCC_LPSPI0_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI0_DIV_SHIFT)) & MRCC_MRCC_LPSPI0_DIV_MASK)

#define MRCC_MRCC_LPSPI0_RSTB_MASK               (0x40000000U)
#define MRCC_MRCC_LPSPI0_RSTB_SHIFT              (30U)
/*! RSTB - Reset Negation
 *  0b0..Module is held in reset
 *  0b1..Module released from reset
 */
#define MRCC_MRCC_LPSPI0_RSTB(x)                 (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI0_RSTB_SHIFT)) & MRCC_MRCC_LPSPI0_RSTB_MASK)

#define MRCC_MRCC_LPSPI0_PR_MASK                 (0x80000000U)
#define MRCC_MRCC_LPSPI0_PR_SHIFT                (31U)
/*! PR - Peripheral Present
 *  0b0..Module is not present; writes to this register are ignored
 *  0b1..Module is present
 */
#define MRCC_MRCC_LPSPI0_PR(x)                   (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI0_PR_SHIFT)) & MRCC_MRCC_LPSPI0_PR_MASK)
/*! @} */

/*! @name MRCC_LPSPI1 - LPSPI1 Reset and Clock Control */
/*! @{ */

#define MRCC_MRCC_LPSPI1_CC_MASK                 (0x3U)
#define MRCC_MRCC_LPSPI1_CC_SHIFT                (0U)
/*! CC - Clock Configuration
 *  0b00..Peripheral clocks are disabled; module does not stall low power mode entry
 *  0b01..Peripheral clocks are enabled; module does not stall low power mode entry
 *  0b10..Peripheral clocks are enabled unless module is idle; low power mode entry stalls until module is idle
 *  0b11..Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle.
 */
#define MRCC_MRCC_LPSPI1_CC(x)                   (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI1_CC_SHIFT)) & MRCC_MRCC_LPSPI1_CC_MASK)

#define MRCC_MRCC_LPSPI1_MUX_MASK                (0x70U)
#define MRCC_MRCC_LPSPI1_MUX_SHIFT               (4U)
/*! MUX - Functional Clock Mux Select
 *  0b100..SOSC-CLK
 *  0b011..FRO-192M
 *  0b010..FRO-6M
 *  0b000..The clock is off
 */
#define MRCC_MRCC_LPSPI1_MUX(x)                  (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI1_MUX_SHIFT)) & MRCC_MRCC_LPSPI1_MUX_MASK)

#define MRCC_MRCC_LPSPI1_DIV_MASK                (0xF00U)
#define MRCC_MRCC_LPSPI1_DIV_SHIFT               (8U)
/*! DIV - Functional Clock Divider
 */
#define MRCC_MRCC_LPSPI1_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI1_DIV_SHIFT)) & MRCC_MRCC_LPSPI1_DIV_MASK)

#define MRCC_MRCC_LPSPI1_RSTB_MASK               (0x40000000U)
#define MRCC_MRCC_LPSPI1_RSTB_SHIFT              (30U)
/*! RSTB - Reset Negation
 *  0b0..Module is held in reset
 *  0b1..Module released from reset
 */
#define MRCC_MRCC_LPSPI1_RSTB(x)                 (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI1_RSTB_SHIFT)) & MRCC_MRCC_LPSPI1_RSTB_MASK)

#define MRCC_MRCC_LPSPI1_PR_MASK                 (0x80000000U)
#define MRCC_MRCC_LPSPI1_PR_SHIFT                (31U)
/*! PR - Peripheral Present
 *  0b0..Module is not present; writes to this register are ignored
 *  0b1..Module is present
 */
#define MRCC_MRCC_LPSPI1_PR(x)                   (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI1_PR_SHIFT)) & MRCC_MRCC_LPSPI1_PR_MASK)
/*! @} */

/*! @name MRCC_LPUART0 - LPUART0 Reset and Clock Control */
/*! @{ */

#define MRCC_MRCC_LPUART0_CC_MASK                (0x3U)
#define MRCC_MRCC_LPUART0_CC_SHIFT               (0U)
/*! CC - Clock Configuration
 *  0b00..Peripheral clocks are disabled; module does not stall low power mode entry
 *  0b01..Peripheral clocks are enabled; module does not stall low power mode entry
 *  0b10..Peripheral clocks are enabled unless module is idle; low power mode entry stalls until module is idle
 *  0b11..Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle.
 */
#define MRCC_MRCC_LPUART0_CC(x)                  (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART0_CC_SHIFT)) & MRCC_MRCC_LPUART0_CC_MASK)

#define MRCC_MRCC_LPUART0_MUX_MASK               (0x70U)
#define MRCC_MRCC_LPUART0_MUX_SHIFT              (4U)
/*! MUX - Functional Clock Mux Select
 *  0b101..32K-CLK
 *  0b100..SOSC-CLK
 *  0b011..FRO-192M
 *  0b010..FRO-6M
 *  0b000..The clock is off
 */
#define MRCC_MRCC_LPUART0_MUX(x)                 (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART0_MUX_SHIFT)) & MRCC_MRCC_LPUART0_MUX_MASK)

#define MRCC_MRCC_LPUART0_DIV_MASK               (0xF00U)
#define MRCC_MRCC_LPUART0_DIV_SHIFT              (8U)
/*! DIV - Functional Clock Divider
 */
#define MRCC_MRCC_LPUART0_DIV(x)                 (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART0_DIV_SHIFT)) & MRCC_MRCC_LPUART0_DIV_MASK)

#define MRCC_MRCC_LPUART0_RSTB_MASK              (0x40000000U)
#define MRCC_MRCC_LPUART0_RSTB_SHIFT             (30U)
/*! RSTB - Reset Negation
 *  0b0..Module is held in reset
 *  0b1..Module released from reset
 */
#define MRCC_MRCC_LPUART0_RSTB(x)                (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART0_RSTB_SHIFT)) & MRCC_MRCC_LPUART0_RSTB_MASK)

#define MRCC_MRCC_LPUART0_PR_MASK                (0x80000000U)
#define MRCC_MRCC_LPUART0_PR_SHIFT               (31U)
/*! PR - Peripheral Present
 *  0b0..Module is not present; writes to this register are ignored
 *  0b1..Module is present
 */
#define MRCC_MRCC_LPUART0_PR(x)                  (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART0_PR_SHIFT)) & MRCC_MRCC_LPUART0_PR_MASK)
/*! @} */

/*! @name MRCC_LPUART1 - LPUART1 Reset and Clock Control */
/*! @{ */

#define MRCC_MRCC_LPUART1_CC_MASK                (0x3U)
#define MRCC_MRCC_LPUART1_CC_SHIFT               (0U)
/*! CC - Clock Configuration
 *  0b00..Peripheral clocks are disabled; module does not stall low power mode entry
 *  0b01..Peripheral clocks are enabled; module does not stall low power mode entry
 *  0b10..Peripheral clocks are enabled unless module is idle; low power mode entry stalls until module is idle
 *  0b11..Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle.
 */
#define MRCC_MRCC_LPUART1_CC(x)                  (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART1_CC_SHIFT)) & MRCC_MRCC_LPUART1_CC_MASK)

#define MRCC_MRCC_LPUART1_MUX_MASK               (0x70U)
#define MRCC_MRCC_LPUART1_MUX_SHIFT              (4U)
/*! MUX - Functional Clock Mux Select
 *  0b101..32K-CLK
 *  0b100..SOSC-CLK
 *  0b011..FRO-192M
 *  0b010..FRO-6M
 *  0b000..The clock is off
 */
#define MRCC_MRCC_LPUART1_MUX(x)                 (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART1_MUX_SHIFT)) & MRCC_MRCC_LPUART1_MUX_MASK)

#define MRCC_MRCC_LPUART1_DIV_MASK               (0xF00U)
#define MRCC_MRCC_LPUART1_DIV_SHIFT              (8U)
/*! DIV - Functional Clock Divider
 */
#define MRCC_MRCC_LPUART1_DIV(x)                 (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART1_DIV_SHIFT)) & MRCC_MRCC_LPUART1_DIV_MASK)

#define MRCC_MRCC_LPUART1_RSTB_MASK              (0x40000000U)
#define MRCC_MRCC_LPUART1_RSTB_SHIFT             (30U)
/*! RSTB - Reset Negation
 *  0b0..Module is held in reset
 *  0b1..Module released from reset
 */
#define MRCC_MRCC_LPUART1_RSTB(x)                (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART1_RSTB_SHIFT)) & MRCC_MRCC_LPUART1_RSTB_MASK)

#define MRCC_MRCC_LPUART1_PR_MASK                (0x80000000U)
#define MRCC_MRCC_LPUART1_PR_SHIFT               (31U)
/*! PR - Peripheral Present
 *  0b0..Module is not present; writes to this register are ignored
 *  0b1..Module is present
 */
#define MRCC_MRCC_LPUART1_PR(x)                  (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART1_PR_SHIFT)) & MRCC_MRCC_LPUART1_PR_MASK)
/*! @} */

/*! @name MRCC_FLEXIO0 - FLEXIO0 Reset and Clock Control */
/*! @{ */

#define MRCC_MRCC_FLEXIO0_CC_MASK                (0x3U)
#define MRCC_MRCC_FLEXIO0_CC_SHIFT               (0U)
/*! CC - Clock Configuration
 *  0b00..Peripheral clocks are disabled; module does not stall low power mode entry
 *  0b01..Peripheral clocks are enabled; module does not stall low power mode entry
 *  0b10..Peripheral clocks are enabled unless module is idle; low power mode entry stalls until module is idle
 *  0b11..Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle.
 */
#define MRCC_MRCC_FLEXIO0_CC(x)                  (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_FLEXIO0_CC_SHIFT)) & MRCC_MRCC_FLEXIO0_CC_MASK)

#define MRCC_MRCC_FLEXIO0_MUX_MASK               (0x70U)
#define MRCC_MRCC_FLEXIO0_MUX_SHIFT              (4U)
/*! MUX - Functional Clock Mux Select
 *  0b100..SOSC-CLK
 *  0b011..FRO-192M
 *  0b010..FRO-6M
 *  0b000..The clock is off
 */
#define MRCC_MRCC_FLEXIO0_MUX(x)                 (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_FLEXIO0_MUX_SHIFT)) & MRCC_MRCC_FLEXIO0_MUX_MASK)

#define MRCC_MRCC_FLEXIO0_DIV_MASK               (0xF00U)
#define MRCC_MRCC_FLEXIO0_DIV_SHIFT              (8U)
/*! DIV - Functional Clock Divider
 */
#define MRCC_MRCC_FLEXIO0_DIV(x)                 (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_FLEXIO0_DIV_SHIFT)) & MRCC_MRCC_FLEXIO0_DIV_MASK)

#define MRCC_MRCC_FLEXIO0_RSTB_MASK              (0x40000000U)
#define MRCC_MRCC_FLEXIO0_RSTB_SHIFT             (30U)
/*! RSTB - Reset Negation
 *  0b0..Module is held in reset
 *  0b1..Module released from reset
 */
#define MRCC_MRCC_FLEXIO0_RSTB(x)                (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_FLEXIO0_RSTB_SHIFT)) & MRCC_MRCC_FLEXIO0_RSTB_MASK)

#define MRCC_MRCC_FLEXIO0_PR_MASK                (0x80000000U)
#define MRCC_MRCC_FLEXIO0_PR_SHIFT               (31U)
/*! PR - Peripheral Present
 *  0b0..Module is not present; writes to this register are ignored
 *  0b1..Module is present
 */
#define MRCC_MRCC_FLEXIO0_PR(x)                  (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_FLEXIO0_PR_SHIFT)) & MRCC_MRCC_FLEXIO0_PR_MASK)
/*! @} */

/*! @name MRCC_CAN0 - CAN0 Reset and Clock Control */
/*! @{ */

#define MRCC_MRCC_CAN0_CC_MASK                   (0x3U)
#define MRCC_MRCC_CAN0_CC_SHIFT                  (0U)
/*! CC - Clock Configuration
 *  0b00..Peripheral clocks are disabled; module does not stall low power mode entry
 *  0b01..Peripheral clocks are enabled; module does not stall low power mode entry
 *  0b10..Reserved
 *  0b11..Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle.
 */
#define MRCC_MRCC_CAN0_CC(x)                     (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CAN0_CC_SHIFT)) & MRCC_MRCC_CAN0_CC_MASK)

#define MRCC_MRCC_CAN0_MUX_MASK                  (0x70U)
#define MRCC_MRCC_CAN0_MUX_SHIFT                 (4U)
/*! MUX - Functional Clock Mux Select
 *  0b100..SOSC-CLK
 *  0b011..FRO-192M
 *  0b000..The clock is off
 */
#define MRCC_MRCC_CAN0_MUX(x)                    (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CAN0_MUX_SHIFT)) & MRCC_MRCC_CAN0_MUX_MASK)

#define MRCC_MRCC_CAN0_DIV_MASK                  (0xF00U)
#define MRCC_MRCC_CAN0_DIV_SHIFT                 (8U)
/*! DIV - Functional Clock Divider
 */
#define MRCC_MRCC_CAN0_DIV(x)                    (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CAN0_DIV_SHIFT)) & MRCC_MRCC_CAN0_DIV_MASK)

#define MRCC_MRCC_CAN0_RSTB_MASK                 (0x40000000U)
#define MRCC_MRCC_CAN0_RSTB_SHIFT                (30U)
/*! RSTB - Reset Negation
 *  0b0..Module is held in reset
 *  0b1..Module released from reset
 */
#define MRCC_MRCC_CAN0_RSTB(x)                   (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CAN0_RSTB_SHIFT)) & MRCC_MRCC_CAN0_RSTB_MASK)

#define MRCC_MRCC_CAN0_PR_MASK                   (0x80000000U)
#define MRCC_MRCC_CAN0_PR_SHIFT                  (31U)
/*! PR - Peripheral Present
 *  0b0..Module is not present; writes to this register are ignored
 *  0b1..Module is present
 */
#define MRCC_MRCC_CAN0_PR(x)                     (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CAN0_PR_SHIFT)) & MRCC_MRCC_CAN0_PR_MASK)
/*! @} */

/*! @name MRCC_SEMA0 - SEMA42 Reset and Clock Control */
/*! @{ */

#define MRCC_MRCC_SEMA0_CC_MASK                  (0x3U)
#define MRCC_MRCC_SEMA0_CC_SHIFT                 (0U)
/*! CC - Clock Configuration
 *  0b00..Peripheral clocks are disabled; module does not stall low power mode entry
 *  0b01..Peripheral clocks are enabled; module does not stall low power mode entry
 *  0b10..Reserved
 *  0b11..Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle.
 */
#define MRCC_MRCC_SEMA0_CC(x)                    (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_SEMA0_CC_SHIFT)) & MRCC_MRCC_SEMA0_CC_MASK)

#define MRCC_MRCC_SEMA0_RSTB_MASK                (0x40000000U)
#define MRCC_MRCC_SEMA0_RSTB_SHIFT               (30U)
/*! RSTB - Reset Negation
 *  0b0..Module is held in reset
 *  0b1..Module released from reset
 */
#define MRCC_MRCC_SEMA0_RSTB(x)                  (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_SEMA0_RSTB_SHIFT)) & MRCC_MRCC_SEMA0_RSTB_MASK)

#define MRCC_MRCC_SEMA0_PR_MASK                  (0x80000000U)
#define MRCC_MRCC_SEMA0_PR_SHIFT                 (31U)
/*! PR - Peripheral Present
 *  0b0..Module is not present; writes to this register are ignored
 *  0b1..Module is present
 */
#define MRCC_MRCC_SEMA0_PR(x)                    (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_SEMA0_PR_SHIFT)) & MRCC_MRCC_SEMA0_PR_MASK)
/*! @} */

/*! @name MRCC_DATA_STREAM_2P4 - DSB Reset and Clock Control */
/*! @{ */

#define MRCC_MRCC_DATA_STREAM_2P4_CC_MASK        (0x3U)
#define MRCC_MRCC_DATA_STREAM_2P4_CC_SHIFT       (0U)
/*! CC - Clock Configuration
 *  0b00..Peripheral clocks are disabled; module does not stall low power mode entry
 *  0b01..Peripheral clocks are enabled; module does not stall low power mode entry
 *  0b10..Reserved
 *  0b11..Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle.
 */
#define MRCC_MRCC_DATA_STREAM_2P4_CC(x)          (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_DATA_STREAM_2P4_CC_SHIFT)) & MRCC_MRCC_DATA_STREAM_2P4_CC_MASK)

#define MRCC_MRCC_DATA_STREAM_2P4_RSTB_MASK      (0x40000000U)
#define MRCC_MRCC_DATA_STREAM_2P4_RSTB_SHIFT     (30U)
/*! RSTB - Reset Negation
 *  0b0..Module is held in reset
 *  0b1..Module released from reset
 */
#define MRCC_MRCC_DATA_STREAM_2P4_RSTB(x)        (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_DATA_STREAM_2P4_RSTB_SHIFT)) & MRCC_MRCC_DATA_STREAM_2P4_RSTB_MASK)

#define MRCC_MRCC_DATA_STREAM_2P4_PR_MASK        (0x80000000U)
#define MRCC_MRCC_DATA_STREAM_2P4_PR_SHIFT       (31U)
/*! PR - Peripheral Present
 *  0b0..Module is not present; writes to this register are ignored
 *  0b1..Module is present
 */
#define MRCC_MRCC_DATA_STREAM_2P4_PR(x)          (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_DATA_STREAM_2P4_PR_SHIFT)) & MRCC_MRCC_DATA_STREAM_2P4_PR_MASK)
/*! @} */

/*! @name MRCC_PORTA - PORTA Reset and Clock Control */
/*! @{ */

#define MRCC_MRCC_PORTA_CC_MASK                  (0x3U)
#define MRCC_MRCC_PORTA_CC_SHIFT                 (0U)
/*! CC - Clock Configuration
 *  0b00..Peripheral clocks are disabled; module does not stall low power mode entry
 *  0b01..Peripheral clocks are enabled; module does not stall low power mode entry
 *  0b10..Reserved
 *  0b11..Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle.
 */
#define MRCC_MRCC_PORTA_CC(x)                    (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_PORTA_CC_SHIFT)) & MRCC_MRCC_PORTA_CC_MASK)

#define MRCC_MRCC_PORTA_RSTB_MASK                (0x40000000U)
#define MRCC_MRCC_PORTA_RSTB_SHIFT               (30U)
/*! RSTB - Reset Negation
 *  0b0..Module is held in reset
 *  0b1..Module released from reset
 */
#define MRCC_MRCC_PORTA_RSTB(x)                  (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_PORTA_RSTB_SHIFT)) & MRCC_MRCC_PORTA_RSTB_MASK)

#define MRCC_MRCC_PORTA_PR_MASK                  (0x80000000U)
#define MRCC_MRCC_PORTA_PR_SHIFT                 (31U)
/*! PR - Peripheral Present
 *  0b0..Module is not present; writes to this register are ignored
 *  0b1..Module is present
 */
#define MRCC_MRCC_PORTA_PR(x)                    (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_PORTA_PR_SHIFT)) & MRCC_MRCC_PORTA_PR_MASK)
/*! @} */

/*! @name MRCC_PORTB - PORTB Reset and Clock Control */
/*! @{ */

#define MRCC_MRCC_PORTB_CC_MASK                  (0x3U)
#define MRCC_MRCC_PORTB_CC_SHIFT                 (0U)
/*! CC - Clock Configuration
 *  0b00..Peripheral clocks are disabled; module does not stall low power mode entry
 *  0b01..Peripheral clocks are enabled; module does not stall low power mode entry
 *  0b10..Reserved
 *  0b11..Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle.
 */
#define MRCC_MRCC_PORTB_CC(x)                    (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_PORTB_CC_SHIFT)) & MRCC_MRCC_PORTB_CC_MASK)

#define MRCC_MRCC_PORTB_RSTB_MASK                (0x40000000U)
#define MRCC_MRCC_PORTB_RSTB_SHIFT               (30U)
/*! RSTB - Reset Negation
 *  0b0..Module is held in reset
 *  0b1..Module released from reset
 */
#define MRCC_MRCC_PORTB_RSTB(x)                  (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_PORTB_RSTB_SHIFT)) & MRCC_MRCC_PORTB_RSTB_MASK)

#define MRCC_MRCC_PORTB_PR_MASK                  (0x80000000U)
#define MRCC_MRCC_PORTB_PR_SHIFT                 (31U)
/*! PR - Peripheral Present
 *  0b0..Module is not present; writes to this register are ignored
 *  0b1..Module is present
 */
#define MRCC_MRCC_PORTB_PR(x)                    (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_PORTB_PR_SHIFT)) & MRCC_MRCC_PORTB_PR_MASK)
/*! @} */

/*! @name MRCC_PORTC - PORTC Reset and Clock Control */
/*! @{ */

#define MRCC_MRCC_PORTC_CC_MASK                  (0x3U)
#define MRCC_MRCC_PORTC_CC_SHIFT                 (0U)
/*! CC - Clock Configuration
 *  0b00..Peripheral clocks are disabled; module does not stall low power mode entry
 *  0b01..Peripheral clocks are enabled; module does not stall low power mode entry
 *  0b10..Reserved
 *  0b11..Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle.
 */
#define MRCC_MRCC_PORTC_CC(x)                    (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_PORTC_CC_SHIFT)) & MRCC_MRCC_PORTC_CC_MASK)

#define MRCC_MRCC_PORTC_RSTB_MASK                (0x40000000U)
#define MRCC_MRCC_PORTC_RSTB_SHIFT               (30U)
/*! RSTB - Reset Negation
 *  0b0..Module is held in reset
 *  0b1..Module released from reset
 */
#define MRCC_MRCC_PORTC_RSTB(x)                  (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_PORTC_RSTB_SHIFT)) & MRCC_MRCC_PORTC_RSTB_MASK)

#define MRCC_MRCC_PORTC_PR_MASK                  (0x80000000U)
#define MRCC_MRCC_PORTC_PR_SHIFT                 (31U)
/*! PR - Peripheral Present
 *  0b0..Module is not present; writes to this register are ignored
 *  0b1..Module is present
 */
#define MRCC_MRCC_PORTC_PR(x)                    (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_PORTC_PR_SHIFT)) & MRCC_MRCC_PORTC_PR_MASK)
/*! @} */

/*! @name MRCC_LPADC0 - ADC0 Reset and Clock Control */
/*! @{ */

#define MRCC_MRCC_LPADC0_CC_MASK                 (0x3U)
#define MRCC_MRCC_LPADC0_CC_SHIFT                (0U)
/*! CC - Clock Configuration
 *  0b00..Peripheral clocks are disabled; module does not stall low power mode entry
 *  0b01..Peripheral clocks are enabled; module does not stall low power mode entry
 *  0b10..Reserved
 *  0b11..Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle.
 */
#define MRCC_MRCC_LPADC0_CC(x)                   (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPADC0_CC_SHIFT)) & MRCC_MRCC_LPADC0_CC_MASK)

#define MRCC_MRCC_LPADC0_MUX_MASK                (0x70U)
#define MRCC_MRCC_LPADC0_MUX_SHIFT               (4U)
/*! MUX - Functional Clock Mux Select
 *  0b100..SOSC-CLK
 *  0b011..FRO-192M
 *  0b010..FRO-6M
 *  0b000..The clock is off
 */
#define MRCC_MRCC_LPADC0_MUX(x)                  (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPADC0_MUX_SHIFT)) & MRCC_MRCC_LPADC0_MUX_MASK)

#define MRCC_MRCC_LPADC0_DIV_MASK                (0xF00U)
#define MRCC_MRCC_LPADC0_DIV_SHIFT               (8U)
/*! DIV - Functional Clock Divider
 */
#define MRCC_MRCC_LPADC0_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPADC0_DIV_SHIFT)) & MRCC_MRCC_LPADC0_DIV_MASK)

#define MRCC_MRCC_LPADC0_RSTB_MASK               (0x40000000U)
#define MRCC_MRCC_LPADC0_RSTB_SHIFT              (30U)
/*! RSTB - Reset Negation
 *  0b0..Module is held in reset
 *  0b1..Module released from reset
 */
#define MRCC_MRCC_LPADC0_RSTB(x)                 (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPADC0_RSTB_SHIFT)) & MRCC_MRCC_LPADC0_RSTB_MASK)

#define MRCC_MRCC_LPADC0_PR_MASK                 (0x80000000U)
#define MRCC_MRCC_LPADC0_PR_SHIFT                (31U)
/*! PR - Peripheral Present
 *  0b0..Module is not present; writes to this register are ignored
 *  0b1..Module is present
 */
#define MRCC_MRCC_LPADC0_PR(x)                   (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPADC0_PR_SHIFT)) & MRCC_MRCC_LPADC0_PR_MASK)
/*! @} */

/*! @name MRCC_LPCMP0 - LPCMP0 Reset and Clock Control */
/*! @{ */

#define MRCC_MRCC_LPCMP0_CC_MASK                 (0x3U)
#define MRCC_MRCC_LPCMP0_CC_SHIFT                (0U)
/*! CC - Clock Configuration
 *  0b00..Peripheral clocks are disabled; module does not stall low power mode entry
 *  0b01..Peripheral clocks are enabled; module does not stall low power mode entry
 *  0b10..Reserved
 *  0b11..Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle.
 */
#define MRCC_MRCC_LPCMP0_CC(x)                   (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPCMP0_CC_SHIFT)) & MRCC_MRCC_LPCMP0_CC_MASK)

#define MRCC_MRCC_LPCMP0_RSTB_MASK               (0x40000000U)
#define MRCC_MRCC_LPCMP0_RSTB_SHIFT              (30U)
/*! RSTB - Reset Negation
 *  0b0..Module is held in reset
 *  0b1..Module released from reset
 */
#define MRCC_MRCC_LPCMP0_RSTB(x)                 (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPCMP0_RSTB_SHIFT)) & MRCC_MRCC_LPCMP0_RSTB_MASK)

#define MRCC_MRCC_LPCMP0_PR_MASK                 (0x80000000U)
#define MRCC_MRCC_LPCMP0_PR_SHIFT                (31U)
/*! PR - Peripheral Present
 *  0b0..Module is not present; writes to this register are ignored
 *  0b1..Module is present
 */
#define MRCC_MRCC_LPCMP0_PR(x)                   (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPCMP0_PR_SHIFT)) & MRCC_MRCC_LPCMP0_PR_MASK)
/*! @} */

/*! @name MRCC_LPCMP1 - LPCMP1 Reset and Clock Control */
/*! @{ */

#define MRCC_MRCC_LPCMP1_CC_MASK                 (0x3U)
#define MRCC_MRCC_LPCMP1_CC_SHIFT                (0U)
/*! CC - Clock Configuration
 *  0b00..Peripheral clocks are disabled; module does not stall low power mode entry
 *  0b01..Peripheral clocks are enabled; module does not stall low power mode entry
 *  0b10..Reserved
 *  0b11..Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle.
 */
#define MRCC_MRCC_LPCMP1_CC(x)                   (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPCMP1_CC_SHIFT)) & MRCC_MRCC_LPCMP1_CC_MASK)

#define MRCC_MRCC_LPCMP1_RSTB_MASK               (0x40000000U)
#define MRCC_MRCC_LPCMP1_RSTB_SHIFT              (30U)
/*! RSTB - Reset Negation
 *  0b0..Module is held in reset
 *  0b1..Module released from reset
 */
#define MRCC_MRCC_LPCMP1_RSTB(x)                 (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPCMP1_RSTB_SHIFT)) & MRCC_MRCC_LPCMP1_RSTB_MASK)

#define MRCC_MRCC_LPCMP1_PR_MASK                 (0x80000000U)
#define MRCC_MRCC_LPCMP1_PR_SHIFT                (31U)
/*! PR - Peripheral Present
 *  0b0..Module is not present; writes to this register are ignored
 *  0b1..Module is present
 */
#define MRCC_MRCC_LPCMP1_PR(x)                   (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPCMP1_PR_SHIFT)) & MRCC_MRCC_LPCMP1_PR_MASK)
/*! @} */

/*! @name MRCC_VREF0 - VREF0 Reset and Clock Control */
/*! @{ */

#define MRCC_MRCC_VREF0_CC_MASK                  (0x3U)
#define MRCC_MRCC_VREF0_CC_SHIFT                 (0U)
/*! CC - Clock Configuration
 *  0b00..Peripheral clocks are disabled; module does not stall low power mode entry
 *  0b01..Peripheral clocks are enabled; module does not stall low power mode entry
 *  0b10..Reserved
 *  0b11..Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle.
 */
#define MRCC_MRCC_VREF0_CC(x)                    (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_VREF0_CC_SHIFT)) & MRCC_MRCC_VREF0_CC_MASK)

#define MRCC_MRCC_VREF0_RSTB_MASK                (0x40000000U)
#define MRCC_MRCC_VREF0_RSTB_SHIFT               (30U)
/*! RSTB - Reset Negation
 *  0b0..Module is held in reset
 *  0b1..Module released from reset
 */
#define MRCC_MRCC_VREF0_RSTB(x)                  (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_VREF0_RSTB_SHIFT)) & MRCC_MRCC_VREF0_RSTB_MASK)

#define MRCC_MRCC_VREF0_PR_MASK                  (0x80000000U)
#define MRCC_MRCC_VREF0_PR_SHIFT                 (31U)
/*! PR - Peripheral Present
 *  0b0..Module is not present; writes to this register are ignored
 *  0b1..Module is present
 */
#define MRCC_MRCC_VREF0_PR(x)                    (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_VREF0_PR_SHIFT)) & MRCC_MRCC_VREF0_PR_MASK)
/*! @} */

/*! @name MRCC_GPIOA - GPIOA Reset and Clock Control */
/*! @{ */

#define MRCC_MRCC_GPIOA_CC_MASK                  (0x3U)
#define MRCC_MRCC_GPIOA_CC_SHIFT                 (0U)
/*! CC - Clock Configuration
 *  0b00..Peripheral clocks are disabled; module does not stall low power mode entry
 *  0b01..Peripheral clocks are enabled; module does not stall low power mode entry
 *  0b10..Peripheral clocks are enabled unless module is idle; low power mode entry stalls until module is idle
 *  0b11..Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle.
 */
#define MRCC_MRCC_GPIOA_CC(x)                    (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GPIOA_CC_SHIFT)) & MRCC_MRCC_GPIOA_CC_MASK)

#define MRCC_MRCC_GPIOA_RSTB_MASK                (0x40000000U)
#define MRCC_MRCC_GPIOA_RSTB_SHIFT               (30U)
/*! RSTB - Reset Negation
 *  0b0..Module is held in reset
 *  0b1..Module released from reset
 */
#define MRCC_MRCC_GPIOA_RSTB(x)                  (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GPIOA_RSTB_SHIFT)) & MRCC_MRCC_GPIOA_RSTB_MASK)

#define MRCC_MRCC_GPIOA_PR_MASK                  (0x80000000U)
#define MRCC_MRCC_GPIOA_PR_SHIFT                 (31U)
/*! PR - Peripheral Present
 *  0b0..Module is not present; writes to this register are ignored
 *  0b1..Module is present
 */
#define MRCC_MRCC_GPIOA_PR(x)                    (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GPIOA_PR_SHIFT)) & MRCC_MRCC_GPIOA_PR_MASK)
/*! @} */

/*! @name MRCC_GPIOB - GPIOB Reset and Clock Control */
/*! @{ */

#define MRCC_MRCC_GPIOB_CC_MASK                  (0x3U)
#define MRCC_MRCC_GPIOB_CC_SHIFT                 (0U)
/*! CC - Clock Configuration
 *  0b00..Peripheral clocks are disabled; module does not stall low power mode entry
 *  0b01..Peripheral clocks are enabled; module does not stall low power mode entry
 *  0b10..Peripheral clocks are enabled unless module is idle; low power mode entry stalls until module is idle
 *  0b11..Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle.
 */
#define MRCC_MRCC_GPIOB_CC(x)                    (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GPIOB_CC_SHIFT)) & MRCC_MRCC_GPIOB_CC_MASK)

#define MRCC_MRCC_GPIOB_RSTB_MASK                (0x40000000U)
#define MRCC_MRCC_GPIOB_RSTB_SHIFT               (30U)
/*! RSTB - Reset Negation
 *  0b0..Module is held in reset
 *  0b1..Module released from reset
 */
#define MRCC_MRCC_GPIOB_RSTB(x)                  (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GPIOB_RSTB_SHIFT)) & MRCC_MRCC_GPIOB_RSTB_MASK)

#define MRCC_MRCC_GPIOB_PR_MASK                  (0x80000000U)
#define MRCC_MRCC_GPIOB_PR_SHIFT                 (31U)
/*! PR - Peripheral Present
 *  0b0..Module is not present; writes to this register are ignored
 *  0b1..Module is present
 */
#define MRCC_MRCC_GPIOB_PR(x)                    (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GPIOB_PR_SHIFT)) & MRCC_MRCC_GPIOB_PR_MASK)
/*! @} */

/*! @name MRCC_GPIOC - GPIOC Reset and Clock Control */
/*! @{ */

#define MRCC_MRCC_GPIOC_CC_MASK                  (0x3U)
#define MRCC_MRCC_GPIOC_CC_SHIFT                 (0U)
/*! CC - Clock Configuration
 *  0b00..Peripheral clocks are disabled; module does not stall low power mode entry
 *  0b01..Peripheral clocks are enabled; module does not stall low power mode entry
 *  0b10..Peripheral clocks are enabled unless module is idle; low power mode entry stalls until module is idle
 *  0b11..Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle.
 */
#define MRCC_MRCC_GPIOC_CC(x)                    (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GPIOC_CC_SHIFT)) & MRCC_MRCC_GPIOC_CC_MASK)

#define MRCC_MRCC_GPIOC_RSTB_MASK                (0x40000000U)
#define MRCC_MRCC_GPIOC_RSTB_SHIFT               (30U)
/*! RSTB - Reset Negation
 *  0b0..Module is held in reset
 *  0b1..Module released from reset
 */
#define MRCC_MRCC_GPIOC_RSTB(x)                  (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GPIOC_RSTB_SHIFT)) & MRCC_MRCC_GPIOC_RSTB_MASK)

#define MRCC_MRCC_GPIOC_PR_MASK                  (0x80000000U)
#define MRCC_MRCC_GPIOC_PR_SHIFT                 (31U)
/*! PR - Peripheral Present
 *  0b0..Module is not present; writes to this register are ignored
 *  0b1..Module is present
 */
#define MRCC_MRCC_GPIOC_PR(x)                    (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GPIOC_PR_SHIFT)) & MRCC_MRCC_GPIOC_PR_MASK)
/*! @} */

/*! @name MRCC_DMA0 - DMA0 Reset and Clock Control */
/*! @{ */

#define MRCC_MRCC_DMA0_CC_MASK                   (0x3U)
#define MRCC_MRCC_DMA0_CC_SHIFT                  (0U)
/*! CC - Clock Configuration
 *  0b00..Peripheral clocks are disabled; module does not stall low power mode entry
 *  0b01..Peripheral clocks are enabled; module does not stall low power mode entry
 *  0b10..Reserved
 *  0b11..Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle.
 */
#define MRCC_MRCC_DMA0_CC(x)                     (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_DMA0_CC_SHIFT)) & MRCC_MRCC_DMA0_CC_MASK)

#define MRCC_MRCC_DMA0_RSTB_MASK                 (0x40000000U)
#define MRCC_MRCC_DMA0_RSTB_SHIFT                (30U)
/*! RSTB - Reset Negation
 *  0b0..Module is held in reset
 *  0b1..Module released from reset
 */
#define MRCC_MRCC_DMA0_RSTB(x)                   (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_DMA0_RSTB_SHIFT)) & MRCC_MRCC_DMA0_RSTB_MASK)

#define MRCC_MRCC_DMA0_PR_MASK                   (0x80000000U)
#define MRCC_MRCC_DMA0_PR_SHIFT                  (31U)
/*! PR - Peripheral Present
 *  0b0..Module is not present; writes to this register are ignored
 *  0b1..Module is present
 */
#define MRCC_MRCC_DMA0_PR(x)                     (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_DMA0_PR_SHIFT)) & MRCC_MRCC_DMA0_PR_MASK)
/*! @} */

/*! @name MRCC_PFLEXNVM - FMC-NPX Reset and Clock Control */
/*! @{ */

#define MRCC_MRCC_PFLEXNVM_CC_MASK               (0x3U)
#define MRCC_MRCC_PFLEXNVM_CC_SHIFT              (0U)
/*! CC - Clock Configuration
 *  0b00..Peripheral clocks are disabled; module does not stall low power mode entry
 *  0b01..Peripheral clocks are enabled; module does not stall low power mode entry
 *  0b10..Reserved
 *  0b11..Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle.
 */
#define MRCC_MRCC_PFLEXNVM_CC(x)                 (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_PFLEXNVM_CC_SHIFT)) & MRCC_MRCC_PFLEXNVM_CC_MASK)
/*! @} */

/*! @name MRCC_SRAM0 - CTCM Reset and Clock Control */
/*! @{ */

#define MRCC_MRCC_SRAM0_CC_MASK                  (0x3U)
#define MRCC_MRCC_SRAM0_CC_SHIFT                 (0U)
/*! CC - Clock Configuration
 *  0b00..Peripheral clocks are disabled; module does not stall low power mode entry
 *  0b01..Peripheral clocks are enabled; module does not stall low power mode entry
 *  0b10..Peripheral clocks are enabled unless module is idle; low power mode entry stalls until module is idle
 *  0b11..Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle.
 */
#define MRCC_MRCC_SRAM0_CC(x)                    (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_SRAM0_CC_SHIFT)) & MRCC_MRCC_SRAM0_CC_MASK)
/*! @} */

/*! @name MRCC_SRAM1 - STCM0 Reset and Clock Control */
/*! @{ */

#define MRCC_MRCC_SRAM1_CC_MASK                  (0x3U)
#define MRCC_MRCC_SRAM1_CC_SHIFT                 (0U)
/*! CC - Clock Configuration
 *  0b00..Peripheral clocks are disabled; module does not stall low power mode entry
 *  0b01..Peripheral clocks are enabled; module does not stall low power mode entry
 *  0b10..Peripheral clocks are enabled unless module is idle; low power mode entry stalls until module is idle
 *  0b11..Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle.
 */
#define MRCC_MRCC_SRAM1_CC(x)                    (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_SRAM1_CC_SHIFT)) & MRCC_MRCC_SRAM1_CC_MASK)
/*! @} */

/*! @name MRCC_SRAM2 - STCM1 Reset and Clock Control */
/*! @{ */

#define MRCC_MRCC_SRAM2_CC_MASK                  (0x3U)
#define MRCC_MRCC_SRAM2_CC_SHIFT                 (0U)
/*! CC - Clock Configuration
 *  0b00..Peripheral clocks are disabled; module does not stall low power mode entry
 *  0b01..Peripheral clocks are enabled; module does not stall low power mode entry
 *  0b10..Peripheral clocks are enabled unless module is idle; low power mode entry stalls until module is idle
 *  0b11..Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle.
 */
#define MRCC_MRCC_SRAM2_CC(x)                    (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_SRAM2_CC_SHIFT)) & MRCC_MRCC_SRAM2_CC_MASK)
/*! @} */

/*! @name MRCC_SRAM3 - STCM2 Reset and Clock Control */
/*! @{ */

#define MRCC_MRCC_SRAM3_CC_MASK                  (0x3U)
#define MRCC_MRCC_SRAM3_CC_SHIFT                 (0U)
/*! CC - Clock Configuration
 *  0b00..Peripheral clocks are disabled; module does not stall low power mode entry
 *  0b01..Peripheral clocks are enabled; module does not stall low power mode entry
 *  0b10..Peripheral clocks are enabled unless module is idle; low power mode entry stalls until module is idle
 *  0b11..Peripheral clocks are enabled unless in SLEEP (or lower) mode; low power mode entry stalls until module is idle.
 */
#define MRCC_MRCC_SRAM3_CC(x)                    (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_SRAM3_CC_SHIFT)) & MRCC_MRCC_SRAM3_CC_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group MRCC_Register_Masks */


/* MRCC - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral MRCC base address */
  #define MRCC_BASE                                (0x5001C000u)
  /** Peripheral MRCC base address */
  #define MRCC_BASE_NS                             (0x4001C000u)
  /** Peripheral MRCC base pointer */
  #define MRCC                                     ((MRCC_Type *)MRCC_BASE)
  /** Peripheral MRCC base pointer */
  #define MRCC_NS                                  ((MRCC_Type *)MRCC_BASE_NS)
  /** Array initializer of MRCC peripheral base addresses */
  #define MRCC_BASE_ADDRS                          { MRCC_BASE }
  /** Array initializer of MRCC peripheral base pointers */
  #define MRCC_BASE_PTRS                           { MRCC }
  /** Array initializer of MRCC peripheral base addresses */
  #define MRCC_BASE_ADDRS_NS                       { MRCC_BASE_NS }
  /** Array initializer of MRCC peripheral base pointers */
  #define MRCC_BASE_PTRS_NS                        { MRCC_NS }
#else
  /** Peripheral MRCC base address */
  #define MRCC_BASE                                (0x4001C000u)
  /** Peripheral MRCC base pointer */
  #define MRCC                                     ((MRCC_Type *)MRCC_BASE)
  /** Array initializer of MRCC peripheral base addresses */
  #define MRCC_BASE_ADDRS                          { MRCC_BASE }
  /** Array initializer of MRCC peripheral base pointers */
  #define MRCC_BASE_PTRS                           { MRCC }
#endif
/* Backward compatibility */
#define MRCC_CC_MASK                              (0x3U)
#define MRCC_CC_SHIFT                             (0U)
#define MRCC_CC(x)                                (((uint32_t)(((uint32_t)(x)) << MRCC_CC_SHIFT))  & MRCC_CC_MASK)
#define MRCC_MUX_MASK                             (0x70U)
#define MRCC_MUX_SHIFT                            (4U)
#define MRCC_MUX(x)                               (((uint32_t)(((uint32_t)(x)) << MRCC_MUX_SHIFT))  & MRCC_MUX_MASK)
#define MRCC_DIV_MASK                             (0xF00U)
#define MRCC_DIV_SHIFT                            (8U)
#define MRCC_DIV(x)                               (((uint32_t)(((uint32_t)(x)) << MRCC_DIV_SHIFT))  & MRCC_DIV_MASK)
#define MRCC_RSTB_MASK                            (0x40000000U)
#define MRCC_RSTB_SHIFT                           (30U)
#define MRCC_RSTB(x)                              (((uint32_t)(((uint32_t)(x)) << MRCC_RSTB_SHIFT)) & MRCC_RSTB_MASK)
#define MRCC_PR_MASK                              (0x80000000U)
#define MRCC_PR_SHIFT                             (31U)
#define MRCC_PR(x)                                (((uint32_t)(((uint32_t)(x)) << MRCC_PR_SHIFT))  & MRCC_PR_MASK)


/*!
 * @}
 */ /* end of group MRCC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- MSCM Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup MSCM_Peripheral_Access_Layer MSCM Peripheral Access Layer
 * @{
 */

/** MSCM - Register Layout Typedef */
typedef struct {
  __I  uint32_t CPXTYPE;                           /**< Processor X Type Register, offset: 0x0 */
  __I  uint32_t CPXNUM;                            /**< Processor X Number Register, offset: 0x4 */
  __I  uint32_t CPXMASTER;                         /**< Processor X Master Register, offset: 0x8 */
  __I  uint32_t CPXCOUNT;                          /**< Processor X Count Register, offset: 0xC */
  __I  uint32_t CPXCFG0;                           /**< Processor X Configuration Register 0, offset: 0x10 */
  __I  uint32_t CPXCFG1;                           /**< Processor X Configuration Register 1, offset: 0x14 */
  __I  uint32_t CPXCFG2;                           /**< Processor X Configuration Register 2, offset: 0x18 */
  __I  uint32_t CPXCFG3;                           /**< Processor X Configuration Register 3, offset: 0x1C */
  __I  uint32_t CP0TYPE;                           /**< Processor 0 Type Register, offset: 0x20 */
  __I  uint32_t CP0NUM;                            /**< Processor 0 Number Register, offset: 0x24 */
  __I  uint32_t CP0MASTER;                         /**< Processor 0 Master Register, offset: 0x28 */
  __I  uint32_t CP0COUNT;                          /**< Processor 0 Count Register, offset: 0x2C */
  __I  uint32_t CP0CFG0;                           /**< Processor 0 Configuration Register 0, offset: 0x30 */
  __I  uint32_t CP0CFG1;                           /**< Processor 0 Configuration Register 1, offset: 0x34 */
  __I  uint32_t CP0CFG2;                           /**< Processor 0 Configuration Register 2, offset: 0x38 */
  __I  uint32_t CP0CFG3;                           /**< Processor 0 Configuration Register 3, offset: 0x3C */
       uint8_t RESERVED_0[960];
  __I  uint32_t OCMDR0;                            /**< On-Chip Memory Descriptor Register, offset: 0x400 */
  __I  uint32_t OCMDR1;                            /**< On-Chip Memory Descriptor Register, offset: 0x404 */
  __I  uint32_t OCMDR2;                            /**< On-Chip Memory Descriptor Register, offset: 0x408 */
  __I  uint32_t OCMDR3;                            /**< On-Chip Memory Descriptor Register, offset: 0x40C */
  __I  uint32_t OCMDR4;                            /**< On-Chip Memory Descriptor Register, offset: 0x410 */
  __I  uint32_t OCMDR5;                            /**< On-Chip Memory Descriptor Register, offset: 0x414 */
       uint8_t RESERVED_1[1000];
  __IO uint32_t SECURE_IRQ;                        /**< Secure Interrupt Request, offset: 0x800 */
       uint8_t RESERVED_2[12];
  __I  uint32_t UID[4];                            /**< Unique ID 0..Unique ID 3, array offset: 0x810, array step: 0x4 */
  __I  uint32_t SID;                               /**< System ID, offset: 0x820 */
} MSCM_Type;

/* ----------------------------------------------------------------------------
   -- MSCM Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup MSCM_Register_Masks MSCM Register Masks
 * @{
 */

/*! @name CPXTYPE - Processor X Type Register */
/*! @{ */

#define MSCM_CPXTYPE_RYPZ_MASK                   (0xFFU)
#define MSCM_CPXTYPE_RYPZ_SHIFT                  (0U)
/*! RYPZ - Processor x Revision
 */
#define MSCM_CPXTYPE_RYPZ(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_CPXTYPE_RYPZ_SHIFT)) & MSCM_CPXTYPE_RYPZ_MASK)

#define MSCM_CPXTYPE_PERSONALITY_MASK            (0xFFFFFF00U)
#define MSCM_CPXTYPE_PERSONALITY_SHIFT           (8U)
/*! PERSONALITY - Processor x Personality
 */
#define MSCM_CPXTYPE_PERSONALITY(x)              (((uint32_t)(((uint32_t)(x)) << MSCM_CPXTYPE_PERSONALITY_SHIFT)) & MSCM_CPXTYPE_PERSONALITY_MASK)
/*! @} */

/*! @name CPXNUM - Processor X Number Register */
/*! @{ */

#define MSCM_CPXNUM_CPN_MASK                     (0x1U)
#define MSCM_CPXNUM_CPN_SHIFT                    (0U)
/*! CPN - Processor x Number
 */
#define MSCM_CPXNUM_CPN(x)                       (((uint32_t)(((uint32_t)(x)) << MSCM_CPXNUM_CPN_SHIFT)) & MSCM_CPXNUM_CPN_MASK)
/*! @} */

/*! @name CPXMASTER - Processor X Master Register */
/*! @{ */

#define MSCM_CPXMASTER_PPMN_MASK                 (0x3FU)
#define MSCM_CPXMASTER_PPMN_SHIFT                (0U)
/*! PPMN - Processor x Physical Master Number
 */
#define MSCM_CPXMASTER_PPMN(x)                   (((uint32_t)(((uint32_t)(x)) << MSCM_CPXMASTER_PPMN_SHIFT)) & MSCM_CPXMASTER_PPMN_MASK)
/*! @} */

/*! @name CPXCOUNT - Processor X Count Register */
/*! @{ */

#define MSCM_CPXCOUNT_PCNT_MASK                  (0x3U)
#define MSCM_CPXCOUNT_PCNT_SHIFT                 (0U)
/*! PCNT - Processor Count
 */
#define MSCM_CPXCOUNT_PCNT(x)                    (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCOUNT_PCNT_SHIFT)) & MSCM_CPXCOUNT_PCNT_MASK)
/*! @} */

/*! @name CPXCFG0 - Processor X Configuration Register 0 */
/*! @{ */

#define MSCM_CPXCFG0_DCWY_MASK                   (0xFFU)
#define MSCM_CPXCFG0_DCWY_SHIFT                  (0U)
/*! DCWY - Level 1 Data Cache Ways
 */
#define MSCM_CPXCFG0_DCWY(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG0_DCWY_SHIFT)) & MSCM_CPXCFG0_DCWY_MASK)

#define MSCM_CPXCFG0_DCSZ_MASK                   (0xFF00U)
#define MSCM_CPXCFG0_DCSZ_SHIFT                  (8U)
/*! DCSZ - Level 1 Data Cache Size
 */
#define MSCM_CPXCFG0_DCSZ(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG0_DCSZ_SHIFT)) & MSCM_CPXCFG0_DCSZ_MASK)

#define MSCM_CPXCFG0_ICWY_MASK                   (0xFF0000U)
#define MSCM_CPXCFG0_ICWY_SHIFT                  (16U)
/*! ICWY - Level 1 Instruction Cache Ways
 */
#define MSCM_CPXCFG0_ICWY(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG0_ICWY_SHIFT)) & MSCM_CPXCFG0_ICWY_MASK)

#define MSCM_CPXCFG0_ICSZ_MASK                   (0xFF000000U)
#define MSCM_CPXCFG0_ICSZ_SHIFT                  (24U)
/*! ICSZ - Level 1 Instruction Cache Size
 */
#define MSCM_CPXCFG0_ICSZ(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG0_ICSZ_SHIFT)) & MSCM_CPXCFG0_ICSZ_MASK)
/*! @} */

/*! @name CPXCFG1 - Processor X Configuration Register 1 */
/*! @{ */

#define MSCM_CPXCFG1_L2WY_MASK                   (0xFF0000U)
#define MSCM_CPXCFG1_L2WY_SHIFT                  (16U)
/*! L2WY - Level 2 Instruction Cache Ways
 */
#define MSCM_CPXCFG1_L2WY(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG1_L2WY_SHIFT)) & MSCM_CPXCFG1_L2WY_MASK)

#define MSCM_CPXCFG1_L2SZ_MASK                   (0xFF000000U)
#define MSCM_CPXCFG1_L2SZ_SHIFT                  (24U)
/*! L2SZ - Level 2 Instruction Cache Size
 */
#define MSCM_CPXCFG1_L2SZ(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG1_L2SZ_SHIFT)) & MSCM_CPXCFG1_L2SZ_MASK)
/*! @} */

/*! @name CPXCFG2 - Processor X Configuration Register 2 */
/*! @{ */

#define MSCM_CPXCFG2_TMUSZ_MASK                  (0xFF00U)
#define MSCM_CPXCFG2_TMUSZ_SHIFT                 (8U)
/*! TMUSZ - Tightly-coupled Memory Upper Size
 */
#define MSCM_CPXCFG2_TMUSZ(x)                    (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG2_TMUSZ_SHIFT)) & MSCM_CPXCFG2_TMUSZ_MASK)

#define MSCM_CPXCFG2_TMLSZ_MASK                  (0xFF000000U)
#define MSCM_CPXCFG2_TMLSZ_SHIFT                 (24U)
/*! TMLSZ - Tightly-coupled Memory Lower Size
 */
#define MSCM_CPXCFG2_TMLSZ(x)                    (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG2_TMLSZ_SHIFT)) & MSCM_CPXCFG2_TMLSZ_MASK)
/*! @} */

/*! @name CPXCFG3 - Processor X Configuration Register 3 */
/*! @{ */

#define MSCM_CPXCFG3_FPU_MASK                    (0x1U)
#define MSCM_CPXCFG3_FPU_SHIFT                   (0U)
/*! FPU - Floating Point Unit
 *  0b0..FPU support is not included.
 *  0b1..FPU support is included.
 */
#define MSCM_CPXCFG3_FPU(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG3_FPU_SHIFT)) & MSCM_CPXCFG3_FPU_MASK)

#define MSCM_CPXCFG3_SIMD_MASK                   (0x2U)
#define MSCM_CPXCFG3_SIMD_SHIFT                  (1U)
/*! SIMD - SIMD/NEON instruction support
 *  0b0..SIMD/NEON support is not included.
 *  0b1..SIMD/NEON support is included.
 */
#define MSCM_CPXCFG3_SIMD(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG3_SIMD_SHIFT)) & MSCM_CPXCFG3_SIMD_MASK)

#define MSCM_CPXCFG3_JAZ_MASK                    (0x4U)
#define MSCM_CPXCFG3_JAZ_SHIFT                   (2U)
/*! JAZ - Jazelle support
 *  0b0..Jazelle support is not included.
 *  0b1..Jazelle support is included.
 */
#define MSCM_CPXCFG3_JAZ(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG3_JAZ_SHIFT)) & MSCM_CPXCFG3_JAZ_MASK)

#define MSCM_CPXCFG3_MMU_MASK                    (0x8U)
#define MSCM_CPXCFG3_MMU_SHIFT                   (3U)
/*! MMU - Memory Management Unit
 *  0b0..MMU support is not included.
 *  0b1..MMU support is included.
 */
#define MSCM_CPXCFG3_MMU(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG3_MMU_SHIFT)) & MSCM_CPXCFG3_MMU_MASK)

#define MSCM_CPXCFG3_TZ_MASK                     (0x10U)
#define MSCM_CPXCFG3_TZ_SHIFT                    (4U)
/*! TZ - Trust Zone
 *  0b0..Trust Zone support is not included.
 *  0b1..Trust Zone support is included.
 */
#define MSCM_CPXCFG3_TZ(x)                       (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG3_TZ_SHIFT)) & MSCM_CPXCFG3_TZ_MASK)

#define MSCM_CPXCFG3_CMP_MASK                    (0x20U)
#define MSCM_CPXCFG3_CMP_SHIFT                   (5U)
/*! CMP - Core Memory Protection unit
 *  0b0..Core Memory Protection is not included.
 *  0b1..Core Memory Protection is included.
 */
#define MSCM_CPXCFG3_CMP(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG3_CMP_SHIFT)) & MSCM_CPXCFG3_CMP_MASK)

#define MSCM_CPXCFG3_BB_MASK                     (0x40U)
#define MSCM_CPXCFG3_BB_SHIFT                    (6U)
/*! BB - Bit Banding
 *  0b0..Bit Banding is not supported.
 *  0b1..Bit Banding is supported.
 */
#define MSCM_CPXCFG3_BB(x)                       (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG3_BB_SHIFT)) & MSCM_CPXCFG3_BB_MASK)

#define MSCM_CPXCFG3_SBP_MASK                    (0x300U)
#define MSCM_CPXCFG3_SBP_SHIFT                   (8U)
/*! SBP - System Bus Ports
 */
#define MSCM_CPXCFG3_SBP(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG3_SBP_SHIFT)) & MSCM_CPXCFG3_SBP_MASK)
/*! @} */

/*! @name CP0TYPE - Processor 0 Type Register */
/*! @{ */

#define MSCM_CP0TYPE_RYPZ_MASK                   (0xFFU)
#define MSCM_CP0TYPE_RYPZ_SHIFT                  (0U)
/*! RYPZ - Processor 0 Revision
 */
#define MSCM_CP0TYPE_RYPZ(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_CP0TYPE_RYPZ_SHIFT)) & MSCM_CP0TYPE_RYPZ_MASK)

#define MSCM_CP0TYPE_PERSONALITY_MASK            (0xFFFFFF00U)
#define MSCM_CP0TYPE_PERSONALITY_SHIFT           (8U)
/*! PERSONALITY - Processor 0 Personality
 */
#define MSCM_CP0TYPE_PERSONALITY(x)              (((uint32_t)(((uint32_t)(x)) << MSCM_CP0TYPE_PERSONALITY_SHIFT)) & MSCM_CP0TYPE_PERSONALITY_MASK)
/*! @} */

/*! @name CP0NUM - Processor 0 Number Register */
/*! @{ */

#define MSCM_CP0NUM_CPN_MASK                     (0x1U)
#define MSCM_CP0NUM_CPN_SHIFT                    (0U)
/*! CPN - Processor 0 Number
 */
#define MSCM_CP0NUM_CPN(x)                       (((uint32_t)(((uint32_t)(x)) << MSCM_CP0NUM_CPN_SHIFT)) & MSCM_CP0NUM_CPN_MASK)
/*! @} */

/*! @name CP0MASTER - Processor 0 Master Register */
/*! @{ */

#define MSCM_CP0MASTER_PPMN_MASK                 (0x3FU)
#define MSCM_CP0MASTER_PPMN_SHIFT                (0U)
/*! PPMN - Processor 0 Physical Master Number
 */
#define MSCM_CP0MASTER_PPMN(x)                   (((uint32_t)(((uint32_t)(x)) << MSCM_CP0MASTER_PPMN_SHIFT)) & MSCM_CP0MASTER_PPMN_MASK)
/*! @} */

/*! @name CP0COUNT - Processor 0 Count Register */
/*! @{ */

#define MSCM_CP0COUNT_PCNT_MASK                  (0x3U)
#define MSCM_CP0COUNT_PCNT_SHIFT                 (0U)
/*! PCNT - Processor Count
 */
#define MSCM_CP0COUNT_PCNT(x)                    (((uint32_t)(((uint32_t)(x)) << MSCM_CP0COUNT_PCNT_SHIFT)) & MSCM_CP0COUNT_PCNT_MASK)
/*! @} */

/*! @name CP0CFG0 - Processor 0 Configuration Register 0 */
/*! @{ */

#define MSCM_CP0CFG0_DCWY_MASK                   (0xFFU)
#define MSCM_CP0CFG0_DCWY_SHIFT                  (0U)
/*! DCWY - Level 1 Data Cache Ways
 */
#define MSCM_CP0CFG0_DCWY(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG0_DCWY_SHIFT)) & MSCM_CP0CFG0_DCWY_MASK)

#define MSCM_CP0CFG0_DCSZ_MASK                   (0xFF00U)
#define MSCM_CP0CFG0_DCSZ_SHIFT                  (8U)
/*! DCSZ - Level 1 Data Cache Size
 */
#define MSCM_CP0CFG0_DCSZ(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG0_DCSZ_SHIFT)) & MSCM_CP0CFG0_DCSZ_MASK)

#define MSCM_CP0CFG0_ICWY_MASK                   (0xFF0000U)
#define MSCM_CP0CFG0_ICWY_SHIFT                  (16U)
/*! ICWY - Level 1 Instruction Cache Ways
 */
#define MSCM_CP0CFG0_ICWY(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG0_ICWY_SHIFT)) & MSCM_CP0CFG0_ICWY_MASK)

#define MSCM_CP0CFG0_ICSZ_MASK                   (0xFF000000U)
#define MSCM_CP0CFG0_ICSZ_SHIFT                  (24U)
/*! ICSZ - Level 1 Instruction Cache Size
 */
#define MSCM_CP0CFG0_ICSZ(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG0_ICSZ_SHIFT)) & MSCM_CP0CFG0_ICSZ_MASK)
/*! @} */

/*! @name CP0CFG1 - Processor 0 Configuration Register 1 */
/*! @{ */

#define MSCM_CP0CFG1_L2WY_MASK                   (0xFF0000U)
#define MSCM_CP0CFG1_L2WY_SHIFT                  (16U)
/*! L2WY - Level 2 Instruction Cache Ways
 */
#define MSCM_CP0CFG1_L2WY(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG1_L2WY_SHIFT)) & MSCM_CP0CFG1_L2WY_MASK)

#define MSCM_CP0CFG1_L2SZ_MASK                   (0xFF000000U)
#define MSCM_CP0CFG1_L2SZ_SHIFT                  (24U)
/*! L2SZ - Level 2 Instruction Cache Size
 */
#define MSCM_CP0CFG1_L2SZ(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG1_L2SZ_SHIFT)) & MSCM_CP0CFG1_L2SZ_MASK)
/*! @} */

/*! @name CP0CFG2 - Processor 0 Configuration Register 2 */
/*! @{ */

#define MSCM_CP0CFG2_TMUSZ_MASK                  (0xFF00U)
#define MSCM_CP0CFG2_TMUSZ_SHIFT                 (8U)
/*! TMUSZ - Tightly-coupled Memory Upper Size
 */
#define MSCM_CP0CFG2_TMUSZ(x)                    (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG2_TMUSZ_SHIFT)) & MSCM_CP0CFG2_TMUSZ_MASK)

#define MSCM_CP0CFG2_TMLSZ_MASK                  (0xFF000000U)
#define MSCM_CP0CFG2_TMLSZ_SHIFT                 (24U)
/*! TMLSZ - Tightly-coupled Memory Lower Size
 */
#define MSCM_CP0CFG2_TMLSZ(x)                    (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG2_TMLSZ_SHIFT)) & MSCM_CP0CFG2_TMLSZ_MASK)
/*! @} */

/*! @name CP0CFG3 - Processor 0 Configuration Register 3 */
/*! @{ */

#define MSCM_CP0CFG3_FPU_MASK                    (0x1U)
#define MSCM_CP0CFG3_FPU_SHIFT                   (0U)
/*! FPU - Floating Point Unit
 *  0b0..FPU support is not included.
 *  0b1..FPU support is included.
 */
#define MSCM_CP0CFG3_FPU(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG3_FPU_SHIFT)) & MSCM_CP0CFG3_FPU_MASK)

#define MSCM_CP0CFG3_SIMD_MASK                   (0x2U)
#define MSCM_CP0CFG3_SIMD_SHIFT                  (1U)
/*! SIMD - SIMD/NEON instruction support
 *  0b0..SIMD/NEON support is not included.
 *  0b1..SIMD/NEON support is included.
 */
#define MSCM_CP0CFG3_SIMD(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG3_SIMD_SHIFT)) & MSCM_CP0CFG3_SIMD_MASK)

#define MSCM_CP0CFG3_JAZ_MASK                    (0x4U)
#define MSCM_CP0CFG3_JAZ_SHIFT                   (2U)
/*! JAZ - Jazelle support
 *  0b0..Jazelle support is not included.
 *  0b1..Jazelle support is included.
 */
#define MSCM_CP0CFG3_JAZ(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG3_JAZ_SHIFT)) & MSCM_CP0CFG3_JAZ_MASK)

#define MSCM_CP0CFG3_MMU_MASK                    (0x8U)
#define MSCM_CP0CFG3_MMU_SHIFT                   (3U)
/*! MMU - Memory Management Unit
 *  0b0..MMU support is not included.
 *  0b1..MMU support is included.
 */
#define MSCM_CP0CFG3_MMU(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG3_MMU_SHIFT)) & MSCM_CP0CFG3_MMU_MASK)

#define MSCM_CP0CFG3_TZ_MASK                     (0x10U)
#define MSCM_CP0CFG3_TZ_SHIFT                    (4U)
/*! TZ - Trust Zone
 *  0b0..Trust Zone support is not included.
 *  0b1..Trust Zone support is included.
 */
#define MSCM_CP0CFG3_TZ(x)                       (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG3_TZ_SHIFT)) & MSCM_CP0CFG3_TZ_MASK)

#define MSCM_CP0CFG3_CMP_MASK                    (0x20U)
#define MSCM_CP0CFG3_CMP_SHIFT                   (5U)
/*! CMP - Core Memory Protection unit
 *  0b0..Core Memory Protection is not included.
 *  0b1..Core Memory Protection is included.
 */
#define MSCM_CP0CFG3_CMP(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG3_CMP_SHIFT)) & MSCM_CP0CFG3_CMP_MASK)

#define MSCM_CP0CFG3_BB_MASK                     (0x40U)
#define MSCM_CP0CFG3_BB_SHIFT                    (6U)
/*! BB - Bit Banding
 *  0b0..Bit Banding is not supported.
 *  0b1..Bit Banding is supported.
 */
#define MSCM_CP0CFG3_BB(x)                       (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG3_BB_SHIFT)) & MSCM_CP0CFG3_BB_MASK)

#define MSCM_CP0CFG3_SBP_MASK                    (0x300U)
#define MSCM_CP0CFG3_SBP_SHIFT                   (8U)
/*! SBP - System Bus Ports
 */
#define MSCM_CP0CFG3_SBP(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG3_SBP_SHIFT)) & MSCM_CP0CFG3_SBP_MASK)
/*! @} */

/*! @name OCMDR0 - On-Chip Memory Descriptor Register */
/*! @{ */

#define MSCM_OCMDR0_OCMPU_MASK                   (0x1000U)
#define MSCM_OCMDR0_OCMPU_SHIFT                  (12U)
/*! OCMPU - OCMPU
 */
#define MSCM_OCMDR0_OCMPU(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR0_OCMPU_SHIFT)) & MSCM_OCMDR0_OCMPU_MASK)

#define MSCM_OCMDR0_OCMT_MASK                    (0xE000U)
#define MSCM_OCMDR0_OCMT_SHIFT                   (13U)
/*! OCMT - OCMT
 *  0b000..OCMEMn is a System RAM.
 *  0b001..Reserved
 *  0b010..Reserved
 *  0b011..OCMEMn is a ROM.
 *  0b100..OCMEMn is a Program Flash.
 *  0b101..Reserved
 *  0b110..Reserved
 *  0b111..Reserved
 */
#define MSCM_OCMDR0_OCMT(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR0_OCMT_SHIFT)) & MSCM_OCMDR0_OCMT_MASK)

#define MSCM_OCMDR0_OCMW_MASK                    (0xE0000U)
#define MSCM_OCMDR0_OCMW_SHIFT                   (17U)
/*! OCMW - OCMW
 *  0b000-0b001..Reserved
 *  0b010..OCMEMn 32-bits wide
 *  0b011..OCMEMn 64-bits wide
 *  0b100..OCMEMn 128-bits wide
 *  0b101..OCMEMn 256-bits wide
 *  0b110-0b111..Reserved
 */
#define MSCM_OCMDR0_OCMW(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR0_OCMW_SHIFT)) & MSCM_OCMDR0_OCMW_MASK)

#define MSCM_OCMDR0_OCMSZ_MASK                   (0xF000000U)
#define MSCM_OCMDR0_OCMSZ_SHIFT                  (24U)
/*! OCMSZ - OCMSZ
 *  0b0000..no OCMEMn
 *  0b0001..1KB OCMEMn
 *  0b0010..2KB OCMEMn
 *  0b0011..4KB OCMEMn
 *  0b0100..8KB OCMEMn
 *  0b0101..16KB OCMEMn
 *  0b0110..32KB OCMEMn
 *  0b0111..64KB OCMEMn
 *  0b1000..128KB OCMEMn
 *  0b1001..256KB OCMEMn
 *  0b1010..512KB OCMEMn
 *  0b1011..1MB OCMEMn
 *  0b1100..2MB OCMEMn
 *  0b1101..4MB OCMEMn
 *  0b1110..8MB OCMEMn
 *  0b1111..16MB OCMEMn
 */
#define MSCM_OCMDR0_OCMSZ(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR0_OCMSZ_SHIFT)) & MSCM_OCMDR0_OCMSZ_MASK)

#define MSCM_OCMDR0_OCMSZH_MASK                  (0x10000000U)
#define MSCM_OCMDR0_OCMSZH_SHIFT                 (28U)
/*! OCMSZH - OCMSZH
 *  0b0..OCMEMn is a power-of-2 capacity.
 *  0b1..OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ.
 */
#define MSCM_OCMDR0_OCMSZH(x)                    (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR0_OCMSZH_SHIFT)) & MSCM_OCMDR0_OCMSZH_MASK)

#define MSCM_OCMDR0_OCMECC_MASK                  (0x20000000U)
#define MSCM_OCMDR0_OCMECC_SHIFT                 (29U)
/*! OCMECC - OCMECC
 *  0b0..OCMEMn does not have ECC support.
 *  0b1..OCMEMn has ECC support.
 */
#define MSCM_OCMDR0_OCMECC(x)                    (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR0_OCMECC_SHIFT)) & MSCM_OCMDR0_OCMECC_MASK)

#define MSCM_OCMDR0_V_MASK                       (0x80000000U)
#define MSCM_OCMDR0_V_SHIFT                      (31U)
/*! V - V
 *  0b0..OCMEMn is not present.
 *  0b1..OCMEMn is present.
 */
#define MSCM_OCMDR0_V(x)                         (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR0_V_SHIFT)) & MSCM_OCMDR0_V_MASK)
/*! @} */

/*! @name OCMDR1 - On-Chip Memory Descriptor Register */
/*! @{ */

#define MSCM_OCMDR1_OCMPU_MASK                   (0x1000U)
#define MSCM_OCMDR1_OCMPU_SHIFT                  (12U)
/*! OCMPU - OCMPU
 */
#define MSCM_OCMDR1_OCMPU(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR1_OCMPU_SHIFT)) & MSCM_OCMDR1_OCMPU_MASK)

#define MSCM_OCMDR1_OCMT_MASK                    (0xE000U)
#define MSCM_OCMDR1_OCMT_SHIFT                   (13U)
/*! OCMT - OCMT
 *  0b000..OCMEMn is a System RAM.
 *  0b001..Reserved
 *  0b010..Reserved
 *  0b011..OCMEMn is a ROM.
 *  0b100..OCMEMn is a Program Flash.
 *  0b101..Reserved
 *  0b110..Reserved
 *  0b111..Reserved
 */
#define MSCM_OCMDR1_OCMT(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR1_OCMT_SHIFT)) & MSCM_OCMDR1_OCMT_MASK)

#define MSCM_OCMDR1_OCMW_MASK                    (0xE0000U)
#define MSCM_OCMDR1_OCMW_SHIFT                   (17U)
/*! OCMW - OCMW
 *  0b000-0b001..Reserved
 *  0b010..OCMEMn 32-bits wide
 *  0b011..OCMEMn 64-bits wide
 *  0b100..OCMEMn 128-bits wide
 *  0b101..OCMEMn 256-bits wide
 *  0b110-0b111..Reserved
 */
#define MSCM_OCMDR1_OCMW(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR1_OCMW_SHIFT)) & MSCM_OCMDR1_OCMW_MASK)

#define MSCM_OCMDR1_OCMSZ_MASK                   (0xF000000U)
#define MSCM_OCMDR1_OCMSZ_SHIFT                  (24U)
/*! OCMSZ - OCMSZ
 *  0b0000..no OCMEMn
 *  0b0001..1KB OCMEMn
 *  0b0010..2KB OCMEMn
 *  0b0011..4KB OCMEMn
 *  0b0100..8KB OCMEMn
 *  0b0101..16KB OCMEMn
 *  0b0110..32KB OCMEMn
 *  0b0111..64KB OCMEMn
 *  0b1000..128KB OCMEMn
 *  0b1001..256KB OCMEMn
 *  0b1010..512KB OCMEMn
 *  0b1011..1MB OCMEMn
 *  0b1100..2MB OCMEMn
 *  0b1101..4MB OCMEMn
 *  0b1110..8MB OCMEMn
 *  0b1111..16MB OCMEMn
 */
#define MSCM_OCMDR1_OCMSZ(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR1_OCMSZ_SHIFT)) & MSCM_OCMDR1_OCMSZ_MASK)

#define MSCM_OCMDR1_OCMSZH_MASK                  (0x10000000U)
#define MSCM_OCMDR1_OCMSZH_SHIFT                 (28U)
/*! OCMSZH - OCMSZH
 *  0b0..OCMEMn is a power-of-2 capacity.
 *  0b1..OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ.
 */
#define MSCM_OCMDR1_OCMSZH(x)                    (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR1_OCMSZH_SHIFT)) & MSCM_OCMDR1_OCMSZH_MASK)

#define MSCM_OCMDR1_OCMECC_MASK                  (0x20000000U)
#define MSCM_OCMDR1_OCMECC_SHIFT                 (29U)
/*! OCMECC - OCMECC
 *  0b0..OCMEMn does not have ECC support.
 *  0b1..OCMEMn has ECC support.
 */
#define MSCM_OCMDR1_OCMECC(x)                    (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR1_OCMECC_SHIFT)) & MSCM_OCMDR1_OCMECC_MASK)

#define MSCM_OCMDR1_V_MASK                       (0x80000000U)
#define MSCM_OCMDR1_V_SHIFT                      (31U)
/*! V - V
 *  0b0..OCMEMn is not present.
 *  0b1..OCMEMn is present.
 */
#define MSCM_OCMDR1_V(x)                         (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR1_V_SHIFT)) & MSCM_OCMDR1_V_MASK)
/*! @} */

/*! @name OCMDR2 - On-Chip Memory Descriptor Register */
/*! @{ */

#define MSCM_OCMDR2_OCMPU_MASK                   (0x1000U)
#define MSCM_OCMDR2_OCMPU_SHIFT                  (12U)
/*! OCMPU - OCMPU
 */
#define MSCM_OCMDR2_OCMPU(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR2_OCMPU_SHIFT)) & MSCM_OCMDR2_OCMPU_MASK)

#define MSCM_OCMDR2_OCMT_MASK                    (0xE000U)
#define MSCM_OCMDR2_OCMT_SHIFT                   (13U)
/*! OCMT - OCMT
 *  0b000..OCMEMn is a System RAM.
 *  0b001..Reserved
 *  0b010..Reserved
 *  0b011..OCMEMn is a ROM.
 *  0b100..OCMEMn is a Program Flash.
 *  0b101..Reserved
 *  0b110..Reserved
 *  0b111..Reserved
 */
#define MSCM_OCMDR2_OCMT(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR2_OCMT_SHIFT)) & MSCM_OCMDR2_OCMT_MASK)

#define MSCM_OCMDR2_OCMW_MASK                    (0xE0000U)
#define MSCM_OCMDR2_OCMW_SHIFT                   (17U)
/*! OCMW - OCMW
 *  0b000-0b001..Reserved
 *  0b010..OCMEMn 32-bits wide
 *  0b011..OCMEMn 64-bits wide
 *  0b100..OCMEMn 128-bits wide
 *  0b101..OCMEMn 256-bits wide
 *  0b110-0b111..Reserved
 */
#define MSCM_OCMDR2_OCMW(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR2_OCMW_SHIFT)) & MSCM_OCMDR2_OCMW_MASK)

#define MSCM_OCMDR2_OCMSZ_MASK                   (0xF000000U)
#define MSCM_OCMDR2_OCMSZ_SHIFT                  (24U)
/*! OCMSZ - OCMSZ
 *  0b0000..no OCMEMn
 *  0b0001..1KB OCMEMn
 *  0b0010..2KB OCMEMn
 *  0b0011..4KB OCMEMn
 *  0b0100..8KB OCMEMn
 *  0b0101..16KB OCMEMn
 *  0b0110..32KB OCMEMn
 *  0b0111..64KB OCMEMn
 *  0b1000..128KB OCMEMn
 *  0b1001..256KB OCMEMn
 *  0b1010..512KB OCMEMn
 *  0b1011..1MB OCMEMn
 *  0b1100..2MB OCMEMn
 *  0b1101..4MB OCMEMn
 *  0b1110..8MB OCMEMn
 *  0b1111..16MB OCMEMn
 */
#define MSCM_OCMDR2_OCMSZ(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR2_OCMSZ_SHIFT)) & MSCM_OCMDR2_OCMSZ_MASK)

#define MSCM_OCMDR2_OCMSZH_MASK                  (0x10000000U)
#define MSCM_OCMDR2_OCMSZH_SHIFT                 (28U)
/*! OCMSZH - OCMSZH
 *  0b0..OCMEMn is a power-of-2 capacity.
 *  0b1..OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ.
 */
#define MSCM_OCMDR2_OCMSZH(x)                    (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR2_OCMSZH_SHIFT)) & MSCM_OCMDR2_OCMSZH_MASK)

#define MSCM_OCMDR2_OCMECC_MASK                  (0x20000000U)
#define MSCM_OCMDR2_OCMECC_SHIFT                 (29U)
/*! OCMECC - OCMECC
 *  0b0..OCMEMn does not have ECC support.
 *  0b1..OCMEMn has ECC support.
 */
#define MSCM_OCMDR2_OCMECC(x)                    (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR2_OCMECC_SHIFT)) & MSCM_OCMDR2_OCMECC_MASK)

#define MSCM_OCMDR2_V_MASK                       (0x80000000U)
#define MSCM_OCMDR2_V_SHIFT                      (31U)
/*! V - V
 *  0b0..OCMEMn is not present.
 *  0b1..OCMEMn is present.
 */
#define MSCM_OCMDR2_V(x)                         (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR2_V_SHIFT)) & MSCM_OCMDR2_V_MASK)
/*! @} */

/*! @name OCMDR3 - On-Chip Memory Descriptor Register */
/*! @{ */

#define MSCM_OCMDR3_OCMPU_MASK                   (0x1000U)
#define MSCM_OCMDR3_OCMPU_SHIFT                  (12U)
/*! OCMPU - OCMPU
 */
#define MSCM_OCMDR3_OCMPU(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR3_OCMPU_SHIFT)) & MSCM_OCMDR3_OCMPU_MASK)

#define MSCM_OCMDR3_OCMT_MASK                    (0xE000U)
#define MSCM_OCMDR3_OCMT_SHIFT                   (13U)
/*! OCMT - OCMT
 *  0b000..OCMEMn is a System RAM.
 *  0b001..Reserved
 *  0b010..Reserved
 *  0b011..OCMEMn is a ROM.
 *  0b100..OCMEMn is a Program Flash.
 *  0b101..Reserved
 *  0b110..Reserved
 *  0b111..Reserved
 */
#define MSCM_OCMDR3_OCMT(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR3_OCMT_SHIFT)) & MSCM_OCMDR3_OCMT_MASK)

#define MSCM_OCMDR3_OCMW_MASK                    (0xE0000U)
#define MSCM_OCMDR3_OCMW_SHIFT                   (17U)
/*! OCMW - OCMW
 *  0b000-0b001..Reserved
 *  0b010..OCMEMn 32-bits wide
 *  0b011..OCMEMn 64-bits wide
 *  0b100..OCMEMn 128-bits wide
 *  0b101..OCMEMn 256-bits wide
 *  0b110-0b111..Reserved
 */
#define MSCM_OCMDR3_OCMW(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR3_OCMW_SHIFT)) & MSCM_OCMDR3_OCMW_MASK)

#define MSCM_OCMDR3_OCMSZ_MASK                   (0xF000000U)
#define MSCM_OCMDR3_OCMSZ_SHIFT                  (24U)
/*! OCMSZ - OCMSZ
 *  0b0000..no OCMEMn
 *  0b0001..1KB OCMEMn
 *  0b0010..2KB OCMEMn
 *  0b0011..4KB OCMEMn
 *  0b0100..8KB OCMEMn
 *  0b0101..16KB OCMEMn
 *  0b0110..32KB OCMEMn
 *  0b0111..64KB OCMEMn
 *  0b1000..128KB OCMEMn
 *  0b1001..256KB OCMEMn
 *  0b1010..512KB OCMEMn
 *  0b1011..1MB OCMEMn
 *  0b1100..2MB OCMEMn
 *  0b1101..4MB OCMEMn
 *  0b1110..8MB OCMEMn
 *  0b1111..16MB OCMEMn
 */
#define MSCM_OCMDR3_OCMSZ(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR3_OCMSZ_SHIFT)) & MSCM_OCMDR3_OCMSZ_MASK)

#define MSCM_OCMDR3_OCMSZH_MASK                  (0x10000000U)
#define MSCM_OCMDR3_OCMSZH_SHIFT                 (28U)
/*! OCMSZH - OCMSZH
 *  0b0..OCMEMn is a power-of-2 capacity.
 *  0b1..OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ.
 */
#define MSCM_OCMDR3_OCMSZH(x)                    (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR3_OCMSZH_SHIFT)) & MSCM_OCMDR3_OCMSZH_MASK)

#define MSCM_OCMDR3_OCMECC_MASK                  (0x20000000U)
#define MSCM_OCMDR3_OCMECC_SHIFT                 (29U)
/*! OCMECC - OCMECC
 *  0b0..OCMEMn does not have ECC support.
 *  0b1..OCMEMn has ECC support.
 */
#define MSCM_OCMDR3_OCMECC(x)                    (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR3_OCMECC_SHIFT)) & MSCM_OCMDR3_OCMECC_MASK)

#define MSCM_OCMDR3_V_MASK                       (0x80000000U)
#define MSCM_OCMDR3_V_SHIFT                      (31U)
/*! V - V
 *  0b0..OCMEMn is not present.
 *  0b1..OCMEMn is present.
 */
#define MSCM_OCMDR3_V(x)                         (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR3_V_SHIFT)) & MSCM_OCMDR3_V_MASK)
/*! @} */

/*! @name OCMDR4 - On-Chip Memory Descriptor Register */
/*! @{ */

#define MSCM_OCMDR4_OCMPU_MASK                   (0x1000U)
#define MSCM_OCMDR4_OCMPU_SHIFT                  (12U)
/*! OCMPU - OCMPU
 */
#define MSCM_OCMDR4_OCMPU(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR4_OCMPU_SHIFT)) & MSCM_OCMDR4_OCMPU_MASK)

#define MSCM_OCMDR4_OCMT_MASK                    (0xE000U)
#define MSCM_OCMDR4_OCMT_SHIFT                   (13U)
/*! OCMT - OCMT
 *  0b000..OCMEMn is a System RAM.
 *  0b001..Reserved
 *  0b010..Reserved
 *  0b011..OCMEMn is a ROM.
 *  0b100..OCMEMn is a Program Flash.
 *  0b101..Reserved
 *  0b110..Reserved
 *  0b111..Reserved
 */
#define MSCM_OCMDR4_OCMT(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR4_OCMT_SHIFT)) & MSCM_OCMDR4_OCMT_MASK)

#define MSCM_OCMDR4_OCMW_MASK                    (0xE0000U)
#define MSCM_OCMDR4_OCMW_SHIFT                   (17U)
/*! OCMW - OCMW
 *  0b000-0b001..Reserved
 *  0b010..OCMEMn 32-bits wide
 *  0b011..OCMEMn 64-bits wide
 *  0b100..OCMEMn 128-bits wide
 *  0b101..OCMEMn 256-bits wide
 *  0b110-0b111..Reserved
 */
#define MSCM_OCMDR4_OCMW(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR4_OCMW_SHIFT)) & MSCM_OCMDR4_OCMW_MASK)

#define MSCM_OCMDR4_OCMSZ_MASK                   (0xF000000U)
#define MSCM_OCMDR4_OCMSZ_SHIFT                  (24U)
/*! OCMSZ - OCMSZ
 *  0b0000..no OCMEMn
 *  0b0001..1KB OCMEMn
 *  0b0010..2KB OCMEMn
 *  0b0011..4KB OCMEMn
 *  0b0100..8KB OCMEMn
 *  0b0101..16KB OCMEMn
 *  0b0110..32KB OCMEMn
 *  0b0111..64KB OCMEMn
 *  0b1000..128KB OCMEMn
 *  0b1001..256KB OCMEMn
 *  0b1010..512KB OCMEMn
 *  0b1011..1MB OCMEMn
 *  0b1100..2MB OCMEMn
 *  0b1101..4MB OCMEMn
 *  0b1110..8MB OCMEMn
 *  0b1111..16MB OCMEMn
 */
#define MSCM_OCMDR4_OCMSZ(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR4_OCMSZ_SHIFT)) & MSCM_OCMDR4_OCMSZ_MASK)

#define MSCM_OCMDR4_OCMSZH_MASK                  (0x10000000U)
#define MSCM_OCMDR4_OCMSZH_SHIFT                 (28U)
/*! OCMSZH - OCMSZH
 *  0b0..OCMEMn is a power-of-2 capacity.
 *  0b1..OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ.
 */
#define MSCM_OCMDR4_OCMSZH(x)                    (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR4_OCMSZH_SHIFT)) & MSCM_OCMDR4_OCMSZH_MASK)

#define MSCM_OCMDR4_OCMECC_MASK                  (0x20000000U)
#define MSCM_OCMDR4_OCMECC_SHIFT                 (29U)
/*! OCMECC - OCMECC
 *  0b0..OCMEMn does not have ECC support.
 *  0b1..OCMEMn has ECC support.
 */
#define MSCM_OCMDR4_OCMECC(x)                    (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR4_OCMECC_SHIFT)) & MSCM_OCMDR4_OCMECC_MASK)

#define MSCM_OCMDR4_V_MASK                       (0x80000000U)
#define MSCM_OCMDR4_V_SHIFT                      (31U)
/*! V - V
 *  0b0..OCMEMn is not present.
 *  0b1..OCMEMn is present.
 */
#define MSCM_OCMDR4_V(x)                         (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR4_V_SHIFT)) & MSCM_OCMDR4_V_MASK)
/*! @} */

/*! @name OCMDR5 - On-Chip Memory Descriptor Register */
/*! @{ */

#define MSCM_OCMDR5_OCMPU_MASK                   (0x1000U)
#define MSCM_OCMDR5_OCMPU_SHIFT                  (12U)
/*! OCMPU - OCMPU
 */
#define MSCM_OCMDR5_OCMPU(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR5_OCMPU_SHIFT)) & MSCM_OCMDR5_OCMPU_MASK)

#define MSCM_OCMDR5_OCMT_MASK                    (0xE000U)
#define MSCM_OCMDR5_OCMT_SHIFT                   (13U)
/*! OCMT - OCMT
 *  0b000..OCMEMn is a System RAM.
 *  0b001..Reserved
 *  0b010..Reserved
 *  0b011..OCMEMn is a ROM.
 *  0b100..OCMEMn is a Program Flash.
 *  0b101..Reserved
 *  0b110..Reserved
 *  0b111..Reserved
 */
#define MSCM_OCMDR5_OCMT(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR5_OCMT_SHIFT)) & MSCM_OCMDR5_OCMT_MASK)

#define MSCM_OCMDR5_OCMW_MASK                    (0xE0000U)
#define MSCM_OCMDR5_OCMW_SHIFT                   (17U)
/*! OCMW - OCMW
 *  0b000-0b001..Reserved
 *  0b010..OCMEMn 32-bits wide
 *  0b011..OCMEMn 64-bits wide
 *  0b100..OCMEMn 128-bits wide
 *  0b101..OCMEMn 256-bits wide
 *  0b110-0b111..Reserved
 */
#define MSCM_OCMDR5_OCMW(x)                      (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR5_OCMW_SHIFT)) & MSCM_OCMDR5_OCMW_MASK)

#define MSCM_OCMDR5_OCMSZ_MASK                   (0xF000000U)
#define MSCM_OCMDR5_OCMSZ_SHIFT                  (24U)
/*! OCMSZ - OCMSZ
 *  0b0000..no OCMEMn
 *  0b0001..1KB OCMEMn
 *  0b0010..2KB OCMEMn
 *  0b0011..4KB OCMEMn
 *  0b0100..8KB OCMEMn
 *  0b0101..16KB OCMEMn
 *  0b0110..32KB OCMEMn
 *  0b0111..64KB OCMEMn
 *  0b1000..128KB OCMEMn
 *  0b1001..256KB OCMEMn
 *  0b1010..512KB OCMEMn
 *  0b1011..1MB OCMEMn
 *  0b1100..2MB OCMEMn
 *  0b1101..4MB OCMEMn
 *  0b1110..8MB OCMEMn
 *  0b1111..16MB OCMEMn
 */
#define MSCM_OCMDR5_OCMSZ(x)                     (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR5_OCMSZ_SHIFT)) & MSCM_OCMDR5_OCMSZ_MASK)

#define MSCM_OCMDR5_OCMSZH_MASK                  (0x10000000U)
#define MSCM_OCMDR5_OCMSZH_SHIFT                 (28U)
/*! OCMSZH - OCMSZH
 *  0b0..OCMEMn is a power-of-2 capacity.
 *  0b1..OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ.
 */
#define MSCM_OCMDR5_OCMSZH(x)                    (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR5_OCMSZH_SHIFT)) & MSCM_OCMDR5_OCMSZH_MASK)

#define MSCM_OCMDR5_OCMECC_MASK                  (0x20000000U)
#define MSCM_OCMDR5_OCMECC_SHIFT                 (29U)
/*! OCMECC - OCMECC
 *  0b0..OCMEMn does not have ECC support.
 *  0b1..OCMEMn has ECC support.
 */
#define MSCM_OCMDR5_OCMECC(x)                    (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR5_OCMECC_SHIFT)) & MSCM_OCMDR5_OCMECC_MASK)

#define MSCM_OCMDR5_V_MASK                       (0x80000000U)
#define MSCM_OCMDR5_V_SHIFT                      (31U)
/*! V - V
 *  0b0..OCMEMn is not present.
 *  0b1..OCMEMn is present.
 */
#define MSCM_OCMDR5_V(x)                         (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR5_V_SHIFT)) & MSCM_OCMDR5_V_MASK)
/*! @} */

/*! @name SECURE_IRQ - Secure Interrupt Request */
/*! @{ */

#define MSCM_SECURE_IRQ_SEC_IRQ_ARG_MASK         (0xFFFFFFFFU)
#define MSCM_SECURE_IRQ_SEC_IRQ_ARG_SHIFT        (0U)
/*! SEC_IRQ_ARG - Secure Interrupt Argument
 */
#define MSCM_SECURE_IRQ_SEC_IRQ_ARG(x)           (((uint32_t)(((uint32_t)(x)) << MSCM_SECURE_IRQ_SEC_IRQ_ARG_SHIFT)) & MSCM_SECURE_IRQ_SEC_IRQ_ARG_MASK)
/*! @} */

/*! @name UID - Unique ID 0..Unique ID 3 */
/*! @{ */

#define MSCM_UID_UID0_MASK                       (0xFFFFFFFFU)
#define MSCM_UID_UID0_SHIFT                      (0U)
/*! UID0 - Unique ID 0
 */
#define MSCM_UID_UID0(x)                         (((uint32_t)(((uint32_t)(x)) << MSCM_UID_UID0_SHIFT)) & MSCM_UID_UID0_MASK)

#define MSCM_UID_UID1_MASK                       (0xFFFFFFFFU)
#define MSCM_UID_UID1_SHIFT                      (0U)
/*! UID1 - Unique ID 1
 */
#define MSCM_UID_UID1(x)                         (((uint32_t)(((uint32_t)(x)) << MSCM_UID_UID1_SHIFT)) & MSCM_UID_UID1_MASK)

#define MSCM_UID_UID2_MASK                       (0xFFFFFFFFU)
#define MSCM_UID_UID2_SHIFT                      (0U)
/*! UID2 - Unique ID 2
 */
#define MSCM_UID_UID2(x)                         (((uint32_t)(((uint32_t)(x)) << MSCM_UID_UID2_SHIFT)) & MSCM_UID_UID2_MASK)

#define MSCM_UID_UID3_MASK                       (0xFFFFFFFFU)
#define MSCM_UID_UID3_SHIFT                      (0U)
/*! UID3 - Unique ID 3
 */
#define MSCM_UID_UID3(x)                         (((uint32_t)(((uint32_t)(x)) << MSCM_UID_UID3_SHIFT)) & MSCM_UID_UID3_MASK)
/*! @} */

/* The count of MSCM_UID */
#define MSCM_UID_COUNT                           (4U)

/*! @name SID - System ID */
/*! @{ */

#define MSCM_SID_QI_MASK                         (0x3U)
#define MSCM_SID_QI_SHIFT                        (0U)
/*! QI - Qual Info
 *  0b00..Reserved
 *  0b01..Industrial
 *  0b10..Reserved
 *  0b11..Auto
 */
#define MSCM_SID_QI(x)                           (((uint32_t)(((uint32_t)(x)) << MSCM_SID_QI_SHIFT)) & MSCM_SID_QI_MASK)

#define MSCM_SID_SIREV_MASK                      (0xCU)
#define MSCM_SID_SIREV_SHIFT                     (2U)
/*! SIREV - Silicon Revision
 *  0b00..Reserved
 *  0b01..2nd Major Spin
 *  0b10..1st Major Spin
 *  0b11..Initial mask set
 */
#define MSCM_SID_SIREV(x)                        (((uint32_t)(((uint32_t)(x)) << MSCM_SID_SIREV_SHIFT)) & MSCM_SID_SIREV_MASK)

#define MSCM_SID_PINID_MASK                      (0x70U)
#define MSCM_SID_PINID_SHIFT                     (4U)
/*! PINID - Pin Identification
 *  0b010..40HVQFN
 *  0b011..48HVQFN
 *  0b100..56HVQFN
 */
#define MSCM_SID_PINID(x)                        (((uint32_t)(((uint32_t)(x)) << MSCM_SID_PINID_SHIFT)) & MSCM_SID_PINID_MASK)

#define MSCM_SID_CMP_MASK                        (0x80U)
#define MSCM_SID_CMP_SHIFT                       (7U)
/*! CMP - CMP Presence
 *  0b0..No CMP
 *  0b1..CMP present
 */
#define MSCM_SID_CMP(x)                          (((uint32_t)(((uint32_t)(x)) << MSCM_SID_CMP_SHIFT)) & MSCM_SID_CMP_MASK)

#define MSCM_SID_FLXIO_MASK                      (0x100U)
#define MSCM_SID_FLXIO_SHIFT                     (8U)
/*! FLXIO - FlexIO Presence
 *  0b0..No FlexIO
 *  0b1..FlexIO present
 */
#define MSCM_SID_FLXIO(x)                        (((uint32_t)(((uint32_t)(x)) << MSCM_SID_FLXIO_SHIFT)) & MSCM_SID_FLXIO_MASK)

#define MSCM_SID_VREF_MASK                       (0x200U)
#define MSCM_SID_VREF_SHIFT                      (9U)
/*! VREF - VREF Presence
 *  0b0..No VREF
 *  0b1..VREF present
 */
#define MSCM_SID_VREF(x)                         (((uint32_t)(((uint32_t)(x)) << MSCM_SID_VREF_SHIFT)) & MSCM_SID_VREF_MASK)

#define MSCM_SID_I3C_MASK                        (0x400U)
#define MSCM_SID_I3C_SHIFT                       (10U)
/*! I3C - I3C Presence
 *  0b0..No I3C
 *  0b1..I3C present
 */
#define MSCM_SID_I3C(x)                          (((uint32_t)(((uint32_t)(x)) << MSCM_SID_I3C_SHIFT)) & MSCM_SID_I3C_MASK)

#define MSCM_SID_CAN_MASK                        (0x800U)
#define MSCM_SID_CAN_SHIFT                       (11U)
/*! CAN - CAN Presence
 *  0b0..No CAN
 *  0b1..CAN present
 */
#define MSCM_SID_CAN(x)                          (((uint32_t)(((uint32_t)(x)) << MSCM_SID_CAN_SHIFT)) & MSCM_SID_CAN_MASK)

#define MSCM_SID_SEC_MASK                        (0x1000U)
#define MSCM_SID_SEC_SHIFT                       (12U)
/*! SEC - Secure Enclave Presence
 *  0b0..No Secure Enclave
 *  0b1..Secure Enclave present
 */
#define MSCM_SID_SEC(x)                          (((uint32_t)(((uint32_t)(x)) << MSCM_SID_SEC_SHIFT)) & MSCM_SID_SEC_MASK)

#define MSCM_SID_RAMSZ_MASK                      (0xE000U)
#define MSCM_SID_RAMSZ_SHIFT                     (13U)
/*! RAMSZ - RAM Size
 *  0b111..128 KB
 *  0b000..96 KB
 */
#define MSCM_SID_RAMSZ(x)                        (((uint32_t)(((uint32_t)(x)) << MSCM_SID_RAMSZ_SHIFT)) & MSCM_SID_RAMSZ_MASK)

#define MSCM_SID_FLSZ_MASK                       (0xF0000U)
#define MSCM_SID_FLSZ_SHIFT                      (16U)
/*! FLSZ - Flash Size
 *  0b1101..1 MB
 *  0b1111..512 KB
 */
#define MSCM_SID_FLSZ(x)                         (((uint32_t)(((uint32_t)(x)) << MSCM_SID_FLSZ_SHIFT)) & MSCM_SID_FLSZ_MASK)

#define MSCM_SID_BLEF_MASK                       (0xF00000U)
#define MSCM_SID_BLEF_SHIFT                      (20U)
/*! BLEF - Bluetooth LE Feature
 *  0b0000..No Bluetooth LE present
 *  0b0001..Bluetooth LE 5.1
 *  0b0010..Bluetooth LE 5.2
 *  0b0011..Bluetooth LE 5.3
 *  0b1111..Bluetooth LE Upgrade
 */
#define MSCM_SID_BLEF(x)                         (((uint32_t)(((uint32_t)(x)) << MSCM_SID_BLEF_SHIFT)) & MSCM_SID_BLEF_MASK)

#define MSCM_SID_RADIOF_MASK                     (0xF000000U)
#define MSCM_SID_RADIOF_SHIFT                    (24U)
/*! RADIOF - Radio Feature
 *  0b0000..802.15.4
 *  0b0001..Bluetooth LE
 *  0b0010..Bluetooth LE + 15.4
 */
#define MSCM_SID_RADIOF(x)                       (((uint32_t)(((uint32_t)(x)) << MSCM_SID_RADIOF_SHIFT)) & MSCM_SID_RADIOF_MASK)

#define MSCM_SID_FAMID_MASK                      (0xF0000000U)
#define MSCM_SID_FAMID_SHIFT                     (28U)
/*! FAMID - Family ID
 *  0b0000..K4W1
 */
#define MSCM_SID_FAMID(x)                        (((uint32_t)(((uint32_t)(x)) << MSCM_SID_FAMID_SHIFT)) & MSCM_SID_FAMID_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group MSCM_Register_Masks */


/* MSCM - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral MSCM base address */
  #define MSCM_BASE                                (0x50014000u)
  /** Peripheral MSCM base address */
  #define MSCM_BASE_NS                             (0x40014000u)
  /** Peripheral MSCM base pointer */
  #define MSCM                                     ((MSCM_Type *)MSCM_BASE)
  /** Peripheral MSCM base pointer */
  #define MSCM_NS                                  ((MSCM_Type *)MSCM_BASE_NS)
  /** Array initializer of MSCM peripheral base addresses */
  #define MSCM_BASE_ADDRS                          { MSCM_BASE }
  /** Array initializer of MSCM peripheral base pointers */
  #define MSCM_BASE_PTRS                           { MSCM }
  /** Array initializer of MSCM peripheral base addresses */
  #define MSCM_BASE_ADDRS_NS                       { MSCM_BASE_NS }
  /** Array initializer of MSCM peripheral base pointers */
  #define MSCM_BASE_PTRS_NS                        { MSCM_NS }
#else
  /** Peripheral MSCM base address */
  #define MSCM_BASE                                (0x40014000u)
  /** Peripheral MSCM base pointer */
  #define MSCM                                     ((MSCM_Type *)MSCM_BASE)
  /** Array initializer of MSCM peripheral base addresses */
  #define MSCM_BASE_ADDRS                          { MSCM_BASE }
  /** Array initializer of MSCM peripheral base pointers */
  #define MSCM_BASE_PTRS                           { MSCM }
#endif

/*!
 * @}
 */ /* end of group MSCM_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- PORT Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
 * @{
 */

/** PORT - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
       uint8_t RESERVED_0[12];
  __O  uint32_t GPCLR;                             /**< Global Pin Control Low Register, offset: 0x10 */
  __O  uint32_t GPCHR;                             /**< Global Pin Control High Register, offset: 0x14 */
       uint8_t RESERVED_1[8];
  __IO uint32_t CONFIG;                            /**< Configuration Register, offset: 0x20 */
       uint8_t RESERVED_2[28];
  __I  uint32_t EDFR;                              /**< EFT Detect Flag Register, offset: 0x40 */
  __IO uint32_t EDIER;                             /**< EFT Detect Interrupt Enable Register, offset: 0x44 */
  __IO uint32_t EDCR;                              /**< EFT Detect Clear Register, offset: 0x48 */
       uint8_t RESERVED_3[52];
  __IO uint32_t PCR[23];                           /**< Pin Control Register 0..Pin Control Register 6, array offset: 0x80, array step: 0x4 */
} PORT_Type;

/* ----------------------------------------------------------------------------
   -- PORT Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup PORT_Register_Masks PORT Register Masks
 * @{
 */

/*! @name VERID - Version ID Register */
/*! @{ */

#define PORT_VERID_FEATURE_MASK                  (0xFFFFU)
#define PORT_VERID_FEATURE_SHIFT                 (0U)
/*! FEATURE - Feature Specification Number
 *  0b0000000000000000..Basic implementation.
 */
#define PORT_VERID_FEATURE(x)                    (((uint32_t)(((uint32_t)(x)) << PORT_VERID_FEATURE_SHIFT)) & PORT_VERID_FEATURE_MASK)

#define PORT_VERID_MINOR_MASK                    (0xFF0000U)
#define PORT_VERID_MINOR_SHIFT                   (16U)
/*! MINOR - Minor Version Number
 */
#define PORT_VERID_MINOR(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_VERID_MINOR_SHIFT)) & PORT_VERID_MINOR_MASK)

#define PORT_VERID_MAJOR_MASK                    (0xFF000000U)
#define PORT_VERID_MAJOR_SHIFT                   (24U)
/*! MAJOR - Major Version Number
 */
#define PORT_VERID_MAJOR(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_VERID_MAJOR_SHIFT)) & PORT_VERID_MAJOR_MASK)
/*! @} */

/*! @name GPCLR - Global Pin Control Low Register */
/*! @{ */

#define PORT_GPCLR_GPWD_MASK                     (0xFFFFU)
#define PORT_GPCLR_GPWD_SHIFT                    (0U)
/*! GPWD - Global Pin Write Data
 */
#define PORT_GPCLR_GPWD(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)

#define PORT_GPCLR_GPWE0_MASK                    (0x10000U)
#define PORT_GPCLR_GPWE0_SHIFT                   (16U)
/*! GPWE0 - Global Pin Write Enable
 *  0b0..Corresponding lower 16-bit of the PCRa register is not updated with the value in GPWD.
 *  0b1..Corresponding lower 16-bit of the PCRa register is updated with the value in GPWD.
 */
#define PORT_GPCLR_GPWE0(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE0_SHIFT)) & PORT_GPCLR_GPWE0_MASK)

#define PORT_GPCLR_GPWE1_MASK                    (0x20000U)
#define PORT_GPCLR_GPWE1_SHIFT                   (17U)
/*! GPWE1 - Global Pin Write Enable
 *  0b0..Corresponding lower 16-bit of the PCRa register is not updated with the value in GPWD.
 *  0b1..Corresponding lower 16-bit of the PCRa register is updated with the value in GPWD.
 */
#define PORT_GPCLR_GPWE1(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE1_SHIFT)) & PORT_GPCLR_GPWE1_MASK)

#define PORT_GPCLR_GPWE2_MASK                    (0x40000U)
#define PORT_GPCLR_GPWE2_SHIFT                   (18U)
/*! GPWE2 - Global Pin Write Enable
 *  0b0..Corresponding lower 16-bit of the PCRa register is not updated with the value in GPWD.
 *  0b1..Corresponding lower 16-bit of the PCRa register is updated with the value in GPWD.
 */
#define PORT_GPCLR_GPWE2(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE2_SHIFT)) & PORT_GPCLR_GPWE2_MASK)

#define PORT_GPCLR_GPWE3_MASK                    (0x80000U)
#define PORT_GPCLR_GPWE3_SHIFT                   (19U)
/*! GPWE3 - Global Pin Write Enable
 *  0b0..Corresponding lower 16-bit of the PCRa register is not updated with the value in GPWD.
 *  0b1..Corresponding lower 16-bit of the PCRa register is updated with the value in GPWD.
 */
#define PORT_GPCLR_GPWE3(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE3_SHIFT)) & PORT_GPCLR_GPWE3_MASK)

#define PORT_GPCLR_GPWE4_MASK                    (0x100000U)
#define PORT_GPCLR_GPWE4_SHIFT                   (20U)
/*! GPWE4 - Global Pin Write Enable
 *  0b0..Corresponding lower 16-bit of the PCRa register is not updated with the value in GPWD.
 *  0b1..Corresponding lower 16-bit of the PCRa register is updated with the value in GPWD.
 */
#define PORT_GPCLR_GPWE4(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE4_SHIFT)) & PORT_GPCLR_GPWE4_MASK)

#define PORT_GPCLR_GPWE5_MASK                    (0x200000U)
#define PORT_GPCLR_GPWE5_SHIFT                   (21U)
/*! GPWE5 - Global Pin Write Enable
 *  0b0..Corresponding lower 16-bit of the PCRa register is not updated with the value in GPWD.
 *  0b1..Corresponding lower 16-bit of the PCRa register is updated with the value in GPWD.
 */
#define PORT_GPCLR_GPWE5(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE5_SHIFT)) & PORT_GPCLR_GPWE5_MASK)

#define PORT_GPCLR_GPWE6_MASK                    (0x400000U)
#define PORT_GPCLR_GPWE6_SHIFT                   (22U)
/*! GPWE6 - Global Pin Write Enable
 *  0b0..Corresponding lower 16-bit of the PCRa register is not updated with the value in GPWD.
 *  0b1..Corresponding lower 16-bit of the PCRa register is updated with the value in GPWD.
 */
#define PORT_GPCLR_GPWE6(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE6_SHIFT)) & PORT_GPCLR_GPWE6_MASK)

#define PORT_GPCLR_GPWE7_MASK                    (0x800000U)
#define PORT_GPCLR_GPWE7_SHIFT                   (23U)
/*! GPWE7 - Global Pin Write Enable
 *  0b0..Corresponding lower 16-bit of the PCRa register is not updated with the value in GPWD.
 *  0b1..Corresponding lower 16-bit of the PCRa register is updated with the value in GPWD.
 */
#define PORT_GPCLR_GPWE7(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE7_SHIFT)) & PORT_GPCLR_GPWE7_MASK)

#define PORT_GPCLR_GPWE8_MASK                    (0x1000000U)
#define PORT_GPCLR_GPWE8_SHIFT                   (24U)
/*! GPWE8 - Global Pin Write Enable
 *  0b0..Corresponding lower 16-bit of the PCRa register is not updated with the value in GPWD.
 *  0b1..Corresponding lower 16-bit of the PCRa register is updated with the value in GPWD.
 */
#define PORT_GPCLR_GPWE8(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE8_SHIFT)) & PORT_GPCLR_GPWE8_MASK)

#define PORT_GPCLR_GPWE9_MASK                    (0x2000000U)
#define PORT_GPCLR_GPWE9_SHIFT                   (25U)
/*! GPWE9 - Global Pin Write Enable
 *  0b0..Corresponding lower 16-bit of the PCRa register is not updated with the value in GPWD.
 *  0b1..Corresponding lower 16-bit of the PCRa register is updated with the value in GPWD.
 */
#define PORT_GPCLR_GPWE9(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE9_SHIFT)) & PORT_GPCLR_GPWE9_MASK)

#define PORT_GPCLR_GPWE10_MASK                   (0x4000000U)
#define PORT_GPCLR_GPWE10_SHIFT                  (26U)
/*! GPWE10 - Global Pin Write Enable
 *  0b0..Corresponding lower 16-bit of the PCRa register is not updated with the value in GPWD.
 *  0b1..Corresponding lower 16-bit of the PCRa register is updated with the value in GPWD.
 */
#define PORT_GPCLR_GPWE10(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE10_SHIFT)) & PORT_GPCLR_GPWE10_MASK)

#define PORT_GPCLR_GPWE11_MASK                   (0x8000000U)
#define PORT_GPCLR_GPWE11_SHIFT                  (27U)
/*! GPWE11 - Global Pin Write Enable
 *  0b0..Corresponding lower 16-bit of the PCRa register is not updated with the value in GPWD.
 *  0b1..Corresponding lower 16-bit of the PCRa register is updated with the value in GPWD.
 */
#define PORT_GPCLR_GPWE11(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE11_SHIFT)) & PORT_GPCLR_GPWE11_MASK)

#define PORT_GPCLR_GPWE12_MASK                   (0x10000000U)
#define PORT_GPCLR_GPWE12_SHIFT                  (28U)
/*! GPWE12 - Global Pin Write Enable
 *  0b0..Corresponding lower 16-bit of the PCRa register is not updated with the value in GPWD.
 *  0b1..Corresponding lower 16-bit of the PCRa register is updated with the value in GPWD.
 */
#define PORT_GPCLR_GPWE12(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE12_SHIFT)) & PORT_GPCLR_GPWE12_MASK)

#define PORT_GPCLR_GPWE13_MASK                   (0x20000000U)
#define PORT_GPCLR_GPWE13_SHIFT                  (29U)
/*! GPWE13 - Global Pin Write Enable
 *  0b0..Corresponding lower 16-bit of the PCRa register is not updated with the value in GPWD.
 *  0b1..Corresponding lower 16-bit of the PCRa register is updated with the value in GPWD.
 */
#define PORT_GPCLR_GPWE13(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE13_SHIFT)) & PORT_GPCLR_GPWE13_MASK)

#define PORT_GPCLR_GPWE14_MASK                   (0x40000000U)
#define PORT_GPCLR_GPWE14_SHIFT                  (30U)
/*! GPWE14 - Global Pin Write Enable
 *  0b0..Corresponding lower 16-bit of the PCRa register is not updated with the value in GPWD.
 *  0b1..Corresponding lower 16-bit of the PCRa register is updated with the value in GPWD.
 */
#define PORT_GPCLR_GPWE14(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE14_SHIFT)) & PORT_GPCLR_GPWE14_MASK)

#define PORT_GPCLR_GPWE15_MASK                   (0x80000000U)
#define PORT_GPCLR_GPWE15_SHIFT                  (31U)
/*! GPWE15 - Global Pin Write Enable
 *  0b0..Corresponding lower 16-bit of the PCRa register is not updated with the value in GPWD.
 *  0b1..Corresponding lower 16-bit of the PCRa register is updated with the value in GPWD.
 */
#define PORT_GPCLR_GPWE15(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE15_SHIFT)) & PORT_GPCLR_GPWE15_MASK)
/*! @} */

/*! @name GPCHR - Global Pin Control High Register */
/*! @{ */

#define PORT_GPCHR_GPWD_MASK                     (0xFFFFU)
#define PORT_GPCHR_GPWD_SHIFT                    (0U)
/*! GPWD - Global Pin Write Data
 */
#define PORT_GPCHR_GPWD(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)

#define PORT_GPCHR_GPWE16_MASK                   (0x10000U)
#define PORT_GPCHR_GPWE16_SHIFT                  (16U)
/*! GPWE16 - Global Pin Write Enable
 *  0b0..Corresponding lower 16-bit of the PCRa register is not updated with the value in GPWD.
 *  0b1..Corresponding lower 16-bit of the PCRa register is updated with the value in GPWD.
 */
#define PORT_GPCHR_GPWE16(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE16_SHIFT)) & PORT_GPCHR_GPWE16_MASK)

#define PORT_GPCHR_GPWE17_MASK                   (0x20000U)
#define PORT_GPCHR_GPWE17_SHIFT                  (17U)
/*! GPWE17 - Global Pin Write Enable
 *  0b0..Corresponding lower 16-bit of the PCRa register is not updated with the value in GPWD.
 *  0b1..Corresponding lower 16-bit of the PCRa register is updated with the value in GPWD.
 */
#define PORT_GPCHR_GPWE17(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE17_SHIFT)) & PORT_GPCHR_GPWE17_MASK)

#define PORT_GPCHR_GPWE18_MASK                   (0x40000U)
#define PORT_GPCHR_GPWE18_SHIFT                  (18U)
/*! GPWE18 - Global Pin Write Enable
 *  0b0..Corresponding lower 16-bit of the PCRa register is not updated with the value in GPWD.
 *  0b1..Corresponding lower 16-bit of the PCRa register is updated with the value in GPWD.
 */
#define PORT_GPCHR_GPWE18(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE18_SHIFT)) & PORT_GPCHR_GPWE18_MASK)

#define PORT_GPCHR_GPWE19_MASK                   (0x80000U)
#define PORT_GPCHR_GPWE19_SHIFT                  (19U)
/*! GPWE19 - Global Pin Write Enable
 *  0b0..Corresponding lower 16-bit of the PCRa register is not updated with the value in GPWD.
 *  0b1..Corresponding lower 16-bit of the PCRa register is updated with the value in GPWD.
 */
#define PORT_GPCHR_GPWE19(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE19_SHIFT)) & PORT_GPCHR_GPWE19_MASK)

#define PORT_GPCHR_GPWE20_MASK                   (0x100000U)
#define PORT_GPCHR_GPWE20_SHIFT                  (20U)
/*! GPWE20 - Global Pin Write Enable
 *  0b0..Corresponding lower 16-bit of the PCRa register is not updated with the value in GPWD.
 *  0b1..Corresponding lower 16-bit of the PCRa register is updated with the value in GPWD.
 */
#define PORT_GPCHR_GPWE20(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE20_SHIFT)) & PORT_GPCHR_GPWE20_MASK)

#define PORT_GPCHR_GPWE21_MASK                   (0x200000U)
#define PORT_GPCHR_GPWE21_SHIFT                  (21U)
/*! GPWE21 - Global Pin Write Enable
 *  0b0..Corresponding lower 16-bit of the PCRa register is not updated with the value in GPWD.
 *  0b1..Corresponding lower 16-bit of the PCRa register is updated with the value in GPWD.
 */
#define PORT_GPCHR_GPWE21(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE21_SHIFT)) & PORT_GPCHR_GPWE21_MASK)

#define PORT_GPCHR_GPWE22_MASK                   (0x400000U)
#define PORT_GPCHR_GPWE22_SHIFT                  (22U)
/*! GPWE22 - Global Pin Write Enable
 *  0b0..Corresponding lower 16-bit of the PCRa register is not updated with the value in GPWD.
 *  0b1..Corresponding lower 16-bit of the PCRa register is updated with the value in GPWD.
 */
#define PORT_GPCHR_GPWE22(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE22_SHIFT)) & PORT_GPCHR_GPWE22_MASK)

#define PORT_GPCHR_GPWE23_MASK                   (0x800000U)
#define PORT_GPCHR_GPWE23_SHIFT                  (23U)
/*! GPWE23 - Global Pin Write Enable
 *  0b0..Corresponding lower 16-bit of the PCRa register is not updated with the value in GPWD.
 *  0b1..Corresponding lower 16-bit of the PCRa register is updated with the value in GPWD.
 */
#define PORT_GPCHR_GPWE23(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE23_SHIFT)) & PORT_GPCHR_GPWE23_MASK)

#define PORT_GPCHR_GPWE24_MASK                   (0x1000000U)
#define PORT_GPCHR_GPWE24_SHIFT                  (24U)
/*! GPWE24 - Global Pin Write Enable
 *  0b0..Corresponding lower 16-bit of the PCRa register is not updated with the value in GPWD.
 *  0b1..Corresponding lower 16-bit of the PCRa register is updated with the value in GPWD.
 */
#define PORT_GPCHR_GPWE24(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE24_SHIFT)) & PORT_GPCHR_GPWE24_MASK)

#define PORT_GPCHR_GPWE25_MASK                   (0x2000000U)
#define PORT_GPCHR_GPWE25_SHIFT                  (25U)
/*! GPWE25 - Global Pin Write Enable
 *  0b0..Corresponding lower 16-bit of the PCRa register is not updated with the value in GPWD.
 *  0b1..Corresponding lower 16-bit of the PCRa register is updated with the value in GPWD.
 */
#define PORT_GPCHR_GPWE25(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE25_SHIFT)) & PORT_GPCHR_GPWE25_MASK)

#define PORT_GPCHR_GPWE26_MASK                   (0x4000000U)
#define PORT_GPCHR_GPWE26_SHIFT                  (26U)
/*! GPWE26 - Global Pin Write Enable
 *  0b0..Corresponding lower 16-bit of the PCRa register is not updated with the value in GPWD.
 *  0b1..Corresponding lower 16-bit of the PCRa register is updated with the value in GPWD.
 */
#define PORT_GPCHR_GPWE26(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE26_SHIFT)) & PORT_GPCHR_GPWE26_MASK)

#define PORT_GPCHR_GPWE27_MASK                   (0x8000000U)
#define PORT_GPCHR_GPWE27_SHIFT                  (27U)
/*! GPWE27 - Global Pin Write Enable
 *  0b0..Corresponding lower 16-bit of the PCRa register is not updated with the value in GPWD.
 *  0b1..Corresponding lower 16-bit of the PCRa register is updated with the value in GPWD.
 */
#define PORT_GPCHR_GPWE27(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE27_SHIFT)) & PORT_GPCHR_GPWE27_MASK)

#define PORT_GPCHR_GPWE28_MASK                   (0x10000000U)
#define PORT_GPCHR_GPWE28_SHIFT                  (28U)
/*! GPWE28 - Global Pin Write Enable
 *  0b0..Corresponding lower 16-bit of the PCRa register is not updated with the value in GPWD.
 *  0b1..Corresponding lower 16-bit of the PCRa register is updated with the value in GPWD.
 */
#define PORT_GPCHR_GPWE28(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE28_SHIFT)) & PORT_GPCHR_GPWE28_MASK)

#define PORT_GPCHR_GPWE29_MASK                   (0x20000000U)
#define PORT_GPCHR_GPWE29_SHIFT                  (29U)
/*! GPWE29 - Global Pin Write Enable
 *  0b0..Corresponding lower 16-bit of the PCRa register is not updated with the value in GPWD.
 *  0b1..Corresponding lower 16-bit of the PCRa register is updated with the value in GPWD.
 */
#define PORT_GPCHR_GPWE29(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE29_SHIFT)) & PORT_GPCHR_GPWE29_MASK)

#define PORT_GPCHR_GPWE30_MASK                   (0x40000000U)
#define PORT_GPCHR_GPWE30_SHIFT                  (30U)
/*! GPWE30 - Global Pin Write Enable
 *  0b0..Corresponding lower 16-bit of the PCRa register is not updated with the value in GPWD.
 *  0b1..Corresponding lower 16-bit of the PCRa register is updated with the value in GPWD.
 */
#define PORT_GPCHR_GPWE30(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE30_SHIFT)) & PORT_GPCHR_GPWE30_MASK)

#define PORT_GPCHR_GPWE31_MASK                   (0x80000000U)
#define PORT_GPCHR_GPWE31_SHIFT                  (31U)
/*! GPWE31 - Global Pin Write Enable
 *  0b0..Corresponding lower 16-bit of the PCRa register is not updated with the value in GPWD.
 *  0b1..Corresponding lower 16-bit of the PCRa register is updated with the value in GPWD.
 */
#define PORT_GPCHR_GPWE31(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE31_SHIFT)) & PORT_GPCHR_GPWE31_MASK)
/*! @} */

/*! @name CONFIG - Configuration Register */
/*! @{ */

#define PORT_CONFIG_RANGE_MASK                   (0x1U)
#define PORT_CONFIG_RANGE_SHIFT                  (0U)
/*! RANGE - Port Voltage Range
 *  0b0..Port voltage range is 1.71 V - 3.6 V.
 *  0b1..Port voltage range is 2.70 V - 3.6 V.
 */
#define PORT_CONFIG_RANGE(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_CONFIG_RANGE_SHIFT)) & PORT_CONFIG_RANGE_MASK)
/*! @} */

/*! @name EDFR - EFT Detect Flag Register */
/*! @{ */

#define PORT_EDFR_EDF0_MASK                      (0x1U)
#define PORT_EDFR_EDF0_SHIFT                     (0U)
/*! EDF0 - EFT Detect Flag
 *  0b0..No EFT event has been detected.
 *  0b1..High or/and Low EFT event has been detected.
 */
#define PORT_EDFR_EDF0(x)                        (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF0_SHIFT)) & PORT_EDFR_EDF0_MASK)

#define PORT_EDFR_EDF1_MASK                      (0x2U)
#define PORT_EDFR_EDF1_SHIFT                     (1U)
/*! EDF1 - EFT Detect Flag
 *  0b0..No EFT event has been detected.
 *  0b1..High or/and Low EFT event has been detected.
 */
#define PORT_EDFR_EDF1(x)                        (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF1_SHIFT)) & PORT_EDFR_EDF1_MASK)

#define PORT_EDFR_EDF2_MASK                      (0x4U)
#define PORT_EDFR_EDF2_SHIFT                     (2U)
/*! EDF2 - EFT Detect Flag
 *  0b0..No EFT event has been detected.
 *  0b1..High or/and Low EFT event has been detected.
 */
#define PORT_EDFR_EDF2(x)                        (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF2_SHIFT)) & PORT_EDFR_EDF2_MASK)

#define PORT_EDFR_EDF3_MASK                      (0x8U)
#define PORT_EDFR_EDF3_SHIFT                     (3U)
/*! EDF3 - EFT Detect Flag
 *  0b0..No EFT event has been detected.
 *  0b1..High or/and Low EFT event has been detected.
 */
#define PORT_EDFR_EDF3(x)                        (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF3_SHIFT)) & PORT_EDFR_EDF3_MASK)

#define PORT_EDFR_EDF4_MASK                      (0x10U)
#define PORT_EDFR_EDF4_SHIFT                     (4U)
/*! EDF4 - EFT Detect Flag
 *  0b0..No EFT event has been detected.
 *  0b1..High or/and Low EFT event has been detected.
 */
#define PORT_EDFR_EDF4(x)                        (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF4_SHIFT)) & PORT_EDFR_EDF4_MASK)

#define PORT_EDFR_EDF5_MASK                      (0x20U)
#define PORT_EDFR_EDF5_SHIFT                     (5U)
/*! EDF5 - EFT Detect Flag
 *  0b0..No EFT event has been detected.
 *  0b1..High or/and Low EFT event has been detected.
 */
#define PORT_EDFR_EDF5(x)                        (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF5_SHIFT)) & PORT_EDFR_EDF5_MASK)

#define PORT_EDFR_EDF6_MASK                      (0x40U)
#define PORT_EDFR_EDF6_SHIFT                     (6U)
/*! EDF6 - EFT Detect Flag
 *  0b0..No EFT event has been detected.
 *  0b1..High or/and Low EFT event has been detected.
 */
#define PORT_EDFR_EDF6(x)                        (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF6_SHIFT)) & PORT_EDFR_EDF6_MASK)

#define PORT_EDFR_Reserved6_MASK                 (0x40U)
#define PORT_EDFR_Reserved6_SHIFT                (6U)
/*! Reserved6 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define PORT_EDFR_Reserved6(x)                   (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved6_SHIFT)) & PORT_EDFR_Reserved6_MASK)

#define PORT_EDFR_Reserved7_MASK                 (0x80U)
#define PORT_EDFR_Reserved7_SHIFT                (7U)
/*! Reserved7 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define PORT_EDFR_Reserved7(x)                   (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved7_SHIFT)) & PORT_EDFR_Reserved7_MASK)

#define PORT_EDFR_EDF8_MASK                      (0x100U)
#define PORT_EDFR_EDF8_SHIFT                     (8U)
/*! EDF8 - EFT Detect Flag
 *  0b0..No EFT event has been detected.
 *  0b1..High or/and Low EFT event has been detected.
 */
#define PORT_EDFR_EDF8(x)                        (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF8_SHIFT)) & PORT_EDFR_EDF8_MASK)

#define PORT_EDFR_Reserved8_MASK                 (0x100U)
#define PORT_EDFR_Reserved8_SHIFT                (8U)
/*! Reserved8 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define PORT_EDFR_Reserved8(x)                   (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved8_SHIFT)) & PORT_EDFR_Reserved8_MASK)

#define PORT_EDFR_EDF9_MASK                      (0x200U)
#define PORT_EDFR_EDF9_SHIFT                     (9U)
/*! EDF9 - EFT Detect Flag
 *  0b0..No EFT event has been detected.
 *  0b1..High or/and Low EFT event has been detected.
 */
#define PORT_EDFR_EDF9(x)                        (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF9_SHIFT)) & PORT_EDFR_EDF9_MASK)

#define PORT_EDFR_Reserved9_MASK                 (0x200U)
#define PORT_EDFR_Reserved9_SHIFT                (9U)
/*! Reserved9 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define PORT_EDFR_Reserved9(x)                   (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved9_SHIFT)) & PORT_EDFR_Reserved9_MASK)

#define PORT_EDFR_Reserved10_MASK                (0x400U)
#define PORT_EDFR_Reserved10_SHIFT               (10U)
/*! Reserved10 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define PORT_EDFR_Reserved10(x)                  (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved10_SHIFT)) & PORT_EDFR_Reserved10_MASK)

#define PORT_EDFR_Reserved11_MASK                (0x800U)
#define PORT_EDFR_Reserved11_SHIFT               (11U)
/*! Reserved11 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define PORT_EDFR_Reserved11(x)                  (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved11_SHIFT)) & PORT_EDFR_Reserved11_MASK)

#define PORT_EDFR_Reserved12_MASK                (0x1000U)
#define PORT_EDFR_Reserved12_SHIFT               (12U)
/*! Reserved12 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define PORT_EDFR_Reserved12(x)                  (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved12_SHIFT)) & PORT_EDFR_Reserved12_MASK)

#define PORT_EDFR_Reserved13_MASK                (0x2000U)
#define PORT_EDFR_Reserved13_SHIFT               (13U)
/*! Reserved13 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define PORT_EDFR_Reserved13(x)                  (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved13_SHIFT)) & PORT_EDFR_Reserved13_MASK)

#define PORT_EDFR_Reserved14_MASK                (0x4000U)
#define PORT_EDFR_Reserved14_SHIFT               (14U)
/*! Reserved14 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define PORT_EDFR_Reserved14(x)                  (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved14_SHIFT)) & PORT_EDFR_Reserved14_MASK)

#define PORT_EDFR_Reserved15_MASK                (0x8000U)
#define PORT_EDFR_Reserved15_SHIFT               (15U)
/*! Reserved15 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define PORT_EDFR_Reserved15(x)                  (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved15_SHIFT)) & PORT_EDFR_Reserved15_MASK)

#define PORT_EDFR_EDF16_MASK                     (0x10000U)
#define PORT_EDFR_EDF16_SHIFT                    (16U)
/*! EDF16 - EFT Detect Flag
 *  0b0..No EFT event has been detected.
 *  0b1..High or/and Low EFT event has been detected.
 */
#define PORT_EDFR_EDF16(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF16_SHIFT)) & PORT_EDFR_EDF16_MASK)

#define PORT_EDFR_Reserved16_MASK                (0x10000U)
#define PORT_EDFR_Reserved16_SHIFT               (16U)
/*! Reserved16 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define PORT_EDFR_Reserved16(x)                  (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved16_SHIFT)) & PORT_EDFR_Reserved16_MASK)

#define PORT_EDFR_EDF17_MASK                     (0x20000U)
#define PORT_EDFR_EDF17_SHIFT                    (17U)
/*! EDF17 - EFT Detect Flag
 *  0b0..No EFT event has been detected.
 *  0b1..High or/and Low EFT event has been detected.
 */
#define PORT_EDFR_EDF17(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF17_SHIFT)) & PORT_EDFR_EDF17_MASK)

#define PORT_EDFR_Reserved17_MASK                (0x20000U)
#define PORT_EDFR_Reserved17_SHIFT               (17U)
/*! Reserved17 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define PORT_EDFR_Reserved17(x)                  (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved17_SHIFT)) & PORT_EDFR_Reserved17_MASK)

#define PORT_EDFR_EDF18_MASK                     (0x40000U)
#define PORT_EDFR_EDF18_SHIFT                    (18U)
/*! EDF18 - EFT Detect Flag
 *  0b0..No EFT event has been detected.
 *  0b1..High or/and Low EFT event has been detected.
 */
#define PORT_EDFR_EDF18(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF18_SHIFT)) & PORT_EDFR_EDF18_MASK)

#define PORT_EDFR_Reserved18_MASK                (0x40000U)
#define PORT_EDFR_Reserved18_SHIFT               (18U)
/*! Reserved18 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define PORT_EDFR_Reserved18(x)                  (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved18_SHIFT)) & PORT_EDFR_Reserved18_MASK)

#define PORT_EDFR_EDF19_MASK                     (0x80000U)
#define PORT_EDFR_EDF19_SHIFT                    (19U)
/*! EDF19 - EFT Detect Flag
 *  0b0..No EFT event has been detected.
 *  0b1..High or/and Low EFT event has been detected.
 */
#define PORT_EDFR_EDF19(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF19_SHIFT)) & PORT_EDFR_EDF19_MASK)

#define PORT_EDFR_Reserved19_MASK                (0x80000U)
#define PORT_EDFR_Reserved19_SHIFT               (19U)
/*! Reserved19 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define PORT_EDFR_Reserved19(x)                  (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved19_SHIFT)) & PORT_EDFR_Reserved19_MASK)

#define PORT_EDFR_EDF20_MASK                     (0x100000U)
#define PORT_EDFR_EDF20_SHIFT                    (20U)
/*! EDF20 - EFT Detect Flag
 *  0b0..No EFT event has been detected.
 *  0b1..High or/and Low EFT event has been detected.
 */
#define PORT_EDFR_EDF20(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF20_SHIFT)) & PORT_EDFR_EDF20_MASK)

#define PORT_EDFR_Reserved20_MASK                (0x100000U)
#define PORT_EDFR_Reserved20_SHIFT               (20U)
/*! Reserved20 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define PORT_EDFR_Reserved20(x)                  (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved20_SHIFT)) & PORT_EDFR_Reserved20_MASK)

#define PORT_EDFR_EDF21_MASK                     (0x200000U)
#define PORT_EDFR_EDF21_SHIFT                    (21U)
/*! EDF21 - EFT Detect Flag
 *  0b0..No EFT event has been detected.
 *  0b1..High or/and Low EFT event has been detected.
 */
#define PORT_EDFR_EDF21(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF21_SHIFT)) & PORT_EDFR_EDF21_MASK)

#define PORT_EDFR_Reserved21_MASK                (0x200000U)
#define PORT_EDFR_Reserved21_SHIFT               (21U)
/*! Reserved21 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define PORT_EDFR_Reserved21(x)                  (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved21_SHIFT)) & PORT_EDFR_Reserved21_MASK)

#define PORT_EDFR_EDF22_MASK                     (0x400000U)
#define PORT_EDFR_EDF22_SHIFT                    (22U)
/*! EDF22 - EFT Detect Flag
 *  0b0..No EFT event has been detected.
 *  0b1..High or/and Low EFT event has been detected.
 */
#define PORT_EDFR_EDF22(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF22_SHIFT)) & PORT_EDFR_EDF22_MASK)

#define PORT_EDFR_Reserved22_MASK                (0x400000U)
#define PORT_EDFR_Reserved22_SHIFT               (22U)
/*! Reserved22 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define PORT_EDFR_Reserved22(x)                  (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved22_SHIFT)) & PORT_EDFR_Reserved22_MASK)

#define PORT_EDFR_Reserved23_MASK                (0x800000U)
#define PORT_EDFR_Reserved23_SHIFT               (23U)
/*! Reserved23 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define PORT_EDFR_Reserved23(x)                  (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved23_SHIFT)) & PORT_EDFR_Reserved23_MASK)

#define PORT_EDFR_Reserved24_MASK                (0x1000000U)
#define PORT_EDFR_Reserved24_SHIFT               (24U)
/*! Reserved24 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define PORT_EDFR_Reserved24(x)                  (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved24_SHIFT)) & PORT_EDFR_Reserved24_MASK)

#define PORT_EDFR_Reserved25_MASK                (0x2000000U)
#define PORT_EDFR_Reserved25_SHIFT               (25U)
/*! Reserved25 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define PORT_EDFR_Reserved25(x)                  (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved25_SHIFT)) & PORT_EDFR_Reserved25_MASK)

#define PORT_EDFR_Reserved26_MASK                (0x4000000U)
#define PORT_EDFR_Reserved26_SHIFT               (26U)
/*! Reserved26 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define PORT_EDFR_Reserved26(x)                  (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved26_SHIFT)) & PORT_EDFR_Reserved26_MASK)

#define PORT_EDFR_Reserved27_MASK                (0x8000000U)
#define PORT_EDFR_Reserved27_SHIFT               (27U)
/*! Reserved27 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define PORT_EDFR_Reserved27(x)                  (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved27_SHIFT)) & PORT_EDFR_Reserved27_MASK)

#define PORT_EDFR_Reserved28_MASK                (0x10000000U)
#define PORT_EDFR_Reserved28_SHIFT               (28U)
/*! Reserved28 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define PORT_EDFR_Reserved28(x)                  (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved28_SHIFT)) & PORT_EDFR_Reserved28_MASK)

#define PORT_EDFR_Reserved29_MASK                (0x20000000U)
#define PORT_EDFR_Reserved29_SHIFT               (29U)
/*! Reserved29 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define PORT_EDFR_Reserved29(x)                  (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved29_SHIFT)) & PORT_EDFR_Reserved29_MASK)

#define PORT_EDFR_Reserved30_MASK                (0x40000000U)
#define PORT_EDFR_Reserved30_SHIFT               (30U)
/*! Reserved30 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define PORT_EDFR_Reserved30(x)                  (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved30_SHIFT)) & PORT_EDFR_Reserved30_MASK)

#define PORT_EDFR_Reserved31_MASK                (0x80000000U)
#define PORT_EDFR_Reserved31_SHIFT               (31U)
/*! Reserved31 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define PORT_EDFR_Reserved31(x)                  (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_Reserved31_SHIFT)) & PORT_EDFR_Reserved31_MASK)
/*! @} */

/*! @name EDIER - EFT Detect Interrupt Enable Register */
/*! @{ */

#define PORT_EDIER_EDIE0_MASK                    (0x1U)
#define PORT_EDIER_EDIE0_SHIFT                   (0U)
/*! EDIE0 - EFT Detect Interrupt Enable
 *  0b0..Interrupt will not be generated when the EFT event is detected.
 *  0b1..Interrupt will be generated when the EFT event is detected.
 */
#define PORT_EDIER_EDIE0(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE0_SHIFT)) & PORT_EDIER_EDIE0_MASK)

#define PORT_EDIER_EDIE1_MASK                    (0x2U)
#define PORT_EDIER_EDIE1_SHIFT                   (1U)
/*! EDIE1 - EFT Detect Interrupt Enable
 *  0b0..Interrupt will not be generated when the EFT event is detected.
 *  0b1..Interrupt will be generated when the EFT event is detected.
 */
#define PORT_EDIER_EDIE1(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE1_SHIFT)) & PORT_EDIER_EDIE1_MASK)

#define PORT_EDIER_EDIE2_MASK                    (0x4U)
#define PORT_EDIER_EDIE2_SHIFT                   (2U)
/*! EDIE2 - EFT Detect Interrupt Enable
 *  0b0..Interrupt will not be generated when the EFT event is detected.
 *  0b1..Interrupt will be generated when the EFT event is detected.
 */
#define PORT_EDIER_EDIE2(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE2_SHIFT)) & PORT_EDIER_EDIE2_MASK)

#define PORT_EDIER_EDIE3_MASK                    (0x8U)
#define PORT_EDIER_EDIE3_SHIFT                   (3U)
/*! EDIE3 - EFT Detect Interrupt Enable
 *  0b0..Interrupt will not be generated when the EFT event is detected.
 *  0b1..Interrupt will be generated when the EFT event is detected.
 */
#define PORT_EDIER_EDIE3(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE3_SHIFT)) & PORT_EDIER_EDIE3_MASK)

#define PORT_EDIER_EDIE4_MASK                    (0x10U)
#define PORT_EDIER_EDIE4_SHIFT                   (4U)
/*! EDIE4 - EFT Detect Interrupt Enable
 *  0b0..Interrupt will not be generated when the EFT event is detected.
 *  0b1..Interrupt will be generated when the EFT event is detected.
 */
#define PORT_EDIER_EDIE4(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE4_SHIFT)) & PORT_EDIER_EDIE4_MASK)

#define PORT_EDIER_EDIE5_MASK                    (0x20U)
#define PORT_EDIER_EDIE5_SHIFT                   (5U)
/*! EDIE5 - EFT Detect Interrupt Enable
 *  0b0..Interrupt will not be generated when the EFT event is detected.
 *  0b1..Interrupt will be generated when the EFT event is detected.
 */
#define PORT_EDIER_EDIE5(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE5_SHIFT)) & PORT_EDIER_EDIE5_MASK)

#define PORT_EDIER_EDIE6_MASK                    (0x40U)
#define PORT_EDIER_EDIE6_SHIFT                   (6U)
/*! EDIE6 - EFT Detect Interrupt Enable
 *  0b0..Interrupt will not be generated when the EFT event is detected.
 *  0b1..Interrupt will be generated when the EFT event is detected.
 */
#define PORT_EDIER_EDIE6(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE6_SHIFT)) & PORT_EDIER_EDIE6_MASK)

#define PORT_EDIER_Reserved6_MASK                (0x40U)
#define PORT_EDIER_Reserved6_SHIFT               (6U)
/*! Reserved6 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define PORT_EDIER_Reserved6(x)                  (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved6_SHIFT)) & PORT_EDIER_Reserved6_MASK)

#define PORT_EDIER_Reserved7_MASK                (0x80U)
#define PORT_EDIER_Reserved7_SHIFT               (7U)
/*! Reserved7 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define PORT_EDIER_Reserved7(x)                  (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved7_SHIFT)) & PORT_EDIER_Reserved7_MASK)

#define PORT_EDIER_EDIE8_MASK                    (0x100U)
#define PORT_EDIER_EDIE8_SHIFT                   (8U)
/*! EDIE8 - EFT Detect Interrupt Enable
 *  0b0..Interrupt will not be generated when the EFT event is detected.
 *  0b1..Interrupt will be generated when the EFT event is detected.
 */
#define PORT_EDIER_EDIE8(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE8_SHIFT)) & PORT_EDIER_EDIE8_MASK)

#define PORT_EDIER_Reserved8_MASK                (0x100U)
#define PORT_EDIER_Reserved8_SHIFT               (8U)
/*! Reserved8 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define PORT_EDIER_Reserved8(x)                  (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved8_SHIFT)) & PORT_EDIER_Reserved8_MASK)

#define PORT_EDIER_EDIE9_MASK                    (0x200U)
#define PORT_EDIER_EDIE9_SHIFT                   (9U)
/*! EDIE9 - EFT Detect Interrupt Enable
 *  0b0..Interrupt will not be generated when the EFT event is detected.
 *  0b1..Interrupt will be generated when the EFT event is detected.
 */
#define PORT_EDIER_EDIE9(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE9_SHIFT)) & PORT_EDIER_EDIE9_MASK)

#define PORT_EDIER_Reserved9_MASK                (0x200U)
#define PORT_EDIER_Reserved9_SHIFT               (9U)
/*! Reserved9 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define PORT_EDIER_Reserved9(x)                  (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved9_SHIFT)) & PORT_EDIER_Reserved9_MASK)

#define PORT_EDIER_Reserved10_MASK               (0x400U)
#define PORT_EDIER_Reserved10_SHIFT              (10U)
/*! Reserved10 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define PORT_EDIER_Reserved10(x)                 (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved10_SHIFT)) & PORT_EDIER_Reserved10_MASK)

#define PORT_EDIER_Reserved11_MASK               (0x800U)
#define PORT_EDIER_Reserved11_SHIFT              (11U)
/*! Reserved11 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define PORT_EDIER_Reserved11(x)                 (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved11_SHIFT)) & PORT_EDIER_Reserved11_MASK)

#define PORT_EDIER_Reserved12_MASK               (0x1000U)
#define PORT_EDIER_Reserved12_SHIFT              (12U)
/*! Reserved12 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define PORT_EDIER_Reserved12(x)                 (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved12_SHIFT)) & PORT_EDIER_Reserved12_MASK)

#define PORT_EDIER_Reserved13_MASK               (0x2000U)
#define PORT_EDIER_Reserved13_SHIFT              (13U)
/*! Reserved13 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define PORT_EDIER_Reserved13(x)                 (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved13_SHIFT)) & PORT_EDIER_Reserved13_MASK)

#define PORT_EDIER_Reserved14_MASK               (0x4000U)
#define PORT_EDIER_Reserved14_SHIFT              (14U)
/*! Reserved14 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define PORT_EDIER_Reserved14(x)                 (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved14_SHIFT)) & PORT_EDIER_Reserved14_MASK)

#define PORT_EDIER_Reserved15_MASK               (0x8000U)
#define PORT_EDIER_Reserved15_SHIFT              (15U)
/*! Reserved15 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define PORT_EDIER_Reserved15(x)                 (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved15_SHIFT)) & PORT_EDIER_Reserved15_MASK)

#define PORT_EDIER_EDIE16_MASK                   (0x10000U)
#define PORT_EDIER_EDIE16_SHIFT                  (16U)
/*! EDIE16 - EFT Detect Interrupt Enable
 *  0b0..Interrupt will not be generated when the EFT event is detected.
 *  0b1..Interrupt will be generated when the EFT event is detected.
 */
#define PORT_EDIER_EDIE16(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE16_SHIFT)) & PORT_EDIER_EDIE16_MASK)

#define PORT_EDIER_Reserved16_MASK               (0x10000U)
#define PORT_EDIER_Reserved16_SHIFT              (16U)
/*! Reserved16 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define PORT_EDIER_Reserved16(x)                 (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved16_SHIFT)) & PORT_EDIER_Reserved16_MASK)

#define PORT_EDIER_EDIE17_MASK                   (0x20000U)
#define PORT_EDIER_EDIE17_SHIFT                  (17U)
/*! EDIE17 - EFT Detect Interrupt Enable
 *  0b0..Interrupt will not be generated when the EFT event is detected.
 *  0b1..Interrupt will be generated when the EFT event is detected.
 */
#define PORT_EDIER_EDIE17(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE17_SHIFT)) & PORT_EDIER_EDIE17_MASK)

#define PORT_EDIER_Reserved17_MASK               (0x20000U)
#define PORT_EDIER_Reserved17_SHIFT              (17U)
/*! Reserved17 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define PORT_EDIER_Reserved17(x)                 (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved17_SHIFT)) & PORT_EDIER_Reserved17_MASK)

#define PORT_EDIER_EDIE18_MASK                   (0x40000U)
#define PORT_EDIER_EDIE18_SHIFT                  (18U)
/*! EDIE18 - EFT Detect Interrupt Enable
 *  0b0..Interrupt will not be generated when the EFT event is detected.
 *  0b1..Interrupt will be generated when the EFT event is detected.
 */
#define PORT_EDIER_EDIE18(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE18_SHIFT)) & PORT_EDIER_EDIE18_MASK)

#define PORT_EDIER_Reserved18_MASK               (0x40000U)
#define PORT_EDIER_Reserved18_SHIFT              (18U)
/*! Reserved18 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define PORT_EDIER_Reserved18(x)                 (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved18_SHIFT)) & PORT_EDIER_Reserved18_MASK)

#define PORT_EDIER_EDIE19_MASK                   (0x80000U)
#define PORT_EDIER_EDIE19_SHIFT                  (19U)
/*! EDIE19 - EFT Detect Interrupt Enable
 *  0b0..Interrupt will not be generated when the EFT event is detected.
 *  0b1..Interrupt will be generated when the EFT event is detected.
 */
#define PORT_EDIER_EDIE19(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE19_SHIFT)) & PORT_EDIER_EDIE19_MASK)

#define PORT_EDIER_Reserved19_MASK               (0x80000U)
#define PORT_EDIER_Reserved19_SHIFT              (19U)
/*! Reserved19 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define PORT_EDIER_Reserved19(x)                 (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved19_SHIFT)) & PORT_EDIER_Reserved19_MASK)

#define PORT_EDIER_EDIE20_MASK                   (0x100000U)
#define PORT_EDIER_EDIE20_SHIFT                  (20U)
/*! EDIE20 - EFT Detect Interrupt Enable
 *  0b0..Interrupt will not be generated when the EFT event is detected.
 *  0b1..Interrupt will be generated when the EFT event is detected.
 */
#define PORT_EDIER_EDIE20(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE20_SHIFT)) & PORT_EDIER_EDIE20_MASK)

#define PORT_EDIER_Reserved20_MASK               (0x100000U)
#define PORT_EDIER_Reserved20_SHIFT              (20U)
/*! Reserved20 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define PORT_EDIER_Reserved20(x)                 (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved20_SHIFT)) & PORT_EDIER_Reserved20_MASK)

#define PORT_EDIER_EDIE21_MASK                   (0x200000U)
#define PORT_EDIER_EDIE21_SHIFT                  (21U)
/*! EDIE21 - EFT Detect Interrupt Enable
 *  0b0..Interrupt will not be generated when the EFT event is detected.
 *  0b1..Interrupt will be generated when the EFT event is detected.
 */
#define PORT_EDIER_EDIE21(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE21_SHIFT)) & PORT_EDIER_EDIE21_MASK)

#define PORT_EDIER_Reserved21_MASK               (0x200000U)
#define PORT_EDIER_Reserved21_SHIFT              (21U)
/*! Reserved21 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define PORT_EDIER_Reserved21(x)                 (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved21_SHIFT)) & PORT_EDIER_Reserved21_MASK)

#define PORT_EDIER_EDIE22_MASK                   (0x400000U)
#define PORT_EDIER_EDIE22_SHIFT                  (22U)
/*! EDIE22 - EFT Detect Interrupt Enable
 *  0b0..Interrupt will not be generated when the EFT event is detected.
 *  0b1..Interrupt will be generated when the EFT event is detected.
 */
#define PORT_EDIER_EDIE22(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE22_SHIFT)) & PORT_EDIER_EDIE22_MASK)

#define PORT_EDIER_Reserved22_MASK               (0x400000U)
#define PORT_EDIER_Reserved22_SHIFT              (22U)
/*! Reserved22 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define PORT_EDIER_Reserved22(x)                 (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved22_SHIFT)) & PORT_EDIER_Reserved22_MASK)

#define PORT_EDIER_Reserved23_MASK               (0x800000U)
#define PORT_EDIER_Reserved23_SHIFT              (23U)
/*! Reserved23 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define PORT_EDIER_Reserved23(x)                 (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved23_SHIFT)) & PORT_EDIER_Reserved23_MASK)

#define PORT_EDIER_Reserved24_MASK               (0x1000000U)
#define PORT_EDIER_Reserved24_SHIFT              (24U)
/*! Reserved24 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define PORT_EDIER_Reserved24(x)                 (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved24_SHIFT)) & PORT_EDIER_Reserved24_MASK)

#define PORT_EDIER_Reserved25_MASK               (0x2000000U)
#define PORT_EDIER_Reserved25_SHIFT              (25U)
/*! Reserved25 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define PORT_EDIER_Reserved25(x)                 (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved25_SHIFT)) & PORT_EDIER_Reserved25_MASK)

#define PORT_EDIER_Reserved26_MASK               (0x4000000U)
#define PORT_EDIER_Reserved26_SHIFT              (26U)
/*! Reserved26 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define PORT_EDIER_Reserved26(x)                 (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved26_SHIFT)) & PORT_EDIER_Reserved26_MASK)

#define PORT_EDIER_Reserved27_MASK               (0x8000000U)
#define PORT_EDIER_Reserved27_SHIFT              (27U)
/*! Reserved27 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define PORT_EDIER_Reserved27(x)                 (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved27_SHIFT)) & PORT_EDIER_Reserved27_MASK)

#define PORT_EDIER_Reserved28_MASK               (0x10000000U)
#define PORT_EDIER_Reserved28_SHIFT              (28U)
/*! Reserved28 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define PORT_EDIER_Reserved28(x)                 (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved28_SHIFT)) & PORT_EDIER_Reserved28_MASK)

#define PORT_EDIER_Reserved29_MASK               (0x20000000U)
#define PORT_EDIER_Reserved29_SHIFT              (29U)
/*! Reserved29 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define PORT_EDIER_Reserved29(x)                 (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved29_SHIFT)) & PORT_EDIER_Reserved29_MASK)

#define PORT_EDIER_Reserved30_MASK               (0x40000000U)
#define PORT_EDIER_Reserved30_SHIFT              (30U)
/*! Reserved30 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define PORT_EDIER_Reserved30(x)                 (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved30_SHIFT)) & PORT_EDIER_Reserved30_MASK)

#define PORT_EDIER_Reserved31_MASK               (0x80000000U)
#define PORT_EDIER_Reserved31_SHIFT              (31U)
/*! Reserved31 - Reserved
 *  0b0..Not supported
 *  0b1..Not supported
 */
#define PORT_EDIER_Reserved31(x)                 (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_Reserved31_SHIFT)) & PORT_EDIER_Reserved31_MASK)
/*! @} */

/*! @name EDCR - EFT Detect Clear Register */
/*! @{ */

#define PORT_EDCR_EDHC_MASK                      (0x1U)
#define PORT_EDCR_EDHC_SHIFT                     (0U)
/*! EDHC - EFT Detect High Clear
 *  0b0..Do not clear high EFT detectors.
 *  0b1..Clear high EFT detectors.
 */
#define PORT_EDCR_EDHC(x)                        (((uint32_t)(((uint32_t)(x)) << PORT_EDCR_EDHC_SHIFT)) & PORT_EDCR_EDHC_MASK)

#define PORT_EDCR_EDLC_MASK                      (0x2U)
#define PORT_EDCR_EDLC_SHIFT                     (1U)
/*! EDLC - EFT Detect Low Clear
 *  0b0..Do not clear low EFT detectors
 *  0b1..Clear all low EFT detectors whose corresponding high EFT detectors are not asserted.
 */
#define PORT_EDCR_EDLC(x)                        (((uint32_t)(((uint32_t)(x)) << PORT_EDCR_EDLC_SHIFT)) & PORT_EDCR_EDLC_MASK)
/*! @} */

/*! @name PCR - Pin Control Register 0..Pin Control Register 6 */
/*! @{ */

#define PORT_PCR_PS_MASK                         (0x1U)
#define PORT_PCR_PS_SHIFT                        (0U)
/*! PS - Pull Select
 *  0b0..Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
 *  0b1..Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
 */
#define PORT_PCR_PS(x)                           (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)

#define PORT_PCR_PE_MASK                         (0x2U)
#define PORT_PCR_PE_SHIFT                        (1U)
/*! PE - Pull Enable
 *  0b0..Internal pull resistor is not enabled on the corresponding pin.
 *  0b1..Internal pull resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
 */
#define PORT_PCR_PE(x)                           (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)

#define PORT_PCR_PV_MASK                         (0x4U)
#define PORT_PCR_PV_SHIFT                        (2U)
/*! PV - Pull Value
 *  0b0..Low internal pull resistor value is selected.
 *  0b1..High internal pull resistor value is selected.
 */
#define PORT_PCR_PV(x)                           (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PV_SHIFT)) & PORT_PCR_PV_MASK)

#define PORT_PCR_SRE_MASK                        (0x8U)
#define PORT_PCR_SRE_SHIFT                       (3U)
/*! SRE - Slew Rate Enable
 *  0b0..Fast slew rate is configured on the corresponding pin.
 *  0b1..Slow slew rate is configured on the corresponding pin.
 */
#define PORT_PCR_SRE(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)

#define PORT_PCR_PFE_MASK                        (0x10U)
#define PORT_PCR_PFE_SHIFT                       (4U)
/*! PFE - Passive Filter Enable
 *  0b0..Passive input filter is disabled on the corresponding pin.
 *  0b1..Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input.
 *       Refer to the device data sheet for filter characteristics.
 */
#define PORT_PCR_PFE(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)

#define PORT_PCR_ODE_MASK                        (0x20U)
#define PORT_PCR_ODE_SHIFT                       (5U)
/*! ODE - Open Drain Enable
 *  0b0..Open drain output is disabled on the corresponding pin.
 *  0b1..Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
 */
#define PORT_PCR_ODE(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK)

#define PORT_PCR_DSE_MASK                        (0x40U)
#define PORT_PCR_DSE_SHIFT                       (6U)
/*! DSE - Drive Strength Enable
 *  0b0..Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
 *  0b1..High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
 */
#define PORT_PCR_DSE(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)

#define PORT_PCR_DSE1_MASK                       (0x80U)
#define PORT_PCR_DSE1_SHIFT                      (7U)
/*! DSE1 - Drive Strength Enable
 *  0b0..Normal drive strength is configured on the corresponding pin.
 *  0b1..Double drive strength is configured on the corresponding pin.
 */
#define PORT_PCR_DSE1(x)                         (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE1_SHIFT)) & PORT_PCR_DSE1_MASK)

#define PORT_PCR_MUX_MASK                        (0xF00U)
#define PORT_PCR_MUX_SHIFT                       (8U)
/*! MUX - Pin Multiplex Control
 *  0b0000..Pin disabled (analog).
 *  0b0001..Alternative 1 (GPIO).
 *  0b0010..Alternative 2 (chip-specific).
 *  0b0011..Alternative 3 (chip-specific).
 *  0b0100..Alternative 4 (chip-specific).
 *  0b0101..Alternative 5 (chip-specific).
 *  0b0110..Alternative 6 (chip-specific).
 *  0b0111..Alternative 7 (chip-specific).
 *  0b1000..Alternative 8 (chip-specific).
 *  0b1001..Alternative 9 (chip-specific).
 *  0b1010..Alternative 10 (chip-specific).
 *  0b1011..Alternative 11 (chip-specific).
 */
#define PORT_PCR_MUX(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)

#define PORT_PCR_LK_MASK                         (0x8000U)
#define PORT_PCR_LK_SHIFT                        (15U)
/*! LK - Lock Register
 *  0b0..This PCR register is not locked.
 *  0b1..This PCR register is locked and cannot be updated until the next reset.
 */
#define PORT_PCR_LK(x)                           (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK)
/*! @} */

/* The count of PORT_PCR */
#define PORT_PCR_COUNT                           (23U)


/*!
 * @}
 */ /* end of group PORT_Register_Masks */


/* PORT - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral PORTA base address */
  #define PORTA_BASE                               (0x50042000u)
  /** Peripheral PORTA base address */
  #define PORTA_BASE_NS                            (0x40042000u)
  /** Peripheral PORTA base pointer */
  #define PORTA                                    ((PORT_Type *)PORTA_BASE)
  /** Peripheral PORTA base pointer */
  #define PORTA_NS                                 ((PORT_Type *)PORTA_BASE_NS)
  /** Peripheral PORTB base address */
  #define PORTB_BASE                               (0x50043000u)
  /** Peripheral PORTB base address */
  #define PORTB_BASE_NS                            (0x40043000u)
  /** Peripheral PORTB base pointer */
  #define PORTB                                    ((PORT_Type *)PORTB_BASE)
  /** Peripheral PORTB base pointer */
  #define PORTB_NS                                 ((PORT_Type *)PORTB_BASE_NS)
  /** Peripheral PORTC base address */
  #define PORTC_BASE                               (0x50044000u)
  /** Peripheral PORTC base address */
  #define PORTC_BASE_NS                            (0x40044000u)
  /** Peripheral PORTC base pointer */
  #define PORTC                                    ((PORT_Type *)PORTC_BASE)
  /** Peripheral PORTC base pointer */
  #define PORTC_NS                                 ((PORT_Type *)PORTC_BASE_NS)
  /** Peripheral PORTD base address */
  #define PORTD_BASE                               (0x50045000u)
  /** Peripheral PORTD base address */
  #define PORTD_BASE_NS                            (0x40045000u)
  /** Peripheral PORTD base pointer */
  #define PORTD                                    ((PORT_Type *)PORTD_BASE)
  /** Peripheral PORTD base pointer */
  #define PORTD_NS                                 ((PORT_Type *)PORTD_BASE_NS)
  /** Array initializer of PORT peripheral base addresses */
  #define PORT_BASE_ADDRS                          { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE }
  /** Array initializer of PORT peripheral base pointers */
  #define PORT_BASE_PTRS                           { PORTA, PORTB, PORTC, PORTD }
  /** Array initializer of PORT peripheral base addresses */
  #define PORT_BASE_ADDRS_NS                       { PORTA_BASE_NS, PORTB_BASE_NS, PORTC_BASE_NS, PORTD_BASE_NS }
  /** Array initializer of PORT peripheral base pointers */
  #define PORT_BASE_PTRS_NS                        { PORTA_NS, PORTB_NS, PORTC_NS, PORTD_NS }
#else
  /** Peripheral PORTA base address */
  #define PORTA_BASE                               (0x40042000u)
  /** Peripheral PORTA base pointer */
  #define PORTA                                    ((PORT_Type *)PORTA_BASE)
  /** Peripheral PORTB base address */
  #define PORTB_BASE                               (0x40043000u)
  /** Peripheral PORTB base pointer */
  #define PORTB                                    ((PORT_Type *)PORTB_BASE)
  /** Peripheral PORTC base address */
  #define PORTC_BASE                               (0x40044000u)
  /** Peripheral PORTC base pointer */
  #define PORTC                                    ((PORT_Type *)PORTC_BASE)
  /** Peripheral PORTD base address */
  #define PORTD_BASE                               (0x40045000u)
  /** Peripheral PORTD base pointer */
  #define PORTD                                    ((PORT_Type *)PORTD_BASE)
  /** Array initializer of PORT peripheral base addresses */
  #define PORT_BASE_ADDRS                          { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE }
  /** Array initializer of PORT peripheral base pointers */
  #define PORT_BASE_PTRS                           { PORTA, PORTB, PORTC, PORTD }
#endif
/** Interrupt vectors for the PORT peripheral type */
#define PORT_IRQS                                { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn }

/*!
 * @}
 */ /* end of group PORT_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- RADIO_CTRL Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup RADIO_CTRL_Peripheral_Access_Layer RADIO_CTRL Peripheral Access Layer
 * @{
 */

/** RADIO_CTRL - Register Layout Typedef */
typedef struct {
  __I  uint32_t LL_STATUS;                         /**< LL Status Register, offset: 0x0 */
  __IO uint32_t LL_CTRL;                           /**< LL Control Register, offset: 0x4 */
  __IO uint32_t RF_CTRL;                           /**< Radio Control Register, offset: 0x8 */
  __IO uint32_t RF_CLK_CTRL;                       /**< Radio Clock Control Register, offset: 0xC */
  __IO uint32_t COEX_CTRL;                         /**< COEXISTENCE CONTROL, offset: 0x10 */
  __I  uint32_t UID_MSB;                           /**< Radio Control Register, offset: 0x14 */
  __I  uint32_t UID_LSB;                           /**< Radio Control Register, offset: 0x18 */
  __IO uint32_t PACKET_RAM_CTRL;                   /**< PACKET RAM Control Register, offset: 0x1C */
  __IO uint32_t BLE_PHY_CTRL;                      /**< BLE PHY Interface Control Register, offset: 0x20 */
  __IO uint32_t DTEST_CTRL;                        /**< DTEST Control register, offset: 0x24 */
       uint8_t RESERVED_0[8];
  __IO uint32_t DTEST_PIN_CTRL2;                   /**< DTEST PIN Control 2 register, offset: 0x30 */
       uint8_t RESERVED_1[4];
  __IO uint32_t FPGA_CTRL;                         /**< FPGA Control register, offset: 0x38 */
} RADIO_CTRL_Type;

/* ----------------------------------------------------------------------------
   -- RADIO_CTRL Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup RADIO_CTRL_Register_Masks RADIO_CTRL Register Masks
 * @{
 */

/*! @name LL_STATUS - LL Status Register */
/*! @{ */

#define RADIO_CTRL_LL_STATUS_LL_PRESENT_MASK     (0x3FU)
#define RADIO_CTRL_LL_STATUS_LL_PRESENT_SHIFT    (0U)
/*! LL_PRESENT - LL present status
 */
#define RADIO_CTRL_LL_STATUS_LL_PRESENT(x)       (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_LL_STATUS_LL_PRESENT_SHIFT)) & RADIO_CTRL_LL_STATUS_LL_PRESENT_MASK)

#define RADIO_CTRL_LL_STATUS_BLE_VERSION_MASK    (0xF00U)
#define RADIO_CTRL_LL_STATUS_BLE_VERSION_SHIFT   (8U)
/*! BLE_VERSION - Bluetooth LE Version
 *  0b0000..No Bluetooth LE
 *  0b0001..Bluetooth LE 5.1
 *  0b0010..Bluetooth LE 5.2
 *  0b0011..Bluetooth LE 5.3
 *  0b0100-0b1110..Reserved
 *  0b1111..Bluetooth LE Upgrade
 */
#define RADIO_CTRL_LL_STATUS_BLE_VERSION(x)      (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_LL_STATUS_BLE_VERSION_SHIFT)) & RADIO_CTRL_LL_STATUS_BLE_VERSION_MASK)
/*! @} */

/*! @name LL_CTRL - LL Control Register */
/*! @{ */

#define RADIO_CTRL_LL_CTRL_ACTIVE_LL_MASK        (0x3U)
#define RADIO_CTRL_LL_CTRL_ACTIVE_LL_SHIFT       (0U)
/*! ACTIVE_LL - link layer control register
 *  0b00..Bluetooth LE LL is selected
 *  0b10..GENERIC LL is selected
 *  0b11..Disabled (default)
 */
#define RADIO_CTRL_LL_CTRL_ACTIVE_LL(x)          (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_LL_CTRL_ACTIVE_LL_SHIFT)) & RADIO_CTRL_LL_CTRL_ACTIVE_LL_MASK)
/*! @} */

/*! @name RF_CTRL - Radio Control Register */
/*! @{ */

#define RADIO_CTRL_RF_CTRL_RBME_MODE_OVRD_EN_MASK (0x1U)
#define RADIO_CTRL_RF_CTRL_RBME_MODE_OVRD_EN_SHIFT (0U)
/*! RBME_MODE_OVRD_EN - RBME Mode Override Enable
 *  0b0..RBME Mode Override Disable
 *  0b1..RBME Mode Override Enable
 */
#define RADIO_CTRL_RF_CTRL_RBME_MODE_OVRD_EN(x)  (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_RF_CTRL_RBME_MODE_OVRD_EN_SHIFT)) & RADIO_CTRL_RF_CTRL_RBME_MODE_OVRD_EN_MASK)

#define RADIO_CTRL_RF_CTRL_RBME_MODE_OVRD_MASK   (0xEU)
#define RADIO_CTRL_RF_CTRL_RBME_MODE_OVRD_SHIFT  (1U)
/*! RBME_MODE_OVRD - RBME Mode Override
 */
#define RADIO_CTRL_RF_CTRL_RBME_MODE_OVRD(x)     (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_RF_CTRL_RBME_MODE_OVRD_SHIFT)) & RADIO_CTRL_RF_CTRL_RBME_MODE_OVRD_MASK)

#define RADIO_CTRL_RF_CTRL_RX_CON_EN_OVRD_EN_MASK (0x10U)
#define RADIO_CTRL_RF_CTRL_RX_CON_EN_OVRD_EN_SHIFT (4U)
/*! RX_CON_EN_OVRD_EN - rx_con_en Override Enable
 *  0b0..rx_con_en Override Disable
 *  0b1..rx_con_en Override Enable
 */
#define RADIO_CTRL_RF_CTRL_RX_CON_EN_OVRD_EN(x)  (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_RF_CTRL_RX_CON_EN_OVRD_EN_SHIFT)) & RADIO_CTRL_RF_CTRL_RX_CON_EN_OVRD_EN_MASK)

#define RADIO_CTRL_RF_CTRL_RX_CON_EN_OVRD_MASK   (0x20U)
#define RADIO_CTRL_RF_CTRL_RX_CON_EN_OVRD_SHIFT  (5U)
/*! RX_CON_EN_OVRD - rx_con_en Override
 */
#define RADIO_CTRL_RF_CTRL_RX_CON_EN_OVRD(x)     (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_RF_CTRL_RX_CON_EN_OVRD_SHIFT)) & RADIO_CTRL_RF_CTRL_RX_CON_EN_OVRD_MASK)

#define RADIO_CTRL_RF_CTRL_BLE_LR_EN_OVRD_EN_MASK (0x40U)
#define RADIO_CTRL_RF_CTRL_BLE_LR_EN_OVRD_EN_SHIFT (6U)
/*! BLE_LR_EN_OVRD_EN - ble_lr_en Override Enable
 *  0b0..ble_lr_en Override Disable
 *  0b1..ble_lr_en Override Enable
 */
#define RADIO_CTRL_RF_CTRL_BLE_LR_EN_OVRD_EN(x)  (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_RF_CTRL_BLE_LR_EN_OVRD_EN_SHIFT)) & RADIO_CTRL_RF_CTRL_BLE_LR_EN_OVRD_EN_MASK)

#define RADIO_CTRL_RF_CTRL_BLE_LR_EN_OVRD_MASK   (0x80U)
#define RADIO_CTRL_RF_CTRL_BLE_LR_EN_OVRD_SHIFT  (7U)
/*! BLE_LR_EN_OVRD - ble_lr_en Override
 */
#define RADIO_CTRL_RF_CTRL_BLE_LR_EN_OVRD(x)     (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_RF_CTRL_BLE_LR_EN_OVRD_SHIFT)) & RADIO_CTRL_RF_CTRL_BLE_LR_EN_OVRD_MASK)

#define RADIO_CTRL_RF_CTRL_RIF_SEL_2MBPS_OVRD_EN_MASK (0x100U)
#define RADIO_CTRL_RF_CTRL_RIF_SEL_2MBPS_OVRD_EN_SHIFT (8U)
/*! RIF_SEL_2MBPS_OVRD_EN - rif_sel_2mbps Override Enable
 *  0b0..rif_sel_2mbps Override Disable
 *  0b1..rif_sel_2mbps Override Enable
 */
#define RADIO_CTRL_RF_CTRL_RIF_SEL_2MBPS_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_RF_CTRL_RIF_SEL_2MBPS_OVRD_EN_SHIFT)) & RADIO_CTRL_RF_CTRL_RIF_SEL_2MBPS_OVRD_EN_MASK)

#define RADIO_CTRL_RF_CTRL_RIF_SEL_2MBPS_OVRD_MASK (0x200U)
#define RADIO_CTRL_RF_CTRL_RIF_SEL_2MBPS_OVRD_SHIFT (9U)
/*! RIF_SEL_2MBPS_OVRD - rif_sel_2mbps Override
 */
#define RADIO_CTRL_RF_CTRL_RIF_SEL_2MBPS_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_RF_CTRL_RIF_SEL_2MBPS_OVRD_SHIFT)) & RADIO_CTRL_RF_CTRL_RIF_SEL_2MBPS_OVRD_MASK)

#define RADIO_CTRL_RF_CTRL_WOR_RX_FAIL_WAKEUP_EN_MASK (0x10000000U)
#define RADIO_CTRL_RF_CTRL_WOR_RX_FAIL_WAKEUP_EN_SHIFT (28U)
/*! WOR_RX_FAIL_WAKEUP_EN - WOR RX Fail Wakeup Enable
 *  0b0..The wor_rx_fail interrupt doesn't assert rfmc_wakeup.
 *  0b1..The wor_rx_fail interrupt asserts rfmc_wakeup.
 */
#define RADIO_CTRL_RF_CTRL_WOR_RX_FAIL_WAKEUP_EN(x) (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_RF_CTRL_WOR_RX_FAIL_WAKEUP_EN_SHIFT)) & RADIO_CTRL_RF_CTRL_WOR_RX_FAIL_WAKEUP_EN_MASK)

#define RADIO_CTRL_RF_CTRL_BRIC_WAKEUP_EN_MASK   (0x20000000U)
#define RADIO_CTRL_RF_CTRL_BRIC_WAKEUP_EN_SHIFT  (29U)
/*! BRIC_WAKEUP_EN - BRIC Wakeup Enable
 *  0b0..The BRIC interrupt doesn't assert rfmc_wakeup.
 *  0b1..The BRIC interrupt asserts rfmc_wakeup.
 */
#define RADIO_CTRL_RF_CTRL_BRIC_WAKEUP_EN(x)     (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_RF_CTRL_BRIC_WAKEUP_EN_SHIFT)) & RADIO_CTRL_RF_CTRL_BRIC_WAKEUP_EN_MASK)

#define RADIO_CTRL_RF_CTRL_GENERIC_WAKEUP_EN_MASK (0x40000000U)
#define RADIO_CTRL_RF_CTRL_GENERIC_WAKEUP_EN_SHIFT (30U)
/*! GENERIC_WAKEUP_EN - Generic LL Wakeup Enable
 *  0b0..The Generic LL interrupt doesn't assert rfmc_wakeup.
 *  0b1..The Genecir LL interrupt asserts rfmc_wakeup.
 */
#define RADIO_CTRL_RF_CTRL_GENERIC_WAKEUP_EN(x)  (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_RF_CTRL_GENERIC_WAKEUP_EN_SHIFT)) & RADIO_CTRL_RF_CTRL_GENERIC_WAKEUP_EN_MASK)

#define RADIO_CTRL_RF_CTRL_ZIGBEE_WAKEUP_EN_MASK (0x80000000U)
#define RADIO_CTRL_RF_CTRL_ZIGBEE_WAKEUP_EN_SHIFT (31U)
/*! ZIGBEE_WAKEUP_EN - Zigbee LL Wakeup Enable
 *  0b0..The Zigbee LL interrupt doesn't assert rfmc_wakeup.
 *  0b1..The Zigbee LL interrupt asserts rfmc_wakeup.
 */
#define RADIO_CTRL_RF_CTRL_ZIGBEE_WAKEUP_EN(x)   (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_RF_CTRL_ZIGBEE_WAKEUP_EN_SHIFT)) & RADIO_CTRL_RF_CTRL_ZIGBEE_WAKEUP_EN_MASK)
/*! @} */

/*! @name RF_CLK_CTRL - Radio Clock Control Register */
/*! @{ */

#define RADIO_CTRL_RF_CLK_CTRL_ZBLL_CLK_EN_OVRD_MASK (0x1U)
#define RADIO_CTRL_RF_CLK_CTRL_ZBLL_CLK_EN_OVRD_SHIFT (0U)
/*! ZBLL_CLK_EN_OVRD - ZBLL Clock Enable Override
 *  0b0..ZBLL clock force on is disabled.
 *  0b1..ZBLL clock force on is enabled.
 */
#define RADIO_CTRL_RF_CLK_CTRL_ZBLL_CLK_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_RF_CLK_CTRL_ZBLL_CLK_EN_OVRD_SHIFT)) & RADIO_CTRL_RF_CLK_CTRL_ZBLL_CLK_EN_OVRD_MASK)

#define RADIO_CTRL_RF_CLK_CTRL_GENLL_CLK_EN_OVRD_MASK (0x2U)
#define RADIO_CTRL_RF_CLK_CTRL_GENLL_CLK_EN_OVRD_SHIFT (1U)
/*! GENLL_CLK_EN_OVRD - GENLL Clock Enable Override
 *  0b0..GENLL clock force on is disabled.
 *  0b1..GENLL clock force on is enabled.
 */
#define RADIO_CTRL_RF_CLK_CTRL_GENLL_CLK_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_RF_CLK_CTRL_GENLL_CLK_EN_OVRD_SHIFT)) & RADIO_CTRL_RF_CLK_CTRL_GENLL_CLK_EN_OVRD_MASK)

#define RADIO_CTRL_RF_CLK_CTRL_BTLL_CLK_EN_OVRD_MASK (0x4U)
#define RADIO_CTRL_RF_CLK_CTRL_BTLL_CLK_EN_OVRD_SHIFT (2U)
/*! BTLL_CLK_EN_OVRD - BTLL Clock Enable Override
 *  0b0..BTLL clock force on is disabled.
 *  0b1..BTLL clock force on is enabled.
 */
#define RADIO_CTRL_RF_CLK_CTRL_BTLL_CLK_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_RF_CLK_CTRL_BTLL_CLK_EN_OVRD_SHIFT)) & RADIO_CTRL_RF_CLK_CTRL_BTLL_CLK_EN_OVRD_MASK)

#define RADIO_CTRL_RF_CLK_CTRL_BTU_EBRAM_CLK_ON_OVRD_MASK (0x8U)
#define RADIO_CTRL_RF_CLK_CTRL_BTU_EBRAM_CLK_ON_OVRD_SHIFT (3U)
/*! BTU_EBRAM_CLK_ON_OVRD - BTU EBRAM Clock Enable Override
 *  0b0..btu_ebram_clk is not forced on.
 *  0b1..btu_ebram_clk is forced on.
 */
#define RADIO_CTRL_RF_CLK_CTRL_BTU_EBRAM_CLK_ON_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_RF_CLK_CTRL_BTU_EBRAM_CLK_ON_OVRD_SHIFT)) & RADIO_CTRL_RF_CLK_CTRL_BTU_EBRAM_CLK_ON_OVRD_MASK)

#define RADIO_CTRL_RF_CLK_CTRL_BT_ECLK_DIV_MASK  (0x10U)
#define RADIO_CTRL_RF_CLK_CTRL_BT_ECLK_DIV_SHIFT (4U)
/*! BT_ECLK_DIV - BE_ECLK Divider
 *  0b0..ref_clk is not divided as bt_eclk.
 *  0b1..ref_clk is divided by 2 as bt_eclk.
 */
#define RADIO_CTRL_RF_CLK_CTRL_BT_ECLK_DIV(x)    (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_RF_CLK_CTRL_BT_ECLK_DIV_SHIFT)) & RADIO_CTRL_RF_CLK_CTRL_BT_ECLK_DIV_MASK)

#define RADIO_CTRL_RF_CLK_CTRL_NBU_HCLK_EN_MASK  (0x100U)
#define RADIO_CTRL_RF_CLK_CTRL_NBU_HCLK_EN_SHIFT (8U)
/*! NBU_HCLK_EN - NBU HCLK Enable
 *  0b0..nbu hclk/cpu_hclk are disabled.
 *  0b1..nbu hclk/cpu_hclk are enabled.
 */
#define RADIO_CTRL_RF_CLK_CTRL_NBU_HCLK_EN(x)    (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_RF_CLK_CTRL_NBU_HCLK_EN_SHIFT)) & RADIO_CTRL_RF_CLK_CTRL_NBU_HCLK_EN_MASK)

#define RADIO_CTRL_RF_CLK_CTRL_CM3_HCLK_EN_MASK  (0x200U)
#define RADIO_CTRL_RF_CLK_CTRL_CM3_HCLK_EN_SHIFT (9U)
/*! CM3_HCLK_EN - CM3 HCLK Enable
 *  0b0..cm3_hclk is disabled.
 *  0b1..cm3_hclk is enabled.
 */
#define RADIO_CTRL_RF_CLK_CTRL_CM3_HCLK_EN(x)    (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_RF_CLK_CTRL_CM3_HCLK_EN_SHIFT)) & RADIO_CTRL_RF_CLK_CTRL_CM3_HCLK_EN_MASK)

#define RADIO_CTRL_RF_CLK_CTRL_BLE_AHB_CLK_EN_MASK (0x400U)
#define RADIO_CTRL_RF_CLK_CTRL_BLE_AHB_CLK_EN_SHIFT (10U)
/*! BLE_AHB_CLK_EN - BLE_AHB CLOCK Enable
 *  0b0..ble_ahb_clk is disabled.
 *  0b1..ble_ahb_clk is enabled.
 */
#define RADIO_CTRL_RF_CLK_CTRL_BLE_AHB_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_RF_CLK_CTRL_BLE_AHB_CLK_EN_SHIFT)) & RADIO_CTRL_RF_CLK_CTRL_BLE_AHB_CLK_EN_MASK)

#define RADIO_CTRL_RF_CLK_CTRL_NBU_PKB_CLK_EN_MASK (0x800U)
#define RADIO_CTRL_RF_CLK_CTRL_NBU_PKB_CLK_EN_SHIFT (11U)
/*! NBU_PKB_CLK_EN - NBU PKB Clock Enable
 *  0b0..nbu_pkb_clk is disabled.
 *  0b1..nbu_pkb_clk is enabled.
 */
#define RADIO_CTRL_RF_CLK_CTRL_NBU_PKB_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_RF_CLK_CTRL_NBU_PKB_CLK_EN_SHIFT)) & RADIO_CTRL_RF_CLK_CTRL_NBU_PKB_CLK_EN_MASK)

#define RADIO_CTRL_RF_CLK_CTRL_BT_16M_CLK_EN_MASK (0x1000U)
#define RADIO_CTRL_RF_CLK_CTRL_BT_16M_CLK_EN_SHIFT (12U)
/*! BT_16M_CLK_EN - BT 16M Clock Enable
 *  0b0..bt_16m_clk is disabled.
 *  0b1..bt_16m_clk is enabled.
 */
#define RADIO_CTRL_RF_CLK_CTRL_BT_16M_CLK_EN(x)  (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_RF_CLK_CTRL_BT_16M_CLK_EN_SHIFT)) & RADIO_CTRL_RF_CLK_CTRL_BT_16M_CLK_EN_MASK)

#define RADIO_CTRL_RF_CLK_CTRL_RTU_CLK_EN_MASK   (0x2000U)
#define RADIO_CTRL_RF_CLK_CTRL_RTU_CLK_EN_SHIFT  (13U)
/*! RTU_CLK_EN - RTU Clock Enable
 *  0b0..rtu_clk is disabled.
 *  0b1..rtu_clk is enabled.
 */
#define RADIO_CTRL_RF_CLK_CTRL_RTU_CLK_EN(x)     (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_RF_CLK_CTRL_RTU_CLK_EN_SHIFT)) & RADIO_CTRL_RF_CLK_CTRL_RTU_CLK_EN_MASK)

#define RADIO_CTRL_RF_CLK_CTRL_BT_4M_CLK_EN_MASK (0x4000U)
#define RADIO_CTRL_RF_CLK_CTRL_BT_4M_CLK_EN_SHIFT (14U)
/*! BT_4M_CLK_EN - BT 4M Clock Enable
 *  0b0..bt_4m_clk is disabled.
 *  0b1..bt_4m_clk is enabled.
 */
#define RADIO_CTRL_RF_CLK_CTRL_BT_4M_CLK_EN(x)   (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_RF_CLK_CTRL_BT_4M_CLK_EN_SHIFT)) & RADIO_CTRL_RF_CLK_CTRL_BT_4M_CLK_EN_MASK)

#define RADIO_CTRL_RF_CLK_CTRL_BT_REF_4M_CLK_EN_MASK (0x8000U)
#define RADIO_CTRL_RF_CLK_CTRL_BT_REF_4M_CLK_EN_SHIFT (15U)
/*! BT_REF_4M_CLK_EN - BT REF 4M Clock Enable
 *  0b0..bt_ref_4m_clk is disabled.
 *  0b1..bt_ref_4m_clk is enabled.
 */
#define RADIO_CTRL_RF_CLK_CTRL_BT_REF_4M_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_RF_CLK_CTRL_BT_REF_4M_CLK_EN_SHIFT)) & RADIO_CTRL_RF_CLK_CTRL_BT_REF_4M_CLK_EN_MASK)

#define RADIO_CTRL_RF_CLK_CTRL_BT_XCVR_4M_CLK_EN_MASK (0x10000U)
#define RADIO_CTRL_RF_CLK_CTRL_BT_XCVR_4M_CLK_EN_SHIFT (16U)
/*! BT_XCVR_4M_CLK_EN - BT XCVR 4M Clock Enable
 *  0b0..bt_xcvr_4m_clk is disabled.
 *  0b1..bt_xcvr_4m_clk is enabled.
 */
#define RADIO_CTRL_RF_CLK_CTRL_BT_XCVR_4M_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_RF_CLK_CTRL_BT_XCVR_4M_CLK_EN_SHIFT)) & RADIO_CTRL_RF_CLK_CTRL_BT_XCVR_4M_CLK_EN_MASK)

#define RADIO_CTRL_RF_CLK_CTRL_BT_XCVR_32M_CLK_EN_MASK (0x20000U)
#define RADIO_CTRL_RF_CLK_CTRL_BT_XCVR_32M_CLK_EN_SHIFT (17U)
/*! BT_XCVR_32M_CLK_EN - BT XCVR 32M Clock Enable
 *  0b0..bt_xcvr_32m_clk is disabled.
 *  0b1..bt_xcvr_32m_clk is enabled.
 */
#define RADIO_CTRL_RF_CLK_CTRL_BT_XCVR_32M_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_RF_CLK_CTRL_BT_XCVR_32M_CLK_EN_SHIFT)) & RADIO_CTRL_RF_CLK_CTRL_BT_XCVR_32M_CLK_EN_MASK)

#define RADIO_CTRL_RF_CLK_CTRL_BT_ECLK_EN_MASK   (0x40000U)
#define RADIO_CTRL_RF_CLK_CTRL_BT_ECLK_EN_SHIFT  (18U)
/*! BT_ECLK_EN - BT_ECLK Enable
 *  0b0..bt_eclk is disabled.
 *  0b1..bt_eclk is enabled.
 */
#define RADIO_CTRL_RF_CLK_CTRL_BT_ECLK_EN(x)     (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_RF_CLK_CTRL_BT_ECLK_EN_SHIFT)) & RADIO_CTRL_RF_CLK_CTRL_BT_ECLK_EN_MASK)

#define RADIO_CTRL_RF_CLK_CTRL_BLE_AES_CLK_EN_MASK (0x80000U)
#define RADIO_CTRL_RF_CLK_CTRL_BLE_AES_CLK_EN_SHIFT (19U)
/*! BLE_AES_CLK_EN - BLE_AES_CLK Enable
 *  0b0..bt_aes_clk is disabled.
 *  0b1..bt_aes_clk is enabled.
 */
#define RADIO_CTRL_RF_CLK_CTRL_BLE_AES_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_RF_CLK_CTRL_BLE_AES_CLK_EN_SHIFT)) & RADIO_CTRL_RF_CLK_CTRL_BLE_AES_CLK_EN_MASK)

#define RADIO_CTRL_RF_CLK_CTRL_UART_CLK_EN_MASK  (0x100000U)
#define RADIO_CTRL_RF_CLK_CTRL_UART_CLK_EN_SHIFT (20U)
/*! UART_CLK_EN - UART Clock Enable
 *  0b0..uart_clk is disabled.
 *  0b1..uart_clk is enabled.
 */
#define RADIO_CTRL_RF_CLK_CTRL_UART_CLK_EN(x)    (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_RF_CLK_CTRL_UART_CLK_EN_SHIFT)) & RADIO_CTRL_RF_CLK_CTRL_UART_CLK_EN_MASK)

#define RADIO_CTRL_RF_CLK_CTRL_MAN_DS_EN_MASK    (0x20000000U)
#define RADIO_CTRL_RF_CLK_CTRL_MAN_DS_EN_SHIFT   (29U)
/*! MAN_DS_EN - Manual deep sleep control enable
 *  0b0..Disable the control of rfmc_man_deep_sleep_enable for nbu_hclk.
 *  0b1..Enable the control of rfmc_man_deep_sleep_enable for nbu_hclk.
 */
#define RADIO_CTRL_RF_CLK_CTRL_MAN_DS_EN(x)      (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_RF_CLK_CTRL_MAN_DS_EN_SHIFT)) & RADIO_CTRL_RF_CLK_CTRL_MAN_DS_EN_MASK)

#define RADIO_CTRL_RF_CLK_CTRL_WOR_DS_EN_MASK    (0x40000000U)
#define RADIO_CTRL_RF_CLK_CTRL_WOR_DS_EN_SHIFT   (30U)
/*! WOR_DS_EN - WOR deep sleep control enable
 *  0b0..Disable the control of rfmc_wor_deep_sleep_enable for nbu_hclk.
 *  0b1..Enable the control of rfmc_wor_deep_sleep_enable for nbu_hclk.
 */
#define RADIO_CTRL_RF_CLK_CTRL_WOR_DS_EN(x)      (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_RF_CLK_CTRL_WOR_DS_EN_SHIFT)) & RADIO_CTRL_RF_CLK_CTRL_WOR_DS_EN_MASK)

#define RADIO_CTRL_RF_CLK_CTRL_BT_CLK_REQ_EN_MASK (0x80000000U)
#define RADIO_CTRL_RF_CLK_CTRL_BT_CLK_REQ_EN_SHIFT (31U)
/*! BT_CLK_REQ_EN - BT_CLK_REQ control enable
 *  0b0..Disable the control of bt_clk_req for nbu_hclk.
 *  0b1..Enable the control of bt_clk_req for nbu_hclk.
 */
#define RADIO_CTRL_RF_CLK_CTRL_BT_CLK_REQ_EN(x)  (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_RF_CLK_CTRL_BT_CLK_REQ_EN_SHIFT)) & RADIO_CTRL_RF_CLK_CTRL_BT_CLK_REQ_EN_MASK)
/*! @} */

/*! @name COEX_CTRL - COEXISTENCE CONTROL */
/*! @{ */

#define RADIO_CTRL_COEX_CTRL_RF_NOT_ALLOWED_EN_MASK (0xFU)
#define RADIO_CTRL_COEX_CTRL_RF_NOT_ALLOWED_EN_SHIFT (0U)
/*! RF_NOT_ALLOWED_EN - RF_NOT_ALLOWED PER-LINK-LAYER ENABLE
 */
#define RADIO_CTRL_COEX_CTRL_RF_NOT_ALLOWED_EN(x) (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_COEX_CTRL_RF_NOT_ALLOWED_EN_SHIFT)) & RADIO_CTRL_COEX_CTRL_RF_NOT_ALLOWED_EN_MASK)

#define RADIO_CTRL_COEX_CTRL_RF_NOT_ALLOWED_ASSERTED_MASK (0x10U)
#define RADIO_CTRL_COEX_CTRL_RF_NOT_ALLOWED_ASSERTED_SHIFT (4U)
/*! RF_NOT_ALLOWED_ASSERTED - RF_NOT_ALLOWED_ASSERTED
 *  0b0..Assertion on RF_NOT_ALLOWED has not occurred
 *  0b1..Assertion on RF_NOT_ALLOWED has occurred since the last time this bit was cleared
 */
#define RADIO_CTRL_COEX_CTRL_RF_NOT_ALLOWED_ASSERTED(x) (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_COEX_CTRL_RF_NOT_ALLOWED_ASSERTED_SHIFT)) & RADIO_CTRL_COEX_CTRL_RF_NOT_ALLOWED_ASSERTED_MASK)

#define RADIO_CTRL_COEX_CTRL_RF_NOT_ALLOWED_MASK (0x20U)
#define RADIO_CTRL_COEX_CTRL_RF_NOT_ALLOWED_SHIFT (5U)
/*! RF_NOT_ALLOWED - RF_NOT_ALLOWED
 */
#define RADIO_CTRL_COEX_CTRL_RF_NOT_ALLOWED(x)   (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_COEX_CTRL_RF_NOT_ALLOWED_SHIFT)) & RADIO_CTRL_COEX_CTRL_RF_NOT_ALLOWED_MASK)

#define RADIO_CTRL_COEX_CTRL_RF_NOT_ALLOWED_OVRD_MASK (0x40U)
#define RADIO_CTRL_COEX_CTRL_RF_NOT_ALLOWED_OVRD_SHIFT (6U)
/*! RF_NOT_ALLOWED_OVRD - RF_NOT_ALLOWED Override
 */
#define RADIO_CTRL_COEX_CTRL_RF_NOT_ALLOWED_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_COEX_CTRL_RF_NOT_ALLOWED_OVRD_SHIFT)) & RADIO_CTRL_COEX_CTRL_RF_NOT_ALLOWED_OVRD_MASK)

#define RADIO_CTRL_COEX_CTRL_RF_NOT_ALLOWED_OVRD_EN_MASK (0x80U)
#define RADIO_CTRL_COEX_CTRL_RF_NOT_ALLOWED_OVRD_EN_SHIFT (7U)
/*! RF_NOT_ALLOWED_OVRD_EN - RF_NOT_ALLOWED Override Enable
 *  0b0..RF_NALLOWED Override Disable
 *  0b1..RF_NALLOWED Override Enable
 */
#define RADIO_CTRL_COEX_CTRL_RF_NOT_ALLOWED_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_COEX_CTRL_RF_NOT_ALLOWED_OVRD_EN_SHIFT)) & RADIO_CTRL_COEX_CTRL_RF_NOT_ALLOWED_OVRD_EN_MASK)

#define RADIO_CTRL_COEX_CTRL_RF_NALLOWED_INV_MASK (0x100U)
#define RADIO_CTRL_COEX_CTRL_RF_NALLOWED_INV_SHIFT (8U)
/*! RF_NALLOWED_INV - RF_NALLOWED Invert
 *  0b0..rf_nallowed is not inverted.
 *  0b1..rf_nallowed is inverted.
 */
#define RADIO_CTRL_COEX_CTRL_RF_NALLOWED_INV(x)  (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_COEX_CTRL_RF_NALLOWED_INV_SHIFT)) & RADIO_CTRL_COEX_CTRL_RF_NALLOWED_INV_MASK)

#define RADIO_CTRL_COEX_CTRL_RF_ACTIVE_INV_MASK  (0x200U)
#define RADIO_CTRL_COEX_CTRL_RF_ACTIVE_INV_SHIFT (9U)
/*! RF_ACTIVE_INV - RF_ACTIVE Invert
 *  0b0..rf_active is not inverted.
 *  0b1..rf_active is inverted.
 */
#define RADIO_CTRL_COEX_CTRL_RF_ACTIVE_INV(x)    (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_COEX_CTRL_RF_ACTIVE_INV_SHIFT)) & RADIO_CTRL_COEX_CTRL_RF_ACTIVE_INV_MASK)

#define RADIO_CTRL_COEX_CTRL_RF_PRIORITY_INV_MASK (0xC00U)
#define RADIO_CTRL_COEX_CTRL_RF_PRIORITY_INV_SHIFT (10U)
/*! RF_PRIORITY_INV - RF_PRIORITY Invert
 *  0bx0..rf_priority[0] is not inverted.
 *  0bx1..rf_priority[0] is inverted.
 *  0b0x..rf_priority[1] is not inverted.
 *  0b1x..rf_priority[1] is inverted.
 */
#define RADIO_CTRL_COEX_CTRL_RF_PRIORITY_INV(x)  (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_COEX_CTRL_RF_PRIORITY_INV_SHIFT)) & RADIO_CTRL_COEX_CTRL_RF_PRIORITY_INV_MASK)

#define RADIO_CTRL_COEX_CTRL_RF_STATUS_INV_MASK  (0x1000U)
#define RADIO_CTRL_COEX_CTRL_RF_STATUS_INV_SHIFT (12U)
/*! RF_STATUS_INV - RF_STATUS Invert
 *  0b0..rf_status is not inverted.
 *  0b1..rf_status is inverted.
 */
#define RADIO_CTRL_COEX_CTRL_RF_STATUS_INV(x)    (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_COEX_CTRL_RF_STATUS_INV_SHIFT)) & RADIO_CTRL_COEX_CTRL_RF_STATUS_INV_MASK)

#define RADIO_CTRL_COEX_CTRL_COEX_SEL_MASK       (0x2000U)
#define RADIO_CTRL_COEX_CTRL_COEX_SEL_SHIFT      (13U)
/*! COEX_SEL - COEX_SEL
 *  0b0..Select coexistence signals from LL.
 *  0b1..Select coexistence signals from TSM.
 */
#define RADIO_CTRL_COEX_CTRL_COEX_SEL(x)         (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_COEX_CTRL_COEX_SEL_SHIFT)) & RADIO_CTRL_COEX_CTRL_COEX_SEL_MASK)
/*! @} */

/*! @name UID_MSB - Radio Control Register */
/*! @{ */

#define RADIO_CTRL_UID_MSB_RADIO_UID_MSB_MASK    (0xFFU)
#define RADIO_CTRL_UID_MSB_RADIO_UID_MSB_SHIFT   (0U)
/*! RADIO_UID_MSB - The most signficant 8bits of the 40bit Radio UID.
 */
#define RADIO_CTRL_UID_MSB_RADIO_UID_MSB(x)      (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_UID_MSB_RADIO_UID_MSB_SHIFT)) & RADIO_CTRL_UID_MSB_RADIO_UID_MSB_MASK)
/*! @} */

/*! @name UID_LSB - Radio Control Register */
/*! @{ */

#define RADIO_CTRL_UID_LSB_RADIO_UID_LSB_MASK    (0xFFFFFFFFU)
#define RADIO_CTRL_UID_LSB_RADIO_UID_LSB_SHIFT   (0U)
/*! RADIO_UID_LSB - The least signficant 32bits of the 40bit Radio UID.
 */
#define RADIO_CTRL_UID_LSB_RADIO_UID_LSB(x)      (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_UID_LSB_RADIO_UID_LSB_SHIFT)) & RADIO_CTRL_UID_LSB_RADIO_UID_LSB_MASK)
/*! @} */

/*! @name PACKET_RAM_CTRL - PACKET RAM Control Register */
/*! @{ */

#define RADIO_CTRL_PACKET_RAM_CTRL_PB_PROTECT_MASK (0x1U)
#define RADIO_CTRL_PACKET_RAM_CTRL_PB_PROTECT_SHIFT (0U)
/*! PB_PROTECT - PB_PROTECT
 *  0b0..Incoming receive data can overwrite the existing contents of the RX section of the Packet Buffer.
 *  0b1..Incoming receive data is been blocked from overwriting the existing contents of the RX section of the Packet Buffer.
 */
#define RADIO_CTRL_PACKET_RAM_CTRL_PB_PROTECT(x) (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_PACKET_RAM_CTRL_PB_PROTECT_SHIFT)) & RADIO_CTRL_PACKET_RAM_CTRL_PB_PROTECT_MASK)
/*! @} */

/*! @name BLE_PHY_CTRL - BLE PHY Interface Control Register */
/*! @{ */

#define RADIO_CTRL_BLE_PHY_CTRL_CTE_AVG_SAMP_SEL_MASK (0x3U)
#define RADIO_CTRL_BLE_PHY_CTRL_CTE_AVG_SAMP_SEL_SHIFT (0U)
/*! CTE_AVG_SAMP_SEL - Sampling select
 */
#define RADIO_CTRL_BLE_PHY_CTRL_CTE_AVG_SAMP_SEL(x) (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_BLE_PHY_CTRL_CTE_AVG_SAMP_SEL_SHIFT)) & RADIO_CTRL_BLE_PHY_CTRL_CTE_AVG_SAMP_SEL_MASK)

#define RADIO_CTRL_BLE_PHY_CTRL_READ_START_OFFSET_1M_MASK (0xF0U)
#define RADIO_CTRL_BLE_PHY_CTRL_READ_START_OFFSET_1M_SHIFT (4U)
/*! READ_START_OFFSET_1M - Start sending Rx data to NBU after a programmable number of symbols are received from PHY - 1M
 */
#define RADIO_CTRL_BLE_PHY_CTRL_READ_START_OFFSET_1M(x) (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_BLE_PHY_CTRL_READ_START_OFFSET_1M_SHIFT)) & RADIO_CTRL_BLE_PHY_CTRL_READ_START_OFFSET_1M_MASK)

#define RADIO_CTRL_BLE_PHY_CTRL_READ_START_OFFSET_2M_MASK (0xF00U)
#define RADIO_CTRL_BLE_PHY_CTRL_READ_START_OFFSET_2M_SHIFT (8U)
/*! READ_START_OFFSET_2M - Start sending Rx data to NBU after a programmable number of symbols are received from PHY - 2M
 */
#define RADIO_CTRL_BLE_PHY_CTRL_READ_START_OFFSET_2M(x) (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_BLE_PHY_CTRL_READ_START_OFFSET_2M_SHIFT)) & RADIO_CTRL_BLE_PHY_CTRL_READ_START_OFFSET_2M_MASK)

#define RADIO_CTRL_BLE_PHY_CTRL_READ_START_OFFSET_LR_MASK (0xF000U)
#define RADIO_CTRL_BLE_PHY_CTRL_READ_START_OFFSET_LR_SHIFT (12U)
/*! READ_START_OFFSET_LR - Start sending Rx data to NBU after a programmable number of symbols are received from PHY - LR
 */
#define RADIO_CTRL_BLE_PHY_CTRL_READ_START_OFFSET_LR(x) (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_BLE_PHY_CTRL_READ_START_OFFSET_LR_SHIFT)) & RADIO_CTRL_BLE_PHY_CTRL_READ_START_OFFSET_LR_MASK)

#define RADIO_CTRL_BLE_PHY_CTRL_GUARD_TIME_1M_MASK (0xFF0000U)
#define RADIO_CTRL_BLE_PHY_CTRL_GUARD_TIME_1M_SHIFT (16U)
/*! GUARD_TIME_1M - Guard time offset for 1M
 */
#define RADIO_CTRL_BLE_PHY_CTRL_GUARD_TIME_1M(x) (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_BLE_PHY_CTRL_GUARD_TIME_1M_SHIFT)) & RADIO_CTRL_BLE_PHY_CTRL_GUARD_TIME_1M_MASK)

#define RADIO_CTRL_BLE_PHY_CTRL_GUARD_TIME_2M_MASK (0x3F000000U)
#define RADIO_CTRL_BLE_PHY_CTRL_GUARD_TIME_2M_SHIFT (24U)
/*! GUARD_TIME_2M - Guard time offset for 2M
 */
#define RADIO_CTRL_BLE_PHY_CTRL_GUARD_TIME_2M(x) (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_BLE_PHY_CTRL_GUARD_TIME_2M_SHIFT)) & RADIO_CTRL_BLE_PHY_CTRL_GUARD_TIME_2M_MASK)

#define RADIO_CTRL_BLE_PHY_CTRL_AVG_IQ_DISABLE_MASK (0x40000000U)
#define RADIO_CTRL_BLE_PHY_CTRL_AVG_IQ_DISABLE_SHIFT (30U)
/*! AVG_IQ_DISABLE - Disable IQ sample averaging
 */
#define RADIO_CTRL_BLE_PHY_CTRL_AVG_IQ_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_BLE_PHY_CTRL_AVG_IQ_DISABLE_SHIFT)) & RADIO_CTRL_BLE_PHY_CTRL_AVG_IQ_DISABLE_MASK)

#define RADIO_CTRL_BLE_PHY_CTRL_CTE_SINGLE_BUF_MASK (0x80000000U)
#define RADIO_CTRL_BLE_PHY_CTRL_CTE_SINGLE_BUF_SHIFT (31U)
/*! CTE_SINGLE_BUF - Config for using single buffer for Rx data and CTE samples
 */
#define RADIO_CTRL_BLE_PHY_CTRL_CTE_SINGLE_BUF(x) (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_BLE_PHY_CTRL_CTE_SINGLE_BUF_SHIFT)) & RADIO_CTRL_BLE_PHY_CTRL_CTE_SINGLE_BUF_MASK)
/*! @} */

/*! @name DTEST_CTRL - DTEST Control register */
/*! @{ */

#define RADIO_CTRL_DTEST_CTRL_DTEST_PAGE_MASK    (0x7FU)
#define RADIO_CTRL_DTEST_CTRL_DTEST_PAGE_SHIFT   (0U)
/*! DTEST_PAGE - DTEST PAGE Number
 */
#define RADIO_CTRL_DTEST_CTRL_DTEST_PAGE(x)      (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_DTEST_CTRL_DTEST_PAGE_SHIFT)) & RADIO_CTRL_DTEST_CTRL_DTEST_PAGE_MASK)

#define RADIO_CTRL_DTEST_CTRL_DTEST_EN_MASK      (0x80U)
#define RADIO_CTRL_DTEST_CTRL_DTEST_EN_SHIFT     (7U)
/*! DTEST_EN - DTEST_EN control
 *  0b0..disable dtest feature
 *  0b1..enable dtest feature
 */
#define RADIO_CTRL_DTEST_CTRL_DTEST_EN(x)        (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_DTEST_CTRL_DTEST_EN_SHIFT)) & RADIO_CTRL_DTEST_CTRL_DTEST_EN_MASK)

#define RADIO_CTRL_DTEST_CTRL_DTEST_OUT_REG_EN_MASK (0x100U)
#define RADIO_CTRL_DTEST_CTRL_DTEST_OUT_REG_EN_SHIFT (8U)
/*! DTEST_OUT_REG_EN - Enable/Disable register dtest signal
 *  0b0..output dtest signal directly
 *  0b1..output dtest signal after registered
 */
#define RADIO_CTRL_DTEST_CTRL_DTEST_OUT_REG_EN(x) (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_DTEST_CTRL_DTEST_OUT_REG_EN_SHIFT)) & RADIO_CTRL_DTEST_CTRL_DTEST_OUT_REG_EN_MASK)

#define RADIO_CTRL_DTEST_CTRL_RAW_MODE_I_MASK    (0x200U)
#define RADIO_CTRL_DTEST_CTRL_RAW_MODE_I_SHIFT   (9U)
/*! RAW_MODE_I - Select rx_dig_i as DTEST RX_IQ page
 */
#define RADIO_CTRL_DTEST_CTRL_RAW_MODE_I(x)      (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_DTEST_CTRL_RAW_MODE_I_SHIFT)) & RADIO_CTRL_DTEST_CTRL_RAW_MODE_I_MASK)

#define RADIO_CTRL_DTEST_CTRL_RAW_MODE_Q_MASK    (0x400U)
#define RADIO_CTRL_DTEST_CTRL_RAW_MODE_Q_SHIFT   (10U)
/*! RAW_MODE_Q - Select rx_dig_q as DTEST RX_IQ page
 */
#define RADIO_CTRL_DTEST_CTRL_RAW_MODE_Q(x)      (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_DTEST_CTRL_RAW_MODE_Q_SHIFT)) & RADIO_CTRL_DTEST_CTRL_RAW_MODE_Q_MASK)

#define RADIO_CTRL_DTEST_CTRL_DTEST_SHIFT_MASK   (0x3800U)
#define RADIO_CTRL_DTEST_CTRL_DTEST_SHIFT_SHIFT  (11U)
/*! DTEST_SHIFT - DTEST shift control
 */
#define RADIO_CTRL_DTEST_CTRL_DTEST_SHIFT(x)     (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_DTEST_CTRL_DTEST_SHIFT_SHIFT)) & RADIO_CTRL_DTEST_CTRL_DTEST_SHIFT_MASK)
/*! @} */

/*! @name DTEST_PIN_CTRL2 - DTEST PIN Control 2 register */
/*! @{ */

#define RADIO_CTRL_DTEST_PIN_CTRL2_DTEST_PIN8_MUX_SEL_MASK (0xFU)
#define RADIO_CTRL_DTEST_PIN_CTRL2_DTEST_PIN8_MUX_SEL_SHIFT (0U)
/*! DTEST_PIN8_MUX_SEL - DTEST_PIN8_MUX_SEL
 */
#define RADIO_CTRL_DTEST_PIN_CTRL2_DTEST_PIN8_MUX_SEL(x) (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_DTEST_PIN_CTRL2_DTEST_PIN8_MUX_SEL_SHIFT)) & RADIO_CTRL_DTEST_PIN_CTRL2_DTEST_PIN8_MUX_SEL_MASK)

#define RADIO_CTRL_DTEST_PIN_CTRL2_DTEST_PIN8_OVRD_SEL_MASK (0xF0U)
#define RADIO_CTRL_DTEST_PIN_CTRL2_DTEST_PIN8_OVRD_SEL_SHIFT (4U)
/*! DTEST_PIN8_OVRD_SEL - DTEST_PIN8_OVRD_SEL
 *  0b0000..override is disabled
 *  0b0001..aa_sfd_matched
 *  0b0010..rx_pd_fnd
 *  0b0011..agc_gain_change
 *  0b0100..tsm_combined_tx_en
 *  0b0101..tsm_combined_rx_en
 *  0b0110..crc_fail
 *  0b0111..decode_data_out
 *  0b1000..tx_data_out
 *  0b1001..nbu_testbus[14]
 *  0b1010..nbu_testbus[15]
 *  0b1011-0b1111..reserved
 */
#define RADIO_CTRL_DTEST_PIN_CTRL2_DTEST_PIN8_OVRD_SEL(x) (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_DTEST_PIN_CTRL2_DTEST_PIN8_OVRD_SEL_SHIFT)) & RADIO_CTRL_DTEST_PIN_CTRL2_DTEST_PIN8_OVRD_SEL_MASK)

#define RADIO_CTRL_DTEST_PIN_CTRL2_DTEST_PIN9_MUX_SEL_MASK (0xF00U)
#define RADIO_CTRL_DTEST_PIN_CTRL2_DTEST_PIN9_MUX_SEL_SHIFT (8U)
/*! DTEST_PIN9_MUX_SEL - DTEST_PIN9_MUX_SEL
 */
#define RADIO_CTRL_DTEST_PIN_CTRL2_DTEST_PIN9_MUX_SEL(x) (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_DTEST_PIN_CTRL2_DTEST_PIN9_MUX_SEL_SHIFT)) & RADIO_CTRL_DTEST_PIN_CTRL2_DTEST_PIN9_MUX_SEL_MASK)

#define RADIO_CTRL_DTEST_PIN_CTRL2_DTEST_PIN9_OVRD_SEL_MASK (0xF000U)
#define RADIO_CTRL_DTEST_PIN_CTRL2_DTEST_PIN9_OVRD_SEL_SHIFT (12U)
/*! DTEST_PIN9_OVRD_SEL - DTEST_PIN9_OVRD_SEL
 *  0b0000..override is disabled
 *  0b0001..aa_sfd_matched
 *  0b0010..rx_pd_fnd
 *  0b0011..agc_gain_change
 *  0b0100..tsm_combined_tx_en
 *  0b0101..tsm_combined_rx_en
 *  0b0110..crc_fail
 *  0b0111..decode_data_out
 *  0b1000..tx_data_out
 *  0b1001..nbu_testbus[14]
 *  0b1010..nbu_testbus[15]
 *  0b1011-0b1111..reserved
 */
#define RADIO_CTRL_DTEST_PIN_CTRL2_DTEST_PIN9_OVRD_SEL(x) (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_DTEST_PIN_CTRL2_DTEST_PIN9_OVRD_SEL_SHIFT)) & RADIO_CTRL_DTEST_PIN_CTRL2_DTEST_PIN9_OVRD_SEL_MASK)

#define RADIO_CTRL_DTEST_PIN_CTRL2_DTEST_PIN10_MUX_SEL_MASK (0xF0000U)
#define RADIO_CTRL_DTEST_PIN_CTRL2_DTEST_PIN10_MUX_SEL_SHIFT (16U)
/*! DTEST_PIN10_MUX_SEL - DTEST_PIN10_MUX_SEL
 */
#define RADIO_CTRL_DTEST_PIN_CTRL2_DTEST_PIN10_MUX_SEL(x) (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_DTEST_PIN_CTRL2_DTEST_PIN10_MUX_SEL_SHIFT)) & RADIO_CTRL_DTEST_PIN_CTRL2_DTEST_PIN10_MUX_SEL_MASK)

#define RADIO_CTRL_DTEST_PIN_CTRL2_DTEST_PIN10_OVRD_SEL_MASK (0xF00000U)
#define RADIO_CTRL_DTEST_PIN_CTRL2_DTEST_PIN10_OVRD_SEL_SHIFT (20U)
/*! DTEST_PIN10_OVRD_SEL - DTEST_PIN10_OVRD_SEL
 *  0b0000..override is disabled
 *  0b0001..aa_sfd_matched
 *  0b0010..rx_pd_fnd
 *  0b0011..agc_gain_change
 *  0b0100..tsm_combined_tx_en
 *  0b0101..tsm_combined_rx_en
 *  0b0110..crc_fail
 *  0b0111..decode_data_out
 *  0b1000..tx_data_out
 *  0b1001..nbu_testbus[14]
 *  0b1010..nbu_testbus[15]
 *  0b1011-0b1111..reserved
 */
#define RADIO_CTRL_DTEST_PIN_CTRL2_DTEST_PIN10_OVRD_SEL(x) (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_DTEST_PIN_CTRL2_DTEST_PIN10_OVRD_SEL_SHIFT)) & RADIO_CTRL_DTEST_PIN_CTRL2_DTEST_PIN10_OVRD_SEL_MASK)

#define RADIO_CTRL_DTEST_PIN_CTRL2_DTEST_PIN11_MUX_SEL_MASK (0xF000000U)
#define RADIO_CTRL_DTEST_PIN_CTRL2_DTEST_PIN11_MUX_SEL_SHIFT (24U)
/*! DTEST_PIN11_MUX_SEL - DTEST_PIN11_MUX_SEL
 */
#define RADIO_CTRL_DTEST_PIN_CTRL2_DTEST_PIN11_MUX_SEL(x) (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_DTEST_PIN_CTRL2_DTEST_PIN11_MUX_SEL_SHIFT)) & RADIO_CTRL_DTEST_PIN_CTRL2_DTEST_PIN11_MUX_SEL_MASK)

#define RADIO_CTRL_DTEST_PIN_CTRL2_DTEST_PIN11_OVRD_SEL_MASK (0xF0000000U)
#define RADIO_CTRL_DTEST_PIN_CTRL2_DTEST_PIN11_OVRD_SEL_SHIFT (28U)
/*! DTEST_PIN11_OVRD_SEL - DTEST_PIN11_OVRD_SEL
 *  0b0000..override is disabled
 *  0b0001..aa_sfd_matched
 *  0b0010..rx_pd_fnd
 *  0b0011..agc_gain_change
 *  0b0100..tsm_combined_tx_en
 *  0b0101..tsm_combined_rx_en
 *  0b0110..crc_fail
 *  0b0111..decode_data_out
 *  0b1000..tx_data_out
 *  0b1001..nbu_testbus[14]
 *  0b1010..nbu_testbus[15]
 *  0b1011-0b1111..reserved
 */
#define RADIO_CTRL_DTEST_PIN_CTRL2_DTEST_PIN11_OVRD_SEL(x) (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_DTEST_PIN_CTRL2_DTEST_PIN11_OVRD_SEL_SHIFT)) & RADIO_CTRL_DTEST_PIN_CTRL2_DTEST_PIN11_OVRD_SEL_MASK)
/*! @} */

/*! @name FPGA_CTRL - FPGA Control register */
/*! @{ */

#define RADIO_CTRL_FPGA_CTRL_HOP_FREQ_WORD_MASK  (0xFFFFU)
#define RADIO_CTRL_FPGA_CTRL_HOP_FREQ_WORD_SHIFT (0U)
/*! HOP_FREQ_WORD - HOP FREQ WORD to PLL_DIG
 */
#define RADIO_CTRL_FPGA_CTRL_HOP_FREQ_WORD(x)    (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_FPGA_CTRL_HOP_FREQ_WORD_SHIFT)) & RADIO_CTRL_FPGA_CTRL_HOP_FREQ_WORD_MASK)

#define RADIO_CTRL_FPGA_CTRL_TGT_POWER_LL_MASK   (0x3F0000U)
#define RADIO_CTRL_FPGA_CTRL_TGT_POWER_LL_SHIFT  (16U)
/*! TGT_POWER_LL - Target Power Register
 */
#define RADIO_CTRL_FPGA_CTRL_TGT_POWER_LL(x)     (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_FPGA_CTRL_TGT_POWER_LL_SHIFT)) & RADIO_CTRL_FPGA_CTRL_TGT_POWER_LL_MASK)

#define RADIO_CTRL_FPGA_CTRL_DATA_RATE_SEL_MASK  (0x40000000U)
#define RADIO_CTRL_FPGA_CTRL_DATA_RATE_SEL_SHIFT (30U)
/*! DATA_RATE_SEL - Data Rate Select Register
 */
#define RADIO_CTRL_FPGA_CTRL_DATA_RATE_SEL(x)    (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_FPGA_CTRL_DATA_RATE_SEL_SHIFT)) & RADIO_CTRL_FPGA_CTRL_DATA_RATE_SEL_MASK)

#define RADIO_CTRL_FPGA_CTRL_HDI_MODE_MASK       (0x80000000U)
#define RADIO_CTRL_FPGA_CTRL_HDI_MODE_SHIFT      (31U)
/*! HDI_MODE - HDI Mode Select Register
 *  0b0..HDI Mode disabled. (default)
 *  0b1..HDI Mode enabled
 */
#define RADIO_CTRL_FPGA_CTRL_HDI_MODE(x)         (((uint32_t)(((uint32_t)(x)) << RADIO_CTRL_FPGA_CTRL_HDI_MODE_SHIFT)) & RADIO_CTRL_FPGA_CTRL_HDI_MODE_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group RADIO_CTRL_Register_Masks */


/* RADIO_CTRL - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral RADIO_CTRL base address */
  #define RADIO_CTRL_BASE                          (0x58A06000u)
  /** Peripheral RADIO_CTRL base address */
  #define RADIO_CTRL_BASE_NS                       (0x48A06000u)
  /** Peripheral RADIO_CTRL base pointer */
  #define RADIO_CTRL                               ((RADIO_CTRL_Type *)RADIO_CTRL_BASE)
  /** Peripheral RADIO_CTRL base pointer */
  #define RADIO_CTRL_NS                            ((RADIO_CTRL_Type *)RADIO_CTRL_BASE_NS)
  /** Array initializer of RADIO_CTRL peripheral base addresses */
  #define RADIO_CTRL_BASE_ADDRS                    { RADIO_CTRL_BASE }
  /** Array initializer of RADIO_CTRL peripheral base pointers */
  #define RADIO_CTRL_BASE_PTRS                     { RADIO_CTRL }
  /** Array initializer of RADIO_CTRL peripheral base addresses */
  #define RADIO_CTRL_BASE_ADDRS_NS                 { RADIO_CTRL_BASE_NS }
  /** Array initializer of RADIO_CTRL peripheral base pointers */
  #define RADIO_CTRL_BASE_PTRS_NS                  { RADIO_CTRL_NS }
#else
  /** Peripheral RADIO_CTRL base address */
  #define RADIO_CTRL_BASE                          (0x48A06000u)
  /** Peripheral RADIO_CTRL base pointer */
  #define RADIO_CTRL                               ((RADIO_CTRL_Type *)RADIO_CTRL_BASE)
  /** Array initializer of RADIO_CTRL peripheral base addresses */
  #define RADIO_CTRL_BASE_ADDRS                    { RADIO_CTRL_BASE }
  /** Array initializer of RADIO_CTRL peripheral base pointers */
  #define RADIO_CTRL_BASE_PTRS                     { RADIO_CTRL }
#endif

/*!
 * @}
 */ /* end of group RADIO_CTRL_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- RBME Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup RBME_Peripheral_Access_Layer RBME Peripheral Access Layer
 * @{
 */

/** RBME - Register Layout Typedef */
typedef struct {
  __IO uint32_t CRCW_CFG;                          /**< CRC/WHITENER CONFIG REGISTER, offset: 0x0 */
  __I  uint32_t CRC_EC_MASK;                       /**< CRC ERROR CORRECTION MASK, offset: 0x4 */
  __I  uint32_t CRC_RES_OUT;                       /**< CRC RESULT, offset: 0x8 */
  __IO uint32_t CRCW_CFG2;                         /**< CRC/WHITENER CONFIG 2 REGISTER, offset: 0xC */
  __IO uint32_t CRCW_CFG3;                         /**< CRC CONFIGURATION, offset: 0x10 */
  __IO uint32_t CRC_INIT;                          /**< CRC INITIALIZATION, offset: 0x14 */
  __IO uint32_t CRC_POLY;                          /**< CRC POLYNOMIAL, offset: 0x18 */
  __IO uint32_t CRC_XOR_OUT;                       /**< CRC XOR OUT, offset: 0x1C */
  __IO uint32_t WHITEN_CFG;                        /**< WHITENER CONFIGURATION, offset: 0x20 */
  __IO uint32_t WHITEN_POLY;                       /**< WHITENER POLYNOMIAL, offset: 0x24 */
  __IO uint32_t WHITEN_SZ_THR;                     /**< WHITENER SIZE THRESHOLD, offset: 0x28 */
  __IO uint32_t FEC_CFG1;                          /**< FEC CONFIG REGISTER 1, offset: 0x2C */
  __IO uint32_t RBME_RST;                          /**< RBME SOFT RESET REGISTER, offset: 0x30 */
  __IO uint32_t FEC_CFG2;                          /**< FEC CONFIG REGISTER 2, offset: 0x34 */
       uint8_t RESERVED_0[4];
  __IO uint32_t SPREAD_CFG;                        /**< SPREADER CONFIG REGISTER, offset: 0x3C */
  __IO uint32_t WHT_CFG;                           /**< WHITEN CONFIG REGISTER, offset: 0x40 */
  __IO uint32_t PKT_SZ;                            /**< PACKET SIZE REGISTER, offset: 0x44 */
  __IO uint32_t CRC_PHR_SZ;                        /**< LENGTH OF PHR CONFIG REGISTER, offset: 0x48 */
  __IO uint32_t FCP_CFG;                           /**< FCP SUPPORT CONFIG REGISTER, offset: 0x4C */
  __IO uint32_t FRAME_OVER_SZ;                     /**< FRAME OVERRIDE SIZE REGISTER, offset: 0x50 */
  __IO uint32_t FEC_BSZ_OV_B4SP;                   /**< OVERRIDE OF FEC BLOCK SIZE REGISTER, offset: 0x54 */
  __IO uint32_t LEG0_CFG;                          /**< LEG0 CONFIG REGISTER, offset: 0x58 */
  __IO uint32_t NPAYL_OVER_SZ;                     /**< OVERRIDE PAYLOAD LENGTH REGISTER, offset: 0x5C */
       uint8_t RESERVED_1[4];
  __IO uint32_t RAM_S_ADDR;                        /**< PACKET RAM SOURCE ADDRESS, offset: 0x64 */
  __IO uint32_t RAM_D_ADDR;                        /**< PACKET RAM DESTINATION ADDRESS, offset: 0x68 */
  __IO uint32_t RAM_IF_CFG;                        /**< PACKET RAM INTERFACE CONFIG REGISTER, offset: 0x6C */
} RBME_Type;

/* ----------------------------------------------------------------------------
   -- RBME Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup RBME_Register_Masks RBME Register Masks
 * @{
 */

/*! @name CRCW_CFG - CRC/WHITENER CONFIG REGISTER */
/*! @{ */

#define RBME_CRCW_CFG_CRCW_EN_MASK               (0x1U)
#define RBME_CRCW_CFG_CRCW_EN_SHIFT              (0U)
/*! CRCW_EN - CRC calculation enable
 */
#define RBME_CRCW_CFG_CRCW_EN(x)                 (((uint32_t)(((uint32_t)(x)) << RBME_CRCW_CFG_CRCW_EN_SHIFT)) & RBME_CRCW_CFG_CRCW_EN_MASK)

#define RBME_CRCW_CFG_CRCW_EC_EN_MASK            (0x2U)
#define RBME_CRCW_CFG_CRCW_EC_EN_SHIFT           (1U)
/*! CRCW_EC_EN - CRC Error Correction Enable
 */
#define RBME_CRCW_CFG_CRCW_EC_EN(x)              (((uint32_t)(((uint32_t)(x)) << RBME_CRCW_CFG_CRCW_EC_EN_SHIFT)) & RBME_CRCW_CFG_CRCW_EC_EN_MASK)

#define RBME_CRCW_CFG_CRC_ZERO_MASK              (0x4U)
#define RBME_CRCW_CFG_CRC_ZERO_SHIFT             (2U)
/*! CRC_ZERO - CRC zero
 */
#define RBME_CRCW_CFG_CRC_ZERO(x)                (((uint32_t)(((uint32_t)(x)) << RBME_CRCW_CFG_CRC_ZERO_SHIFT)) & RBME_CRCW_CFG_CRC_ZERO_MASK)

#define RBME_CRCW_CFG_CRC_EARLY_FAIL_MASK        (0x8U)
#define RBME_CRCW_CFG_CRC_EARLY_FAIL_SHIFT       (3U)
/*! CRC_EARLY_FAIL - CRC error correction fail
 */
#define RBME_CRCW_CFG_CRC_EARLY_FAIL(x)          (((uint32_t)(((uint32_t)(x)) << RBME_CRCW_CFG_CRC_EARLY_FAIL_SHIFT)) & RBME_CRCW_CFG_CRC_EARLY_FAIL_MASK)

#define RBME_CRCW_CFG_CRC_RES_OUT_VLD_MASK       (0x10U)
#define RBME_CRCW_CFG_CRC_RES_OUT_VLD_SHIFT      (4U)
/*! CRC_RES_OUT_VLD - CRC result output valid
 */
#define RBME_CRCW_CFG_CRC_RES_OUT_VLD(x)         (((uint32_t)(((uint32_t)(x)) << RBME_CRCW_CFG_CRC_RES_OUT_VLD_SHIFT)) & RBME_CRCW_CFG_CRC_RES_OUT_VLD_MASK)

#define RBME_CRCW_CFG_CRC_EC_OFFSET_MASK         (0x7FF0000U)
#define RBME_CRCW_CFG_CRC_EC_OFFSET_SHIFT        (16U)
/*! CRC_EC_OFFSET - CRC error correction offset
 */
#define RBME_CRCW_CFG_CRC_EC_OFFSET(x)           (((uint32_t)(((uint32_t)(x)) << RBME_CRCW_CFG_CRC_EC_OFFSET_SHIFT)) & RBME_CRCW_CFG_CRC_EC_OFFSET_MASK)

#define RBME_CRCW_CFG_CRC_EC_DONE_MASK           (0x10000000U)
#define RBME_CRCW_CFG_CRC_EC_DONE_SHIFT          (28U)
/*! CRC_EC_DONE - CRC error correction done
 */
#define RBME_CRCW_CFG_CRC_EC_DONE(x)             (((uint32_t)(((uint32_t)(x)) << RBME_CRCW_CFG_CRC_EC_DONE_SHIFT)) & RBME_CRCW_CFG_CRC_EC_DONE_MASK)

#define RBME_CRCW_CFG_CRC_EC_FAIL_MASK           (0x20000000U)
#define RBME_CRCW_CFG_CRC_EC_FAIL_SHIFT          (29U)
/*! CRC_EC_FAIL - CRC error correction fail
 */
#define RBME_CRCW_CFG_CRC_EC_FAIL(x)             (((uint32_t)(((uint32_t)(x)) << RBME_CRCW_CFG_CRC_EC_FAIL_SHIFT)) & RBME_CRCW_CFG_CRC_EC_FAIL_MASK)
/*! @} */

/*! @name CRC_EC_MASK - CRC ERROR CORRECTION MASK */
/*! @{ */

#define RBME_CRC_EC_MASK_CRC_EC_MASK_MASK        (0xFFFFFFFFU)
#define RBME_CRC_EC_MASK_CRC_EC_MASK_SHIFT       (0U)
/*! CRC_EC_MASK - CRC error correction mask
 */
#define RBME_CRC_EC_MASK_CRC_EC_MASK(x)          (((uint32_t)(((uint32_t)(x)) << RBME_CRC_EC_MASK_CRC_EC_MASK_SHIFT)) & RBME_CRC_EC_MASK_CRC_EC_MASK_MASK)
/*! @} */

/*! @name CRC_RES_OUT - CRC RESULT */
/*! @{ */

#define RBME_CRC_RES_OUT_CRC_RES_OUT_MASK        (0xFFFFFFFFU)
#define RBME_CRC_RES_OUT_CRC_RES_OUT_SHIFT       (0U)
/*! CRC_RES_OUT - CRC result output
 */
#define RBME_CRC_RES_OUT_CRC_RES_OUT(x)          (((uint32_t)(((uint32_t)(x)) << RBME_CRC_RES_OUT_CRC_RES_OUT_SHIFT)) & RBME_CRC_RES_OUT_CRC_RES_OUT_MASK)
/*! @} */

/*! @name CRCW_CFG2 - CRC/WHITENER CONFIG 2 REGISTER */
/*! @{ */

#define RBME_CRCW_CFG2_CRC_EC_SPKT_BYTES_MASK    (0xFFU)
#define RBME_CRCW_CFG2_CRC_EC_SPKT_BYTES_SHIFT   (0U)
/*! CRC_EC_SPKT_BYTES - Error Correction Short Packet Bytes
 */
#define RBME_CRCW_CFG2_CRC_EC_SPKT_BYTES(x)      (((uint32_t)(((uint32_t)(x)) << RBME_CRCW_CFG2_CRC_EC_SPKT_BYTES_SHIFT)) & RBME_CRCW_CFG2_CRC_EC_SPKT_BYTES_MASK)

#define RBME_CRCW_CFG2_CRC_EC_SPKT_WND_MASK      (0xF00U)
#define RBME_CRCW_CFG2_CRC_EC_SPKT_WND_SHIFT     (8U)
/*! CRC_EC_SPKT_WND - Error correction short packet burst error window
 */
#define RBME_CRCW_CFG2_CRC_EC_SPKT_WND(x)        (((uint32_t)(((uint32_t)(x)) << RBME_CRCW_CFG2_CRC_EC_SPKT_WND_SHIFT)) & RBME_CRCW_CFG2_CRC_EC_SPKT_WND_MASK)

#define RBME_CRCW_CFG2_CRC_EC_LPKT_WND_MASK      (0xF000U)
#define RBME_CRCW_CFG2_CRC_EC_LPKT_WND_SHIFT     (12U)
/*! CRC_EC_LPKT_WND - Error correction long packet burst error window
 */
#define RBME_CRCW_CFG2_CRC_EC_LPKT_WND(x)        (((uint32_t)(((uint32_t)(x)) << RBME_CRCW_CFG2_CRC_EC_LPKT_WND_SHIFT)) & RBME_CRCW_CFG2_CRC_EC_LPKT_WND_MASK)
/*! @} */

/*! @name CRCW_CFG3 - CRC CONFIGURATION */
/*! @{ */

#define RBME_CRCW_CFG3_CRC_SZ_MASK               (0x7U)
#define RBME_CRCW_CFG3_CRC_SZ_SHIFT              (0U)
/*! CRC_SZ - CRC Size (in octets)
 */
#define RBME_CRCW_CFG3_CRC_SZ(x)                 (((uint32_t)(((uint32_t)(x)) << RBME_CRCW_CFG3_CRC_SZ_SHIFT)) & RBME_CRCW_CFG3_CRC_SZ_MASK)

#define RBME_CRCW_CFG3_CRC_START_BYTE_MASK       (0xF00U)
#define RBME_CRCW_CFG3_CRC_START_BYTE_SHIFT      (8U)
/*! CRC_START_BYTE - Configure CRC Start Point
 */
#define RBME_CRCW_CFG3_CRC_START_BYTE(x)         (((uint32_t)(((uint32_t)(x)) << RBME_CRCW_CFG3_CRC_START_BYTE_SHIFT)) & RBME_CRCW_CFG3_CRC_START_BYTE_MASK)

#define RBME_CRCW_CFG3_CRC_REF_IN_MASK           (0x10000U)
#define RBME_CRCW_CFG3_CRC_REF_IN_SHIFT          (16U)
/*! CRC_REF_IN - CRC Reflect In
 *  0b0..Does not manipulate input data stream
 *  0b1..reflect each byte in the input stream bitwise
 */
#define RBME_CRCW_CFG3_CRC_REF_IN(x)             (((uint32_t)(((uint32_t)(x)) << RBME_CRCW_CFG3_CRC_REF_IN_SHIFT)) & RBME_CRCW_CFG3_CRC_REF_IN_MASK)

#define RBME_CRCW_CFG3_CRC_REF_OUT_MASK          (0x20000U)
#define RBME_CRCW_CFG3_CRC_REF_OUT_SHIFT         (17U)
/*! CRC_REF_OUT - CRC Reflect Out
 *  0b0..Does not manipulate CRC result
 *  0b1..CRC result is to be reflected bitwise (operated on entire word)
 */
#define RBME_CRCW_CFG3_CRC_REF_OUT(x)            (((uint32_t)(((uint32_t)(x)) << RBME_CRCW_CFG3_CRC_REF_OUT_SHIFT)) & RBME_CRCW_CFG3_CRC_REF_OUT_MASK)

#define RBME_CRCW_CFG3_CRC_BYTE_ORD_MASK         (0x40000U)
#define RBME_CRCW_CFG3_CRC_BYTE_ORD_SHIFT        (18U)
/*! CRC_BYTE_ORD - CRC Byte Order
 *  0b0..LS Byte First
 *  0b1..MS Byte First
 */
#define RBME_CRCW_CFG3_CRC_BYTE_ORD(x)           (((uint32_t)(((uint32_t)(x)) << RBME_CRCW_CFG3_CRC_BYTE_ORD_SHIFT)) & RBME_CRCW_CFG3_CRC_BYTE_ORD_MASK)
/*! @} */

/*! @name CRC_INIT - CRC INITIALIZATION */
/*! @{ */

#define RBME_CRC_INIT_CRC_SEED_MASK              (0xFFFFFFFFU)
#define RBME_CRC_INIT_CRC_SEED_SHIFT             (0U)
/*! CRC_SEED - CRC Seed Value
 */
#define RBME_CRC_INIT_CRC_SEED(x)                (((uint32_t)(((uint32_t)(x)) << RBME_CRC_INIT_CRC_SEED_SHIFT)) & RBME_CRC_INIT_CRC_SEED_MASK)
/*! @} */

/*! @name CRC_POLY - CRC POLYNOMIAL */
/*! @{ */

#define RBME_CRC_POLY_CRC_POLY_MASK              (0xFFFFFFFFU)
#define RBME_CRC_POLY_CRC_POLY_SHIFT             (0U)
/*! CRC_POLY - CRC Polynomial.
 */
#define RBME_CRC_POLY_CRC_POLY(x)                (((uint32_t)(((uint32_t)(x)) << RBME_CRC_POLY_CRC_POLY_SHIFT)) & RBME_CRC_POLY_CRC_POLY_MASK)
/*! @} */

/*! @name CRC_XOR_OUT - CRC XOR OUT */
/*! @{ */

#define RBME_CRC_XOR_OUT_CRC_XOR_OUT_MASK        (0xFFFFFFFFU)
#define RBME_CRC_XOR_OUT_CRC_XOR_OUT_SHIFT       (0U)
/*! CRC_XOR_OUT - CRC XOR OUT Register
 */
#define RBME_CRC_XOR_OUT_CRC_XOR_OUT(x)          (((uint32_t)(((uint32_t)(x)) << RBME_CRC_XOR_OUT_CRC_XOR_OUT_SHIFT)) & RBME_CRC_XOR_OUT_CRC_XOR_OUT_MASK)
/*! @} */

/*! @name WHITEN_CFG - WHITENER CONFIGURATION */
/*! @{ */

#define RBME_WHITEN_CFG_WHITEN_START_MASK        (0x3U)
#define RBME_WHITEN_CFG_WHITEN_START_SHIFT       (0U)
/*! WHITEN_START - Configure Whitener Start Point
 *  0b00..no whitening
 *  0b01..start whitening at start-of-H0
 *  0b10..start whitening at start-of-H1 but only if LENGTH > WHITEN_SZ_THR
 *  0b11..start whitening at start-of-payload but only if LENGTH > WHITEN_SZ_THR
 */
#define RBME_WHITEN_CFG_WHITEN_START(x)          (((uint32_t)(((uint32_t)(x)) << RBME_WHITEN_CFG_WHITEN_START_SHIFT)) & RBME_WHITEN_CFG_WHITEN_START_MASK)

#define RBME_WHITEN_CFG_WHITEN_END_MASK          (0x4U)
#define RBME_WHITEN_CFG_WHITEN_END_SHIFT         (2U)
/*! WHITEN_END - Configure end-of-whitening
 *  0b0..end whiten at end-of-payload
 *  0b1..end whiten at end-of-crc
 */
#define RBME_WHITEN_CFG_WHITEN_END(x)            (((uint32_t)(((uint32_t)(x)) << RBME_WHITEN_CFG_WHITEN_END_SHIFT)) & RBME_WHITEN_CFG_WHITEN_END_MASK)

#define RBME_WHITEN_CFG_WHITEN_B4_CRC_MASK       (0x8U)
#define RBME_WHITEN_CFG_WHITEN_B4_CRC_SHIFT      (3U)
/*! WHITEN_B4_CRC - Congifure for Whitening-before-CRC
 *  0b0..CRC before whiten/de-whiten
 *  0b1..Whiten/de-whiten before CRC
 */
#define RBME_WHITEN_CFG_WHITEN_B4_CRC(x)         (((uint32_t)(((uint32_t)(x)) << RBME_WHITEN_CFG_WHITEN_B4_CRC_SHIFT)) & RBME_WHITEN_CFG_WHITEN_B4_CRC_MASK)

#define RBME_WHITEN_CFG_WHITEN_POLY_TYPE_MASK    (0x10U)
#define RBME_WHITEN_CFG_WHITEN_POLY_TYPE_SHIFT   (4U)
/*! WHITEN_POLY_TYPE - Whiten Polynomial Type
 */
#define RBME_WHITEN_CFG_WHITEN_POLY_TYPE(x)      (((uint32_t)(((uint32_t)(x)) << RBME_WHITEN_CFG_WHITEN_POLY_TYPE_SHIFT)) & RBME_WHITEN_CFG_WHITEN_POLY_TYPE_MASK)

#define RBME_WHITEN_CFG_WHITEN_REF_IN_MASK       (0x20U)
#define RBME_WHITEN_CFG_WHITEN_REF_IN_SHIFT      (5U)
/*! WHITEN_REF_IN - Whiten Reflect Input
 */
#define RBME_WHITEN_CFG_WHITEN_REF_IN(x)         (((uint32_t)(((uint32_t)(x)) << RBME_WHITEN_CFG_WHITEN_REF_IN_SHIFT)) & RBME_WHITEN_CFG_WHITEN_REF_IN_MASK)

#define RBME_WHITEN_CFG_WHITEN_PAYLOAD_REINIT_MASK (0x40U)
#define RBME_WHITEN_CFG_WHITEN_PAYLOAD_REINIT_SHIFT (6U)
/*! WHITEN_PAYLOAD_REINIT - Configure for Whitener re-initialization
 *  0b0..Does not re-initialize Whitener LFSR at start-of-payload
 *  0b1..Re-initialize Whitener LFSR at start-of-payload
 */
#define RBME_WHITEN_CFG_WHITEN_PAYLOAD_REINIT(x) (((uint32_t)(((uint32_t)(x)) << RBME_WHITEN_CFG_WHITEN_PAYLOAD_REINIT_SHIFT)) & RBME_WHITEN_CFG_WHITEN_PAYLOAD_REINIT_MASK)

#define RBME_WHITEN_CFG_WHITEN_SIZE_MASK         (0xF00U)
#define RBME_WHITEN_CFG_WHITEN_SIZE_SHIFT        (8U)
/*! WHITEN_SIZE - Length of Whitener LFSR
 */
#define RBME_WHITEN_CFG_WHITEN_SIZE(x)           (((uint32_t)(((uint32_t)(x)) << RBME_WHITEN_CFG_WHITEN_SIZE_SHIFT)) & RBME_WHITEN_CFG_WHITEN_SIZE_MASK)

#define RBME_WHITEN_CFG_WHITEN_INIT_MASK         (0x1FF0000U)
#define RBME_WHITEN_CFG_WHITEN_INIT_SHIFT        (16U)
/*! WHITEN_INIT - Initialization value for whitening/de-whitening
 */
#define RBME_WHITEN_CFG_WHITEN_INIT(x)           (((uint32_t)(((uint32_t)(x)) << RBME_WHITEN_CFG_WHITEN_INIT_SHIFT)) & RBME_WHITEN_CFG_WHITEN_INIT_MASK)
/*! @} */

/*! @name WHITEN_POLY - WHITENER POLYNOMIAL */
/*! @{ */

#define RBME_WHITEN_POLY_WHITEN_POLY_MASK        (0x1FFU)
#define RBME_WHITEN_POLY_WHITEN_POLY_SHIFT       (0U)
/*! WHITEN_POLY - Whitener Polynomial
 */
#define RBME_WHITEN_POLY_WHITEN_POLY(x)          (((uint32_t)(((uint32_t)(x)) << RBME_WHITEN_POLY_WHITEN_POLY_SHIFT)) & RBME_WHITEN_POLY_WHITEN_POLY_MASK)
/*! @} */

/*! @name WHITEN_SZ_THR - WHITENER SIZE THRESHOLD */
/*! @{ */

#define RBME_WHITEN_SZ_THR_WHITEN_SZ_THR_MASK    (0xFFFU)
#define RBME_WHITEN_SZ_THR_WHITEN_SZ_THR_SHIFT   (0U)
/*! WHITEN_SZ_THR - Whitener Size Threshold
 */
#define RBME_WHITEN_SZ_THR_WHITEN_SZ_THR(x)      (((uint32_t)(((uint32_t)(x)) << RBME_WHITEN_SZ_THR_WHITEN_SZ_THR_SHIFT)) & RBME_WHITEN_SZ_THR_WHITEN_SZ_THR_MASK)
/*! @} */

/*! @name FEC_CFG1 - FEC CONFIG REGISTER 1 */
/*! @{ */

#define RBME_FEC_CFG1_FEC_EN_MASK                (0x1U)
#define RBME_FEC_CFG1_FEC_EN_SHIFT               (0U)
/*! FEC_EN - FEC enable
 *  0b0..Disable FEC encoder and decoder
 *  0b1..Enable FEC encoder and decoder
 */
#define RBME_FEC_CFG1_FEC_EN(x)                  (((uint32_t)(((uint32_t)(x)) << RBME_FEC_CFG1_FEC_EN_SHIFT)) & RBME_FEC_CFG1_FEC_EN_MASK)

#define RBME_FEC_CFG1_FEC_SWAP_MASK              (0x2U)
#define RBME_FEC_CFG1_FEC_SWAP_SHIFT             (1U)
/*! FEC_SWAP - FEC output swap
 */
#define RBME_FEC_CFG1_FEC_SWAP(x)                (((uint32_t)(((uint32_t)(x)) << RBME_FEC_CFG1_FEC_SWAP_SHIFT)) & RBME_FEC_CFG1_FEC_SWAP_MASK)

#define RBME_FEC_CFG1_FECOV_EN_MASK              (0x4U)
#define RBME_FEC_CFG1_FECOV_EN_SHIFT             (2U)
/*! FECOV_EN - Enable dynamic overide of FEC
 *  0b1..The override of FEC is only used in Bluetooth LE LR cases, dynamically depending on the LR AA detected
 *  0b0..Disable FEC override
 */
#define RBME_FEC_CFG1_FECOV_EN(x)                (((uint32_t)(((uint32_t)(x)) << RBME_FEC_CFG1_FECOV_EN_SHIFT)) & RBME_FEC_CFG1_FECOV_EN_MASK)

#define RBME_FEC_CFG1_INTV_EN_MASK               (0x10U)
#define RBME_FEC_CFG1_INTV_EN_SHIFT              (4U)
/*! INTV_EN - Enable interleaver reigster
 */
#define RBME_FEC_CFG1_INTV_EN(x)                 (((uint32_t)(((uint32_t)(x)) << RBME_FEC_CFG1_INTV_EN_SHIFT)) & RBME_FEC_CFG1_INTV_EN_MASK)

#define RBME_FEC_CFG1_FEC_START_BYTE_MASK        (0xE0U)
#define RBME_FEC_CFG1_FEC_START_BYTE_SHIFT       (5U)
/*! FEC_START_BYTE - FEC Start Byte
 */
#define RBME_FEC_CFG1_FEC_START_BYTE(x)          (((uint32_t)(((uint32_t)(x)) << RBME_FEC_CFG1_FEC_START_BYTE_SHIFT)) & RBME_FEC_CFG1_FEC_START_BYTE_MASK)

#define RBME_FEC_CFG1_NTERM_MASK                 (0x700U)
#define RBME_FEC_CFG1_NTERM_SHIFT                (8U)
/*! NTERM - Number of term bits
 */
#define RBME_FEC_CFG1_NTERM(x)                   (((uint32_t)(((uint32_t)(x)) << RBME_FEC_CFG1_NTERM_SHIFT)) & RBME_FEC_CFG1_NTERM_MASK)
/*! @} */

/*! @name RBME_RST - RBME SOFT RESET REGISTER */
/*! @{ */

#define RBME_RBME_RST_RBME_RST_MASK              (0x1U)
#define RBME_RBME_RST_RBME_RST_SHIFT             (0U)
/*! RBME_RST - RBME reset signal
 *  0b0..Disable soft reset
 *  0b1..Enable soft reset. When this bit is write to 1, the soft reset to RBME happens immediately. Then all
 *       internal registers and functions will be reset.
 */
#define RBME_RBME_RST_RBME_RST(x)                (((uint32_t)(((uint32_t)(x)) << RBME_RBME_RST_RBME_RST_SHIFT)) & RBME_RBME_RST_RBME_RST_MASK)

#define RBME_RBME_RST_RBME_CLK_EN_OVRD_MASK      (0x2U)
#define RBME_RBME_RST_RBME_CLK_EN_OVRD_SHIFT     (1U)
/*! RBME_CLK_EN_OVRD - RBME Clock Enable override
 */
#define RBME_RBME_RST_RBME_CLK_EN_OVRD(x)        (((uint32_t)(((uint32_t)(x)) << RBME_RBME_RST_RBME_CLK_EN_OVRD_SHIFT)) & RBME_RBME_RST_RBME_CLK_EN_OVRD_MASK)
/*! @} */

/*! @name FEC_CFG2 - FEC CONFIG REGISTER 2 */
/*! @{ */

#define RBME_FEC_CFG2_TB_LENGTH_MASK             (0x1FU)
#define RBME_FEC_CFG2_TB_LENGTH_SHIFT            (0U)
/*! TB_LENGTH - Trace-back length
 */
#define RBME_FEC_CFG2_TB_LENGTH(x)               (((uint32_t)(((uint32_t)(x)) << RBME_FEC_CFG2_TB_LENGTH_SHIFT)) & RBME_FEC_CFG2_TB_LENGTH_MASK)

#define RBME_FEC_CFG2_SAT_VL_MASK                (0xFF00U)
#define RBME_FEC_CFG2_SAT_VL_SHIFT               (8U)
/*! SAT_VL - Saturation value for PM
 */
#define RBME_FEC_CFG2_SAT_VL(x)                  (((uint32_t)(((uint32_t)(x)) << RBME_FEC_CFG2_SAT_VL_SHIFT)) & RBME_FEC_CFG2_SAT_VL_MASK)

#define RBME_FEC_CFG2_LARGE_VL_MASK              (0x7F0000U)
#define RBME_FEC_CFG2_LARGE_VL_SHIFT             (16U)
/*! LARGE_VL - Large value used at startup phase, assigned to the initial PMs.
 */
#define RBME_FEC_CFG2_LARGE_VL(x)                (((uint32_t)(((uint32_t)(x)) << RBME_FEC_CFG2_LARGE_VL_SHIFT)) & RBME_FEC_CFG2_LARGE_VL_MASK)

#define RBME_FEC_CFG2_SDIDX_MASK                 (0x7000000U)
#define RBME_FEC_CFG2_SDIDX_SHIFT                (24U)
/*! SDIDX - Index of startup state. PM(startStIdx)=0
 */
#define RBME_FEC_CFG2_SDIDX(x)                   (((uint32_t)(((uint32_t)(x)) << RBME_FEC_CFG2_SDIDX_SHIFT)) & RBME_FEC_CFG2_SDIDX_MASK)
/*! @} */

/*! @name SPREAD_CFG - SPREADER CONFIG REGISTER */
/*! @{ */

#define RBME_SPREAD_CFG_SP_EN_MASK               (0x1U)
#define RBME_SPREAD_CFG_SP_EN_SHIFT              (0U)
/*! SP_EN - Spreader Enable bit
 *  0b0..Disable spreader
 *  0b1..Enable spreader
 */
#define RBME_SPREAD_CFG_SP_EN(x)                 (((uint32_t)(((uint32_t)(x)) << RBME_SPREAD_CFG_SP_EN_SHIFT)) & RBME_SPREAD_CFG_SP_EN_MASK)

#define RBME_SPREAD_CFG_SPOV_EN_MASK             (0x2U)
#define RBME_SPREAD_CFG_SPOV_EN_SHIFT            (1U)
/*! SPOV_EN - Spreader Override Enable
 *  0b0..Does not allow active override of the spreading enable
 *  0b1..Allows active override of the spreading enable
 */
#define RBME_SPREAD_CFG_SPOV_EN(x)               (((uint32_t)(((uint32_t)(x)) << RBME_SPREAD_CFG_SPOV_EN_SHIFT)) & RBME_SPREAD_CFG_SPOV_EN_MASK)

#define RBME_SPREAD_CFG_CI_TX_MASK               (0x4U)
#define RBME_SPREAD_CFG_CI_TX_SHIFT              (2U)
/*! CI_TX - Bluetooth LE
 *  0b0..FEC Block 2 coded using S=8
 *  0b1..FEC Block 2 coded using S=2
 */
#define RBME_SPREAD_CFG_CI_TX(x)                 (((uint32_t)(((uint32_t)(x)) << RBME_SPREAD_CFG_CI_TX_SHIFT)) & RBME_SPREAD_CFG_CI_TX_MASK)

#define RBME_SPREAD_CFG_SP_START_BYTE_MASK       (0x38U)
#define RBME_SPREAD_CFG_SP_START_BYTE_SHIFT      (3U)
/*! SP_START_BYTE - Spread Start Byte
 */
#define RBME_SPREAD_CFG_SP_START_BYTE(x)         (((uint32_t)(((uint32_t)(x)) << RBME_SPREAD_CFG_SP_START_BYTE_SHIFT)) & RBME_SPREAD_CFG_SP_START_BYTE_MASK)

#define RBME_SPREAD_CFG_SP_FACTOR_MASK           (0x700U)
#define RBME_SPREAD_CFG_SP_FACTOR_SHIFT          (8U)
/*! SP_FACTOR - Spreading Factor
 *  0b000..Factor = 1(No spreading and despreading)
 *  0b001..Factor = 2
 *  0b010..Factor = 4
 *  0b011..Factor = 8
 *  0b100..Factor = 16
 */
#define RBME_SPREAD_CFG_SP_FACTOR(x)             (((uint32_t)(((uint32_t)(x)) << RBME_SPREAD_CFG_SP_FACTOR_SHIFT)) & RBME_SPREAD_CFG_SP_FACTOR_MASK)

#define RBME_SPREAD_CFG_SP_SEQ_MASK              (0xFFFF0000U)
#define RBME_SPREAD_CFG_SP_SEQ_SHIFT             (16U)
/*! SP_SEQ - Spreading Bit Sequence
 */
#define RBME_SPREAD_CFG_SP_SEQ(x)                (((uint32_t)(((uint32_t)(x)) << RBME_SPREAD_CFG_SP_SEQ_SHIFT)) & RBME_SPREAD_CFG_SP_SEQ_MASK)
/*! @} */

/*! @name WHT_CFG - WHITEN CONFIG REGISTER */
/*! @{ */

#define RBME_WHT_CFG_W1_EN_MASK                  (0x1U)
#define RBME_WHT_CFG_W1_EN_SHIFT                 (0U)
/*! W1_EN - Enable first whitener
 */
#define RBME_WHT_CFG_W1_EN(x)                    (((uint32_t)(((uint32_t)(x)) << RBME_WHT_CFG_W1_EN_SHIFT)) & RBME_WHT_CFG_W1_EN_MASK)

#define RBME_WHT_CFG_WFIRST_MASK                 (0x4U)
#define RBME_WHT_CFG_WFIRST_SHIFT                (2U)
/*! WFIRST - Whitens before CRC
 */
#define RBME_WHT_CFG_WFIRST(x)                   (((uint32_t)(((uint32_t)(x)) << RBME_WHT_CFG_WFIRST_SHIFT)) & RBME_WHT_CFG_WFIRST_MASK)

#define RBME_WHT_CFG_WTOV_EN_MASK                (0x8U)
#define RBME_WHT_CFG_WTOV_EN_SHIFT               (3U)
/*! WTOV_EN - Allows overwrite of the whitening
 */
#define RBME_WHT_CFG_WTOV_EN(x)                  (((uint32_t)(((uint32_t)(x)) << RBME_WHT_CFG_WTOV_EN_SHIFT)) & RBME_WHT_CFG_WTOV_EN_MASK)

#define RBME_WHT_CFG_WT_OUT_SEL_MASK             (0xF000U)
#define RBME_WHT_CFG_WT_OUT_SEL_SHIFT            (12U)
/*! WT_OUT_SEL - Selected Output
 */
#define RBME_WHT_CFG_WT_OUT_SEL(x)               (((uint32_t)(((uint32_t)(x)) << RBME_WHT_CFG_WT_OUT_SEL_SHIFT)) & RBME_WHT_CFG_WT_OUT_SEL_MASK)

#define RBME_WHT_CFG_WT_TPOGY_MASK               (0x3000000U)
#define RBME_WHT_CFG_WT_TPOGY_SHIFT              (24U)
/*! WT_TPOGY - Whiten 1 Polynomial Type
 */
#define RBME_WHT_CFG_WT_TPOGY(x)                 (((uint32_t)(((uint32_t)(x)) << RBME_WHT_CFG_WT_TPOGY_SHIFT)) & RBME_WHT_CFG_WT_TPOGY_MASK)
/*! @} */

/*! @name PKT_SZ - PACKET SIZE REGISTER */
/*! @{ */

#define RBME_PKT_SZ_MAX_PKT_SZ_MASK              (0xFFFFU)
#define RBME_PKT_SZ_MAX_PKT_SZ_SHIFT             (0U)
/*! MAX_PKT_SZ - Maximum Packet Size In Bits
 */
#define RBME_PKT_SZ_MAX_PKT_SZ(x)                (((uint32_t)(((uint32_t)(x)) << RBME_PKT_SZ_MAX_PKT_SZ_SHIFT)) & RBME_PKT_SZ_MAX_PKT_SZ_MASK)

#define RBME_PKT_SZ_DEF_PKT_SZ_MASK              (0xFFFF0000U)
#define RBME_PKT_SZ_DEF_PKT_SZ_SHIFT             (16U)
/*! DEF_PKT_SZ - Default Packet Size
 */
#define RBME_PKT_SZ_DEF_PKT_SZ(x)                (((uint32_t)(((uint32_t)(x)) << RBME_PKT_SZ_DEF_PKT_SZ_SHIFT)) & RBME_PKT_SZ_DEF_PKT_SZ_MASK)
/*! @} */

/*! @name CRC_PHR_SZ - LENGTH OF PHR CONFIG REGISTER */
/*! @{ */

#define RBME_CRC_PHR_SZ_PHR_SZ_MASK              (0xFU)
#define RBME_CRC_PHR_SZ_PHR_SZ_SHIFT             (0U)
/*! PHR_SZ - PHR Size Config
 */
#define RBME_CRC_PHR_SZ_PHR_SZ(x)                (((uint32_t)(((uint32_t)(x)) << RBME_CRC_PHR_SZ_PHR_SZ_SHIFT)) & RBME_CRC_PHR_SZ_PHR_SZ_MASK)
/*! @} */

/*! @name FCP_CFG - FCP SUPPORT CONFIG REGISTER */
/*! @{ */

#define RBME_FCP_CFG_FCP_SUPPORT_MASK            (0x1U)
#define RBME_FCP_CFG_FCP_SUPPORT_SHIFT           (0U)
/*! FCP_SUPPORT - FCP Suppport
 *  0b0..Disable FCP support
 *  0b1..Enable FCP support
 */
#define RBME_FCP_CFG_FCP_SUPPORT(x)              (((uint32_t)(((uint32_t)(x)) << RBME_FCP_CFG_FCP_SUPPORT_SHIFT)) & RBME_FCP_CFG_FCP_SUPPORT_MASK)
/*! @} */

/*! @name FRAME_OVER_SZ - FRAME OVERRIDE SIZE REGISTER */
/*! @{ */

#define RBME_FRAME_OVER_SZ_STD_FRM_OV_EN_MASK    (0x1U)
#define RBME_FRAME_OVER_SZ_STD_FRM_OV_EN_SHIFT   (0U)
/*! STD_FRM_OV_EN - Overrides actvie STD frame length from link layer enable bit
 *  0b0..Disable override actvie STD frame length from link layer
 *  0b1..Enable override actvie STD frame length from link layer
 */
#define RBME_FRAME_OVER_SZ_STD_FRM_OV_EN(x)      (((uint32_t)(((uint32_t)(x)) << RBME_FRAME_OVER_SZ_STD_FRM_OV_EN_SHIFT)) & RBME_FRAME_OVER_SZ_STD_FRM_OV_EN_MASK)

#define RBME_FRAME_OVER_SZ_STD_FRM_OV_MASK       (0x7FF0000U)
#define RBME_FRAME_OVER_SZ_STD_FRM_OV_SHIFT      (16U)
/*! STD_FRM_OV - Value to overide the STD frame length (bits)
 */
#define RBME_FRAME_OVER_SZ_STD_FRM_OV(x)         (((uint32_t)(((uint32_t)(x)) << RBME_FRAME_OVER_SZ_STD_FRM_OV_SHIFT)) & RBME_FRAME_OVER_SZ_STD_FRM_OV_MASK)
/*! @} */

/*! @name FEC_BSZ_OV_B4SP - OVERRIDE OF FEC BLOCK SIZE REGISTER */
/*! @{ */

#define RBME_FEC_BSZ_OV_B4SP_FEC_BSZ_OV_B4SP_EN_MASK (0x1U)
#define RBME_FEC_BSZ_OV_B4SP_FEC_BSZ_OV_B4SP_EN_SHIFT (0U)
/*! FEC_BSZ_OV_B4SP_EN - Override of the FEC block size for data
 *  0b0..Disable Override actvie STD frame length from link layer
 *  0b1..Enable Override actvie STD frame length from link layer
 */
#define RBME_FEC_BSZ_OV_B4SP_FEC_BSZ_OV_B4SP_EN(x) (((uint32_t)(((uint32_t)(x)) << RBME_FEC_BSZ_OV_B4SP_FEC_BSZ_OV_B4SP_EN_SHIFT)) & RBME_FEC_BSZ_OV_B4SP_FEC_BSZ_OV_B4SP_EN_MASK)

#define RBME_FEC_BSZ_OV_B4SP_FEC_BSZ_OV_MASK     (0xFFFF0000U)
#define RBME_FEC_BSZ_OV_B4SP_FEC_BSZ_OV_SHIFT    (16U)
/*! FEC_BSZ_OV - Value of the override in bits. It is for test purpose.
 */
#define RBME_FEC_BSZ_OV_B4SP_FEC_BSZ_OV(x)       (((uint32_t)(((uint32_t)(x)) << RBME_FEC_BSZ_OV_B4SP_FEC_BSZ_OV_SHIFT)) & RBME_FEC_BSZ_OV_B4SP_FEC_BSZ_OV_MASK)
/*! @} */

/*! @name LEG0_CFG - LEG0 CONFIG REGISTER */
/*! @{ */

#define RBME_LEG0_CFG_LEG0_INV_EN_MASK           (0x1U)
#define RBME_LEG0_CFG_LEG0_INV_EN_SHIFT          (0U)
/*! LEG0_INV_EN - Whiten invert enable bit
 *  0b0..Disable whiten invert for LEG0
 *  0b1..Enable whiten invert for LEG0
 */
#define RBME_LEG0_CFG_LEG0_INV_EN(x)             (((uint32_t)(((uint32_t)(x)) << RBME_LEG0_CFG_LEG0_INV_EN_SHIFT)) & RBME_LEG0_CFG_LEG0_INV_EN_MASK)

#define RBME_LEG0_CFG_LEG0_SUP_MASK              (0x2U)
#define RBME_LEG0_CFG_LEG0_SUP_SHIFT             (1U)
/*! LEG0_SUP - LEG0 support register
 *  0b0..Disable LEG0 support
 *  0b1..Enable LEG0 support
 */
#define RBME_LEG0_CFG_LEG0_SUP(x)                (((uint32_t)(((uint32_t)(x)) << RBME_LEG0_CFG_LEG0_SUP_SHIFT)) & RBME_LEG0_CFG_LEG0_SUP_MASK)

#define RBME_LEG0_CFG_LEG0_XOR_BYTE_MASK         (0xFF00U)
#define RBME_LEG0_CFG_LEG0_XOR_BYTE_SHIFT        (8U)
/*! LEG0_XOR_BYTE - LEG0 whitening masking byte
 */
#define RBME_LEG0_CFG_LEG0_XOR_BYTE(x)           (((uint32_t)(((uint32_t)(x)) << RBME_LEG0_CFG_LEG0_XOR_BYTE_SHIFT)) & RBME_LEG0_CFG_LEG0_XOR_BYTE_MASK)

#define RBME_LEG0_CFG_LEG0_XOR_RP_BYTE_MASK      (0xFF0000U)
#define RBME_LEG0_CFG_LEG0_XOR_RP_BYTE_SHIFT     (16U)
/*! LEG0_XOR_RP_BYTE - LEG0 repeat bytes masking
 */
#define RBME_LEG0_CFG_LEG0_XOR_RP_BYTE(x)        (((uint32_t)(((uint32_t)(x)) << RBME_LEG0_CFG_LEG0_XOR_RP_BYTE_SHIFT)) & RBME_LEG0_CFG_LEG0_XOR_RP_BYTE_MASK)

#define RBME_LEG0_CFG_LEG0_XOR_FST_BYTE_MASK     (0xFF000000U)
#define RBME_LEG0_CFG_LEG0_XOR_FST_BYTE_SHIFT    (24U)
/*! LEG0_XOR_FST_BYTE - FEC first byte masking
 */
#define RBME_LEG0_CFG_LEG0_XOR_FST_BYTE(x)       (((uint32_t)(((uint32_t)(x)) << RBME_LEG0_CFG_LEG0_XOR_FST_BYTE_SHIFT)) & RBME_LEG0_CFG_LEG0_XOR_FST_BYTE_MASK)
/*! @} */

/*! @name NPAYL_OVER_SZ - OVERRIDE PAYLOAD LENGTH REGISTER */
/*! @{ */

#define RBME_NPAYL_OVER_SZ_NPAYL_OV_EN_MASK      (0x1U)
#define RBME_NPAYL_OVER_SZ_NPAYL_OV_EN_SHIFT     (0U)
/*! NPAYL_OV_EN - Override the internal payload length computation
 *  0b0..Disable override the internal payload length
 *  0b1..Enable override the internal payload length
 */
#define RBME_NPAYL_OVER_SZ_NPAYL_OV_EN(x)        (((uint32_t)(((uint32_t)(x)) << RBME_NPAYL_OVER_SZ_NPAYL_OV_EN_SHIFT)) & RBME_NPAYL_OVER_SZ_NPAYL_OV_EN_MASK)

#define RBME_NPAYL_OVER_SZ_FT_FEC_FLUSH_MASK     (0x1F00U)
#define RBME_NPAYL_OVER_SZ_FT_FEC_FLUSH_SHIFT    (8U)
/*! FT_FEC_FLUSH - Value to overide the payload length (bits)
 */
#define RBME_NPAYL_OVER_SZ_FT_FEC_FLUSH(x)       (((uint32_t)(((uint32_t)(x)) << RBME_NPAYL_OVER_SZ_FT_FEC_FLUSH_SHIFT)) & RBME_NPAYL_OVER_SZ_FT_FEC_FLUSH_MASK)

#define RBME_NPAYL_OVER_SZ_NPAYL_OV_MASK         (0x7FF0000U)
#define RBME_NPAYL_OVER_SZ_NPAYL_OV_SHIFT        (16U)
#define RBME_NPAYL_OVER_SZ_NPAYL_OV(x)           (((uint32_t)(((uint32_t)(x)) << RBME_NPAYL_OVER_SZ_NPAYL_OV_SHIFT)) & RBME_NPAYL_OVER_SZ_NPAYL_OV_MASK)
/*! @} */

/*! @name RAM_S_ADDR - PACKET RAM SOURCE ADDRESS */
/*! @{ */

#define RBME_RAM_S_ADDR_RAM_S_ADDR_MASK          (0x3FFFU)
#define RBME_RAM_S_ADDR_RAM_S_ADDR_SHIFT         (0U)
/*! RAM_S_ADDR - Packet RAM source address. This address is ram physical address.
 */
#define RBME_RAM_S_ADDR_RAM_S_ADDR(x)            (((uint32_t)(((uint32_t)(x)) << RBME_RAM_S_ADDR_RAM_S_ADDR_SHIFT)) & RBME_RAM_S_ADDR_RAM_S_ADDR_MASK)
/*! @} */

/*! @name RAM_D_ADDR - PACKET RAM DESTINATION ADDRESS */
/*! @{ */

#define RBME_RAM_D_ADDR_RAM_D_ADDR_MASK          (0x3FFFU)
#define RBME_RAM_D_ADDR_RAM_D_ADDR_SHIFT         (0U)
/*! RAM_D_ADDR - Packet RAM destination address, this address is ram physical address.
 */
#define RBME_RAM_D_ADDR_RAM_D_ADDR(x)            (((uint32_t)(((uint32_t)(x)) << RBME_RAM_D_ADDR_RAM_D_ADDR_SHIFT)) & RBME_RAM_D_ADDR_RAM_D_ADDR_MASK)
/*! @} */

/*! @name RAM_IF_CFG - PACKET RAM INTERFACE CONFIG REGISTER */
/*! @{ */

#define RBME_RAM_IF_CFG_RAM_IF_TX_EN_MASK        (0x1U)
#define RBME_RAM_IF_CFG_RAM_IF_TX_EN_SHIFT       (0U)
/*! RAM_IF_TX_EN - RAM interface TX enable bit
 *  0b0..Disable RAM interface TX
 *  0b1..Enable RAM interface TX
 */
#define RBME_RAM_IF_CFG_RAM_IF_TX_EN(x)          (((uint32_t)(((uint32_t)(x)) << RBME_RAM_IF_CFG_RAM_IF_TX_EN_SHIFT)) & RBME_RAM_IF_CFG_RAM_IF_TX_EN_MASK)

#define RBME_RAM_IF_CFG_RAM_IF_RX_EN_MASK        (0x2U)
#define RBME_RAM_IF_CFG_RAM_IF_RX_EN_SHIFT       (1U)
/*! RAM_IF_RX_EN - RAM interface RX enable
 *  0b0..Disable RAM interface RX
 *  0b1..Enable RAM interface RX
 */
#define RBME_RAM_IF_CFG_RAM_IF_RX_EN(x)          (((uint32_t)(((uint32_t)(x)) << RBME_RAM_IF_CFG_RAM_IF_RX_EN_SHIFT)) & RBME_RAM_IF_CFG_RAM_IF_RX_EN_MASK)

#define RBME_RAM_IF_CFG_RAM_IF_IE_MASK           (0x10U)
#define RBME_RAM_IF_CFG_RAM_IF_IE_SHIFT          (4U)
/*! RAM_IF_IE - RAM interface interrupt enable bit
 *  0b0..Disable RAM interface interrupt
 *  0b1..Enable RAM interface interrupt
 */
#define RBME_RAM_IF_CFG_RAM_IF_IE(x)             (((uint32_t)(((uint32_t)(x)) << RBME_RAM_IF_CFG_RAM_IF_IE_SHIFT)) & RBME_RAM_IF_CFG_RAM_IF_IE_MASK)

#define RBME_RAM_IF_CFG_RAM_IF_IC_MASK           (0x20U)
#define RBME_RAM_IF_CFG_RAM_IF_IC_SHIFT          (5U)
/*! RAM_IF_IC - RAM interface interrupt clear
 *  0b0..To do nothing to RAM interface interrupt
 *  0b1..To clear RAM interface interrupt
 */
#define RBME_RAM_IF_CFG_RAM_IF_IC(x)             (((uint32_t)(((uint32_t)(x)) << RBME_RAM_IF_CFG_RAM_IF_IC_SHIFT)) & RBME_RAM_IF_CFG_RAM_IF_IC_MASK)

#define RBME_RAM_IF_CFG_H2S_EN_MASK              (0x40U)
#define RBME_RAM_IF_CFG_H2S_EN_SHIFT             (6U)
/*! H2S_EN - Hard bit convert to soft bit enable
 *  0b0..Disable hard bit to soft bits coversion
 *  0b1..Enable hard bit to soft bits coversion
 */
#define RBME_RAM_IF_CFG_H2S_EN(x)                (((uint32_t)(((uint32_t)(x)) << RBME_RAM_IF_CFG_H2S_EN_SHIFT)) & RBME_RAM_IF_CFG_H2S_EN_MASK)

#define RBME_RAM_IF_CFG_SOFT_HD_SEL_RD_MASK      (0x100U)
#define RBME_RAM_IF_CFG_SOFT_HD_SEL_RD_SHIFT     (8U)
/*! SOFT_HD_SEL_RD - Soft and hard bit selection of write operation
 *  0b0..Hard bit selection of write operation
 *  0b1..Soft bit selection of write operation
 */
#define RBME_RAM_IF_CFG_SOFT_HD_SEL_RD(x)        (((uint32_t)(((uint32_t)(x)) << RBME_RAM_IF_CFG_SOFT_HD_SEL_RD_SHIFT)) & RBME_RAM_IF_CFG_SOFT_HD_SEL_RD_MASK)

#define RBME_RAM_IF_CFG_SOFT_HD_SEL_WR_MASK      (0x200U)
#define RBME_RAM_IF_CFG_SOFT_HD_SEL_WR_SHIFT     (9U)
/*! SOFT_HD_SEL_WR - Soft and hard bit selection of read operation
 *  0b0..Hard bit selection of read operation
 *  0b1..Soft bit selection of read operation
 */
#define RBME_RAM_IF_CFG_SOFT_HD_SEL_WR(x)        (((uint32_t)(((uint32_t)(x)) << RBME_RAM_IF_CFG_SOFT_HD_SEL_WR_SHIFT)) & RBME_RAM_IF_CFG_SOFT_HD_SEL_WR_MASK)

#define RBME_RAM_IF_CFG_WR_IRQ_MASK              (0x400U)
#define RBME_RAM_IF_CFG_WR_IRQ_SHIFT             (10U)
/*! WR_IRQ - Write to RAM complete flag
 *  0b0..Writing to RAM not complete
 *  0b1..Writing to RAM complete
 */
#define RBME_RAM_IF_CFG_WR_IRQ(x)                (((uint32_t)(((uint32_t)(x)) << RBME_RAM_IF_CFG_WR_IRQ_SHIFT)) & RBME_RAM_IF_CFG_WR_IRQ_MASK)

#define RBME_RAM_IF_CFG_RD_IRQ_MASK              (0x800U)
#define RBME_RAM_IF_CFG_RD_IRQ_SHIFT             (11U)
/*! RD_IRQ - Read to RAM complete flag
 *  0b0..Reading to RAM not complete
 *  0b1..Reading to RAM complete
 */
#define RBME_RAM_IF_CFG_RD_IRQ(x)                (((uint32_t)(((uint32_t)(x)) << RBME_RAM_IF_CFG_RD_IRQ_SHIFT)) & RBME_RAM_IF_CFG_RD_IRQ_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group RBME_Register_Masks */


/* RBME - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral RBME base address */
  #define RBME_BASE                                (0x58A06200u)
  /** Peripheral RBME base address */
  #define RBME_BASE_NS                             (0x48A06200u)
  /** Peripheral RBME base pointer */
  #define RBME                                     ((RBME_Type *)RBME_BASE)
  /** Peripheral RBME base pointer */
  #define RBME_NS                                  ((RBME_Type *)RBME_BASE_NS)
  /** Array initializer of RBME peripheral base addresses */
  #define RBME_BASE_ADDRS                          { RBME_BASE }
  /** Array initializer of RBME peripheral base pointers */
  #define RBME_BASE_PTRS                           { RBME }
  /** Array initializer of RBME peripheral base addresses */
  #define RBME_BASE_ADDRS_NS                       { RBME_BASE_NS }
  /** Array initializer of RBME peripheral base pointers */
  #define RBME_BASE_PTRS_NS                        { RBME_NS }
#else
  /** Peripheral RBME base address */
  #define RBME_BASE                                (0x48A06200u)
  /** Peripheral RBME base pointer */
  #define RBME                                     ((RBME_Type *)RBME_BASE)
  /** Array initializer of RBME peripheral base addresses */
  #define RBME_BASE_ADDRS                          { RBME_BASE }
  /** Array initializer of RBME peripheral base pointers */
  #define RBME_BASE_PTRS                           { RBME }
#endif

/*!
 * @}
 */ /* end of group RBME_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- REGFILE Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup REGFILE_Peripheral_Access_Layer REGFILE Peripheral Access Layer
 * @{
 */

/** REGFILE - Register Layout Typedef */
typedef struct {
  __IO uint32_t REG[8];                            /**< Register File Register 0..Register File Register 7, array offset: 0x0, array step: 0x4 */
       uint8_t RESERVED_0[224];
  __IO uint32_t WAR;                               /**< Write Access Register, offset: 0x100 */
  __IO uint32_t RAR;                               /**< Read Access Register, offset: 0x104 */
} REGFILE_Type;

/* ----------------------------------------------------------------------------
   -- REGFILE Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup REGFILE_Register_Masks REGFILE Register Masks
 * @{
 */

/*! @name REG - Register File Register 0..Register File Register 7 */
/*! @{ */

#define REGFILE_REG_REG_MASK                     (0xFFFFFFFFU)
#define REGFILE_REG_REG_SHIFT                    (0U)
/*! REG - Register File
 */
#define REGFILE_REG_REG(x)                       (((uint32_t)(((uint32_t)(x)) << REGFILE_REG_REG_SHIFT)) & REGFILE_REG_REG_MASK)
/*! @} */

/* The count of REGFILE_REG */
#define REGFILE_REG_COUNT                        (8U)

/*! @name WAR - Write Access Register */
/*! @{ */

#define REGFILE_WAR_WAR0_MASK                    (0x1U)
#define REGFILE_WAR_WAR0_SHIFT                   (0U)
/*! WAR0 - REG0 Register Write Access
 *  0b0..Not allow to write to the REGn register and WARn field until next reset.
 *  0b1..Allow to write to the REGn register and WAR0 field.
 */
#define REGFILE_WAR_WAR0(x)                      (((uint32_t)(((uint32_t)(x)) << REGFILE_WAR_WAR0_SHIFT)) & REGFILE_WAR_WAR0_MASK)

#define REGFILE_WAR_WAR1_MASK                    (0x2U)
#define REGFILE_WAR_WAR1_SHIFT                   (1U)
/*! WAR1 - REG1 Register Write Access
 *  0b0..Not allow to write to the REGn register and WARn field until next reset.
 *  0b1..Allow to write to the REGn register and WAR1 field.
 */
#define REGFILE_WAR_WAR1(x)                      (((uint32_t)(((uint32_t)(x)) << REGFILE_WAR_WAR1_SHIFT)) & REGFILE_WAR_WAR1_MASK)

#define REGFILE_WAR_WAR2_MASK                    (0x4U)
#define REGFILE_WAR_WAR2_SHIFT                   (2U)
/*! WAR2 - REG2 Register Write Access
 *  0b0..Not allow to write to the REGn register and WARn field until next reset.
 *  0b1..Allow to write to the REGn register and WAR2 field.
 */
#define REGFILE_WAR_WAR2(x)                      (((uint32_t)(((uint32_t)(x)) << REGFILE_WAR_WAR2_SHIFT)) & REGFILE_WAR_WAR2_MASK)

#define REGFILE_WAR_WAR3_MASK                    (0x8U)
#define REGFILE_WAR_WAR3_SHIFT                   (3U)
/*! WAR3 - REG3 Register Write Access
 *  0b0..Not allow to write to the REGn register and WARn field until next reset.
 *  0b1..Allow to write to the REGn register and WAR3 field.
 */
#define REGFILE_WAR_WAR3(x)                      (((uint32_t)(((uint32_t)(x)) << REGFILE_WAR_WAR3_SHIFT)) & REGFILE_WAR_WAR3_MASK)

#define REGFILE_WAR_WAR4_MASK                    (0x10U)
#define REGFILE_WAR_WAR4_SHIFT                   (4U)
/*! WAR4 - REG4 Register Write Access
 *  0b0..Not allow to write to the REGn register and WARn field until next reset.
 *  0b1..Allow to write to the REGn register and WAR4 field.
 */
#define REGFILE_WAR_WAR4(x)                      (((uint32_t)(((uint32_t)(x)) << REGFILE_WAR_WAR4_SHIFT)) & REGFILE_WAR_WAR4_MASK)

#define REGFILE_WAR_WAR5_MASK                    (0x20U)
#define REGFILE_WAR_WAR5_SHIFT                   (5U)
/*! WAR5 - REG5 Register Write Access
 *  0b0..Not allow to write to the REGn register and WARn field until next reset.
 *  0b1..Allow to write to the REGn register and WAR5 field.
 */
#define REGFILE_WAR_WAR5(x)                      (((uint32_t)(((uint32_t)(x)) << REGFILE_WAR_WAR5_SHIFT)) & REGFILE_WAR_WAR5_MASK)

#define REGFILE_WAR_WAR6_MASK                    (0x40U)
#define REGFILE_WAR_WAR6_SHIFT                   (6U)
/*! WAR6 - REG6 Register Write Access
 *  0b0..Not allow to write to the REGn register and WARn field until next reset.
 *  0b1..Allow to write to the REGn register and WAR6 field.
 */
#define REGFILE_WAR_WAR6(x)                      (((uint32_t)(((uint32_t)(x)) << REGFILE_WAR_WAR6_SHIFT)) & REGFILE_WAR_WAR6_MASK)

#define REGFILE_WAR_WAR7_MASK                    (0x80U)
#define REGFILE_WAR_WAR7_SHIFT                   (7U)
/*! WAR7 - REG7 Register Write Access
 *  0b0..Not allow to write to the REGn register and WARn field until next reset.
 *  0b1..Allow to write to the REGn register and WAR7 field.
 */
#define REGFILE_WAR_WAR7(x)                      (((uint32_t)(((uint32_t)(x)) << REGFILE_WAR_WAR7_SHIFT)) & REGFILE_WAR_WAR7_MASK)
/*! @} */

/*! @name RAR - Read Access Register */
/*! @{ */

#define REGFILE_RAR_RAR0_MASK                    (0x1U)
#define REGFILE_RAR_RAR0_SHIFT                   (0U)
/*! RAR0 - REG0 Register Read Access
 *  0b0..Not allow to read the REGn register until next reset. Reading corresponding REGn register returns all 0.
 *  0b1..Allow to read the REGn register.
 */
#define REGFILE_RAR_RAR0(x)                      (((uint32_t)(((uint32_t)(x)) << REGFILE_RAR_RAR0_SHIFT)) & REGFILE_RAR_RAR0_MASK)

#define REGFILE_RAR_RAR1_MASK                    (0x2U)
#define REGFILE_RAR_RAR1_SHIFT                   (1U)
/*! RAR1 - REG1 Register Read Access
 *  0b0..Not allow to read the REGn register until next reset. Reading corresponding REGn register returns all 0.
 *  0b1..Allow to read the REGn register.
 */
#define REGFILE_RAR_RAR1(x)                      (((uint32_t)(((uint32_t)(x)) << REGFILE_RAR_RAR1_SHIFT)) & REGFILE_RAR_RAR1_MASK)

#define REGFILE_RAR_RAR2_MASK                    (0x4U)
#define REGFILE_RAR_RAR2_SHIFT                   (2U)
/*! RAR2 - REG2 Register Read Access
 *  0b0..Not allow to read the REGn register until next reset. Reading corresponding REGn register returns all 0.
 *  0b1..Allow to read the REGn register.
 */
#define REGFILE_RAR_RAR2(x)                      (((uint32_t)(((uint32_t)(x)) << REGFILE_RAR_RAR2_SHIFT)) & REGFILE_RAR_RAR2_MASK)

#define REGFILE_RAR_RAR3_MASK                    (0x8U)
#define REGFILE_RAR_RAR3_SHIFT                   (3U)
/*! RAR3 - REG3 Register Read Access
 *  0b0..Not allow to read the REGn register until next reset. Reading corresponding REGn register returns all 0.
 *  0b1..Allow to read the REGn register.
 */
#define REGFILE_RAR_RAR3(x)                      (((uint32_t)(((uint32_t)(x)) << REGFILE_RAR_RAR3_SHIFT)) & REGFILE_RAR_RAR3_MASK)

#define REGFILE_RAR_RAR4_MASK                    (0x10U)
#define REGFILE_RAR_RAR4_SHIFT                   (4U)
/*! RAR4 - REG4 Register Read Access
 *  0b0..Not allow to read the REGn register until next reset. Reading corresponding REGn register returns all 0.
 *  0b1..Allow to read the REGn register.
 */
#define REGFILE_RAR_RAR4(x)                      (((uint32_t)(((uint32_t)(x)) << REGFILE_RAR_RAR4_SHIFT)) & REGFILE_RAR_RAR4_MASK)

#define REGFILE_RAR_RAR5_MASK                    (0x20U)
#define REGFILE_RAR_RAR5_SHIFT                   (5U)
/*! RAR5 - REG5 Register Read Access
 *  0b0..Not allow to read the REGn register until next reset. Reading corresponding REGn register returns all 0.
 *  0b1..Allow to read the REGn register.
 */
#define REGFILE_RAR_RAR5(x)                      (((uint32_t)(((uint32_t)(x)) << REGFILE_RAR_RAR5_SHIFT)) & REGFILE_RAR_RAR5_MASK)

#define REGFILE_RAR_RAR6_MASK                    (0x40U)
#define REGFILE_RAR_RAR6_SHIFT                   (6U)
/*! RAR6 - REG6 Register Read Access
 *  0b0..Not allow to read the REGn register until next reset. Reading corresponding REGn register returns all 0.
 *  0b1..Allow to read the REGn register.
 */
#define REGFILE_RAR_RAR6(x)                      (((uint32_t)(((uint32_t)(x)) << REGFILE_RAR_RAR6_SHIFT)) & REGFILE_RAR_RAR6_MASK)

#define REGFILE_RAR_RAR7_MASK                    (0x80U)
#define REGFILE_RAR_RAR7_SHIFT                   (7U)
/*! RAR7 - REG7 Register Read Access
 *  0b0..Not allow to read the REGn register until next reset. Reading corresponding REGn register returns all 0.
 *  0b1..Allow to read the REGn register.
 */
#define REGFILE_RAR_RAR7(x)                      (((uint32_t)(((uint32_t)(x)) << REGFILE_RAR_RAR7_SHIFT)) & REGFILE_RAR_RAR7_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group REGFILE_Register_Masks */


/* REGFILE - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral REGFILE0 base address */
  #define REGFILE0_BASE                            (0x50021000u)
  /** Peripheral REGFILE0 base address */
  #define REGFILE0_BASE_NS                         (0x40021000u)
  /** Peripheral REGFILE0 base pointer */
  #define REGFILE0                                 ((REGFILE_Type *)REGFILE0_BASE)
  /** Peripheral REGFILE0 base pointer */
  #define REGFILE0_NS                              ((REGFILE_Type *)REGFILE0_BASE_NS)
  /** Peripheral REGFILE1 base address */
  #define REGFILE1_BASE                            (0x50022000u)
  /** Peripheral REGFILE1 base address */
  #define REGFILE1_BASE_NS                         (0x40022000u)
  /** Peripheral REGFILE1 base pointer */
  #define REGFILE1                                 ((REGFILE_Type *)REGFILE1_BASE)
  /** Peripheral REGFILE1 base pointer */
  #define REGFILE1_NS                              ((REGFILE_Type *)REGFILE1_BASE_NS)
  /** Array initializer of REGFILE peripheral base addresses */
  #define REGFILE_BASE_ADDRS                       { REGFILE0_BASE, REGFILE1_BASE }
  /** Array initializer of REGFILE peripheral base pointers */
  #define REGFILE_BASE_PTRS                        { REGFILE0, REGFILE1 }
  /** Array initializer of REGFILE peripheral base addresses */
  #define REGFILE_BASE_ADDRS_NS                    { REGFILE0_BASE_NS, REGFILE1_BASE_NS }
  /** Array initializer of REGFILE peripheral base pointers */
  #define REGFILE_BASE_PTRS_NS                     { REGFILE0_NS, REGFILE1_NS }
#else
  /** Peripheral REGFILE0 base address */
  #define REGFILE0_BASE                            (0x40021000u)
  /** Peripheral REGFILE0 base pointer */
  #define REGFILE0                                 ((REGFILE_Type *)REGFILE0_BASE)
  /** Peripheral REGFILE1 base address */
  #define REGFILE1_BASE                            (0x40022000u)
  /** Peripheral REGFILE1 base pointer */
  #define REGFILE1                                 ((REGFILE_Type *)REGFILE1_BASE)
  /** Array initializer of REGFILE peripheral base addresses */
  #define REGFILE_BASE_ADDRS                       { REGFILE0_BASE, REGFILE1_BASE }
  /** Array initializer of REGFILE peripheral base pointers */
  #define REGFILE_BASE_PTRS                        { REGFILE0, REGFILE1 }
#endif

/*!
 * @}
 */ /* end of group REGFILE_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- RFMC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup RFMC_Peripheral_Access_Layer RFMC Peripheral Access Layer
 * @{
 */

/** RFMC - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< RFMC Version ID Register, offset: 0x0 */
  __I  uint32_t PARAM;                             /**< RFMC Parameter Register, offset: 0x4 */
  __IO uint32_t CTRL;                              /**< RFMC Control Register, offset: 0x8 */
  __IO uint32_t XO_CTRL;                           /**< XO Control Register, offset: 0xC */
  __IO uint32_t XO_STAT;                           /**< XO Status Register, offset: 0x10 */
  __IO uint32_t XO_TEST;                           /**< XO Test Register, offset: 0x14 */
  __IO uint32_t RF2P4GHZ_CTRL;                     /**< 2.4GHz Radio Control Register, offset: 0x18 */
  __IO uint32_t RF2P4GHZ_STAT;                     /**< 2.4GHz Radio Status Register, offset: 0x1C */
  __IO uint32_t RF2P4GHZ_COEXT;                    /**< 2.4GHz Radio Coexistence Register, offset: 0x20 */
  __IO uint32_t RF2P4GHZ_TIMER;                    /**< 2.4GHz TIMER Register, offset: 0x24 */
  __I  uint32_t RF2P4GHZ_WOR1;                     /**< 2.4GHz WOR Register 1, offset: 0x28 */
  __IO uint32_t RF2P4GHZ_WOR2;                     /**< 2.4GHz WOR Register 2, offset: 0x2C */
  __I  uint32_t RF2P4GHZ_MAN1;                     /**< 2.4GHz MAN Register 1, offset: 0x30 */
  __IO uint32_t RF2P4GHZ_MAN2;                     /**< 2.4GHz MAN Register 2, offset: 0x34 */
  __I  uint32_t RF2P4GHZ_MAN3;                     /**< 2.4GHz MAN Register 3, offset: 0x38 */
  __I  uint32_t RF2P4GHZ_MAN4;                     /**< 2.4GHz MAN Register 4, offset: 0x3C */
} RFMC_Type;

/* ----------------------------------------------------------------------------
   -- RFMC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup RFMC_Register_Masks RFMC Register Masks
 * @{
 */

/*! @name VERID - RFMC Version ID Register */
/*! @{ */

#define RFMC_VERID_RADIO_ID_MASK                 (0xFFFFU)
#define RFMC_VERID_RADIO_ID_SHIFT                (0U)
/*! RADIO_ID - Radio Identification Number
 */
#define RFMC_VERID_RADIO_ID(x)                   (((uint32_t)(((uint32_t)(x)) << RFMC_VERID_RADIO_ID_SHIFT)) & RFMC_VERID_RADIO_ID_MASK)

#define RFMC_VERID_MINOR_MASK                    (0xFF0000U)
#define RFMC_VERID_MINOR_SHIFT                   (16U)
/*! MINOR - Minor RFMC Version Number
 */
#define RFMC_VERID_MINOR(x)                      (((uint32_t)(((uint32_t)(x)) << RFMC_VERID_MINOR_SHIFT)) & RFMC_VERID_MINOR_MASK)

#define RFMC_VERID_MAJOR_MASK                    (0xFF000000U)
#define RFMC_VERID_MAJOR_SHIFT                   (24U)
/*! MAJOR - Major RFMC Version Number
 */
#define RFMC_VERID_MAJOR(x)                      (((uint32_t)(((uint32_t)(x)) << RFMC_VERID_MAJOR_SHIFT)) & RFMC_VERID_MAJOR_MASK)
/*! @} */

/*! @name PARAM - RFMC Parameter Register */
/*! @{ */

#define RFMC_PARAM_RF2p4GHz_EN_MASK              (0x1U)
#define RFMC_PARAM_RF2p4GHz_EN_SHIFT             (0U)
/*! RF2p4GHz_EN
 *  0b0..2.4GHz radio disabled
 *  0b1..2.4GHz radio enabled
 */
#define RFMC_PARAM_RF2p4GHz_EN(x)                (((uint32_t)(((uint32_t)(x)) << RFMC_PARAM_RF2p4GHz_EN_SHIFT)) & RFMC_PARAM_RF2p4GHz_EN_MASK)
/*! @} */

/*! @name CTRL - RFMC Control Register */
/*! @{ */

#define RFMC_CTRL_RST_MSK_MASK                   (0x40000000U)
#define RFMC_CTRL_RST_MSK_SHIFT                  (30U)
/*! RST_MSK - Reset Mask
 */
#define RFMC_CTRL_RST_MSK(x)                     (((uint32_t)(((uint32_t)(x)) << RFMC_CTRL_RST_MSK_SHIFT)) & RFMC_CTRL_RST_MSK_MASK)

#define RFMC_CTRL_RFMC_RST_MASK                  (0x80000000U)
#define RFMC_CTRL_RFMC_RST_SHIFT                 (31U)
/*! RFMC_RST - S/W System Reset for RFMC
 *  0b0..Release the RFMC from reset
 *  0b1..Hold the RFMC in reset
 */
#define RFMC_CTRL_RFMC_RST(x)                    (((uint32_t)(((uint32_t)(x)) << RFMC_CTRL_RFMC_RST_SHIFT)) & RFMC_CTRL_RFMC_RST_MASK)
/*! @} */

/*! @name XO_CTRL - XO Control Register */
/*! @{ */

#define RFMC_XO_CTRL_RDY_IE_MASK                 (0x1U)
#define RFMC_XO_CTRL_RDY_IE_SHIFT                (0U)
/*! RDY_IE - XTAL Ready Interrupt Enable
 *  0b0..XTAL ready interrupt disabled
 *  0b1..XTAL ready interrupt enabled
 */
#define RFMC_XO_CTRL_RDY_IE(x)                   (((uint32_t)(((uint32_t)(x)) << RFMC_XO_CTRL_RDY_IE_SHIFT)) & RFMC_XO_CTRL_RDY_IE_MASK)

#define RFMC_XO_CTRL_INT_IE_MASK                 (0x2U)
#define RFMC_XO_CTRL_INT_IE_SHIFT                (1U)
/*! INT_IE - XO Internal Request Interrupt Enable
 *  0b0..XO internal request interrupt disabled
 *  0b1..XO internal request interrupt enabled
 */
#define RFMC_XO_CTRL_INT_IE(x)                   (((uint32_t)(((uint32_t)(x)) << RFMC_XO_CTRL_INT_IE_SHIFT)) & RFMC_XO_CTRL_INT_IE_MASK)

#define RFMC_XO_CTRL_EXT_IE_MASK                 (0x4U)
#define RFMC_XO_CTRL_EXT_IE_SHIFT                (2U)
/*! EXT_IE - XO External Request Interrupt Enable
 *  0b0..XO external request interrupt disabled
 *  0b1..XO external request interrupt enabled
 */
#define RFMC_XO_CTRL_EXT_IE(x)                   (((uint32_t)(((uint32_t)(x)) << RFMC_XO_CTRL_EXT_IE_SHIFT)) & RFMC_XO_CTRL_EXT_IE_MASK)

#define RFMC_XO_CTRL_XTAL_OUT_EN_MASK            (0x10U)
#define RFMC_XO_CTRL_XTAL_OUT_EN_SHIFT           (4U)
/*! XTAL_OUT_EN - XTAL_OUT Output Pin Enable
 *  0b0..XTAL_OUT output disabled
 *  0b1..XTAL_OUT output enabled
 */
#define RFMC_XO_CTRL_XTAL_OUT_EN(x)              (((uint32_t)(((uint32_t)(x)) << RFMC_XO_CTRL_XTAL_OUT_EN_SHIFT)) & RFMC_XO_CTRL_XTAL_OUT_EN_MASK)

#define RFMC_XO_CTRL_XTAL_REQ_OBE_MASK           (0x20U)
#define RFMC_XO_CTRL_XTAL_REQ_OBE_SHIFT          (5U)
/*! XTAL_REQ_OBE - XTAL_REQ Output Pin Enable
 *  0b0..XTAL_REQ output pin disabled
 *  0b1..XTAL_REQ output pin enabled
 */
#define RFMC_XO_CTRL_XTAL_REQ_OBE(x)             (((uint32_t)(((uint32_t)(x)) << RFMC_XO_CTRL_XTAL_REQ_OBE_SHIFT)) & RFMC_XO_CTRL_XTAL_REQ_OBE_MASK)

#define RFMC_XO_CTRL_XTAL_EN_IBE_MASK            (0x40U)
#define RFMC_XO_CTRL_XTAL_EN_IBE_SHIFT           (6U)
/*! XTAL_EN_IBE - XTAL_OUT_EN Input Pin Enable
 *  0b0..XTAL_OUT_EN input pin disabled
 *  0b1..XTAL_OUT_EN input pin enabled
 */
#define RFMC_XO_CTRL_XTAL_EN_IBE(x)              (((uint32_t)(((uint32_t)(x)) << RFMC_XO_CTRL_XTAL_EN_IBE_SHIFT)) & RFMC_XO_CTRL_XTAL_EN_IBE_MASK)

#define RFMC_XO_CTRL_WKUP_OFFSET_MASK            (0x3F00U)
#define RFMC_XO_CTRL_WKUP_OFFSET_SHIFT           (8U)
/*! WKUP_OFFSET - XO Wakeup Offset
 */
#define RFMC_XO_CTRL_WKUP_OFFSET(x)              (((uint32_t)(((uint32_t)(x)) << RFMC_XO_CTRL_WKUP_OFFSET_SHIFT)) & RFMC_XO_CTRL_WKUP_OFFSET_MASK)

#define RFMC_XO_CTRL_RDY_CNT_MASK                (0x30000U)
#define RFMC_XO_CTRL_RDY_CNT_SHIFT               (16U)
/*! RDY_CNT - XTAL Ready Count
 *  0b00..1024
 *  0b01..2048
 *  0b10..4096
 *  0b11..8192
 */
#define RFMC_XO_CTRL_RDY_CNT(x)                  (((uint32_t)(((uint32_t)(x)) << RFMC_XO_CTRL_RDY_CNT_SHIFT)) & RFMC_XO_CTRL_RDY_CNT_MASK)

#define RFMC_XO_CTRL_RDY_CNT_OFF_MASK            (0x40000U)
#define RFMC_XO_CTRL_RDY_CNT_OFF_SHIFT           (18U)
/*! RDY_CNT_OFF - XTAL Ready Count Disable
 *  0b0..XTAL Ready Count Enabled
 *  0b1..XTAL Ready Count Disabled
 */
#define RFMC_XO_CTRL_RDY_CNT_OFF(x)              (((uint32_t)(((uint32_t)(x)) << RFMC_XO_CTRL_RDY_CNT_OFF_SHIFT)) & RFMC_XO_CTRL_RDY_CNT_OFF_MASK)

#define RFMC_XO_CTRL_XTAL_OUT_INV_MASK           (0x80000U)
#define RFMC_XO_CTRL_XTAL_OUT_INV_SHIFT          (19U)
/*! XTAL_OUT_INV - XO Clock Output Invert
 *  0b0..XTAL_OUT not inverted
 *  0b1..XTAL_OUT inverted
 */
#define RFMC_XO_CTRL_XTAL_OUT_INV(x)             (((uint32_t)(((uint32_t)(x)) << RFMC_XO_CTRL_XTAL_OUT_INV_SHIFT)) & RFMC_XO_CTRL_XTAL_OUT_INV_MASK)

#define RFMC_XO_CTRL_LDO_BYPASS_MASK             (0x100000U)
#define RFMC_XO_CTRL_LDO_BYPASS_SHIFT            (20U)
/*! LDO_BYPASS - XO LDO Bypass
 */
#define RFMC_XO_CTRL_LDO_BYPASS(x)               (((uint32_t)(((uint32_t)(x)) << RFMC_XO_CTRL_LDO_BYPASS_SHIFT)) & RFMC_XO_CTRL_LDO_BYPASS_MASK)

#define RFMC_XO_CTRL_EXT_MODE_MASK               (0x200000U)
#define RFMC_XO_CTRL_EXT_MODE_SHIFT              (21U)
/*! EXT_MODE - External Clock Mode
 *  0b0..DC coupled external clock mode (amplifier powered down).
 *  0b1..AC coupled external clock mode or crystal mode (amplifier powered up).
 */
#define RFMC_XO_CTRL_EXT_MODE(x)                 (((uint32_t)(((uint32_t)(x)) << RFMC_XO_CTRL_EXT_MODE_SHIFT)) & RFMC_XO_CTRL_EXT_MODE_MASK)

#define RFMC_XO_CTRL_XTAL_RDY_OVR_EN_MASK        (0x400000U)
#define RFMC_XO_CTRL_XTAL_RDY_OVR_EN_SHIFT       (22U)
/*! XTAL_RDY_OVR_EN - XTAL Ready Override Enable
 */
#define RFMC_XO_CTRL_XTAL_RDY_OVR_EN(x)          (((uint32_t)(((uint32_t)(x)) << RFMC_XO_CTRL_XTAL_RDY_OVR_EN_SHIFT)) & RFMC_XO_CTRL_XTAL_RDY_OVR_EN_MASK)

#define RFMC_XO_CTRL_XTAL_RDY_OVR_MASK           (0x800000U)
#define RFMC_XO_CTRL_XTAL_RDY_OVR_SHIFT          (23U)
/*! XTAL_RDY_OVR - XTAL Ready Override
 */
#define RFMC_XO_CTRL_XTAL_RDY_OVR(x)             (((uint32_t)(((uint32_t)(x)) << RFMC_XO_CTRL_XTAL_RDY_OVR_SHIFT)) & RFMC_XO_CTRL_XTAL_RDY_OVR_MASK)

#define RFMC_XO_CTRL_SPARE_MASK                  (0xF000000U)
#define RFMC_XO_CTRL_SPARE_SHIFT                 (24U)
/*! SPARE - XO Spare Registers
 */
#define RFMC_XO_CTRL_SPARE(x)                    (((uint32_t)(((uint32_t)(x)) << RFMC_XO_CTRL_SPARE_SHIFT)) & RFMC_XO_CTRL_SPARE_MASK)

#define RFMC_XO_CTRL_XO_LDO_OVR_MASK             (0x10000000U)
#define RFMC_XO_CTRL_XO_LDO_OVR_SHIFT            (28U)
/*! XO_LDO_OVR - XO LDO Enable Override
 *  0b0..XO LDO enable not overridden
 *  0b1..XO LDO enable overridden by XO_LDO_EN bit
 */
#define RFMC_XO_CTRL_XO_LDO_OVR(x)               (((uint32_t)(((uint32_t)(x)) << RFMC_XO_CTRL_XO_LDO_OVR_SHIFT)) & RFMC_XO_CTRL_XO_LDO_OVR_MASK)

#define RFMC_XO_CTRL_XO_LDO_EN_MASK              (0x20000000U)
#define RFMC_XO_CTRL_XO_LDO_EN_SHIFT             (29U)
/*! XO_LDO_EN - XO LDO Enable
 *  0b0..XO LDO disabled
 *  0b1..XO LDO enabled
 */
#define RFMC_XO_CTRL_XO_LDO_EN(x)                (((uint32_t)(((uint32_t)(x)) << RFMC_XO_CTRL_XO_LDO_EN_SHIFT)) & RFMC_XO_CTRL_XO_LDO_EN_MASK)

#define RFMC_XO_CTRL_XO_ANA_OVR_MASK             (0x40000000U)
#define RFMC_XO_CTRL_XO_ANA_OVR_SHIFT            (30U)
/*! XO_ANA_OVR - XO Analog Enable Override
 *  0b0..XO analog enable not overridden
 *  0b1..XO analog enable overridden by XO_ANA_EN bit
 */
#define RFMC_XO_CTRL_XO_ANA_OVR(x)               (((uint32_t)(((uint32_t)(x)) << RFMC_XO_CTRL_XO_ANA_OVR_SHIFT)) & RFMC_XO_CTRL_XO_ANA_OVR_MASK)

#define RFMC_XO_CTRL_XO_ANA_EN_MASK              (0x80000000U)
#define RFMC_XO_CTRL_XO_ANA_EN_SHIFT             (31U)
/*! XO_ANA_EN - XO Analog Enable
 *  0b0..XO analog disabled
 *  0b1..XO analog enabled
 */
#define RFMC_XO_CTRL_XO_ANA_EN(x)                (((uint32_t)(((uint32_t)(x)) << RFMC_XO_CTRL_XO_ANA_EN_SHIFT)) & RFMC_XO_CTRL_XO_ANA_EN_MASK)
/*! @} */

/*! @name XO_STAT - XO Status Register */
/*! @{ */

#define RFMC_XO_STAT_RDY_FLAG_MASK               (0x1U)
#define RFMC_XO_STAT_RDY_FLAG_SHIFT              (0U)
/*! RDY_FLAG - XTAL Ready Flag
 */
#define RFMC_XO_STAT_RDY_FLAG(x)                 (((uint32_t)(((uint32_t)(x)) << RFMC_XO_STAT_RDY_FLAG_SHIFT)) & RFMC_XO_STAT_RDY_FLAG_MASK)

#define RFMC_XO_STAT_INT_FLAG_MASK               (0x2U)
#define RFMC_XO_STAT_INT_FLAG_SHIFT              (1U)
/*! INT_FLAG - XO Internal Request Flag
 */
#define RFMC_XO_STAT_INT_FLAG(x)                 (((uint32_t)(((uint32_t)(x)) << RFMC_XO_STAT_INT_FLAG_SHIFT)) & RFMC_XO_STAT_INT_FLAG_MASK)

#define RFMC_XO_STAT_EXT_FLAG_MASK               (0x4U)
#define RFMC_XO_STAT_EXT_FLAG_SHIFT              (2U)
/*! EXT_FLAG - XO External Request Flag
 */
#define RFMC_XO_STAT_EXT_FLAG(x)                 (((uint32_t)(((uint32_t)(x)) << RFMC_XO_STAT_EXT_FLAG_SHIFT)) & RFMC_XO_STAT_EXT_FLAG_MASK)

#define RFMC_XO_STAT_XTAL_RDY_MASK               (0x10U)
#define RFMC_XO_STAT_XTAL_RDY_SHIFT              (4U)
/*! XTAL_RDY - XTAL Ready
 */
#define RFMC_XO_STAT_XTAL_RDY(x)                 (((uint32_t)(((uint32_t)(x)) << RFMC_XO_STAT_XTAL_RDY_SHIFT)) & RFMC_XO_STAT_XTAL_RDY_MASK)

#define RFMC_XO_STAT_XO_EN_MASK                  (0x20U)
#define RFMC_XO_STAT_XO_EN_SHIFT                 (5U)
/*! XO_EN - XO_EN
 */
#define RFMC_XO_STAT_XO_EN(x)                    (((uint32_t)(((uint32_t)(x)) << RFMC_XO_STAT_XO_EN_SHIFT)) & RFMC_XO_STAT_XO_EN_MASK)
/*! @} */

/*! @name XO_TEST - XO Test Register */
/*! @{ */

#define RFMC_XO_TEST_ISEL_MASK                   (0xFU)
#define RFMC_XO_TEST_ISEL_SHIFT                  (0U)
/*! ISEL - XO Amplifier Current Select
 *  0b0000..40uA (min)
 *  0b0001..80uA
 *  0b0101..240uA (default)
 *  0b1111..640uA (max)
 */
#define RFMC_XO_TEST_ISEL(x)                     (((uint32_t)(((uint32_t)(x)) << RFMC_XO_TEST_ISEL_SHIFT)) & RFMC_XO_TEST_ISEL_MASK)

#define RFMC_XO_TEST_CDAC_MASK                   (0x3F0U)
#define RFMC_XO_TEST_CDAC_SHIFT                  (4U)
/*! CDAC - XO On-chip Load Capacitor Trim
 *  0b000000..6pF
 *  0b111111..11pF
 */
#define RFMC_XO_TEST_CDAC(x)                     (((uint32_t)(((uint32_t)(x)) << RFMC_XO_TEST_CDAC_SHIFT)) & RFMC_XO_TEST_CDAC_MASK)

#define RFMC_XO_TEST_CAP_OFF_MASK                (0x400U)
#define RFMC_XO_TEST_CAP_OFF_SHIFT               (10U)
/*! CAP_OFF - XO Load Capacitor Disable
 */
#define RFMC_XO_TEST_CAP_OFF(x)                  (((uint32_t)(((uint32_t)(x)) << RFMC_XO_TEST_CAP_OFF_SHIFT)) & RFMC_XO_TEST_CAP_OFF_MASK)

#define RFMC_XO_TEST_AUX_PD_MASK                 (0x800U)
#define RFMC_XO_TEST_AUX_PD_SHIFT                (11U)
/*! AUX_PD - XO CLK_AUX_DRV Powerdown
 */
#define RFMC_XO_TEST_AUX_PD(x)                   (((uint32_t)(((uint32_t)(x)) << RFMC_XO_TEST_AUX_PD_SHIFT)) & RFMC_XO_TEST_AUX_PD_MASK)

#define RFMC_XO_TEST_AMP_FORCE_MASK              (0x1000U)
#define RFMC_XO_TEST_AMP_FORCE_SHIFT             (12U)
/*! AMP_FORCE - XO Amplifier Force PTAT Startup
 */
#define RFMC_XO_TEST_AMP_FORCE(x)                (((uint32_t)(((uint32_t)(x)) << RFMC_XO_TEST_AMP_FORCE_SHIFT)) & RFMC_XO_TEST_AMP_FORCE_MASK)

#define RFMC_XO_TEST_DYN_ISEL_MASK               (0x2000U)
#define RFMC_XO_TEST_DYN_ISEL_SHIFT              (13U)
/*! DYN_ISEL - XO Amplifier: enable current switching during startup
 */
#define RFMC_XO_TEST_DYN_ISEL(x)                 (((uint32_t)(((uint32_t)(x)) << RFMC_XO_TEST_DYN_ISEL_SHIFT)) & RFMC_XO_TEST_DYN_ISEL_MASK)

#define RFMC_XO_TEST_DYN_CAP_MASK                (0x4000U)
#define RFMC_XO_TEST_DYN_CAP_SHIFT               (14U)
/*! DYN_CAP - XO On-chip Load Capacitor: enable switching during startup
 */
#define RFMC_XO_TEST_DYN_CAP(x)                  (((uint32_t)(((uint32_t)(x)) << RFMC_XO_TEST_DYN_CAP_SHIFT)) & RFMC_XO_TEST_DYN_CAP_MASK)

#define RFMC_XO_TEST_LDO_TRIM_MASK               (0x30000U)
#define RFMC_XO_TEST_LDO_TRIM_SHIFT              (16U)
/*! LDO_TRIM - XO LDO Output Voltage Trim
 *  0b00..0.92V
 *  0b01..0.885V
 *  0b10..0.955V
 *  0b11..1.011V
 */
#define RFMC_XO_TEST_LDO_TRIM(x)                 (((uint32_t)(((uint32_t)(x)) << RFMC_XO_TEST_LDO_TRIM_SHIFT)) & RFMC_XO_TEST_LDO_TRIM_MASK)

#define RFMC_XO_TEST_LDO_BUMP_MASK               (0xC0000U)
#define RFMC_XO_TEST_LDO_BUMP_SHIFT              (18U)
/*! LDO_BUMP - XO LDO PTAT Current Bump
 *  0b00..PTAT current bump default
 *  0b01..PTAT current boost: +30%
 */
#define RFMC_XO_TEST_LDO_BUMP(x)                 (((uint32_t)(((uint32_t)(x)) << RFMC_XO_TEST_LDO_BUMP_SHIFT)) & RFMC_XO_TEST_LDO_BUMP_MASK)

#define RFMC_XO_TEST_LDO_FORCE_MASK              (0x100000U)
#define RFMC_XO_TEST_LDO_FORCE_SHIFT             (20U)
/*! LDO_FORCE - XO LDO Force PTAT Startup
 */
#define RFMC_XO_TEST_LDO_FORCE(x)                (((uint32_t)(((uint32_t)(x)) << RFMC_XO_TEST_LDO_FORCE_SHIFT)) & RFMC_XO_TEST_LDO_FORCE_MASK)
/*! @} */

/*! @name RF2P4GHZ_CTRL - 2.4GHz Radio Control Register */
/*! @{ */

#define RFMC_RF2P4GHZ_CTRL_WOR_WKUP_IE_MASK      (0x1U)
#define RFMC_RF2P4GHZ_CTRL_WOR_WKUP_IE_SHIFT     (0U)
/*! WOR_WKUP_IE - WOR Wakeup Interrupt Enable
 *  0b0..WOR wakeup interrupt disabled
 *  0b1..WOR wakeup interrupt enabled
 */
#define RFMC_RF2P4GHZ_CTRL_WOR_WKUP_IE(x)        (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_CTRL_WOR_WKUP_IE_SHIFT)) & RFMC_RF2P4GHZ_CTRL_WOR_WKUP_IE_MASK)

#define RFMC_RF2P4GHZ_CTRL_MAN_WKUP_IE_MASK      (0x2U)
#define RFMC_RF2P4GHZ_CTRL_MAN_WKUP_IE_SHIFT     (1U)
/*! MAN_WKUP_IE - MAN Wakeup Interrupt Enable
 *  0b0..MAN wakeup interrupt disabled
 *  0b1..MAN wakeup interrupt enabled
 */
#define RFMC_RF2P4GHZ_CTRL_MAN_WKUP_IE(x)        (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_CTRL_MAN_WKUP_IE_SHIFT)) & RFMC_RF2P4GHZ_CTRL_MAN_WKUP_IE_MASK)

#define RFMC_RF2P4GHZ_CTRL_BLE_WKUP_IE_MASK      (0x4U)
#define RFMC_RF2P4GHZ_CTRL_BLE_WKUP_IE_SHIFT     (2U)
/*! BLE_WKUP_IE - Bluetooth LE Wakeup Interrupt Enable
 *  0b0..Bluetooth LE wakeup interrupt disabled
 *  0b1..Bluetooth LE wakeup interrupt enabled
 */
#define RFMC_RF2P4GHZ_CTRL_BLE_WKUP_IE(x)        (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_CTRL_BLE_WKUP_IE_SHIFT)) & RFMC_RF2P4GHZ_CTRL_BLE_WKUP_IE_MASK)

#define RFMC_RF2P4GHZ_CTRL_RFACT_IE_MASK         (0x8U)
#define RFMC_RF2P4GHZ_CTRL_RFACT_IE_SHIFT        (3U)
/*! RFACT_IE - RF_ACTIVE Interrupt Enable
 *  0b0..RF_ACTIVE interrupt disabled
 *  0b1..RF_ACTIVE interrupt enabled
 */
#define RFMC_RF2P4GHZ_CTRL_RFACT_IE(x)           (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_CTRL_RFACT_IE_SHIFT)) & RFMC_RF2P4GHZ_CTRL_RFACT_IE_MASK)

#define RFMC_RF2P4GHZ_CTRL_LP_WKUP_IE_MASK       (0x10U)
#define RFMC_RF2P4GHZ_CTRL_LP_WKUP_IE_SHIFT      (4U)
/*! LP_WKUP_IE - Low Power Wakeup Interrupt Enable
 *  0b0..Low Power wakeup interrupt disabled
 *  0b1..Low Power wakeup interrupt enabled
 */
#define RFMC_RF2P4GHZ_CTRL_LP_WKUP_IE(x)         (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_CTRL_LP_WKUP_IE_SHIFT)) & RFMC_RF2P4GHZ_CTRL_LP_WKUP_IE_MASK)

#define RFMC_RF2P4GHZ_CTRL_BLE_WKUP_MASK         (0x20U)
#define RFMC_RF2P4GHZ_CTRL_BLE_WKUP_SHIFT        (5U)
/*! BLE_WKUP - Bluetooth LE Wakeup
 *  0b0..Bluetooth LE low power mode wakeup deasserted
 *  0b1..Bluetooth LE low power mode wakeup asserted
 */
#define RFMC_RF2P4GHZ_CTRL_BLE_WKUP(x)           (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_CTRL_BLE_WKUP_SHIFT)) & RFMC_RF2P4GHZ_CTRL_BLE_WKUP_MASK)

#define RFMC_RF2P4GHZ_CTRL_BLE_LP_EN_MASK        (0x40U)
#define RFMC_RF2P4GHZ_CTRL_BLE_LP_EN_SHIFT       (6U)
/*! BLE_LP_EN - Bluetooth LE Low Power Enable
 *  0b0..Bluetooth LE wakeup request disabled
 *  0b1..Bluetooth LE wakeup request enabled
 */
#define RFMC_RF2P4GHZ_CTRL_BLE_LP_EN(x)          (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_CTRL_BLE_LP_EN_SHIFT)) & RFMC_RF2P4GHZ_CTRL_BLE_LP_EN_MASK)

#define RFMC_RF2P4GHZ_CTRL_LP_ENTER_MASK         (0x80U)
#define RFMC_RF2P4GHZ_CTRL_LP_ENTER_SHIFT        (7U)
/*! LP_ENTER - S/W Low Power Entry Request
 *  0b0..Deassert S/W request for low power mode entry
 *  0b1..Assert S/W request for low power mode entry
 */
#define RFMC_RF2P4GHZ_CTRL_LP_ENTER(x)           (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_CTRL_LP_ENTER_SHIFT)) & RFMC_RF2P4GHZ_CTRL_LP_ENTER_MASK)

#define RFMC_RF2P4GHZ_CTRL_LP_MODE_MASK          (0xF00U)
#define RFMC_RF2P4GHZ_CTRL_LP_MODE_SHIFT         (8U)
/*! LP_MODE - Radio Low Power Mode
 *  0b0000..Active: clock gating only (only intended for debug)
 *  0b0001..Sleep: clock gating, PMC in low power mode(only intended for debug)
 *  0b0011..Deep Sleep: low power static mode with retention of digital logic and SRAMs.
 *  0b0111..Power Down: power down of radio digital logic, optional SRAM retention.
 *  0b1111..Deep Power Down: power down of radio digital logic and SRAMs.
 */
#define RFMC_RF2P4GHZ_CTRL_LP_MODE(x)            (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_CTRL_LP_MODE_SHIFT)) & RFMC_RF2P4GHZ_CTRL_LP_MODE_MASK)

#define RFMC_RF2P4GHZ_CTRL_LP_WKUP_DLY_MASK      (0x3F000U)
#define RFMC_RF2P4GHZ_CTRL_LP_WKUP_DLY_SHIFT     (12U)
/*! LP_WKUP_DLY - LP Wakeup Delay
 */
#define RFMC_RF2P4GHZ_CTRL_LP_WKUP_DLY(x)        (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_CTRL_LP_WKUP_DLY_SHIFT)) & RFMC_RF2P4GHZ_CTRL_LP_WKUP_DLY_MASK)

#define RFMC_RF2P4GHZ_CTRL_SFA_TRIG_EN_MASK      (0x1C0000U)
#define RFMC_RF2P4GHZ_CTRL_SFA_TRIG_EN_SHIFT     (18U)
/*! SFA_TRIG_EN - SFA Trigger Enable
 *  0bxx0..MAN Low Power Controller is not allowed to cause an SFA trigger.
 *  0bxx1..MAN Low Power Controller is allowed to cause an SFA trigger.
 *  0bx0x..WOR Low Power Controller is not allowed to cause an SFA trigger.
 *  0bx1x..WOR Low Power Controller is allowed to cause an SFA trigger.
 *  0b0xx..Bluetooth LE Low Power Controller is not allowed to cause an SFA trigger.
 *  0b1xx..Bluetooth LE Low Power Controller is allowed to cause an SFA trigger.
 */
#define RFMC_RF2P4GHZ_CTRL_SFA_TRIG_EN(x)        (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_CTRL_SFA_TRIG_EN_SHIFT)) & RFMC_RF2P4GHZ_CTRL_SFA_TRIG_EN_MASK)

#define RFMC_RF2P4GHZ_CTRL_LP_STOP_REQ_GLITCH_DIS_MASK (0x200000U)
#define RFMC_RF2P4GHZ_CTRL_LP_STOP_REQ_GLITCH_DIS_SHIFT (21U)
/*! LP_STOP_REQ_GLITCH_DIS - LP_STOP_REQ Glitch Disable for 2.4GHz Radio
 */
#define RFMC_RF2P4GHZ_CTRL_LP_STOP_REQ_GLITCH_DIS(x) (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_CTRL_LP_STOP_REQ_GLITCH_DIS_SHIFT)) & RFMC_RF2P4GHZ_CTRL_LP_STOP_REQ_GLITCH_DIS_MASK)

#define RFMC_RF2P4GHZ_CTRL_XO_EN_GLITCH_DIS_MASK (0x400000U)
#define RFMC_RF2P4GHZ_CTRL_XO_EN_GLITCH_DIS_SHIFT (22U)
/*! XO_EN_GLITCH_DIS - XO_EN Glitch Disable for 2.4GHz Radio
 */
#define RFMC_RF2P4GHZ_CTRL_XO_EN_GLITCH_DIS(x)   (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_CTRL_XO_EN_GLITCH_DIS_SHIFT)) & RFMC_RF2P4GHZ_CTRL_XO_EN_GLITCH_DIS_MASK)

#define RFMC_RF2P4GHZ_CTRL_XO_EN_MASK            (0x800000U)
#define RFMC_RF2P4GHZ_CTRL_XO_EN_SHIFT           (23U)
/*! XO_EN - XO Enable for 2.4GHz Radio
 *  0b0..XO software enable deasserted
 *  0b1..XO software enable asserted
 */
#define RFMC_RF2P4GHZ_CTRL_XO_EN(x)              (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_CTRL_XO_EN_SHIFT)) & RFMC_RF2P4GHZ_CTRL_XO_EN_MASK)

#define RFMC_RF2P4GHZ_CTRL_CLK_OVR_MASK          (0xF000000U)
#define RFMC_RF2P4GHZ_CTRL_CLK_OVR_SHIFT         (24U)
/*! CLK_OVR - Clock Gating Override
 *  0bxxx0..TIMER clock only enabled when TIM_EN=1
 *  0bxxx1..TIMER clock always enabled
 *  0bxx0x..MAN power controller clock only enabled when MAN_EN=1 (default)
 *  0bxx1x..MAN power controller clock always enabled
 *  0bx0xx..WOR power controller clock only enabled when WOR_EN=1 (default)
 *  0bx1xx..WOR power controller clock always enabled
 *  0b0xxx..Bluetooth LE power controller clock (and 32kHz clock used by Bluetooth LE link layer) only enabled when BLE_LP_EN=1 (default)
 *  0b1xxx..Bluetooth LE power controller clock (and 32kHz clock used by Bluetooth LE link layer) always enabled
 */
#define RFMC_RF2P4GHZ_CTRL_CLK_OVR(x)            (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_CTRL_CLK_OVR_SHIFT)) & RFMC_RF2P4GHZ_CTRL_CLK_OVR_MASK)

#define RFMC_RF2P4GHZ_CTRL_CPU_RST_LOCK_MASK     (0x10000000U)
#define RFMC_RF2P4GHZ_CTRL_CPU_RST_LOCK_SHIFT    (28U)
/*! CPU_RST_LOCK - LOCK for CPU_RST
 *  0b0..CPU_RST bit is not locked
 *  0b1..CPU_RST bit is locked
 */
#define RFMC_RF2P4GHZ_CTRL_CPU_RST_LOCK(x)       (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_CTRL_CPU_RST_LOCK_SHIFT)) & RFMC_RF2P4GHZ_CTRL_CPU_RST_LOCK_MASK)

#define RFMC_RF2P4GHZ_CTRL_CPU_RST_MASK          (0x20000000U)
#define RFMC_RF2P4GHZ_CTRL_CPU_RST_SHIFT         (29U)
/*! CPU_RST - S/W Reset for 2.4GHz Radio CPU
 *  0b0..Release the 2.4GHz radio CPU from reset
 *  0b1..Hold the 2.4GHz radio CPU in reset
 */
#define RFMC_RF2P4GHZ_CTRL_CPU_RST(x)            (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_CTRL_CPU_RST_SHIFT)) & RFMC_RF2P4GHZ_CTRL_CPU_RST_MASK)

#define RFMC_RF2P4GHZ_CTRL_RF_POR_MASK           (0x40000000U)
#define RFMC_RF2P4GHZ_CTRL_RF_POR_SHIFT          (30U)
/*! RF_POR - S/W Power-on-Reset for 2.4GHz Radio
 *  0b0..Release the 2.4GHz radio from power-on-reset
 *  0b1..Hold the 2.4GHz radio in power-on-reset
 */
#define RFMC_RF2P4GHZ_CTRL_RF_POR(x)             (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_CTRL_RF_POR_SHIFT)) & RFMC_RF2P4GHZ_CTRL_RF_POR_MASK)

#define RFMC_RF2P4GHZ_CTRL_RST_MASK              (0x80000000U)
#define RFMC_RF2P4GHZ_CTRL_RST_SHIFT             (31U)
/*! RST - S/W Reset for 2.4GHz Radio
 *  0b0..Release the 2.4GHz radio from reset
 *  0b1..Hold the 2.4GHz radio in reset
 */
#define RFMC_RF2P4GHZ_CTRL_RST(x)                (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_CTRL_RST_SHIFT)) & RFMC_RF2P4GHZ_CTRL_RST_MASK)
/*! @} */

/*! @name RF2P4GHZ_STAT - 2.4GHz Radio Status Register */
/*! @{ */

#define RFMC_RF2P4GHZ_STAT_WOR_WKUP_FLAG_MASK    (0x1U)
#define RFMC_RF2P4GHZ_STAT_WOR_WKUP_FLAG_SHIFT   (0U)
/*! WOR_WKUP_FLAG - WOR Wakeup Flag
 */
#define RFMC_RF2P4GHZ_STAT_WOR_WKUP_FLAG(x)      (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_STAT_WOR_WKUP_FLAG_SHIFT)) & RFMC_RF2P4GHZ_STAT_WOR_WKUP_FLAG_MASK)

#define RFMC_RF2P4GHZ_STAT_MAN_WKUP_FLAG_MASK    (0x2U)
#define RFMC_RF2P4GHZ_STAT_MAN_WKUP_FLAG_SHIFT   (1U)
/*! MAN_WKUP_FLAG - MAN Wakeup Flag
 */
#define RFMC_RF2P4GHZ_STAT_MAN_WKUP_FLAG(x)      (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_STAT_MAN_WKUP_FLAG_SHIFT)) & RFMC_RF2P4GHZ_STAT_MAN_WKUP_FLAG_MASK)

#define RFMC_RF2P4GHZ_STAT_BLE_WKUP_FLAG_MASK    (0x4U)
#define RFMC_RF2P4GHZ_STAT_BLE_WKUP_FLAG_SHIFT   (2U)
/*! BLE_WKUP_FLAG - Bluetooth LE Wakeup Flag
 */
#define RFMC_RF2P4GHZ_STAT_BLE_WKUP_FLAG(x)      (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_STAT_BLE_WKUP_FLAG_SHIFT)) & RFMC_RF2P4GHZ_STAT_BLE_WKUP_FLAG_MASK)

#define RFMC_RF2P4GHZ_STAT_RFACT_FLAG_MASK       (0x8U)
#define RFMC_RF2P4GHZ_STAT_RFACT_FLAG_SHIFT      (3U)
/*! RFACT_FLAG - RF_ACTIVE Flag
 */
#define RFMC_RF2P4GHZ_STAT_RFACT_FLAG(x)         (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_STAT_RFACT_FLAG_SHIFT)) & RFMC_RF2P4GHZ_STAT_RFACT_FLAG_MASK)

#define RFMC_RF2P4GHZ_STAT_LP_WKUP_FLAG_MASK     (0x10U)
#define RFMC_RF2P4GHZ_STAT_LP_WKUP_FLAG_SHIFT    (4U)
/*! LP_WKUP_FLAG - Low Power Wakeup Flag
 */
#define RFMC_RF2P4GHZ_STAT_LP_WKUP_FLAG(x)       (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_STAT_LP_WKUP_FLAG_SHIFT)) & RFMC_RF2P4GHZ_STAT_LP_WKUP_FLAG_MASK)

#define RFMC_RF2P4GHZ_STAT_SLP_RDY_STAT_MASK     (0x20U)
#define RFMC_RF2P4GHZ_STAT_SLP_RDY_STAT_SHIFT    (5U)
/*! SLP_RDY_STAT - RF_CMC Sleep Ready Status
 */
#define RFMC_RF2P4GHZ_STAT_SLP_RDY_STAT(x)       (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_STAT_SLP_RDY_STAT_SHIFT)) & RFMC_RF2P4GHZ_STAT_SLP_RDY_STAT_MASK)

#define RFMC_RF2P4GHZ_STAT_RST_STAT_MASK         (0x40U)
#define RFMC_RF2P4GHZ_STAT_RST_STAT_SHIFT        (6U)
/*! RST_STAT - Reset Status
 *  0b0..Reset is not asserted.
 *  0b1..Reset is asserted.
 */
#define RFMC_RF2P4GHZ_STAT_RST_STAT(x)           (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_STAT_RST_STAT_SHIFT)) & RFMC_RF2P4GHZ_STAT_RST_STAT_MASK)

#define RFMC_RF2P4GHZ_STAT_FRO_CLK_VLD_STAT_MASK (0x80U)
#define RFMC_RF2P4GHZ_STAT_FRO_CLK_VLD_STAT_SHIFT (7U)
/*! FRO_CLK_VLD_STAT - FRO Clock Valid Status
 */
#define RFMC_RF2P4GHZ_STAT_FRO_CLK_VLD_STAT(x)   (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_STAT_FRO_CLK_VLD_STAT_SHIFT)) & RFMC_RF2P4GHZ_STAT_FRO_CLK_VLD_STAT_MASK)

#define RFMC_RF2P4GHZ_STAT_LP_REQ_STAT_MASK      (0x100U)
#define RFMC_RF2P4GHZ_STAT_LP_REQ_STAT_SHIFT     (8U)
/*! LP_REQ_STAT - Low Power Request Status
 */
#define RFMC_RF2P4GHZ_STAT_LP_REQ_STAT(x)        (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_STAT_LP_REQ_STAT_SHIFT)) & RFMC_RF2P4GHZ_STAT_LP_REQ_STAT_MASK)

#define RFMC_RF2P4GHZ_STAT_LP_ACK_STAT_MASK      (0x200U)
#define RFMC_RF2P4GHZ_STAT_LP_ACK_STAT_SHIFT     (9U)
/*! LP_ACK_STAT - Low Power Acknowledge Status
 */
#define RFMC_RF2P4GHZ_STAT_LP_ACK_STAT(x)        (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_STAT_LP_ACK_STAT_SHIFT)) & RFMC_RF2P4GHZ_STAT_LP_ACK_STAT_MASK)

#define RFMC_RF2P4GHZ_STAT_BLE_WKUP_STAT_MASK    (0x400U)
#define RFMC_RF2P4GHZ_STAT_BLE_WKUP_STAT_SHIFT   (10U)
/*! BLE_WKUP_STAT - Bluetooth LE Wakeup Status
 */
#define RFMC_RF2P4GHZ_STAT_BLE_WKUP_STAT(x)      (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_STAT_BLE_WKUP_STAT_SHIFT)) & RFMC_RF2P4GHZ_STAT_BLE_WKUP_STAT_MASK)

#define RFMC_RF2P4GHZ_STAT_WOR_STATE_MASK        (0x7000U)
#define RFMC_RF2P4GHZ_STAT_WOR_STATE_SHIFT       (12U)
/*! WOR_STATE - WOR Low Power State
 *  0b000..RESET state (WOR_EN=0).
 *  0b001..ACTIVE state (XO enabled, RF_ACTIVE asserted, LP request deasserted).
 *  0b010..SLEEP state (XO disabled, RF_ACTIVE deasserted, LP request asserted).
 *  0b011..WAKEUP state (XO enabled, RF_ACTIVE asserted after RFACT_WKUP_DLY, LP request deasserted after LP_WKUP_DLY).
 */
#define RFMC_RF2P4GHZ_STAT_WOR_STATE(x)          (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_STAT_WOR_STATE_SHIFT)) & RFMC_RF2P4GHZ_STAT_WOR_STATE_MASK)

#define RFMC_RF2P4GHZ_STAT_MAN_STATE_MASK        (0x38000U)
#define RFMC_RF2P4GHZ_STAT_MAN_STATE_SHIFT       (15U)
/*! MAN_STATE - MAN Low Power State
 *  0b000..RESET state (MAN_EN=0).
 *  0b001..ACTIVE state (XO enabled, RF_ACTIVE asserted, LP request deasserted).
 *  0b010..SLEEP state (XO disabled, RF_ACTIVE deasserted, LP request asserted).
 *  0b011..WAKEUP state (XO enabled, RF_ACTIVE asserted after RFACT_WKUP_DLY, LP request deasserted after LP_WKUP_DLY).
 */
#define RFMC_RF2P4GHZ_STAT_MAN_STATE(x)          (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_STAT_MAN_STATE_SHIFT)) & RFMC_RF2P4GHZ_STAT_MAN_STATE_MASK)

#define RFMC_RF2P4GHZ_STAT_BLE_STATE_MASK        (0x1C0000U)
#define RFMC_RF2P4GHZ_STAT_BLE_STATE_SHIFT       (18U)
/*! BLE_STATE - Bluetooth LE Low Power State
 *  0b000..RESET state (BLE_LP_EN=0).
 *  0b001..ACTIVE state (XO enabled, RF_ACTIVE asserted, LP request deasserted).
 *  0b010..SLEEP state (XO disabled, RF_ACTIVE deasserted, LP request asserted).
 *  0b011..WAKEUP state (XO enabled, RF_ACTIVE asserted after RFACT_WKUP_DLY, LP request deasserted after LP_WKUP_DLY).
 */
#define RFMC_RF2P4GHZ_STAT_BLE_STATE(x)          (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_STAT_BLE_STATE_SHIFT)) & RFMC_RF2P4GHZ_STAT_BLE_STATE_MASK)
/*! @} */

/*! @name RF2P4GHZ_COEXT - 2.4GHz Radio Coexistence Register */
/*! @{ */

#define RFMC_RF2P4GHZ_COEXT_RFGPO_OBE_MASK       (0xFFU)
#define RFMC_RF2P4GHZ_COEXT_RFGPO_OBE_SHIFT      (0U)
/*! RFGPO_OBE - RF_GPO Output Buffer Enable
 */
#define RFMC_RF2P4GHZ_COEXT_RFGPO_OBE(x)         (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_COEXT_RFGPO_OBE_SHIFT)) & RFMC_RF2P4GHZ_COEXT_RFGPO_OBE_MASK)

#define RFMC_RF2P4GHZ_COEXT_RFGPO_SRC_MASK       (0x700U)
#define RFMC_RF2P4GHZ_COEXT_RFGPO_SRC_SHIFT      (8U)
/*! RFGPO_SRC - RF_GPO Source
 *  0b000..RF_GPO[7:0] = {coext[3:0], fem_ctrl[3:0]}
 *  0b001..RF_GPO[7:0] = {fem_ctrl[3:0], coext[3:0]}
 *  0b010..RF_GPO[7:0] = {lant_lut_gpio[3:0], fem_ctrl[3:0]}
 *  0b011..RF_GPO[7:0] = {fem_ctrl[3:0], lant_lut_gpio[3:0]}
 *  0b100..RF_GPO[7:0] = {lant_lut_gpio[3:0], coext[3:0]}
 *  0b101..RF_GPO[7:0] = {coext[3:0], lant_lut_gpio[3:0]}
 */
#define RFMC_RF2P4GHZ_COEXT_RFGPO_SRC(x)         (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_COEXT_RFGPO_SRC_SHIFT)) & RFMC_RF2P4GHZ_COEXT_RFGPO_SRC_MASK)

#define RFMC_RF2P4GHZ_COEXT_PORTA_PWR_MASK       (0x800U)
#define RFMC_RF2P4GHZ_COEXT_PORTA_PWR_SHIFT      (11U)
/*! PORTA_PWR - PORTA Power
 *  0b0..PORTA pins do not remain powered (default behavior)
 *  0b1..PORTA pins remain powered
 */
#define RFMC_RF2P4GHZ_COEXT_PORTA_PWR(x)         (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_COEXT_PORTA_PWR_SHIFT)) & RFMC_RF2P4GHZ_COEXT_PORTA_PWR_MASK)

#define RFMC_RF2P4GHZ_COEXT_RFACT_SRC_MASK       (0x3000U)
#define RFMC_RF2P4GHZ_COEXT_RFACT_SRC_SHIFT      (12U)
/*! RFACT_SRC - RF_ACTIVE Source
 *  0b00..RF_ACTIVE is driven by the RFMC
 *  0b01..RF_ACTIVE is driven by the TSM/LL
 *  0b10..RF_ACTIVE is driven by the Bluetooth LE wakeup request (bt_clk_req)
 *  0b11..Reserved
 */
#define RFMC_RF2P4GHZ_COEXT_RFACT_SRC(x)         (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_COEXT_RFACT_SRC_SHIFT)) & RFMC_RF2P4GHZ_COEXT_RFACT_SRC_MASK)

#define RFMC_RF2P4GHZ_COEXT_RFACT_IDIS_MASK      (0x4000U)
#define RFMC_RF2P4GHZ_COEXT_RFACT_IDIS_SHIFT     (14U)
/*! RFACT_IDIS - RF_ACTIVE Idle Disable
 *  0b0..RF_ACTIVE does not deassert when TSM is idle (will deassert on next low power mode entry)
 *  0b1..RF_ACTIVE will deassert when TSM is idle
 */
#define RFMC_RF2P4GHZ_COEXT_RFACT_IDIS(x)        (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_COEXT_RFACT_IDIS_SHIFT)) & RFMC_RF2P4GHZ_COEXT_RFACT_IDIS_MASK)

#define RFMC_RF2P4GHZ_COEXT_RFACT_EN_MASK        (0x8000U)
#define RFMC_RF2P4GHZ_COEXT_RFACT_EN_SHIFT       (15U)
/*! RFACT_EN - S/W Enable of RF_ACTIVE pin
 *  0b0..Take no action
 *  0b1..Assert RF_ACTIVE pin
 */
#define RFMC_RF2P4GHZ_COEXT_RFACT_EN(x)          (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_COEXT_RFACT_EN_SHIFT)) & RFMC_RF2P4GHZ_COEXT_RFACT_EN_MASK)

#define RFMC_RF2P4GHZ_COEXT_RFACT_WKUP_DLY_MASK  (0x3F0000U)
#define RFMC_RF2P4GHZ_COEXT_RFACT_WKUP_DLY_SHIFT (16U)
/*! RFACT_WKUP_DLY - RF_ACTIVE Wakeup Delay
 */
#define RFMC_RF2P4GHZ_COEXT_RFACT_WKUP_DLY(x)    (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_COEXT_RFACT_WKUP_DLY_SHIFT)) & RFMC_RF2P4GHZ_COEXT_RFACT_WKUP_DLY_MASK)

#define RFMC_RF2P4GHZ_COEXT_QREQ_SRC_MASK        (0x1000000U)
#define RFMC_RF2P4GHZ_COEXT_QREQ_SRC_SHIFT       (24U)
/*! QREQ_SRC - QUIET_REQ Source
 *  0b0..QUIET_REQ is driven by the RFMC
 *  0b1..QUIET_REQ is driven by the TSM/LL
 */
#define RFMC_RF2P4GHZ_COEXT_QREQ_SRC(x)          (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_COEXT_QREQ_SRC_SHIFT)) & RFMC_RF2P4GHZ_COEXT_QREQ_SRC_MASK)

#define RFMC_RF2P4GHZ_COEXT_QREQ_SOC_EN_MASK     (0x2000000U)
#define RFMC_RF2P4GHZ_COEXT_QREQ_SOC_EN_SHIFT    (25U)
/*! QREQ_SOC_EN - QUIET_REQ Enable for SOC Core Flash
 *  0b0..QUIET_REQ is not enabled for SOC Core Flash
 *  0b1..QUIET_REQ is enabled for SOC Core Flash
 */
#define RFMC_RF2P4GHZ_COEXT_QREQ_SOC_EN(x)       (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_COEXT_QREQ_SOC_EN_SHIFT)) & RFMC_RF2P4GHZ_COEXT_QREQ_SOC_EN_MASK)

#define RFMC_RF2P4GHZ_COEXT_QREQ_RF_EN_MASK      (0x4000000U)
#define RFMC_RF2P4GHZ_COEXT_QREQ_RF_EN_SHIFT     (26U)
/*! QREQ_RF_EN - QUIET_REQ Enable for Radio CPU Flash
 *  0b0..QUIET_REQ is not enabled for Radio CPU Flash
 *  0b1..QUIET_REQ is enabled for Radio CPU Flash
 */
#define RFMC_RF2P4GHZ_COEXT_QREQ_RF_EN(x)        (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_COEXT_QREQ_RF_EN_SHIFT)) & RFMC_RF2P4GHZ_COEXT_QREQ_RF_EN_MASK)

#define RFMC_RF2P4GHZ_COEXT_RFNA_IBE_MASK        (0x70000000U)
#define RFMC_RF2P4GHZ_COEXT_RFNA_IBE_SHIFT       (28U)
/*! RFNA_IBE - RF_NOT_ALLOWED Input Buffer Enables
 *  0b000..RF_NOT_ALLOWED input pin disabled
 *  0b001..RF_NOT_ALLOWED input pin uses PTA16
 *  0b010..RF_NOT_ALLOWED input pin uses PTA17
 *  0b011..RF_NOT_ALLOWED input pin uses PTA22
 *  0b100..RF_NOT_ALLOWED input pin uses PTC7
 *  0b101..RF_NOT_ALLOWED input pin uses PTD6
 */
#define RFMC_RF2P4GHZ_COEXT_RFNA_IBE(x)          (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_COEXT_RFNA_IBE_SHIFT)) & RFMC_RF2P4GHZ_COEXT_RFNA_IBE_MASK)
/*! @} */

/*! @name RF2P4GHZ_TIMER - 2.4GHz TIMER Register */
/*! @{ */

#define RFMC_RF2P4GHZ_TIMER_TIME_MASK            (0xFFFFFFU)
#define RFMC_RF2P4GHZ_TIMER_TIME_SHIFT           (0U)
/*! TIME - Timer Count
 */
#define RFMC_RF2P4GHZ_TIMER_TIME(x)              (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_TIMER_TIME_SHIFT)) & RFMC_RF2P4GHZ_TIMER_TIME_MASK)

#define RFMC_RF2P4GHZ_TIMER_TIM_CLR_MASK         (0x40000000U)
#define RFMC_RF2P4GHZ_TIMER_TIM_CLR_SHIFT        (30U)
/*! TIM_CLR - Timer Clear
 *  0b0..Timer not cleared
 *  0b1..Timer cleared
 */
#define RFMC_RF2P4GHZ_TIMER_TIM_CLR(x)           (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_TIMER_TIM_CLR_SHIFT)) & RFMC_RF2P4GHZ_TIMER_TIM_CLR_MASK)

#define RFMC_RF2P4GHZ_TIMER_TIM_EN_MASK          (0x80000000U)
#define RFMC_RF2P4GHZ_TIMER_TIM_EN_SHIFT         (31U)
/*! TIM_EN - Timer Enable
 *  0b0..Timer disabled
 *  0b1..Timer enabled
 */
#define RFMC_RF2P4GHZ_TIMER_TIM_EN(x)            (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_TIMER_TIM_EN_SHIFT)) & RFMC_RF2P4GHZ_TIMER_TIM_EN_MASK)
/*! @} */

/*! @name RF2P4GHZ_WOR1 - 2.4GHz WOR Register 1 */
/*! @{ */

#define RFMC_RF2P4GHZ_WOR1_DURATION_TGT_MASK     (0xFFFFFFU)
#define RFMC_RF2P4GHZ_WOR1_DURATION_TGT_SHIFT    (0U)
/*! DURATION_TGT - WOR Low Power Duration Target
 */
#define RFMC_RF2P4GHZ_WOR1_DURATION_TGT(x)       (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_WOR1_DURATION_TGT_SHIFT)) & RFMC_RF2P4GHZ_WOR1_DURATION_TGT_MASK)

#define RFMC_RF2P4GHZ_WOR1_ENTER_REQ_MASK        (0x80000000U)
#define RFMC_RF2P4GHZ_WOR1_ENTER_REQ_SHIFT       (31U)
/*! ENTER_REQ - WOR Low Power Entry Request
 *  0b0..WOR low power mode request deasserted
 *  0b1..WOR low power mode request asserted
 */
#define RFMC_RF2P4GHZ_WOR1_ENTER_REQ(x)          (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_WOR1_ENTER_REQ_SHIFT)) & RFMC_RF2P4GHZ_WOR1_ENTER_REQ_MASK)
/*! @} */

/*! @name RF2P4GHZ_WOR2 - 2.4GHz WOR Register 2 */
/*! @{ */

#define RFMC_RF2P4GHZ_WOR2_DURATION_MASK         (0xFFFFFFU)
#define RFMC_RF2P4GHZ_WOR2_DURATION_SHIFT        (0U)
/*! DURATION - WOR Low Power Duration
 */
#define RFMC_RF2P4GHZ_WOR2_DURATION(x)           (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_WOR2_DURATION_SHIFT)) & RFMC_RF2P4GHZ_WOR2_DURATION_MASK)

#define RFMC_RF2P4GHZ_WOR2_WOR_WKUP_MASK         (0x40000000U)
#define RFMC_RF2P4GHZ_WOR2_WOR_WKUP_SHIFT        (30U)
/*! WOR_WKUP - WOR Wakeup
 *  0b0..WOR low power mode wakeup deasserted
 *  0b1..WOR low power mode wakeup asserted
 */
#define RFMC_RF2P4GHZ_WOR2_WOR_WKUP(x)           (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_WOR2_WOR_WKUP_SHIFT)) & RFMC_RF2P4GHZ_WOR2_WOR_WKUP_MASK)

#define RFMC_RF2P4GHZ_WOR2_WOR_EN_MASK           (0x80000000U)
#define RFMC_RF2P4GHZ_WOR2_WOR_EN_SHIFT          (31U)
/*! WOR_EN - WOR Enable
 *  0b0..WOR low power mode entry/wakeup disabled
 *  0b1..WOR low power mode entry/wakeup enabled
 */
#define RFMC_RF2P4GHZ_WOR2_WOR_EN(x)             (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_WOR2_WOR_EN_SHIFT)) & RFMC_RF2P4GHZ_WOR2_WOR_EN_MASK)
/*! @} */

/*! @name RF2P4GHZ_MAN1 - 2.4GHz MAN Register 1 */
/*! @{ */

#define RFMC_RF2P4GHZ_MAN1_ENTER_TIME_MASK       (0xFFFFFFU)
#define RFMC_RF2P4GHZ_MAN1_ENTER_TIME_SHIFT      (0U)
/*! ENTER_TIME - MAN Low Power Entry Time Stamp
 */
#define RFMC_RF2P4GHZ_MAN1_ENTER_TIME(x)         (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_MAN1_ENTER_TIME_SHIFT)) & RFMC_RF2P4GHZ_MAN1_ENTER_TIME_MASK)

#define RFMC_RF2P4GHZ_MAN1_ENTER_REQ_MASK        (0x80000000U)
#define RFMC_RF2P4GHZ_MAN1_ENTER_REQ_SHIFT       (31U)
/*! ENTER_REQ - MAN Low Power Entry Request
 *  0b0..MAN low power mode request deasserted
 *  0b1..MAN low power mode request asserted
 */
#define RFMC_RF2P4GHZ_MAN1_ENTER_REQ(x)          (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_MAN1_ENTER_REQ_SHIFT)) & RFMC_RF2P4GHZ_MAN1_ENTER_REQ_MASK)
/*! @} */

/*! @name RF2P4GHZ_MAN2 - 2.4GHz MAN Register 2 */
/*! @{ */

#define RFMC_RF2P4GHZ_MAN2_WKUP_TIME_MASK        (0xFFFFFFU)
#define RFMC_RF2P4GHZ_MAN2_WKUP_TIME_SHIFT       (0U)
/*! WKUP_TIME - MAN Low Power Wakeup Time Stamp
 */
#define RFMC_RF2P4GHZ_MAN2_WKUP_TIME(x)          (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_MAN2_WKUP_TIME_SHIFT)) & RFMC_RF2P4GHZ_MAN2_WKUP_TIME_MASK)

#define RFMC_RF2P4GHZ_MAN2_MAN_WKUP_MASK         (0x40000000U)
#define RFMC_RF2P4GHZ_MAN2_MAN_WKUP_SHIFT        (30U)
/*! MAN_WKUP - MAN Wakeup
 *  0b0..MAN low power mode wakeup deasserted
 *  0b1..MAN low power mode wakeup asserted
 */
#define RFMC_RF2P4GHZ_MAN2_MAN_WKUP(x)           (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_MAN2_MAN_WKUP_SHIFT)) & RFMC_RF2P4GHZ_MAN2_MAN_WKUP_MASK)

#define RFMC_RF2P4GHZ_MAN2_MAN_EN_MASK           (0x80000000U)
#define RFMC_RF2P4GHZ_MAN2_MAN_EN_SHIFT          (31U)
/*! MAN_EN - MAN Enable
 *  0b0..MAN low power mode entry/wakeup disabled
 *  0b1..MAN low power mode entry/wakeup enabled
 */
#define RFMC_RF2P4GHZ_MAN2_MAN_EN(x)             (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_MAN2_MAN_EN_SHIFT)) & RFMC_RF2P4GHZ_MAN2_MAN_EN_MASK)
/*! @} */

/*! @name RF2P4GHZ_MAN3 - 2.4GHz MAN Register 3 */
/*! @{ */

#define RFMC_RF2P4GHZ_MAN3_ENTER_TIME_CAPT_MASK  (0xFFFFFFU)
#define RFMC_RF2P4GHZ_MAN3_ENTER_TIME_CAPT_SHIFT (0U)
/*! ENTER_TIME_CAPT - MAN Low Power Entry Time Captured
 */
#define RFMC_RF2P4GHZ_MAN3_ENTER_TIME_CAPT(x)    (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_MAN3_ENTER_TIME_CAPT_SHIFT)) & RFMC_RF2P4GHZ_MAN3_ENTER_TIME_CAPT_MASK)
/*! @} */

/*! @name RF2P4GHZ_MAN4 - 2.4GHz MAN Register 4 */
/*! @{ */

#define RFMC_RF2P4GHZ_MAN4_WKUP_TIME_CAPT_MASK   (0xFFFFFFU)
#define RFMC_RF2P4GHZ_MAN4_WKUP_TIME_CAPT_SHIFT  (0U)
/*! WKUP_TIME_CAPT - MAN Low Power Wakeup Time Captured
 */
#define RFMC_RF2P4GHZ_MAN4_WKUP_TIME_CAPT(x)     (((uint32_t)(((uint32_t)(x)) << RFMC_RF2P4GHZ_MAN4_WKUP_TIME_CAPT_SHIFT)) & RFMC_RF2P4GHZ_MAN4_WKUP_TIME_CAPT_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group RFMC_Register_Masks */


/* RFMC - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral RFMC base address */
  #define RFMC_BASE                                (0x50040000u)
  /** Peripheral RFMC base address */
  #define RFMC_BASE_NS                             (0x40040000u)
  /** Peripheral RFMC base pointer */
  #define RFMC                                     ((RFMC_Type *)RFMC_BASE)
  /** Peripheral RFMC base pointer */
  #define RFMC_NS                                  ((RFMC_Type *)RFMC_BASE_NS)
  /** Array initializer of RFMC peripheral base addresses */
  #define RFMC_BASE_ADDRS                          { RFMC_BASE }
  /** Array initializer of RFMC peripheral base pointers */
  #define RFMC_BASE_PTRS                           { RFMC }
  /** Array initializer of RFMC peripheral base addresses */
  #define RFMC_BASE_ADDRS_NS                       { RFMC_BASE_NS }
  /** Array initializer of RFMC peripheral base pointers */
  #define RFMC_BASE_PTRS_NS                        { RFMC_NS }
#else
  /** Peripheral RFMC base address */
  #define RFMC_BASE                                (0x40040000u)
  /** Peripheral RFMC base pointer */
  #define RFMC                                     ((RFMC_Type *)RFMC_BASE)
  /** Array initializer of RFMC peripheral base addresses */
  #define RFMC_BASE_ADDRS                          { RFMC_BASE }
  /** Array initializer of RFMC peripheral base pointers */
  #define RFMC_BASE_PTRS                           { RFMC }
#endif

/*!
 * @}
 */ /* end of group RFMC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- RF_CMC1 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup RF_CMC1_Peripheral_Access_Layer RF_CMC1 Peripheral Access Layer
 * @{
 */

/** RF_CMC1 - Register Layout Typedef */
typedef struct {
  __IO uint32_t RADIO_LP;                          /**< Radio Low Power Control Register, offset: 0x0 */
  __IO uint32_t SOC_LP;                            /**< SOC Low Power Control and Status Register, offset: 0x4 */
  __IO uint32_t IRQ_CTRL;                          /**< Interrupt Control Register, offset: 0x8 */
  __IO uint32_t TPM2_CFG;                          /**< TPM2 Configuration Register, offset: 0xC */
  __IO uint32_t RADIO_TRIM;                        /**< Radio Trim Register, offset: 0x10 */
  __IO uint32_t RAM_PWR;                           /**< RAM Power Control register, offset: 0x14 */
} RF_CMC1_Type;

/* ----------------------------------------------------------------------------
   -- RF_CMC1 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup RF_CMC1_Register_Masks RF_CMC1 Register Masks
 * @{
 */

/*! @name RADIO_LP - Radio Low Power Control Register */
/*! @{ */

#define RF_CMC1_RADIO_LP_SLEEP_EN_MASK           (0x1U)
#define RF_CMC1_RADIO_LP_SLEEP_EN_SHIFT          (0U)
/*! SLEEP_EN - Sleep Enable
 */
#define RF_CMC1_RADIO_LP_SLEEP_EN(x)             (((uint32_t)(((uint32_t)(x)) << RF_CMC1_RADIO_LP_SLEEP_EN_SHIFT)) & RF_CMC1_RADIO_LP_SLEEP_EN_MASK)

#define RF_CMC1_RADIO_LP_BLE_WKUP_MASK           (0x2U)
#define RF_CMC1_RADIO_LP_BLE_WKUP_SHIFT          (1U)
/*! BLE_WKUP - Bluetooth Wakeup
 */
#define RF_CMC1_RADIO_LP_BLE_WKUP(x)             (((uint32_t)(((uint32_t)(x)) << RF_CMC1_RADIO_LP_BLE_WKUP_SHIFT)) & RF_CMC1_RADIO_LP_BLE_WKUP_MASK)

#define RF_CMC1_RADIO_LP_CK_MASK                 (0xCU)
#define RF_CMC1_RADIO_LP_CK_SHIFT                (2U)
/*! CK - Clock Control
 *  0b00..Normal configuration. When NBU CPU executes WFI and SLEEP_EN=1 (or if NBU CPU reset is asserted), and a
 *        sleep request from RFMC (LP_ENTER) NBU, MAN or WOR is asserted, the flash is put in low power, the
 *        sleep_rdy to RFMC asserts and the FRO will be disabled.
 *  0b01..Configuration where NBU, FRO and flash are not used. When NBU CPU reset is asserted, or NBU CPU executes
 *        WFI and SLEEP_EN=1, the flash will be placed in low power, the FRO disabled, the sleep_rdy to RFMC will
 *        assert and the NBU CM3 and AHB clocks will be gated off. The RF_CMC and NBU CPU will be without a clock
 *        until the next reset, but low power requests (RFMC LP_ENTER, MAN or WOR) will by accepted by RFMC since
 *        RF_CMC's sleep_rdy output will remain asserted.
 *  0b10..Configuration where NBU CPU is not used but FRO and flash can still be used. When NBU CPU reset is
 *        asserted, or NBU CPU executes WFI and SLEEP_EN=1, the clock to the NBU CPU will be gated. When RFMC
 *        (LP_ENTER), MAN or WOR request sleep, the flash is put in low power, the sleep_rdy to RFMC asserts and the FRO will
 *        be disabled as in configuration 00.
 */
#define RF_CMC1_RADIO_LP_CK(x)                   (((uint32_t)(((uint32_t)(x)) << RF_CMC1_RADIO_LP_CK_SHIFT)) & RF_CMC1_RADIO_LP_CK_MASK)
/*! @} */

/*! @name SOC_LP - SOC Low Power Control and Status Register */
/*! @{ */

#define RF_CMC1_SOC_LP_BUS_REQ_MASK              (0x1U)
#define RF_CMC1_SOC_LP_BUS_REQ_SHIFT             (0U)
/*! BUS_REQ - Bus Access Request
 */
#define RF_CMC1_SOC_LP_BUS_REQ(x)                (((uint32_t)(((uint32_t)(x)) << RF_CMC1_SOC_LP_BUS_REQ_SHIFT)) & RF_CMC1_SOC_LP_BUS_REQ_MASK)

#define RF_CMC1_SOC_LP_BUS_AWAKE_MASK            (0x10U)
#define RF_CMC1_SOC_LP_BUS_AWAKE_SHIFT           (4U)
/*! BUS_AWAKE - Bus Awake
 */
#define RF_CMC1_SOC_LP_BUS_AWAKE(x)              (((uint32_t)(((uint32_t)(x)) << RF_CMC1_SOC_LP_BUS_AWAKE_SHIFT)) & RF_CMC1_SOC_LP_BUS_AWAKE_MASK)
/*! @} */

/*! @name IRQ_CTRL - Interrupt Control Register */
/*! @{ */

#define RF_CMC1_IRQ_CTRL_RDY_FLAG_MASK           (0x1U)
#define RF_CMC1_IRQ_CTRL_RDY_FLAG_SHIFT          (0U)
/*! RDY_FLAG - XTAL Ready Flag
 */
#define RF_CMC1_IRQ_CTRL_RDY_FLAG(x)             (((uint32_t)(((uint32_t)(x)) << RF_CMC1_IRQ_CTRL_RDY_FLAG_SHIFT)) & RF_CMC1_IRQ_CTRL_RDY_FLAG_MASK)

#define RF_CMC1_IRQ_CTRL_RDY_IE_MASK             (0x10U)
#define RF_CMC1_IRQ_CTRL_RDY_IE_SHIFT            (4U)
/*! RDY_IE - XTAL Ready Interrupt Enable
 */
#define RF_CMC1_IRQ_CTRL_RDY_IE(x)               (((uint32_t)(((uint32_t)(x)) << RF_CMC1_IRQ_CTRL_RDY_IE_SHIFT)) & RF_CMC1_IRQ_CTRL_RDY_IE_MASK)

#define RF_CMC1_IRQ_CTRL_XTAL_RDY_MASK           (0x100U)
#define RF_CMC1_IRQ_CTRL_XTAL_RDY_SHIFT          (8U)
/*! XTAL_RDY - XTAL Ready
 */
#define RF_CMC1_IRQ_CTRL_XTAL_RDY(x)             (((uint32_t)(((uint32_t)(x)) << RF_CMC1_IRQ_CTRL_XTAL_RDY_SHIFT)) & RF_CMC1_IRQ_CTRL_XTAL_RDY_MASK)
/*! @} */

/*! @name TPM2_CFG - TPM2 Configuration Register */
/*! @{ */

#define RF_CMC1_TPM2_CFG_CH0_MUX_SEL_MASK        (0x1U)
#define RF_CMC1_TPM2_CFG_CH0_MUX_SEL_SHIFT       (0U)
/*! CH0_MUX_SEL - Channel0 Input Mux Select
 *  0b0..TPM2_CH0 pin
 *  0b1..tof_timestamp_trig signal from radio
 */
#define RF_CMC1_TPM2_CFG_CH0_MUX_SEL(x)          (((uint32_t)(((uint32_t)(x)) << RF_CMC1_TPM2_CFG_CH0_MUX_SEL_SHIFT)) & RF_CMC1_TPM2_CFG_CH0_MUX_SEL_MASK)

#define RF_CMC1_TPM2_CFG_CH1_MUX_SEL_MASK        (0xF0U)
#define RF_CMC1_TPM2_CFG_CH1_MUX_SEL_SHIFT       (4U)
/*! CH1_MUX_SEL - Channel1 Input Mux Select
 *  0b0000..TPM2_CH1 pin
 *  0b0001..dtest[0] signal from radio
 *  0b0010..dtest[1] signal from radio
 *  0b0011..dtest[2] signal from radio
 *  0b0100..dtest[3] signal from radio
 *  0b0101..dtest[4] signal from radio
 *  0b0110..dtest[5] signal from radio
 *  0b0111..dtest[6] signal from radio
 *  0b1000..dtest[7] signal from radio
 *  0b1001..dtest[8] signal from radio
 *  0b1010..dtest[9] signal from radio
 *  0b1011..dtest[10] signal from radio
 *  0b1100..dtest[11] signal from radio
 *  0b1101..dtest[12] signal from radio
 *  0b1110..dtest[13] signal from radio
 *  0b1111..Reserved
 */
#define RF_CMC1_TPM2_CFG_CH1_MUX_SEL(x)          (((uint32_t)(((uint32_t)(x)) << RF_CMC1_TPM2_CFG_CH1_MUX_SEL_SHIFT)) & RF_CMC1_TPM2_CFG_CH1_MUX_SEL_MASK)

#define RF_CMC1_TPM2_CFG_CGC_MASK                (0x100U)
#define RF_CMC1_TPM2_CFG_CGC_SHIFT               (8U)
/*! CGC - Clock Gate Control
 *  0b0..TPM2 clock disabled
 *  0b1..TPM2 clock enabled
 */
#define RF_CMC1_TPM2_CFG_CGC(x)                  (((uint32_t)(((uint32_t)(x)) << RF_CMC1_TPM2_CFG_CGC_SHIFT)) & RF_CMC1_TPM2_CFG_CGC_MASK)

#define RF_CMC1_TPM2_CFG_CLK_MUX_SEL_MASK        (0xC00U)
#define RF_CMC1_TPM2_CFG_CLK_MUX_SEL_SHIFT       (10U)
/*! CLK_MUX_SEL - Clock Mux Select
 *  0b00..No clock
 *  0b01..Core Clock
 *  0b10..Radio Oscillator
 *  0b11..Reserved
 */
#define RF_CMC1_TPM2_CFG_CLK_MUX_SEL(x)          (((uint32_t)(((uint32_t)(x)) << RF_CMC1_TPM2_CFG_CLK_MUX_SEL_SHIFT)) & RF_CMC1_TPM2_CFG_CLK_MUX_SEL_MASK)
/*! @} */

/*! @name RADIO_TRIM - Radio Trim Register */
/*! @{ */

#define RF_CMC1_RADIO_TRIM_BG_TRIM_MASK          (0x7U)
#define RF_CMC1_RADIO_TRIM_BG_TRIM_SHIFT         (0U)
/*! BG_TRIM - Bandgap Trim
 *  0b000..787mV
 *  0b001..794mV
 *  0b010..800mV
 *  0b011..806mV
 *  0b100..812mV
 *  0b101..819mV
 *  0b110..825mV
 *  0b111..831mV
 */
#define RF_CMC1_RADIO_TRIM_BG_TRIM(x)            (((uint32_t)(((uint32_t)(x)) << RF_CMC1_RADIO_TRIM_BG_TRIM_SHIFT)) & RF_CMC1_RADIO_TRIM_BG_TRIM_MASK)

#define RF_CMC1_RADIO_TRIM_CM3_PHANTOM_MASK      (0x70U)
#define RF_CMC1_RADIO_TRIM_CM3_PHANTOM_SHIFT     (4U)
/*! CM3_PHANTOM - CM3 Phantom
 *  0b010..CM3 disabled. The RF_CMC will hold the CM3 in reset
 *  0b111..CM3 enabled.
 */
#define RF_CMC1_RADIO_TRIM_CM3_PHANTOM(x)        (((uint32_t)(((uint32_t)(x)) << RF_CMC1_RADIO_TRIM_CM3_PHANTOM_SHIFT)) & RF_CMC1_RADIO_TRIM_CM3_PHANTOM_MASK)
/*! @} */

/*! @name RAM_PWR - RAM Power Control register */
/*! @{ */

#define RF_CMC1_RAM_PWR_SD_EN_MASK               (0x7FFU)
#define RF_CMC1_RAM_PWR_SD_EN_SHIFT              (0U)
/*! SD_EN - Shut Down Enable
 */
#define RF_CMC1_RAM_PWR_SD_EN(x)                 (((uint32_t)(((uint32_t)(x)) << RF_CMC1_RAM_PWR_SD_EN_SHIFT)) & RF_CMC1_RAM_PWR_SD_EN_MASK)

#define RF_CMC1_RAM_PWR_DS_EN_MASK               (0x7FF0000U)
#define RF_CMC1_RAM_PWR_DS_EN_SHIFT              (16U)
/*! DS_EN - Deep Sleep Enable
 */
#define RF_CMC1_RAM_PWR_DS_EN(x)                 (((uint32_t)(((uint32_t)(x)) << RF_CMC1_RAM_PWR_DS_EN_SHIFT)) & RF_CMC1_RAM_PWR_DS_EN_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group RF_CMC1_Register_Masks */


/* RF_CMC1 - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral RF_CMC1 base address */
  #define RF_CMC1_BASE                             (0x58983000u)
  /** Peripheral RF_CMC1 base address */
  #define RF_CMC1_BASE_NS                          (0x48983000u)
  /** Peripheral RF_CMC1 base pointer */
  #define RF_CMC1                                  ((RF_CMC1_Type *)RF_CMC1_BASE)
  /** Peripheral RF_CMC1 base pointer */
  #define RF_CMC1_NS                               ((RF_CMC1_Type *)RF_CMC1_BASE_NS)
  /** Array initializer of RF_CMC1 peripheral base addresses */
  #define RF_CMC1_BASE_ADDRS                       { RF_CMC1_BASE }
  /** Array initializer of RF_CMC1 peripheral base pointers */
  #define RF_CMC1_BASE_PTRS                        { RF_CMC1 }
  /** Array initializer of RF_CMC1 peripheral base addresses */
  #define RF_CMC1_BASE_ADDRS_NS                    { RF_CMC1_BASE_NS }
  /** Array initializer of RF_CMC1 peripheral base pointers */
  #define RF_CMC1_BASE_PTRS_NS                     { RF_CMC1_NS }
#else
  /** Peripheral RF_CMC1 base address */
  #define RF_CMC1_BASE                             (0x48983000u)
  /** Peripheral RF_CMC1 base pointer */
  #define RF_CMC1                                  ((RF_CMC1_Type *)RF_CMC1_BASE)
  /** Array initializer of RF_CMC1 peripheral base addresses */
  #define RF_CMC1_BASE_ADDRS                       { RF_CMC1_BASE }
  /** Array initializer of RF_CMC1 peripheral base pointers */
  #define RF_CMC1_BASE_PTRS                        { RF_CMC1 }
#endif

/*!
 * @}
 */ /* end of group RF_CMC1_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- RF_FMCCFG Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup RF_FMCCFG_Peripheral_Access_Layer RF_FMCCFG Peripheral Access Layer
 * @{
 */

/** RF_FMCCFG - Register Layout Typedef */
typedef struct {
  __IO uint32_t RFMCCFG;                           /**< Radio Flash Memory Controller Configuration Register, offset: 0x0 */
} RF_FMCCFG_Type;

/* ----------------------------------------------------------------------------
   -- RF_FMCCFG Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup RF_FMCCFG_Register_Masks RF_FMCCFG Register Masks
 * @{
 */

/*! @name RFMCCFG - Radio Flash Memory Controller Configuration Register */
/*! @{ */

#define RF_FMCCFG_RFMCCFG_RFCF0_MASK             (0x3U)
#define RF_FMCCFG_RFMCCFG_RFCF0_SHIFT            (0U)
/*! RFCF0 - Radio Flash Control Field 0
 */
#define RF_FMCCFG_RFMCCFG_RFCF0(x)               (((uint32_t)(((uint32_t)(x)) << RF_FMCCFG_RFMCCFG_RFCF0_SHIFT)) & RF_FMCCFG_RFMCCFG_RFCF0_MASK)

#define RF_FMCCFG_RFMCCFG_RFCF1_MASK             (0xCU)
#define RF_FMCCFG_RFMCCFG_RFCF1_SHIFT            (2U)
/*! RFCF1 - Radio Flash Control Field 1
 */
#define RF_FMCCFG_RFMCCFG_RFCF1(x)               (((uint32_t)(((uint32_t)(x)) << RF_FMCCFG_RFMCCFG_RFCF1_SHIFT)) & RF_FMCCFG_RFMCCFG_RFCF1_MASK)

#define RF_FMCCFG_RFMCCFG_RFCF2_MASK             (0x70U)
#define RF_FMCCFG_RFMCCFG_RFCF2_SHIFT            (4U)
/*! RFCF2 - Radio Flash Control Field 2
 */
#define RF_FMCCFG_RFMCCFG_RFCF2(x)               (((uint32_t)(((uint32_t)(x)) << RF_FMCCFG_RFMCCFG_RFCF2_SHIFT)) & RF_FMCCFG_RFMCCFG_RFCF2_MASK)

#define RF_FMCCFG_RFMCCFG_RFCF3_MASK             (0xF00U)
#define RF_FMCCFG_RFMCCFG_RFCF3_SHIFT            (8U)
/*! RFCF3 - Radio Flash Control Field 3
 */
#define RF_FMCCFG_RFMCCFG_RFCF3(x)               (((uint32_t)(((uint32_t)(x)) << RF_FMCCFG_RFMCCFG_RFCF3_SHIFT)) & RF_FMCCFG_RFMCCFG_RFCF3_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group RF_FMCCFG_Register_Masks */


/* RF_FMCCFG - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral RF_FMCCFG base address */
  #define RF_FMCCFG_BASE                           (0x58982000u)
  /** Peripheral RF_FMCCFG base address */
  #define RF_FMCCFG_BASE_NS                        (0x48982000u)
  /** Peripheral RF_FMCCFG base pointer */
  #define RF_FMCCFG                                ((RF_FMCCFG_Type *)RF_FMCCFG_BASE)
  /** Peripheral RF_FMCCFG base pointer */
  #define RF_FMCCFG_NS                             ((RF_FMCCFG_Type *)RF_FMCCFG_BASE_NS)
  /** Array initializer of RF_FMCCFG peripheral base addresses */
  #define RF_FMCCFG_BASE_ADDRS                     { RF_FMCCFG_BASE }
  /** Array initializer of RF_FMCCFG peripheral base pointers */
  #define RF_FMCCFG_BASE_PTRS                      { RF_FMCCFG }
  /** Array initializer of RF_FMCCFG peripheral base addresses */
  #define RF_FMCCFG_BASE_ADDRS_NS                  { RF_FMCCFG_BASE_NS }
  /** Array initializer of RF_FMCCFG peripheral base pointers */
  #define RF_FMCCFG_BASE_PTRS_NS                   { RF_FMCCFG_NS }
#else
  /** Peripheral RF_FMCCFG base address */
  #define RF_FMCCFG_BASE                           (0x48982000u)
  /** Peripheral RF_FMCCFG base pointer */
  #define RF_FMCCFG                                ((RF_FMCCFG_Type *)RF_FMCCFG_BASE)
  /** Array initializer of RF_FMCCFG peripheral base addresses */
  #define RF_FMCCFG_BASE_ADDRS                     { RF_FMCCFG_BASE }
  /** Array initializer of RF_FMCCFG peripheral base pointers */
  #define RF_FMCCFG_BASE_PTRS                      { RF_FMCCFG }
#endif

/*!
 * @}
 */ /* end of group RF_FMCCFG_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- RTC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
 * @{
 */

/** RTC - Register Layout Typedef */
typedef struct {
  __IO uint32_t TSR;                               /**< RTC Time Seconds Register, offset: 0x0 */
  __IO uint32_t TPR;                               /**< RTC Time Prescaler Register, offset: 0x4 */
  __IO uint32_t TAR;                               /**< RTC Time Alarm Register, offset: 0x8 */
  __IO uint32_t TCR;                               /**< RTC Time Compensation Register, offset: 0xC */
  __IO uint32_t CR;                                /**< RTC Control Register, offset: 0x10 */
  __IO uint32_t SR;                                /**< RTC Status Register, offset: 0x14 */
  __IO uint32_t LR;                                /**< RTC Lock Register, offset: 0x18 */
  __IO uint32_t IER;                               /**< RTC Interrupt Enable Register, offset: 0x1C */
  __I  uint32_t TTSR;                              /**< RTC Tamper Time Seconds Register, offset: 0x20 */
  __IO uint32_t MER;                               /**< RTC Monotonic Enable Register, offset: 0x24 */
  __IO uint32_t MCLR;                              /**< RTC Monotonic Counter Low Register, offset: 0x28 */
  __IO uint32_t MCHR;                              /**< RTC Monotonic Counter High Register, offset: 0x2C */
       uint8_t RESERVED_0[4];
  __IO uint32_t TDR;                               /**< RTC Tamper Detect Register, offset: 0x34 */
       uint8_t RESERVED_1[4];
  __IO uint32_t TIR;                               /**< RTC Tamper Interrupt Register, offset: 0x3C */
  __IO uint32_t PCR[4];                            /**< RTC Pin Configuration Register, array offset: 0x40, array step: 0x4 */
       uint8_t RESERVED_2[1968];
  __IO uint32_t WAR;                               /**< RTC Write Access Register, offset: 0x800 */
  __IO uint32_t RAR;                               /**< RTC Read Access Register, offset: 0x804 */
} RTC_Type;

/* ----------------------------------------------------------------------------
   -- RTC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup RTC_Register_Masks RTC Register Masks
 * @{
 */

/*! @name TSR - RTC Time Seconds Register */
/*! @{ */

#define RTC_TSR_TSR_MASK                         (0xFFFFFFFFU)
#define RTC_TSR_TSR_SHIFT                        (0U)
/*! TSR - Time Seconds Register
 */
#define RTC_TSR_TSR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK)
/*! @} */

/*! @name TPR - RTC Time Prescaler Register */
/*! @{ */

#define RTC_TPR_TPR_MASK                         (0xFFFFU)
#define RTC_TPR_TPR_SHIFT                        (0U)
/*! TPR - Time Prescaler Register
 */
#define RTC_TPR_TPR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK)
/*! @} */

/*! @name TAR - RTC Time Alarm Register */
/*! @{ */

#define RTC_TAR_TAR_MASK                         (0xFFFFFFFFU)
#define RTC_TAR_TAR_SHIFT                        (0U)
/*! TAR - Time Alarm Register
 */
#define RTC_TAR_TAR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK)
/*! @} */

/*! @name TCR - RTC Time Compensation Register */
/*! @{ */

#define RTC_TCR_TCR_MASK                         (0xFFU)
#define RTC_TCR_TCR_SHIFT                        (0U)
/*! TCR - Time Compensation Register
 *  0b10000000..Time Prescaler Register overflows every 32896 clock cycles.
 *  0b10000001..Time Prescaler Register overflows every 32895 clock cycles.
 *  0b11111111..Time Prescaler Register overflows every 32769 clock cycles.
 *  0b00000000..Time Prescaler Register overflows every 32768 clock cycles.
 *  0b00000001..Time Prescaler Register overflows every 32767 clock cycles.
 *  0b01111110..Time Prescaler Register overflows every 32642 clock cycles.
 *  0b01111111..Time Prescaler Register overflows every 32641 clock cycles.
 */
#define RTC_TCR_TCR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK)

#define RTC_TCR_CIR_MASK                         (0xFF00U)
#define RTC_TCR_CIR_SHIFT                        (8U)
/*! CIR - Compensation Interval Register
 */
#define RTC_TCR_CIR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK)

#define RTC_TCR_TCV_MASK                         (0xFF0000U)
#define RTC_TCR_TCV_SHIFT                        (16U)
/*! TCV - Time Compensation Value
 */
#define RTC_TCR_TCV(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK)

#define RTC_TCR_CIC_MASK                         (0xFF000000U)
#define RTC_TCR_CIC_SHIFT                        (24U)
/*! CIC - Compensation Interval Counter
 */
#define RTC_TCR_CIC(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK)
/*! @} */

/*! @name CR - RTC Control Register */
/*! @{ */

#define RTC_CR_SWR_MASK                          (0x1U)
#define RTC_CR_SWR_SHIFT                         (0U)
/*! SWR - Software Reset
 *  0b0..No effect.
 *  0b1..Resets all RTC registers except for the SWR bit and the RTC_WAR and RTC_RAR registers . The SWR bit is
 *       cleared by VBAT POR and by software explicitly clearing it.
 */
#define RTC_CR_SWR(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK)

#define RTC_CR_WPE_MASK                          (0x2U)
#define RTC_CR_WPE_SHIFT                         (1U)
/*! WPE - Wakeup Pin Enable
 *  0b0..RTC_WAKEUP pin is disabled.
 *  0b1..RTC_WAKEUP pin is enabled and asserts if the RTC interrupt asserts or if the wakeup pin is forced on.
 */
#define RTC_CR_WPE(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK)

#define RTC_CR_UM_MASK                           (0x8U)
#define RTC_CR_UM_SHIFT                          (3U)
/*! UM - Update Mode
 *  0b0..Registers cannot be written when locked.
 *  0b1..Registers can be written when locked under limited conditions.
 */
#define RTC_CR_UM(x)                             (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK)

#define RTC_CR_CPS_MASK                          (0x20U)
#define RTC_CR_CPS_SHIFT                         (5U)
/*! CPS - Clock Pin Select
 *  0b0..The prescaler output clock (as configured by TSIC) is output on RTC_CLKOUT.
 *  0b1..The RTC 32.768 kHz clock is output on RTC_CLKOUT, provided it is output to other peripherals.
 */
#define RTC_CR_CPS(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_CR_CPS_SHIFT)) & RTC_CR_CPS_MASK)

#define RTC_CR_CLKO_MASK                         (0x200U)
#define RTC_CR_CLKO_SHIFT                        (9U)
/*! CLKO - Clock Output
 *  0b0..The 32 kHz clock is output to other peripherals.
 *  0b1..The 32 kHz clock is not output to other peripherals.
 */
#define RTC_CR_CLKO(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK)

#define RTC_CR_CPE_MASK                          (0x3000000U)
#define RTC_CR_CPE_SHIFT                         (24U)
/*! CPE - Clock Pin Enable
 *  0b00..The RTC_CLKOUT function is disabled.
 *  0b01..Enable RTC_CLKOUT function on RTC_TAMPER[1].
 *  0b10..Enable RTC_CLKOUT function on RTC_TAMPER[2].
 *  0b11..Enable RTC_CLKOUT function on RTC_TAMPER[3].
 */
#define RTC_CR_CPE(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_CR_CPE_SHIFT)) & RTC_CR_CPE_MASK)
/*! @} */

/*! @name SR - RTC Status Register */
/*! @{ */

#define RTC_SR_TIF_MASK                          (0x1U)
#define RTC_SR_TIF_SHIFT                         (0U)
/*! TIF - Time Invalid Flag
 *  0b0..Time is valid.
 *  0b1..Time is invalid and time counter is read as zero.
 */
#define RTC_SR_TIF(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK)

#define RTC_SR_TOF_MASK                          (0x2U)
#define RTC_SR_TOF_SHIFT                         (1U)
/*! TOF - Time Overflow Flag
 *  0b0..Time overflow has not occurred.
 *  0b1..Time overflow has occurred and time counter is read as zero.
 */
#define RTC_SR_TOF(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK)

#define RTC_SR_TAF_MASK                          (0x4U)
#define RTC_SR_TAF_SHIFT                         (2U)
/*! TAF - Time Alarm Flag
 *  0b0..Time alarm has not occurred.
 *  0b1..Time alarm has occurred.
 */
#define RTC_SR_TAF(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK)

#define RTC_SR_MOF_MASK                          (0x8U)
#define RTC_SR_MOF_SHIFT                         (3U)
/*! MOF - Monotonic Overflow Flag
 *  0b0..Monotonic counter overflow has not occurred.
 *  0b1..Monotonic counter overflow has occurred and monotonic counter is read as zero.
 */
#define RTC_SR_MOF(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_SR_MOF_SHIFT)) & RTC_SR_MOF_MASK)

#define RTC_SR_TCE_MASK                          (0x10U)
#define RTC_SR_TCE_SHIFT                         (4U)
/*! TCE - Time Counter Enable
 *  0b0..Time counter is disabled.
 *  0b1..Time counter is enabled.
 */
#define RTC_SR_TCE(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK)

#define RTC_SR_TIDF_MASK                         (0x80U)
#define RTC_SR_TIDF_SHIFT                        (7U)
/*! TIDF - Tamper Interrupt Detect Flag
 *  0b0..Tamper interrupt has not asserted.
 *  0b1..Tamper interrupt has asserted.
 */
#define RTC_SR_TIDF(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIDF_SHIFT)) & RTC_SR_TIDF_MASK)
/*! @} */

/*! @name LR - RTC Lock Register */
/*! @{ */

#define RTC_LR_TCL_MASK                          (0x8U)
#define RTC_LR_TCL_SHIFT                         (3U)
/*! TCL - Time Compensation Lock
 *  0b0..Time Compensation Register is locked and writes are ignored.
 *  0b1..Time Compensation Register is not locked and writes complete as normal.
 */
#define RTC_LR_TCL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK)

#define RTC_LR_CRL_MASK                          (0x10U)
#define RTC_LR_CRL_SHIFT                         (4U)
/*! CRL - Control Register Lock
 *  0b0..Control Register is locked and writes are ignored.
 *  0b1..Control Register is not locked and writes complete as normal.
 */
#define RTC_LR_CRL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK)

#define RTC_LR_SRL_MASK                          (0x20U)
#define RTC_LR_SRL_SHIFT                         (5U)
/*! SRL - Status Register Lock
 *  0b0..Status Register is locked and writes are ignored.
 *  0b1..Status Register is not locked and writes complete as normal.
 */
#define RTC_LR_SRL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK)

#define RTC_LR_LRL_MASK                          (0x40U)
#define RTC_LR_LRL_SHIFT                         (6U)
/*! LRL - Lock Register Lock
 *  0b0..Lock Register is locked and writes are ignored.
 *  0b1..Lock Register is not locked and writes complete as normal.
 */
#define RTC_LR_LRL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK)

#define RTC_LR_TTSL_MASK                         (0x100U)
#define RTC_LR_TTSL_SHIFT                        (8U)
/*! TTSL - Tamper Time Seconds Lock
 *  0b0..Tamper Time Seconds Register is locked and writes are ignored.
 *  0b1..Tamper Time Seconds Register is not locked and writes complete as normal.
 */
#define RTC_LR_TTSL(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_LR_TTSL_SHIFT)) & RTC_LR_TTSL_MASK)

#define RTC_LR_MEL_MASK                          (0x200U)
#define RTC_LR_MEL_SHIFT                         (9U)
/*! MEL - Monotonic Enable Lock
 *  0b0..Monotonic Enable Register is locked and writes are ignored.
 *  0b1..Monotonic Enable Register is not locked and writes complete as normal.
 */
#define RTC_LR_MEL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_MEL_SHIFT)) & RTC_LR_MEL_MASK)

#define RTC_LR_MCLL_MASK                         (0x400U)
#define RTC_LR_MCLL_SHIFT                        (10U)
/*! MCLL - Monotonic Counter Low Lock
 *  0b0..Monotonic Counter Low Register is locked and writes are ignored.
 *  0b1..Monotonic Counter Low Register is not locked and writes complete as normal.
 */
#define RTC_LR_MCLL(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_LR_MCLL_SHIFT)) & RTC_LR_MCLL_MASK)

#define RTC_LR_MCHL_MASK                         (0x800U)
#define RTC_LR_MCHL_SHIFT                        (11U)
/*! MCHL - Monotonic Counter High Lock
 *  0b0..Monotonic Counter High Register is locked and writes are ignored.
 *  0b1..Monotonic Counter High Register is not locked and writes complete as normal.
 */
#define RTC_LR_MCHL(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_LR_MCHL_SHIFT)) & RTC_LR_MCHL_MASK)

#define RTC_LR_TDL_MASK                          (0x2000U)
#define RTC_LR_TDL_SHIFT                         (13U)
/*! TDL - Tamper Detect Lock
 *  0b0..Tamper Detect Register is locked and writes are ignored.
 *  0b1..Tamper Detect Register is not locked and writes complete as normal.
 */
#define RTC_LR_TDL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_TDL_SHIFT)) & RTC_LR_TDL_MASK)

#define RTC_LR_TIL_MASK                          (0x8000U)
#define RTC_LR_TIL_SHIFT                         (15U)
/*! TIL - Tamper Interrupt Lock
 *  0b0..Tamper Interrupt Register is locked and writes are ignored.
 *  0b1..Tamper Interrupt Register is not locked and writes complete as normal.
 */
#define RTC_LR_TIL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_TIL_SHIFT)) & RTC_LR_TIL_MASK)

#define RTC_LR_PCL_MASK                          (0xF0000U)
#define RTC_LR_PCL_SHIFT                         (16U)
/*! PCL - Pin Configuration Lock
 */
#define RTC_LR_PCL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_PCL_SHIFT)) & RTC_LR_PCL_MASK)
/*! @} */

/*! @name IER - RTC Interrupt Enable Register */
/*! @{ */

#define RTC_IER_TIIE_MASK                        (0x1U)
#define RTC_IER_TIIE_SHIFT                       (0U)
/*! TIIE - Time Invalid Interrupt Enable
 *  0b0..Time invalid flag does not generate an interrupt.
 *  0b1..Time invalid flag does generate an interrupt.
 */
#define RTC_IER_TIIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK)

#define RTC_IER_TOIE_MASK                        (0x2U)
#define RTC_IER_TOIE_SHIFT                       (1U)
/*! TOIE - Time Overflow Interrupt Enable
 *  0b0..Time overflow flag does not generate an interrupt.
 *  0b1..Time overflow flag does generate an interrupt.
 */
#define RTC_IER_TOIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK)

#define RTC_IER_TAIE_MASK                        (0x4U)
#define RTC_IER_TAIE_SHIFT                       (2U)
/*! TAIE - Time Alarm Interrupt Enable
 *  0b0..Time alarm flag does not generate an interrupt.
 *  0b1..Time alarm flag does generate an interrupt.
 */
#define RTC_IER_TAIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK)

#define RTC_IER_MOIE_MASK                        (0x8U)
#define RTC_IER_MOIE_SHIFT                       (3U)
/*! MOIE - Monotonic Overflow Interrupt Enable
 *  0b0..Monotonic overflow flag does not generate an interrupt.
 *  0b1..Monotonic overflow flag does generate an interrupt.
 */
#define RTC_IER_MOIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_MOIE_SHIFT)) & RTC_IER_MOIE_MASK)

#define RTC_IER_TSIE_MASK                        (0x10U)
#define RTC_IER_TSIE_SHIFT                       (4U)
/*! TSIE - Time Seconds Interrupt Enable
 *  0b0..Seconds interrupt is disabled.
 *  0b1..Seconds interrupt is enabled.
 */
#define RTC_IER_TSIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK)

#define RTC_IER_WPON_MASK                        (0x80U)
#define RTC_IER_WPON_SHIFT                       (7U)
/*! WPON - Wakeup Pin On
 *  0b0..No effect.
 *  0b1..If the RTC_WAKEUP pin is enabled, then the pin will assert.
 */
#define RTC_IER_WPON(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK)

#define RTC_IER_TSIC_MASK                        (0x70000U)
#define RTC_IER_TSIC_SHIFT                       (16U)
/*! TSIC - Timer Seconds Interrupt Configuration
 *  0b000..1 Hz.
 *  0b001..2 Hz.
 *  0b010..4 Hz.
 *  0b011..8 Hz.
 *  0b100..16 Hz.
 *  0b101..32 Hz.
 *  0b110..64 Hz.
 *  0b111..128 Hz.
 */
#define RTC_IER_TSIC(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIC_SHIFT)) & RTC_IER_TSIC_MASK)
/*! @} */

/*! @name TTSR - RTC Tamper Time Seconds Register */
/*! @{ */

#define RTC_TTSR_TTS_MASK                        (0xFFFFFFFFU)
#define RTC_TTSR_TTS_SHIFT                       (0U)
/*! TTS - Tamper Time Seconds
 */
#define RTC_TTSR_TTS(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_TTSR_TTS_SHIFT)) & RTC_TTSR_TTS_MASK)
/*! @} */

/*! @name MER - RTC Monotonic Enable Register */
/*! @{ */

#define RTC_MER_MCE_MASK                         (0x10U)
#define RTC_MER_MCE_SHIFT                        (4U)
/*! MCE - Monotonic Counter Enable
 *  0b0..Writes to the monotonic counter load the counter with the value written.
 *  0b1..Writes to the monotonic counter increment the counter.
 */
#define RTC_MER_MCE(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_MER_MCE_SHIFT)) & RTC_MER_MCE_MASK)
/*! @} */

/*! @name MCLR - RTC Monotonic Counter Low Register */
/*! @{ */

#define RTC_MCLR_MCL_MASK                        (0xFFFFFFFFU)
#define RTC_MCLR_MCL_SHIFT                       (0U)
/*! MCL - Monotonic Counter Low
 */
#define RTC_MCLR_MCL(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_MCLR_MCL_SHIFT)) & RTC_MCLR_MCL_MASK)
/*! @} */

/*! @name MCHR - RTC Monotonic Counter High Register */
/*! @{ */

#define RTC_MCHR_MCH_MASK                        (0xFFFFFFFFU)
#define RTC_MCHR_MCH_SHIFT                       (0U)
/*! MCH - Monotonic Counter High
 */
#define RTC_MCHR_MCH(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_MCHR_MCH_SHIFT)) & RTC_MCHR_MCH_MASK)
/*! @} */

/*! @name TDR - RTC Tamper Detect Register */
/*! @{ */

#define RTC_TDR_LCTF_MASK                        (0x10U)
#define RTC_TDR_LCTF_SHIFT                       (4U)
/*! LCTF - Loss of Clock Tamper Flag
 *  0b0..Tamper not detected.
 *  0b1..Loss of Clock tamper detected.
 */
#define RTC_TDR_LCTF(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_TDR_LCTF_SHIFT)) & RTC_TDR_LCTF_MASK)

#define RTC_TDR_STF_MASK                         (0x20U)
#define RTC_TDR_STF_SHIFT                        (5U)
/*! STF - Security Tamper Flag
 *  0b0..Tamper not detected.
 *  0b1..Security module tamper detected.
 */
#define RTC_TDR_STF(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TDR_STF_SHIFT)) & RTC_TDR_STF_MASK)

#define RTC_TDR_FSF_MASK                         (0x40U)
#define RTC_TDR_FSF_SHIFT                        (6U)
/*! FSF - Flash Security Flag
 *  0b0..Tamper not detected.
 *  0b1..Flash security tamper detected.
 */
#define RTC_TDR_FSF(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TDR_FSF_SHIFT)) & RTC_TDR_FSF_MASK)

#define RTC_TDR_TMF_MASK                         (0x80U)
#define RTC_TDR_TMF_SHIFT                        (7U)
/*! TMF - Test Mode Flag
 *  0b0..Tamper not detected.
 *  0b1..Test mode tamper detected.
 */
#define RTC_TDR_TMF(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TDR_TMF_SHIFT)) & RTC_TDR_TMF_MASK)

#define RTC_TDR_TPF_MASK                         (0xF0000U)
#define RTC_TDR_TPF_SHIFT                        (16U)
/*! TPF - Tamper Pin Flag
 */
#define RTC_TDR_TPF(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TDR_TPF_SHIFT)) & RTC_TDR_TPF_MASK)
/*! @} */

/*! @name TIR - RTC Tamper Interrupt Register */
/*! @{ */

#define RTC_TIR_LCIE_MASK                        (0x10U)
#define RTC_TIR_LCIE_SHIFT                       (4U)
/*! LCIE - Loss of Clock Interrupt Enable
 *  0b0..Interrupt disabled.
 *  0b1..An interrupt is generated when the loss of clock flag is set.
 */
#define RTC_TIR_LCIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_TIR_LCIE_SHIFT)) & RTC_TIR_LCIE_MASK)

#define RTC_TIR_SIE_MASK                         (0x20U)
#define RTC_TIR_SIE_SHIFT                        (5U)
/*! SIE - Security Module Interrupt Enable
 *  0b0..Interrupt disabled.
 *  0b1..An interrupt is generated when the security module flag is set.
 */
#define RTC_TIR_SIE(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TIR_SIE_SHIFT)) & RTC_TIR_SIE_MASK)

#define RTC_TIR_FSIE_MASK                        (0x40U)
#define RTC_TIR_FSIE_SHIFT                       (6U)
/*! FSIE - Flash Security Interrupt Enable
 *  0b0..Interrupt disabled.
 *  0b1..An interrupt is generated when the flash security flag is set.
 */
#define RTC_TIR_FSIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_TIR_FSIE_SHIFT)) & RTC_TIR_FSIE_MASK)

#define RTC_TIR_TMIE_MASK                        (0x80U)
#define RTC_TIR_TMIE_SHIFT                       (7U)
/*! TMIE - Test Mode Interrupt Enable
 *  0b0..Interrupt disabled.
 *  0b1..An interrupt is generated when the test mode flag is set.
 */
#define RTC_TIR_TMIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_TIR_TMIE_SHIFT)) & RTC_TIR_TMIE_MASK)

#define RTC_TIR_TPIE_MASK                        (0xF0000U)
#define RTC_TIR_TPIE_SHIFT                       (16U)
/*! TPIE - Tamper Pin Interrupt Enable
 *  0b0000..Interrupt disabled.
 *  0b0001..An interrupt is generated when the corresponding tamper pin flag is set.
 */
#define RTC_TIR_TPIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_TIR_TPIE_SHIFT)) & RTC_TIR_TPIE_MASK)
/*! @} */

/*! @name PCR - RTC Pin Configuration Register */
/*! @{ */

#define RTC_PCR_TPE_MASK                         (0x1000000U)
#define RTC_PCR_TPE_SHIFT                        (24U)
/*! TPE - Tamper Pull Enable
 *  0b0..Pull resistor is disabled on tamper pin.
 *  0b1..Pull resistor is enabled on tamper pin.
 */
#define RTC_PCR_TPE(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_PCR_TPE_SHIFT)) & RTC_PCR_TPE_MASK)

#define RTC_PCR_TPS_MASK                         (0x2000000U)
#define RTC_PCR_TPS_SHIFT                        (25U)
/*! TPS - Tamper Pull Select
 *  0b0..Tamper pin pull resistor direction will assert the tamper pin.
 *  0b1..Tamper pin pull resistor direction will negate the tamper pin.
 */
#define RTC_PCR_TPS(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_PCR_TPS_SHIFT)) & RTC_PCR_TPS_MASK)

#define RTC_PCR_TFE_MASK                         (0x4000000U)
#define RTC_PCR_TFE_SHIFT                        (26U)
/*! TFE - Tamper Filter Enable
 *  0b0..Input filter is disabled on the tamper pin.
 *  0b1..Input filter is enabled on the tamper pin.
 */
#define RTC_PCR_TFE(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_PCR_TFE_SHIFT)) & RTC_PCR_TFE_MASK)

#define RTC_PCR_TPP_MASK                         (0x8000000U)
#define RTC_PCR_TPP_SHIFT                        (27U)
/*! TPP - Tamper Pin Polarity
 *  0b0..Tamper pin is active high.
 *  0b1..Tamper pin is active low.
 */
#define RTC_PCR_TPP(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_PCR_TPP_SHIFT)) & RTC_PCR_TPP_MASK)

#define RTC_PCR_TPID_MASK                        (0x80000000U)
#define RTC_PCR_TPID_SHIFT                       (31U)
/*! TPID - Tamper Pin Input Data
 *  0b0..Tamper pin input data is logic zero.
 *  0b1..Tamper pin input data is logic one.
 */
#define RTC_PCR_TPID(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_PCR_TPID_SHIFT)) & RTC_PCR_TPID_MASK)
/*! @} */

/* The count of RTC_PCR */
#define RTC_PCR_COUNT                            (4U)

/*! @name WAR - RTC Write Access Register */
/*! @{ */

#define RTC_WAR_TSRW_MASK                        (0x1U)
#define RTC_WAR_TSRW_SHIFT                       (0U)
/*! TSRW - Time Seconds Register Write
 *  0b0..Writes to the Time Seconds Register are ignored.
 *  0b1..Writes to the Time Seconds Register complete as normal.
 */
#define RTC_WAR_TSRW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TSRW_SHIFT)) & RTC_WAR_TSRW_MASK)

#define RTC_WAR_TPRW_MASK                        (0x2U)
#define RTC_WAR_TPRW_SHIFT                       (1U)
/*! TPRW - Time Prescaler Register Write
 *  0b0..Writes to the Time Prescaler Register are ignored.
 *  0b1..Writes to the Time Prescaler Register complete as normal.
 */
#define RTC_WAR_TPRW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TPRW_SHIFT)) & RTC_WAR_TPRW_MASK)

#define RTC_WAR_TARW_MASK                        (0x4U)
#define RTC_WAR_TARW_SHIFT                       (2U)
/*! TARW - Time Alarm Register Write
 *  0b0..Writes to the Time Alarm Register are ignored.
 *  0b1..Writes to the Time Alarm Register complete as normal.
 */
#define RTC_WAR_TARW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TARW_SHIFT)) & RTC_WAR_TARW_MASK)

#define RTC_WAR_TCRW_MASK                        (0x8U)
#define RTC_WAR_TCRW_SHIFT                       (3U)
/*! TCRW - Time Compensation Register Write
 *  0b0..Writes to the Time Compensation Register are ignored.
 *  0b1..Writes to the Time Compensation Register complete as normal.
 */
#define RTC_WAR_TCRW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TCRW_SHIFT)) & RTC_WAR_TCRW_MASK)

#define RTC_WAR_CRW_MASK                         (0x10U)
#define RTC_WAR_CRW_SHIFT                        (4U)
/*! CRW - Control Register Write
 *  0b0..Writes to the Control Register are ignored.
 *  0b1..Writes to the Control Register complete as normal.
 */
#define RTC_WAR_CRW(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_WAR_CRW_SHIFT)) & RTC_WAR_CRW_MASK)

#define RTC_WAR_SRW_MASK                         (0x20U)
#define RTC_WAR_SRW_SHIFT                        (5U)
/*! SRW - Status Register Write
 *  0b0..Writes to the Status Register are ignored.
 *  0b1..Writes to the Status Register complete as normal.
 */
#define RTC_WAR_SRW(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_WAR_SRW_SHIFT)) & RTC_WAR_SRW_MASK)

#define RTC_WAR_LRW_MASK                         (0x40U)
#define RTC_WAR_LRW_SHIFT                        (6U)
/*! LRW - Lock Register Write
 *  0b0..Writes to the Lock Register are ignored.
 *  0b1..Writes to the Lock Register complete as normal.
 */
#define RTC_WAR_LRW(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_WAR_LRW_SHIFT)) & RTC_WAR_LRW_MASK)

#define RTC_WAR_IERW_MASK                        (0x80U)
#define RTC_WAR_IERW_SHIFT                       (7U)
/*! IERW - Interrupt Enable Register Write
 *  0b0..Writes to the Interrupt Enable Register are ignored.
 *  0b1..Writes to the Interrupt Enable Register complete as normal.
 */
#define RTC_WAR_IERW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_IERW_SHIFT)) & RTC_WAR_IERW_MASK)

#define RTC_WAR_TTSW_MASK                        (0x100U)
#define RTC_WAR_TTSW_SHIFT                       (8U)
/*! TTSW - Tamper Time Seconds Write
 *  0b0..Writes to the Tamper Time Seconds Register are ignored.
 *  0b1..Writes to the Tamper Time Seconds Register complete as normal.
 */
#define RTC_WAR_TTSW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TTSW_SHIFT)) & RTC_WAR_TTSW_MASK)

#define RTC_WAR_MERW_MASK                        (0x200U)
#define RTC_WAR_MERW_SHIFT                       (9U)
/*! MERW - Monotonic Enable Register Write
 *  0b0..Writes to the Monotonic Enable Register are ignored.
 *  0b1..Writes to the Monotonic Enable Register complete as normal.
 */
#define RTC_WAR_MERW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MERW_SHIFT)) & RTC_WAR_MERW_MASK)

#define RTC_WAR_MCLW_MASK                        (0x400U)
#define RTC_WAR_MCLW_SHIFT                       (10U)
/*! MCLW - Monotonic Counter Low Write
 *  0b0..Writes to the Monotonic Counter Low Register are ignored.
 *  0b1..Writes to the Monotonic Counter Low Register complete as normal.
 */
#define RTC_WAR_MCLW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MCLW_SHIFT)) & RTC_WAR_MCLW_MASK)

#define RTC_WAR_MCHW_MASK                        (0x800U)
#define RTC_WAR_MCHW_SHIFT                       (11U)
/*! MCHW - Monotonic Counter High Write
 *  0b0..Writes to the Monotonic Counter High Register are ignored.
 *  0b1..Writes to the Monotonic Counter High Register complete as normal.
 */
#define RTC_WAR_MCHW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MCHW_SHIFT)) & RTC_WAR_MCHW_MASK)

#define RTC_WAR_TDRW_MASK                        (0x2000U)
#define RTC_WAR_TDRW_SHIFT                       (13U)
/*! TDRW - Tamper Detect Register Write
 *  0b0..Writes to the Tamper Detect Register are ignored.
 *  0b1..Writes to the Tamper Detect Register complete as normal.
 */
#define RTC_WAR_TDRW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TDRW_SHIFT)) & RTC_WAR_TDRW_MASK)

#define RTC_WAR_TIRW_MASK                        (0x8000U)
#define RTC_WAR_TIRW_SHIFT                       (15U)
/*! TIRW - Tamper Interrupt Register Write
 *  0b0..Writes to the Tamper Interrupt Register are ignored.
 *  0b1..Writes to the Tamper Interrupt Register complete as normal.
 */
#define RTC_WAR_TIRW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TIRW_SHIFT)) & RTC_WAR_TIRW_MASK)

#define RTC_WAR_PCRW_MASK                        (0xF0000U)
#define RTC_WAR_PCRW_SHIFT                       (16U)
/*! PCRW - Pin Configuration Register Write
 */
#define RTC_WAR_PCRW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_PCRW_SHIFT)) & RTC_WAR_PCRW_MASK)
/*! @} */

/*! @name RAR - RTC Read Access Register */
/*! @{ */

#define RTC_RAR_TSRR_MASK                        (0x1U)
#define RTC_RAR_TSRR_SHIFT                       (0U)
/*! TSRR - Time Seconds Register Read
 *  0b0..Reads to the Time Seconds Register are ignored.
 *  0b1..Reads to the Time Seconds Register complete as normal.
 */
#define RTC_RAR_TSRR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TSRR_SHIFT)) & RTC_RAR_TSRR_MASK)

#define RTC_RAR_TPRR_MASK                        (0x2U)
#define RTC_RAR_TPRR_SHIFT                       (1U)
/*! TPRR - Time Prescaler Register Read
 *  0b0..Reads to the Time Pprescaler Register are ignored.
 *  0b1..Reads to the Time Prescaler Register complete as normal.
 */
#define RTC_RAR_TPRR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TPRR_SHIFT)) & RTC_RAR_TPRR_MASK)

#define RTC_RAR_TARR_MASK                        (0x4U)
#define RTC_RAR_TARR_SHIFT                       (2U)
/*! TARR - Time Alarm Register Read
 *  0b0..Reads to the Time Alarm Register are ignored.
 *  0b1..Reads to the Time Alarm Register complete as normal.
 */
#define RTC_RAR_TARR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TARR_SHIFT)) & RTC_RAR_TARR_MASK)

#define RTC_RAR_TCRR_MASK                        (0x8U)
#define RTC_RAR_TCRR_SHIFT                       (3U)
/*! TCRR - Time Compensation Register Read
 *  0b0..Reads to the Time Compensation Register are ignored.
 *  0b1..Reads to the Time Compensation Register complete as normal.
 */
#define RTC_RAR_TCRR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TCRR_SHIFT)) & RTC_RAR_TCRR_MASK)

#define RTC_RAR_CRR_MASK                         (0x10U)
#define RTC_RAR_CRR_SHIFT                        (4U)
/*! CRR - Control Register Read
 *  0b0..Reads to the Control Register are ignored.
 *  0b1..Reads to the Control Register complete as normal.
 */
#define RTC_RAR_CRR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_RAR_CRR_SHIFT)) & RTC_RAR_CRR_MASK)

#define RTC_RAR_SRR_MASK                         (0x20U)
#define RTC_RAR_SRR_SHIFT                        (5U)
/*! SRR - Status Register Read
 *  0b0..Reads to the Status Register are ignored.
 *  0b1..Reads to the Status Register complete as normal.
 */
#define RTC_RAR_SRR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_RAR_SRR_SHIFT)) & RTC_RAR_SRR_MASK)

#define RTC_RAR_LRR_MASK                         (0x40U)
#define RTC_RAR_LRR_SHIFT                        (6U)
/*! LRR - Lock Register Read
 *  0b0..Reads to the Lock Register are ignored.
 *  0b1..Reads to the Lock Register complete as normal.
 */
#define RTC_RAR_LRR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_RAR_LRR_SHIFT)) & RTC_RAR_LRR_MASK)

#define RTC_RAR_IERR_MASK                        (0x80U)
#define RTC_RAR_IERR_SHIFT                       (7U)
/*! IERR - Interrupt Enable Register Read
 *  0b0..Reads to the Interrupt Enable Register are ignored.
 *  0b1..Reads to the Interrupt Enable Register complete as normal.
 */
#define RTC_RAR_IERR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_IERR_SHIFT)) & RTC_RAR_IERR_MASK)

#define RTC_RAR_TTSR_MASK                        (0x100U)
#define RTC_RAR_TTSR_SHIFT                       (8U)
/*! TTSR - Tamper Time Seconds Read
 *  0b0..Reads to the Tamper Time Seconds Register are ignored.
 *  0b1..Reads to the Tamper Time Seconds Register complete as normal.
 */
#define RTC_RAR_TTSR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TTSR_SHIFT)) & RTC_RAR_TTSR_MASK)

#define RTC_RAR_MERR_MASK                        (0x200U)
#define RTC_RAR_MERR_SHIFT                       (9U)
/*! MERR - Monotonic Enable Register Read
 *  0b0..Reads to the Monotonic Enable Register are ignored.
 *  0b1..Reads to the Monotonic Enable Register complete as normal.
 */
#define RTC_RAR_MERR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MERR_SHIFT)) & RTC_RAR_MERR_MASK)

#define RTC_RAR_MCLR_MASK                        (0x400U)
#define RTC_RAR_MCLR_SHIFT                       (10U)
/*! MCLR - Monotonic Counter Low Read
 *  0b0..Reads to the Monotonic Counter Low Register are ignored.
 *  0b1..Reads to the Monotonic Counter Low Register complete as normal.
 */
#define RTC_RAR_MCLR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MCLR_SHIFT)) & RTC_RAR_MCLR_MASK)

#define RTC_RAR_MCHR_MASK                        (0x800U)
#define RTC_RAR_MCHR_SHIFT                       (11U)
/*! MCHR - Monotonic Counter High Read
 *  0b0..Reads to the Monotonic Counter High Register are ignored.
 *  0b1..Reads to the Monotonic Counter High Register complete as normal.
 */
#define RTC_RAR_MCHR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MCHR_SHIFT)) & RTC_RAR_MCHR_MASK)

#define RTC_RAR_TDRR_MASK                        (0x2000U)
#define RTC_RAR_TDRR_SHIFT                       (13U)
/*! TDRR - Tamper Detect Register Read
 *  0b0..Reads to the Tamper Detect Register are ignored.
 *  0b1..Reads to the Tamper Detect Register complete as normal.
 */
#define RTC_RAR_TDRR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TDRR_SHIFT)) & RTC_RAR_TDRR_MASK)

#define RTC_RAR_TIRR_MASK                        (0x8000U)
#define RTC_RAR_TIRR_SHIFT                       (15U)
/*! TIRR - Tamper Interrupt Register Read
 *  0b0..Reads to the Tamper Interrupt Register are ignored.
 *  0b1..Reads to the Tamper Interrupt Register complete as normal.
 */
#define RTC_RAR_TIRR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TIRR_SHIFT)) & RTC_RAR_TIRR_MASK)

#define RTC_RAR_PCRR_MASK                        (0xF0000U)
#define RTC_RAR_PCRR_SHIFT                       (16U)
/*! PCRR - Pin Configuration Register Read
 */
#define RTC_RAR_PCRR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_PCRR_SHIFT)) & RTC_RAR_PCRR_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group RTC_Register_Masks */


/* RTC - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral RTC base address */
  #define RTC_BASE                                 (0x5002C000u)
  /** Peripheral RTC base address */
  #define RTC_BASE_NS                              (0x4002C000u)
  /** Peripheral RTC base pointer */
  #define RTC                                      ((RTC_Type *)RTC_BASE)
  /** Peripheral RTC base pointer */
  #define RTC_NS                                   ((RTC_Type *)RTC_BASE_NS)
  /** Array initializer of RTC peripheral base addresses */
  #define RTC_BASE_ADDRS                           { RTC_BASE }
  /** Array initializer of RTC peripheral base pointers */
  #define RTC_BASE_PTRS                            { RTC }
  /** Array initializer of RTC peripheral base addresses */
  #define RTC_BASE_ADDRS_NS                        { RTC_BASE_NS }
  /** Array initializer of RTC peripheral base pointers */
  #define RTC_BASE_PTRS_NS                         { RTC_NS }
#else
  /** Peripheral RTC base address */
  #define RTC_BASE                                 (0x4002C000u)
  /** Peripheral RTC base pointer */
  #define RTC                                      ((RTC_Type *)RTC_BASE)
  /** Array initializer of RTC peripheral base addresses */
  #define RTC_BASE_ADDRS                           { RTC_BASE }
  /** Array initializer of RTC peripheral base pointers */
  #define RTC_BASE_PTRS                            { RTC }
#endif
/** Interrupt vectors for the RTC peripheral type */
#define RTC_IRQS                                 { RTC_Alarm_IRQn }
#define RTC_SECONDS_IRQS                         { RTC_Seconds_IRQn }

/*!
 * @}
 */ /* end of group RTC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- RX_PACKET_RAM Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup RX_PACKET_RAM_Peripheral_Access_Layer RX_PACKET_RAM Peripheral Access Layer
 * @{
 */

/** RX_PACKET_RAM - Register Layout Typedef */
typedef struct {
  __IO uint32_t PACKET_RAM[512];                   /**< Shared Packet RAM for multiple Link Layer usage., array offset: 0x0, array step: 0x4 */
} RX_PACKET_RAM_Type;

/* ----------------------------------------------------------------------------
   -- RX_PACKET_RAM Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup RX_PACKET_RAM_Register_Masks RX_PACKET_RAM Register Masks
 * @{
 */

/*! @name PACKET_RAM - Shared Packet RAM for multiple Link Layer usage. */
/*! @{ */

#define RX_PACKET_RAM_PACKET_RAM_RAM_MASK        (0xFFFFFFFFU)
#define RX_PACKET_RAM_PACKET_RAM_RAM_SHIFT       (0U)
/*! RAM - One entry in the packet RAM
 */
#define RX_PACKET_RAM_PACKET_RAM_RAM(x)          (((uint32_t)(((uint32_t)(x)) << RX_PACKET_RAM_PACKET_RAM_RAM_SHIFT)) & RX_PACKET_RAM_PACKET_RAM_RAM_MASK)
/*! @} */

/* The count of RX_PACKET_RAM_PACKET_RAM */
#define RX_PACKET_RAM_PACKET_RAM_COUNT           (512U)


/*!
 * @}
 */ /* end of group RX_PACKET_RAM_Register_Masks */


/* RX_PACKET_RAM - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral RX_PACKET_RAM base address */
  #define RX_PACKET_RAM_BASE                       (0x58A09000u)
  /** Peripheral RX_PACKET_RAM base address */
  #define RX_PACKET_RAM_BASE_NS                    (0x48A09000u)
  /** Peripheral RX_PACKET_RAM base pointer */
  #define RX_PACKET_RAM                            ((RX_PACKET_RAM_Type *)RX_PACKET_RAM_BASE)
  /** Peripheral RX_PACKET_RAM base pointer */
  #define RX_PACKET_RAM_NS                         ((RX_PACKET_RAM_Type *)RX_PACKET_RAM_BASE_NS)
  /** Array initializer of RX_PACKET_RAM peripheral base addresses */
  #define RX_PACKET_RAM_BASE_ADDRS                 { RX_PACKET_RAM_BASE }
  /** Array initializer of RX_PACKET_RAM peripheral base pointers */
  #define RX_PACKET_RAM_BASE_PTRS                  { RX_PACKET_RAM }
  /** Array initializer of RX_PACKET_RAM peripheral base addresses */
  #define RX_PACKET_RAM_BASE_ADDRS_NS              { RX_PACKET_RAM_BASE_NS }
  /** Array initializer of RX_PACKET_RAM peripheral base pointers */
  #define RX_PACKET_RAM_BASE_PTRS_NS               { RX_PACKET_RAM_NS }
#else
  /** Peripheral RX_PACKET_RAM base address */
  #define RX_PACKET_RAM_BASE                       (0x48A09000u)
  /** Peripheral RX_PACKET_RAM base pointer */
  #define RX_PACKET_RAM                            ((RX_PACKET_RAM_Type *)RX_PACKET_RAM_BASE)
  /** Array initializer of RX_PACKET_RAM peripheral base addresses */
  #define RX_PACKET_RAM_BASE_ADDRS                 { RX_PACKET_RAM_BASE }
  /** Array initializer of RX_PACKET_RAM peripheral base pointers */
  #define RX_PACKET_RAM_BASE_PTRS                  { RX_PACKET_RAM }
#endif

/*!
 * @}
 */ /* end of group RX_PACKET_RAM_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- SCG Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SCG_Peripheral_Access_Layer SCG Peripheral Access Layer
 * @{
 */

/** SCG - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
       uint8_t RESERVED_0[8];
  __I  uint32_t CSR;                               /**< Clock Status Register, offset: 0x10 */
  __IO uint32_t RCCR;                              /**< Run Clock Control Register, offset: 0x14 */
       uint8_t RESERVED_1[8];
  __IO uint32_t CLKOUTCNFG;                        /**< SCG CLKOUT Configuration Register, offset: 0x20 */
       uint8_t RESERVED_2[220];
  __IO uint32_t SOSCCSR;                           /**< System OSC Control Status Register, offset: 0x100 */
       uint8_t RESERVED_3[252];
  __IO uint32_t SIRCCSR;                           /**< Slow IRC Control Status Register, offset: 0x200 */
       uint8_t RESERVED_4[252];
  __IO uint32_t FIRCCSR;                           /**< Fast IRC Control Status Register, offset: 0x300 */
       uint8_t RESERVED_5[4];
  __IO uint32_t FIRCCFG;                           /**< Fast IRC Configuration Register, offset: 0x308 */
  __IO uint32_t FIRCTCFG;                          /**< Fast IRC Trim Configuration Register, offset: 0x30C */
       uint8_t RESERVED_6[8];
  __IO uint32_t FIRCSTAT;                          /**< Fast IRC Status Register, offset: 0x318 */
       uint8_t RESERVED_7[228];
  __IO uint32_t ROSCCSR;                           /**< RTC OSC Control Status Register, offset: 0x400 */
} SCG_Type;

/* ----------------------------------------------------------------------------
   -- SCG Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SCG_Register_Masks SCG Register Masks
 * @{
 */

/*! @name VERID - Version ID Register */
/*! @{ */

#define SCG_VERID_VERSION_MASK                   (0xFFFFFFFFU)
#define SCG_VERID_VERSION_SHIFT                  (0U)
/*! VERSION - SCG Version Number
 */
#define SCG_VERID_VERSION(x)                     (((uint32_t)(((uint32_t)(x)) << SCG_VERID_VERSION_SHIFT)) & SCG_VERID_VERSION_MASK)
/*! @} */

/*! @name PARAM - Parameter Register */
/*! @{ */

#define SCG_PARAM_CLKPRES_MASK                   (0xFFU)
#define SCG_PARAM_CLKPRES_SHIFT                  (0U)
/*! CLKPRES - Clock Present
 *  0b00000000-0b00000001..Reserved
 *  0bxxxxxx1x..System OSC (SOSC) is present.
 *  0bxxxxx1xx..Slow IRC (SIRC) is present.
 *  0bxxxx1xxx..Fast IRC (FIRC) is present.
 *  0bxxx1xxxx..RTC OSC (ROSC) is present.
 */
#define SCG_PARAM_CLKPRES(x)                     (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_CLKPRES_SHIFT)) & SCG_PARAM_CLKPRES_MASK)

#define SCG_PARAM_DIVPRES_MASK                   (0xF8000000U)
#define SCG_PARAM_DIVPRES_SHIFT                  (27U)
/*! DIVPRES - Divider Present
 *  0bxxxx1..System DIVSLOW is present.
 *  0bxxx1x..System DIVBUS is present.
 *  0b1xxxx..System DIVCORE is present.
 */
#define SCG_PARAM_DIVPRES(x)                     (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_DIVPRES_SHIFT)) & SCG_PARAM_DIVPRES_MASK)
/*! @} */

/*! @name CSR - Clock Status Register */
/*! @{ */

#define SCG_CSR_DIVSLOW_MASK                     (0xFU)
#define SCG_CSR_DIVSLOW_SHIFT                    (0U)
/*! DIVSLOW - Slow Clock Divide Ratio
 *  0b0000..Divide-by-1
 *  0b0001..Divide-by-2
 *  0b0010..Divide-by-3
 *  0b0011..Divide-by-4
 *  0b0100..Divide-by-5
 *  0b0101..Divide-by-6
 *  0b0110..Divide-by-7
 *  0b0111..Divide-by-8
 *  0b1000..Divide-by-9
 *  0b1001..Divide-by-10
 *  0b1010..Divide-by-11
 *  0b1011..Divide-by-12
 *  0b1100..Divide-by-13
 *  0b1101..Divide-by-14
 *  0b1110..Divide-by-15
 *  0b1111..Divide-by-16
 */
#define SCG_CSR_DIVSLOW(x)                       (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVSLOW_SHIFT)) & SCG_CSR_DIVSLOW_MASK)

#define SCG_CSR_DIVBUS_MASK                      (0xF0U)
#define SCG_CSR_DIVBUS_SHIFT                     (4U)
/*! DIVBUS - Bus Clock Divide Ratio
 *  0b0000..Divide-by-1
 *  0b0001..Divide-by-2
 *  0b0010..Divide-by-3
 *  0b0011..Divide-by-4
 *  0b0100..Divide-by-5
 *  0b0101..Divide-by-6
 *  0b0110..Divide-by-7
 *  0b0111..Divide-by-8
 *  0b1000..Divide-by-9
 *  0b1001..Divide-by-10
 *  0b1010..Divide-by-11
 *  0b1011..Divide-by-12
 *  0b1100..Divide-by-13
 *  0b1101..Divide-by-14
 *  0b1110..Divide-by-15
 *  0b1111..Divide-by-16
 */
#define SCG_CSR_DIVBUS(x)                        (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVBUS_SHIFT)) & SCG_CSR_DIVBUS_MASK)

#define SCG_CSR_DIVCORE_MASK                     (0xF0000U)
#define SCG_CSR_DIVCORE_SHIFT                    (16U)
/*! DIVCORE - Core Clock Divide Ratio
 *  0b0000..Divide-by-1
 *  0b0001..Divide-by-2
 *  0b0010..Divide-by-3
 *  0b0011..Divide-by-4
 *  0b0100..Divide-by-5
 *  0b0101..Divide-by-6
 *  0b0110..Divide-by-7
 *  0b0111..Divide-by-8
 *  0b1000..Divide-by-9
 *  0b1001..Divide-by-10
 *  0b1010..Divide-by-11
 *  0b1011..Divide-by-12
 *  0b1100..Divide-by-13
 *  0b1101..Divide-by-14
 *  0b1110..Divide-by-15
 *  0b1111..Divide-by-16
 */
#define SCG_CSR_DIVCORE(x)                       (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVCORE_SHIFT)) & SCG_CSR_DIVCORE_MASK)

#define SCG_CSR_SCS_MASK                         (0xF000000U)
#define SCG_CSR_SCS_SHIFT                        (24U)
/*! SCS - System Clock Source
 *  0b0000..Reserved
 *  0b0001..System OSC (SOSC_CLK)
 *  0b0010..Slow IRC (SIRC_CLK)
 *  0b0011..Fast IRC (FIRC_CLK)
 *  0b0100..RTC OSC (ROSC_CLK)
 *  0b0101..Reserved
 *  0b0110..Reserved
 *  0b0111..Reserved
 */
#define SCG_CSR_SCS(x)                           (((uint32_t)(((uint32_t)(x)) << SCG_CSR_SCS_SHIFT)) & SCG_CSR_SCS_MASK)
/*! @} */

/*! @name RCCR - Run Clock Control Register */
/*! @{ */

#define SCG_RCCR_DIVSLOW_MASK                    (0xFU)
#define SCG_RCCR_DIVSLOW_SHIFT                   (0U)
/*! DIVSLOW - Slow Clock Divide Ratio
 *  0b0000..Divide-by-1
 *  0b0001..Divide-by-2
 *  0b0010..Divide-by-3
 *  0b0011..Divide-by-4
 *  0b0100..Divide-by-5
 *  0b0101..Divide-by-6
 *  0b0110..Divide-by-7
 *  0b0111..Divide-by-8
 *  0b1000..Divide-by-9
 *  0b1001..Divide-by-10
 *  0b1010..Divide-by-11
 *  0b1011..Divide-by-12
 *  0b1100..Divide-by-13
 *  0b1101..Divide-by-14
 *  0b1110..Divide-by-15
 *  0b1111..Divide-by-16
 */
#define SCG_RCCR_DIVSLOW(x)                      (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_DIVSLOW_SHIFT)) & SCG_RCCR_DIVSLOW_MASK)

#define SCG_RCCR_DIVBUS_MASK                     (0xF0U)
#define SCG_RCCR_DIVBUS_SHIFT                    (4U)
/*! DIVBUS - Bus Clock Divide Ratio
 *  0b0000..Divide-by-1
 *  0b0001..Divide-by-2
 *  0b0010..Divide-by-3
 *  0b0011..Divide-by-4
 *  0b0100..Divide-by-5
 *  0b0101..Divide-by-6
 *  0b0110..Divide-by-7
 *  0b0111..Divide-by-8
 *  0b1000..Divide-by-9
 *  0b1001..Divide-by-10
 *  0b1010..Divide-by-11
 *  0b1011..Divide-by-12
 *  0b1100..Divide-by-13
 *  0b1101..Divide-by-14
 *  0b1110..Divide-by-15
 *  0b1111..Divide-by-16
 */
#define SCG_RCCR_DIVBUS(x)                       (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_DIVBUS_SHIFT)) & SCG_RCCR_DIVBUS_MASK)

#define SCG_RCCR_DIVCORE_MASK                    (0xF0000U)
#define SCG_RCCR_DIVCORE_SHIFT                   (16U)
/*! DIVCORE - Core Clock Divide Ratio
 *  0b0000..Divide-by-1
 *  0b0001..Divide-by-2
 *  0b0010..Divide-by-3
 *  0b0011..Divide-by-4
 *  0b0100..Divide-by-5
 *  0b0101..Divide-by-6
 *  0b0110..Divide-by-7
 *  0b0111..Divide-by-8
 *  0b1000..Divide-by-9
 *  0b1001..Divide-by-10
 *  0b1010..Divide-by-11
 *  0b1011..Divide-by-12
 *  0b1100..Divide-by-13
 *  0b1101..Divide-by-14
 *  0b1110..Divide-by-15
 *  0b1111..Divide-by-16
 */
#define SCG_RCCR_DIVCORE(x)                      (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_DIVCORE_SHIFT)) & SCG_RCCR_DIVCORE_MASK)

#define SCG_RCCR_SCS_MASK                        (0x7000000U)
#define SCG_RCCR_SCS_SHIFT                       (24U)
/*! SCS - System Clock Source
 *  0b000..Reserved
 *  0b001..System OSC (SOSC_CLK)
 *  0b010..Slow IRC (SIRC_CLK)
 *  0b011..Fast IRC (FIRC_CLK)
 *  0b100..RTC OSC (ROSC_CLK)
 *  0b101..Reserved
 *  0b110..Reserved
 *  0b111..Reserved
 */
#define SCG_RCCR_SCS(x)                          (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_SCS_SHIFT)) & SCG_RCCR_SCS_MASK)
/*! @} */

/*! @name CLKOUTCNFG - SCG CLKOUT Configuration Register */
/*! @{ */

#define SCG_CLKOUTCNFG_CLKOUTSEL_MASK            (0xF000000U)
#define SCG_CLKOUTCNFG_CLKOUTSEL_SHIFT           (24U)
/*! CLKOUTSEL - SCG Clkout Select
 *  0b0000..SCG SLOW Clock
 *  0b0001..System OSC (SOSC_CLK)
 *  0b0010..Slow IRC (SIRC_CLK)
 *  0b0011..Fast IRC (FIRC_CLK)
 *  0b0100..RTC OSC (ROSC_CLK)
 *  0b0101..Reserved
 *  0b0110..Reserved
 *  0b0111..Reserved
 *  0b1111..Reserved
 */
#define SCG_CLKOUTCNFG_CLKOUTSEL(x)              (((uint32_t)(((uint32_t)(x)) << SCG_CLKOUTCNFG_CLKOUTSEL_SHIFT)) & SCG_CLKOUTCNFG_CLKOUTSEL_MASK)
/*! @} */

/*! @name SOSCCSR - System OSC Control Status Register */
/*! @{ */

#define SCG_SOSCCSR_SOSCEN_MASK                  (0x1U)
#define SCG_SOSCCSR_SOSCEN_SHIFT                 (0U)
/*! SOSCEN - System OSC Enable
 *  0b0..System OSC is disabled
 *  0b1..System OSC is enabled
 */
#define SCG_SOSCCSR_SOSCEN(x)                    (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCEN_SHIFT)) & SCG_SOSCCSR_SOSCEN_MASK)

#define SCG_SOSCCSR_SOSCSTEN_MASK                (0x2U)
#define SCG_SOSCCSR_SOSCSTEN_SHIFT               (1U)
/*! SOSCSTEN - System OSC Stop Enable
 *  0b0..System OSC is disabled in any of the sleep modes
 *  0b1..System OSC is enabled in SLEEP mode only if SOSCEN=1. SOSCSTEN must be cleared when its power domain is
 *       going to enter Deep Sleep or Power Down mode.
 */
#define SCG_SOSCCSR_SOSCSTEN(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCSTEN_SHIFT)) & SCG_SOSCCSR_SOSCSTEN_MASK)

#define SCG_SOSCCSR_SOSCCM_MASK                  (0x10000U)
#define SCG_SOSCCSR_SOSCCM_SHIFT                 (16U)
/*! SOSCCM - System OSC Clock Monitor Enable
 *  0b0..System OSC Clock Monitor is disabled
 *  0b1..System OSC Clock Monitor is enabled
 */
#define SCG_SOSCCSR_SOSCCM(x)                    (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCCM_SHIFT)) & SCG_SOSCCSR_SOSCCM_MASK)

#define SCG_SOSCCSR_SOSCCMRE_MASK                (0x20000U)
#define SCG_SOSCCSR_SOSCCMRE_SHIFT               (17U)
/*! SOSCCMRE - System OSC Clock Monitor Reset Enable
 *  0b0..Clock Monitor generates interrupt when error detected
 *  0b1..Clock Monitor generates reset when error detected
 */
#define SCG_SOSCCSR_SOSCCMRE(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCCMRE_SHIFT)) & SCG_SOSCCSR_SOSCCMRE_MASK)

#define SCG_SOSCCSR_LK_MASK                      (0x800000U)
#define SCG_SOSCCSR_LK_SHIFT                     (23U)
/*! LK - Lock Register
 *  0b0..This Control Status Register can be written.
 *  0b1..This Control Status Register cannot be written.
 */
#define SCG_SOSCCSR_LK(x)                        (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_LK_SHIFT)) & SCG_SOSCCSR_LK_MASK)

#define SCG_SOSCCSR_SOSCVLD_MASK                 (0x1000000U)
#define SCG_SOSCCSR_SOSCVLD_SHIFT                (24U)
/*! SOSCVLD - System OSC Valid
 *  0b0..System OSC is not enabled or clock is not valid
 *  0b1..System OSC is enabled and output clock is valid
 */
#define SCG_SOSCCSR_SOSCVLD(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCVLD_SHIFT)) & SCG_SOSCCSR_SOSCVLD_MASK)

#define SCG_SOSCCSR_SOSCSEL_MASK                 (0x2000000U)
#define SCG_SOSCCSR_SOSCSEL_SHIFT                (25U)
/*! SOSCSEL - System OSC Selected
 *  0b0..System OSC is not the system clock source
 *  0b1..System OSC is the system clock source
 */
#define SCG_SOSCCSR_SOSCSEL(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCSEL_SHIFT)) & SCG_SOSCCSR_SOSCSEL_MASK)

#define SCG_SOSCCSR_SOSCERR_MASK                 (0x4000000U)
#define SCG_SOSCCSR_SOSCERR_SHIFT                (26U)
/*! SOSCERR - System OSC Clock Error
 *  0b0..System OSC Clock Monitor is disabled or has not detected an error
 *  0b1..System OSC Clock Monitor is enabled and detected an error
 */
#define SCG_SOSCCSR_SOSCERR(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCERR_SHIFT)) & SCG_SOSCCSR_SOSCERR_MASK)
/*! @} */

/*! @name SIRCCSR - Slow IRC Control Status Register */
/*! @{ */

#define SCG_SIRCCSR_SIRCSTEN_MASK                (0x2U)
#define SCG_SIRCCSR_SIRCSTEN_SHIFT               (1U)
/*! SIRCSTEN - Slow IRC Stop Enable
 *  0b0..Slow IRC is disabled in sleep modes
 *  0b1..Slow IRC is enabled in SLEEP mode
 */
#define SCG_SIRCCSR_SIRCSTEN(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCSTEN_SHIFT)) & SCG_SIRCCSR_SIRCSTEN_MASK)

#define SCG_SIRCCSR_LK_MASK                      (0x800000U)
#define SCG_SIRCCSR_LK_SHIFT                     (23U)
/*! LK - Lock Register
 *  0b0..Control Status Register can be written.
 *  0b1..Control Status Register cannot be written.
 */
#define SCG_SIRCCSR_LK(x)                        (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_LK_SHIFT)) & SCG_SIRCCSR_LK_MASK)

#define SCG_SIRCCSR_SIRCVLD_MASK                 (0x1000000U)
#define SCG_SIRCCSR_SIRCVLD_SHIFT                (24U)
/*! SIRCVLD - Slow IRC Valid
 *  0b0..Slow IRC is not enabled or clock is not valid
 *  0b1..Slow IRC is enabled and output clock is valid
 */
#define SCG_SIRCCSR_SIRCVLD(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCVLD_SHIFT)) & SCG_SIRCCSR_SIRCVLD_MASK)

#define SCG_SIRCCSR_SIRCSEL_MASK                 (0x2000000U)
#define SCG_SIRCCSR_SIRCSEL_SHIFT                (25U)
/*! SIRCSEL - Slow IRC Selected
 *  0b0..Slow IRC is not the system clock source
 *  0b1..Slow IRC is the system clock source
 */
#define SCG_SIRCCSR_SIRCSEL(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCSEL_SHIFT)) & SCG_SIRCCSR_SIRCSEL_MASK)
/*! @} */

/*! @name FIRCCSR - Fast IRC Control Status Register */
/*! @{ */

#define SCG_FIRCCSR_FIRCEN_MASK                  (0x1U)
#define SCG_FIRCCSR_FIRCEN_SHIFT                 (0U)
/*! FIRCEN - Fast IRC Enable
 *  0b0..Fast IRC is disabled
 *  0b1..Fast IRC is enabled
 */
#define SCG_FIRCCSR_FIRCEN(x)                    (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCEN_SHIFT)) & SCG_FIRCCSR_FIRCEN_MASK)

#define SCG_FIRCCSR_FIRCSTEN_MASK                (0x2U)
#define SCG_FIRCCSR_FIRCSTEN_SHIFT               (1U)
/*! FIRCSTEN - Fast IRC Stop Enable
 *  0b0..Fast IRC is disabled in sleep modes.
 *  0b1..Fast IRC is enabled in SLEEP modes
 */
#define SCG_FIRCCSR_FIRCSTEN(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCSTEN_SHIFT)) & SCG_FIRCCSR_FIRCSTEN_MASK)

#define SCG_FIRCCSR_FIRCTREN_MASK                (0x100U)
#define SCG_FIRCCSR_FIRCTREN_SHIFT               (8U)
/*! FIRCTREN - Fast IRC Trim Enable
 *  0b0..Disable trimming Fast IRC to an external clock source
 *  0b1..Enable trimming Fast IRC to an external clock source
 */
#define SCG_FIRCCSR_FIRCTREN(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCTREN_SHIFT)) & SCG_FIRCCSR_FIRCTREN_MASK)

#define SCG_FIRCCSR_FIRCTRUP_MASK                (0x200U)
#define SCG_FIRCCSR_FIRCTRUP_SHIFT               (9U)
/*! FIRCTRUP - Fast IRC Trim Update
 *  0b0..Disable Fast IRC trimming updates
 *  0b1..Enable Fast IRC trimming updates
 */
#define SCG_FIRCCSR_FIRCTRUP(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCTRUP_SHIFT)) & SCG_FIRCCSR_FIRCTRUP_MASK)

#define SCG_FIRCCSR_TRIM_LOCK_MASK               (0x400U)
#define SCG_FIRCCSR_TRIM_LOCK_SHIFT              (10U)
/*! TRIM_LOCK - Fast IRC TRIM LOCK
 *  0b0..FIRC auto trim not locked to target frequency range.
 *  0b1..FIRC auto trim locked to target frequency range
 */
#define SCG_FIRCCSR_TRIM_LOCK(x)                 (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_TRIM_LOCK_SHIFT)) & SCG_FIRCCSR_TRIM_LOCK_MASK)

#define SCG_FIRCCSR_COARSE_TRIM_BYPASS_MASK      (0x800U)
#define SCG_FIRCCSR_COARSE_TRIM_BYPASS_SHIFT     (11U)
/*! COARSE_TRIM_BYPASS - Fast Coarse Auto Trim Bypass
 *  0b0..FIRC Coarse Auto Trim NOT Bypassed
 *  0b1..FIRC Coarse Auto Trim Bypassed
 */
#define SCG_FIRCCSR_COARSE_TRIM_BYPASS(x)        (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_COARSE_TRIM_BYPASS_SHIFT)) & SCG_FIRCCSR_COARSE_TRIM_BYPASS_MASK)

#define SCG_FIRCCSR_LK_MASK                      (0x800000U)
#define SCG_FIRCCSR_LK_SHIFT                     (23U)
/*! LK - Lock Register
 *  0b0..Control Status Register can be written.
 *  0b1..Control Status Register cannot be written.
 */
#define SCG_FIRCCSR_LK(x)                        (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_LK_SHIFT)) & SCG_FIRCCSR_LK_MASK)

#define SCG_FIRCCSR_FIRCVLD_MASK                 (0x1000000U)
#define SCG_FIRCCSR_FIRCVLD_SHIFT                (24U)
/*! FIRCVLD - Fast IRC Valid status
 *  0b0..Fast IRC is not enabled or clock is not valid.
 *  0b1..Fast IRC is enabled and output clock is valid. The clock is valid after there is an output clock from the FIRC analog.
 */
#define SCG_FIRCCSR_FIRCVLD(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCVLD_SHIFT)) & SCG_FIRCCSR_FIRCVLD_MASK)

#define SCG_FIRCCSR_FIRCSEL_MASK                 (0x2000000U)
#define SCG_FIRCCSR_FIRCSEL_SHIFT                (25U)
/*! FIRCSEL - Fast IRC Selected status
 *  0b0..Fast IRC is not the system clock source
 *  0b1..Fast IRC is the system clock source
 */
#define SCG_FIRCCSR_FIRCSEL(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCSEL_SHIFT)) & SCG_FIRCCSR_FIRCSEL_MASK)

#define SCG_FIRCCSR_FIRCERR_MASK                 (0x4000000U)
#define SCG_FIRCCSR_FIRCERR_SHIFT                (26U)
/*! FIRCERR - Fast IRC Clock Error
 *  0b0..Error not detected with the Fast IRC trimming.
 *  0b1..Error detected with the Fast IRC trimming.
 */
#define SCG_FIRCCSR_FIRCERR(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCERR_SHIFT)) & SCG_FIRCCSR_FIRCERR_MASK)
/*! @} */

/*! @name FIRCCFG - Fast IRC Configuration Register */
/*! @{ */

#define SCG_FIRCCFG_RANGE_MASK                   (0x3U)
#define SCG_FIRCCFG_RANGE_SHIFT                  (0U)
/*! RANGE - Frequency Range
 *  0b00..48 MHz FIRC clock selected.
 *  0b01..64 MHz FIRC clock selected.
 *  0b10..96 MHz FIRC clock selected.
 *  0b11..192 MHz FIRC clock selected.
 */
#define SCG_FIRCCFG_RANGE(x)                     (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCFG_RANGE_SHIFT)) & SCG_FIRCCFG_RANGE_MASK)
/*! @} */

/*! @name FIRCTCFG - Fast IRC Trim Configuration Register */
/*! @{ */

#define SCG_FIRCTCFG_TRIMSRC_MASK                (0x3U)
#define SCG_FIRCTCFG_TRIMSRC_SHIFT               (0U)
/*! TRIMSRC - Trim Source
 *  0b00..Reserved
 *  0b01..Reserved
 *  0b10..System OSC. This option requires that SOSC be divided using the TRIMDIV field to get a frequency of 1 MHz.
 *  0b11..RTC OSC (32.768 kHz)
 */
#define SCG_FIRCTCFG_TRIMSRC(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTCFG_TRIMSRC_SHIFT)) & SCG_FIRCTCFG_TRIMSRC_MASK)

#define SCG_FIRCTCFG_TRIMDIV_MASK                (0x7FF0000U)
#define SCG_FIRCTCFG_TRIMDIV_SHIFT               (16U)
/*! TRIMDIV - Fast IRC Trim Predivide
 */
#define SCG_FIRCTCFG_TRIMDIV(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTCFG_TRIMDIV_SHIFT)) & SCG_FIRCTCFG_TRIMDIV_MASK)
/*! @} */

/*! @name FIRCSTAT - Fast IRC Status Register */
/*! @{ */

#define SCG_FIRCSTAT_TRIMFINE_MASK               (0xFFU)
#define SCG_FIRCSTAT_TRIMFINE_SHIFT              (0U)
/*! TRIMFINE - Trim Fine
 */
#define SCG_FIRCSTAT_TRIMFINE(x)                 (((uint32_t)(((uint32_t)(x)) << SCG_FIRCSTAT_TRIMFINE_SHIFT)) & SCG_FIRCSTAT_TRIMFINE_MASK)

#define SCG_FIRCSTAT_TRIMCOAR_MASK               (0x3F00U)
#define SCG_FIRCSTAT_TRIMCOAR_SHIFT              (8U)
/*! TRIMCOAR - Trim Coarse
 */
#define SCG_FIRCSTAT_TRIMCOAR(x)                 (((uint32_t)(((uint32_t)(x)) << SCG_FIRCSTAT_TRIMCOAR_SHIFT)) & SCG_FIRCSTAT_TRIMCOAR_MASK)
/*! @} */

/*! @name ROSCCSR - RTC OSC Control Status Register */
/*! @{ */

#define SCG_ROSCCSR_ROSCCM_MASK                  (0x10000U)
#define SCG_ROSCCSR_ROSCCM_SHIFT                 (16U)
/*! ROSCCM - RTC OSC Clock Monitor
 *  0b0..RTC OSC Clock Monitor is disabled
 *  0b1..RTC OSC Clock Monitor is enabled
 */
#define SCG_ROSCCSR_ROSCCM(x)                    (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCCM_SHIFT)) & SCG_ROSCCSR_ROSCCM_MASK)

#define SCG_ROSCCSR_ROSCCMRE_MASK                (0x20000U)
#define SCG_ROSCCSR_ROSCCMRE_SHIFT               (17U)
/*! ROSCCMRE - RTC OSC Clock Monitor Reset Enable
 *  0b0..Clock Monitor generates interrupt when error detected
 *  0b1..Clock Monitor generates reset when error detected
 */
#define SCG_ROSCCSR_ROSCCMRE(x)                  (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCCMRE_SHIFT)) & SCG_ROSCCSR_ROSCCMRE_MASK)

#define SCG_ROSCCSR_LK_MASK                      (0x800000U)
#define SCG_ROSCCSR_LK_SHIFT                     (23U)
/*! LK - Lock Register
 *  0b0..Control Status Register can be written.
 *  0b1..Control Status Register cannot be written.
 */
#define SCG_ROSCCSR_LK(x)                        (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_LK_SHIFT)) & SCG_ROSCCSR_LK_MASK)

#define SCG_ROSCCSR_ROSCVLD_MASK                 (0x1000000U)
#define SCG_ROSCCSR_ROSCVLD_SHIFT                (24U)
/*! ROSCVLD - RTC OSC Valid
 *  0b0..RTC OSC is not enabled or clock is not valid
 *  0b1..RTC OSC is enabled and output clock is valid
 */
#define SCG_ROSCCSR_ROSCVLD(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCVLD_SHIFT)) & SCG_ROSCCSR_ROSCVLD_MASK)

#define SCG_ROSCCSR_ROSCSEL_MASK                 (0x2000000U)
#define SCG_ROSCCSR_ROSCSEL_SHIFT                (25U)
/*! ROSCSEL - RTC OSC Selected
 *  0b0..RTC OSC is not the system clock source
 *  0b1..RTC OSC is the system clock source
 */
#define SCG_ROSCCSR_ROSCSEL(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCSEL_SHIFT)) & SCG_ROSCCSR_ROSCSEL_MASK)

#define SCG_ROSCCSR_ROSCERR_MASK                 (0x4000000U)
#define SCG_ROSCCSR_ROSCERR_SHIFT                (26U)
/*! ROSCERR - RTC OSC Clock Error
 *  0b0..RTC OSC Clock Monitor is disabled or has not detected an error
 *  0b1..RTC OSC Clock Monitor is enabled and detected an RTC loss of clock error
 */
#define SCG_ROSCCSR_ROSCERR(x)                   (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCERR_SHIFT)) & SCG_ROSCCSR_ROSCERR_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group SCG_Register_Masks */


/* SCG - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral SCG0 base address */
  #define SCG0_BASE                                (0x5001E000u)
  /** Peripheral SCG0 base address */
  #define SCG0_BASE_NS                             (0x4001E000u)
  /** Peripheral SCG0 base pointer */
  #define SCG0                                     ((SCG_Type *)SCG0_BASE)
  /** Peripheral SCG0 base pointer */
  #define SCG0_NS                                  ((SCG_Type *)SCG0_BASE_NS)
  /** Array initializer of SCG peripheral base addresses */
  #define SCG_BASE_ADDRS                           { SCG0_BASE }
  /** Array initializer of SCG peripheral base pointers */
  #define SCG_BASE_PTRS                            { SCG0 }
  /** Array initializer of SCG peripheral base addresses */
  #define SCG_BASE_ADDRS_NS                        { SCG0_BASE_NS }
  /** Array initializer of SCG peripheral base pointers */
  #define SCG_BASE_PTRS_NS                         { SCG0_NS }
#else
  /** Peripheral SCG0 base address */
  #define SCG0_BASE                                (0x4001E000u)
  /** Peripheral SCG0 base pointer */
  #define SCG0                                     ((SCG_Type *)SCG0_BASE)
  /** Array initializer of SCG peripheral base addresses */
  #define SCG_BASE_ADDRS                           { SCG0_BASE }
  /** Array initializer of SCG peripheral base pointers */
  #define SCG_BASE_PTRS                            { SCG0 }
#endif

/*!
 * @}
 */ /* end of group SCG_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- SEMA42 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SEMA42_Peripheral_Access_Layer SEMA42 Peripheral Access Layer
 * @{
 */

/** SEMA42 - Register Layout Typedef */
typedef struct {
  __IO uint8_t GATE3;                              /**< Gate Register, offset: 0x0 */
  __IO uint8_t GATE2;                              /**< Gate Register, offset: 0x1 */
  __IO uint8_t GATE1;                              /**< Gate Register, offset: 0x2 */
  __IO uint8_t GATE0;                              /**< Gate Register, offset: 0x3 */
  __IO uint8_t GATE7;                              /**< Gate Register, offset: 0x4 */
  __IO uint8_t GATE6;                              /**< Gate Register, offset: 0x5 */
  __IO uint8_t GATE5;                              /**< Gate Register, offset: 0x6 */
  __IO uint8_t GATE4;                              /**< Gate Register, offset: 0x7 */
  __IO uint8_t GATE11;                             /**< Gate Register, offset: 0x8 */
  __IO uint8_t GATE10;                             /**< Gate Register, offset: 0x9 */
  __IO uint8_t GATE9;                              /**< Gate Register, offset: 0xA */
  __IO uint8_t GATE8;                              /**< Gate Register, offset: 0xB */
  __IO uint8_t GATE15;                             /**< Gate Register, offset: 0xC */
  __IO uint8_t GATE14;                             /**< Gate Register, offset: 0xD */
  __IO uint8_t GATE13;                             /**< Gate Register, offset: 0xE */
  __IO uint8_t GATE12;                             /**< Gate Register, offset: 0xF */
       uint8_t RESERVED_0[50];
  union {                                          /* offset: 0x42 */
    __I  uint16_t RSTGT_R;                           /**< Reset Gate Read, offset: 0x42 */
    __O  uint16_t RSTGT_W;                           /**< Reset Gate Write, offset: 0x42 */
  };
} SEMA42_Type;

/* ----------------------------------------------------------------------------
   -- SEMA42 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SEMA42_Register_Masks SEMA42 Register Masks
 * @{
 */

/*! @name GATE3 - Gate Register */
/*! @{ */

#define SEMA42_GATE3_GTFSM_MASK                  (0xFU)
#define SEMA42_GATE3_GTFSM_SHIFT                 (0U)
/*! GTFSM - Gate finite state machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE3_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE3_GTFSM_SHIFT)) & SEMA42_GATE3_GTFSM_MASK)
/*! @} */

/*! @name GATE2 - Gate Register */
/*! @{ */

#define SEMA42_GATE2_GTFSM_MASK                  (0xFU)
#define SEMA42_GATE2_GTFSM_SHIFT                 (0U)
/*! GTFSM - Gate finite state machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE2_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE2_GTFSM_SHIFT)) & SEMA42_GATE2_GTFSM_MASK)
/*! @} */

/*! @name GATE1 - Gate Register */
/*! @{ */

#define SEMA42_GATE1_GTFSM_MASK                  (0xFU)
#define SEMA42_GATE1_GTFSM_SHIFT                 (0U)
/*! GTFSM - Gate finite state machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE1_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE1_GTFSM_SHIFT)) & SEMA42_GATE1_GTFSM_MASK)
/*! @} */

/*! @name GATE0 - Gate Register */
/*! @{ */

#define SEMA42_GATE0_GTFSM_MASK                  (0xFU)
#define SEMA42_GATE0_GTFSM_SHIFT                 (0U)
/*! GTFSM - Gate finite state machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE0_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE0_GTFSM_SHIFT)) & SEMA42_GATE0_GTFSM_MASK)
/*! @} */

/*! @name GATE7 - Gate Register */
/*! @{ */

#define SEMA42_GATE7_GTFSM_MASK                  (0xFU)
#define SEMA42_GATE7_GTFSM_SHIFT                 (0U)
/*! GTFSM - Gate finite state machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE7_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE7_GTFSM_SHIFT)) & SEMA42_GATE7_GTFSM_MASK)
/*! @} */

/*! @name GATE6 - Gate Register */
/*! @{ */

#define SEMA42_GATE6_GTFSM_MASK                  (0xFU)
#define SEMA42_GATE6_GTFSM_SHIFT                 (0U)
/*! GTFSM - Gate finite state machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE6_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE6_GTFSM_SHIFT)) & SEMA42_GATE6_GTFSM_MASK)
/*! @} */

/*! @name GATE5 - Gate Register */
/*! @{ */

#define SEMA42_GATE5_GTFSM_MASK                  (0xFU)
#define SEMA42_GATE5_GTFSM_SHIFT                 (0U)
/*! GTFSM - Gate finite state machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE5_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE5_GTFSM_SHIFT)) & SEMA42_GATE5_GTFSM_MASK)
/*! @} */

/*! @name GATE4 - Gate Register */
/*! @{ */

#define SEMA42_GATE4_GTFSM_MASK                  (0xFU)
#define SEMA42_GATE4_GTFSM_SHIFT                 (0U)
/*! GTFSM - Gate finite state machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE4_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE4_GTFSM_SHIFT)) & SEMA42_GATE4_GTFSM_MASK)
/*! @} */

/*! @name GATE11 - Gate Register */
/*! @{ */

#define SEMA42_GATE11_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE11_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate finite state machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE11_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE11_GTFSM_SHIFT)) & SEMA42_GATE11_GTFSM_MASK)
/*! @} */

/*! @name GATE10 - Gate Register */
/*! @{ */

#define SEMA42_GATE10_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE10_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate finite state machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE10_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE10_GTFSM_SHIFT)) & SEMA42_GATE10_GTFSM_MASK)
/*! @} */

/*! @name GATE9 - Gate Register */
/*! @{ */

#define SEMA42_GATE9_GTFSM_MASK                  (0xFU)
#define SEMA42_GATE9_GTFSM_SHIFT                 (0U)
/*! GTFSM - Gate finite state machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE9_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE9_GTFSM_SHIFT)) & SEMA42_GATE9_GTFSM_MASK)
/*! @} */

/*! @name GATE8 - Gate Register */
/*! @{ */

#define SEMA42_GATE8_GTFSM_MASK                  (0xFU)
#define SEMA42_GATE8_GTFSM_SHIFT                 (0U)
/*! GTFSM - Gate finite state machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE8_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE8_GTFSM_SHIFT)) & SEMA42_GATE8_GTFSM_MASK)
/*! @} */

/*! @name GATE15 - Gate Register */
/*! @{ */

#define SEMA42_GATE15_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE15_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate finite state machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE15_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE15_GTFSM_SHIFT)) & SEMA42_GATE15_GTFSM_MASK)
/*! @} */

/*! @name GATE14 - Gate Register */
/*! @{ */

#define SEMA42_GATE14_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE14_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate finite state machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE14_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE14_GTFSM_SHIFT)) & SEMA42_GATE14_GTFSM_MASK)
/*! @} */

/*! @name GATE13 - Gate Register */
/*! @{ */

#define SEMA42_GATE13_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE13_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate finite state machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE13_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE13_GTFSM_SHIFT)) & SEMA42_GATE13_GTFSM_MASK)
/*! @} */

/*! @name GATE12 - Gate Register */
/*! @{ */

#define SEMA42_GATE12_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE12_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate finite state machine
 *  0b0000..The gate is unlocked (free).
 *  0b0001..Domain 0 locked the gate.
 *  0b0010..Domain 1 locked the gate.
 *  0b0011..Domain 2 locked the gate.
 *  0b0100..Domain 3 locked the gate.
 *  0b0101..Domain 4 locked the gate.
 *  0b0110..Domain 5 locked the gate.
 *  0b0111..Domain 6 locked the gate.
 *  0b1000..Domain 7 locked the gate.
 *  0b1001..Domain 8 locked the gate.
 *  0b1010..Domain 9 locked the gate.
 *  0b1011..Domain 10 locked the gate.
 *  0b1100..Domain 11 locked the gate.
 *  0b1101..Domain 12 locked the gate.
 *  0b1110..Domain 13 locked the gate.
 *  0b1111..Domain 14 locked the gate.
 */
#define SEMA42_GATE12_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE12_GTFSM_SHIFT)) & SEMA42_GATE12_GTFSM_MASK)
/*! @} */

/*! @name RSTGT_R - Reset Gate Read */
/*! @{ */

#define SEMA42_RSTGT_R_RSTGTN_MASK               (0xFFU)
#define SEMA42_RSTGT_R_RSTGTN_SHIFT              (0U)
/*! RSTGTN - Reset gate number
 */
#define SEMA42_RSTGT_R_RSTGTN(x)                 (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGTN_SHIFT)) & SEMA42_RSTGT_R_RSTGTN_MASK)

#define SEMA42_RSTGT_R_RSTGMS_MASK               (0xF00U)
#define SEMA42_RSTGT_R_RSTGMS_SHIFT              (8U)
/*! RSTGMS - Reset gate domain
 */
#define SEMA42_RSTGT_R_RSTGMS(x)                 (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGMS_SHIFT)) & SEMA42_RSTGT_R_RSTGMS_MASK)

#define SEMA42_RSTGT_R_RSTGSM_MASK               (0x3000U)
#define SEMA42_RSTGT_R_RSTGSM_SHIFT              (12U)
/*! RSTGSM - Reset gate finite state machine
 *  0b00..Idle, waiting for the first data pattern write.
 *  0b01..Waiting for the second data pattern write
 *  0b10..The 2-write sequence has completed. Generate the specified gate reset(s). After the reset is performed,
 *        this machine returns to the idle (waiting for first data pattern write) state.
 *  0b11..This state encoding is never used and therefore reserved.
 */
#define SEMA42_RSTGT_R_RSTGSM(x)                 (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGSM_SHIFT)) & SEMA42_RSTGT_R_RSTGSM_MASK)

#define SEMA42_RSTGT_R_ROZ_MASK                  (0xC000U)
#define SEMA42_RSTGT_R_ROZ_SHIFT                 (14U)
/*! ROZ - ROZ
 */
#define SEMA42_RSTGT_R_ROZ(x)                    (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_ROZ_SHIFT)) & SEMA42_RSTGT_R_ROZ_MASK)
/*! @} */

/*! @name RSTGT_W - Reset Gate Write */
/*! @{ */

#define SEMA42_RSTGT_W_RSTGTN_MASK               (0xFFU)
#define SEMA42_RSTGT_W_RSTGTN_SHIFT              (0U)
/*! RSTGTN - Reset gate number
 */
#define SEMA42_RSTGT_W_RSTGTN(x)                 (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_W_RSTGTN_SHIFT)) & SEMA42_RSTGT_W_RSTGTN_MASK)

#define SEMA42_RSTGT_W_RSTGDP_MASK               (0xFF00U)
#define SEMA42_RSTGT_W_RSTGDP_SHIFT              (8U)
/*! RSTGDP - Reset gate data pattern
 */
#define SEMA42_RSTGT_W_RSTGDP(x)                 (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_W_RSTGDP_SHIFT)) & SEMA42_RSTGT_W_RSTGDP_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group SEMA42_Register_Masks */


/* SEMA42 - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral SEMA42 base address */
  #define SEMA42_BASE                              (0x5003F000u)
  /** Peripheral SEMA42 base address */
  #define SEMA42_BASE_NS                           (0x4003F000u)
  /** Peripheral SEMA42 base pointer */
  #define SEMA42                                   ((SEMA42_Type *)SEMA42_BASE)
  /** Peripheral SEMA42 base pointer */
  #define SEMA42_NS                                ((SEMA42_Type *)SEMA42_BASE_NS)
  /** Array initializer of SEMA42 peripheral base addresses */
  #define SEMA42_BASE_ADDRS                        { SEMA42_BASE }
  /** Array initializer of SEMA42 peripheral base pointers */
  #define SEMA42_BASE_PTRS                         { SEMA42 }
  /** Array initializer of SEMA42 peripheral base addresses */
  #define SEMA42_BASE_ADDRS_NS                     { SEMA42_BASE_NS }
  /** Array initializer of SEMA42 peripheral base pointers */
  #define SEMA42_BASE_PTRS_NS                      { SEMA42_NS }
#else
  /** Peripheral SEMA42 base address */
  #define SEMA42_BASE                              (0x4003F000u)
  /** Peripheral SEMA42 base pointer */
  #define SEMA42                                   ((SEMA42_Type *)SEMA42_BASE)
  /** Array initializer of SEMA42 peripheral base addresses */
  #define SEMA42_BASE_ADDRS                        { SEMA42_BASE }
  /** Array initializer of SEMA42 peripheral base pointers */
  #define SEMA42_BASE_PTRS                         { SEMA42 }
#endif

/*!
 * @}
 */ /* end of group SEMA42_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- SFA Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SFA_Peripheral_Access_Layer SFA Peripheral Access Layer
 * @{
 */

/** SFA - Register Layout Typedef */
typedef struct {
  __IO uint32_t CTRL;                              /**< Signal Frequency Analyser (SFA) Control, offset: 0x0 */
  __IO uint32_t CTRL_EXT;                          /**< Signal Frequency Analyser (SFA) Control Extended, offset: 0x4 */
  __IO uint32_t CNT_STAT;                          /**< Signal Frequency Analyser Count Status Register, offset: 0x8 */
  __IO uint32_t CUT_CNT;                           /**< Signal Frequency Analyser Clock Under Test Counter, offset: 0xC */
  __IO uint32_t REF_CNT;                           /**< Signal Frequency Analyser Reference Clock Counter, offset: 0x10 */
  __IO uint32_t CUT_TARGET;                        /**< Signal Frequency Analyser Clock Under Test Target Count, offset: 0x14 */
  __IO uint32_t REF_TARGET;                        /**< Signal Frequency Analyser Reference Clock Target Count, offset: 0x18 */
  __I  uint32_t REF_CNT_ST_SAVED;                  /**< Signal Frequency Analyser Reference Clock Count Start Saved Register, offset: 0x1C */
  __I  uint32_t REF_CNT_END_SAVED;                 /**< Signal Frequency Analyser Reference Clock Count End Saved Register, offset: 0x20 */
  __IO uint32_t CTRL2;                             /**< Extended control register for SFA, offset: 0x24 */
  __IO uint32_t REF_LOW_LIMIT_CNT;                 /**< Record the low limit reference clock count, offset: 0x28 */
  __IO uint32_t REF_HIGH_LIMIT_CNT;                /**< This register record the low limit of ref clk counter, offset: 0x2C */
  __IO uint32_t CUT_LOW_LIMIT_CNT;                 /**< Record the CUT clock low limit counter, offset: 0x30 */
  __IO uint32_t CUT_HIGH_LIMIT_CNT;                /**< Record high limit count of cut clock, offset: 0x34 */
} SFA_Type;

/* ----------------------------------------------------------------------------
   -- SFA Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SFA_Register_Masks SFA Register Masks
 * @{
 */

/*! @name CTRL - Signal Frequency Analyser (SFA) Control */
/*! @{ */

#define SFA_CTRL_MODE_MASK                       (0x3U)
#define SFA_CTRL_MODE_SHIFT                      (0U)
/*! MODE - MEASUREMENT MODE
 *  0b00..Frequency measurement performed with REF frequency > CUT Frequency.
 *  0b01..Frequency measurement performed with REF frequency < CUT Frequency.
 *  0b10..CUT period measurement performed.
 *  0b11..Trigger based measurement performed. Note, each trigger pulse must be held for at least 2 ref_clk cycles.
 */
#define SFA_CTRL_MODE(x)                         (((uint32_t)(((uint32_t)(x)) << SFA_CTRL_MODE_SHIFT)) & SFA_CTRL_MODE_MASK)

#define SFA_CTRL_TRIG_START_POL_MASK             (0x4U)
#define SFA_CTRL_TRIG_START_POL_SHIFT            (2U)
/*! TRIG_START_POL - Trigger Start Polarity
 *  0b0..Rising edge of TRIGGER[TRIG_START_SEL] will begin the measurement sequence.
 *  0b1..Falling edge of TRIGGER[TRIG_START_SEL] will begin the measurement sequence.
 */
#define SFA_CTRL_TRIG_START_POL(x)               (((uint32_t)(((uint32_t)(x)) << SFA_CTRL_TRIG_START_POL_SHIFT)) & SFA_CTRL_TRIG_START_POL_MASK)

#define SFA_CTRL_TRIG_END_POL_MASK               (0x8U)
#define SFA_CTRL_TRIG_END_POL_SHIFT              (3U)
/*! TRIG_END_POL - Trigger End Polarity
 *  0b0..Rising edge of TRIGER[TRIG_END_SEL] will end the measurement sequence.
 *  0b1..Falling edge of TRIGGER[TRIG_END_SEL] will end the measurement sequence.
 */
#define SFA_CTRL_TRIG_END_POL(x)                 (((uint32_t)(((uint32_t)(x)) << SFA_CTRL_TRIG_END_POL_SHIFT)) & SFA_CTRL_TRIG_END_POL_MASK)

#define SFA_CTRL_SFA_TRIG_MEAS_EN_MASK           (0x10U)
#define SFA_CTRL_SFA_TRIG_MEAS_EN_SHIFT          (4U)
/*! SFA_TRIG_MEAS_EN - SFA Triggered Measurement Enable
 *  0b0..The measurement will start by default with a dummy write to the REF and CUT counters.
 *  0b1..The measurement will start after receiging a dummy write to the REF_CNT followed by receiving the trigger
 *       edge selected by TRIG_START_SEL and TRIG_START_POL.
 */
#define SFA_CTRL_SFA_TRIG_MEAS_EN(x)             (((uint32_t)(((uint32_t)(x)) << SFA_CTRL_SFA_TRIG_MEAS_EN_SHIFT)) & SFA_CTRL_SFA_TRIG_MEAS_EN_MASK)

#define SFA_CTRL_SFA_IRQ_EN_MASK                 (0x20U)
#define SFA_CTRL_SFA_IRQ_EN_SHIFT                (5U)
/*! SFA_IRQ_EN - SFA Interrupt Enable
 *  0b0..Interrupts are disabled.
 *  0b1..Interrupts are enabled.
 */
#define SFA_CTRL_SFA_IRQ_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SFA_CTRL_SFA_IRQ_EN_SHIFT)) & SFA_CTRL_SFA_IRQ_EN_MASK)

#define SFA_CTRL_SFA_EN_MASK                     (0x40U)
#define SFA_CTRL_SFA_EN_SHIFT                    (6U)
/*! SFA_EN - SFA Enable
 *  0b0..The SFA is disabled.
 *  0b1..The SFA is enabled.
 */
#define SFA_CTRL_SFA_EN(x)                       (((uint32_t)(((uint32_t)(x)) << SFA_CTRL_SFA_EN_SHIFT)) & SFA_CTRL_SFA_EN_MASK)

#define SFA_CTRL_TRIG_START_SEL_MASK             (0x100U)
#define SFA_CTRL_TRIG_START_SEL_SHIFT            (8U)
/*! TRIG_START_SEL - Signal MUX For Trigger Based Measurement Start
 */
#define SFA_CTRL_TRIG_START_SEL(x)               (((uint32_t)(((uint32_t)(x)) << SFA_CTRL_TRIG_START_SEL_SHIFT)) & SFA_CTRL_TRIG_START_SEL_MASK)

#define SFA_CTRL_TRIG_END_SEL_MASK               (0x1000U)
#define SFA_CTRL_TRIG_END_SEL_SHIFT              (12U)
/*! TRIG_END_SEL - Signal MUX For Trigger Based Measurement End
 */
#define SFA_CTRL_TRIG_END_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SFA_CTRL_TRIG_END_SEL_SHIFT)) & SFA_CTRL_TRIG_END_SEL_MASK)

#define SFA_CTRL_CUT_PREDIV_MASK                 (0xFF0000U)
#define SFA_CTRL_CUT_PREDIV_SHIFT                (16U)
/*! CUT_PREDIV - CUT_PREDIV
 *  0b00000000..No Divide
 *  0b00000001..No Divide
 *  0b00000010..Divide by 2
 *  0b00000011..Divide by 2
 *  0b00000100..Divide by 4
 *  0b00000101..Divide by 4
 *  0b00000110..Divide by 6
 *  0b00000111..Divide by 6
 *  0b00001000..Divide by 8
 *  0b00001001..Divide by 8
 *  0b00001010-0b11111101..Divide by CUT_PREDIV - CUT_PREDIV%2
 *  0b11111110..Divide by 254
 *  0b11111111..Divide by 254
 */
#define SFA_CTRL_CUT_PREDIV(x)                   (((uint32_t)(((uint32_t)(x)) << SFA_CTRL_CUT_PREDIV_SHIFT)) & SFA_CTRL_CUT_PREDIV_MASK)

#define SFA_CTRL_CUT_SEL_MASK                    (0xF000000U)  /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
#define SFA_CTRL_CUT_SEL_SHIFT                   (24U)
/*! CUT_SEL - CUT_SEL
 */
#define SFA_CTRL_CUT_SEL(x)                      (((uint32_t)(((uint32_t)(x)) << SFA_CTRL_CUT_SEL_SHIFT)) & SFA_CTRL_CUT_SEL_MASK)  /* Merged from fields with different position or width, of widths (1, 4), largest definition used */

#define SFA_CTRL_CUT_PIN_EN_MASK                 (0x80000000U)
#define SFA_CTRL_CUT_PIN_EN_SHIFT                (31U)
/*! CUT_PIN_EN - CUT_PIN_EN
 */
#define SFA_CTRL_CUT_PIN_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SFA_CTRL_CUT_PIN_EN_SHIFT)) & SFA_CTRL_CUT_PIN_EN_MASK)
/*! @} */

/*! @name CTRL_EXT - Signal Frequency Analyser (SFA) Control Extended */
/*! @{ */

#define SFA_CTRL_EXT_CUT_CLK_EN_MASK             (0xFFFFU)  /* Merged from fields with different position or width, of widths (1, 16), largest definition used */
#define SFA_CTRL_EXT_CUT_CLK_EN_SHIFT            (0U)
/*! CUT_CLK_EN - CUT_CLK_EN
 */
#define SFA_CTRL_EXT_CUT_CLK_EN(x)               (((uint32_t)(((uint32_t)(x)) << SFA_CTRL_EXT_CUT_CLK_EN_SHIFT)) & SFA_CTRL_EXT_CUT_CLK_EN_MASK)  /* Merged from fields with different position or width, of widths (1, 16), largest definition used */
/*! @} */

/*! @name CNT_STAT - Signal Frequency Analyser Count Status Register */
/*! @{ */

#define SFA_CNT_STAT_REF_STOPPED_MASK            (0x1U)
#define SFA_CNT_STAT_REF_STOPPED_SHIFT           (0U)
/*! REF_STOPPED - REF_STOPPED
 */
#define SFA_CNT_STAT_REF_STOPPED(x)              (((uint32_t)(((uint32_t)(x)) << SFA_CNT_STAT_REF_STOPPED_SHIFT)) & SFA_CNT_STAT_REF_STOPPED_MASK)

#define SFA_CNT_STAT_CUT_STOPPED_MASK            (0x2U)
#define SFA_CNT_STAT_CUT_STOPPED_SHIFT           (1U)
/*! CUT_STOPPED - CUT_STOPPED
 */
#define SFA_CNT_STAT_CUT_STOPPED(x)              (((uint32_t)(((uint32_t)(x)) << SFA_CNT_STAT_CUT_STOPPED_SHIFT)) & SFA_CNT_STAT_CUT_STOPPED_MASK)

#define SFA_CNT_STAT_MEAS_STARTED_MASK           (0x4U)
#define SFA_CNT_STAT_MEAS_STARTED_SHIFT          (2U)
/*! MEAS_STARTED - Measurement Started Flag
 */
#define SFA_CNT_STAT_MEAS_STARTED(x)             (((uint32_t)(((uint32_t)(x)) << SFA_CNT_STAT_MEAS_STARTED_SHIFT)) & SFA_CNT_STAT_MEAS_STARTED_MASK)

#define SFA_CNT_STAT_REF_CNT_TIMEOUT_MASK        (0x8U)
#define SFA_CNT_STAT_REF_CNT_TIMEOUT_SHIFT       (3U)
/*! REF_CNT_TIMEOUT - Reference Counter Time Out
 */
#define SFA_CNT_STAT_REF_CNT_TIMEOUT(x)          (((uint32_t)(((uint32_t)(x)) << SFA_CNT_STAT_REF_CNT_TIMEOUT_SHIFT)) & SFA_CNT_STAT_REF_CNT_TIMEOUT_MASK)

#define SFA_CNT_STAT_SFA_IRQ_MASK                (0x10U)
#define SFA_CNT_STAT_SFA_IRQ_SHIFT               (4U)
/*! SFA_IRQ - SFA Interrupt Request
 */
#define SFA_CNT_STAT_SFA_IRQ(x)                  (((uint32_t)(((uint32_t)(x)) << SFA_CNT_STAT_SFA_IRQ_SHIFT)) & SFA_CNT_STAT_SFA_IRQ_MASK)

#define SFA_CNT_STAT_FREQ_GT_MAX_IRQ_MASK        (0x20U)
#define SFA_CNT_STAT_FREQ_GT_MAX_IRQ_SHIFT       (5U)
/*! FREQ_GT_MAX_IRQ - FREQ_GT_MAX interrupt flag
 */
#define SFA_CNT_STAT_FREQ_GT_MAX_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << SFA_CNT_STAT_FREQ_GT_MAX_IRQ_SHIFT)) & SFA_CNT_STAT_FREQ_GT_MAX_IRQ_MASK)

#define SFA_CNT_STAT_FREQ_LT_MIN_IRQ_MASK        (0x40U)
#define SFA_CNT_STAT_FREQ_LT_MIN_IRQ_SHIFT       (6U)
/*! FREQ_LT_MIN_IRQ - FREQ_LT_MIN interrupt flag
 */
#define SFA_CNT_STAT_FREQ_LT_MIN_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << SFA_CNT_STAT_FREQ_LT_MIN_IRQ_SHIFT)) & SFA_CNT_STAT_FREQ_LT_MIN_IRQ_MASK)
/*! @} */

/*! @name CUT_CNT - Signal Frequency Analyser Clock Under Test Counter */
/*! @{ */

#define SFA_CUT_CNT_CUT_CNT_MASK                 (0xFFFFFFFFU)
#define SFA_CUT_CNT_CUT_CNT_SHIFT                (0U)
/*! CUT_CNT - CUT_CNT
 */
#define SFA_CUT_CNT_CUT_CNT(x)                   (((uint32_t)(((uint32_t)(x)) << SFA_CUT_CNT_CUT_CNT_SHIFT)) & SFA_CUT_CNT_CUT_CNT_MASK)
/*! @} */

/*! @name REF_CNT - Signal Frequency Analyser Reference Clock Counter */
/*! @{ */

#define SFA_REF_CNT_REF_CNT_MASK                 (0xFFFFFFFFU)
#define SFA_REF_CNT_REF_CNT_SHIFT                (0U)
/*! REF_CNT - REF_CNT
 */
#define SFA_REF_CNT_REF_CNT(x)                   (((uint32_t)(((uint32_t)(x)) << SFA_REF_CNT_REF_CNT_SHIFT)) & SFA_REF_CNT_REF_CNT_MASK)
/*! @} */

/*! @name CUT_TARGET - Signal Frequency Analyser Clock Under Test Target Count */
/*! @{ */

#define SFA_CUT_TARGET_CUT_TARGET_MASK           (0xFFFFFFFFU)
#define SFA_CUT_TARGET_CUT_TARGET_SHIFT          (0U)
/*! CUT_TARGET - CUT_TARGET
 */
#define SFA_CUT_TARGET_CUT_TARGET(x)             (((uint32_t)(((uint32_t)(x)) << SFA_CUT_TARGET_CUT_TARGET_SHIFT)) & SFA_CUT_TARGET_CUT_TARGET_MASK)
/*! @} */

/*! @name REF_TARGET - Signal Frequency Analyser Reference Clock Target Count */
/*! @{ */

#define SFA_REF_TARGET_REF_TARGET_MASK           (0xFFFFFFFFU)
#define SFA_REF_TARGET_REF_TARGET_SHIFT          (0U)
/*! REF_TARGET - REF_TARGET
 */
#define SFA_REF_TARGET_REF_TARGET(x)             (((uint32_t)(((uint32_t)(x)) << SFA_REF_TARGET_REF_TARGET_SHIFT)) & SFA_REF_TARGET_REF_TARGET_MASK)
/*! @} */

/*! @name REF_CNT_ST_SAVED - Signal Frequency Analyser Reference Clock Count Start Saved Register */
/*! @{ */

#define SFA_REF_CNT_ST_SAVED_REF_CNT_ST_SAVED_MASK (0xFFFFFFFFU)
#define SFA_REF_CNT_ST_SAVED_REF_CNT_ST_SAVED_SHIFT (0U)
/*! REF_CNT_ST_SAVED - REF_CNT_ST_SAVED
 */
#define SFA_REF_CNT_ST_SAVED_REF_CNT_ST_SAVED(x) (((uint32_t)(((uint32_t)(x)) << SFA_REF_CNT_ST_SAVED_REF_CNT_ST_SAVED_SHIFT)) & SFA_REF_CNT_ST_SAVED_REF_CNT_ST_SAVED_MASK)
/*! @} */

/*! @name REF_CNT_END_SAVED - Signal Frequency Analyser Reference Clock Count End Saved Register */
/*! @{ */

#define SFA_REF_CNT_END_SAVED_REF_CNT_END_SAVED_MASK (0xFFFFFFFFU)
#define SFA_REF_CNT_END_SAVED_REF_CNT_END_SAVED_SHIFT (0U)
/*! REF_CNT_END_SAVED - REF_CNT_END_SAVED
 */
#define SFA_REF_CNT_END_SAVED_REF_CNT_END_SAVED(x) (((uint32_t)(((uint32_t)(x)) << SFA_REF_CNT_END_SAVED_REF_CNT_END_SAVED_SHIFT)) & SFA_REF_CNT_END_SAVED_REF_CNT_END_SAVED_MASK)
/*! @} */

/*! @name CTRL2 - Extended control register for SFA */
/*! @{ */

#define SFA_CTRL2_REF_CLK_SEL_MASK               (0x3U)  /* Merged from fields with different position or width, of widths (1, 2), largest definition used */
#define SFA_CTRL2_REF_CLK_SEL_SHIFT              (0U)
/*! REF_CLK_SEL - Reference clock select
 */
#define SFA_CTRL2_REF_CLK_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SFA_CTRL2_REF_CLK_SEL_SHIFT)) & SFA_CTRL2_REF_CLK_SEL_MASK)  /* Merged from fields with different position or width, of widths (1, 2), largest definition used */

#define SFA_CTRL2_FREQ_GT_MAX_IRQ_EN_MASK        (0x10000U)
#define SFA_CTRL2_FREQ_GT_MAX_IRQ_EN_SHIFT       (16U)
/*! FREQ_GT_MAX_IRQ_EN - FREQ_GT_MAX interrupt enable
 */
#define SFA_CTRL2_FREQ_GT_MAX_IRQ_EN(x)          (((uint32_t)(((uint32_t)(x)) << SFA_CTRL2_FREQ_GT_MAX_IRQ_EN_SHIFT)) & SFA_CTRL2_FREQ_GT_MAX_IRQ_EN_MASK)

#define SFA_CTRL2_FREQ_LT_MIN_IRQ_EN_MASK        (0x20000U)
#define SFA_CTRL2_FREQ_LT_MIN_IRQ_EN_SHIFT       (17U)
/*! FREQ_LT_MIN_IRQ_EN - FREQ_LT_MIN interrupt enable
 */
#define SFA_CTRL2_FREQ_LT_MIN_IRQ_EN(x)          (((uint32_t)(((uint32_t)(x)) << SFA_CTRL2_FREQ_LT_MIN_IRQ_EN_SHIFT)) & SFA_CTRL2_FREQ_LT_MIN_IRQ_EN_MASK)
/*! @} */

/*! @name REF_LOW_LIMIT_CNT - Record the low limit reference clock count */
/*! @{ */

#define SFA_REF_LOW_LIMIT_CNT_REF_LOW_LIMIT_CNT_MASK (0xFFFFFFFFU)
#define SFA_REF_LOW_LIMIT_CNT_REF_LOW_LIMIT_CNT_SHIFT (0U)
/*! REF_LOW_LIMIT_CNT - Low limit reference clock count value
 */
#define SFA_REF_LOW_LIMIT_CNT_REF_LOW_LIMIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << SFA_REF_LOW_LIMIT_CNT_REF_LOW_LIMIT_CNT_SHIFT)) & SFA_REF_LOW_LIMIT_CNT_REF_LOW_LIMIT_CNT_MASK)
/*! @} */

/*! @name REF_HIGH_LIMIT_CNT - This register record the low limit of ref clk counter */
/*! @{ */

#define SFA_REF_HIGH_LIMIT_CNT_REF_HIGH_LIMIT_CNT_MASK (0xFFFFFFFFU)
#define SFA_REF_HIGH_LIMIT_CNT_REF_HIGH_LIMIT_CNT_SHIFT (0U)
/*! REF_HIGH_LIMIT_CNT - High limit reference clock count value
 */
#define SFA_REF_HIGH_LIMIT_CNT_REF_HIGH_LIMIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << SFA_REF_HIGH_LIMIT_CNT_REF_HIGH_LIMIT_CNT_SHIFT)) & SFA_REF_HIGH_LIMIT_CNT_REF_HIGH_LIMIT_CNT_MASK)
/*! @} */

/*! @name CUT_LOW_LIMIT_CNT - Record the CUT clock low limit counter */
/*! @{ */

#define SFA_CUT_LOW_LIMIT_CNT_cut_low_limit_cnt_MASK (0xFFFFFFFFU)
#define SFA_CUT_LOW_LIMIT_CNT_cut_low_limit_cnt_SHIFT (0U)
/*! cut_low_limit_cnt - Low limit cut clock count value
 */
#define SFA_CUT_LOW_LIMIT_CNT_cut_low_limit_cnt(x) (((uint32_t)(((uint32_t)(x)) << SFA_CUT_LOW_LIMIT_CNT_cut_low_limit_cnt_SHIFT)) & SFA_CUT_LOW_LIMIT_CNT_cut_low_limit_cnt_MASK)
/*! @} */

/*! @name CUT_HIGH_LIMIT_CNT - Record high limit count of cut clock */
/*! @{ */

#define SFA_CUT_HIGH_LIMIT_CNT_cut_high_limit_cnt_MASK (0xFFFFFFFFU)
#define SFA_CUT_HIGH_LIMIT_CNT_cut_high_limit_cnt_SHIFT (0U)
/*! cut_high_limit_cnt - High limit cut clock count value
 */
#define SFA_CUT_HIGH_LIMIT_CNT_cut_high_limit_cnt(x) (((uint32_t)(((uint32_t)(x)) << SFA_CUT_HIGH_LIMIT_CNT_cut_high_limit_cnt_SHIFT)) & SFA_CUT_HIGH_LIMIT_CNT_cut_high_limit_cnt_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group SFA_Register_Masks */


/* SFA - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral SFA0 base address */
  #define SFA0_BASE                                (0x5001D000u)
  /** Peripheral SFA0 base address */
  #define SFA0_BASE_NS                             (0x4001D000u)
  /** Peripheral SFA0 base pointer */
  #define SFA0                                     ((SFA_Type *)SFA0_BASE)
  /** Peripheral SFA0 base pointer */
  #define SFA0_NS                                  ((SFA_Type *)SFA0_BASE_NS)
  /** Peripheral RF_SFA base address */
  #define RF_SFA_BASE                              (0x58A06300u)
  /** Peripheral RF_SFA base address */
  #define RF_SFA_BASE_NS                           (0x48A06300u)
  /** Peripheral RF_SFA base pointer */
  #define RF_SFA                                   ((SFA_Type *)RF_SFA_BASE)
  /** Peripheral RF_SFA base pointer */
  #define RF_SFA_NS                                ((SFA_Type *)RF_SFA_BASE_NS)
  /** Array initializer of SFA peripheral base addresses */
  #define SFA_BASE_ADDRS                           { SFA0_BASE, RF_SFA_BASE }
  /** Array initializer of SFA peripheral base pointers */
  #define SFA_BASE_PTRS                            { SFA0, RF_SFA }
  /** Array initializer of SFA peripheral base addresses */
  #define SFA_BASE_ADDRS_NS                        { SFA0_BASE_NS, RF_SFA_BASE_NS }
  /** Array initializer of SFA peripheral base pointers */
  #define SFA_BASE_PTRS_NS                         { SFA0_NS, RF_SFA_NS }
#else
  /** Peripheral SFA0 base address */
  #define SFA0_BASE                                (0x4001D000u)
  /** Peripheral SFA0 base pointer */
  #define SFA0                                     ((SFA_Type *)SFA0_BASE)
  /** Peripheral RF_SFA base address */
  #define RF_SFA_BASE                              (0x48A06300u)
  /** Peripheral RF_SFA base pointer */
  #define RF_SFA                                   ((SFA_Type *)RF_SFA_BASE)
  /** Array initializer of SFA peripheral base addresses */
  #define SFA_BASE_ADDRS                           { SFA0_BASE, RF_SFA_BASE }
  /** Array initializer of SFA peripheral base pointers */
  #define SFA_BASE_PTRS                            { SFA0, RF_SFA }
#endif

/*!
 * @}
 */ /* end of group SFA_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- SMSCM Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SMSCM_Peripheral_Access_Layer SMSCM Peripheral Access Layer
 * @{
 */

/** SMSCM - Register Layout Typedef */
typedef struct {
  __IO uint32_t DBGEN;                             /**< Debug Enable, offset: 0x0 */
  __IO uint32_t DBGEN_B;                           /**< Debug Enable Complement, offset: 0x4 */
  __IO uint32_t DBGEN_LOCK;                        /**< Debug Enable Lock, offset: 0x8 */
       uint8_t RESERVED_0[20];
  __IO uint32_t DBG_AUTH_BEACON;                   /**< Debug Authentication Beacon, offset: 0x20 */
       uint8_t RESERVED_1[12];
  __I  uint32_t LIFECYCLE;                         /**< Lifecycle Fuse Word, offset: 0x30 */
  __I  uint32_t LIFECYCLE_B;                       /**< Lifecycle Fuse Word Complement, offset: 0x34 */
       uint8_t RESERVED_2[8];
  __IO uint32_t ROM_LOCKOUT;                       /**< ROM Lockout Register, offset: 0x40 */
       uint8_t RESERVED_3[188];
  __IO uint32_t SCTR;                              /**< Security Counter Register, offset: 0x100 */
  __O  uint32_t SCTRP1;                            /**< Security Counter Plus 1 Register, offset: 0x104 */
       uint8_t RESERVED_4[4];
  __O  uint32_t SCTRM1;                            /**< Security Counter Minus 1 Register, offset: 0x10C */
       uint8_t RESERVED_5[4];
  __O  uint32_t SCTRPX;                            /**< Security Counter Plus X Register, offset: 0x114 */
       uint8_t RESERVED_6[4];
  __O  uint32_t SCTRMX;                            /**< Security Counter Minus X Register, offset: 0x11C */
       uint8_t RESERVED_7[736];
  __IO uint32_t OCMDR0;                            /**< On-Chip Memory Descriptor Register, offset: 0x400 */
       uint8_t RESERVED_8[4];
  __IO uint32_t OCMDR2;                            /**< On-Chip Memory Descriptor Register, offset: 0x408 */
  __IO uint32_t OCMDR3;                            /**< On-Chip Memory Descriptor Register, offset: 0x40C */
       uint8_t RESERVED_9[4];
  __IO uint32_t OCMDR5;                            /**< On-Chip Memory Descriptor Register, offset: 0x414 */
       uint8_t RESERVED_10[104];
  __IO uint32_t OCMECR;                            /**< On-Chip Memory ECC Control Register, offset: 0x480 */
       uint8_t RESERVED_11[4];
  __IO uint32_t OCMEIR;                            /**< On-Chip Memory ECC Interrupt Register, offset: 0x488 */
       uint8_t RESERVED_12[4];
  __I  uint32_t OCMFAR;                            /**< On-Chip Memory Fault Address Register, offset: 0x490 */
  __I  uint32_t OCMFTR;                            /**< On-Chip Memory Fault Attribute Register, offset: 0x494 */
  __I  uint32_t OCMFDRH;                           /**< On-Chip Memory ECC Fault Data High Register, offset: 0x498 */
  __I  uint32_t OCMFDRL;                           /**< On-Chip Memory ECC Fault Data Low Register, offset: 0x49C */
       uint8_t RESERVED_13[1888];
  __IO uint32_t CPCR;                              /**< Core Platform Control Register, offset: 0xC00 */
} SMSCM_Type;

/* ----------------------------------------------------------------------------
   -- SMSCM Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SMSCM_Register_Masks SMSCM Register Masks
 * @{
 */

/*! @name DBGEN - Debug Enable */
/*! @{ */

#define SMSCM_DBGEN_DBGEN_MASK                   (0x7U)
#define SMSCM_DBGEN_DBGEN_SHIFT                  (0U)
/*! DBGEN - Invasive Debug Enable (DFF3 bitfield)
 *  0b101..W5C - Disable Invasive Debug.
 *  0b010..W2S - Enable Invasive Debug.
 *  0b000..Invasive Debug Disabled.
 *  0b010..Invasive Debug Enabled.
 */
#define SMSCM_DBGEN_DBGEN(x)                     (((uint32_t)(((uint32_t)(x)) << SMSCM_DBGEN_DBGEN_SHIFT)) & SMSCM_DBGEN_DBGEN_MASK)

#define SMSCM_DBGEN_SPIDEN_MASK                  (0x70U)
#define SMSCM_DBGEN_SPIDEN_SHIFT                 (4U)
/*! SPIDEN - Secure Invasive Debug Enable (DFF3 bitfield)
 *  0b101..W5C - Disable Secure Invasive Debug.
 *  0b010..W2S - Enable Secure Invasive Debug.
 *  0b000..Secure Invasive Debug Disabled.
 *  0b010..Secure Invasive Debug Enabled.
 */
#define SMSCM_DBGEN_SPIDEN(x)                    (((uint32_t)(((uint32_t)(x)) << SMSCM_DBGEN_SPIDEN_SHIFT)) & SMSCM_DBGEN_SPIDEN_MASK)

#define SMSCM_DBGEN_NIDEN_MASK                   (0x700U)
#define SMSCM_DBGEN_NIDEN_SHIFT                  (8U)
/*! NIDEN - Non-Invasive Debug Enable (DFF3 bitfield)
 *  0b101..W5C - Disable Non-Invasive Debug.
 *  0b010..W2S - Enable Non-Invasive Debug.
 *  0b000..Non-Invasive Debug Disabled.
 *  0b010..Non-Invasive Debug Enabled.
 */
#define SMSCM_DBGEN_NIDEN(x)                     (((uint32_t)(((uint32_t)(x)) << SMSCM_DBGEN_NIDEN_SHIFT)) & SMSCM_DBGEN_NIDEN_MASK)

#define SMSCM_DBGEN_SPNIDEN_MASK                 (0x7000U)
#define SMSCM_DBGEN_SPNIDEN_SHIFT                (12U)
/*! SPNIDEN - Secure Non-Invasive Debug Enable (DFF3 bitfield)
 *  0b101..W5C - Disable Secure Non-Invasive Debug.
 *  0b010..W2S - Enable Secure Non-Invasive Debug.
 *  0b000..Secure Non-Invasive Debug Disabled.
 *  0b010..Secure Non-Invasive Debug Enabled.
 */
#define SMSCM_DBGEN_SPNIDEN(x)                   (((uint32_t)(((uint32_t)(x)) << SMSCM_DBGEN_SPNIDEN_SHIFT)) & SMSCM_DBGEN_SPNIDEN_MASK)

#define SMSCM_DBGEN_ALTDBGEN_MASK                (0x70000U)
#define SMSCM_DBGEN_ALTDBGEN_SHIFT               (16U)
/*! ALTDBGEN - Alternate Invasive Debug Enable (DFF3 bitfield)
 *  0b101..W5C - Disable Alternate Invasive Debug.
 *  0b010..W2S - Enable Alternate Invasive Debug.
 *  0b000..Alternate Invasive Debug Disabled.
 *  0b010..Alternate Invasive Debug Enabled.
 */
#define SMSCM_DBGEN_ALTDBGEN(x)                  (((uint32_t)(((uint32_t)(x)) << SMSCM_DBGEN_ALTDBGEN_SHIFT)) & SMSCM_DBGEN_ALTDBGEN_MASK)

#define SMSCM_DBGEN_ALTEN_MASK                   (0x700000U)
#define SMSCM_DBGEN_ALTEN_SHIFT                  (20U)
/*! ALTEN - Alternate Enable (DFF3 bitfield)
 *  0b101..W5C - Disable Alternate.
 *  0b010..W2S - Enable Alternate.
 *  0b000..Alternate Disabled.
 *  0b010..Alternate Enabled.
 */
#define SMSCM_DBGEN_ALTEN(x)                     (((uint32_t)(((uint32_t)(x)) << SMSCM_DBGEN_ALTEN_SHIFT)) & SMSCM_DBGEN_ALTEN_MASK)
/*! @} */

/*! @name DBGEN_B - Debug Enable Complement */
/*! @{ */

#define SMSCM_DBGEN_B_DBGEN_B_MASK               (0x7U)
#define SMSCM_DBGEN_B_DBGEN_B_SHIFT              (0U)
/*! DBGEN_B - Invasive Debug Enable Complement (DFF3 bitfield)
 *  0b101..W5C - Enable Invasive Debug.
 *  0b010..W2S - Disable Invasive Debug.
 *  0b000..Invasive Debug Enabled.
 *  0b010..Invasive Debug Disabled.
 */
#define SMSCM_DBGEN_B_DBGEN_B(x)                 (((uint32_t)(((uint32_t)(x)) << SMSCM_DBGEN_B_DBGEN_B_SHIFT)) & SMSCM_DBGEN_B_DBGEN_B_MASK)

#define SMSCM_DBGEN_B_SPIDEN_B_MASK              (0x70U)
#define SMSCM_DBGEN_B_SPIDEN_B_SHIFT             (4U)
/*! SPIDEN_B - Secure Invasive Debug Enable - Complement (DFF3 bitfield)
 *  0b101..W5C - Enable Secure Invasive Debug.
 *  0b010..W2S - Disable Secure Invasive Debug.
 *  0b000..Secure Invasive Debug Enabled.
 *  0b010..Secure Invasive Debug Disabled.
 */
#define SMSCM_DBGEN_B_SPIDEN_B(x)                (((uint32_t)(((uint32_t)(x)) << SMSCM_DBGEN_B_SPIDEN_B_SHIFT)) & SMSCM_DBGEN_B_SPIDEN_B_MASK)

#define SMSCM_DBGEN_B_NIDEN_B_MASK               (0x700U)
#define SMSCM_DBGEN_B_NIDEN_B_SHIFT              (8U)
/*! NIDEN_B - Non-Invasive Debug Enable Complement (DFF3 bitfield)
 *  0b101..W5C - Enable Non-Invasive Debug.
 *  0b010..W2S - Disable Non-Invasive Debug.
 *  0b000..Non-Invasive Debug Enabled.
 *  0b010..Non-Invasive Debug Disabled.
 */
#define SMSCM_DBGEN_B_NIDEN_B(x)                 (((uint32_t)(((uint32_t)(x)) << SMSCM_DBGEN_B_NIDEN_B_SHIFT)) & SMSCM_DBGEN_B_NIDEN_B_MASK)

#define SMSCM_DBGEN_B_SPNIDEN_B_MASK             (0x7000U)
#define SMSCM_DBGEN_B_SPNIDEN_B_SHIFT            (12U)
/*! SPNIDEN_B - Secure Non-Invasive Debug Enable Complement (DFF3 bitfield)
 *  0b101..W5C - Enable Secure Non-Invasive Debug.
 *  0b010..W2S - Disable Secure Non-Invasive Debug.
 *  0b000..Secure Non-Invasive Debug Enabled.
 *  0b010..Secure Non-Invasive Debug Disabled.
 */
#define SMSCM_DBGEN_B_SPNIDEN_B(x)               (((uint32_t)(((uint32_t)(x)) << SMSCM_DBGEN_B_SPNIDEN_B_SHIFT)) & SMSCM_DBGEN_B_SPNIDEN_B_MASK)

#define SMSCM_DBGEN_B_ALTDBGEN_B_MASK            (0x70000U)
#define SMSCM_DBGEN_B_ALTDBGEN_B_SHIFT           (16U)
/*! ALTDBGEN_B - Alternate Invasive Debug Enable Complement (DFF3 bitfield)
 *  0b101..W5C - Alternate Enable Invasive Debug.
 *  0b010..W2S - Alternate Disable Invasive Debug.
 *  0b000..Alternate Invasive Debug Enabled.
 *  0b010..Alternate Invasive Debug Disabled.
 */
#define SMSCM_DBGEN_B_ALTDBGEN_B(x)              (((uint32_t)(((uint32_t)(x)) << SMSCM_DBGEN_B_ALTDBGEN_B_SHIFT)) & SMSCM_DBGEN_B_ALTDBGEN_B_MASK)

#define SMSCM_DBGEN_B_ALTEN_B_MASK               (0x700000U)
#define SMSCM_DBGEN_B_ALTEN_B_SHIFT              (20U)
/*! ALTEN_B - Alternate Enable Complement (DFF3 bitfield)
 *  0b101..W5C - Enable Alternate.
 *  0b010..W2S - Disable Alternate.
 *  0b000..Alternrate Enabled.
 *  0b010..Alternate Disabled.
 */
#define SMSCM_DBGEN_B_ALTEN_B(x)                 (((uint32_t)(((uint32_t)(x)) << SMSCM_DBGEN_B_ALTEN_B_SHIFT)) & SMSCM_DBGEN_B_ALTEN_B_MASK)
/*! @} */

/*! @name DBGEN_LOCK - Debug Enable Lock */
/*! @{ */

#define SMSCM_DBGEN_LOCK_LOCK_MASK               (0x7U)
#define SMSCM_DBGEN_LOCK_LOCK_SHIFT              (0U)
/*! LOCK - Lock (DFF3 bitfield)
 *  0b101..When DBGEN_LOCK[LOCK] is locked, DBGEN_LOCK[LOCK] cannot be unlocked with a write of 101b to this
 *         field. When DBGEN_LOCK[LOCK] is unlocked, a write of 101b to this field, DBGEN_LOCK[LOCK] remains unlocked
 *         and the DBGEN[DBGEN, SPIDEN, NIDEN, SPNIDEN],DBGEN_B[DBGEN_B, SPIDEN_B, NIDEN_B, SPNIDEN_B] fields remain
 *         writeable.
 *  0b010, 0b000, 0b001, 0b011, 0b100, 0b111..Lock DBGEN[SPNIDEN,NIDEN,SPIDEN,DBGEN], DBGEN_B[SPNIDEN_B,NIDEN_B,SPIDEN_B,DBGEN_B], and DBGEN_LOCK[LOCK].
 *  0b000..DBGEN[SPNIDEN,NIDEN,SPIDEN,DBGEN], DBGEN_B[SPNIDEN_B,NIDEN_B,SPIDEN_B,DBGEN_B], and DBGEN_LOCK[LOCK] unlocked.
 *  0b010..DBGEN[SPNIDEN,NIDEN,SPIDEN,DBGEN], DBGEN_B[SPNIDEN_B,NIDEN_B,SPIDEN_B,DBGEN_B], and DBGEN_LOCK[LOCK] locked.
 */
#define SMSCM_DBGEN_LOCK_LOCK(x)                 (((uint32_t)(((uint32_t)(x)) << SMSCM_DBGEN_LOCK_LOCK_SHIFT)) & SMSCM_DBGEN_LOCK_LOCK_MASK)

#define SMSCM_DBGEN_LOCK_ALT_DBGEN_LOCK_MASK     (0x70000U)
#define SMSCM_DBGEN_LOCK_ALT_DBGEN_LOCK_SHIFT    (16U)
/*! ALT_DBGEN_LOCK - Alternate Lock (DFF3 bitfield)
 *  0b101..When ALT_DBGEN_LOCK is locked, ALT_DBGEN_LOCK cannot be unlocked with a write of 101b to this field.
 *         When ALT_DBGEN_LOCK is unlocked, a write of 101b to this field, ALT_DBGEN_LOCK remains unlocked and
 *         DBGEN/DBGEN_B remains writeable.
 *  0b010, 0b000, 0b001, 0b011, 0b100, 0b111..Lock DBGEN[ALTDBGEN], DBGEN_B[ALTDBGEN_B, and DBGEN_LOCK[ALT_DBGEN_LOCK].
 *  0b000..ALT_DBGEN, ALT_DBGEN_B, ALT_DBGEN_LOCK unlocked.
 *  0b010..ALT_DBGEN, ALT_DBGEN_B, ALT_DBGEN_LOCK locked.
 */
#define SMSCM_DBGEN_LOCK_ALT_DBGEN_LOCK(x)       (((uint32_t)(((uint32_t)(x)) << SMSCM_DBGEN_LOCK_ALT_DBGEN_LOCK_SHIFT)) & SMSCM_DBGEN_LOCK_ALT_DBGEN_LOCK_MASK)

#define SMSCM_DBGEN_LOCK_ALT_EN_LOCK_MASK        (0x700000U)
#define SMSCM_DBGEN_LOCK_ALT_EN_LOCK_SHIFT       (20U)
/*! ALT_EN_LOCK - Alternate Lock (DFF3 bitfield)
 *  0b101..f When ALT_EN_LOCK is locked, ALT_EN_LOCK cannot be unlocked with a write of 101b to this field. When
 *         ALT_EN_LOCK is unlocked, a write of 101b to this field, ALT_EN_LOCK remains unlocked and ALTEN/ALTEN_B
 *         remains writeable.
 *  0b010, 0b000, 0b001, 0b011, 0b100, 0b111..Lock DBGEN[ALTEN], DBGEN_B[ALTEN_B, and DBGEN_LOCK[ALT_EN_LOCK].
 *  0b000..ALTEN, ALTEN_B, ALT_EN_LOCK unlocked.
 *  0b010..ALTEN, ALTEN_B, ALT_EN_LOCK locked.
 */
#define SMSCM_DBGEN_LOCK_ALT_EN_LOCK(x)          (((uint32_t)(((uint32_t)(x)) << SMSCM_DBGEN_LOCK_ALT_EN_LOCK_SHIFT)) & SMSCM_DBGEN_LOCK_ALT_EN_LOCK_MASK)
/*! @} */

/*! @name DBG_AUTH_BEACON - Debug Authentication Beacon */
/*! @{ */

#define SMSCM_DBG_AUTH_BEACON_AUTH_BEACON_MASK   (0xFFFFU)
#define SMSCM_DBG_AUTH_BEACON_AUTH_BEACON_SHIFT  (0U)
/*! AUTH_BEACON - Authentication Beacon
 */
#define SMSCM_DBG_AUTH_BEACON_AUTH_BEACON(x)     (((uint32_t)(((uint32_t)(x)) << SMSCM_DBG_AUTH_BEACON_AUTH_BEACON_SHIFT)) & SMSCM_DBG_AUTH_BEACON_AUTH_BEACON_MASK)

#define SMSCM_DBG_AUTH_BEACON_CREDENTIAL_BEACON_MASK (0xFFFF0000U)
#define SMSCM_DBG_AUTH_BEACON_CREDENTIAL_BEACON_SHIFT (16U)
/*! CREDENTIAL_BEACON - Credential Beacon
 */
#define SMSCM_DBG_AUTH_BEACON_CREDENTIAL_BEACON(x) (((uint32_t)(((uint32_t)(x)) << SMSCM_DBG_AUTH_BEACON_CREDENTIAL_BEACON_SHIFT)) & SMSCM_DBG_AUTH_BEACON_CREDENTIAL_BEACON_MASK)
/*! @} */

/*! @name LIFECYCLE - Lifecycle Fuse Word */
/*! @{ */

#define SMSCM_LIFECYCLE_CLC_MASK                 (0xFFU)
#define SMSCM_LIFECYCLE_CLC_SHIFT                (0U)
/*! CLC - Converged Lifecycle
 *  0b00000000..BLANK
 *  0b00000001..NXP Fab
 *  0b00000011..NXP Provisioned
 *  0b00000111..OEM Open
 *  0b00001111..OEM Secure World Closed
 *  0b00011111..OEM Closed
 *  0b10011111..OEM Locked
 *  0b00111111..OEM Return
 *  0b01111111..NXP Return
 *  0b11xxxxxx..BRICK
 */
#define SMSCM_LIFECYCLE_CLC(x)                   (((uint32_t)(((uint32_t)(x)) << SMSCM_LIFECYCLE_CLC_SHIFT)) & SMSCM_LIFECYCLE_CLC_MASK)

#define SMSCM_LIFECYCLE_DBG_EN_LOCK_MASK         (0x100U)
#define SMSCM_LIFECYCLE_DBG_EN_LOCK_SHIFT        (8U)
/*! DBG_EN_LOCK - Debug Enable Lock
 *  0b0..The debug access control registers remain open when jumping to customer code.
 *  0b1..The debug access control registers are write-locked before jumping to customer code.
 */
#define SMSCM_LIFECYCLE_DBG_EN_LOCK(x)           (((uint32_t)(((uint32_t)(x)) << SMSCM_LIFECYCLE_DBG_EN_LOCK_SHIFT)) & SMSCM_LIFECYCLE_DBG_EN_LOCK_MASK)

#define SMSCM_LIFECYCLE_DBG_AUTH_DIS_MASK        (0x200U)
#define SMSCM_LIFECYCLE_DBG_AUTH_DIS_SHIFT       (9U)
/*! DBG_AUTH_DIS - Debug Authentication Disabled
 *  0b0..Debug Authentication enabled.
 *  0b1..Debug Authentication disabled.
 */
#define SMSCM_LIFECYCLE_DBG_AUTH_DIS(x)          (((uint32_t)(((uint32_t)(x)) << SMSCM_LIFECYCLE_DBG_AUTH_DIS_SHIFT)) & SMSCM_LIFECYCLE_DBG_AUTH_DIS_MASK)

#define SMSCM_LIFECYCLE_TZM_EN_MASK              (0x400U)
#define SMSCM_LIFECYCLE_TZM_EN_SHIFT             (10U)
/*! TZM_EN - Trust Zone Mode Enable
 *  0b0..TZ-M is disabled by default, can be enabled by software.
 *  0b1..TZ-M is enabled.
 */
#define SMSCM_LIFECYCLE_TZM_EN(x)                (((uint32_t)(((uint32_t)(x)) << SMSCM_LIFECYCLE_TZM_EN_SHIFT)) & SMSCM_LIFECYCLE_TZM_EN_MASK)

#define SMSCM_LIFECYCLE_DICE_EN_MASK             (0x800U)
#define SMSCM_LIFECYCLE_DICE_EN_SHIFT            (11U)
/*! DICE_EN - DICE Enable
 *  0b0..DICE is disabled by default.
 *  0b1..DICE is enabled.
 */
#define SMSCM_LIFECYCLE_DICE_EN(x)               (((uint32_t)(((uint32_t)(x)) << SMSCM_LIFECYCLE_DICE_EN_SHIFT)) & SMSCM_LIFECYCLE_DICE_EN_MASK)

#define SMSCM_LIFECYCLE_SERIAL_DIS_MASK          (0x4000U)
#define SMSCM_LIFECYCLE_SERIAL_DIS_SHIFT         (14U)
/*! SERIAL_DIS - Serial Download Disabled
 *  0b0..Serial download path is enabled.
 *  0b1..Serial download path is disabled.
 */
#define SMSCM_LIFECYCLE_SERIAL_DIS(x)            (((uint32_t)(((uint32_t)(x)) << SMSCM_LIFECYCLE_SERIAL_DIS_SHIFT)) & SMSCM_LIFECYCLE_SERIAL_DIS_MASK)

#define SMSCM_LIFECYCLE_WAKEUP_DIS_MASK          (0x8000U)
#define SMSCM_LIFECYCLE_WAKEUP_DIS_SHIFT         (15U)
/*! WAKEUP_DIS - Wakeup Disabled
 *  0b0..Boot-ROM LP wakup is enabled.
 *  0b1..Boot-ROM LP wakup is disabled.
 */
#define SMSCM_LIFECYCLE_WAKEUP_DIS(x)            (((uint32_t)(((uint32_t)(x)) << SMSCM_LIFECYCLE_WAKEUP_DIS_SHIFT)) & SMSCM_LIFECYCLE_WAKEUP_DIS_MASK)

#define SMSCM_LIFECYCLE_CTRK_REVOKE_MASK         (0xF0000U)
#define SMSCM_LIFECYCLE_CTRK_REVOKE_SHIFT        (16U)
/*! CTRK_REVOKE - Revocation indicator from OEM Firmware Authentication Public Key
 */
#define SMSCM_LIFECYCLE_CTRK_REVOKE(x)           (((uint32_t)(((uint32_t)(x)) << SMSCM_LIFECYCLE_CTRK_REVOKE_SHIFT)) & SMSCM_LIFECYCLE_CTRK_REVOKE_MASK)

#define SMSCM_LIFECYCLE_SWD_ID_MASK              (0xF0000000U)
#define SMSCM_LIFECYCLE_SWD_ID_SHIFT             (28U)
/*! SWD_ID - Serial Wire Debug Instance ID
 */
#define SMSCM_LIFECYCLE_SWD_ID(x)                (((uint32_t)(((uint32_t)(x)) << SMSCM_LIFECYCLE_SWD_ID_SHIFT)) & SMSCM_LIFECYCLE_SWD_ID_MASK)
/*! @} */

/*! @name LIFECYCLE_B - Lifecycle Fuse Word Complement */
/*! @{ */

#define SMSCM_LIFECYCLE_B_CLC_B_MASK             (0xFFU)
#define SMSCM_LIFECYCLE_B_CLC_B_SHIFT            (0U)
/*! CLC_B - Converged Lifecycle Complement
 *  0b11111111..BLANK
 *  0b11111110..NXP Fab
 *  0b11111100..NXP Provisioned
 *  0b11111000..OEM Open
 *  0b11110000..OEM Secure World Closed
 *  0b11100000..OEM Closed
 *  0b01100000..OEM Locked
 *  0b11000000..OEM Return
 *  0b10000000..NXP Return
 *  0b00xxxxxx..BRICK
 */
#define SMSCM_LIFECYCLE_B_CLC_B(x)               (((uint32_t)(((uint32_t)(x)) << SMSCM_LIFECYCLE_B_CLC_B_SHIFT)) & SMSCM_LIFECYCLE_B_CLC_B_MASK)

#define SMSCM_LIFECYCLE_B_DBG_EN_LOCK_B_MASK     (0x100U)
#define SMSCM_LIFECYCLE_B_DBG_EN_LOCK_B_SHIFT    (8U)
/*! DBG_EN_LOCK_B - Debug Enable Lock Complement
 *  0b0..The debug access control registers are write-locked before jumping to customer code.
 *  0b1..The debug access control registers remain open when jumping to customer code.
 */
#define SMSCM_LIFECYCLE_B_DBG_EN_LOCK_B(x)       (((uint32_t)(((uint32_t)(x)) << SMSCM_LIFECYCLE_B_DBG_EN_LOCK_B_SHIFT)) & SMSCM_LIFECYCLE_B_DBG_EN_LOCK_B_MASK)

#define SMSCM_LIFECYCLE_B_DBG_AUTH_DIS_B_MASK    (0x200U)
#define SMSCM_LIFECYCLE_B_DBG_AUTH_DIS_B_SHIFT   (9U)
/*! DBG_AUTH_DIS_B - Debug Authentication Disabled Complement
 *  0b1..Debug Authentication enabled.
 *  0b0..Debug Authentication disabled.
 */
#define SMSCM_LIFECYCLE_B_DBG_AUTH_DIS_B(x)      (((uint32_t)(((uint32_t)(x)) << SMSCM_LIFECYCLE_B_DBG_AUTH_DIS_B_SHIFT)) & SMSCM_LIFECYCLE_B_DBG_AUTH_DIS_B_MASK)

#define SMSCM_LIFECYCLE_B_TZM_EN_B_MASK          (0x400U)
#define SMSCM_LIFECYCLE_B_TZM_EN_B_SHIFT         (10U)
/*! TZM_EN_B - Trust Zone Mode Enable Complement
 *  0b0..TZ-M is enabled.
 *  0b1..TZ-M is disabled by default, can be enabled by software.
 */
#define SMSCM_LIFECYCLE_B_TZM_EN_B(x)            (((uint32_t)(((uint32_t)(x)) << SMSCM_LIFECYCLE_B_TZM_EN_B_SHIFT)) & SMSCM_LIFECYCLE_B_TZM_EN_B_MASK)

#define SMSCM_LIFECYCLE_B_DICE_EN_B_MASK         (0x800U)
#define SMSCM_LIFECYCLE_B_DICE_EN_B_SHIFT        (11U)
/*! DICE_EN_B - DICE Enable Complement
 *  0b0..DICE is enabled.
 *  0b1..DICE is disabled by default.
 */
#define SMSCM_LIFECYCLE_B_DICE_EN_B(x)           (((uint32_t)(((uint32_t)(x)) << SMSCM_LIFECYCLE_B_DICE_EN_B_SHIFT)) & SMSCM_LIFECYCLE_B_DICE_EN_B_MASK)

#define SMSCM_LIFECYCLE_B_SERIAL_DIS_B_MASK      (0x4000U)
#define SMSCM_LIFECYCLE_B_SERIAL_DIS_B_SHIFT     (14U)
/*! SERIAL_DIS_B - Serial Download Disabled Complement
 *  0b1..Serial download path is enabled.
 *  0b0..Serial download path is disabled.
 */
#define SMSCM_LIFECYCLE_B_SERIAL_DIS_B(x)        (((uint32_t)(((uint32_t)(x)) << SMSCM_LIFECYCLE_B_SERIAL_DIS_B_SHIFT)) & SMSCM_LIFECYCLE_B_SERIAL_DIS_B_MASK)

#define SMSCM_LIFECYCLE_B_WAKEUP_DIS_B_MASK      (0x8000U)
#define SMSCM_LIFECYCLE_B_WAKEUP_DIS_B_SHIFT     (15U)
/*! WAKEUP_DIS_B - Wakeup Disabled Complement
 *  0b1..Boot-ROM LP wakup is enabled.
 *  0b0..Boot-ROM LP wakup is disabled.
 */
#define SMSCM_LIFECYCLE_B_WAKEUP_DIS_B(x)        (((uint32_t)(((uint32_t)(x)) << SMSCM_LIFECYCLE_B_WAKEUP_DIS_B_SHIFT)) & SMSCM_LIFECYCLE_B_WAKEUP_DIS_B_MASK)

#define SMSCM_LIFECYCLE_B_CTRK_REVOKE_B_MASK     (0xF0000U)
#define SMSCM_LIFECYCLE_B_CTRK_REVOKE_B_SHIFT    (16U)
/*! CTRK_REVOKE_B - Revocation indicator from OEM Firmware Authentication Public Key Complement
 */
#define SMSCM_LIFECYCLE_B_CTRK_REVOKE_B(x)       (((uint32_t)(((uint32_t)(x)) << SMSCM_LIFECYCLE_B_CTRK_REVOKE_B_SHIFT)) & SMSCM_LIFECYCLE_B_CTRK_REVOKE_B_MASK)

#define SMSCM_LIFECYCLE_B_SWD_ID_B_MASK          (0xF0000000U)
#define SMSCM_LIFECYCLE_B_SWD_ID_B_SHIFT         (28U)
/*! SWD_ID_B - Serial Wire Debug Instance ID Complement
 */
#define SMSCM_LIFECYCLE_B_SWD_ID_B(x)            (((uint32_t)(((uint32_t)(x)) << SMSCM_LIFECYCLE_B_SWD_ID_B_SHIFT)) & SMSCM_LIFECYCLE_B_SWD_ID_B_MASK)
/*! @} */

/*! @name ROM_LOCKOUT - ROM Lockout Register */
/*! @{ */

#define SMSCM_ROM_LOCKOUT_ROMWA_MASK             (0x3FFFF0U)
#define SMSCM_ROM_LOCKOUT_ROMWA_SHIFT            (4U)
/*! ROMWA - ROM Watermark Address
 */
#define SMSCM_ROM_LOCKOUT_ROMWA(x)               (((uint32_t)(((uint32_t)(x)) << SMSCM_ROM_LOCKOUT_ROMWA_SHIFT)) & SMSCM_ROM_LOCKOUT_ROMWA_MASK)

#define SMSCM_ROM_LOCKOUT_REGLOCK_MASK           (0xE0000000U)
#define SMSCM_ROM_LOCKOUT_REGLOCK_SHIFT          (29U)
/*! REGLOCK - ROM_LOCKOUT Register Lock (DFF3 bitfield)
 *  0b101..Writing this value has no effect.
 *  0b010, 0b000, 0b001, 0b011, 0b100, 0b111..Lock ROM_LOCKOUT register.
 *  0b000..ROM_LOCKOUT unlocked.
 *  0b010..ROM_LOCKOUT locked.
 */
#define SMSCM_ROM_LOCKOUT_REGLOCK(x)             (((uint32_t)(((uint32_t)(x)) << SMSCM_ROM_LOCKOUT_REGLOCK_SHIFT)) & SMSCM_ROM_LOCKOUT_REGLOCK_MASK)
/*! @} */

/*! @name SCTR - Security Counter Register */
/*! @{ */

#define SMSCM_SCTR_DATA32_MASK                   (0xFFFFFFFFU)
#define SMSCM_SCTR_DATA32_SHIFT                  (0U)
/*! DATA32 - Data, 32 bits
 */
#define SMSCM_SCTR_DATA32(x)                     (((uint32_t)(((uint32_t)(x)) << SMSCM_SCTR_DATA32_SHIFT)) & SMSCM_SCTR_DATA32_MASK)
/*! @} */

/*! @name SCTRP1 - Security Counter Plus 1 Register */
/*! @{ */

#define SMSCM_SCTRP1_DONTCARE32_MASK             (0xFFFFFFFFU)
#define SMSCM_SCTRP1_DONTCARE32_SHIFT            (0U)
/*! DONTCARE32 - Don't Care Data, 32 bits
 */
#define SMSCM_SCTRP1_DONTCARE32(x)               (((uint32_t)(((uint32_t)(x)) << SMSCM_SCTRP1_DONTCARE32_SHIFT)) & SMSCM_SCTRP1_DONTCARE32_MASK)
/*! @} */

/*! @name SCTRM1 - Security Counter Minus 1 Register */
/*! @{ */

#define SMSCM_SCTRM1_DONTCARE32_MASK             (0xFFFFFFFFU)
#define SMSCM_SCTRM1_DONTCARE32_SHIFT            (0U)
/*! DONTCARE32 - Don't Care Data, 32 bits
 */
#define SMSCM_SCTRM1_DONTCARE32(x)               (((uint32_t)(((uint32_t)(x)) << SMSCM_SCTRM1_DONTCARE32_SHIFT)) & SMSCM_SCTRM1_DONTCARE32_MASK)
/*! @} */

/*! @name SCTRPX - Security Counter Plus X Register */
/*! @{ */

#define SMSCM_SCTRPX_DATA32_MASK                 (0xFFFFFFFFU)
#define SMSCM_SCTRPX_DATA32_SHIFT                (0U)
/*! DATA32 - Data, 32 bits
 */
#define SMSCM_SCTRPX_DATA32(x)                   (((uint32_t)(((uint32_t)(x)) << SMSCM_SCTRPX_DATA32_SHIFT)) & SMSCM_SCTRPX_DATA32_MASK)
/*! @} */

/*! @name SCTRMX - Security Counter Minus X Register */
/*! @{ */

#define SMSCM_SCTRMX_DATA32_MASK                 (0xFFFFFFFFU)
#define SMSCM_SCTRMX_DATA32_SHIFT                (0U)
/*! DATA32 - Data, 32 bits
 */
#define SMSCM_SCTRMX_DATA32(x)                   (((uint32_t)(((uint32_t)(x)) << SMSCM_SCTRMX_DATA32_SHIFT)) & SMSCM_SCTRMX_DATA32_MASK)
/*! @} */

/*! @name OCMDR0 - On-Chip Memory Descriptor Register */
/*! @{ */

#define SMSCM_OCMDR0_OCMCF0_MASK                 (0xFU)
#define SMSCM_OCMDR0_OCMCF0_SHIFT                (0U)
/*! OCMCF0 - OCMEM Control Field 0
 */
#define SMSCM_OCMDR0_OCMCF0(x)                   (((uint32_t)(((uint32_t)(x)) << SMSCM_OCMDR0_OCMCF0_SHIFT)) & SMSCM_OCMDR0_OCMCF0_MASK)

#define SMSCM_OCMDR0_OCMCF1_MASK                 (0xF0U)
#define SMSCM_OCMDR0_OCMCF1_SHIFT                (4U)
/*! OCMCF1 - OCMEM Control Field 1
 */
#define SMSCM_OCMDR0_OCMCF1(x)                   (((uint32_t)(((uint32_t)(x)) << SMSCM_OCMDR0_OCMCF1_SHIFT)) & SMSCM_OCMDR0_OCMCF1_MASK)

#define SMSCM_OCMDR0_OCMCF2_MASK                 (0xF00U)
#define SMSCM_OCMDR0_OCMCF2_SHIFT                (8U)
/*! OCMCF2 - OCMEM Control Field 2
 */
#define SMSCM_OCMDR0_OCMCF2(x)                   (((uint32_t)(((uint32_t)(x)) << SMSCM_OCMDR0_OCMCF2_SHIFT)) & SMSCM_OCMDR0_OCMCF2_MASK)

#define SMSCM_OCMDR0_RO_MASK                     (0x10000U)
#define SMSCM_OCMDR0_RO_SHIFT                    (16U)
/*! RO - Read-Only
 *  0b0..Writes to the OCMDRn[11:0] are allowed
 *  0b1..Writes to the OCMDRn[11:0] are ignored
 */
#define SMSCM_OCMDR0_RO(x)                       (((uint32_t)(((uint32_t)(x)) << SMSCM_OCMDR0_RO_SHIFT)) & SMSCM_OCMDR0_RO_MASK)
/*! @} */

/*! @name OCMDR2 - On-Chip Memory Descriptor Register */
/*! @{ */

#define SMSCM_OCMDR2_OCMCF0_MASK                 (0xFU)
#define SMSCM_OCMDR2_OCMCF0_SHIFT                (0U)
/*! OCMCF0 - OCMEM Control Field 0
 */
#define SMSCM_OCMDR2_OCMCF0(x)                   (((uint32_t)(((uint32_t)(x)) << SMSCM_OCMDR2_OCMCF0_SHIFT)) & SMSCM_OCMDR2_OCMCF0_MASK)

#define SMSCM_OCMDR2_RO_MASK                     (0x10000U)
#define SMSCM_OCMDR2_RO_SHIFT                    (16U)
/*! RO - Read-Only
 *  0b0..Writes to the OCMDRn[11:0] are allowed
 *  0b1..Writes to the OCMDRn[11:0] are ignored
 */
#define SMSCM_OCMDR2_RO(x)                       (((uint32_t)(((uint32_t)(x)) << SMSCM_OCMDR2_RO_SHIFT)) & SMSCM_OCMDR2_RO_MASK)
/*! @} */

/*! @name OCMDR3 - On-Chip Memory Descriptor Register */
/*! @{ */

#define SMSCM_OCMDR3_OCMCF0_MASK                 (0xFU)
#define SMSCM_OCMDR3_OCMCF0_SHIFT                (0U)
/*! OCMCF0 - OCMEM Control Field 0
 */
#define SMSCM_OCMDR3_OCMCF0(x)                   (((uint32_t)(((uint32_t)(x)) << SMSCM_OCMDR3_OCMCF0_SHIFT)) & SMSCM_OCMDR3_OCMCF0_MASK)

#define SMSCM_OCMDR3_RO_MASK                     (0x10000U)
#define SMSCM_OCMDR3_RO_SHIFT                    (16U)
/*! RO - Read-Only
 *  0b0..Writes to the OCMDRn[11:0] are allowed
 *  0b1..Writes to the OCMDRn[11:0] are ignored
 */
#define SMSCM_OCMDR3_RO(x)                       (((uint32_t)(((uint32_t)(x)) << SMSCM_OCMDR3_RO_SHIFT)) & SMSCM_OCMDR3_RO_MASK)
/*! @} */

/*! @name OCMDR5 - On-Chip Memory Descriptor Register */
/*! @{ */

#define SMSCM_OCMDR5_OCMCF0_MASK                 (0xFU)
#define SMSCM_OCMDR5_OCMCF0_SHIFT                (0U)
/*! OCMCF0 - OCMEM Control Field 0
 */
#define SMSCM_OCMDR5_OCMCF0(x)                   (((uint32_t)(((uint32_t)(x)) << SMSCM_OCMDR5_OCMCF0_SHIFT)) & SMSCM_OCMDR5_OCMCF0_MASK)

#define SMSCM_OCMDR5_RO_MASK                     (0x10000U)
#define SMSCM_OCMDR5_RO_SHIFT                    (16U)
/*! RO - Read-Only
 *  0b0..Writes to the OCMDRn[11:0] are allowed
 *  0b1..Writes to the OCMDRn[11:0] are ignored
 */
#define SMSCM_OCMDR5_RO(x)                       (((uint32_t)(((uint32_t)(x)) << SMSCM_OCMDR5_RO_SHIFT)) & SMSCM_OCMDR5_RO_MASK)
/*! @} */

/*! @name OCMECR - On-Chip Memory ECC Control Register */
/*! @{ */

#define SMSCM_OCMECR_ENCR_MASK                   (0x1U)
#define SMSCM_OCMECR_ENCR_SHIFT                  (0U)
/*! ENCR - Enable RAM ECC Non-correctable Reporting
 *  0b0..Non-correctable reporting disabled
 *  0b1..Non-correctable reporting enabled
 */
#define SMSCM_OCMECR_ENCR(x)                     (((uint32_t)(((uint32_t)(x)) << SMSCM_OCMECR_ENCR_SHIFT)) & SMSCM_OCMECR_ENCR_MASK)

#define SMSCM_OCMECR_E1BR_MASK                   (0x100U)
#define SMSCM_OCMECR_E1BR_SHIFT                  (8U)
/*! E1BR - Enable RAM ECC 1 Bit Reporting
 *  0b0..1-bit reporting disabled
 *  0b1..1-bit reporting enabled
 */
#define SMSCM_OCMECR_E1BR(x)                     (((uint32_t)(((uint32_t)(x)) << SMSCM_OCMECR_E1BR_SHIFT)) & SMSCM_OCMECR_E1BR_MASK)
/*! @} */

/*! @name OCMEIR - On-Chip Memory ECC Interrupt Register */
/*! @{ */

#define SMSCM_OCMEIR_ENCERRN_MASK                (0xFFU)
#define SMSCM_OCMEIR_ENCERRN_SHIFT               (0U)
/*! ENCERRN - ECC Non-correctable Error OCRAMn
 */
#define SMSCM_OCMEIR_ENCERRN(x)                  (((uint32_t)(((uint32_t)(x)) << SMSCM_OCMEIR_ENCERRN_SHIFT)) & SMSCM_OCMEIR_ENCERRN_MASK)

#define SMSCM_OCMEIR_E1BERRN_MASK                (0xFF00U)
#define SMSCM_OCMEIR_E1BERRN_SHIFT               (8U)
/*! E1BERRN - ECC 1-bit Error OCRAMn
 */
#define SMSCM_OCMEIR_E1BERRN(x)                  (((uint32_t)(((uint32_t)(x)) << SMSCM_OCMEIR_E1BERRN_SHIFT)) & SMSCM_OCMEIR_E1BERRN_MASK)

#define SMSCM_OCMEIR_EELOC_MASK                  (0xF000000U)
#define SMSCM_OCMEIR_EELOC_SHIFT                 (24U)
/*! EELOC - ECC Error Location
 *  0b0000..non-correctable on OCRAM0
 *  0b0001..non-correctable on OCRAM1
 *  0b0010..non-correctable on OCRAM2
 *  0b0011..non-correctable on OCRAM3
 *  0b0100..non-correctable on OCRAM4
 *  0b0101..non-correctable on OCRAM5
 *  0b0110..non-correctable on OCRAM6
 *  0b0111..non-correctable on OCRAM7
 *  0b1000..1-bit correctable on OCRAM0
 *  0b1001..1-bit correctable on OCRAM1
 *  0b1010..1-bit correctable on OCRAM2
 *  0b1011..1-bit correctable on OCRAM3
 *  0b1100..1-bit correctable on OCRAM4
 *  0b1101..1-bit correctable on OCRAM5
 *  0b1110..1-bit correctable on OCRAM6
 *  0b1111..1-bit correctable on OCRAM7
 */
#define SMSCM_OCMEIR_EELOC(x)                    (((uint32_t)(((uint32_t)(x)) << SMSCM_OCMEIR_EELOC_SHIFT)) & SMSCM_OCMEIR_EELOC_MASK)

#define SMSCM_OCMEIR_VALID_MASK                  (0x80000000U)
#define SMSCM_OCMEIR_VALID_SHIFT                 (31U)
/*! VALID - Valid ECC Error Location field
 *  0b0..ECC Error Location field is not valid
 *  0b1..ECC Error Location field is valid
 */
#define SMSCM_OCMEIR_VALID(x)                    (((uint32_t)(((uint32_t)(x)) << SMSCM_OCMEIR_VALID_SHIFT)) & SMSCM_OCMEIR_VALID_MASK)
/*! @} */

/*! @name OCMFAR - On-Chip Memory Fault Address Register */
/*! @{ */

#define SMSCM_OCMFAR_EFADD_MASK                  (0xFFFFFFFFU)
#define SMSCM_OCMFAR_EFADD_SHIFT                 (0U)
/*! EFADD - ECC Fault Address
 */
#define SMSCM_OCMFAR_EFADD(x)                    (((uint32_t)(((uint32_t)(x)) << SMSCM_OCMFAR_EFADD_SHIFT)) & SMSCM_OCMFAR_EFADD_MASK)
/*! @} */

/*! @name OCMFTR - On-Chip Memory Fault Attribute Register */
/*! @{ */

#define SMSCM_OCMFTR_EFPRT_MASK                  (0xFU)
#define SMSCM_OCMFTR_EFPRT_SHIFT                 (0U)
/*! EFPRT - On-Chip Memory ECC Fault Protection
 */
#define SMSCM_OCMFTR_EFPRT(x)                    (((uint32_t)(((uint32_t)(x)) << SMSCM_OCMFTR_EFPRT_SHIFT)) & SMSCM_OCMFTR_EFPRT_MASK)

#define SMSCM_OCMFTR_EFMS_MASK                   (0x70U)
#define SMSCM_OCMFTR_EFMS_SHIFT                  (4U)
/*! EFMS - On-Chip Memory ECC Fault Master Size
 *  0b000..8-bit size
 *  0b001..16-bit size
 *  0b010..32-bit size
 *  0b011..64-bit size
 *  0b100..Reserved
 *  0b101..Reserved
 *  0b110..Reserved
 *  0b111..Reserved
 */
#define SMSCM_OCMFTR_EFMS(x)                     (((uint32_t)(((uint32_t)(x)) << SMSCM_OCMFTR_EFMS_SHIFT)) & SMSCM_OCMFTR_EFMS_MASK)

#define SMSCM_OCMFTR_EFW_MASK                    (0x80U)
#define SMSCM_OCMFTR_EFW_SHIFT                   (7U)
/*! EFW - On-Chip Memory ECC Fault Write
 *  0b0..Last captured ECC event was not a write bus cycle
 *  0b1..Last captured ECC event was a write bus cycle
 */
#define SMSCM_OCMFTR_EFW(x)                      (((uint32_t)(((uint32_t)(x)) << SMSCM_OCMFTR_EFW_SHIFT)) & SMSCM_OCMFTR_EFW_MASK)

#define SMSCM_OCMFTR_EFMST_MASK                  (0xFF00U)
#define SMSCM_OCMFTR_EFMST_SHIFT                 (8U)
/*! EFMST - On-Chip Memory ECC Fault Master Number
 */
#define SMSCM_OCMFTR_EFMST(x)                    (((uint32_t)(((uint32_t)(x)) << SMSCM_OCMFTR_EFMST_SHIFT)) & SMSCM_OCMFTR_EFMST_MASK)

#define SMSCM_OCMFTR_EFSYN_MASK                  (0xFF0000U)
#define SMSCM_OCMFTR_EFSYN_SHIFT                 (16U)
/*! EFSYN - On-Chip Memory ECC Fault Syndrome
 */
#define SMSCM_OCMFTR_EFSYN(x)                    (((uint32_t)(((uint32_t)(x)) << SMSCM_OCMFTR_EFSYN_SHIFT)) & SMSCM_OCMFTR_EFSYN_MASK)
/*! @} */

/*! @name OCMFDRH - On-Chip Memory ECC Fault Data High Register */
/*! @{ */

#define SMSCM_OCMFDRH_EFDH_MASK                  (0xFFFFFFFFU)
#define SMSCM_OCMFDRH_EFDH_SHIFT                 (0U)
/*! EFDH - On-Chip Memory ECC Fault Data High
 */
#define SMSCM_OCMFDRH_EFDH(x)                    (((uint32_t)(((uint32_t)(x)) << SMSCM_OCMFDRH_EFDH_SHIFT)) & SMSCM_OCMFDRH_EFDH_MASK)
/*! @} */

/*! @name OCMFDRL - On-Chip Memory ECC Fault Data Low Register */
/*! @{ */

#define SMSCM_OCMFDRL_EFDL_MASK                  (0xFFFFFFFFU)
#define SMSCM_OCMFDRL_EFDL_SHIFT                 (0U)
/*! EFDL - On-Chip Memory ECC Fault Data Low
 */
#define SMSCM_OCMFDRL_EFDL(x)                    (((uint32_t)(((uint32_t)(x)) << SMSCM_OCMFDRL_EFDL_SHIFT)) & SMSCM_OCMFDRL_EFDL_MASK)
/*! @} */

/*! @name CPCR - Core Platform Control Register */
/*! @{ */

#define SMSCM_CPCR_AXBS0_RREN_MASK               (0x1U)
#define SMSCM_CPCR_AXBS0_RREN_SHIFT              (0U)
/*! AXBS0_RREN - AXBS0 Round Robin Enable
 *  0b0..AXBS0 in fixed priority arbitration mode at reset.
 *  0b1..AXBS0 in round robin arbitration mode at reset.
 */
#define SMSCM_CPCR_AXBS0_RREN(x)                 (((uint32_t)(((uint32_t)(x)) << SMSCM_CPCR_AXBS0_RREN_SHIFT)) & SMSCM_CPCR_AXBS0_RREN_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group SMSCM_Register_Masks */


/* SMSCM - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral SMSCM base address */
  #define SMSCM_BASE                               (0x50015000u)
  /** Peripheral SMSCM base address */
  #define SMSCM_BASE_NS                            (0x40015000u)
  /** Peripheral SMSCM base pointer */
  #define SMSCM                                    ((SMSCM_Type *)SMSCM_BASE)
  /** Peripheral SMSCM base pointer */
  #define SMSCM_NS                                 ((SMSCM_Type *)SMSCM_BASE_NS)
  /** Array initializer of SMSCM peripheral base addresses */
  #define SMSCM_BASE_ADDRS                         { SMSCM_BASE }
  /** Array initializer of SMSCM peripheral base pointers */
  #define SMSCM_BASE_PTRS                          { SMSCM }
  /** Array initializer of SMSCM peripheral base addresses */
  #define SMSCM_BASE_ADDRS_NS                      { SMSCM_BASE_NS }
  /** Array initializer of SMSCM peripheral base pointers */
  #define SMSCM_BASE_PTRS_NS                       { SMSCM_NS }
#else
  /** Peripheral SMSCM base address */
  #define SMSCM_BASE                               (0x40015000u)
  /** Peripheral SMSCM base pointer */
  #define SMSCM                                    ((SMSCM_Type *)SMSCM_BASE)
  /** Array initializer of SMSCM peripheral base addresses */
  #define SMSCM_BASE_ADDRS                         { SMSCM_BASE }
  /** Array initializer of SMSCM peripheral base pointers */
  #define SMSCM_BASE_PTRS                          { SMSCM }
#endif

/*!
 * @}
 */ /* end of group SMSCM_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- SPC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SPC_Peripheral_Access_Layer SPC Peripheral Access Layer
 * @{
 */

/** SPC - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
       uint8_t RESERVED_0[12];
  __IO uint32_t SC;                                /**< SPC Status Control Register, offset: 0x10 */
  __IO uint32_t CNTRL;                             /**< SPC Regulator Control Register, offset: 0x14 */
  __IO uint32_t TRIM_LOCK;                         /**< TRIM LOCK Register, offset: 0x18 */
  __IO uint32_t LPREQ_CFG;                         /**< Low Power Request Configuration Register, offset: 0x1C */
  __IO uint32_t CFG;                               /**< SPC Configuration Register, offset: 0x20 */
       uint8_t RESERVED_1[12];
  __IO uint32_t PD_STATUS[3];                      /**< SPC Power Domain Mode Status Register, array offset: 0x30, array step: 0x4 */
       uint8_t RESERVED_2[4];
  __IO uint32_t SRAMCTL;                           /**< SRAM Control Register, offset: 0x40 */
       uint8_t RESERVED_3[156];
  __IO uint32_t WAKEUP;                            /**< General Purpose Wakeup Register, offset: 0xE0 */
       uint8_t RESERVED_4[28];
  __IO uint32_t ACTIVE_CFG;                        /**< Active Power Mode Configuration Register, offset: 0x100 */
  __IO uint32_t LP_CFG;                            /**< Low Power Mode Configuration Register, offset: 0x104 */
       uint8_t RESERVED_5[24];
  __IO uint32_t LPWKUP_DELAY;                      /**< Low Power Wake Up Delay Register, offset: 0x120 */
  __IO uint32_t ACTIVE_VDELAY;                     /**< Active Voltage Trim Delay Register, offset: 0x124 */
       uint8_t RESERVED_6[8];
  __IO uint32_t VD_STAT;                           /**< Voltage Detect Status Register, offset: 0x130 */
  __IO uint32_t VD_CORE_CFG;                       /**< Core Voltage Detect Configuration Register, offset: 0x134 */
  __IO uint32_t VD_SYS_CFG;                        /**< System Voltage Detect Configuration Register, offset: 0x138 */
  __IO uint32_t VD_IO_CFG;                         /**< IO Voltage Detect Configuration Register, offset: 0x13C */
  __IO uint32_t EVD_CFG;                           /**< External Voltage Domain Configuration Register, offset: 0x140 */
  __IO uint32_t VDD_CORE_GLITCH_DETECT_SC;         /**< VDD Core Glitch Detect Status Control Register, offset: 0x144 */
       uint8_t RESERVED_7[440];
  __IO uint32_t CORELDO_CFG;                       /**< LDO_CORE Configuration Register, offset: 0x300 */
       uint8_t RESERVED_8[252];
  __IO uint32_t SYSLDO_CFG;                        /**< LDO_SYS Configuration Register, offset: 0x400 */
  __IO uint32_t SYSLDO_FPTRIM;                     /**< LDO_SYS Regulator Full Power Trim Register, offset: 0x404 */
       uint8_t RESERVED_9[248];
  __IO uint32_t DCDC_CFG;                          /**< DCDC Configuration Register, offset: 0x500 */
  __IO uint32_t DCDC_BURST_CFG;                    /**< DCDC BURST Configuration Register, offset: 0x504 */
  __IO uint32_t DCDC_VTRIM;                        /**< DCDC Voltage Trim Register, offset: 0x508 */
  __IO uint32_t DCDC_LPVTRIM;                      /**< DCDC Low Power Voltage Trim Register, offset: 0x50C */
       uint8_t RESERVED_10[224];
  __IO uint32_t DCDC_TEST;                         /**< DCDC Test Control Register, offset: 0x5F0 */
} SPC_Type;

/* ----------------------------------------------------------------------------
   -- SPC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SPC_Register_Masks SPC Register Masks
 * @{
 */

/*! @name VERID - Version ID Register */
/*! @{ */

#define SPC_VERID_FEATURE_MASK                   (0xFFFFU)
#define SPC_VERID_FEATURE_SHIFT                  (0U)
/*! FEATURE - Feature Specification Number
 *  0b0000000000000000..Standard features implemented.
 */
#define SPC_VERID_FEATURE(x)                     (((uint32_t)(((uint32_t)(x)) << SPC_VERID_FEATURE_SHIFT)) & SPC_VERID_FEATURE_MASK)

#define SPC_VERID_MINOR_MASK                     (0xFF0000U)
#define SPC_VERID_MINOR_SHIFT                    (16U)
/*! MINOR - Minor Version Number
 */
#define SPC_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << SPC_VERID_MINOR_SHIFT)) & SPC_VERID_MINOR_MASK)

#define SPC_VERID_MAJOR_MASK                     (0xFF000000U)
#define SPC_VERID_MAJOR_SHIFT                    (24U)
/*! MAJOR - Major Version Number
 */
#define SPC_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << SPC_VERID_MAJOR_SHIFT)) & SPC_VERID_MAJOR_MASK)
/*! @} */

/*! @name SC - SPC Status Control Register */
/*! @{ */

#define SPC_SC_BUSY_MASK                         (0x1U)
#define SPC_SC_BUSY_SHIFT                        (0U)
/*! BUSY - SPC Busy Status Flag
 *  0b0..SPC NOT BUSY.
 *  0b1..SPC IS BUSY.
 */
#define SPC_SC_BUSY(x)                           (((uint32_t)(((uint32_t)(x)) << SPC_SC_BUSY_SHIFT)) & SPC_SC_BUSY_MASK)

#define SPC_SC_SPC_LP_REQ_MASK                   (0x2U)
#define SPC_SC_SPC_LP_REQ_SHIFT                  (1U)
/*! SPC_LP_REQ - SPC Power Mode Configuration Status Flag
 *  0b0..SPC in active mode and ACTIVE_CFG register has control.
 *  0b1..All Power Domains have requested low power mode and SPC has entered a low power state and power mode
 *       configuration are based from the LP_CFG configuration register.
 */
#define SPC_SC_SPC_LP_REQ(x)                     (((uint32_t)(((uint32_t)(x)) << SPC_SC_SPC_LP_REQ_SHIFT)) & SPC_SC_SPC_LP_REQ_MASK)

#define SPC_SC_SPC_LP_MODE_MASK                  (0xF0U)
#define SPC_SC_SPC_LP_MODE_SHIFT                 (4U)
/*! SPC_LP_MODE - Power Domain Low Power Mode Request
 *  0b0000..SLEEP with SYS clock running
 *  0b0001..SLEEP with SYS clock OFF
 *  0b0010..DSLEEP with SYS clock OFF
 *  0b0100..PDOWN with SYS clock OFF
 *  0b1000..DPDOWN with SYS clock OFF
 */
#define SPC_SC_SPC_LP_MODE(x)                    (((uint32_t)(((uint32_t)(x)) << SPC_SC_SPC_LP_MODE_SHIFT)) & SPC_SC_SPC_LP_MODE_MASK)

#define SPC_SC_ISO_CLR_MASK                      (0x70000U)
#define SPC_SC_ISO_CLR_SHIFT                     (16U)
/*! ISO_CLR - Isolation Clear
 */
#define SPC_SC_ISO_CLR(x)                        (((uint32_t)(((uint32_t)(x)) << SPC_SC_ISO_CLR_SHIFT)) & SPC_SC_ISO_CLR_MASK)

#define SPC_SC_SWITCH_STATE_MASK                 (0x80000000U)
#define SPC_SC_SWITCH_STATE_SHIFT                (31U)
/*! SWITCH_STATE - Power Switch State
 *  0b0..OFF
 *  0b1..ON
 */
#define SPC_SC_SWITCH_STATE(x)                   (((uint32_t)(((uint32_t)(x)) << SPC_SC_SWITCH_STATE_SHIFT)) & SPC_SC_SWITCH_STATE_MASK)
/*! @} */

/*! @name CNTRL - SPC Regulator Control Register */
/*! @{ */

#define SPC_CNTRL_CORELDO_EN_MASK                (0x1U)
#define SPC_CNTRL_CORELDO_EN_SHIFT               (0U)
/*! CORELDO_EN - LDO_CORE Regulator Enable
 *  0b0..LDO_CORE Regulator Disabled
 *  0b1..LDO_CORE Regulator Enabled
 */
#define SPC_CNTRL_CORELDO_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SPC_CNTRL_CORELDO_EN_SHIFT)) & SPC_CNTRL_CORELDO_EN_MASK)

#define SPC_CNTRL_SYSLDO_EN_MASK                 (0x2U)
#define SPC_CNTRL_SYSLDO_EN_SHIFT                (1U)
/*! SYSLDO_EN - LDO_SYS Regulator Enable
 *  0b0..LDO_SYS Regulator Disabled
 *  0b1..LDO_SYS Regulator Enabled
 */
#define SPC_CNTRL_SYSLDO_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SPC_CNTRL_SYSLDO_EN_SHIFT)) & SPC_CNTRL_SYSLDO_EN_MASK)

#define SPC_CNTRL_DCDC_EN_MASK                   (0x4U)
#define SPC_CNTRL_DCDC_EN_SHIFT                  (2U)
/*! DCDC_EN - DCDC_CORE Regulator Enable
 *  0b0..DCDC_CORE Regulator Disabled
 *  0b1..DCDC_CORE Regulator Enabled
 */
#define SPC_CNTRL_DCDC_EN(x)                     (((uint32_t)(((uint32_t)(x)) << SPC_CNTRL_DCDC_EN_SHIFT)) & SPC_CNTRL_DCDC_EN_MASK)
/*! @} */

/*! @name TRIM_LOCK - TRIM LOCK Register */
/*! @{ */

#define SPC_TRIM_LOCK_TRIM_UNLOCK_MASK           (0x1U)
#define SPC_TRIM_LOCK_TRIM_UNLOCK_SHIFT          (0U)
/*! TRIM_UNLOCK - TRIM_UNLOCK
 *  0b0..SPC Trim Registers locked and not writable.
 *  0b1..SPC Trim registers un-locked and writable.
 */
#define SPC_TRIM_LOCK_TRIM_UNLOCK(x)             (((uint32_t)(((uint32_t)(x)) << SPC_TRIM_LOCK_TRIM_UNLOCK_SHIFT)) & SPC_TRIM_LOCK_TRIM_UNLOCK_MASK)

#define SPC_TRIM_LOCK_IFR_DISABLE_MASK           (0x2U)
#define SPC_TRIM_LOCK_IFR_DISABLE_SHIFT          (1U)
/*! IFR_DISABLE - IFR_DISABLE
 *  0b0..IFR write access to SPC trim registers not disabled. SPC Trim registers will be reprogrammed with the IFR values after any system reset.
 *  0b1..IFR write access to SPC trim registers during system reset will be block.
 */
#define SPC_TRIM_LOCK_IFR_DISABLE(x)             (((uint32_t)(((uint32_t)(x)) << SPC_TRIM_LOCK_IFR_DISABLE_SHIFT)) & SPC_TRIM_LOCK_IFR_DISABLE_MASK)

#define SPC_TRIM_LOCK_TRIM_LOCK_KEY_MASK         (0xFFFF0000U)
#define SPC_TRIM_LOCK_TRIM_LOCK_KEY_SHIFT        (16U)
/*! TRIM_LOCK_KEY - TRIM_LOCK_KEY
 */
#define SPC_TRIM_LOCK_TRIM_LOCK_KEY(x)           (((uint32_t)(((uint32_t)(x)) << SPC_TRIM_LOCK_TRIM_LOCK_KEY_SHIFT)) & SPC_TRIM_LOCK_TRIM_LOCK_KEY_MASK)
/*! @} */

/*! @name LPREQ_CFG - Low Power Request Configuration Register */
/*! @{ */

#define SPC_LPREQ_CFG_LPREQOE_MASK               (0x1U)
#define SPC_LPREQ_CFG_LPREQOE_SHIFT              (0U)
/*! LPREQOE - Low Power Request Output Enable
 *  0b0..Low Power request output pin not enabled.
 *  0b1..Low Power request output pin enabled.
 */
#define SPC_LPREQ_CFG_LPREQOE(x)                 (((uint32_t)(((uint32_t)(x)) << SPC_LPREQ_CFG_LPREQOE_SHIFT)) & SPC_LPREQ_CFG_LPREQOE_MASK)

#define SPC_LPREQ_CFG_LPREQPOL_MASK              (0x2U)
#define SPC_LPREQ_CFG_LPREQPOL_SHIFT             (1U)
/*! LPREQPOL - Low Power Request Output Pin Polarity Control
 *  0b0..High true polarity.
 *  0b1..Low true polarity.
 */
#define SPC_LPREQ_CFG_LPREQPOL(x)                (((uint32_t)(((uint32_t)(x)) << SPC_LPREQ_CFG_LPREQPOL_SHIFT)) & SPC_LPREQ_CFG_LPREQPOL_MASK)

#define SPC_LPREQ_CFG_LPREQOV_MASK               (0xCU)
#define SPC_LPREQ_CFG_LPREQOV_SHIFT              (2U)
/*! LPREQOV - Low Power Request Output Override
 *  0b00..Not Forced.
 *  0b01..Reserved.
 *  0b10..Forced Low (ignore LPREQPOL settings).
 *  0b11..Forced high (ignore LPREQPOL settings).
 */
#define SPC_LPREQ_CFG_LPREQOV(x)                 (((uint32_t)(((uint32_t)(x)) << SPC_LPREQ_CFG_LPREQOV_SHIFT)) & SPC_LPREQ_CFG_LPREQOV_MASK)
/*! @} */

/*! @name CFG - SPC Configuration Register */
/*! @{ */

#define SPC_CFG_INTG_PWSWTCH_SLEEP_EN_MASK       (0x1U)
#define SPC_CFG_INTG_PWSWTCH_SLEEP_EN_SHIFT      (0U)
/*! INTG_PWSWTCH_SLEEP_EN - Integrated power switch sleep enable.
 *  0b0..Sleep Integrated power switch disabled.
 *  0b1..Integrated power switch enabled in low power modes.
 */
#define SPC_CFG_INTG_PWSWTCH_SLEEP_EN(x)         (((uint32_t)(((uint32_t)(x)) << SPC_CFG_INTG_PWSWTCH_SLEEP_EN_SHIFT)) & SPC_CFG_INTG_PWSWTCH_SLEEP_EN_MASK)

#define SPC_CFG_INTG_PWSWTCH_WKUP_EN_MASK        (0x2U)
#define SPC_CFG_INTG_PWSWTCH_WKUP_EN_SHIFT       (1U)
/*! INTG_PWSWTCH_WKUP_EN - Integrated power switch wakeup enable.
 *  0b0..Sleep Integrated power switch disabled.
 *  0b1..Integrated power switch enabled in low power modes.
 */
#define SPC_CFG_INTG_PWSWTCH_WKUP_EN(x)          (((uint32_t)(((uint32_t)(x)) << SPC_CFG_INTG_PWSWTCH_WKUP_EN_SHIFT)) & SPC_CFG_INTG_PWSWTCH_WKUP_EN_MASK)

#define SPC_CFG_INTG_PWSWTCH_SLEEP_ACTIVE_EN_MASK (0x4U)
#define SPC_CFG_INTG_PWSWTCH_SLEEP_ACTIVE_EN_SHIFT (2U)
/*! INTG_PWSWTCH_SLEEP_ACTIVE_EN - Integrated power switch active enable.
 *  0b0..Integrated power switch disabled.
 *  0b1..Integrated power switch enabled in active modes.
 */
#define SPC_CFG_INTG_PWSWTCH_SLEEP_ACTIVE_EN(x)  (((uint32_t)(((uint32_t)(x)) << SPC_CFG_INTG_PWSWTCH_SLEEP_ACTIVE_EN_SHIFT)) & SPC_CFG_INTG_PWSWTCH_SLEEP_ACTIVE_EN_MASK)

#define SPC_CFG_INTG_PWSWTCH_WKUP_ACTIVE_EN_MASK (0x8U)
#define SPC_CFG_INTG_PWSWTCH_WKUP_ACTIVE_EN_SHIFT (3U)
/*! INTG_PWSWTCH_WKUP_ACTIVE_EN - Integrated power switch wakeup enable.
 *  0b0..Sleep Integrated power switch disabled.
 *  0b1..Integrated power switch enabled in active modes.
 */
#define SPC_CFG_INTG_PWSWTCH_WKUP_ACTIVE_EN(x)   (((uint32_t)(((uint32_t)(x)) << SPC_CFG_INTG_PWSWTCH_WKUP_ACTIVE_EN_SHIFT)) & SPC_CFG_INTG_PWSWTCH_WKUP_ACTIVE_EN_MASK)
/*! @} */

/*! @name PD_STATUS - SPC Power Domain Mode Status Register */
/*! @{ */

#define SPC_PD_STATUS_PWR_REQ_STATUS_MASK        (0x1U)
#define SPC_PD_STATUS_PWR_REQ_STATUS_SHIFT       (0U)
/*! PWR_REQ_STATUS - Power Request Status Flag
 *  0b0..Low power mode NOT requested.
 *  0b1..Low power mode requested
 */
#define SPC_PD_STATUS_PWR_REQ_STATUS(x)          (((uint32_t)(((uint32_t)(x)) << SPC_PD_STATUS_PWR_REQ_STATUS_SHIFT)) & SPC_PD_STATUS_PWR_REQ_STATUS_MASK)

#define SPC_PD_STATUS_PD_LP_REQ_MASK             (0x10U)
#define SPC_PD_STATUS_PD_LP_REQ_SHIFT            (4U)
/*! PD_LP_REQ - Power Domain Low Power Request Flag
 *  0b0..Low power mode not requested.
 *  0b1..Low power mode requested
 */
#define SPC_PD_STATUS_PD_LP_REQ(x)               (((uint32_t)(((uint32_t)(x)) << SPC_PD_STATUS_PD_LP_REQ_SHIFT)) & SPC_PD_STATUS_PD_LP_REQ_MASK)

#define SPC_PD_STATUS_LP_MODE_MASK               (0xF00U)
#define SPC_PD_STATUS_LP_MODE_SHIFT              (8U)
/*! LP_MODE - Power Domain Low Power Mode Request
 *  0b0000..SLEEP with SYS clock running
 *  0b0001..SLEEP with SYS clock off
 *  0b0010..DSLEEP with SYS clock off
 *  0b0100..PDOWN with SYS clock OFF
 *  0b1000..DPDOWN with SYS clock off
 */
#define SPC_PD_STATUS_LP_MODE(x)                 (((uint32_t)(((uint32_t)(x)) << SPC_PD_STATUS_LP_MODE_SHIFT)) & SPC_PD_STATUS_LP_MODE_MASK)
/*! @} */

/* The count of SPC_PD_STATUS */
#define SPC_PD_STATUS_COUNT                      (3U)

/*! @name SRAMCTL - SRAM Control Register */
/*! @{ */

#define SPC_SRAMCTL_VSM_MASK                     (0x3U)
#define SPC_SRAMCTL_VSM_SHIFT                    (0U)
/*! VSM - Voltage Select Margin
 *  0b00..Reserved
 *  0b01..SRAM configured for 1.0 V operation
 *  0b10..SRAM configured for 1.1 V operation
 *  0b11..SRAM configured for 1.1 V operation
 */
#define SPC_SRAMCTL_VSM(x)                       (((uint32_t)(((uint32_t)(x)) << SPC_SRAMCTL_VSM_SHIFT)) & SPC_SRAMCTL_VSM_MASK)

#define SPC_SRAMCTL_REQ_MASK                     (0x40000000U)
#define SPC_SRAMCTL_REQ_SHIFT                    (30U)
/*! REQ - SRAM Voltage Update Request
 *  0b0..SRAM trim value change has not been requested
 *  0b1..SRAM trim value change requested
 */
#define SPC_SRAMCTL_REQ(x)                       (((uint32_t)(((uint32_t)(x)) << SPC_SRAMCTL_REQ_SHIFT)) & SPC_SRAMCTL_REQ_MASK)

#define SPC_SRAMCTL_ACK_MASK                     (0x80000000U)
#define SPC_SRAMCTL_ACK_SHIFT                    (31U)
/*! ACK - SRAM Voltage Update Request Acknowledge
 *  0b0..SRAM trim value change not acknowledged
 *  0b1..SRAM trim value change requested has been acknowledged
 */
#define SPC_SRAMCTL_ACK(x)                       (((uint32_t)(((uint32_t)(x)) << SPC_SRAMCTL_ACK_SHIFT)) & SPC_SRAMCTL_ACK_MASK)
/*! @} */

/*! @name WAKEUP - General Purpose Wakeup Register */
/*! @{ */

#define SPC_WAKEUP_WAKEUP_MASK                   (0xFFFFFFFFU)
#define SPC_WAKEUP_WAKEUP_SHIFT                  (0U)
/*! WAKEUP - Wakeup Register
 */
#define SPC_WAKEUP_WAKEUP(x)                     (((uint32_t)(((uint32_t)(x)) << SPC_WAKEUP_WAKEUP_SHIFT)) & SPC_WAKEUP_WAKEUP_MASK)
/*! @} */

/*! @name ACTIVE_CFG - Active Power Mode Configuration Register */
/*! @{ */

#define SPC_ACTIVE_CFG_CORELDO_VDD_LVL_MASK      (0xCU)
#define SPC_ACTIVE_CFG_CORELDO_VDD_LVL_SHIFT     (2U)
/*! CORELDO_VDD_LVL - LDO_CORE VDD Regulator Voltage Level
 *  0b00..Reserved
 *  0b01..Regulate to Mid Drive Voltage (1.0 V)
 *  0b10..Regulate to Normal Voltage (1.1 V)
 *  0b11..Regulate to Safe-Mode Voltage (1.15 V)
 */
#define SPC_ACTIVE_CFG_CORELDO_VDD_LVL(x)        (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_CORELDO_VDD_LVL_SHIFT)) & SPC_ACTIVE_CFG_CORELDO_VDD_LVL_MASK)

#define SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK        (0x10U)
#define SPC_ACTIVE_CFG_SYSLDO_VDD_DS_SHIFT       (4U)
/*! SYSLDO_VDD_DS - LDO_SYS VDD Drive Strength
 *  0b0..LDO_SYS VDD regulator Drive Strength set to Low
 *  0b1..LDO_SYS VDD regulator Drive Strength set to Normal
 */
#define SPC_ACTIVE_CFG_SYSLDO_VDD_DS(x)          (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_SYSLDO_VDD_DS_SHIFT)) & SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK)

#define SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_MASK       (0x40U)
#define SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_SHIFT      (6U)
/*! SYSLDO_VDD_LVL - LDO_SYS VDD Regulator Voltage Level
 *  0b0..Regulate to Normal Voltage (1.8 V)
 *  0b1..Regulate to Over Drive Voltage (2.5 V).
 */
#define SPC_ACTIVE_CFG_SYSLDO_VDD_LVL(x)         (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_SHIFT)) & SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_MASK)

#define SPC_ACTIVE_CFG_DCDC_VDD_DS_MASK          (0x300U)
#define SPC_ACTIVE_CFG_DCDC_VDD_DS_SHIFT         (8U)
/*! DCDC_VDD_DS - DCDC VDD Drive Strength
 *  0b00..Reserved
 *  0b01..DCDC VDD regulator Drive Strength set to Low
 *  0b10..DCDC VDD Regulator Drive Strength set to Normal
 *  0b11..Reserved
 */
#define SPC_ACTIVE_CFG_DCDC_VDD_DS(x)            (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_DCDC_VDD_DS_SHIFT)) & SPC_ACTIVE_CFG_DCDC_VDD_DS_MASK)

#define SPC_ACTIVE_CFG_DCDC_VDD_LVL_MASK         (0xC00U)
#define SPC_ACTIVE_CFG_DCDC_VDD_LVL_SHIFT        (10U)
/*! DCDC_VDD_LVL - DCDC VDD Regulator Voltage Level
 *  0b00..Regulate to Low Under Voltage (1.25 V)
 *  0b01..Regulate to Mid Voltage (1.35 V)
 *  0b10..Regulate to Normal Voltage (2.5 V)
 *  0b11..Regulate to Safe-Mode Voltage (1.8 V)
 */
#define SPC_ACTIVE_CFG_DCDC_VDD_LVL(x)           (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_DCDC_VDD_LVL_SHIFT)) & SPC_ACTIVE_CFG_DCDC_VDD_LVL_MASK)

#define SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK (0x1000U)
#define SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_SHIFT (12U)
/*! GLITCH_DETECT_DISABLE - VDD Core Glitch Detect Disable
 *  0b0..VDD Core Low Voltage Glitch Detect enabled
 *  0b1..VDD Core Low Voltage Glitch Detect disabled
 */
#define SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE(x)  (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_SHIFT)) & SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK)

#define SPC_ACTIVE_CFG_LPBUFF_EN_MASK            (0x40000U)
#define SPC_ACTIVE_CFG_LPBUFF_EN_SHIFT           (18U)
/*! LPBUFF_EN - CMP Bandgap Buffer Enable
 *  0b0..Buffer Stored Reference voltage to CMP is disabled.
 *  0b1..Buffer Stored Reference voltage to CMP is enabled.
 */
#define SPC_ACTIVE_CFG_LPBUFF_EN(x)              (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_LPBUFF_EN_SHIFT)) & SPC_ACTIVE_CFG_LPBUFF_EN_MASK)

#define SPC_ACTIVE_CFG_BGMODE_MASK               (0x300000U)
#define SPC_ACTIVE_CFG_BGMODE_SHIFT              (20U)
/*! BGMODE - Bandgap Mode
 *  0b00..Bandgap Disabled
 *  0b01..Bandgap Enabled with Buffer Disabled
 *  0b10..Bandgap Enabled with Buffer Enabled
 *  0b11..Reserved
 */
#define SPC_ACTIVE_CFG_BGMODE(x)                 (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_BGMODE_SHIFT)) & SPC_ACTIVE_CFG_BGMODE_MASK)

#define SPC_ACTIVE_CFG_CORE_LVDE_MASK            (0x1000000U)
#define SPC_ACTIVE_CFG_CORE_LVDE_SHIFT           (24U)
/*! CORE_LVDE - Core Low Voltage Detect Enable
 *  0b0..Core Low Voltage Detect disabled
 *  0b1..Core Low Voltage Detect enabled. BGMODE must be programmed so that Bandgap is enabled.
 */
#define SPC_ACTIVE_CFG_CORE_LVDE(x)              (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_CORE_LVDE_SHIFT)) & SPC_ACTIVE_CFG_CORE_LVDE_MASK)

#define SPC_ACTIVE_CFG_SYS_LVDE_MASK             (0x2000000U)
#define SPC_ACTIVE_CFG_SYS_LVDE_SHIFT            (25U)
/*! SYS_LVDE - System Low Voltage Detect Enable
 *  0b0..System Low Voltage Detect disabled
 *  0b1..System Low Voltage Detect enabled. BGMODE must be programmed so that Bandgap is enabled.
 */
#define SPC_ACTIVE_CFG_SYS_LVDE(x)               (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_SYS_LVDE_SHIFT)) & SPC_ACTIVE_CFG_SYS_LVDE_MASK)

#define SPC_ACTIVE_CFG_IO_LVDE_MASK              (0x4000000U)
#define SPC_ACTIVE_CFG_IO_LVDE_SHIFT             (26U)
/*! IO_LVDE - IO Low Voltage Detect Enable
 *  0b0..IO Low Voltage Detect disabled
 *  0b1..IO Low Voltage Detect enabled. BGMODE must be programmed so that Bandgap is enabled.
 */
#define SPC_ACTIVE_CFG_IO_LVDE(x)                (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_IO_LVDE_SHIFT)) & SPC_ACTIVE_CFG_IO_LVDE_MASK)

#define SPC_ACTIVE_CFG_CORE_HVDE_MASK            (0x8000000U)
#define SPC_ACTIVE_CFG_CORE_HVDE_SHIFT           (27U)
/*! CORE_HVDE - Core High Voltage Detect Enable
 *  0b0..Core High Voltage Detect disabled
 *  0b1..Core High Voltage Detect enabled. BGMODE must be programmed so that Bandgap is enabled.
 */
#define SPC_ACTIVE_CFG_CORE_HVDE(x)              (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_CORE_HVDE_SHIFT)) & SPC_ACTIVE_CFG_CORE_HVDE_MASK)

#define SPC_ACTIVE_CFG_SYS_HVDE_MASK             (0x10000000U)
#define SPC_ACTIVE_CFG_SYS_HVDE_SHIFT            (28U)
/*! SYS_HVDE - System High Voltage Detect Enable
 *  0b0..System High Voltage Detect disabled
 *  0b1..System High Voltage Detect enabled. BGMODE must be programmed so that Bandgap is enabled.
 */
#define SPC_ACTIVE_CFG_SYS_HVDE(x)               (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_SYS_HVDE_SHIFT)) & SPC_ACTIVE_CFG_SYS_HVDE_MASK)

#define SPC_ACTIVE_CFG_IO_HVDE_MASK              (0x20000000U)
#define SPC_ACTIVE_CFG_IO_HVDE_SHIFT             (29U)
/*! IO_HVDE - IO High Voltage Detect Enable
 *  0b0..IO High Voltage Detect disabled
 *  0b1..IO High Voltage Detect enabled. BGMODE must be programmed so that Bandgap is enabled.
 */
#define SPC_ACTIVE_CFG_IO_HVDE(x)                (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_IO_HVDE_SHIFT)) & SPC_ACTIVE_CFG_IO_HVDE_MASK)
/*! @} */

/*! @name LP_CFG - Low Power Mode Configuration Register */
/*! @{ */

#define SPC_LP_CFG_CORELDO_VDD_DS_MASK           (0x1U)
#define SPC_LP_CFG_CORELDO_VDD_DS_SHIFT          (0U)
/*! CORELDO_VDD_DS - LDO_CORE VDD Drive Strength
 *  0b0..LDO_CORE VDD Regulator Drive Strength set to Low
 *  0b1..LDO_CORE VDD Regulator Drive Strength set to Normal
 */
#define SPC_LP_CFG_CORELDO_VDD_DS(x)             (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_CORELDO_VDD_DS_SHIFT)) & SPC_LP_CFG_CORELDO_VDD_DS_MASK)

#define SPC_LP_CFG_CORELDO_VDD_LVL_MASK          (0xCU)
#define SPC_LP_CFG_CORELDO_VDD_LVL_SHIFT         (2U)
/*! CORELDO_VDD_LVL - LDO_CORE VDD Regulator Voltage Level
 *  0b00..Reserved
 *  0b01..Regulate to Mid Voltage (1.0 V)
 *  0b10..Regulate to Normal Voltage (1.1 V)
 *  0b11..Regulate to Safe-Mode Voltage (1.15 V)
 */
#define SPC_LP_CFG_CORELDO_VDD_LVL(x)            (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_CORELDO_VDD_LVL_SHIFT)) & SPC_LP_CFG_CORELDO_VDD_LVL_MASK)

#define SPC_LP_CFG_SYSLDO_VDD_DS_MASK            (0x10U)
#define SPC_LP_CFG_SYSLDO_VDD_DS_SHIFT           (4U)
/*! SYSLDO_VDD_DS - LDO_SYS VDD Drive Strength
 *  0b0..LDO_SYS VDD regulator Drive Strength set to Low
 *  0b1..LDO_SYS VDD Regulator Drive Strength set to Normal.
 */
#define SPC_LP_CFG_SYSLDO_VDD_DS(x)              (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_SYSLDO_VDD_DS_SHIFT)) & SPC_LP_CFG_SYSLDO_VDD_DS_MASK)

#define SPC_LP_CFG_DCDC_VDD_DS_MASK              (0x300U)
#define SPC_LP_CFG_DCDC_VDD_DS_SHIFT             (8U)
/*! DCDC_VDD_DS - DCDC VDD Drive Strength
 *  0b00..DCDC VDD regulator Drive Strength set to Pulse Refresh Mode.
 *  0b01..DCDC VDD Regulator Drive Strength set to Low
 *  0b10..DCDC VDD Regulator Drive Strength set to Normal
 *  0b11..Reserved
 */
#define SPC_LP_CFG_DCDC_VDD_DS(x)                (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_DCDC_VDD_DS_SHIFT)) & SPC_LP_CFG_DCDC_VDD_DS_MASK)

#define SPC_LP_CFG_DCDC_VDD_LVL_MASK             (0xC00U)
#define SPC_LP_CFG_DCDC_VDD_LVL_SHIFT            (10U)
/*! DCDC_VDD_LVL - DCDC VDD Regulator Voltage Level
 *  0b00..Regulate to Low Under Voltage (1.25 V)
 *  0b01..Regulate to Mid Voltage (1.35 V)
 *  0b10..Regulate to Normal Voltage (2.5 V)
 *  0b11..Regulate to Safe-Mode Voltage (1.8 V)
 */
#define SPC_LP_CFG_DCDC_VDD_LVL(x)               (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_DCDC_VDD_LVL_SHIFT)) & SPC_LP_CFG_DCDC_VDD_LVL_MASK)

#define SPC_LP_CFG_GLITCH_DETECT_DISABLE_MASK    (0x1000U)
#define SPC_LP_CFG_GLITCH_DETECT_DISABLE_SHIFT   (12U)
/*! GLITCH_DETECT_DISABLE - VDD Core Glitch Detect Disable
 *  0b0..VDD Core Low Voltage Glitch Detect enabled
 *  0b1..VDD Core Low Voltage Glitch Detect disabled
 */
#define SPC_LP_CFG_GLITCH_DETECT_DISABLE(x)      (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_GLITCH_DETECT_DISABLE_SHIFT)) & SPC_LP_CFG_GLITCH_DETECT_DISABLE_MASK)

#define SPC_LP_CFG_COREVDD_IVS_EN_MASK           (0x20000U)
#define SPC_LP_CFG_COREVDD_IVS_EN_SHIFT          (17U)
/*! COREVDD_IVS_EN - CORE VDD Internal Voltage Scaling (IVS) Enable
 *  0b0..CORE VDD IVS Regulator Disabled.
 *  0b1..CORE VDD IVS Regulator Enabled. IVS automatically gets disabled in SLEEP and DPDOWN low power modes
 */
#define SPC_LP_CFG_COREVDD_IVS_EN(x)             (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_COREVDD_IVS_EN_SHIFT)) & SPC_LP_CFG_COREVDD_IVS_EN_MASK)

#define SPC_LP_CFG_LPBUFF_EN_MASK                (0x40000U)
#define SPC_LP_CFG_LPBUFF_EN_SHIFT               (18U)
/*! LPBUFF_EN - CMP Bandgap Buffer Enable
 *  0b0..Buffer Stored Reference voltage to CMP is disabled.
 *  0b1..Buffer Stored Reference voltage to CMP is enabled.
 */
#define SPC_LP_CFG_LPBUFF_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_LPBUFF_EN_SHIFT)) & SPC_LP_CFG_LPBUFF_EN_MASK)

#define SPC_LP_CFG_BGMODE_MASK                   (0x300000U)
#define SPC_LP_CFG_BGMODE_SHIFT                  (20U)
/*! BGMODE - Bandgap Mode
 *  0b00..Bandgap Disabled
 *  0b01..Bandgap Enabled with Buffer Disabled
 *  0b10..Bandgap Enabled with Buffer Enabled
 *  0b11..Reserved
 */
#define SPC_LP_CFG_BGMODE(x)                     (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_BGMODE_SHIFT)) & SPC_LP_CFG_BGMODE_MASK)

#define SPC_LP_CFG_LP_IREFEN_MASK                (0x800000U)
#define SPC_LP_CFG_LP_IREFEN_SHIFT               (23U)
/*! LP_IREFEN - Low Power IREF Enable
 *  0b0..Low Power IREF is disabled for power saving in Deep Power Down mode
 *  0b1..Low Power IREF is enabled
 */
#define SPC_LP_CFG_LP_IREFEN(x)                  (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_LP_IREFEN_SHIFT)) & SPC_LP_CFG_LP_IREFEN_MASK)

#define SPC_LP_CFG_CORE_LVDE_MASK                (0x1000000U)
#define SPC_LP_CFG_CORE_LVDE_SHIFT               (24U)
/*! CORE_LVDE - Core Low Voltage Detect Enable
 *  0b0..Core Low Voltage Detect disabled
 *  0b1..Core Low Voltage Detect enabled. BGMODE must be programmed so that Bandgap is enabled Enabling Bandgap to
 *       support voltage detect will increase the low power mode Idd.
 */
#define SPC_LP_CFG_CORE_LVDE(x)                  (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_CORE_LVDE_SHIFT)) & SPC_LP_CFG_CORE_LVDE_MASK)

#define SPC_LP_CFG_SYS_LVDE_MASK                 (0x2000000U)
#define SPC_LP_CFG_SYS_LVDE_SHIFT                (25U)
/*! SYS_LVDE - System Low Voltage Detect Enable
 *  0b0..System Low Voltage Detect disabled
 *  0b1..System Low Voltage Detect enabled. BGMODE must be programmed so that Bandgap is enabled Enabling Bandgap
 *       to support voltage detect will increase the low power mode Idd.
 */
#define SPC_LP_CFG_SYS_LVDE(x)                   (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_SYS_LVDE_SHIFT)) & SPC_LP_CFG_SYS_LVDE_MASK)

#define SPC_LP_CFG_IO_LVDE_MASK                  (0x4000000U)
#define SPC_LP_CFG_IO_LVDE_SHIFT                 (26U)
/*! IO_LVDE - IO Low Voltage Detect Enable
 *  0b0..IO Low Voltage Detect disabled
 *  0b1..IO Low Voltage Detect enabled. BGMODE must be programmed so that Bandgap is enabled Enabling Bandgap to
 *       support voltage detect will increase the low power mode Idd.
 */
#define SPC_LP_CFG_IO_LVDE(x)                    (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_IO_LVDE_SHIFT)) & SPC_LP_CFG_IO_LVDE_MASK)

#define SPC_LP_CFG_CORE_HVDE_MASK                (0x8000000U)
#define SPC_LP_CFG_CORE_HVDE_SHIFT               (27U)
/*! CORE_HVDE - Core High Voltage Detect Enable
 *  0b0..Core High Voltage Detect disabled
 *  0b1..Core High Voltage Detect enabled. BGMODE must be programmed so that Bandgap is enabled Enabling Bandgap
 *       to support voltage detect will increase the low power mode Idd.
 */
#define SPC_LP_CFG_CORE_HVDE(x)                  (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_CORE_HVDE_SHIFT)) & SPC_LP_CFG_CORE_HVDE_MASK)

#define SPC_LP_CFG_SYS_HVDE_MASK                 (0x10000000U)
#define SPC_LP_CFG_SYS_HVDE_SHIFT                (28U)
/*! SYS_HVDE - System High Voltage Detect Enable
 *  0b0..System High Voltage Detect disabled
 *  0b1..System High Voltage Detect enabled. BGMODE must be programmed so that Bandgap is enabled Enabling Bandgap
 *       to support voltage detect will increase the low power mode Idd.
 */
#define SPC_LP_CFG_SYS_HVDE(x)                   (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_SYS_HVDE_SHIFT)) & SPC_LP_CFG_SYS_HVDE_MASK)

#define SPC_LP_CFG_IO_HVDE_MASK                  (0x20000000U)
#define SPC_LP_CFG_IO_HVDE_SHIFT                 (29U)
/*! IO_HVDE - IO High Voltage Detect Enable
 *  0b0..IO High Voltage Detect disabled
 *  0b1..IO High Voltage Detect enabled. BGMODE must be programmed so that Bandgap is enabled. Enabling Bandgap to
 *       support voltage detect will increase the low power mode Idd.
 */
#define SPC_LP_CFG_IO_HVDE(x)                    (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_IO_HVDE_SHIFT)) & SPC_LP_CFG_IO_HVDE_MASK)
/*! @} */

/*! @name LPWKUP_DELAY - Low Power Wake Up Delay Register */
/*! @{ */

#define SPC_LPWKUP_DELAY_LPWKUP_DELAY_MASK       (0xFFFFU)
#define SPC_LPWKUP_DELAY_LPWKUP_DELAY_SHIFT      (0U)
/*! LPWKUP_DELAY - Low Power Wake Up Delay
 */
#define SPC_LPWKUP_DELAY_LPWKUP_DELAY(x)         (((uint32_t)(((uint32_t)(x)) << SPC_LPWKUP_DELAY_LPWKUP_DELAY_SHIFT)) & SPC_LPWKUP_DELAY_LPWKUP_DELAY_MASK)
/*! @} */

/*! @name ACTIVE_VDELAY - Active Voltage Trim Delay Register */
/*! @{ */

#define SPC_ACTIVE_VDELAY_ACTIVE_VDELAY_MASK     (0xFFFFU)
#define SPC_ACTIVE_VDELAY_ACTIVE_VDELAY_SHIFT    (0U)
/*! ACTIVE_VDELAY - Active Voltage Delay
 */
#define SPC_ACTIVE_VDELAY_ACTIVE_VDELAY(x)       (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_VDELAY_ACTIVE_VDELAY_SHIFT)) & SPC_ACTIVE_VDELAY_ACTIVE_VDELAY_MASK)
/*! @} */

/*! @name VD_STAT - Voltage Detect Status Register */
/*! @{ */

#define SPC_VD_STAT_COREVDD_LVDF_MASK            (0x1U)
#define SPC_VD_STAT_COREVDD_LVDF_SHIFT           (0U)
/*! COREVDD_LVDF - Core VDD Low-Voltage Detect Flag
 *  0b0..Low-voltage event not detected
 *  0b1..Low-voltage event detected
 */
#define SPC_VD_STAT_COREVDD_LVDF(x)              (((uint32_t)(((uint32_t)(x)) << SPC_VD_STAT_COREVDD_LVDF_SHIFT)) & SPC_VD_STAT_COREVDD_LVDF_MASK)

#define SPC_VD_STAT_SYSVDD_LVDF_MASK             (0x2U)
#define SPC_VD_STAT_SYSVDD_LVDF_SHIFT            (1U)
/*! SYSVDD_LVDF - System VDD Low-Voltage Detect Flag
 *  0b0..Low-voltage event not detected
 *  0b1..Low-voltage event detected
 */
#define SPC_VD_STAT_SYSVDD_LVDF(x)               (((uint32_t)(((uint32_t)(x)) << SPC_VD_STAT_SYSVDD_LVDF_SHIFT)) & SPC_VD_STAT_SYSVDD_LVDF_MASK)

#define SPC_VD_STAT_IOVDD_LVDF_MASK              (0x4U)
#define SPC_VD_STAT_IOVDD_LVDF_SHIFT             (2U)
/*! IOVDD_LVDF - IO VDD Low-Voltage Detect Flag
 *  0b0..Low-voltage event not detected
 *  0b1..Low-voltage event detected
 */
#define SPC_VD_STAT_IOVDD_LVDF(x)                (((uint32_t)(((uint32_t)(x)) << SPC_VD_STAT_IOVDD_LVDF_SHIFT)) & SPC_VD_STAT_IOVDD_LVDF_MASK)

#define SPC_VD_STAT_COREVDD_HVDF_MASK            (0x10U)
#define SPC_VD_STAT_COREVDD_HVDF_SHIFT           (4U)
/*! COREVDD_HVDF - Core VDD High-Voltage Detect Flag
 *  0b0..High-voltage event not detected
 *  0b1..High-voltage event detected
 */
#define SPC_VD_STAT_COREVDD_HVDF(x)              (((uint32_t)(((uint32_t)(x)) << SPC_VD_STAT_COREVDD_HVDF_SHIFT)) & SPC_VD_STAT_COREVDD_HVDF_MASK)

#define SPC_VD_STAT_SYSVDD_HVDF_MASK             (0x20U)
#define SPC_VD_STAT_SYSVDD_HVDF_SHIFT            (5U)
/*! SYSVDD_HVDF - System VDD High-Voltage Detect Flag
 *  0b0..High-voltage event not detected
 *  0b1..High-voltage event detected
 */
#define SPC_VD_STAT_SYSVDD_HVDF(x)               (((uint32_t)(((uint32_t)(x)) << SPC_VD_STAT_SYSVDD_HVDF_SHIFT)) & SPC_VD_STAT_SYSVDD_HVDF_MASK)

#define SPC_VD_STAT_IOVDD_HVDF_MASK              (0x40U)
#define SPC_VD_STAT_IOVDD_HVDF_SHIFT             (6U)
/*! IOVDD_HVDF - IO VDD High-Voltage Detect Flag
 *  0b0..High-voltage event not detected
 *  0b1..High-voltage event detected
 */
#define SPC_VD_STAT_IOVDD_HVDF(x)                (((uint32_t)(((uint32_t)(x)) << SPC_VD_STAT_IOVDD_HVDF_SHIFT)) & SPC_VD_STAT_IOVDD_HVDF_MASK)
/*! @} */

/*! @name VD_CORE_CFG - Core Voltage Detect Configuration Register */
/*! @{ */

#define SPC_VD_CORE_CFG_LVDRE_MASK               (0x1U)
#define SPC_VD_CORE_CFG_LVDRE_SHIFT              (0U)
/*! LVDRE - Core VDD Low-Voltage Detect Reset Enable
 *  0b0..COREVDD_LVDF does not generate hardware reset
 *  0b1..COREVDD_LVDF does generate hardware reset
 */
#define SPC_VD_CORE_CFG_LVDRE(x)                 (((uint32_t)(((uint32_t)(x)) << SPC_VD_CORE_CFG_LVDRE_SHIFT)) & SPC_VD_CORE_CFG_LVDRE_MASK)

#define SPC_VD_CORE_CFG_LVDIE_MASK               (0x2U)
#define SPC_VD_CORE_CFG_LVDIE_SHIFT              (1U)
/*! LVDIE - Core VDD Low-Voltage Detect Interrupt Enable
 *  0b0..COREVDD_LVDF does not generate hardware interrupt (user polling)
 *  0b1..COREVDD_LVDF does generate hardware interrupt
 */
#define SPC_VD_CORE_CFG_LVDIE(x)                 (((uint32_t)(((uint32_t)(x)) << SPC_VD_CORE_CFG_LVDIE_SHIFT)) & SPC_VD_CORE_CFG_LVDIE_MASK)

#define SPC_VD_CORE_CFG_HVDRE_MASK               (0x4U)
#define SPC_VD_CORE_CFG_HVDRE_SHIFT              (2U)
/*! HVDRE - Core VDD High-Voltage Detect Reset Enable
 *  0b0..COREVDD_HVDF does not generate hardware reset
 *  0b1..COREVDD_HVDF does generate hardware reset
 */
#define SPC_VD_CORE_CFG_HVDRE(x)                 (((uint32_t)(((uint32_t)(x)) << SPC_VD_CORE_CFG_HVDRE_SHIFT)) & SPC_VD_CORE_CFG_HVDRE_MASK)

#define SPC_VD_CORE_CFG_HVDIE_MASK               (0x8U)
#define SPC_VD_CORE_CFG_HVDIE_SHIFT              (3U)
/*! HVDIE - Core VDD High-Voltage Detect Interrupt Enable
 *  0b0..COREVDD_HVDF does not generate hardware interrupt (user polling)
 *  0b1..COREVDD_HVDF does generate hardware interrupt
 */
#define SPC_VD_CORE_CFG_HVDIE(x)                 (((uint32_t)(((uint32_t)(x)) << SPC_VD_CORE_CFG_HVDIE_SHIFT)) & SPC_VD_CORE_CFG_HVDIE_MASK)

#define SPC_VD_CORE_CFG_LOCK_MASK                (0x10000U)
#define SPC_VD_CORE_CFG_LOCK_SHIFT               (16U)
/*! LOCK - CORE Voltage Detect Reset Enable Lock Bit
 *  0b0..Writes to VD_CORE_CGF[LVDRE] and VD_CORE_CFG[HVDRE] are allowed.
 *  0b1..Writes to VD_CORE_CGF[LVDRE] and VD_CORE_CFG[HVDRE] are ignored.
 */
#define SPC_VD_CORE_CFG_LOCK(x)                  (((uint32_t)(((uint32_t)(x)) << SPC_VD_CORE_CFG_LOCK_SHIFT)) & SPC_VD_CORE_CFG_LOCK_MASK)
/*! @} */

/*! @name VD_SYS_CFG - System Voltage Detect Configuration Register */
/*! @{ */

#define SPC_VD_SYS_CFG_LVDRE_MASK                (0x1U)
#define SPC_VD_SYS_CFG_LVDRE_SHIFT               (0U)
/*! LVDRE - System VDD Low-Voltage Detect Reset Enable
 *  0b0..SYSVDD_LVDF does not generate hardware reset
 *  0b1..SYSVDD_LVDF does generate hardware reset
 */
#define SPC_VD_SYS_CFG_LVDRE(x)                  (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_LVDRE_SHIFT)) & SPC_VD_SYS_CFG_LVDRE_MASK)

#define SPC_VD_SYS_CFG_LVDIE_MASK                (0x2U)
#define SPC_VD_SYS_CFG_LVDIE_SHIFT               (1U)
/*! LVDIE - System VDD Low-Voltage Detect Interrupt Enable
 *  0b0..SYSVDD_LVDF does not generate hardware interrupt (user polling)
 *  0b1..SYSVDD_LVDF does generate hardware interrupt
 */
#define SPC_VD_SYS_CFG_LVDIE(x)                  (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_LVDIE_SHIFT)) & SPC_VD_SYS_CFG_LVDIE_MASK)

#define SPC_VD_SYS_CFG_HVDRE_MASK                (0x4U)
#define SPC_VD_SYS_CFG_HVDRE_SHIFT               (2U)
/*! HVDRE - System VDD High-Voltage Detect Reset Enable
 *  0b0..SYSVDD_HVDF does not generate hardware reset
 *  0b1..SYSVDD_HVDF does generate hardware reset
 */
#define SPC_VD_SYS_CFG_HVDRE(x)                  (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_HVDRE_SHIFT)) & SPC_VD_SYS_CFG_HVDRE_MASK)

#define SPC_VD_SYS_CFG_HVDIE_MASK                (0x8U)
#define SPC_VD_SYS_CFG_HVDIE_SHIFT               (3U)
/*! HVDIE - System VDD High-Voltage Detect Interrupt Enable
 *  0b0..SYSVDD_HVDF does not generate hardware interrupt (user polling)
 *  0b1..SYSVDD_HVDF does generate hardware interrupt
 */
#define SPC_VD_SYS_CFG_HVDIE(x)                  (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_HVDIE_SHIFT)) & SPC_VD_SYS_CFG_HVDIE_MASK)

#define SPC_VD_SYS_CFG_LVSEL_MASK                (0x100U)
#define SPC_VD_SYS_CFG_LVSEL_SHIFT               (8U)
/*! LVSEL - System VDD Low-Voltage Level Select
 *  0b0..Trip point set to Normal level (See the device data sheet for the normal level value)
 *  0b1..Trip point set to Safe level (See the device data sheet for the safe level value)
 */
#define SPC_VD_SYS_CFG_LVSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_LVSEL_SHIFT)) & SPC_VD_SYS_CFG_LVSEL_MASK)

#define SPC_VD_SYS_CFG_LOCK_MASK                 (0x10000U)
#define SPC_VD_SYS_CFG_LOCK_SHIFT                (16U)
/*! LOCK - System Voltage Detect Reset Enable Lock Bit
 *  0b0..Writes to VD_SYS_CFG[LVDRE, HVDRE, LVSEL] are allowed.
 *  0b1..Writes to VD_SYS_CFG[LVDRE, HVDRE, LVSEL] are ignored.
 */
#define SPC_VD_SYS_CFG_LOCK(x)                   (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_LOCK_SHIFT)) & SPC_VD_SYS_CFG_LOCK_MASK)
/*! @} */

/*! @name VD_IO_CFG - IO Voltage Detect Configuration Register */
/*! @{ */

#define SPC_VD_IO_CFG_LVDRE_MASK                 (0x1U)
#define SPC_VD_IO_CFG_LVDRE_SHIFT                (0U)
/*! LVDRE - IO VDD Low-Voltage Detect Reset Enable
 *  0b0..IOVDD_LVDF does not generate hardware reset
 *  0b1..IOVDD_LVDF does generate hardware reset
 */
#define SPC_VD_IO_CFG_LVDRE(x)                   (((uint32_t)(((uint32_t)(x)) << SPC_VD_IO_CFG_LVDRE_SHIFT)) & SPC_VD_IO_CFG_LVDRE_MASK)

#define SPC_VD_IO_CFG_LVDIE_MASK                 (0x2U)
#define SPC_VD_IO_CFG_LVDIE_SHIFT                (1U)
/*! LVDIE - IO VDD Low-Voltage Detect Interrupt Enable
 *  0b0..IOVDD_LVDF does not generate hardware interrupt (user polling)
 *  0b1..IOVDD_LVDF does generate hardware interrupt
 */
#define SPC_VD_IO_CFG_LVDIE(x)                   (((uint32_t)(((uint32_t)(x)) << SPC_VD_IO_CFG_LVDIE_SHIFT)) & SPC_VD_IO_CFG_LVDIE_MASK)

#define SPC_VD_IO_CFG_HVDRE_MASK                 (0x4U)
#define SPC_VD_IO_CFG_HVDRE_SHIFT                (2U)
/*! HVDRE - IO VDD High-Voltage Detect Reset Enable
 *  0b0..IOVDD_HVDF does not generate hardware reset
 *  0b1..IOVDD_HVDF does generate hardware reset
 */
#define SPC_VD_IO_CFG_HVDRE(x)                   (((uint32_t)(((uint32_t)(x)) << SPC_VD_IO_CFG_HVDRE_SHIFT)) & SPC_VD_IO_CFG_HVDRE_MASK)

#define SPC_VD_IO_CFG_HVDIE_MASK                 (0x8U)
#define SPC_VD_IO_CFG_HVDIE_SHIFT                (3U)
/*! HVDIE - IO VDD High-Voltage Detect Interrupt Enable
 *  0b0..IOVDD_HVDF does not generate hardware interrupt (user polling)
 *  0b1..IOVDD_HVDF does generate hardware interrupt
 */
#define SPC_VD_IO_CFG_HVDIE(x)                   (((uint32_t)(((uint32_t)(x)) << SPC_VD_IO_CFG_HVDIE_SHIFT)) & SPC_VD_IO_CFG_HVDIE_MASK)

#define SPC_VD_IO_CFG_LVSEL_MASK                 (0x100U)
#define SPC_VD_IO_CFG_LVSEL_SHIFT                (8U)
/*! LVSEL - IO VDD Low-Voltage Level Select
 *  0b0..Trip point set to Normal (See the device data sheet for the normal level value)
 *  0b1..Trip point set to Safe (See the device data sheet for the safe level value)
 */
#define SPC_VD_IO_CFG_LVSEL(x)                   (((uint32_t)(((uint32_t)(x)) << SPC_VD_IO_CFG_LVSEL_SHIFT)) & SPC_VD_IO_CFG_LVSEL_MASK)

#define SPC_VD_IO_CFG_LOCK_MASK                  (0x10000U)
#define SPC_VD_IO_CFG_LOCK_SHIFT                 (16U)
/*! LOCK - IO Voltage Detect Reset Enable Lock Bit
 *  0b0..Writes to VD_IO_CFG[LVDRE, HVDRE, HVSEL, LVSEL] are allowed.
 *  0b1..Writes to VD_IO_CFG[LVDRE, HVDRE, HVSEL, LVSEL] are ignored.
 */
#define SPC_VD_IO_CFG_LOCK(x)                    (((uint32_t)(((uint32_t)(x)) << SPC_VD_IO_CFG_LOCK_SHIFT)) & SPC_VD_IO_CFG_LOCK_MASK)
/*! @} */

/*! @name EVD_CFG - External Voltage Domain Configuration Register */
/*! @{ */

#define SPC_EVD_CFG_EVDISO_MASK                  (0x7U)
#define SPC_EVD_CFG_EVDISO_SHIFT                 (0U)
/*! EVDISO - External Voltage Domain Isolation
 */
#define SPC_EVD_CFG_EVDISO(x)                    (((uint32_t)(((uint32_t)(x)) << SPC_EVD_CFG_EVDISO_SHIFT)) & SPC_EVD_CFG_EVDISO_MASK)

#define SPC_EVD_CFG_EVDLPISO_MASK                (0x700U)
#define SPC_EVD_CFG_EVDLPISO_SHIFT               (8U)
/*! EVDLPISO - External Voltage Domain Low Power Isolation
 */
#define SPC_EVD_CFG_EVDLPISO(x)                  (((uint32_t)(((uint32_t)(x)) << SPC_EVD_CFG_EVDLPISO_SHIFT)) & SPC_EVD_CFG_EVDLPISO_MASK)

#define SPC_EVD_CFG_EVDSTAT_MASK                 (0x70000U)
#define SPC_EVD_CFG_EVDSTAT_SHIFT                (16U)
/*! EVDSTAT - External Voltage Domain Status
 */
#define SPC_EVD_CFG_EVDSTAT(x)                   (((uint32_t)(((uint32_t)(x)) << SPC_EVD_CFG_EVDSTAT_SHIFT)) & SPC_EVD_CFG_EVDSTAT_MASK)
/*! @} */

/*! @name VDD_CORE_GLITCH_DETECT_SC - VDD Core Glitch Detect Status Control Register */
/*! @{ */

#define SPC_VDD_CORE_GLITCH_DETECT_SC_CNT_SELECT_MASK (0x3U)
#define SPC_VDD_CORE_GLITCH_DETECT_SC_CNT_SELECT_SHIFT (0U)
/*! CNT_SELECT - CNT_SELECT
 *  0b00..Select bit-0 of 4-bit Ripple Counter to detect glitch on VDD Core
 *  0b01..Select bit-1 of 4-bit Ripple Counter to detect glitch on VDD Core
 *  0b10..Select bit-2 of 4-bit Ripple Counter to detect glitch on VDD Core
 *  0b11..Select bit-3 of 4-bit Ripple Counter to detect glitch on VDD Core
 */
#define SPC_VDD_CORE_GLITCH_DETECT_SC_CNT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << SPC_VDD_CORE_GLITCH_DETECT_SC_CNT_SELECT_SHIFT)) & SPC_VDD_CORE_GLITCH_DETECT_SC_CNT_SELECT_MASK)

#define SPC_VDD_CORE_GLITCH_DETECT_SC_TIMEOUT_MASK (0x3CU)
#define SPC_VDD_CORE_GLITCH_DETECT_SC_TIMEOUT_SHIFT (2U)
/*! TIMEOUT - TIMEOUT
 */
#define SPC_VDD_CORE_GLITCH_DETECT_SC_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SPC_VDD_CORE_GLITCH_DETECT_SC_TIMEOUT_SHIFT)) & SPC_VDD_CORE_GLITCH_DETECT_SC_TIMEOUT_MASK)

#define SPC_VDD_CORE_GLITCH_DETECT_SC_RE_MASK    (0x40U)
#define SPC_VDD_CORE_GLITCH_DETECT_SC_RE_SHIFT   (6U)
/*! RE - Core VDD Glitch Detect Reset Enable
 *  0b0..GLITCH_DETECT_FLAG[CNT_SELECT] does not generate POR/LVD reset
 *  0b1..GLITCH_DETECT_FLAG[CNT_SELECT] does generate POR/LVD reset
 */
#define SPC_VDD_CORE_GLITCH_DETECT_SC_RE(x)      (((uint32_t)(((uint32_t)(x)) << SPC_VDD_CORE_GLITCH_DETECT_SC_RE_SHIFT)) & SPC_VDD_CORE_GLITCH_DETECT_SC_RE_MASK)

#define SPC_VDD_CORE_GLITCH_DETECT_SC_IE_MASK    (0x80U)
#define SPC_VDD_CORE_GLITCH_DETECT_SC_IE_SHIFT   (7U)
/*! IE - Core VDD Glitch Detect Interrupt Enable
 *  0b0..GLITCH_DETECT_FLAG[CNT_SELECT] does not generate hardware interrupt (user polling)
 *  0b1..GLITCH_DETECT_FLAG[CNT_SELECT] does generate hardware interrupt
 */
#define SPC_VDD_CORE_GLITCH_DETECT_SC_IE(x)      (((uint32_t)(((uint32_t)(x)) << SPC_VDD_CORE_GLITCH_DETECT_SC_IE_SHIFT)) & SPC_VDD_CORE_GLITCH_DETECT_SC_IE_MASK)

#define SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_MASK (0xF00U)
#define SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_SHIFT (8U)
/*! GLITCH_DETECT_FLAG - GLITCH_DETECT_FLAG
 */
#define SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_SHIFT)) & SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_MASK)

#define SPC_VDD_CORE_GLITCH_DETECT_SC_LOCK_MASK  (0x10000U)
#define SPC_VDD_CORE_GLITCH_DETECT_SC_LOCK_SHIFT (16U)
/*! LOCK - VDD Core Voltage Glitch Detect Reset Enable Lock Bit
 *  0b0..Writes to RE are allowed.
 *  0b1..Writes to RE are ignored.
 */
#define SPC_VDD_CORE_GLITCH_DETECT_SC_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << SPC_VDD_CORE_GLITCH_DETECT_SC_LOCK_SHIFT)) & SPC_VDD_CORE_GLITCH_DETECT_SC_LOCK_MASK)
/*! @} */

/*! @name CORELDO_CFG - LDO_CORE Configuration Register */
/*! @{ */

#define SPC_CORELDO_CFG_PASSTHROUGH_MASK         (0x100U)
#define SPC_CORELDO_CFG_PASSTHROUGH_SHIFT        (8U)
/*! PASSTHROUGH - LDO_CORE Pass Through Enable
 */
#define SPC_CORELDO_CFG_PASSTHROUGH(x)           (((uint32_t)(((uint32_t)(x)) << SPC_CORELDO_CFG_PASSTHROUGH_SHIFT)) & SPC_CORELDO_CFG_PASSTHROUGH_MASK)

#define SPC_CORELDO_CFG_DPDOWN_PULLDOWN_DISABLE_MASK (0x10000U)
#define SPC_CORELDO_CFG_DPDOWN_PULLDOWN_DISABLE_SHIFT (16U)
/*! DPDOWN_PULLDOWN_DISABLE - LDO_CORE Deep Power Down Pulldown Disable
 *  0b0..LDO_CORE pulldown in Deep Power Down not disabled
 *  0b1..LDO_CORE pulldown in Deep Power Down disabled
 */
#define SPC_CORELDO_CFG_DPDOWN_PULLDOWN_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SPC_CORELDO_CFG_DPDOWN_PULLDOWN_DISABLE_SHIFT)) & SPC_CORELDO_CFG_DPDOWN_PULLDOWN_DISABLE_MASK)
/*! @} */

/*! @name SYSLDO_CFG - LDO_SYS Configuration Register */
/*! @{ */

#define SPC_SYSLDO_CFG_ISINKEN_MASK              (0x1U)
#define SPC_SYSLDO_CFG_ISINKEN_SHIFT             (0U)
/*! ISINKEN - Current Sink Enable
 *  0b0..Disable current sink feature of System low power regulator.
 *  0b1..Enable current sink feature of System low power regulator.
 */
#define SPC_SYSLDO_CFG_ISINKEN(x)                (((uint32_t)(((uint32_t)(x)) << SPC_SYSLDO_CFG_ISINKEN_SHIFT)) & SPC_SYSLDO_CFG_ISINKEN_MASK)
/*! @} */

/*! @name SYSLDO_FPTRIM - LDO_SYS Regulator Full Power Trim Register */
/*! @{ */

#define SPC_SYSLDO_FPTRIM_TRIM1P8_MASK           (0x7FU)
#define SPC_SYSLDO_FPTRIM_TRIM1P8_SHIFT          (0U)
/*! TRIM1P8 - LDO_SYS 1.8V trim value
 */
#define SPC_SYSLDO_FPTRIM_TRIM1P8(x)             (((uint32_t)(((uint32_t)(x)) << SPC_SYSLDO_FPTRIM_TRIM1P8_SHIFT)) & SPC_SYSLDO_FPTRIM_TRIM1P8_MASK)

#define SPC_SYSLDO_FPTRIM_TRIM2P5_MASK           (0x7F00U)
#define SPC_SYSLDO_FPTRIM_TRIM2P5_SHIFT          (8U)
/*! TRIM2P5 - LDO_SYS 2.5V trim value
 */
#define SPC_SYSLDO_FPTRIM_TRIM2P5(x)             (((uint32_t)(((uint32_t)(x)) << SPC_SYSLDO_FPTRIM_TRIM2P5_SHIFT)) & SPC_SYSLDO_FPTRIM_TRIM2P5_MASK)
/*! @} */

/*! @name DCDC_CFG - DCDC Configuration Register */
/*! @{ */

#define SPC_DCDC_CFG_FREQ_CNTRL_ON_MASK          (0x1U)
#define SPC_DCDC_CFG_FREQ_CNTRL_ON_SHIFT         (0U)
/*! FREQ_CNTRL_ON - DCDC Burst Frequency Control Enable
 */
#define SPC_DCDC_CFG_FREQ_CNTRL_ON(x)            (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_CFG_FREQ_CNTRL_ON_SHIFT)) & SPC_DCDC_CFG_FREQ_CNTRL_ON_MASK)

#define SPC_DCDC_CFG_FREQ_CNTRL_MASK             (0x3F00U)
#define SPC_DCDC_CFG_FREQ_CNTRL_SHIFT            (8U)
/*! FREQ_CNTRL - DCDC Burst Frequency Control Register
 */
#define SPC_DCDC_CFG_FREQ_CNTRL(x)               (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_CFG_FREQ_CNTRL_SHIFT)) & SPC_DCDC_CFG_FREQ_CNTRL_MASK)

#define SPC_DCDC_CFG_VOUT2P5_SEL_MASK            (0x40000U)
#define SPC_DCDC_CFG_VOUT2P5_SEL_SHIFT           (18U)
/*! VOUT2P5_SEL - VOUT2P5_SEL
 *  0b0..DCDC Vout set by DCDC_VDD_LVL register
 *  0b1..DCDC Vout set to 2p5V.
 */
#define SPC_DCDC_CFG_VOUT2P5_SEL(x)              (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_CFG_VOUT2P5_SEL_SHIFT)) & SPC_DCDC_CFG_VOUT2P5_SEL_MASK)
/*! @} */

/*! @name DCDC_BURST_CFG - DCDC BURST Configuration Register */
/*! @{ */

#define SPC_DCDC_BURST_CFG_BURST_REQ_MASK        (0x1U)
#define SPC_DCDC_BURST_CFG_BURST_REQ_SHIFT       (0U)
/*! BURST_REQ - Software Burst Request Register
 *  0b0..No burst request generated
 *  0b1..Burst request generated
 */
#define SPC_DCDC_BURST_CFG_BURST_REQ(x)          (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_BURST_CFG_BURST_REQ_SHIFT)) & SPC_DCDC_BURST_CFG_BURST_REQ_MASK)

#define SPC_DCDC_BURST_CFG_EXT_BURST_EN_MASK     (0x2U)
#define SPC_DCDC_BURST_CFG_EXT_BURST_EN_SHIFT    (1U)
/*! EXT_BURST_EN - DCDC External Burst Request Enable Register
 *  0b0..External Burst Request are not enabled
 *  0b1..External Burst Request are enabled
 */
#define SPC_DCDC_BURST_CFG_EXT_BURST_EN(x)       (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_BURST_CFG_EXT_BURST_EN_SHIFT)) & SPC_DCDC_BURST_CFG_EXT_BURST_EN_MASK)

#define SPC_DCDC_BURST_CFG_BURST_ACK_MASK        (0x8U)
#define SPC_DCDC_BURST_CFG_BURST_ACK_SHIFT       (3U)
/*! BURST_ACK - DCDC Burst Acknowledge Flag
 *  0b0..DCDC Burst request has not acknowledged.
 *  0b1..DCDC Burst request has completed and acknowledged.
 */
#define SPC_DCDC_BURST_CFG_BURST_ACK(x)          (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_BURST_CFG_BURST_ACK_SHIFT)) & SPC_DCDC_BURST_CFG_BURST_ACK_MASK)

#define SPC_DCDC_BURST_CFG_PULSE_REFRESH_CNT_MASK (0xFFFF0000U)
#define SPC_DCDC_BURST_CFG_PULSE_REFRESH_CNT_SHIFT (16U)
/*! PULSE_REFRESH_CNT - DCDC 16-bit refresh count value
 */
#define SPC_DCDC_BURST_CFG_PULSE_REFRESH_CNT(x)  (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_BURST_CFG_PULSE_REFRESH_CNT_SHIFT)) & SPC_DCDC_BURST_CFG_PULSE_REFRESH_CNT_MASK)
/*! @} */

/*! @name DCDC_VTRIM - DCDC Voltage Trim Register */
/*! @{ */

#define SPC_DCDC_VTRIM_LVL00_MASK                (0xFFU)
#define SPC_DCDC_VTRIM_LVL00_SHIFT               (0U)
/*! LVL00 - DCDC 1.25V Trim Value
 */
#define SPC_DCDC_VTRIM_LVL00(x)                  (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_VTRIM_LVL00_SHIFT)) & SPC_DCDC_VTRIM_LVL00_MASK)

#define SPC_DCDC_VTRIM_LVL01_MASK                (0xFF00U)
#define SPC_DCDC_VTRIM_LVL01_SHIFT               (8U)
/*! LVL01 - DCDC 1.35V Trim Value
 */
#define SPC_DCDC_VTRIM_LVL01(x)                  (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_VTRIM_LVL01_SHIFT)) & SPC_DCDC_VTRIM_LVL01_MASK)

#define SPC_DCDC_VTRIM_LVL10_MASK                (0xFF0000U)
#define SPC_DCDC_VTRIM_LVL10_SHIFT               (16U)
/*! LVL10 - DCDC 1.5V Trim Value
 */
#define SPC_DCDC_VTRIM_LVL10(x)                  (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_VTRIM_LVL10_SHIFT)) & SPC_DCDC_VTRIM_LVL10_MASK)

#define SPC_DCDC_VTRIM_LVL11_MASK                (0xFF000000U)
#define SPC_DCDC_VTRIM_LVL11_SHIFT               (24U)
/*! LVL11 - DCDC 1.8V Trim Value
 */
#define SPC_DCDC_VTRIM_LVL11(x)                  (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_VTRIM_LVL11_SHIFT)) & SPC_DCDC_VTRIM_LVL11_MASK)
/*! @} */

/*! @name DCDC_LPVTRIM - DCDC Low Power Voltage Trim Register */
/*! @{ */

#define SPC_DCDC_LPVTRIM_LP_LVL00_MASK           (0xFFU)
#define SPC_DCDC_LPVTRIM_LP_LVL00_SHIFT          (0U)
/*! LP_LVL00 - DCDC 1.25V Trim Value
 */
#define SPC_DCDC_LPVTRIM_LP_LVL00(x)             (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_LPVTRIM_LP_LVL00_SHIFT)) & SPC_DCDC_LPVTRIM_LP_LVL00_MASK)

#define SPC_DCDC_LPVTRIM_LP_LVL01_MASK           (0xFF00U)
#define SPC_DCDC_LPVTRIM_LP_LVL01_SHIFT          (8U)
/*! LP_LVL01 - DCDC 1.35V Trim Value
 */
#define SPC_DCDC_LPVTRIM_LP_LVL01(x)             (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_LPVTRIM_LP_LVL01_SHIFT)) & SPC_DCDC_LPVTRIM_LP_LVL01_MASK)

#define SPC_DCDC_LPVTRIM_LP_LVL10_MASK           (0xFF0000U)
#define SPC_DCDC_LPVTRIM_LP_LVL10_SHIFT          (16U)
/*! LP_LVL10 - DCDC 1.5V Trim Value
 */
#define SPC_DCDC_LPVTRIM_LP_LVL10(x)             (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_LPVTRIM_LP_LVL10_SHIFT)) & SPC_DCDC_LPVTRIM_LP_LVL10_MASK)

#define SPC_DCDC_LPVTRIM_LP_LVL11_MASK           (0xFF000000U)
#define SPC_DCDC_LPVTRIM_LP_LVL11_SHIFT          (24U)
/*! LP_LVL11 - DCDC 1.8V Trim Value
 */
#define SPC_DCDC_LPVTRIM_LP_LVL11(x)             (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_LPVTRIM_LP_LVL11_SHIFT)) & SPC_DCDC_LPVTRIM_LP_LVL11_MASK)
/*! @} */

/*! @name DCDC_TEST - DCDC Test Control Register */
/*! @{ */

#define SPC_DCDC_TEST_TESTEN_MASK                (0x1U)
#define SPC_DCDC_TEST_TESTEN_SHIFT               (0U)
/*! TESTEN - TESTEN
 *  0b0..Normal Mode. DCDC not selected for analog test
 *  0b1..DCDC analog test selected.
 */
#define SPC_DCDC_TEST_TESTEN(x)                  (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_TEST_TESTEN_SHIFT)) & SPC_DCDC_TEST_TESTEN_MASK)

#define SPC_DCDC_TEST_DCDC_PASSTHROUGH_MASK      (0x2U)
#define SPC_DCDC_TEST_DCDC_PASSTHROUGH_SHIFT     (1U)
/*! DCDC_PASSTHROUGH - DCDC_PASSTHROUGH
 *  0b0..DCDC not in passthrough mode.
 *  0b1..DCDC in passthrough mode
 */
#define SPC_DCDC_TEST_DCDC_PASSTHROUGH(x)        (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_TEST_DCDC_PASSTHROUGH_SHIFT)) & SPC_DCDC_TEST_DCDC_PASSTHROUGH_MASK)

#define SPC_DCDC_TEST_VOUT2P5_SEL_MASK           (0x4U)
#define SPC_DCDC_TEST_VOUT2P5_SEL_SHIFT          (2U)
/*! VOUT2P5_SEL - VOUT2P5_SEL
 *  0b0..DCDC Vout set by DCDC_VDD_LVL register
 *  0b1..DCDC Vout set to 2p5V.
 */
#define SPC_DCDC_TEST_VOUT2P5_SEL(x)             (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_TEST_VOUT2P5_SEL_SHIFT)) & SPC_DCDC_TEST_VOUT2P5_SEL_MASK)

#define SPC_DCDC_TEST_SWOFF_MASK                 (0x8U)
#define SPC_DCDC_TEST_SWOFF_SHIFT                (3U)
/*! SWOFF - SWOFF
 */
#define SPC_DCDC_TEST_SWOFF(x)                   (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_TEST_SWOFF_SHIFT)) & SPC_DCDC_TEST_SWOFF_MASK)

#define SPC_DCDC_TEST_DCDC_REFRESH_EN_MASK       (0x10U)
#define SPC_DCDC_TEST_DCDC_REFRESH_EN_SHIFT      (4U)
/*! DCDC_REFRESH_EN - DCDC_REFRESH_EN
 *  0b0..DCDC Refresh Mode disabled.
 *  0b1..DCDC Refresh Mode enabled. DCDC_REFRESH_EN must be set to 1 before setting DCDC_REFRESH_REG_EN=1.
 */
#define SPC_DCDC_TEST_DCDC_REFRESH_EN(x)         (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_TEST_DCDC_REFRESH_EN_SHIFT)) & SPC_DCDC_TEST_DCDC_REFRESH_EN_MASK)

#define SPC_DCDC_TEST_DCDC_REFRESH_REG_EN_MASK   (0x20U)
#define SPC_DCDC_TEST_DCDC_REFRESH_REG_EN_SHIFT  (5U)
/*! DCDC_REFRESH_REG_EN - DCDC_REFRESH_REG_EN
 *  0b0..DCDC Refresh Regulator disabled.
 *  0b1..DCDC Refresh Regulator enabled.
 */
#define SPC_DCDC_TEST_DCDC_REFRESH_REG_EN(x)     (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_TEST_DCDC_REFRESH_REG_EN_SHIFT)) & SPC_DCDC_TEST_DCDC_REFRESH_REG_EN_MASK)

#define SPC_DCDC_TEST_TSTMODE_MASK               (0x1F00U)
#define SPC_DCDC_TEST_TSTMODE_SHIFT              (8U)
/*! TSTMODE - TSTMODE
 */
#define SPC_DCDC_TEST_TSTMODE(x)                 (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_TEST_TSTMODE_SHIFT)) & SPC_DCDC_TEST_TSTMODE_MASK)

#define SPC_DCDC_TEST_CNTRLLOG_EN_MASK           (0x10000U)
#define SPC_DCDC_TEST_CNTRLLOG_EN_SHIFT          (16U)
/*! CNTRLLOG_EN - CNTRLLOG_EN
 */
#define SPC_DCDC_TEST_CNTRLLOG_EN(x)             (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_TEST_CNTRLLOG_EN_SHIFT)) & SPC_DCDC_TEST_CNTRLLOG_EN_MASK)

#define SPC_DCDC_TEST_CNTRLLOG_IN_MASK           (0xFF000000U)
#define SPC_DCDC_TEST_CNTRLLOG_IN_SHIFT          (24U)
/*! CNTRLLOG_IN - CNTRLLOG_IN
 */
#define SPC_DCDC_TEST_CNTRLLOG_IN(x)             (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_TEST_CNTRLLOG_IN_SHIFT)) & SPC_DCDC_TEST_CNTRLLOG_IN_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group SPC_Register_Masks */


/* SPC - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral SPC0 base address */
  #define SPC0_BASE                                (0x50016000u)
  /** Peripheral SPC0 base address */
  #define SPC0_BASE_NS                             (0x40016000u)
  /** Peripheral SPC0 base pointer */
  #define SPC0                                     ((SPC_Type *)SPC0_BASE)
  /** Peripheral SPC0 base pointer */
  #define SPC0_NS                                  ((SPC_Type *)SPC0_BASE_NS)
  /** Array initializer of SPC peripheral base addresses */
  #define SPC_BASE_ADDRS                           { SPC0_BASE }
  /** Array initializer of SPC peripheral base pointers */
  #define SPC_BASE_PTRS                            { SPC0 }
  /** Array initializer of SPC peripheral base addresses */
  #define SPC_BASE_ADDRS_NS                        { SPC0_BASE_NS }
  /** Array initializer of SPC peripheral base pointers */
  #define SPC_BASE_PTRS_NS                         { SPC0_NS }
#else
  /** Peripheral SPC0 base address */
  #define SPC0_BASE                                (0x40016000u)
  /** Peripheral SPC0 base pointer */
  #define SPC0                                     ((SPC_Type *)SPC0_BASE)
  /** Array initializer of SPC peripheral base addresses */
  #define SPC_BASE_ADDRS                           { SPC0_BASE }
  /** Array initializer of SPC peripheral base pointers */
  #define SPC_BASE_PTRS                            { SPC0 }
#endif

/*!
 * @}
 */ /* end of group SPC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- SYSPM Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SYSPM_Peripheral_Access_Layer SYSPM Peripheral Access Layer
 * @{
 */

/** SYSPM - Register Layout Typedef */
typedef struct {
  __I  uint32_t CFGSS[4];                          /**< Configuration 0..Configuration 3, array offset: 0x0, array step: 0x4 */
       uint8_t RESERVED_0[496];
  struct {                                         /* offset: 0x200, array step: 0x100 */
    __IO uint32_t PMCR;                              /**< Performance Monitor Control Register, array offset: 0x200, array step: 0x100 */
         uint8_t RESERVED_0[20];
    struct {                                         /* offset: 0x218, array step: index*0x100, index2*0x8 */
      __I  uint8_t HI;                                 /**< Performance Monitor Event Counter, array offset: 0x218, array step: index*0x100, index2*0x8 */
           uint8_t RESERVED_0[3];
      __I  uint32_t LO;                                /**< Performance Monitor Event Counter, array offset: 0x21C, array step: index*0x100, index2*0x8 */
    } PMECTR[3];
         uint8_t RESERVED_1[208];
  } PMCR[2];
} SYSPM_Type;

/* ----------------------------------------------------------------------------
   -- SYSPM Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SYSPM_Register_Masks SYSPM Register Masks
 * @{
 */

/*! @name CFGSS - Configuration 0..Configuration 3 */
/*! @{ */

#define SYSPM_CFGSS_ID_MASK                      (0xFFU)
#define SYSPM_CFGSS_ID_SHIFT                     (0U)
/*! ID - Identifier
 */
#define SYSPM_CFGSS_ID(x)                        (((uint32_t)(((uint32_t)(x)) << SYSPM_CFGSS_ID_SHIFT)) & SYSPM_CFGSS_ID_MASK)

#define SYSPM_CFGSS_HRL_MASK                     (0xFF00U)
#define SYSPM_CFGSS_HRL_SHIFT                    (8U)
/*! HRL - Hardware revision level
 */
#define SYSPM_CFGSS_HRL(x)                       (((uint32_t)(((uint32_t)(x)) << SYSPM_CFGSS_HRL_SHIFT)) & SYSPM_CFGSS_HRL_MASK)

#define SYSPM_CFGSS_NCTRS_MASK                   (0xFF0000U)
#define SYSPM_CFGSS_NCTRS_SHIFT                  (16U)
/*! NCTRS - Number of Counters
 */
#define SYSPM_CFGSS_NCTRS(x)                     (((uint32_t)(((uint32_t)(x)) << SYSPM_CFGSS_NCTRS_SHIFT)) & SYSPM_CFGSS_NCTRS_MASK)

#define SYSPM_CFGSS_MSC_MASK                     (0xFF000000U)
#define SYSPM_CFGSS_MSC_SHIFT                    (24U)
/*! MSC - Miscellaneous
 */
#define SYSPM_CFGSS_MSC(x)                       (((uint32_t)(((uint32_t)(x)) << SYSPM_CFGSS_MSC_SHIFT)) & SYSPM_CFGSS_MSC_MASK)
/*! @} */

/* The count of SYSPM_CFGSS */
#define SYSPM_CFGSS_COUNT                        (4U)

/*! @name PMCR - Performance Monitor Control Register */
/*! @{ */

#define SYSPM_PMCR_MENB_MASK                     (0x1U)
#define SYSPM_PMCR_MENB_SHIFT                    (0U)
/*! MENB - Module is Enabled
 *  0b0..Disable the performance monitor.
 *  0b1..Enable the performance monitor.
 */
#define SYSPM_PMCR_MENB(x)                       (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_MENB_SHIFT)) & SYSPM_PMCR_MENB_MASK)

#define SYSPM_PMCR_SSC_MASK                      (0xEU)
#define SYSPM_PMCR_SSC_SHIFT                     (1U)
/*! SSC - Start/Stop Control
 *  0b000..Idle
 *  0b001..local stop
 *  0b010..local start
 *  0b011..local start
 *  0b100..
 *  0b101..
 *  0b110..
 *  0b111..
 */
#define SYSPM_PMCR_SSC(x)                        (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_SSC_SHIFT)) & SYSPM_PMCR_SSC_MASK)

#define SYSPM_PMCR_CMODE_MASK                    (0x30U)
#define SYSPM_PMCR_CMODE_SHIFT                   (4U)
/*! CMODE - Count Mode
 *  0b00..count in both user and previleged modes
 *  0b01..Reserved
 *  0b10..count only in user mode
 *  0b11..count only in privileged mode
 */
#define SYSPM_PMCR_CMODE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_CMODE_SHIFT)) & SYSPM_PMCR_CMODE_MASK)

#define SYSPM_PMCR_DCIFSH_MASK                   (0x40U)
#define SYSPM_PMCR_DCIFSH_SHIFT                  (6U)
/*! DCIFSH - Disable Counters if Stopped or Halted
 *  0b0..Conitnue counting
 *  0b1..Stops counting when the CPU is halted
 */
#define SYSPM_PMCR_DCIFSH(x)                     (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_DCIFSH_SHIFT)) & SYSPM_PMCR_DCIFSH_MASK)

#define SYSPM_PMCR_RICTR_MASK                    (0x80U)
#define SYSPM_PMCR_RICTR_SHIFT                   (7U)
/*! RICTR - Resets the Instruction Counter
 *  0b0..do not reset the instruction counter
 *  0b1..clear the instruction counter
 */
#define SYSPM_PMCR_RICTR(x)                      (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_RICTR_SHIFT)) & SYSPM_PMCR_RICTR_MASK)

#define SYSPM_PMCR_RECTR1_MASK                   (0x100U)
#define SYSPM_PMCR_RECTR1_SHIFT                  (8U)
/*! RECTR1 - Reset Event Counter 1
 */
#define SYSPM_PMCR_RECTR1(x)                     (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_RECTR1_SHIFT)) & SYSPM_PMCR_RECTR1_MASK)

#define SYSPM_PMCR_RECTR2_MASK                   (0x200U)
#define SYSPM_PMCR_RECTR2_SHIFT                  (9U)
/*! RECTR2 - Reset Event Counter 2
 */
#define SYSPM_PMCR_RECTR2(x)                     (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_RECTR2_SHIFT)) & SYSPM_PMCR_RECTR2_MASK)

#define SYSPM_PMCR_RECTR3_MASK                   (0x400U)
#define SYSPM_PMCR_RECTR3_SHIFT                  (10U)
/*! RECTR3 - Reset Event Counter 3
 *  0b0..Counter runs normally
 *  0b1..Counter value resets at the end of the cycle
 */
#define SYSPM_PMCR_RECTR3(x)                     (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_RECTR3_SHIFT)) & SYSPM_PMCR_RECTR3_MASK)

#define SYSPM_PMCR_SELEVT1_MASK                  (0x3F800U)
#define SYSPM_PMCR_SELEVT1_SHIFT                 (11U)
/*! SELEVT1 - Select Event 1
 */
#define SYSPM_PMCR_SELEVT1(x)                    (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_SELEVT1_SHIFT)) & SYSPM_PMCR_SELEVT1_MASK)

#define SYSPM_PMCR_SELEVT2_MASK                  (0x1FC0000U)
#define SYSPM_PMCR_SELEVT2_SHIFT                 (18U)
/*! SELEVT2 - Select Event 2
 */
#define SYSPM_PMCR_SELEVT2(x)                    (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_SELEVT2_SHIFT)) & SYSPM_PMCR_SELEVT2_MASK)

#define SYSPM_PMCR_SELEVT3_MASK                  (0xFE000000U)
#define SYSPM_PMCR_SELEVT3_SHIFT                 (25U)
/*! SELEVT3 - Select Event 3
 */
#define SYSPM_PMCR_SELEVT3(x)                    (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_SELEVT3_SHIFT)) & SYSPM_PMCR_SELEVT3_MASK)
/*! @} */

/* The count of SYSPM_PMCR */
#define SYSPM_PMCR_COUNT                         (2U)

/*! @name HI - Performance Monitor Event Counter */
/*! @{ */

#define SYSPM_HI_ECTR_MASK                       (0xFFU)
#define SYSPM_HI_ECTR_SHIFT                      (0U)
/*! ECTR - Event Counter
 */
#define SYSPM_HI_ECTR(x)                         (((uint8_t)(((uint8_t)(x)) << SYSPM_HI_ECTR_SHIFT)) & SYSPM_HI_ECTR_MASK)
/*! @} */

/* The count of SYSPM_HI */
#define SYSPM_HI_COUNT                           (2U)

/* The count of SYSPM_HI */
#define SYSPM_HI_COUNT2                          (3U)

/*! @name LO - Performance Monitor Event Counter */
/*! @{ */

#define SYSPM_LO_ECTR_MASK                       (0xFFFFFFFFU)
#define SYSPM_LO_ECTR_SHIFT                      (0U)
/*! ECTR - Event Counter
 */
#define SYSPM_LO_ECTR(x)                         (((uint32_t)(((uint32_t)(x)) << SYSPM_LO_ECTR_SHIFT)) & SYSPM_LO_ECTR_MASK)
/*! @} */

/* The count of SYSPM_LO */
#define SYSPM_LO_COUNT                           (2U)

/* The count of SYSPM_LO */
#define SYSPM_LO_COUNT2                          (3U)


/*!
 * @}
 */ /* end of group SYSPM_Register_Masks */


/* SYSPM - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral SYSPM base address */
  #define SYSPM_BASE                               (0x50017000u)
  /** Peripheral SYSPM base address */
  #define SYSPM_BASE_NS                            (0x40017000u)
  /** Peripheral SYSPM base pointer */
  #define SYSPM                                    ((SYSPM_Type *)SYSPM_BASE)
  /** Peripheral SYSPM base pointer */
  #define SYSPM_NS                                 ((SYSPM_Type *)SYSPM_BASE_NS)
  /** Array initializer of SYSPM peripheral base addresses */
  #define SYSPM_BASE_ADDRS                         { SYSPM_BASE }
  /** Array initializer of SYSPM peripheral base pointers */
  #define SYSPM_BASE_PTRS                          { SYSPM }
  /** Array initializer of SYSPM peripheral base addresses */
  #define SYSPM_BASE_ADDRS_NS                      { SYSPM_BASE_NS }
  /** Array initializer of SYSPM peripheral base pointers */
  #define SYSPM_BASE_PTRS_NS                       { SYSPM_NS }
#else
  /** Peripheral SYSPM base address */
  #define SYSPM_BASE                               (0x40017000u)
  /** Peripheral SYSPM base pointer */
  #define SYSPM                                    ((SYSPM_Type *)SYSPM_BASE)
  /** Array initializer of SYSPM peripheral base addresses */
  #define SYSPM_BASE_ADDRS                         { SYSPM_BASE }
  /** Array initializer of SYSPM peripheral base pointers */
  #define SYSPM_BASE_PTRS                          { SYSPM }
#endif

/*!
 * @}
 */ /* end of group SYSPM_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- TPM Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
 * @{
 */

/** TPM - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
  __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
  __IO uint32_t GLOBAL;                            /**< TPM Global, offset: 0x8 */
       uint8_t RESERVED_0[4];
  __IO uint32_t SC;                                /**< Status and Control, offset: 0x10 */
  __IO uint32_t CNT;                               /**< Counter, offset: 0x14 */
  __IO uint32_t MOD;                               /**< Modulo, offset: 0x18 */
  __IO uint32_t STATUS;                            /**< Capture and Compare Status, offset: 0x1C */
  struct {                                         /* offset: 0x20, array step: 0x8 */
    __IO uint32_t CnSC;                              /**< Channel (n) Status and Control, array offset: 0x20, array step: 0x8 */
    __IO uint32_t CnV;                               /**< Channel (n) Value, array offset: 0x24, array step: 0x8 */
  } CONTROLS[6];
       uint8_t RESERVED_1[20];
  __IO uint32_t COMBINE;                           /**< Combine Channel Register, offset: 0x64 */
       uint8_t RESERVED_2[4];
  __IO uint32_t TRIG;                              /**< Channel Trigger, offset: 0x6C */
  __IO uint32_t POL;                               /**< Channel Polarity, offset: 0x70 */
       uint8_t RESERVED_3[4];
  __IO uint32_t FILTER;                            /**< Filter Control, offset: 0x78 */
       uint8_t RESERVED_4[4];
  __IO uint32_t QDCTRL;                            /**< Quadrature Decoder Control and Status, offset: 0x80 */
  __IO uint32_t CONF;                              /**< Configuration, offset: 0x84 */
} TPM_Type;

/* ----------------------------------------------------------------------------
   -- TPM Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup TPM_Register_Masks TPM Register Masks
 * @{
 */

/*! @name VERID - Version ID */
/*! @{ */

#define TPM_VERID_FEATURE_MASK                   (0xFFFFU)
#define TPM_VERID_FEATURE_SHIFT                  (0U)
/*! FEATURE - Feature Identification Number
 *  0b0000000000000001..Standard feature set.
 *  0b0000000000000011..Standard feature set with Filter and Combine registers implemented.
 *  0b0000000000000101..Standard feature set with Quadrature registers implemented.
 *  0b0000000000000111..Standard feature set with Filter, Combine and Quadrature registers implemented.
 */
#define TPM_VERID_FEATURE(x)                     (((uint32_t)(((uint32_t)(x)) << TPM_VERID_FEATURE_SHIFT)) & TPM_VERID_FEATURE_MASK)

#define TPM_VERID_MINOR_MASK                     (0xFF0000U)
#define TPM_VERID_MINOR_SHIFT                    (16U)
/*! MINOR - Minor Version Number
 */
#define TPM_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_VERID_MINOR_SHIFT)) & TPM_VERID_MINOR_MASK)

#define TPM_VERID_MAJOR_MASK                     (0xFF000000U)
#define TPM_VERID_MAJOR_SHIFT                    (24U)
/*! MAJOR - Major Version Number
 */
#define TPM_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_VERID_MAJOR_SHIFT)) & TPM_VERID_MAJOR_MASK)
/*! @} */

/*! @name PARAM - Parameter */
/*! @{ */

#define TPM_PARAM_CHAN_MASK                      (0xFFU)
#define TPM_PARAM_CHAN_SHIFT                     (0U)
/*! CHAN - Channel Count
 */
#define TPM_PARAM_CHAN(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_PARAM_CHAN_SHIFT)) & TPM_PARAM_CHAN_MASK)

#define TPM_PARAM_TRIG_MASK                      (0xFF00U)
#define TPM_PARAM_TRIG_SHIFT                     (8U)
/*! TRIG - Trigger Count
 */
#define TPM_PARAM_TRIG(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_PARAM_TRIG_SHIFT)) & TPM_PARAM_TRIG_MASK)

#define TPM_PARAM_WIDTH_MASK                     (0xFF0000U)
#define TPM_PARAM_WIDTH_SHIFT                    (16U)
/*! WIDTH - Counter Width
 */
#define TPM_PARAM_WIDTH(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_PARAM_WIDTH_SHIFT)) & TPM_PARAM_WIDTH_MASK)
/*! @} */

/*! @name GLOBAL - TPM Global */
/*! @{ */

#define TPM_GLOBAL_NOUPDATE_MASK                 (0x1U)
#define TPM_GLOBAL_NOUPDATE_SHIFT                (0U)
/*! NOUPDATE - No Update
 *  0b0..Internal double buffered registers update as normal.
 *  0b1..Internal double buffered registers do not update.
 */
#define TPM_GLOBAL_NOUPDATE(x)                   (((uint32_t)(((uint32_t)(x)) << TPM_GLOBAL_NOUPDATE_SHIFT)) & TPM_GLOBAL_NOUPDATE_MASK)

#define TPM_GLOBAL_RST_MASK                      (0x2U)
#define TPM_GLOBAL_RST_SHIFT                     (1U)
/*! RST - Software Reset
 *  0b0..Module is not reset.
 *  0b1..Module is reset.
 */
#define TPM_GLOBAL_RST(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_GLOBAL_RST_SHIFT)) & TPM_GLOBAL_RST_MASK)
/*! @} */

/*! @name SC - Status and Control */
/*! @{ */

#define TPM_SC_PS_MASK                           (0x7U)
#define TPM_SC_PS_SHIFT                          (0U)
/*! PS - Prescale Factor Selection
 *  0b000..Divide by 1
 *  0b001..Divide by 2
 *  0b010..Divide by 4
 *  0b011..Divide by 8
 *  0b100..Divide by 16
 *  0b101..Divide by 32
 *  0b110..Divide by 64
 *  0b111..Divide by 128
 */
#define TPM_SC_PS(x)                             (((uint32_t)(((uint32_t)(x)) << TPM_SC_PS_SHIFT)) & TPM_SC_PS_MASK)

#define TPM_SC_CMOD_MASK                         (0x18U)
#define TPM_SC_CMOD_SHIFT                        (3U)
/*! CMOD - Clock Mode Selection
 *  0b00..TPM counter is disabled
 *  0b01..TPM counter increments on every TPM counter clock
 *  0b10..TPM counter increments on rising edge of EXTCLK synchronized to the TPM counter clock
 *  0b11..TPM counter increments on rising edge of the selected external input trigger.
 */
#define TPM_SC_CMOD(x)                           (((uint32_t)(((uint32_t)(x)) << TPM_SC_CMOD_SHIFT)) & TPM_SC_CMOD_MASK)

#define TPM_SC_CPWMS_MASK                        (0x20U)
#define TPM_SC_CPWMS_SHIFT                       (5U)
/*! CPWMS - Center-Aligned PWM Select
 *  0b0..TPM counter operates in up counting mode.
 *  0b1..TPM counter operates in up-down counting mode.
 */
#define TPM_SC_CPWMS(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_SC_CPWMS_SHIFT)) & TPM_SC_CPWMS_MASK)

#define TPM_SC_TOIE_MASK                         (0x40U)
#define TPM_SC_TOIE_SHIFT                        (6U)
/*! TOIE - Timer Overflow Interrupt Enable
 *  0b0..Disable TOF interrupts. Use software polling or DMA request.
 *  0b1..Enable TOF interrupts. An interrupt is generated when TOF equals one.
 */
#define TPM_SC_TOIE(x)                           (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOIE_SHIFT)) & TPM_SC_TOIE_MASK)

#define TPM_SC_TOF_MASK                          (0x80U)
#define TPM_SC_TOF_SHIFT                         (7U)
/*! TOF - Timer Overflow Flag
 *  0b0..TPM counter has not overflowed.
 *  0b1..TPM counter has overflowed.
 */
#define TPM_SC_TOF(x)                            (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOF_SHIFT)) & TPM_SC_TOF_MASK)

#define TPM_SC_DMA_MASK                          (0x100U)
#define TPM_SC_DMA_SHIFT                         (8U)
/*! DMA - DMA Enable
 *  0b0..Disables DMA transfers.
 *  0b1..Enables DMA transfers.
 */
#define TPM_SC_DMA(x)                            (((uint32_t)(((uint32_t)(x)) << TPM_SC_DMA_SHIFT)) & TPM_SC_DMA_MASK)
/*! @} */

/*! @name CNT - Counter */
/*! @{ */

#define TPM_CNT_COUNT_MASK                       (0xFFFFFFFFU)
#define TPM_CNT_COUNT_SHIFT                      (0U)
/*! COUNT - Counter value
 */
#define TPM_CNT_COUNT(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CNT_COUNT_SHIFT)) & TPM_CNT_COUNT_MASK)
/*! @} */

/*! @name MOD - Modulo */
/*! @{ */

#define TPM_MOD_MOD_MASK                         (0xFFFFFFFFU)
#define TPM_MOD_MOD_SHIFT                        (0U)
/*! MOD - Modulo value
 */
#define TPM_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x)) << TPM_MOD_MOD_SHIFT)) & TPM_MOD_MOD_MASK)
/*! @} */

/*! @name STATUS - Capture and Compare Status */
/*! @{ */

#define TPM_STATUS_CH0F_MASK                     (0x1U)
#define TPM_STATUS_CH0F_SHIFT                    (0U)
/*! CH0F - Channel 0 Flag
 *  0b0..No channel event has occurred.
 *  0b1..A channel event has occurred.
 */
#define TPM_STATUS_CH0F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH0F_SHIFT)) & TPM_STATUS_CH0F_MASK)

#define TPM_STATUS_CH1F_MASK                     (0x2U)
#define TPM_STATUS_CH1F_SHIFT                    (1U)
/*! CH1F - Channel 1 Flag
 *  0b0..No channel event has occurred.
 *  0b1..A channel event has occurred.
 */
#define TPM_STATUS_CH1F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH1F_SHIFT)) & TPM_STATUS_CH1F_MASK)

#define TPM_STATUS_CH2F_MASK                     (0x4U)
#define TPM_STATUS_CH2F_SHIFT                    (2U)
/*! CH2F - Channel 2 Flag
 *  0b0..No channel event has occurred.
 *  0b1..A channel event has occurred.
 */
#define TPM_STATUS_CH2F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH2F_SHIFT)) & TPM_STATUS_CH2F_MASK)

#define TPM_STATUS_CH3F_MASK                     (0x8U)
#define TPM_STATUS_CH3F_SHIFT                    (3U)
/*! CH3F - Channel 3 Flag
 *  0b0..No channel event has occurred.
 *  0b1..A channel event has occurred.
 */
#define TPM_STATUS_CH3F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH3F_SHIFT)) & TPM_STATUS_CH3F_MASK)

#define TPM_STATUS_CH4F_MASK                     (0x10U)
#define TPM_STATUS_CH4F_SHIFT                    (4U)
/*! CH4F - Channel 4 Flag
 *  0b0..No channel event has occurred.
 *  0b1..A channel event has occurred.
 */
#define TPM_STATUS_CH4F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH4F_SHIFT)) & TPM_STATUS_CH4F_MASK)

#define TPM_STATUS_CH5F_MASK                     (0x20U)
#define TPM_STATUS_CH5F_SHIFT                    (5U)
/*! CH5F - Channel 5 Flag
 *  0b0..No channel event has occurred.
 *  0b1..A channel event has occurred.
 */
#define TPM_STATUS_CH5F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH5F_SHIFT)) & TPM_STATUS_CH5F_MASK)

#define TPM_STATUS_TOF_MASK                      (0x100U)
#define TPM_STATUS_TOF_SHIFT                     (8U)
/*! TOF - Timer Overflow Flag
 *  0b0..TPM counter has not overflowed.
 *  0b1..TPM counter has overflowed.
 */
#define TPM_STATUS_TOF(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_TOF_SHIFT)) & TPM_STATUS_TOF_MASK)
/*! @} */

/*! @name CnSC - Channel (n) Status and Control */
/*! @{ */

#define TPM_CnSC_DMA_MASK                        (0x1U)
#define TPM_CnSC_DMA_SHIFT                       (0U)
/*! DMA - DMA Enable
 *  0b0..Disable DMA transfers.
 *  0b1..Enable DMA transfers.
 */
#define TPM_CnSC_DMA(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_DMA_SHIFT)) & TPM_CnSC_DMA_MASK)

#define TPM_CnSC_ELSA_MASK                       (0x4U)
#define TPM_CnSC_ELSA_SHIFT                      (2U)
/*! ELSA - Edge or Level Select
 */
#define TPM_CnSC_ELSA(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSA_SHIFT)) & TPM_CnSC_ELSA_MASK)

#define TPM_CnSC_ELSB_MASK                       (0x8U)
#define TPM_CnSC_ELSB_SHIFT                      (3U)
/*! ELSB - Edge or Level Select
 */
#define TPM_CnSC_ELSB(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSB_SHIFT)) & TPM_CnSC_ELSB_MASK)

#define TPM_CnSC_MSA_MASK                        (0x10U)
#define TPM_CnSC_MSA_SHIFT                       (4U)
/*! MSA - Channel Mode Select
 */
#define TPM_CnSC_MSA(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSA_SHIFT)) & TPM_CnSC_MSA_MASK)

#define TPM_CnSC_MSB_MASK                        (0x20U)
#define TPM_CnSC_MSB_SHIFT                       (5U)
/*! MSB - Channel Mode Select
 */
#define TPM_CnSC_MSB(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSB_SHIFT)) & TPM_CnSC_MSB_MASK)

#define TPM_CnSC_CHIE_MASK                       (0x40U)
#define TPM_CnSC_CHIE_SHIFT                      (6U)
/*! CHIE - Channel Interrupt Enable
 *  0b0..Disable channel interrupts.
 *  0b1..Enable channel interrupts.
 */
#define TPM_CnSC_CHIE(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHIE_SHIFT)) & TPM_CnSC_CHIE_MASK)

#define TPM_CnSC_CHF_MASK                        (0x80U)
#define TPM_CnSC_CHF_SHIFT                       (7U)
/*! CHF - Channel Flag
 *  0b0..No channel event has occurred.
 *  0b1..A channel event has occurred.
 */
#define TPM_CnSC_CHF(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHF_SHIFT)) & TPM_CnSC_CHF_MASK)
/*! @} */

/* The count of TPM_CnSC */
#define TPM_CnSC_COUNT                           (6U)

/*! @name CnV - Channel (n) Value */
/*! @{ */

#define TPM_CnV_VAL_MASK                         (0xFFFFFFFFU)
#define TPM_CnV_VAL_SHIFT                        (0U)
/*! VAL - Channel Value
 */
#define TPM_CnV_VAL(x)                           (((uint32_t)(((uint32_t)(x)) << TPM_CnV_VAL_SHIFT)) & TPM_CnV_VAL_MASK)
/*! @} */

/* The count of TPM_CnV */
#define TPM_CnV_COUNT                            (6U)

/*! @name COMBINE - Combine Channel Register */
/*! @{ */

#define TPM_COMBINE_COMBINE0_MASK                (0x1U)
#define TPM_COMBINE_COMBINE0_SHIFT               (0U)
/*! COMBINE0 - Combine Channels 0 and 1
 *  0b0..Channels 0 and 1 are independent.
 *  0b1..Channels 0 and 1 are combined.
 */
#define TPM_COMBINE_COMBINE0(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE0_SHIFT)) & TPM_COMBINE_COMBINE0_MASK)

#define TPM_COMBINE_COMSWAP0_MASK                (0x2U)
#define TPM_COMBINE_COMSWAP0_SHIFT               (1U)
/*! COMSWAP0 - Combine Channel 0 and 1 Swap
 *  0b0..Even channel is used for input capture and 1st compare.
 *  0b1..Odd channel is used for input capture and 1st compare.
 */
#define TPM_COMBINE_COMSWAP0(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP0_SHIFT)) & TPM_COMBINE_COMSWAP0_MASK)

#define TPM_COMBINE_COMBINE1_MASK                (0x100U)
#define TPM_COMBINE_COMBINE1_SHIFT               (8U)
/*! COMBINE1 - Combine Channels 2 and 3
 *  0b0..Channels 2 and 3 are independent.
 *  0b1..Channels 2 and 3 are combined.
 */
#define TPM_COMBINE_COMBINE1(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE1_SHIFT)) & TPM_COMBINE_COMBINE1_MASK)

#define TPM_COMBINE_COMSWAP1_MASK                (0x200U)
#define TPM_COMBINE_COMSWAP1_SHIFT               (9U)
/*! COMSWAP1 - Combine Channels 2 and 3 Swap
 *  0b0..Even channel is used for input capture and 1st compare.
 *  0b1..Odd channel is used for input capture and 1st compare.
 */
#define TPM_COMBINE_COMSWAP1(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP1_SHIFT)) & TPM_COMBINE_COMSWAP1_MASK)

#define TPM_COMBINE_COMBINE2_MASK                (0x10000U)
#define TPM_COMBINE_COMBINE2_SHIFT               (16U)
/*! COMBINE2 - Combine Channels 4 and 5
 *  0b0..Channels 4 and 5 are independent.
 *  0b1..Channels 4 and 5 are combined.
 */
#define TPM_COMBINE_COMBINE2(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE2_SHIFT)) & TPM_COMBINE_COMBINE2_MASK)

#define TPM_COMBINE_COMSWAP2_MASK                (0x20000U)
#define TPM_COMBINE_COMSWAP2_SHIFT               (17U)
/*! COMSWAP2 - Combine Channels 4 and 5 Swap
 *  0b0..Even channel is used for input capture and 1st compare.
 *  0b1..Odd channel is used for input capture and 1st compare.
 */
#define TPM_COMBINE_COMSWAP2(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP2_SHIFT)) & TPM_COMBINE_COMSWAP2_MASK)
/*! @} */

/*! @name TRIG - Channel Trigger */
/*! @{ */

#define TPM_TRIG_TRIG0_MASK                      (0x1U)
#define TPM_TRIG_TRIG0_SHIFT                     (0U)
/*! TRIG0 - Channel 0 Trigger
 *  0b0..No effect.
 *  0b1..Configures trigger input 0 to be used by channel 0.
 */
#define TPM_TRIG_TRIG0(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG0_SHIFT)) & TPM_TRIG_TRIG0_MASK)

#define TPM_TRIG_TRIG1_MASK                      (0x2U)
#define TPM_TRIG_TRIG1_SHIFT                     (1U)
/*! TRIG1 - Channel 1 Trigger
 *  0b0..No effect.
 *  0b1..Configures trigger input 1 to be used by channel 1.
 */
#define TPM_TRIG_TRIG1(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG1_SHIFT)) & TPM_TRIG_TRIG1_MASK)

#define TPM_TRIG_TRIG2_MASK                      (0x4U)
#define TPM_TRIG_TRIG2_SHIFT                     (2U)
/*! TRIG2 - Channel 2 Trigger
 *  0b0..No effect.
 *  0b1..Configures trigger input 0 to be used by channel 2.
 */
#define TPM_TRIG_TRIG2(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG2_SHIFT)) & TPM_TRIG_TRIG2_MASK)

#define TPM_TRIG_TRIG3_MASK                      (0x8U)
#define TPM_TRIG_TRIG3_SHIFT                     (3U)
/*! TRIG3 - Channel 3 Trigger
 *  0b0..No effect.
 *  0b1..Configures trigger input 1 to be used by channel 3.
 */
#define TPM_TRIG_TRIG3(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG3_SHIFT)) & TPM_TRIG_TRIG3_MASK)

#define TPM_TRIG_TRIG4_MASK                      (0x10U)
#define TPM_TRIG_TRIG4_SHIFT                     (4U)
/*! TRIG4 - Channel 4 Trigger
 *  0b0..No effect.
 *  0b1..Configures trigger input 0 to be used by channel 4.
 */
#define TPM_TRIG_TRIG4(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG4_SHIFT)) & TPM_TRIG_TRIG4_MASK)

#define TPM_TRIG_TRIG5_MASK                      (0x20U)
#define TPM_TRIG_TRIG5_SHIFT                     (5U)
/*! TRIG5 - Channel 5 Trigger
 *  0b0..No effect.
 *  0b1..Configures trigger input 1 to be used by channel 5.
 */
#define TPM_TRIG_TRIG5(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG5_SHIFT)) & TPM_TRIG_TRIG5_MASK)
/*! @} */

/*! @name POL - Channel Polarity */
/*! @{ */

#define TPM_POL_POL0_MASK                        (0x1U)
#define TPM_POL_POL0_SHIFT                       (0U)
/*! POL0 - Channel 0 Polarity
 *  0b0..The channel polarity is active high.
 *  0b1..The channel polarity is active low.
 */
#define TPM_POL_POL0(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL0_SHIFT)) & TPM_POL_POL0_MASK)

#define TPM_POL_POL1_MASK                        (0x2U)
#define TPM_POL_POL1_SHIFT                       (1U)
/*! POL1 - Channel 1 Polarity
 *  0b0..The channel polarity is active high.
 *  0b1..The channel polarity is active low.
 */
#define TPM_POL_POL1(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL1_SHIFT)) & TPM_POL_POL1_MASK)

#define TPM_POL_POL2_MASK                        (0x4U)
#define TPM_POL_POL2_SHIFT                       (2U)
/*! POL2 - Channel 2 Polarity
 *  0b0..The channel polarity is active high.
 *  0b1..The channel polarity is active low.
 */
#define TPM_POL_POL2(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL2_SHIFT)) & TPM_POL_POL2_MASK)

#define TPM_POL_POL3_MASK                        (0x8U)
#define TPM_POL_POL3_SHIFT                       (3U)
/*! POL3 - Channel 3 Polarity
 *  0b0..The channel polarity is active high.
 *  0b1..The channel polarity is active low.
 */
#define TPM_POL_POL3(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL3_SHIFT)) & TPM_POL_POL3_MASK)

#define TPM_POL_POL4_MASK                        (0x10U)
#define TPM_POL_POL4_SHIFT                       (4U)
/*! POL4 - Channel 4 Polarity
 *  0b0..The channel polarity is active high
 *  0b1..The channel polarity is active low.
 */
#define TPM_POL_POL4(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL4_SHIFT)) & TPM_POL_POL4_MASK)

#define TPM_POL_POL5_MASK                        (0x20U)
#define TPM_POL_POL5_SHIFT                       (5U)
/*! POL5 - Channel 5 Polarity
 *  0b0..The channel polarity is active high.
 *  0b1..The channel polarity is active low.
 */
#define TPM_POL_POL5(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL5_SHIFT)) & TPM_POL_POL5_MASK)
/*! @} */

/*! @name FILTER - Filter Control */
/*! @{ */

#define TPM_FILTER_CH0FVAL_MASK                  (0xFU)
#define TPM_FILTER_CH0FVAL_SHIFT                 (0U)
/*! CH0FVAL - Channel 0 Filter Value
 */
#define TPM_FILTER_CH0FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH0FVAL_SHIFT)) & TPM_FILTER_CH0FVAL_MASK)

#define TPM_FILTER_CH1FVAL_MASK                  (0xF0U)
#define TPM_FILTER_CH1FVAL_SHIFT                 (4U)
/*! CH1FVAL - Channel 1 Filter Value
 */
#define TPM_FILTER_CH1FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH1FVAL_SHIFT)) & TPM_FILTER_CH1FVAL_MASK)

#define TPM_FILTER_CH2FVAL_MASK                  (0xF00U)
#define TPM_FILTER_CH2FVAL_SHIFT                 (8U)
/*! CH2FVAL - Channel 2 Filter Value
 */
#define TPM_FILTER_CH2FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH2FVAL_SHIFT)) & TPM_FILTER_CH2FVAL_MASK)

#define TPM_FILTER_CH3FVAL_MASK                  (0xF000U)
#define TPM_FILTER_CH3FVAL_SHIFT                 (12U)
/*! CH3FVAL - Channel 3 Filter Value
 */
#define TPM_FILTER_CH3FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH3FVAL_SHIFT)) & TPM_FILTER_CH3FVAL_MASK)

#define TPM_FILTER_CH4FVAL_MASK                  (0xF0000U)
#define TPM_FILTER_CH4FVAL_SHIFT                 (16U)
/*! CH4FVAL - Channel 4 Filter Value
 */
#define TPM_FILTER_CH4FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH4FVAL_SHIFT)) & TPM_FILTER_CH4FVAL_MASK)

#define TPM_FILTER_CH5FVAL_MASK                  (0xF00000U)
#define TPM_FILTER_CH5FVAL_SHIFT                 (20U)
/*! CH5FVAL - Channel 5 Filter Value
 */
#define TPM_FILTER_CH5FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH5FVAL_SHIFT)) & TPM_FILTER_CH5FVAL_MASK)
/*! @} */

/*! @name QDCTRL - Quadrature Decoder Control and Status */
/*! @{ */

#define TPM_QDCTRL_QUADEN_MASK                   (0x1U)
#define TPM_QDCTRL_QUADEN_SHIFT                  (0U)
/*! QUADEN - QUADEN
 *  0b0..Quadrature decoder mode is disabled.
 *  0b1..Quadrature decoder mode is enabled.
 */
#define TPM_QDCTRL_QUADEN(x)                     (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADEN_SHIFT)) & TPM_QDCTRL_QUADEN_MASK)

#define TPM_QDCTRL_TOFDIR_MASK                   (0x2U)
#define TPM_QDCTRL_TOFDIR_SHIFT                  (1U)
/*! TOFDIR - TOFDIR
 *  0b0..TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes
 *       from its minimum value (zero) to its maximum value (MOD register).
 *  0b1..TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from
 *       its maximum value (MOD register) to its minimum value (zero).
 */
#define TPM_QDCTRL_TOFDIR(x)                     (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_TOFDIR_SHIFT)) & TPM_QDCTRL_TOFDIR_MASK)

#define TPM_QDCTRL_QUADIR_MASK                   (0x4U)
#define TPM_QDCTRL_QUADIR_SHIFT                  (2U)
/*! QUADIR - Counter Direction in Quadrature Decode Mode
 *  0b0..Counter direction is decreasing (counter decrement).
 *  0b1..Counter direction is increasing (counter increment).
 */
#define TPM_QDCTRL_QUADIR(x)                     (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADIR_SHIFT)) & TPM_QDCTRL_QUADIR_MASK)

#define TPM_QDCTRL_QUADMODE_MASK                 (0x8U)
#define TPM_QDCTRL_QUADMODE_SHIFT                (3U)
/*! QUADMODE - Quadrature Decoder Mode
 *  0b0..Phase encoding mode.
 *  0b1..Count and direction encoding mode.
 */
#define TPM_QDCTRL_QUADMODE(x)                   (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADMODE_SHIFT)) & TPM_QDCTRL_QUADMODE_MASK)
/*! @} */

/*! @name CONF - Configuration */
/*! @{ */

#define TPM_CONF_DOZEEN_MASK                     (0x20U)
#define TPM_CONF_DOZEEN_SHIFT                    (5U)
/*! DOZEEN - Doze Enable
 *  0b0..Internal TPM counter continues.
 *  0b1..Internal TPM counter is paused and does not increment. Trigger inputs and input capture events are
 *       ignored, and PWM outputs are forced to their default state.
 */
#define TPM_CONF_DOZEEN(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DOZEEN_SHIFT)) & TPM_CONF_DOZEEN_MASK)

#define TPM_CONF_DBGMODE_MASK                    (0xC0U)
#define TPM_CONF_DBGMODE_SHIFT                   (6U)
/*! DBGMODE - Debug Mode
 *  0b00..TPM counter is paused and does not increment. Trigger inputs and input capture events are ignored, and
 *        PWM outputs are forced to their default state.
 *  0b11..TPM counter continues.
 */
#define TPM_CONF_DBGMODE(x)                      (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DBGMODE_SHIFT)) & TPM_CONF_DBGMODE_MASK)

#define TPM_CONF_GTBSYNC_MASK                    (0x100U)
#define TPM_CONF_GTBSYNC_SHIFT                   (8U)
/*! GTBSYNC - Global Time Base Synchronization
 *  0b0..Global timebase synchronization disabled.
 *  0b1..Global timebase synchronization enabled.
 */
#define TPM_CONF_GTBSYNC(x)                      (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBSYNC_SHIFT)) & TPM_CONF_GTBSYNC_MASK)

#define TPM_CONF_GTBEEN_MASK                     (0x200U)
#define TPM_CONF_GTBEEN_SHIFT                    (9U)
/*! GTBEEN - Global time base enable
 *  0b0..All channels use the internally generated TPM counter as their timebase
 *  0b1..All channels use an externally generated global timebase as their timebase
 */
#define TPM_CONF_GTBEEN(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBEEN_SHIFT)) & TPM_CONF_GTBEEN_MASK)

#define TPM_CONF_CSOT_MASK                       (0x10000U)
#define TPM_CONF_CSOT_SHIFT                      (16U)
/*! CSOT - Counter Start on Trigger
 *  0b0..TPM counter starts to increment immediately, once it is enabled.
 *  0b1..TPM counter only starts to increment when it a rising edge on the selected input trigger is detected,
 *       after it has been enabled or after it has stopped due to overflow.
 */
#define TPM_CONF_CSOT(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOT_SHIFT)) & TPM_CONF_CSOT_MASK)

#define TPM_CONF_CSOO_MASK                       (0x20000U)
#define TPM_CONF_CSOO_SHIFT                      (17U)
/*! CSOO - Counter Stop On Overflow
 *  0b0..TPM counter continues incrementing or decrementing after overflow
 *  0b1..TPM counter stops incrementing or decrementing after overflow.
 */
#define TPM_CONF_CSOO(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOO_SHIFT)) & TPM_CONF_CSOO_MASK)

#define TPM_CONF_CROT_MASK                       (0x40000U)
#define TPM_CONF_CROT_SHIFT                      (18U)
/*! CROT - Counter Reload On Trigger
 *  0b0..Counter is not reloaded due to a rising edge on the selected input trigger
 *  0b1..Counter is reloaded when a rising edge is detected on the selected input trigger
 */
#define TPM_CONF_CROT(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CROT_SHIFT)) & TPM_CONF_CROT_MASK)

#define TPM_CONF_CPOT_MASK                       (0x80000U)
#define TPM_CONF_CPOT_SHIFT                      (19U)
/*! CPOT - Counter Pause On Trigger
 *  0b0..TPM counter continues
 *  0b1..TPM counter pauses
 */
#define TPM_CONF_CPOT(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CPOT_SHIFT)) & TPM_CONF_CPOT_MASK)

#define TPM_CONF_TRGPOL_MASK                     (0x400000U)
#define TPM_CONF_TRGPOL_SHIFT                    (22U)
/*! TRGPOL - Trigger Polarity
 *  0b0..Trigger is active high.
 *  0b1..Trigger is active low.
 */
#define TPM_CONF_TRGPOL(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGPOL_SHIFT)) & TPM_CONF_TRGPOL_MASK)

#define TPM_CONF_TRGSRC_MASK                     (0x800000U)
#define TPM_CONF_TRGSRC_SHIFT                    (23U)
/*! TRGSRC - Trigger Source
 *  0b0..Trigger source selected by TRGSEL is external.
 *  0b1..Trigger source selected by TRGSEL is internal (channel pin input capture).
 */
#define TPM_CONF_TRGSRC(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSRC_SHIFT)) & TPM_CONF_TRGSRC_MASK)

#define TPM_CONF_TRGSEL_MASK                     (0x3000000U)
#define TPM_CONF_TRGSEL_SHIFT                    (24U)
/*! TRGSEL - Trigger Select
 *  0b01..Channel 0 pin input capture
 *  0b10..Channel 1 pin input capture
 *  0b11..Channel 0 or Channel 1 pin input capture
 */
#define TPM_CONF_TRGSEL(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSEL_SHIFT)) & TPM_CONF_TRGSEL_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group TPM_Register_Masks */


/* TPM - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral TPM0 base address */
  #define TPM0_BASE                                (0x50031000u)
  /** Peripheral TPM0 base address */
  #define TPM0_BASE_NS                             (0x40031000u)
  /** Peripheral TPM0 base pointer */
  #define TPM0                                     ((TPM_Type *)TPM0_BASE)
  /** Peripheral TPM0 base pointer */
  #define TPM0_NS                                  ((TPM_Type *)TPM0_BASE_NS)
  /** Peripheral TPM1 base address */
  #define TPM1_BASE                                (0x50032000u)
  /** Peripheral TPM1 base address */
  #define TPM1_BASE_NS                             (0x40032000u)
  /** Peripheral TPM1 base pointer */
  #define TPM1                                     ((TPM_Type *)TPM1_BASE)
  /** Peripheral TPM1 base pointer */
  #define TPM1_NS                                  ((TPM_Type *)TPM1_BASE_NS)
  /** Peripheral TPM2 base address */
  #define TPM2_BASE                                (0x58984000u)
  /** Peripheral TPM2 base address */
  #define TPM2_BASE_NS                             (0x48984000u)
  /** Peripheral TPM2 base pointer */
  #define TPM2                                     ((TPM_Type *)TPM2_BASE)
  /** Peripheral TPM2 base pointer */
  #define TPM2_NS                                  ((TPM_Type *)TPM2_BASE_NS)
  /** Array initializer of TPM peripheral base addresses */
  #define TPM_BASE_ADDRS                           { TPM0_BASE, TPM1_BASE, TPM2_BASE }
  /** Array initializer of TPM peripheral base pointers */
  #define TPM_BASE_PTRS                            { TPM0, TPM1, TPM2 }
  /** Array initializer of TPM peripheral base addresses */
  #define TPM_BASE_ADDRS_NS                        { TPM0_BASE_NS, TPM1_BASE_NS, TPM2_BASE_NS }
  /** Array initializer of TPM peripheral base pointers */
  #define TPM_BASE_PTRS_NS                         { TPM0_NS, TPM1_NS, TPM2_NS }
#else
  /** Peripheral TPM0 base address */
  #define TPM0_BASE                                (0x40031000u)
  /** Peripheral TPM0 base pointer */
  #define TPM0                                     ((TPM_Type *)TPM0_BASE)
  /** Peripheral TPM1 base address */
  #define TPM1_BASE                                (0x40032000u)
  /** Peripheral TPM1 base pointer */
  #define TPM1                                     ((TPM_Type *)TPM1_BASE)
  /** Peripheral TPM2 base address */
  #define TPM2_BASE                                (0x48984000u)
  /** Peripheral TPM2 base pointer */
  #define TPM2                                     ((TPM_Type *)TPM2_BASE)
  /** Array initializer of TPM peripheral base addresses */
  #define TPM_BASE_ADDRS                           { TPM0_BASE, TPM1_BASE, TPM2_BASE }
  /** Array initializer of TPM peripheral base pointers */
  #define TPM_BASE_PTRS                            { TPM0, TPM1, TPM2 }
#endif
/** Interrupt vectors for the TPM peripheral type */
#define TPM_IRQS                                 { TPM0_IRQn, TPM1_IRQn, NotAvail_IRQn }

/*!
 * @}
 */ /* end of group TPM_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- TRDC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup TRDC_Peripheral_Access_Layer TRDC Peripheral Access Layer
 * @{
 */

/** TRDC - Register Layout Typedef */
typedef struct {
  __IO uint32_t TRDC_CR;                           /**< TRDC Register, offset: 0x0 */
       uint8_t RESERVED_0[236];
  __I  uint32_t TRDC_HWCFG0;                       /**< Hardware Configuration Register 0, offset: 0xF0 */
  __I  uint32_t TRDC_HWCFG1;                       /**< TRDC Hardware Configuration Register 1, offset: 0xF4 */
       uint8_t RESERVED_1[8];
  __I  uint8_t DACFG[4];                           /**< Domain Assignment Configuration Register, array offset: 0x100, array step: 0x1 */
       uint8_t RESERVED_2[60];
  __I  uint32_t CFG[4][2];                         /**< Memory Block Configuration Register, array offset: 0x140, array step: index*0x8, index2*0x4 */
  __I  uint8_t MRCFG[8];                           /**< Memory Region Configuration Register, array offset: 0x160, array step: 0x1 */
       uint8_t RESERVED_3[88];
  __IO uint32_t TRDC_IDAU_CR;                      /**< TRDC IDAU Control Register, offset: 0x1C0 */
       uint8_t RESERVED_4[28];
  __IO uint32_t TRDC_FLW_CTL;                      /**< TRDC FLW Control, offset: 0x1E0 */
  __I  uint32_t TRDC_FLW_PBASE;                    /**< TRDC FLW Physical Base, offset: 0x1E4 */
  __IO uint32_t TRDC_FLW_ABASE;                    /**< TRDC FLW Array Base, offset: 0x1E8 */
  __IO uint32_t TRDC_FLW_BCNT;                     /**< TRDC FLW Block Count, offset: 0x1EC */
       uint8_t RESERVED_5[12];
  __IO uint32_t TRDC_FDID;                         /**< TRDC Fault Domain ID, offset: 0x1FC */
  __I  uint32_t TRDC_DERRLOC[3];                   /**< TRDC Domain Error Location Register, array offset: 0x200, array step: 0x4 */
       uint8_t RESERVED_6[500];
  struct {                                         /* offset: 0x400, array step: 0x10 */
    __I  uint32_t W0;                                /**< MBC Domain Error Word0 Register, array offset: 0x400, array step: 0x10 */
    __I  uint32_t W1;                                /**< MBC Domain Error Word1 Register, array offset: 0x404, array step: 0x10 */
         uint8_t RESERVED_0[4];
    __O  uint32_t W3;                                /**< MBC Domain Error Word3 Register, array offset: 0x40C, array step: 0x10 */
  } MBC_DERR[3];
       uint8_t RESERVED_7[80];
  struct {                                         /* offset: 0x480, array step: 0x10 */
    __I  uint32_t W0;                                /**< MRC Domain Error Word0 Register, array offset: 0x480, array step: 0x10 */
    __I  uint32_t W1;                                /**< MRC Domain Error Word1 Register, array offset: 0x484, array step: 0x10 */
         uint8_t RESERVED_0[4];
    __O  uint32_t W3;                                /**< MRC Domain Error Word3 Register, array offset: 0x48C, array step: 0x10 */
  } MRC_DERR[1];
       uint8_t RESERVED_8[880];
  __IO uint32_t MDA_W0_0_DFMT0;                    /**< DAC Master Domain Assignment Register, offset: 0x800 */
       uint8_t RESERVED_9[28];
  struct {                                         /* offset: 0x820, array step: 0x20 */
    __IO uint32_t MDA_W0_x_DFMT1;                    /**< DAC Master Domain Assignment Register, array offset: 0x820, array step: 0x20 */
         uint8_t RESERVED_0[28];
  } MDA_W0_DFMT1[3];
       uint8_t RESERVED_10[1920];
  struct {                                         /* offset: 0x1000, array step: 0x1000 */
    __I  uint32_t MBC_MEM_GLBCFG[4];                 /**< MBC Global Configuration Register, array offset: 0x1000, array step: index*0x1000, index2*0x4 */
    __IO uint32_t MBC_NSE_BLK_INDEX;                 /**< MBC NonSecure Enable Block Index, array offset: 0x1010, array step: 0x1000 */
    __O  uint32_t MBC_NSE_BLK_SET;                   /**< MBC NonSecure Enable Block Set, array offset: 0x1014, array step: 0x1000 */
    __O  uint32_t MBC_NSE_BLK_CLR;                   /**< MBC NonSecure Enable Block Clear, array offset: 0x1018, array step: 0x1000 */
    __O  uint32_t MBC_NSE_BLK_CLR_ALL;               /**< MBC NonSecure Enable Block Clear All, array offset: 0x101C, array step: 0x1000 */
    __IO uint32_t MBC_MEMN_GLBAC[8];                 /**< MBC Global Access Control, array offset: 0x1020, array step: index*0x1000, index2*0x4 */
    __IO uint32_t MBC_DOM0_MEM0_BLK_CFG_W[10];       /**< MBC Memory Block Configuration Word, array offset: 0x1040, array step: index*0x1000, index2*0x4 */
         uint8_t RESERVED_0[216];
    __IO uint32_t MBC_DOM0_MEM0_BLK_NSE_W[3];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x1140, array step: index*0x1000, index2*0x4 */
         uint8_t RESERVED_1[52];
    __IO uint32_t MBC_DOM0_MEM1_BLK_CFG_W[1];        /**< MBC Memory Block Configuration Word, array offset: 0x1180, array step: index*0x1000, index2*0x4 */
         uint8_t RESERVED_2[28];
    __IO uint32_t MBC_DOM0_MEM1_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11A0, array step: index*0x1000, index2*0x4 */
         uint8_t RESERVED_3[4];
    __IO uint32_t MBC_DOM0_MEM2_BLK_CFG_W[2];        /**< MBC Memory Block Configuration Word, array offset: 0x11A8, array step: index*0x1000, index2*0x4 */
         uint8_t RESERVED_4[24];
    __IO uint32_t MBC_DOM0_MEM2_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11C8, array step: index*0x1000, index2*0x4 */
         uint8_t RESERVED_5[4];
    __IO uint32_t MBC_DOM0_MEM3_BLK_CFG_W[2];        /**< MBC Memory Block Configuration Word, array offset: 0x11D0, array step: index*0x1000, index2*0x4 */
         uint8_t RESERVED_6[24];
    __IO uint32_t MBC_DOM0_MEM3_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11F0, array step: index*0x1000, index2*0x4 */
         uint8_t RESERVED_7[76];
    __IO uint32_t MBC_DOM1_MEM0_BLK_CFG_W[10];       /**< MBC Memory Block Configuration Word, array offset: 0x1240, array step: index*0x1000, index2*0x4 */
         uint8_t RESERVED_8[216];
    __IO uint32_t MBC_DOM1_MEM0_BLK_NSE_W[3];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x1340, array step: index*0x1000, index2*0x4 */
         uint8_t RESERVED_9[52];
    __IO uint32_t MBC_DOM1_MEM1_BLK_CFG_W[1];        /**< MBC Memory Block Configuration Word, array offset: 0x1380, array step: index*0x1000, index2*0x4 */
         uint8_t RESERVED_10[28];
    __IO uint32_t MBC_DOM1_MEM1_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x13A0, array step: index*0x1000, index2*0x4 */
         uint8_t RESERVED_11[4];
    __IO uint32_t MBC_DOM1_MEM2_BLK_CFG_W[2];        /**< MBC Memory Block Configuration Word, array offset: 0x13A8, array step: index*0x1000, index2*0x4 */
         uint8_t RESERVED_12[24];
    __IO uint32_t MBC_DOM1_MEM2_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x13C8, array step: index*0x1000, index2*0x4 */
         uint8_t RESERVED_13[4];
    __IO uint32_t MBC_DOM1_MEM3_BLK_CFG_W[2];        /**< MBC Memory Block Configuration Word, array offset: 0x13D0, array step: index*0x1000, index2*0x4 */
         uint8_t RESERVED_14[24];
    __IO uint32_t MBC_DOM1_MEM3_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x13F0, array step: index*0x1000, index2*0x4 */
         uint8_t RESERVED_15[76];
    __IO uint32_t MBC_DOM2_MEM0_BLK_CFG_W[10];       /**< MBC Memory Block Configuration Word, array offset: 0x1440, array step: index*0x1000, index2*0x4 */
         uint8_t RESERVED_16[216];
    __IO uint32_t MBC_DOM2_MEM0_BLK_NSE_W[3];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x1540, array step: index*0x1000, index2*0x4 */
         uint8_t RESERVED_17[52];
    __IO uint32_t MBC_DOM2_MEM1_BLK_CFG_W[1];        /**< MBC Memory Block Configuration Word, array offset: 0x1580, array step: index*0x1000, index2*0x4 */
         uint8_t RESERVED_18[28];
    __IO uint32_t MBC_DOM2_MEM1_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x15A0, array step: index*0x1000, index2*0x4 */
         uint8_t RESERVED_19[4];
    __IO uint32_t MBC_DOM2_MEM2_BLK_CFG_W[2];        /**< MBC Memory Block Configuration Word, array offset: 0x15A8, array step: index*0x1000, index2*0x4 */
         uint8_t RESERVED_20[24];
    __IO uint32_t MBC_DOM2_MEM2_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x15C8, array step: index*0x1000, index2*0x4 */
         uint8_t RESERVED_21[4];
    __IO uint32_t MBC_DOM2_MEM3_BLK_CFG_W[2];        /**< MBC Memory Block Configuration Word, array offset: 0x15D0, array step: index*0x1000, index2*0x4 */
         uint8_t RESERVED_22[24];
    __IO uint32_t MBC_DOM2_MEM3_BLK_NSE_W[1];        /**< MBC Memory Block NonSecure Enable Word, array offset: 0x15F0, array step: index*0x1000, index2*0x4 */
         uint8_t RESERVED_23[2572];
  } MBC_INDEX[3];
  struct {                                         /* offset: 0x4000, array step: 0x2C4 */
    __I  uint32_t MRC_GLBCFG;                        /**< MRC Global Configuration Register, array offset: 0x4000, array step: 0x2C4 */
         uint8_t RESERVED_0[12];
    __IO uint32_t MRC_NSE_RGN_INDIRECT;              /**< MRC NonSecure Enable Region Indirect, array offset: 0x4010, array step: 0x2C4 */
    __O  uint32_t MRC_NSE_RGN_SET;                   /**< MRC NonSecure Enable Region Set, array offset: 0x4014, array step: 0x2C4 */
    __O  uint32_t MRC_NSE_RGN_CLR;                   /**< MRC NonSecure Enable Region Clear, array offset: 0x4018, array step: 0x2C4 */
    __O  uint32_t MRC_NSE_RGN_CLR_ALL;               /**< MRC NonSecure Enable Region Clear All, array offset: 0x401C, array step: 0x2C4 */
    __IO uint32_t MRC_GLBAC[8];                      /**< MRC Global Access Control, array offset: 0x4020, array step: index*0x2C4, index2*0x4 */
    __IO uint32_t MRC_DOM0_RGD_W[8][2];              /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x4040, array step: index*0x2C4, index2*0x8, index3*0x4 */
         uint8_t RESERVED_1[64];
    __IO uint32_t MRC_DOM0_RGD_NSE;                  /**< MRC Region Descriptor NonSecure Enable, array offset: 0x40C0, array step: 0x2C4 */
         uint8_t RESERVED_2[124];
    __IO uint32_t MRC_DOM1_RGD_W[8][2];              /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x4140, array step: index*0x2C4, index2*0x8, index3*0x4 */
         uint8_t RESERVED_3[64];
    __IO uint32_t MRC_DOM1_RGD_NSE;                  /**< MRC Region Descriptor NonSecure Enable, array offset: 0x41C0, array step: 0x2C4 */
         uint8_t RESERVED_4[124];
    __IO uint32_t MRC_DOM2_RGD_W[8][2];              /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: 0x4240, array step: index*0x2C4, index2*0x8, index3*0x4 */
         uint8_t RESERVED_5[64];
    __IO uint32_t MRC_DOM2_RGD_NSE;                  /**< MRC Region Descriptor NonSecure Enable, array offset: 0x42C0, array step: 0x2C4 */
  } MRC_INDEX[1];
} TRDC_Type;

/* ----------------------------------------------------------------------------
   -- TRDC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup TRDC_Register_Masks TRDC Register Masks
 * @{
 */

/*! @name TRDC_CR - TRDC Register */
/*! @{ */

#define TRDC_TRDC_CR_GVLDM_MASK                  (0x1U)
#define TRDC_TRDC_CR_GVLDM_SHIFT                 (0U)
/*! GVLDM - Global Valid for Domain Assignment Controllers
 *  0b0..TRDC DACs are disabled.
 *  0b1..TRDC DACs are enabled.
 */
#define TRDC_TRDC_CR_GVLDM(x)                    (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_CR_GVLDM_SHIFT)) & TRDC_TRDC_CR_GVLDM_MASK)

#define TRDC_TRDC_CR_HRL_MASK                    (0x1EU)
#define TRDC_TRDC_CR_HRL_SHIFT                   (1U)
/*! HRL - Hardware Revision Level
 */
#define TRDC_TRDC_CR_HRL(x)                      (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_CR_HRL_SHIFT)) & TRDC_TRDC_CR_HRL_MASK)

#define TRDC_TRDC_CR_GVLDB_MASK                  (0x4000U)
#define TRDC_TRDC_CR_GVLDB_SHIFT                 (14U)
/*! GVLDB - Global Valid for Memory Block Checkers
 *  0b0..TRDC MBCs are disabled.
 *  0b1..TRDC MBCs are enabled.
 */
#define TRDC_TRDC_CR_GVLDB(x)                    (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_CR_GVLDB_SHIFT)) & TRDC_TRDC_CR_GVLDB_MASK)

#define TRDC_TRDC_CR_GVLDR_MASK                  (0x8000U)
#define TRDC_TRDC_CR_GVLDR_SHIFT                 (15U)
/*! GVLDR - Global Valid for Memory Region Checkers
 *  0b0..TRDC MRCs are disabled.
 *  0b1..TRDC MRCs are enabled.
 */
#define TRDC_TRDC_CR_GVLDR(x)                    (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_CR_GVLDR_SHIFT)) & TRDC_TRDC_CR_GVLDR_MASK)

#define TRDC_TRDC_CR_LK1_MASK                    (0x40000000U)
#define TRDC_TRDC_CR_LK1_SHIFT                   (30U)
/*! LK1 - Lock Status
 *  0b0..The CR can be written by any secure privileged write.
 *  0b1..The CR is locked (read-only) until the next reset.
 */
#define TRDC_TRDC_CR_LK1(x)                      (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_CR_LK1_SHIFT)) & TRDC_TRDC_CR_LK1_MASK)
/*! @} */

/*! @name TRDC_HWCFG0 - Hardware Configuration Register 0 */
/*! @{ */

#define TRDC_TRDC_HWCFG0_NDID_MASK               (0xFU)
#define TRDC_TRDC_HWCFG0_NDID_SHIFT              (0U)
/*! NDID - Number of domains
 */
#define TRDC_TRDC_HWCFG0_NDID(x)                 (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_HWCFG0_NDID_SHIFT)) & TRDC_TRDC_HWCFG0_NDID_MASK)

#define TRDC_TRDC_HWCFG0_NMSTR_MASK              (0xFF00U)
#define TRDC_TRDC_HWCFG0_NMSTR_SHIFT             (8U)
/*! NMSTR - Number of bus masters
 */
#define TRDC_TRDC_HWCFG0_NMSTR(x)                (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_HWCFG0_NMSTR_SHIFT)) & TRDC_TRDC_HWCFG0_NMSTR_MASK)

#define TRDC_TRDC_HWCFG0_NMBC_MASK               (0x70000U)
#define TRDC_TRDC_HWCFG0_NMBC_SHIFT              (16U)
/*! NMBC - Number of MBCs
 */
#define TRDC_TRDC_HWCFG0_NMBC(x)                 (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_HWCFG0_NMBC_SHIFT)) & TRDC_TRDC_HWCFG0_NMBC_MASK)

#define TRDC_TRDC_HWCFG0_NMRC_MASK               (0xF000000U)
#define TRDC_TRDC_HWCFG0_NMRC_SHIFT              (24U)
/*! NMRC - Number of MRCs
 */
#define TRDC_TRDC_HWCFG0_NMRC(x)                 (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_HWCFG0_NMRC_SHIFT)) & TRDC_TRDC_HWCFG0_NMRC_MASK)

#define TRDC_TRDC_HWCFG0_MID_MASK                (0xF0000000U)
#define TRDC_TRDC_HWCFG0_MID_SHIFT               (28U)
/*! MID - Module ID
 */
#define TRDC_TRDC_HWCFG0_MID(x)                  (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_HWCFG0_MID_SHIFT)) & TRDC_TRDC_HWCFG0_MID_MASK)
/*! @} */

/*! @name TRDC_HWCFG1 - TRDC Hardware Configuration Register 1 */
/*! @{ */

#define TRDC_TRDC_HWCFG1_DID_MASK                (0x7U)
#define TRDC_TRDC_HWCFG1_DID_SHIFT               (0U)
/*! DID - Domain identifier number
 */
#define TRDC_TRDC_HWCFG1_DID(x)                  (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_HWCFG1_DID_SHIFT)) & TRDC_TRDC_HWCFG1_DID_MASK)
/*! @} */

/*! @name DACFG - Domain Assignment Configuration Register */
/*! @{ */

#define TRDC_DACFG_NMDAR_MASK                    (0xFU)
#define TRDC_DACFG_NMDAR_SHIFT                   (0U)
/*! NMDAR - Number of master domain assignment registers for bus master m
 */
#define TRDC_DACFG_NMDAR(x)                      (((uint8_t)(((uint8_t)(x)) << TRDC_DACFG_NMDAR_SHIFT)) & TRDC_DACFG_NMDAR_MASK)

#define TRDC_DACFG_NCM_MASK                      (0x80U)
#define TRDC_DACFG_NCM_SHIFT                     (7U)
/*! NCM - Non-CPU Master
 *  0b0..Bus master is a processor.
 *  0b1..Bus master is a non-processor.
 */
#define TRDC_DACFG_NCM(x)                        (((uint8_t)(((uint8_t)(x)) << TRDC_DACFG_NCM_SHIFT)) & TRDC_DACFG_NCM_MASK)
/*! @} */

/* The count of TRDC_DACFG */
#define TRDC_DACFG_COUNT                         (4U)

/*! @name CFG - Memory Block Configuration Register */
/*! @{ */

#define TRDC_CFG_SLV0_NMBLK_MASK                 (0x3FFU)
#define TRDC_CFG_SLV0_NMBLK_SHIFT                (0U)
/*! SLV0_NMBLK - Number of blocks in slave 0.
 */
#define TRDC_CFG_SLV0_NMBLK(x)                   (((uint32_t)(((uint32_t)(x)) << TRDC_CFG_SLV0_NMBLK_SHIFT)) & TRDC_CFG_SLV0_NMBLK_MASK)

#define TRDC_CFG_SLV2_NMBLK_MASK                 (0x3FFU)
#define TRDC_CFG_SLV2_NMBLK_SHIFT                (0U)
/*! SLV2_NMBLK - Number of blocks in slave 2.
 */
#define TRDC_CFG_SLV2_NMBLK(x)                   (((uint32_t)(((uint32_t)(x)) << TRDC_CFG_SLV2_NMBLK_SHIFT)) & TRDC_CFG_SLV2_NMBLK_MASK)

#define TRDC_CFG_SLV0_BLKSZL2_MASK               (0x7C00U)
#define TRDC_CFG_SLV0_BLKSZL2_SHIFT              (10U)
/*! SLV0_BLKSZL2 - Block size log2 in slave 0.
 */
#define TRDC_CFG_SLV0_BLKSZL2(x)                 (((uint32_t)(((uint32_t)(x)) << TRDC_CFG_SLV0_BLKSZL2_SHIFT)) & TRDC_CFG_SLV0_BLKSZL2_MASK)

#define TRDC_CFG_SLV2_BLKSZL2_MASK               (0x7C00U)
#define TRDC_CFG_SLV2_BLKSZL2_SHIFT              (10U)
/*! SLV2_BLKSZL2 - Block size log2 in slave 2.
 */
#define TRDC_CFG_SLV2_BLKSZL2(x)                 (((uint32_t)(((uint32_t)(x)) << TRDC_CFG_SLV2_BLKSZL2_SHIFT)) & TRDC_CFG_SLV2_BLKSZL2_MASK)

#define TRDC_CFG_SLV1_NMBLK_MASK                 (0x3FF0000U)
#define TRDC_CFG_SLV1_NMBLK_SHIFT                (16U)
/*! SLV1_NMBLK - Number of blocks in slave 1.
 */
#define TRDC_CFG_SLV1_NMBLK(x)                   (((uint32_t)(((uint32_t)(x)) << TRDC_CFG_SLV1_NMBLK_SHIFT)) & TRDC_CFG_SLV1_NMBLK_MASK)

#define TRDC_CFG_SLV3_NMBLK_MASK                 (0x3FF0000U)
#define TRDC_CFG_SLV3_NMBLK_SHIFT                (16U)
/*! SLV3_NMBLK - Number of blocks in slave 3.
 */
#define TRDC_CFG_SLV3_NMBLK(x)                   (((uint32_t)(((uint32_t)(x)) << TRDC_CFG_SLV3_NMBLK_SHIFT)) & TRDC_CFG_SLV3_NMBLK_MASK)

#define TRDC_CFG_SLV1_BLKSZL2_MASK               (0x7C000000U)
#define TRDC_CFG_SLV1_BLKSZL2_SHIFT              (26U)
/*! SLV1_BLKSZL2 - Block size log2 in slave 1.
 */
#define TRDC_CFG_SLV1_BLKSZL2(x)                 (((uint32_t)(((uint32_t)(x)) << TRDC_CFG_SLV1_BLKSZL2_SHIFT)) & TRDC_CFG_SLV1_BLKSZL2_MASK)

#define TRDC_CFG_SLV3_BLKSZL2_MASK               (0x7C000000U)
#define TRDC_CFG_SLV3_BLKSZL2_SHIFT              (26U)
/*! SLV3_BLKSZL2 - Block size log2 in slave 3.
 */
#define TRDC_CFG_SLV3_BLKSZL2(x)                 (((uint32_t)(((uint32_t)(x)) << TRDC_CFG_SLV3_BLKSZL2_SHIFT)) & TRDC_CFG_SLV3_BLKSZL2_MASK)
/*! @} */

/* The count of TRDC_CFG */
#define TRDC_CFG_COUNT                           (4U)

/* The count of TRDC_CFG */
#define TRDC_CFG_COUNT2                          (2U)

/*! @name MRCFG - Memory Region Configuration Register */
/*! @{ */

#define TRDC_MRCFG_NMRGD_MASK                    (0x1FU)
#define TRDC_MRCFG_NMRGD_SHIFT                   (0U)
/*! NMRGD - Number of memory region descriptors for memory region checker n
 */
#define TRDC_MRCFG_NMRGD(x)                      (((uint8_t)(((uint8_t)(x)) << TRDC_MRCFG_NMRGD_SHIFT)) & TRDC_MRCFG_NMRGD_MASK)
/*! @} */

/* The count of TRDC_MRCFG */
#define TRDC_MRCFG_COUNT                         (8U)

/*! @name TRDC_IDAU_CR - TRDC IDAU Control Register */
/*! @{ */

#define TRDC_TRDC_IDAU_CR_VLD_MASK               (0x1U)
#define TRDC_TRDC_IDAU_CR_VLD_SHIFT              (0U)
/*! VLD - Valid
 */
#define TRDC_TRDC_IDAU_CR_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_IDAU_CR_VLD_SHIFT)) & TRDC_TRDC_IDAU_CR_VLD_MASK)

#define TRDC_TRDC_IDAU_CR_CFGSECEXT_MASK         (0x8U)
#define TRDC_TRDC_IDAU_CR_CFGSECEXT_SHIFT        (3U)
/*! CFGSECEXT - Configure Security Extension
 *  0b0..ARMv8M Security Extension is disabled
 *  0b1..ARMv8-M Security Extension is enabled
 */
#define TRDC_TRDC_IDAU_CR_CFGSECEXT(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_IDAU_CR_CFGSECEXT_SHIFT)) & TRDC_TRDC_IDAU_CR_CFGSECEXT_MASK)

#define TRDC_TRDC_IDAU_CR_MPUSDIS_MASK           (0x10U)
#define TRDC_TRDC_IDAU_CR_MPUSDIS_SHIFT          (4U)
/*! MPUSDIS - Secure Memory Protection Unit Disabled
 *  0b0..Secure MPU is enabled
 *  0b1..Secure MPU is disabled
 */
#define TRDC_TRDC_IDAU_CR_MPUSDIS(x)             (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_IDAU_CR_MPUSDIS_SHIFT)) & TRDC_TRDC_IDAU_CR_MPUSDIS_MASK)

#define TRDC_TRDC_IDAU_CR_MPUNSDIS_MASK          (0x20U)
#define TRDC_TRDC_IDAU_CR_MPUNSDIS_SHIFT         (5U)
/*! MPUNSDIS - NonSecure Memory Protection Unit Disabled
 *  0b0..Nonsecure MPU is enabled
 *  0b1..Nonsecure MPU is disabled
 */
#define TRDC_TRDC_IDAU_CR_MPUNSDIS(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_IDAU_CR_MPUNSDIS_SHIFT)) & TRDC_TRDC_IDAU_CR_MPUNSDIS_MASK)

#define TRDC_TRDC_IDAU_CR_SAUDIS_MASK            (0x40U)
#define TRDC_TRDC_IDAU_CR_SAUDIS_SHIFT           (6U)
/*! SAUDIS - Security Attribution Unit Disable
 *  0b0..SAU is enabled
 *  0b1..SAU is disabled
 */
#define TRDC_TRDC_IDAU_CR_SAUDIS(x)              (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_IDAU_CR_SAUDIS_SHIFT)) & TRDC_TRDC_IDAU_CR_SAUDIS_MASK)

#define TRDC_TRDC_IDAU_CR_LKSVTAIRCR_MASK        (0x100U)
#define TRDC_TRDC_IDAU_CR_LKSVTAIRCR_SHIFT       (8U)
/*! LKSVTAIRCR - Lock Secure VTOR, Application interrupt and Reset Control Registers
 *  0b0..Unlock these registers
 *  0b1..Disable writes to the VTOR_S, AIRCR[PRIS], and AIRCR[BFHFNMINS] registers
 */
#define TRDC_TRDC_IDAU_CR_LKSVTAIRCR(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_IDAU_CR_LKSVTAIRCR_SHIFT)) & TRDC_TRDC_IDAU_CR_LKSVTAIRCR_MASK)

#define TRDC_TRDC_IDAU_CR_LKNSVTOR_MASK          (0x200U)
#define TRDC_TRDC_IDAU_CR_LKNSVTOR_SHIFT         (9U)
/*! LKNSVTOR - Lock Nonsecure Vector Table Offset Register
 *  0b0..Unlock this register
 *  0b1..Disable writes to the VTOR_NS register
 */
#define TRDC_TRDC_IDAU_CR_LKNSVTOR(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_IDAU_CR_LKNSVTOR_SHIFT)) & TRDC_TRDC_IDAU_CR_LKNSVTOR_MASK)

#define TRDC_TRDC_IDAU_CR_LKSMPU_MASK            (0x400U)
#define TRDC_TRDC_IDAU_CR_LKSMPU_SHIFT           (10U)
/*! LKSMPU - Lock Secure MPU
 *  0b0..Unlock these registers
 *  0b1..Disable writes to the MPU_CTRL, MPU_RNR, MPU_RBAR, MPU_RLAR, MPU_RBAR_An and MPU_RLAR_An from software or
 *       from a debug agent connected to the processor in Secure state
 */
#define TRDC_TRDC_IDAU_CR_LKSMPU(x)              (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_IDAU_CR_LKSMPU_SHIFT)) & TRDC_TRDC_IDAU_CR_LKSMPU_MASK)

#define TRDC_TRDC_IDAU_CR_LKNSMPU_MASK           (0x800U)
#define TRDC_TRDC_IDAU_CR_LKNSMPU_SHIFT          (11U)
/*! LKNSMPU - Lock Nonsecure MPU
 *  0b0..Unlock these registers
 *  0b1..Disable writes to the MPU_CTRL_NS, MPU_RNR_NS, MPU_RBAR_NS, MPU_RLAR_NS, MPU_RBAR_A_NSn and
 *       MPU_RLAR_A_NSn from software or from a debug agent connected to the processor
 */
#define TRDC_TRDC_IDAU_CR_LKNSMPU(x)             (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_IDAU_CR_LKNSMPU_SHIFT)) & TRDC_TRDC_IDAU_CR_LKNSMPU_MASK)

#define TRDC_TRDC_IDAU_CR_LKSAU_MASK             (0x1000U)
#define TRDC_TRDC_IDAU_CR_LKSAU_SHIFT            (12U)
/*! LKSAU - Lock SAU
 *  0b0..Unlock these registers
 *  0b1..Disable writes to the SAU_CTRL, SAU_RNR, SAU_RBAR and SAU_RLAR registers from software or from a debug agent connected to the processor
 */
#define TRDC_TRDC_IDAU_CR_LKSAU(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_IDAU_CR_LKSAU_SHIFT)) & TRDC_TRDC_IDAU_CR_LKSAU_MASK)

#define TRDC_TRDC_IDAU_CR_PCURRNS_MASK           (0x80000000U)
#define TRDC_TRDC_IDAU_CR_PCURRNS_SHIFT          (31U)
/*! PCURRNS - Processor current security
 *  0b0..Processor is in Secure state
 *  0b1..Processor is in Nonsecure state
 */
#define TRDC_TRDC_IDAU_CR_PCURRNS(x)             (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_IDAU_CR_PCURRNS_SHIFT)) & TRDC_TRDC_IDAU_CR_PCURRNS_MASK)
/*! @} */

/*! @name TRDC_FLW_CTL - TRDC FLW Control */
/*! @{ */

#define TRDC_TRDC_FLW_CTL_LK_MASK                (0x40000000U)
#define TRDC_TRDC_FLW_CTL_LK_SHIFT               (30U)
/*! LK - Lock bit
 *  0b0..FLW registers may be modified.
 *  0b1..FLW registers are locked until the next reset.
 */
#define TRDC_TRDC_FLW_CTL_LK(x)                  (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_FLW_CTL_LK_SHIFT)) & TRDC_TRDC_FLW_CTL_LK_MASK)

#define TRDC_TRDC_FLW_CTL_V_MASK                 (0x80000000U)
#define TRDC_TRDC_FLW_CTL_V_SHIFT                (31U)
/*! V - Valid bit
 *  0b0..FLW function is disabled.
 *  0b1..FLW function is enabled.
 */
#define TRDC_TRDC_FLW_CTL_V(x)                   (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_FLW_CTL_V_SHIFT)) & TRDC_TRDC_FLW_CTL_V_MASK)
/*! @} */

/*! @name TRDC_FLW_PBASE - TRDC FLW Physical Base */
/*! @{ */

#define TRDC_TRDC_FLW_PBASE_PBASE_MASK           (0xFFFFFFFFU)
#define TRDC_TRDC_FLW_PBASE_PBASE_SHIFT          (0U)
/*! PBASE - Physical base address
 */
#define TRDC_TRDC_FLW_PBASE_PBASE(x)             (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_FLW_PBASE_PBASE_SHIFT)) & TRDC_TRDC_FLW_PBASE_PBASE_MASK)
/*! @} */

/*! @name TRDC_FLW_ABASE - TRDC FLW Array Base */
/*! @{ */

#define TRDC_TRDC_FLW_ABASE_ABASE_L_MASK         (0x3F8000U)
#define TRDC_TRDC_FLW_ABASE_ABASE_L_SHIFT        (15U)
/*! ABASE_L - Array base address low
 */
#define TRDC_TRDC_FLW_ABASE_ABASE_L(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_FLW_ABASE_ABASE_L_SHIFT)) & TRDC_TRDC_FLW_ABASE_ABASE_L_MASK)

#define TRDC_TRDC_FLW_ABASE_ABASE_H_MASK         (0xFFC00000U)
#define TRDC_TRDC_FLW_ABASE_ABASE_H_SHIFT        (22U)
/*! ABASE_H - Array base address high
 */
#define TRDC_TRDC_FLW_ABASE_ABASE_H(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_FLW_ABASE_ABASE_H_SHIFT)) & TRDC_TRDC_FLW_ABASE_ABASE_H_MASK)
/*! @} */

/*! @name TRDC_FLW_BCNT - TRDC FLW Block Count */
/*! @{ */

#define TRDC_TRDC_FLW_BCNT_BCNT_MASK             (0x7FFFU)
#define TRDC_TRDC_FLW_BCNT_BCNT_SHIFT            (0U)
/*! BCNT - Block Count
 */
#define TRDC_TRDC_FLW_BCNT_BCNT(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_FLW_BCNT_BCNT_SHIFT)) & TRDC_TRDC_FLW_BCNT_BCNT_MASK)
/*! @} */

/*! @name TRDC_FDID - TRDC Fault Domain ID */
/*! @{ */

#define TRDC_TRDC_FDID_FDID_MASK                 (0xFU)
#define TRDC_TRDC_FDID_FDID_SHIFT                (0U)
/*! FDID - Domain ID of Faulted Access
 */
#define TRDC_TRDC_FDID_FDID(x)                   (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_FDID_FDID_SHIFT)) & TRDC_TRDC_FDID_FDID_MASK)
/*! @} */

/*! @name TRDC_DERRLOC - TRDC Domain Error Location Register */
/*! @{ */

#define TRDC_TRDC_DERRLOC_mbc0_err_slv_MASK      (0xFU)
#define TRDC_TRDC_DERRLOC_mbc0_err_slv_SHIFT     (0U)
/*! mbc0_err_slv - MBC0 ERROR SLAVE
 */
#define TRDC_TRDC_DERRLOC_mbc0_err_slv(x)        (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_DERRLOC_mbc0_err_slv_SHIFT)) & TRDC_TRDC_DERRLOC_mbc0_err_slv_MASK)

#define TRDC_TRDC_DERRLOC_mbc1_err_slv_MASK      (0xF0U)
#define TRDC_TRDC_DERRLOC_mbc1_err_slv_SHIFT     (4U)
/*! mbc1_err_slv - MBC1 ERROR SLAVE
 */
#define TRDC_TRDC_DERRLOC_mbc1_err_slv(x)        (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_DERRLOC_mbc1_err_slv_SHIFT)) & TRDC_TRDC_DERRLOC_mbc1_err_slv_MASK)

#define TRDC_TRDC_DERRLOC_mbc2_err_slv_MASK      (0xF00U)
#define TRDC_TRDC_DERRLOC_mbc2_err_slv_SHIFT     (8U)
/*! mbc2_err_slv - MBC2 ERROR SLAVE
 */
#define TRDC_TRDC_DERRLOC_mbc2_err_slv(x)        (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_DERRLOC_mbc2_err_slv_SHIFT)) & TRDC_TRDC_DERRLOC_mbc2_err_slv_MASK)

#define TRDC_TRDC_DERRLOC_mbc3_err_slv_MASK      (0xF000U)
#define TRDC_TRDC_DERRLOC_mbc3_err_slv_SHIFT     (12U)
/*! mbc3_err_slv - MBC3 ERROR SLAVE
 */
#define TRDC_TRDC_DERRLOC_mbc3_err_slv(x)        (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_DERRLOC_mbc3_err_slv_SHIFT)) & TRDC_TRDC_DERRLOC_mbc3_err_slv_MASK)

#define TRDC_TRDC_DERRLOC_MRCINST_MASK           (0xFF0000U)
#define TRDC_TRDC_DERRLOC_MRCINST_SHIFT          (16U)
/*! MRCINST - MRC instance
 */
#define TRDC_TRDC_DERRLOC_MRCINST(x)             (((uint32_t)(((uint32_t)(x)) << TRDC_TRDC_DERRLOC_MRCINST_SHIFT)) & TRDC_TRDC_DERRLOC_MRCINST_MASK)
/*! @} */

/* The count of TRDC_TRDC_DERRLOC */
#define TRDC_TRDC_DERRLOC_COUNT                  (3U)

/*! @name W0 - MBC Domain Error Word0 Register */
/*! @{ */

#define TRDC_W0_EADDR_MASK                       (0xFFFFFFFFU)
#define TRDC_W0_EADDR_SHIFT                      (0U)
/*! EADDR - Error address
 */
#define TRDC_W0_EADDR(x)                         (((uint32_t)(((uint32_t)(x)) << TRDC_W0_EADDR_SHIFT)) & TRDC_W0_EADDR_MASK)
/*! @} */

/* The count of TRDC_W0 */
#define TRDC_W0_COUNT                            (3U)

/*! @name W1 - MBC Domain Error Word1 Register */
/*! @{ */

#define TRDC_W1_EDID_MASK                        (0xFU)
#define TRDC_W1_EDID_SHIFT                       (0U)
/*! EDID - Error domain identifier
 */
#define TRDC_W1_EDID(x)                          (((uint32_t)(((uint32_t)(x)) << TRDC_W1_EDID_SHIFT)) & TRDC_W1_EDID_MASK)

#define TRDC_W1_EATR_MASK                        (0x700U)
#define TRDC_W1_EATR_SHIFT                       (8U)
/*! EATR - Error attributes
 *  0b000..Secure user mode, instruction fetch access.
 *  0b001..Secure user mode, data access.
 *  0b010..Secure privileged mode, instruction fetch access.
 *  0b011..Secure privileged mode, data access.
 *  0b100..Nonsecure user mode, instruction fetch access.
 *  0b101..Nonsecure user mode, data access.
 *  0b110..Nonsecure privileged mode, instruction fetch access.
 *  0b111..Nonsecure privileged mode, data access.
 */
#define TRDC_W1_EATR(x)                          (((uint32_t)(((uint32_t)(x)) << TRDC_W1_EATR_SHIFT)) & TRDC_W1_EATR_MASK)

#define TRDC_W1_ERW_MASK                         (0x800U)
#define TRDC_W1_ERW_SHIFT                        (11U)
/*! ERW - Error read/write
 *  0b0..Read access
 *  0b1..Write access
 */
#define TRDC_W1_ERW(x)                           (((uint32_t)(((uint32_t)(x)) << TRDC_W1_ERW_SHIFT)) & TRDC_W1_ERW_MASK)

#define TRDC_W1_EPORT_MASK                       (0x7000000U)
#define TRDC_W1_EPORT_SHIFT                      (24U)
/*! EPORT - Error port
 *  0b000..mbcxslv0
 *  0b001..mbcxslv1
 *  0b010..mbcxslv2
 *  0b011..mbcxslv3
 */
#define TRDC_W1_EPORT(x)                         (((uint32_t)(((uint32_t)(x)) << TRDC_W1_EPORT_SHIFT)) & TRDC_W1_EPORT_MASK)

#define TRDC_W1_EST_MASK                         (0xC0000000U)
#define TRDC_W1_EST_SHIFT                        (30U)
/*! EST - Error state
 *  0b00..No access violation has been detected.
 *  0b01..No access violation has been detected.
 *  0b10..A single access violation has been detected.
 *  0b11..Multiple access violations for this domain have been detected by this submodule instance. Only the
 *        address and attribute information for the first error have been captured in DERR_W0_i and DERR_W1_i.
 */
#define TRDC_W1_EST(x)                           (((uint32_t)(((uint32_t)(x)) << TRDC_W1_EST_SHIFT)) & TRDC_W1_EST_MASK)
/*! @} */

/* The count of TRDC_W1 */
#define TRDC_W1_COUNT                            (3U)

/*! @name W3 - MBC Domain Error Word3 Register */
/*! @{ */

#define TRDC_W3_RECR_MASK                        (0xC0000000U)
#define TRDC_W3_RECR_SHIFT                       (30U)
/*! RECR - Rearm Error Capture Registers
 */
#define TRDC_W3_RECR(x)                          (((uint32_t)(((uint32_t)(x)) << TRDC_W3_RECR_SHIFT)) & TRDC_W3_RECR_MASK)
/*! @} */

/* The count of TRDC_W3 */
#define TRDC_W3_COUNT                            (3U)

/*! @name W0 - MRC Domain Error Word0 Register */
/*! @{ */

#define TRDC_W0_EADDR_MASK                       (0xFFFFFFFFU)
#define TRDC_W0_EADDR_SHIFT                      (0U)
/*! EADDR - Error address
 */
#define TRDC_W0_EADDR(x)                         (((uint32_t)(((uint32_t)(x)) << TRDC_W0_EADDR_SHIFT)) & TRDC_W0_EADDR_MASK)
/*! @} */

/* The count of TRDC_W0 */
#define TRDC_MRC_DERR_W0_COUNT                   (1U)

/*! @name W1 - MRC Domain Error Word1 Register */
/*! @{ */

#define TRDC_W1_EDID_MASK                        (0xFU)
#define TRDC_W1_EDID_SHIFT                       (0U)
/*! EDID - Error domain identifier
 */
#define TRDC_W1_EDID(x)                          (((uint32_t)(((uint32_t)(x)) << TRDC_W1_EDID_SHIFT)) & TRDC_W1_EDID_MASK)

#define TRDC_W1_EATR_MASK                        (0x700U)
#define TRDC_W1_EATR_SHIFT                       (8U)
/*! EATR - Error attributes
 *  0b000..Secure user mode, instruction fetch access.
 *  0b001..Secure user mode, data access.
 *  0b010..Secure privileged mode, instruction fetch access.
 *  0b011..Secure privileged mode, data access.
 *  0b100..Nonsecure user mode, instruction fetch access.
 *  0b101..Nonsecure user mode, data access.
 *  0b110..Nonsecure privileged mode, instruction fetch access.
 *  0b111..Nonsecure privileged mode, data access.
 */
#define TRDC_W1_EATR(x)                          (((uint32_t)(((uint32_t)(x)) << TRDC_W1_EATR_SHIFT)) & TRDC_W1_EATR_MASK)

#define TRDC_W1_ERW_MASK                         (0x800U)
#define TRDC_W1_ERW_SHIFT                        (11U)
/*! ERW - Error read/write
 *  0b0..Read access
 *  0b1..Write access
 */
#define TRDC_W1_ERW(x)                           (((uint32_t)(((uint32_t)(x)) << TRDC_W1_ERW_SHIFT)) & TRDC_W1_ERW_MASK)

#define TRDC_W1_EPORT_MASK                       (0x7000000U)
#define TRDC_W1_EPORT_SHIFT                      (24U)
/*! EPORT - Error port
 */
#define TRDC_W1_EPORT(x)                         (((uint32_t)(((uint32_t)(x)) << TRDC_W1_EPORT_SHIFT)) & TRDC_W1_EPORT_MASK)

#define TRDC_W1_EST_MASK                         (0xC0000000U)
#define TRDC_W1_EST_SHIFT                        (30U)
/*! EST - Error state
 *  0b00..No access violation has been detected.
 *  0b01..No access violation has been detected.
 *  0b10..A single access violation has been detected.
 *  0b11..Multiple access violations for this domain have been detected by this submodule instance. Only the
 *        address and attribute information for the first error have been captured in DERR_W0_i and DERR_W1_i.
 */
#define TRDC_W1_EST(x)                           (((uint32_t)(((uint32_t)(x)) << TRDC_W1_EST_SHIFT)) & TRDC_W1_EST_MASK)
/*! @} */

/* The count of TRDC_W1 */
#define TRDC_MRC_DERR_W1_COUNT                   (1U)

/*! @name W3 - MRC Domain Error Word3 Register */
/*! @{ */

#define TRDC_W3_RECR_MASK                        (0xC0000000U)
#define TRDC_W3_RECR_SHIFT                       (30U)
/*! RECR - Rearm Error Capture Registers
 */
#define TRDC_W3_RECR(x)                          (((uint32_t)(((uint32_t)(x)) << TRDC_W3_RECR_SHIFT)) & TRDC_W3_RECR_MASK)
/*! @} */

/* The count of TRDC_W3 */
#define TRDC_MRC_DERR_W3_COUNT                   (1U)

/*! @name MDA_W0_0_DFMT0 - DAC Master Domain Assignment Register */
/*! @{ */

#define TRDC_MDA_W0_0_DFMT0_DID_MASK             (0xFU)
#define TRDC_MDA_W0_0_DFMT0_DID_SHIFT            (0U)
/*! DID - Domain identifier
 */
#define TRDC_MDA_W0_0_DFMT0_DID(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W0_0_DFMT0_DID_SHIFT)) & TRDC_MDA_W0_0_DFMT0_DID_MASK)

#define TRDC_MDA_W0_0_DFMT0_DIDS_MASK            (0x30U)
#define TRDC_MDA_W0_0_DFMT0_DIDS_SHIFT           (4U)
/*! DIDS - DID Select
 *  0b00..Use MDAm[3:0] as the domain identifier.
 *  0b01..Use the input DID as the domain identifier.
 *  0b10..Use MDAm[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier.
 *  0b11..Reserved for future use.
 */
#define TRDC_MDA_W0_0_DFMT0_DIDS(x)              (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W0_0_DFMT0_DIDS_SHIFT)) & TRDC_MDA_W0_0_DFMT0_DIDS_MASK)

#define TRDC_MDA_W0_0_DFMT0_DFMT_MASK            (0x20000000U)
#define TRDC_MDA_W0_0_DFMT0_DFMT_SHIFT           (29U)
/*! DFMT - Domain format
 *  0b0..Processor-core domain assignment
 *  0b1..Non-processor domain assignment
 */
#define TRDC_MDA_W0_0_DFMT0_DFMT(x)              (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W0_0_DFMT0_DFMT_SHIFT)) & TRDC_MDA_W0_0_DFMT0_DFMT_MASK)

#define TRDC_MDA_W0_0_DFMT0_LK1_MASK             (0x40000000U)
#define TRDC_MDA_W0_0_DFMT0_LK1_SHIFT            (30U)
/*! LK1 - 1-bit Lock
 *  0b0..Register can be written by any secure privileged write.
 *  0b1..Register is locked (read-only) until the next reset.
 */
#define TRDC_MDA_W0_0_DFMT0_LK1(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W0_0_DFMT0_LK1_SHIFT)) & TRDC_MDA_W0_0_DFMT0_LK1_MASK)

#define TRDC_MDA_W0_0_DFMT0_VLD_MASK             (0x80000000U)
#define TRDC_MDA_W0_0_DFMT0_VLD_SHIFT            (31U)
/*! VLD - Valid
 *  0b0..The Wr domain assignment is invalid.
 *  0b1..The Wr domain assignment is valid.
 */
#define TRDC_MDA_W0_0_DFMT0_VLD(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W0_0_DFMT0_VLD_SHIFT)) & TRDC_MDA_W0_0_DFMT0_VLD_MASK)
/*! @} */

/*! @name MDA_W0_x_DFMT1 - DAC Master Domain Assignment Register */
/*! @{ */

#define TRDC_MDA_W0_x_DFMT1_DID_MASK             (0xFU)
#define TRDC_MDA_W0_x_DFMT1_DID_SHIFT            (0U)
/*! DID - Domain identifier
 */
#define TRDC_MDA_W0_x_DFMT1_DID(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W0_x_DFMT1_DID_SHIFT)) & TRDC_MDA_W0_x_DFMT1_DID_MASK)

#define TRDC_MDA_W0_x_DFMT1_PA_MASK              (0x30U)
#define TRDC_MDA_W0_x_DFMT1_PA_SHIFT             (4U)
/*! PA - Privileged attribute
 *  0b00..Force the bus attribute for this master to user.
 *  0b01..Force the bus attribute for this master to privileged.
 *  0b10..Use the bus master's privileged/user attribute directly.
 *  0b11..Use the bus master's privileged/user attribute directly.
 */
#define TRDC_MDA_W0_x_DFMT1_PA(x)                (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W0_x_DFMT1_PA_SHIFT)) & TRDC_MDA_W0_x_DFMT1_PA_MASK)

#define TRDC_MDA_W0_x_DFMT1_SA_MASK              (0xC0U)
#define TRDC_MDA_W0_x_DFMT1_SA_SHIFT             (6U)
/*! SA - Secure attribute
 *  0b00..Force the bus attribute for this master to secure.
 *  0b01..Force the bus attribute for this master to nonsecure.
 *  0b10..Use the bus master's secure/nonsecure attribute directly.
 *  0b11..Use the bus master's secure/nonsecure attribute directly.
 */
#define TRDC_MDA_W0_x_DFMT1_SA(x)                (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W0_x_DFMT1_SA_SHIFT)) & TRDC_MDA_W0_x_DFMT1_SA_MASK)

#define TRDC_MDA_W0_x_DFMT1_DIDB_MASK            (0x100U)
#define TRDC_MDA_W0_x_DFMT1_DIDB_SHIFT           (8U)
/*! DIDB - DID Bypass
 *  0b0..Use MDAn[3:0] as the domain identifier.
 *  0b1..Use the DID input as the domain identifier.
 */
#define TRDC_MDA_W0_x_DFMT1_DIDB(x)              (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W0_x_DFMT1_DIDB_SHIFT)) & TRDC_MDA_W0_x_DFMT1_DIDB_MASK)

#define TRDC_MDA_W0_x_DFMT1_DFMT_MASK            (0x20000000U)
#define TRDC_MDA_W0_x_DFMT1_DFMT_SHIFT           (29U)
/*! DFMT - Domain format
 *  0b0..Processor-core domain assignment
 *  0b1..Non-processor domain assignment
 */
#define TRDC_MDA_W0_x_DFMT1_DFMT(x)              (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W0_x_DFMT1_DFMT_SHIFT)) & TRDC_MDA_W0_x_DFMT1_DFMT_MASK)

#define TRDC_MDA_W0_x_DFMT1_LK1_MASK             (0x40000000U)
#define TRDC_MDA_W0_x_DFMT1_LK1_SHIFT            (30U)
/*! LK1 - 1-bit Lock
 *  0b0..Register can be written by any secure privileged write.
 *  0b1..Register is locked (read-only) until the next reset.
 */
#define TRDC_MDA_W0_x_DFMT1_LK1(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W0_x_DFMT1_LK1_SHIFT)) & TRDC_MDA_W0_x_DFMT1_LK1_MASK)

#define TRDC_MDA_W0_x_DFMT1_VLD_MASK             (0x80000000U)
#define TRDC_MDA_W0_x_DFMT1_VLD_SHIFT            (31U)
/*! VLD - Valid
 *  0b0..The Wr domain assignment is invalid.
 *  0b1..The Wr domain assignment is valid.
 */
#define TRDC_MDA_W0_x_DFMT1_VLD(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MDA_W0_x_DFMT1_VLD_SHIFT)) & TRDC_MDA_W0_x_DFMT1_VLD_MASK)
/*! @} */

/* The count of TRDC_MDA_W0_x_DFMT1 */
#define TRDC_MDA_W0_x_DFMT1_COUNT                (3U)

/*! @name MBC_MEM_GLBCFG - MBC Global Configuration Register */
/*! @{ */

#define TRDC_MBC_MEM_GLBCFG_NBLKS_MASK           (0x3FFU)
#define TRDC_MBC_MEM_GLBCFG_NBLKS_SHIFT          (0U)
/*! NBLKS - Number of blocks in this memory
 */
#define TRDC_MBC_MEM_GLBCFG_NBLKS(x)             (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_MEM_GLBCFG_NBLKS_SHIFT)) & TRDC_MBC_MEM_GLBCFG_NBLKS_MASK)

#define TRDC_MBC_MEM_GLBCFG_SIZE_LOG2_MASK       (0x1F0000U)
#define TRDC_MBC_MEM_GLBCFG_SIZE_LOG2_SHIFT      (16U)
/*! SIZE_LOG2 - Log2 size per block
 */
#define TRDC_MBC_MEM_GLBCFG_SIZE_LOG2(x)         (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_MEM_GLBCFG_SIZE_LOG2_SHIFT)) & TRDC_MBC_MEM_GLBCFG_SIZE_LOG2_MASK)
/*! @} */

/* The count of TRDC_MBC_MEM_GLBCFG */
#define TRDC_MBC_MEM_GLBCFG_COUNT                (3U)

/* The count of TRDC_MBC_MEM_GLBCFG */
#define TRDC_MBC_MEM_GLBCFG_COUNT2               (4U)

/*! @name MBC_NSE_BLK_INDEX - MBC NonSecure Enable Block Index */
/*! @{ */

#define TRDC_MBC_NSE_BLK_INDEX_WNDX_MASK         (0x3CU)
#define TRDC_MBC_NSE_BLK_INDEX_WNDX_SHIFT        (2U)
/*! WNDX - Word index into the block NSE bitmap. It selects the BLK_NSE_Wn register, where WNDX determines the value of n.
 */
#define TRDC_MBC_NSE_BLK_INDEX_WNDX(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_INDEX_WNDX_SHIFT)) & TRDC_MBC_NSE_BLK_INDEX_WNDX_MASK)

#define TRDC_MBC_NSE_BLK_INDEX_MEM_SEL_MASK      (0xF00U)
#define TRDC_MBC_NSE_BLK_INDEX_MEM_SEL_SHIFT     (8U)
/*! MEM_SEL - Memory Select
 */
#define TRDC_MBC_NSE_BLK_INDEX_MEM_SEL(x)        (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_INDEX_MEM_SEL_SHIFT)) & TRDC_MBC_NSE_BLK_INDEX_MEM_SEL_MASK)

#define TRDC_MBC_NSE_BLK_INDEX_DID_SEL0_MASK     (0x10000U)
#define TRDC_MBC_NSE_BLK_INDEX_DID_SEL0_SHIFT    (16U)
/*! DID_SEL0 - DID Select
 *  0b0..No effect.
 *  0b1..Selects NSE bits for this domain.
 */
#define TRDC_MBC_NSE_BLK_INDEX_DID_SEL0(x)       (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_INDEX_DID_SEL0_SHIFT)) & TRDC_MBC_NSE_BLK_INDEX_DID_SEL0_MASK)

#define TRDC_MBC_NSE_BLK_INDEX_DID_SEL1_MASK     (0x20000U)
#define TRDC_MBC_NSE_BLK_INDEX_DID_SEL1_SHIFT    (17U)
/*! DID_SEL1 - DID Select
 *  0b0..No effect.
 *  0b1..Selects NSE bits for this domain.
 */
#define TRDC_MBC_NSE_BLK_INDEX_DID_SEL1(x)       (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_INDEX_DID_SEL1_SHIFT)) & TRDC_MBC_NSE_BLK_INDEX_DID_SEL1_MASK)

#define TRDC_MBC_NSE_BLK_INDEX_DID_SEL2_MASK     (0x40000U)
#define TRDC_MBC_NSE_BLK_INDEX_DID_SEL2_SHIFT    (18U)
/*! DID_SEL2 - DID Select
 *  0b0..No effect.
 *  0b1..Selects NSE bits for this domain.
 */
#define TRDC_MBC_NSE_BLK_INDEX_DID_SEL2(x)       (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_INDEX_DID_SEL2_SHIFT)) & TRDC_MBC_NSE_BLK_INDEX_DID_SEL2_MASK)

#define TRDC_MBC_NSE_BLK_INDEX_AI_MASK           (0x80000000U)
#define TRDC_MBC_NSE_BLK_INDEX_AI_SHIFT          (31U)
/*! AI - Auto Increment
 *  0b0..No effect.
 *  0b1..Add 1 to the WNDX field after the register write.
 */
#define TRDC_MBC_NSE_BLK_INDEX_AI(x)             (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_INDEX_AI_SHIFT)) & TRDC_MBC_NSE_BLK_INDEX_AI_MASK)
/*! @} */

/* The count of TRDC_MBC_NSE_BLK_INDEX */
#define TRDC_MBC_NSE_BLK_INDEX_COUNT             (3U)

/*! @name MBC_NSE_BLK_SET - MBC NonSecure Enable Block Set */
/*! @{ */

#define TRDC_MBC_NSE_BLK_SET_W1SET_MASK          (0xFFFFFFFFU)
#define TRDC_MBC_NSE_BLK_SET_W1SET_SHIFT         (0U)
/*! W1SET - Write-1 Set
 */
#define TRDC_MBC_NSE_BLK_SET_W1SET(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_SET_W1SET_SHIFT)) & TRDC_MBC_NSE_BLK_SET_W1SET_MASK)
/*! @} */

/* The count of TRDC_MBC_NSE_BLK_SET */
#define TRDC_MBC_NSE_BLK_SET_COUNT               (3U)

/*! @name MBC_NSE_BLK_CLR - MBC NonSecure Enable Block Clear */
/*! @{ */

#define TRDC_MBC_NSE_BLK_CLR_W1CLR_MASK          (0xFFFFFFFFU)
#define TRDC_MBC_NSE_BLK_CLR_W1CLR_SHIFT         (0U)
/*! W1CLR - Write-1 Clear
 */
#define TRDC_MBC_NSE_BLK_CLR_W1CLR(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_CLR_W1CLR_SHIFT)) & TRDC_MBC_NSE_BLK_CLR_W1CLR_MASK)
/*! @} */

/* The count of TRDC_MBC_NSE_BLK_CLR */
#define TRDC_MBC_NSE_BLK_CLR_COUNT               (3U)

/*! @name MBC_NSE_BLK_CLR_ALL - MBC NonSecure Enable Block Clear All */
/*! @{ */

#define TRDC_MBC_NSE_BLK_CLR_ALL_MEMSEL_MASK     (0xF00U)
#define TRDC_MBC_NSE_BLK_CLR_ALL_MEMSEL_SHIFT    (8U)
/*! MEMSEL - Memory Select
 */
#define TRDC_MBC_NSE_BLK_CLR_ALL_MEMSEL(x)       (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_CLR_ALL_MEMSEL_SHIFT)) & TRDC_MBC_NSE_BLK_CLR_ALL_MEMSEL_MASK)

#define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL_MASK    (0x70000U)
#define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL_SHIFT   (16U)
/*! DID_SEL - DID Select
 *  0b000..No effect.
 *  0b001..Clear all NSE bits for this domain.
 */
#define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL(x)      (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL_SHIFT)) & TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL_MASK)
/*! @} */

/* The count of TRDC_MBC_NSE_BLK_CLR_ALL */
#define TRDC_MBC_NSE_BLK_CLR_ALL_COUNT           (3U)

/*! @name MBC_MEMN_GLBAC - MBC Global Access Control */
/*! @{ */

#define TRDC_MBC_MEMN_GLBAC_NUX_MASK             (0x1U)
#define TRDC_MBC_MEMN_GLBAC_NUX_SHIFT            (0U)
/*! NUX - NonsecureUser Execute
 *  0b0..Execute access is not allowed in Nonsecure User mode.
 *  0b1..Execute access is allowed in Nonsecure User mode.
 */
#define TRDC_MBC_MEMN_GLBAC_NUX(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_MEMN_GLBAC_NUX_SHIFT)) & TRDC_MBC_MEMN_GLBAC_NUX_MASK)

#define TRDC_MBC_MEMN_GLBAC_NUW_MASK             (0x2U)
#define TRDC_MBC_MEMN_GLBAC_NUW_SHIFT            (1U)
/*! NUW - NonsecureUser Write
 *  0b0..Write access is not allowed in Nonsecure User mode.
 *  0b1..Write access is allowed in Nonsecure User mode.
 */
#define TRDC_MBC_MEMN_GLBAC_NUW(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_MEMN_GLBAC_NUW_SHIFT)) & TRDC_MBC_MEMN_GLBAC_NUW_MASK)

#define TRDC_MBC_MEMN_GLBAC_NUR_MASK             (0x4U)
#define TRDC_MBC_MEMN_GLBAC_NUR_SHIFT            (2U)
/*! NUR - NonsecureUser Read
 *  0b0..Read access is not allowed in Nonsecure User mode.
 *  0b1..Read access is allowed in Nonsecure User mode.
 */
#define TRDC_MBC_MEMN_GLBAC_NUR(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_MEMN_GLBAC_NUR_SHIFT)) & TRDC_MBC_MEMN_GLBAC_NUR_MASK)

#define TRDC_MBC_MEMN_GLBAC_NPX_MASK             (0x10U)
#define TRDC_MBC_MEMN_GLBAC_NPX_SHIFT            (4U)
/*! NPX - NonsecurePriv Execute
 *  0b0..Execute access is not allowed in Nonsecure Privilege mode.
 *  0b1..Execute access is allowed in Nonsecure Privilege mode.
 */
#define TRDC_MBC_MEMN_GLBAC_NPX(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_MEMN_GLBAC_NPX_SHIFT)) & TRDC_MBC_MEMN_GLBAC_NPX_MASK)

#define TRDC_MBC_MEMN_GLBAC_NPW_MASK             (0x20U)
#define TRDC_MBC_MEMN_GLBAC_NPW_SHIFT            (5U)
/*! NPW - NonsecurePriv Write
 *  0b0..Write access is not allowed in Nonsecure Privilege mode.
 *  0b1..Write access is allowed in Nonsecure Privilege mode.
 */
#define TRDC_MBC_MEMN_GLBAC_NPW(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_MEMN_GLBAC_NPW_SHIFT)) & TRDC_MBC_MEMN_GLBAC_NPW_MASK)

#define TRDC_MBC_MEMN_GLBAC_NPR_MASK             (0x40U)
#define TRDC_MBC_MEMN_GLBAC_NPR_SHIFT            (6U)
/*! NPR - NonsecurePriv Read
 *  0b0..Read access is not allowed in Nonsecure Privilege mode.
 *  0b1..Read access is allowed in Nonsecure Privilege mode.
 */
#define TRDC_MBC_MEMN_GLBAC_NPR(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_MEMN_GLBAC_NPR_SHIFT)) & TRDC_MBC_MEMN_GLBAC_NPR_MASK)

#define TRDC_MBC_MEMN_GLBAC_SUX_MASK             (0x100U)
#define TRDC_MBC_MEMN_GLBAC_SUX_SHIFT            (8U)
/*! SUX - SecureUser Execute
 *  0b0..Execute access is not allowed in Secure User mode.
 *  0b1..Execute access is allowed in Secure User mode.
 */
#define TRDC_MBC_MEMN_GLBAC_SUX(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_MEMN_GLBAC_SUX_SHIFT)) & TRDC_MBC_MEMN_GLBAC_SUX_MASK)

#define TRDC_MBC_MEMN_GLBAC_SUW_MASK             (0x200U)
#define TRDC_MBC_MEMN_GLBAC_SUW_SHIFT            (9U)
/*! SUW - SecureUser Write
 *  0b0..Write access is not allowed in Secure User mode.
 *  0b1..Write access is allowed in Secure User mode.
 */
#define TRDC_MBC_MEMN_GLBAC_SUW(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_MEMN_GLBAC_SUW_SHIFT)) & TRDC_MBC_MEMN_GLBAC_SUW_MASK)

#define TRDC_MBC_MEMN_GLBAC_SUR_MASK             (0x400U)
#define TRDC_MBC_MEMN_GLBAC_SUR_SHIFT            (10U)
/*! SUR - SecureUser Read
 *  0b0..Read access is not allowed in Secure User mode.
 *  0b1..Read access is allowed in Secure User mode.
 */
#define TRDC_MBC_MEMN_GLBAC_SUR(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_MEMN_GLBAC_SUR_SHIFT)) & TRDC_MBC_MEMN_GLBAC_SUR_MASK)

#define TRDC_MBC_MEMN_GLBAC_SPX_MASK             (0x1000U)
#define TRDC_MBC_MEMN_GLBAC_SPX_SHIFT            (12U)
/*! SPX - SecurePriv Execute
 *  0b0..Execute access is not allowed in Secure Privilege mode.
 *  0b1..Execute access is allowed in Secure Privilege mode.
 */
#define TRDC_MBC_MEMN_GLBAC_SPX(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_MEMN_GLBAC_SPX_SHIFT)) & TRDC_MBC_MEMN_GLBAC_SPX_MASK)

#define TRDC_MBC_MEMN_GLBAC_SPW_MASK             (0x2000U)
#define TRDC_MBC_MEMN_GLBAC_SPW_SHIFT            (13U)
/*! SPW - SecurePriv Write
 *  0b0..Write access is not allowed in Secure Privilege mode.
 *  0b1..Write access is allowed in Secure Privilege mode.
 */
#define TRDC_MBC_MEMN_GLBAC_SPW(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_MEMN_GLBAC_SPW_SHIFT)) & TRDC_MBC_MEMN_GLBAC_SPW_MASK)

#define TRDC_MBC_MEMN_GLBAC_SPR_MASK             (0x4000U)
#define TRDC_MBC_MEMN_GLBAC_SPR_SHIFT            (14U)
/*! SPR - SecurePriv Read
 *  0b0..Read access is not allowed in Secure Privilege mode.
 *  0b1..Read access is allowed in Secure Privilege mode.
 */
#define TRDC_MBC_MEMN_GLBAC_SPR(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_MEMN_GLBAC_SPR_SHIFT)) & TRDC_MBC_MEMN_GLBAC_SPR_MASK)

#define TRDC_MBC_MEMN_GLBAC_LK_MASK              (0x80000000U)
#define TRDC_MBC_MEMN_GLBAC_LK_SHIFT             (31U)
/*! LK - LOCK
 *  0b0..This register is not locked and can be altered.
 *  0b1..This register is locked and cannot be altered.
 */
#define TRDC_MBC_MEMN_GLBAC_LK(x)                (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_MEMN_GLBAC_LK_SHIFT)) & TRDC_MBC_MEMN_GLBAC_LK_MASK)
/*! @} */

/* The count of TRDC_MBC_MEMN_GLBAC */
#define TRDC_MBC_MEMN_GLBAC_COUNT                (3U)

/* The count of TRDC_MBC_MEMN_GLBAC */
#define TRDC_MBC_MEMN_GLBAC_COUNT2               (8U)

/*! @name MBC_DOM0_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */
/*! @{ */

#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U)
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U)
/*! MBACSEL0 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_MASK   (0x8U)
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_SHIFT  (3U)
/*! NSE0 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U)
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U)
/*! MBACSEL1 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_MASK   (0x80U)
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_SHIFT  (7U)
/*! NSE1 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U)
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U)
/*! MBACSEL2 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_MASK   (0x800U)
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_SHIFT  (11U)
/*! NSE2 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U)
/*! MBACSEL3 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_MASK   (0x8000U)
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_SHIFT  (15U)
/*! NSE3 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U)
/*! MBACSEL4 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_MASK   (0x80000U)
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_SHIFT  (19U)
/*! NSE4 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U)
/*! MBACSEL5 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_MASK   (0x800000U)
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_SHIFT  (23U)
/*! NSE5 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U)
/*! MBACSEL6 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_MASK   (0x8000000U)
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_SHIFT  (27U)
/*! NSE6 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U)
/*! MBACSEL7 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_MASK   (0x80000000U)
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_SHIFT  (31U)
/*! NSE7 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM0_MEM0_BLK_CFG_W */
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_COUNT       (3U)

/* The count of TRDC_MBC_DOM0_MEM0_BLK_CFG_W */
#define TRDC_MBC_DOM0_MEM0_BLK_CFG_W_COUNT2      (10U)

/*! @name MBC_DOM0_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
/*! @{ */

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_MASK   (0x1U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_SHIFT  (0U)
/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_MASK   (0x2U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_SHIFT  (1U)
/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_MASK   (0x4U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_SHIFT  (2U)
/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_MASK   (0x8U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_SHIFT  (3U)
/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_MASK   (0x10U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_SHIFT  (4U)
/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_MASK   (0x20U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_SHIFT  (5U)
/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_MASK   (0x40U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_SHIFT  (6U)
/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_MASK   (0x80U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_SHIFT  (7U)
/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_MASK   (0x100U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_SHIFT  (8U)
/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_MASK   (0x200U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_SHIFT  (9U)
/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_MASK  (0x400U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_SHIFT (10U)
/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_MASK  (0x800U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_SHIFT (11U)
/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_MASK  (0x1000U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_SHIFT (12U)
/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_MASK  (0x2000U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_SHIFT (13U)
/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_MASK  (0x4000U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_SHIFT (14U)
/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_MASK  (0x8000U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_SHIFT (15U)
/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_MASK  (0x10000U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_SHIFT (16U)
/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_MASK  (0x20000U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_SHIFT (17U)
/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_MASK  (0x40000U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_SHIFT (18U)
/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_MASK  (0x80000U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_SHIFT (19U)
/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_MASK  (0x100000U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_SHIFT (20U)
/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_MASK  (0x200000U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_SHIFT (21U)
/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_MASK  (0x400000U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_SHIFT (22U)
/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_MASK  (0x800000U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_SHIFT (23U)
/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_MASK  (0x1000000U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_SHIFT (24U)
/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_MASK  (0x2000000U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_SHIFT (25U)
/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_MASK  (0x4000000U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_SHIFT (26U)
/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_MASK  (0x8000000U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_SHIFT (27U)
/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_MASK  (0x10000000U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_SHIFT (28U)
/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_MASK  (0x20000000U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_SHIFT (29U)
/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_MASK  (0x40000000U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_SHIFT (30U)
/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_MASK)

#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_MASK  (0x80000000U)
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_SHIFT (31U)
/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM0_MEM0_BLK_NSE_W */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_COUNT       (3U)

/* The count of TRDC_MBC_DOM0_MEM0_BLK_NSE_W */
#define TRDC_MBC_DOM0_MEM0_BLK_NSE_W_COUNT2      (3U)

/*! @name MBC_DOM0_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */
/*! @{ */

#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U)
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U)
/*! MBACSEL0 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_MASK   (0x8U)
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_SHIFT  (3U)
/*! NSE0 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U)
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U)
/*! MBACSEL1 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_MASK   (0x80U)
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_SHIFT  (7U)
/*! NSE1 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U)
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U)
/*! MBACSEL2 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_MASK   (0x800U)
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_SHIFT  (11U)
/*! NSE2 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U)
/*! MBACSEL3 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_MASK   (0x8000U)
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_SHIFT  (15U)
/*! NSE3 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U)
/*! MBACSEL4 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_MASK   (0x80000U)
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_SHIFT  (19U)
/*! NSE4 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U)
/*! MBACSEL5 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_MASK   (0x800000U)
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_SHIFT  (23U)
/*! NSE5 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U)
/*! MBACSEL6 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_MASK   (0x8000000U)
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_SHIFT  (27U)
/*! NSE6 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U)
/*! MBACSEL7 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_MASK   (0x80000000U)
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_SHIFT  (31U)
/*! NSE7 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM0_MEM1_BLK_CFG_W */
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_COUNT       (3U)

/* The count of TRDC_MBC_DOM0_MEM1_BLK_CFG_W */
#define TRDC_MBC_DOM0_MEM1_BLK_CFG_W_COUNT2      (1U)

/*! @name MBC_DOM0_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
/*! @{ */

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_MASK   (0x1U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_SHIFT  (0U)
/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_MASK   (0x2U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_SHIFT  (1U)
/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_MASK   (0x4U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_SHIFT  (2U)
/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_MASK   (0x8U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_SHIFT  (3U)
/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_MASK   (0x10U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_SHIFT  (4U)
/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_MASK   (0x20U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_SHIFT  (5U)
/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_MASK   (0x40U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_SHIFT  (6U)
/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_MASK   (0x80U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_SHIFT  (7U)
/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_MASK   (0x100U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_SHIFT  (8U)
/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_MASK   (0x200U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_SHIFT  (9U)
/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_MASK  (0x400U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_SHIFT (10U)
/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_MASK  (0x800U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_SHIFT (11U)
/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_MASK  (0x1000U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_SHIFT (12U)
/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_MASK  (0x2000U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_SHIFT (13U)
/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_MASK  (0x4000U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_SHIFT (14U)
/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_MASK  (0x8000U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_SHIFT (15U)
/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_MASK  (0x10000U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_SHIFT (16U)
/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_MASK  (0x20000U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_SHIFT (17U)
/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_MASK  (0x40000U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_SHIFT (18U)
/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_MASK  (0x80000U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_SHIFT (19U)
/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_MASK  (0x100000U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_SHIFT (20U)
/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_MASK  (0x200000U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_SHIFT (21U)
/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_MASK  (0x400000U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_SHIFT (22U)
/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_MASK  (0x800000U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_SHIFT (23U)
/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_MASK  (0x1000000U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_SHIFT (24U)
/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_MASK  (0x2000000U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_SHIFT (25U)
/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_MASK  (0x4000000U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_SHIFT (26U)
/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_MASK  (0x8000000U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_SHIFT (27U)
/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_MASK  (0x10000000U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_SHIFT (28U)
/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_MASK  (0x20000000U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_SHIFT (29U)
/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_MASK  (0x40000000U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_SHIFT (30U)
/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_MASK)

#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_MASK  (0x80000000U)
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_SHIFT (31U)
/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM0_MEM1_BLK_NSE_W */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_COUNT       (3U)

/* The count of TRDC_MBC_DOM0_MEM1_BLK_NSE_W */
#define TRDC_MBC_DOM0_MEM1_BLK_NSE_W_COUNT2      (1U)

/*! @name MBC_DOM0_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */
/*! @{ */

#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U)
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U)
/*! MBACSEL0 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_MASK   (0x8U)
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_SHIFT  (3U)
/*! NSE0 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U)
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U)
/*! MBACSEL1 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_MASK   (0x80U)
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_SHIFT  (7U)
/*! NSE1 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U)
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U)
/*! MBACSEL2 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_MASK   (0x800U)
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_SHIFT  (11U)
/*! NSE2 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U)
/*! MBACSEL3 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_MASK   (0x8000U)
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_SHIFT  (15U)
/*! NSE3 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U)
/*! MBACSEL4 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_MASK   (0x80000U)
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_SHIFT  (19U)
/*! NSE4 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U)
/*! MBACSEL5 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_MASK   (0x800000U)
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_SHIFT  (23U)
/*! NSE5 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U)
/*! MBACSEL6 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_MASK   (0x8000000U)
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_SHIFT  (27U)
/*! NSE6 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U)
/*! MBACSEL7 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_MASK   (0x80000000U)
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_SHIFT  (31U)
/*! NSE7 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM0_MEM2_BLK_CFG_W */
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_COUNT       (3U)

/* The count of TRDC_MBC_DOM0_MEM2_BLK_CFG_W */
#define TRDC_MBC_DOM0_MEM2_BLK_CFG_W_COUNT2      (2U)

/*! @name MBC_DOM0_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
/*! @{ */

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_MASK   (0x1U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_SHIFT  (0U)
/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_MASK   (0x2U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_SHIFT  (1U)
/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_MASK   (0x4U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_SHIFT  (2U)
/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_MASK   (0x8U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_SHIFT  (3U)
/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_MASK   (0x10U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_SHIFT  (4U)
/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_MASK   (0x20U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_SHIFT  (5U)
/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_MASK   (0x40U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_SHIFT  (6U)
/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_MASK   (0x80U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_SHIFT  (7U)
/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_MASK   (0x100U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_SHIFT  (8U)
/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_MASK   (0x200U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_SHIFT  (9U)
/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_MASK  (0x400U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_SHIFT (10U)
/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_MASK  (0x800U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_SHIFT (11U)
/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_MASK  (0x1000U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_SHIFT (12U)
/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_MASK  (0x2000U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_SHIFT (13U)
/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_MASK  (0x4000U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_SHIFT (14U)
/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_MASK  (0x8000U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_SHIFT (15U)
/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_MASK  (0x10000U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_SHIFT (16U)
/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_MASK  (0x20000U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_SHIFT (17U)
/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_MASK  (0x40000U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_SHIFT (18U)
/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_MASK  (0x80000U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_SHIFT (19U)
/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_MASK  (0x100000U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_SHIFT (20U)
/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_MASK  (0x200000U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_SHIFT (21U)
/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_MASK  (0x400000U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_SHIFT (22U)
/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_MASK  (0x800000U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_SHIFT (23U)
/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_MASK  (0x1000000U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_SHIFT (24U)
/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_MASK  (0x2000000U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_SHIFT (25U)
/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_MASK  (0x4000000U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_SHIFT (26U)
/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_MASK  (0x8000000U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_SHIFT (27U)
/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_MASK  (0x10000000U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_SHIFT (28U)
/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_MASK  (0x20000000U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_SHIFT (29U)
/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_MASK  (0x40000000U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_SHIFT (30U)
/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_MASK)

#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_MASK  (0x80000000U)
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_SHIFT (31U)
/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM0_MEM2_BLK_NSE_W */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_COUNT       (3U)

/* The count of TRDC_MBC_DOM0_MEM2_BLK_NSE_W */
#define TRDC_MBC_DOM0_MEM2_BLK_NSE_W_COUNT2      (1U)

/*! @name MBC_DOM0_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */
/*! @{ */

#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U)
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U)
/*! MBACSEL0 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL0_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE0_MASK   (0x8U)
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE0_SHIFT  (3U)
/*! NSE0 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE0_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U)
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U)
/*! MBACSEL1 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL1_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE1_MASK   (0x80U)
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE1_SHIFT  (7U)
/*! NSE1 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE1_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U)
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U)
/*! MBACSEL2 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL2_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE2_MASK   (0x800U)
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE2_SHIFT  (11U)
/*! NSE2 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE2_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U)
/*! MBACSEL3 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL3_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE3_MASK   (0x8000U)
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE3_SHIFT  (15U)
/*! NSE3 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE3_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U)
/*! MBACSEL4 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL4_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE4_MASK   (0x80000U)
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE4_SHIFT  (19U)
/*! NSE4 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE4_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U)
/*! MBACSEL5 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL5_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE5_MASK   (0x800000U)
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE5_SHIFT  (23U)
/*! NSE5 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE5_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U)
/*! MBACSEL6 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL6_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE6_MASK   (0x8000000U)
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE6_SHIFT  (27U)
/*! NSE6 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE6_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U)
/*! MBACSEL7 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_CFG_W_MBACSEL7_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE7_MASK   (0x80000000U)
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE7_SHIFT  (31U)
/*! NSE7 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_CFG_W_NSE7_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM0_MEM3_BLK_CFG_W */
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_COUNT       (3U)

/* The count of TRDC_MBC_DOM0_MEM3_BLK_CFG_W */
#define TRDC_MBC_DOM0_MEM3_BLK_CFG_W_COUNT2      (2U)

/*! @name MBC_DOM0_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
/*! @{ */

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT0_MASK   (0x1U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT0_SHIFT  (0U)
/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT0_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT1_MASK   (0x2U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT1_SHIFT  (1U)
/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT1_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT2_MASK   (0x4U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT2_SHIFT  (2U)
/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT2_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT3_MASK   (0x8U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT3_SHIFT  (3U)
/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT3_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT4_MASK   (0x10U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT4_SHIFT  (4U)
/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT4_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT5_MASK   (0x20U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT5_SHIFT  (5U)
/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT5_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT6_MASK   (0x40U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT6_SHIFT  (6U)
/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT6_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT7_MASK   (0x80U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT7_SHIFT  (7U)
/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT7_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT8_MASK   (0x100U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT8_SHIFT  (8U)
/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT8_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT9_MASK   (0x200U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT9_SHIFT  (9U)
/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT9_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT10_MASK  (0x400U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT10_SHIFT (10U)
/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT10_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT11_MASK  (0x800U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT11_SHIFT (11U)
/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT11_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT12_MASK  (0x1000U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT12_SHIFT (12U)
/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT12_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT13_MASK  (0x2000U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT13_SHIFT (13U)
/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT13_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT14_MASK  (0x4000U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT14_SHIFT (14U)
/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT14_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT15_MASK  (0x8000U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT15_SHIFT (15U)
/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT15_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT16_MASK  (0x10000U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT16_SHIFT (16U)
/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT16_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT17_MASK  (0x20000U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT17_SHIFT (17U)
/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT17_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT18_MASK  (0x40000U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT18_SHIFT (18U)
/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT18_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT19_MASK  (0x80000U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT19_SHIFT (19U)
/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT19_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT20_MASK  (0x100000U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT20_SHIFT (20U)
/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT20_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT21_MASK  (0x200000U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT21_SHIFT (21U)
/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT21_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT22_MASK  (0x400000U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT22_SHIFT (22U)
/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT22_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT23_MASK  (0x800000U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT23_SHIFT (23U)
/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT23_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT24_MASK  (0x1000000U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT24_SHIFT (24U)
/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT24_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT25_MASK  (0x2000000U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT25_SHIFT (25U)
/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT25_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT26_MASK  (0x4000000U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT26_SHIFT (26U)
/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT26_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT27_MASK  (0x8000000U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT27_SHIFT (27U)
/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT27_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT28_MASK  (0x10000000U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT28_SHIFT (28U)
/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT28_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT29_MASK  (0x20000000U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT29_SHIFT (29U)
/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT29_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT30_MASK  (0x40000000U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT30_SHIFT (30U)
/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT30_MASK)

#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT31_MASK  (0x80000000U)
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT31_SHIFT (31U)
/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM0_MEM3_BLK_NSE_W_BIT31_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM0_MEM3_BLK_NSE_W */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_COUNT       (3U)

/* The count of TRDC_MBC_DOM0_MEM3_BLK_NSE_W */
#define TRDC_MBC_DOM0_MEM3_BLK_NSE_W_COUNT2      (1U)

/*! @name MBC_DOM1_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */
/*! @{ */

#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U)
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U)
/*! MBACSEL0 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL0_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE0_MASK   (0x8U)
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE0_SHIFT  (3U)
/*! NSE0 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE0_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U)
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U)
/*! MBACSEL1 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL1_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE1_MASK   (0x80U)
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE1_SHIFT  (7U)
/*! NSE1 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE1_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U)
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U)
/*! MBACSEL2 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL2_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE2_MASK   (0x800U)
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE2_SHIFT  (11U)
/*! NSE2 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE2_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U)
/*! MBACSEL3 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL3_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE3_MASK   (0x8000U)
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE3_SHIFT  (15U)
/*! NSE3 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE3_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U)
/*! MBACSEL4 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL4_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE4_MASK   (0x80000U)
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE4_SHIFT  (19U)
/*! NSE4 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE4_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U)
/*! MBACSEL5 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL5_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE5_MASK   (0x800000U)
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE5_SHIFT  (23U)
/*! NSE5 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE5_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U)
/*! MBACSEL6 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL6_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE6_MASK   (0x8000000U)
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE6_SHIFT  (27U)
/*! NSE6 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE6_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U)
/*! MBACSEL7 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_CFG_W_MBACSEL7_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE7_MASK   (0x80000000U)
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE7_SHIFT  (31U)
/*! NSE7 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_CFG_W_NSE7_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM1_MEM0_BLK_CFG_W */
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_COUNT       (3U)

/* The count of TRDC_MBC_DOM1_MEM0_BLK_CFG_W */
#define TRDC_MBC_DOM1_MEM0_BLK_CFG_W_COUNT2      (10U)

/*! @name MBC_DOM1_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
/*! @{ */

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT0_MASK   (0x1U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT0_SHIFT  (0U)
/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT0_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT1_MASK   (0x2U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT1_SHIFT  (1U)
/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT1_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT2_MASK   (0x4U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT2_SHIFT  (2U)
/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT2_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT3_MASK   (0x8U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT3_SHIFT  (3U)
/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT3_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT4_MASK   (0x10U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT4_SHIFT  (4U)
/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT4_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT5_MASK   (0x20U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT5_SHIFT  (5U)
/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT5_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT6_MASK   (0x40U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT6_SHIFT  (6U)
/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT6_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT7_MASK   (0x80U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT7_SHIFT  (7U)
/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT7_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT8_MASK   (0x100U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT8_SHIFT  (8U)
/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT8_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT9_MASK   (0x200U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT9_SHIFT  (9U)
/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT9_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT10_MASK  (0x400U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT10_SHIFT (10U)
/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT10_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT11_MASK  (0x800U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT11_SHIFT (11U)
/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT11_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT12_MASK  (0x1000U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT12_SHIFT (12U)
/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT12_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT13_MASK  (0x2000U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT13_SHIFT (13U)
/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT13_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT14_MASK  (0x4000U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT14_SHIFT (14U)
/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT14_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT15_MASK  (0x8000U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT15_SHIFT (15U)
/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT15_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT16_MASK  (0x10000U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT16_SHIFT (16U)
/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT16_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT17_MASK  (0x20000U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT17_SHIFT (17U)
/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT17_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT18_MASK  (0x40000U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT18_SHIFT (18U)
/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT18_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT19_MASK  (0x80000U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT19_SHIFT (19U)
/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT19_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT20_MASK  (0x100000U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT20_SHIFT (20U)
/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT20_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT21_MASK  (0x200000U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT21_SHIFT (21U)
/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT21_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT22_MASK  (0x400000U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT22_SHIFT (22U)
/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT22_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT23_MASK  (0x800000U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT23_SHIFT (23U)
/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT23_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT24_MASK  (0x1000000U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT24_SHIFT (24U)
/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT24_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT25_MASK  (0x2000000U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT25_SHIFT (25U)
/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT25_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT26_MASK  (0x4000000U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT26_SHIFT (26U)
/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT26_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT27_MASK  (0x8000000U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT27_SHIFT (27U)
/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT27_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT28_MASK  (0x10000000U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT28_SHIFT (28U)
/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT28_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT29_MASK  (0x20000000U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT29_SHIFT (29U)
/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT29_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT30_MASK  (0x40000000U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT30_SHIFT (30U)
/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT30_MASK)

#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT31_MASK  (0x80000000U)
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT31_SHIFT (31U)
/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM1_MEM0_BLK_NSE_W_BIT31_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM1_MEM0_BLK_NSE_W */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_COUNT       (3U)

/* The count of TRDC_MBC_DOM1_MEM0_BLK_NSE_W */
#define TRDC_MBC_DOM1_MEM0_BLK_NSE_W_COUNT2      (3U)

/*! @name MBC_DOM1_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */
/*! @{ */

#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U)
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U)
/*! MBACSEL0 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL0_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE0_MASK   (0x8U)
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE0_SHIFT  (3U)
/*! NSE0 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE0_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U)
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U)
/*! MBACSEL1 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL1_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE1_MASK   (0x80U)
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE1_SHIFT  (7U)
/*! NSE1 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE1_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U)
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U)
/*! MBACSEL2 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL2_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE2_MASK   (0x800U)
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE2_SHIFT  (11U)
/*! NSE2 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE2_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U)
/*! MBACSEL3 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL3_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE3_MASK   (0x8000U)
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE3_SHIFT  (15U)
/*! NSE3 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE3_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U)
/*! MBACSEL4 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL4_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE4_MASK   (0x80000U)
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE4_SHIFT  (19U)
/*! NSE4 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE4_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U)
/*! MBACSEL5 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL5_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE5_MASK   (0x800000U)
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE5_SHIFT  (23U)
/*! NSE5 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE5_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U)
/*! MBACSEL6 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL6_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE6_MASK   (0x8000000U)
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE6_SHIFT  (27U)
/*! NSE6 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE6_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U)
/*! MBACSEL7 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_CFG_W_MBACSEL7_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE7_MASK   (0x80000000U)
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE7_SHIFT  (31U)
/*! NSE7 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_CFG_W_NSE7_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM1_MEM1_BLK_CFG_W */
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_COUNT       (3U)

/* The count of TRDC_MBC_DOM1_MEM1_BLK_CFG_W */
#define TRDC_MBC_DOM1_MEM1_BLK_CFG_W_COUNT2      (1U)

/*! @name MBC_DOM1_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
/*! @{ */

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT0_MASK   (0x1U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT0_SHIFT  (0U)
/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT0_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT1_MASK   (0x2U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT1_SHIFT  (1U)
/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT1_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT2_MASK   (0x4U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT2_SHIFT  (2U)
/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT2_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT3_MASK   (0x8U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT3_SHIFT  (3U)
/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT3_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT4_MASK   (0x10U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT4_SHIFT  (4U)
/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT4_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT5_MASK   (0x20U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT5_SHIFT  (5U)
/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT5_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT6_MASK   (0x40U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT6_SHIFT  (6U)
/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT6_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT7_MASK   (0x80U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT7_SHIFT  (7U)
/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT7_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT8_MASK   (0x100U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT8_SHIFT  (8U)
/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT8_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT9_MASK   (0x200U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT9_SHIFT  (9U)
/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT9_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT10_MASK  (0x400U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT10_SHIFT (10U)
/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT10_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT11_MASK  (0x800U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT11_SHIFT (11U)
/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT11_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT12_MASK  (0x1000U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT12_SHIFT (12U)
/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT12_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT13_MASK  (0x2000U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT13_SHIFT (13U)
/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT13_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT14_MASK  (0x4000U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT14_SHIFT (14U)
/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT14_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT15_MASK  (0x8000U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT15_SHIFT (15U)
/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT15_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT16_MASK  (0x10000U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT16_SHIFT (16U)
/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT16_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT17_MASK  (0x20000U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT17_SHIFT (17U)
/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT17_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT18_MASK  (0x40000U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT18_SHIFT (18U)
/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT18_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT19_MASK  (0x80000U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT19_SHIFT (19U)
/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT19_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT20_MASK  (0x100000U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT20_SHIFT (20U)
/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT20_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT21_MASK  (0x200000U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT21_SHIFT (21U)
/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT21_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT22_MASK  (0x400000U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT22_SHIFT (22U)
/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT22_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT23_MASK  (0x800000U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT23_SHIFT (23U)
/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT23_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT24_MASK  (0x1000000U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT24_SHIFT (24U)
/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT24_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT25_MASK  (0x2000000U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT25_SHIFT (25U)
/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT25_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT26_MASK  (0x4000000U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT26_SHIFT (26U)
/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT26_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT27_MASK  (0x8000000U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT27_SHIFT (27U)
/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT27_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT28_MASK  (0x10000000U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT28_SHIFT (28U)
/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT28_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT29_MASK  (0x20000000U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT29_SHIFT (29U)
/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT29_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT30_MASK  (0x40000000U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT30_SHIFT (30U)
/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT30_MASK)

#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT31_MASK  (0x80000000U)
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT31_SHIFT (31U)
/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM1_MEM1_BLK_NSE_W_BIT31_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM1_MEM1_BLK_NSE_W */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_COUNT       (3U)

/* The count of TRDC_MBC_DOM1_MEM1_BLK_NSE_W */
#define TRDC_MBC_DOM1_MEM1_BLK_NSE_W_COUNT2      (1U)

/*! @name MBC_DOM1_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */
/*! @{ */

#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U)
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U)
/*! MBACSEL0 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL0_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE0_MASK   (0x8U)
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE0_SHIFT  (3U)
/*! NSE0 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE0_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U)
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U)
/*! MBACSEL1 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL1_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE1_MASK   (0x80U)
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE1_SHIFT  (7U)
/*! NSE1 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE1_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U)
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U)
/*! MBACSEL2 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL2_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE2_MASK   (0x800U)
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE2_SHIFT  (11U)
/*! NSE2 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE2_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U)
/*! MBACSEL3 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL3_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE3_MASK   (0x8000U)
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE3_SHIFT  (15U)
/*! NSE3 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE3_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U)
/*! MBACSEL4 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL4_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE4_MASK   (0x80000U)
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE4_SHIFT  (19U)
/*! NSE4 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE4_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U)
/*! MBACSEL5 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL5_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE5_MASK   (0x800000U)
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE5_SHIFT  (23U)
/*! NSE5 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE5_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U)
/*! MBACSEL6 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL6_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE6_MASK   (0x8000000U)
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE6_SHIFT  (27U)
/*! NSE6 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE6_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U)
/*! MBACSEL7 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_CFG_W_MBACSEL7_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE7_MASK   (0x80000000U)
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE7_SHIFT  (31U)
/*! NSE7 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_CFG_W_NSE7_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM1_MEM2_BLK_CFG_W */
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_COUNT       (3U)

/* The count of TRDC_MBC_DOM1_MEM2_BLK_CFG_W */
#define TRDC_MBC_DOM1_MEM2_BLK_CFG_W_COUNT2      (2U)

/*! @name MBC_DOM1_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
/*! @{ */

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT0_MASK   (0x1U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT0_SHIFT  (0U)
/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT0_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT1_MASK   (0x2U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT1_SHIFT  (1U)
/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT1_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT2_MASK   (0x4U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT2_SHIFT  (2U)
/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT2_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT3_MASK   (0x8U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT3_SHIFT  (3U)
/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT3_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT4_MASK   (0x10U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT4_SHIFT  (4U)
/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT4_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT5_MASK   (0x20U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT5_SHIFT  (5U)
/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT5_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT6_MASK   (0x40U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT6_SHIFT  (6U)
/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT6_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT7_MASK   (0x80U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT7_SHIFT  (7U)
/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT7_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT8_MASK   (0x100U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT8_SHIFT  (8U)
/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT8_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT9_MASK   (0x200U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT9_SHIFT  (9U)
/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT9_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT10_MASK  (0x400U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT10_SHIFT (10U)
/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT10_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT11_MASK  (0x800U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT11_SHIFT (11U)
/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT11_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT12_MASK  (0x1000U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT12_SHIFT (12U)
/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT12_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT13_MASK  (0x2000U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT13_SHIFT (13U)
/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT13_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT14_MASK  (0x4000U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT14_SHIFT (14U)
/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT14_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT15_MASK  (0x8000U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT15_SHIFT (15U)
/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT15_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT16_MASK  (0x10000U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT16_SHIFT (16U)
/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT16_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT17_MASK  (0x20000U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT17_SHIFT (17U)
/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT17_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT18_MASK  (0x40000U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT18_SHIFT (18U)
/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT18_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT19_MASK  (0x80000U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT19_SHIFT (19U)
/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT19_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT20_MASK  (0x100000U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT20_SHIFT (20U)
/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT20_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT21_MASK  (0x200000U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT21_SHIFT (21U)
/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT21_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT22_MASK  (0x400000U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT22_SHIFT (22U)
/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT22_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT23_MASK  (0x800000U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT23_SHIFT (23U)
/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT23_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT24_MASK  (0x1000000U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT24_SHIFT (24U)
/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT24_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT25_MASK  (0x2000000U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT25_SHIFT (25U)
/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT25_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT26_MASK  (0x4000000U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT26_SHIFT (26U)
/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT26_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT27_MASK  (0x8000000U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT27_SHIFT (27U)
/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT27_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT28_MASK  (0x10000000U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT28_SHIFT (28U)
/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT28_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT29_MASK  (0x20000000U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT29_SHIFT (29U)
/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT29_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT30_MASK  (0x40000000U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT30_SHIFT (30U)
/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT30_MASK)

#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT31_MASK  (0x80000000U)
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT31_SHIFT (31U)
/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM1_MEM2_BLK_NSE_W_BIT31_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM1_MEM2_BLK_NSE_W */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_COUNT       (3U)

/* The count of TRDC_MBC_DOM1_MEM2_BLK_NSE_W */
#define TRDC_MBC_DOM1_MEM2_BLK_NSE_W_COUNT2      (1U)

/*! @name MBC_DOM1_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */
/*! @{ */

#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U)
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U)
/*! MBACSEL0 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL0_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE0_MASK   (0x8U)
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE0_SHIFT  (3U)
/*! NSE0 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE0_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U)
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U)
/*! MBACSEL1 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL1_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE1_MASK   (0x80U)
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE1_SHIFT  (7U)
/*! NSE1 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE1_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U)
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U)
/*! MBACSEL2 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL2_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE2_MASK   (0x800U)
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE2_SHIFT  (11U)
/*! NSE2 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE2_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U)
/*! MBACSEL3 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL3_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE3_MASK   (0x8000U)
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE3_SHIFT  (15U)
/*! NSE3 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE3_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U)
/*! MBACSEL4 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL4_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE4_MASK   (0x80000U)
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE4_SHIFT  (19U)
/*! NSE4 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE4_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U)
/*! MBACSEL5 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL5_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE5_MASK   (0x800000U)
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE5_SHIFT  (23U)
/*! NSE5 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE5_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U)
/*! MBACSEL6 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL6_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE6_MASK   (0x8000000U)
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE6_SHIFT  (27U)
/*! NSE6 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE6_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U)
/*! MBACSEL7 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_CFG_W_MBACSEL7_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE7_MASK   (0x80000000U)
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE7_SHIFT  (31U)
/*! NSE7 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_CFG_W_NSE7_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM1_MEM3_BLK_CFG_W */
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_COUNT       (3U)

/* The count of TRDC_MBC_DOM1_MEM3_BLK_CFG_W */
#define TRDC_MBC_DOM1_MEM3_BLK_CFG_W_COUNT2      (2U)

/*! @name MBC_DOM1_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
/*! @{ */

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT0_MASK   (0x1U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT0_SHIFT  (0U)
/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT0_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT1_MASK   (0x2U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT1_SHIFT  (1U)
/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT1_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT2_MASK   (0x4U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT2_SHIFT  (2U)
/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT2_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT3_MASK   (0x8U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT3_SHIFT  (3U)
/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT3_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT4_MASK   (0x10U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT4_SHIFT  (4U)
/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT4_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT5_MASK   (0x20U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT5_SHIFT  (5U)
/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT5_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT6_MASK   (0x40U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT6_SHIFT  (6U)
/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT6_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT7_MASK   (0x80U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT7_SHIFT  (7U)
/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT7_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT8_MASK   (0x100U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT8_SHIFT  (8U)
/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT8_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT9_MASK   (0x200U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT9_SHIFT  (9U)
/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT9_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT10_MASK  (0x400U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT10_SHIFT (10U)
/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT10_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT11_MASK  (0x800U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT11_SHIFT (11U)
/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT11_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT12_MASK  (0x1000U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT12_SHIFT (12U)
/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT12_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT13_MASK  (0x2000U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT13_SHIFT (13U)
/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT13_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT14_MASK  (0x4000U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT14_SHIFT (14U)
/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT14_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT15_MASK  (0x8000U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT15_SHIFT (15U)
/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT15_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT16_MASK  (0x10000U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT16_SHIFT (16U)
/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT16_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT17_MASK  (0x20000U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT17_SHIFT (17U)
/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT17_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT18_MASK  (0x40000U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT18_SHIFT (18U)
/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT18_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT19_MASK  (0x80000U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT19_SHIFT (19U)
/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT19_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT20_MASK  (0x100000U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT20_SHIFT (20U)
/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT20_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT21_MASK  (0x200000U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT21_SHIFT (21U)
/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT21_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT22_MASK  (0x400000U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT22_SHIFT (22U)
/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT22_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT23_MASK  (0x800000U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT23_SHIFT (23U)
/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT23_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT24_MASK  (0x1000000U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT24_SHIFT (24U)
/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT24_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT25_MASK  (0x2000000U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT25_SHIFT (25U)
/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT25_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT26_MASK  (0x4000000U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT26_SHIFT (26U)
/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT26_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT27_MASK  (0x8000000U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT27_SHIFT (27U)
/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT27_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT28_MASK  (0x10000000U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT28_SHIFT (28U)
/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT28_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT29_MASK  (0x20000000U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT29_SHIFT (29U)
/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT29_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT30_MASK  (0x40000000U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT30_SHIFT (30U)
/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT30_MASK)

#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT31_MASK  (0x80000000U)
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT31_SHIFT (31U)
/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM1_MEM3_BLK_NSE_W_BIT31_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM1_MEM3_BLK_NSE_W */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_COUNT       (3U)

/* The count of TRDC_MBC_DOM1_MEM3_BLK_NSE_W */
#define TRDC_MBC_DOM1_MEM3_BLK_NSE_W_COUNT2      (1U)

/*! @name MBC_DOM2_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */
/*! @{ */

#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U)
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U)
/*! MBACSEL0 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL0_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE0_MASK   (0x8U)
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE0_SHIFT  (3U)
/*! NSE0 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE0_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U)
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U)
/*! MBACSEL1 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL1_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE1_MASK   (0x80U)
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE1_SHIFT  (7U)
/*! NSE1 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE1_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U)
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U)
/*! MBACSEL2 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL2_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE2_MASK   (0x800U)
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE2_SHIFT  (11U)
/*! NSE2 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE2_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U)
/*! MBACSEL3 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL3_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE3_MASK   (0x8000U)
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE3_SHIFT  (15U)
/*! NSE3 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE3_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U)
/*! MBACSEL4 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL4_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE4_MASK   (0x80000U)
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE4_SHIFT  (19U)
/*! NSE4 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE4_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U)
/*! MBACSEL5 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL5_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE5_MASK   (0x800000U)
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE5_SHIFT  (23U)
/*! NSE5 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE5_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U)
/*! MBACSEL6 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL6_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE6_MASK   (0x8000000U)
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE6_SHIFT  (27U)
/*! NSE6 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE6_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U)
/*! MBACSEL7 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_CFG_W_MBACSEL7_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE7_MASK   (0x80000000U)
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE7_SHIFT  (31U)
/*! NSE7 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_CFG_W_NSE7_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM2_MEM0_BLK_CFG_W */
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_COUNT       (3U)

/* The count of TRDC_MBC_DOM2_MEM0_BLK_CFG_W */
#define TRDC_MBC_DOM2_MEM0_BLK_CFG_W_COUNT2      (10U)

/*! @name MBC_DOM2_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
/*! @{ */

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT0_MASK   (0x1U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT0_SHIFT  (0U)
/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT0_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT1_MASK   (0x2U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT1_SHIFT  (1U)
/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT1_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT2_MASK   (0x4U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT2_SHIFT  (2U)
/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT2_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT3_MASK   (0x8U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT3_SHIFT  (3U)
/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT3_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT4_MASK   (0x10U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT4_SHIFT  (4U)
/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT4_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT5_MASK   (0x20U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT5_SHIFT  (5U)
/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT5_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT6_MASK   (0x40U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT6_SHIFT  (6U)
/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT6_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT7_MASK   (0x80U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT7_SHIFT  (7U)
/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT7_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT8_MASK   (0x100U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT8_SHIFT  (8U)
/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT8_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT9_MASK   (0x200U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT9_SHIFT  (9U)
/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT9_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT10_MASK  (0x400U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT10_SHIFT (10U)
/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT10_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT11_MASK  (0x800U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT11_SHIFT (11U)
/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT11_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT12_MASK  (0x1000U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT12_SHIFT (12U)
/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT12_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT13_MASK  (0x2000U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT13_SHIFT (13U)
/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT13_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT14_MASK  (0x4000U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT14_SHIFT (14U)
/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT14_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT15_MASK  (0x8000U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT15_SHIFT (15U)
/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT15_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT16_MASK  (0x10000U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT16_SHIFT (16U)
/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT16_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT17_MASK  (0x20000U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT17_SHIFT (17U)
/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT17_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT18_MASK  (0x40000U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT18_SHIFT (18U)
/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT18_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT19_MASK  (0x80000U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT19_SHIFT (19U)
/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT19_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT20_MASK  (0x100000U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT20_SHIFT (20U)
/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT20_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT21_MASK  (0x200000U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT21_SHIFT (21U)
/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT21_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT22_MASK  (0x400000U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT22_SHIFT (22U)
/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT22_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT23_MASK  (0x800000U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT23_SHIFT (23U)
/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT23_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT24_MASK  (0x1000000U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT24_SHIFT (24U)
/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT24_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT25_MASK  (0x2000000U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT25_SHIFT (25U)
/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT25_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT26_MASK  (0x4000000U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT26_SHIFT (26U)
/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT26_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT27_MASK  (0x8000000U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT27_SHIFT (27U)
/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT27_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT28_MASK  (0x10000000U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT28_SHIFT (28U)
/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT28_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT29_MASK  (0x20000000U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT29_SHIFT (29U)
/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT29_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT30_MASK  (0x40000000U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT30_SHIFT (30U)
/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT30_MASK)

#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT31_MASK  (0x80000000U)
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT31_SHIFT (31U)
/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM2_MEM0_BLK_NSE_W_BIT31_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM2_MEM0_BLK_NSE_W */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_COUNT       (3U)

/* The count of TRDC_MBC_DOM2_MEM0_BLK_NSE_W */
#define TRDC_MBC_DOM2_MEM0_BLK_NSE_W_COUNT2      (3U)

/*! @name MBC_DOM2_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */
/*! @{ */

#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U)
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U)
/*! MBACSEL0 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL0_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE0_MASK   (0x8U)
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE0_SHIFT  (3U)
/*! NSE0 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE0_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U)
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U)
/*! MBACSEL1 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL1_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE1_MASK   (0x80U)
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE1_SHIFT  (7U)
/*! NSE1 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE1_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U)
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U)
/*! MBACSEL2 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL2_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE2_MASK   (0x800U)
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE2_SHIFT  (11U)
/*! NSE2 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE2_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U)
/*! MBACSEL3 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL3_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE3_MASK   (0x8000U)
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE3_SHIFT  (15U)
/*! NSE3 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE3_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U)
/*! MBACSEL4 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL4_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE4_MASK   (0x80000U)
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE4_SHIFT  (19U)
/*! NSE4 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE4_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U)
/*! MBACSEL5 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL5_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE5_MASK   (0x800000U)
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE5_SHIFT  (23U)
/*! NSE5 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE5_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U)
/*! MBACSEL6 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL6_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE6_MASK   (0x8000000U)
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE6_SHIFT  (27U)
/*! NSE6 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE6_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U)
/*! MBACSEL7 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_CFG_W_MBACSEL7_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE7_MASK   (0x80000000U)
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE7_SHIFT  (31U)
/*! NSE7 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_CFG_W_NSE7_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM2_MEM1_BLK_CFG_W */
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_COUNT       (3U)

/* The count of TRDC_MBC_DOM2_MEM1_BLK_CFG_W */
#define TRDC_MBC_DOM2_MEM1_BLK_CFG_W_COUNT2      (1U)

/*! @name MBC_DOM2_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
/*! @{ */

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT0_MASK   (0x1U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT0_SHIFT  (0U)
/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT0_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT1_MASK   (0x2U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT1_SHIFT  (1U)
/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT1_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT2_MASK   (0x4U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT2_SHIFT  (2U)
/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT2_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT3_MASK   (0x8U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT3_SHIFT  (3U)
/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT3_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT4_MASK   (0x10U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT4_SHIFT  (4U)
/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT4_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT5_MASK   (0x20U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT5_SHIFT  (5U)
/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT5_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT6_MASK   (0x40U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT6_SHIFT  (6U)
/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT6_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT7_MASK   (0x80U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT7_SHIFT  (7U)
/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT7_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT8_MASK   (0x100U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT8_SHIFT  (8U)
/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT8_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT9_MASK   (0x200U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT9_SHIFT  (9U)
/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT9_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT10_MASK  (0x400U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT10_SHIFT (10U)
/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT10_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT11_MASK  (0x800U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT11_SHIFT (11U)
/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT11_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT12_MASK  (0x1000U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT12_SHIFT (12U)
/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT12_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT13_MASK  (0x2000U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT13_SHIFT (13U)
/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT13_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT14_MASK  (0x4000U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT14_SHIFT (14U)
/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT14_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT15_MASK  (0x8000U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT15_SHIFT (15U)
/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT15_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT16_MASK  (0x10000U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT16_SHIFT (16U)
/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT16_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT17_MASK  (0x20000U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT17_SHIFT (17U)
/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT17_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT18_MASK  (0x40000U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT18_SHIFT (18U)
/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT18_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT19_MASK  (0x80000U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT19_SHIFT (19U)
/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT19_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT20_MASK  (0x100000U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT20_SHIFT (20U)
/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT20_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT21_MASK  (0x200000U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT21_SHIFT (21U)
/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT21_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT22_MASK  (0x400000U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT22_SHIFT (22U)
/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT22_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT23_MASK  (0x800000U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT23_SHIFT (23U)
/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT23_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT24_MASK  (0x1000000U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT24_SHIFT (24U)
/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT24_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT25_MASK  (0x2000000U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT25_SHIFT (25U)
/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT25_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT26_MASK  (0x4000000U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT26_SHIFT (26U)
/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT26_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT27_MASK  (0x8000000U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT27_SHIFT (27U)
/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT27_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT28_MASK  (0x10000000U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT28_SHIFT (28U)
/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT28_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT29_MASK  (0x20000000U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT29_SHIFT (29U)
/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT29_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT30_MASK  (0x40000000U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT30_SHIFT (30U)
/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT30_MASK)

#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT31_MASK  (0x80000000U)
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT31_SHIFT (31U)
/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM2_MEM1_BLK_NSE_W_BIT31_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM2_MEM1_BLK_NSE_W */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_COUNT       (3U)

/* The count of TRDC_MBC_DOM2_MEM1_BLK_NSE_W */
#define TRDC_MBC_DOM2_MEM1_BLK_NSE_W_COUNT2      (1U)

/*! @name MBC_DOM2_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */
/*! @{ */

#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U)
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U)
/*! MBACSEL0 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL0_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE0_MASK   (0x8U)
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE0_SHIFT  (3U)
/*! NSE0 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE0_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U)
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U)
/*! MBACSEL1 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL1_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE1_MASK   (0x80U)
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE1_SHIFT  (7U)
/*! NSE1 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE1_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U)
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U)
/*! MBACSEL2 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL2_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE2_MASK   (0x800U)
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE2_SHIFT  (11U)
/*! NSE2 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE2_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U)
/*! MBACSEL3 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL3_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE3_MASK   (0x8000U)
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE3_SHIFT  (15U)
/*! NSE3 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE3_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U)
/*! MBACSEL4 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL4_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE4_MASK   (0x80000U)
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE4_SHIFT  (19U)
/*! NSE4 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE4_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U)
/*! MBACSEL5 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL5_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE5_MASK   (0x800000U)
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE5_SHIFT  (23U)
/*! NSE5 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE5_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U)
/*! MBACSEL6 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL6_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE6_MASK   (0x8000000U)
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE6_SHIFT  (27U)
/*! NSE6 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE6_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U)
/*! MBACSEL7 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_CFG_W_MBACSEL7_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE7_MASK   (0x80000000U)
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE7_SHIFT  (31U)
/*! NSE7 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_CFG_W_NSE7_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM2_MEM2_BLK_CFG_W */
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_COUNT       (3U)

/* The count of TRDC_MBC_DOM2_MEM2_BLK_CFG_W */
#define TRDC_MBC_DOM2_MEM2_BLK_CFG_W_COUNT2      (2U)

/*! @name MBC_DOM2_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
/*! @{ */

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT0_MASK   (0x1U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT0_SHIFT  (0U)
/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT0_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT1_MASK   (0x2U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT1_SHIFT  (1U)
/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT1_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT2_MASK   (0x4U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT2_SHIFT  (2U)
/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT2_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT3_MASK   (0x8U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT3_SHIFT  (3U)
/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT3_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT4_MASK   (0x10U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT4_SHIFT  (4U)
/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT4_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT5_MASK   (0x20U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT5_SHIFT  (5U)
/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT5_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT6_MASK   (0x40U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT6_SHIFT  (6U)
/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT6_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT7_MASK   (0x80U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT7_SHIFT  (7U)
/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT7_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT8_MASK   (0x100U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT8_SHIFT  (8U)
/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT8_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT9_MASK   (0x200U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT9_SHIFT  (9U)
/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT9_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT10_MASK  (0x400U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT10_SHIFT (10U)
/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT10_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT11_MASK  (0x800U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT11_SHIFT (11U)
/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT11_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT12_MASK  (0x1000U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT12_SHIFT (12U)
/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT12_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT13_MASK  (0x2000U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT13_SHIFT (13U)
/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT13_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT14_MASK  (0x4000U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT14_SHIFT (14U)
/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT14_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT15_MASK  (0x8000U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT15_SHIFT (15U)
/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT15_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT16_MASK  (0x10000U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT16_SHIFT (16U)
/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT16_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT17_MASK  (0x20000U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT17_SHIFT (17U)
/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT17_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT18_MASK  (0x40000U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT18_SHIFT (18U)
/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT18_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT19_MASK  (0x80000U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT19_SHIFT (19U)
/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT19_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT20_MASK  (0x100000U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT20_SHIFT (20U)
/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT20_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT21_MASK  (0x200000U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT21_SHIFT (21U)
/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT21_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT22_MASK  (0x400000U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT22_SHIFT (22U)
/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT22_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT23_MASK  (0x800000U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT23_SHIFT (23U)
/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT23_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT24_MASK  (0x1000000U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT24_SHIFT (24U)
/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT24_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT25_MASK  (0x2000000U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT25_SHIFT (25U)
/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT25_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT26_MASK  (0x4000000U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT26_SHIFT (26U)
/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT26_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT27_MASK  (0x8000000U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT27_SHIFT (27U)
/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT27_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT28_MASK  (0x10000000U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT28_SHIFT (28U)
/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT28_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT29_MASK  (0x20000000U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT29_SHIFT (29U)
/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT29_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT30_MASK  (0x40000000U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT30_SHIFT (30U)
/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT30_MASK)

#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT31_MASK  (0x80000000U)
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT31_SHIFT (31U)
/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM2_MEM2_BLK_NSE_W_BIT31_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM2_MEM2_BLK_NSE_W */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_COUNT       (3U)

/* The count of TRDC_MBC_DOM2_MEM2_BLK_NSE_W */
#define TRDC_MBC_DOM2_MEM2_BLK_NSE_W_COUNT2      (1U)

/*! @name MBC_DOM2_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */
/*! @{ */

#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL0_MASK (0x7U)
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL0_SHIFT (0U)
/*! MBACSEL0 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL0_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE0_MASK   (0x8U)
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE0_SHIFT  (3U)
/*! NSE0 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE0_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL1_MASK (0x70U)
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL1_SHIFT (4U)
/*! MBACSEL1 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL1_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE1_MASK   (0x80U)
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE1_SHIFT  (7U)
/*! NSE1 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE1_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL2_MASK (0x700U)
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL2_SHIFT (8U)
/*! MBACSEL2 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL2_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE2_MASK   (0x800U)
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE2_SHIFT  (11U)
/*! NSE2 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE2_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL3_MASK (0x7000U)
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL3_SHIFT (12U)
/*! MBACSEL3 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL3_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE3_MASK   (0x8000U)
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE3_SHIFT  (15U)
/*! NSE3 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE3_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL4_MASK (0x70000U)
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL4_SHIFT (16U)
/*! MBACSEL4 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL4_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE4_MASK   (0x80000U)
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE4_SHIFT  (19U)
/*! NSE4 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE4_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL5_MASK (0x700000U)
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL5_SHIFT (20U)
/*! MBACSEL5 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL5_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE5_MASK   (0x800000U)
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE5_SHIFT  (23U)
/*! NSE5 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE5_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL6_MASK (0x7000000U)
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL6_SHIFT (24U)
/*! MBACSEL6 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL6_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE6_MASK   (0x8000000U)
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE6_SHIFT  (27U)
/*! NSE6 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE6_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL7_MASK (0x70000000U)
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL7_SHIFT (28U)
/*! MBACSEL7 - Memory Block Access Control Select for block B
 *  0b000..select MBC_MEMN_GLBAC0 access control policy for block B
 *  0b001..select MBC_MEMN_GLBAC1 access control policy for block B
 *  0b010..select MBC_MEMN_GLBAC2 access control policy for block B
 *  0b011..select MBC_MEMN_GLBAC3 access control policy for block B
 *  0b100..select MBC_MEMN_GLBAC4 access control policy for block B
 *  0b101..select MBC_MEMN_GLBAC5 access control policy for block B
 *  0b110..select MBC_MEMN_GLBAC6 access control policy for block B
 *  0b111..select MBC_MEMN_GLBAC7 access control policy for block B
 */
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_CFG_W_MBACSEL7_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE7_MASK   (0x80000000U)
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE7_SHIFT  (31U)
/*! NSE7 - NonSecure Enable for block B
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_CFG_W_NSE7_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM2_MEM3_BLK_CFG_W */
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_COUNT       (3U)

/* The count of TRDC_MBC_DOM2_MEM3_BLK_CFG_W */
#define TRDC_MBC_DOM2_MEM3_BLK_CFG_W_COUNT2      (2U)

/*! @name MBC_DOM2_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
/*! @{ */

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT0_MASK   (0x1U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT0_SHIFT  (0U)
/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT0(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT0_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT1_MASK   (0x2U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT1_SHIFT  (1U)
/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT1(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT1_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT2_MASK   (0x4U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT2_SHIFT  (2U)
/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT2(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT2_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT3_MASK   (0x8U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT3_SHIFT  (3U)
/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT3(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT3_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT4_MASK   (0x10U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT4_SHIFT  (4U)
/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT4(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT4_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT5_MASK   (0x20U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT5_SHIFT  (5U)
/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT5(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT5_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT6_MASK   (0x40U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT6_SHIFT  (6U)
/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT6(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT6_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT7_MASK   (0x80U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT7_SHIFT  (7U)
/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT7(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT7_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT8_MASK   (0x100U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT8_SHIFT  (8U)
/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT8(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT8_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT9_MASK   (0x200U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT9_SHIFT  (9U)
/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT9(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT9_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT10_MASK  (0x400U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT10_SHIFT (10U)
/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT10(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT10_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT11_MASK  (0x800U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT11_SHIFT (11U)
/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT11(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT11_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT12_MASK  (0x1000U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT12_SHIFT (12U)
/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT12(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT12_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT13_MASK  (0x2000U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT13_SHIFT (13U)
/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT13(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT13_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT14_MASK  (0x4000U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT14_SHIFT (14U)
/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT14(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT14_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT15_MASK  (0x8000U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT15_SHIFT (15U)
/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT15(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT15_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT16_MASK  (0x10000U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT16_SHIFT (16U)
/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT16(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT16_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT17_MASK  (0x20000U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT17_SHIFT (17U)
/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT17(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT17_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT18_MASK  (0x40000U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT18_SHIFT (18U)
/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT18(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT18_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT19_MASK  (0x80000U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT19_SHIFT (19U)
/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT19(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT19_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT20_MASK  (0x100000U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT20_SHIFT (20U)
/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT20(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT20_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT21_MASK  (0x200000U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT21_SHIFT (21U)
/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT21(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT21_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT22_MASK  (0x400000U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT22_SHIFT (22U)
/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT22(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT22_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT23_MASK  (0x800000U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT23_SHIFT (23U)
/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT23(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT23_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT24_MASK  (0x1000000U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT24_SHIFT (24U)
/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT24(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT24_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT25_MASK  (0x2000000U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT25_SHIFT (25U)
/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT25(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT25_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT26_MASK  (0x4000000U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT26_SHIFT (26U)
/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT26(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT26_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT27_MASK  (0x8000000U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT27_SHIFT (27U)
/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT27(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT27_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT28_MASK  (0x10000000U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT28_SHIFT (28U)
/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT28(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT28_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT29_MASK  (0x20000000U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT29_SHIFT (29U)
/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT29(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT29_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT30_MASK  (0x40000000U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT30_SHIFT (30U)
/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT30(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT30_MASK)

#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT31_MASK  (0x80000000U)
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT31_SHIFT (31U)
/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
 *  0b0..Secure accesses to block B are based on corresponding MBACSEL field in register
 *       (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed.
 *  0b1..Secure accesses to block B are are not allowed, nonsecure accesses to block B are based on corresponding
 *       MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]).
 */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT31(x)    (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_DOM2_MEM3_BLK_NSE_W_BIT31_MASK)
/*! @} */

/* The count of TRDC_MBC_DOM2_MEM3_BLK_NSE_W */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_COUNT       (3U)

/* The count of TRDC_MBC_DOM2_MEM3_BLK_NSE_W */
#define TRDC_MBC_DOM2_MEM3_BLK_NSE_W_COUNT2      (1U)

/*! @name MRC_GLBCFG - MRC Global Configuration Register */
/*! @{ */

#define TRDC_MRC_GLBCFG_NRGNS_MASK               (0x1FU)
#define TRDC_MRC_GLBCFG_NRGNS_SHIFT              (0U)
/*! NRGNS - Number of regions [1-16]
 */
#define TRDC_MRC_GLBCFG_NRGNS(x)                 (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_GLBCFG_NRGNS_SHIFT)) & TRDC_MRC_GLBCFG_NRGNS_MASK)
/*! @} */

/* The count of TRDC_MRC_GLBCFG */
#define TRDC_MRC_GLBCFG_COUNT                    (1U)

/*! @name MRC_NSE_RGN_INDIRECT - MRC NonSecure Enable Region Indirect */
/*! @{ */

#define TRDC_MRC_NSE_RGN_INDIRECT_DID_SEL_MASK   (0xFF0000U)
#define TRDC_MRC_NSE_RGN_INDIRECT_DID_SEL_SHIFT  (16U)
/*! DID_SEL - DID Select
 */
#define TRDC_MRC_NSE_RGN_INDIRECT_DID_SEL(x)     (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_NSE_RGN_INDIRECT_DID_SEL_SHIFT)) & TRDC_MRC_NSE_RGN_INDIRECT_DID_SEL_MASK)
/*! @} */

/* The count of TRDC_MRC_NSE_RGN_INDIRECT */
#define TRDC_MRC_NSE_RGN_INDIRECT_COUNT          (1U)

/*! @name MRC_NSE_RGN_SET - MRC NonSecure Enable Region Set */
/*! @{ */

#define TRDC_MRC_NSE_RGN_SET_W1SET_MASK          (0xFFFFU)
#define TRDC_MRC_NSE_RGN_SET_W1SET_SHIFT         (0U)
/*! W1SET - Write-1 Set
 */
#define TRDC_MRC_NSE_RGN_SET_W1SET(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_NSE_RGN_SET_W1SET_SHIFT)) & TRDC_MRC_NSE_RGN_SET_W1SET_MASK)
/*! @} */

/* The count of TRDC_MRC_NSE_RGN_SET */
#define TRDC_MRC_NSE_RGN_SET_COUNT               (1U)

/*! @name MRC_NSE_RGN_CLR - MRC NonSecure Enable Region Clear */
/*! @{ */

#define TRDC_MRC_NSE_RGN_CLR_W1CLR_MASK          (0xFFFFU)
#define TRDC_MRC_NSE_RGN_CLR_W1CLR_SHIFT         (0U)
/*! W1CLR - Write-1 Clear
 */
#define TRDC_MRC_NSE_RGN_CLR_W1CLR(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_NSE_RGN_CLR_W1CLR_SHIFT)) & TRDC_MRC_NSE_RGN_CLR_W1CLR_MASK)
/*! @} */

/* The count of TRDC_MRC_NSE_RGN_CLR */
#define TRDC_MRC_NSE_RGN_CLR_COUNT               (1U)

/*! @name MRC_NSE_RGN_CLR_ALL - MRC NonSecure Enable Region Clear All */
/*! @{ */

#define TRDC_MRC_NSE_RGN_CLR_ALL_DID_SEL_MASK    (0xFF0000U)
#define TRDC_MRC_NSE_RGN_CLR_ALL_DID_SEL_SHIFT   (16U)
/*! DID_SEL - DID Select
 */
#define TRDC_MRC_NSE_RGN_CLR_ALL_DID_SEL(x)      (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_NSE_RGN_CLR_ALL_DID_SEL_SHIFT)) & TRDC_MRC_NSE_RGN_CLR_ALL_DID_SEL_MASK)
/*! @} */

/* The count of TRDC_MRC_NSE_RGN_CLR_ALL */
#define TRDC_MRC_NSE_RGN_CLR_ALL_COUNT           (1U)

/*! @name MRC_GLBAC - MRC Global Access Control */
/*! @{ */

#define TRDC_MRC_GLBAC_NUX_MASK                  (0x1U)
#define TRDC_MRC_GLBAC_NUX_SHIFT                 (0U)
/*! NUX - NonsecureUser Execute
 *  0b0..Execute access is not allowed in Nonsecure User mode.
 *  0b1..Execute access is allowed in Nonsecure User mode.
 */
#define TRDC_MRC_GLBAC_NUX(x)                    (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_GLBAC_NUX_SHIFT)) & TRDC_MRC_GLBAC_NUX_MASK)

#define TRDC_MRC_GLBAC_NUW_MASK                  (0x2U)
#define TRDC_MRC_GLBAC_NUW_SHIFT                 (1U)
/*! NUW - NonsecureUser Write
 *  0b0..Write access is not allowed in Nonsecure User mode.
 *  0b1..Write access is allowed in Nonsecure User mode.
 */
#define TRDC_MRC_GLBAC_NUW(x)                    (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_GLBAC_NUW_SHIFT)) & TRDC_MRC_GLBAC_NUW_MASK)

#define TRDC_MRC_GLBAC_NUR_MASK                  (0x4U)
#define TRDC_MRC_GLBAC_NUR_SHIFT                 (2U)
/*! NUR - NonsecureUser Read
 *  0b0..Read access is not allowed in Nonsecure User mode.
 *  0b1..Read access is allowed in Nonsecure User mode.
 */
#define TRDC_MRC_GLBAC_NUR(x)                    (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_GLBAC_NUR_SHIFT)) & TRDC_MRC_GLBAC_NUR_MASK)

#define TRDC_MRC_GLBAC_NPX_MASK                  (0x10U)
#define TRDC_MRC_GLBAC_NPX_SHIFT                 (4U)
/*! NPX - NonsecurePriv Execute
 *  0b0..Execute access is not allowed in Nonsecure Privilege mode.
 *  0b1..Execute access is allowed in Nonsecure Privilege mode.
 */
#define TRDC_MRC_GLBAC_NPX(x)                    (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_GLBAC_NPX_SHIFT)) & TRDC_MRC_GLBAC_NPX_MASK)

#define TRDC_MRC_GLBAC_NPW_MASK                  (0x20U)
#define TRDC_MRC_GLBAC_NPW_SHIFT                 (5U)
/*! NPW - NonsecurePriv Write
 *  0b0..Write access is not allowed in Nonsecure Privilege mode.
 *  0b1..Write access is allowed in Nonsecure Privilege mode.
 */
#define TRDC_MRC_GLBAC_NPW(x)                    (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_GLBAC_NPW_SHIFT)) & TRDC_MRC_GLBAC_NPW_MASK)

#define TRDC_MRC_GLBAC_NPR_MASK                  (0x40U)
#define TRDC_MRC_GLBAC_NPR_SHIFT                 (6U)
/*! NPR - NonsecurePriv Read
 *  0b0..Read access is not allowed in Nonsecure Privilege mode.
 *  0b1..Read access is allowed in Nonsecure Privilege mode.
 */
#define TRDC_MRC_GLBAC_NPR(x)                    (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_GLBAC_NPR_SHIFT)) & TRDC_MRC_GLBAC_NPR_MASK)

#define TRDC_MRC_GLBAC_SUX_MASK                  (0x100U)
#define TRDC_MRC_GLBAC_SUX_SHIFT                 (8U)
/*! SUX - SecureUser Execute
 *  0b0..Execute access is not allowed in Secure User mode.
 *  0b1..Execute access is allowed in Secure User mode.
 */
#define TRDC_MRC_GLBAC_SUX(x)                    (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_GLBAC_SUX_SHIFT)) & TRDC_MRC_GLBAC_SUX_MASK)

#define TRDC_MRC_GLBAC_SUW_MASK                  (0x200U)
#define TRDC_MRC_GLBAC_SUW_SHIFT                 (9U)
/*! SUW - SecureUser Write
 *  0b0..Write access is not allowed in Secure User mode.
 *  0b1..Write access is allowed in Secure User mode.
 */
#define TRDC_MRC_GLBAC_SUW(x)                    (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_GLBAC_SUW_SHIFT)) & TRDC_MRC_GLBAC_SUW_MASK)

#define TRDC_MRC_GLBAC_SUR_MASK                  (0x400U)
#define TRDC_MRC_GLBAC_SUR_SHIFT                 (10U)
/*! SUR - SecureUser Read
 *  0b0..Read access is not allowed in Secure User mode.
 *  0b1..Read access is allowed in Secure User mode.
 */
#define TRDC_MRC_GLBAC_SUR(x)                    (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_GLBAC_SUR_SHIFT)) & TRDC_MRC_GLBAC_SUR_MASK)

#define TRDC_MRC_GLBAC_SPX_MASK                  (0x1000U)
#define TRDC_MRC_GLBAC_SPX_SHIFT                 (12U)
/*! SPX - SecurePriv Execute
 *  0b0..Execute access is not allowed in Secure Privilege mode.
 *  0b1..Execute access is allowed in Secure Privilege mode.
 */
#define TRDC_MRC_GLBAC_SPX(x)                    (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_GLBAC_SPX_SHIFT)) & TRDC_MRC_GLBAC_SPX_MASK)

#define TRDC_MRC_GLBAC_SPW_MASK                  (0x2000U)
#define TRDC_MRC_GLBAC_SPW_SHIFT                 (13U)
/*! SPW - SecurePriv Write
 *  0b0..Write access is not allowed in Secure Privilege mode.
 *  0b1..Write access is allowed in Secure Privilege mode.
 */
#define TRDC_MRC_GLBAC_SPW(x)                    (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_GLBAC_SPW_SHIFT)) & TRDC_MRC_GLBAC_SPW_MASK)

#define TRDC_MRC_GLBAC_SPR_MASK                  (0x4000U)
#define TRDC_MRC_GLBAC_SPR_SHIFT                 (14U)
/*! SPR - SecurePriv Read
 *  0b0..Read access is not allowed in Secure Privilege mode.
 *  0b1..Read access is allowed in Secure Privilege mode.
 */
#define TRDC_MRC_GLBAC_SPR(x)                    (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_GLBAC_SPR_SHIFT)) & TRDC_MRC_GLBAC_SPR_MASK)

#define TRDC_MRC_GLBAC_LK_MASK                   (0x80000000U)
#define TRDC_MRC_GLBAC_LK_SHIFT                  (31U)
/*! LK - LOCK
 *  0b0..This register is not locked and can be altered.
 *  0b1..This register is locked (read-only) and cannot be altered.
 */
#define TRDC_MRC_GLBAC_LK(x)                     (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_GLBAC_LK_SHIFT)) & TRDC_MRC_GLBAC_LK_MASK)
/*! @} */

/* The count of TRDC_MRC_GLBAC */
#define TRDC_MRC_GLBAC_COUNT                     (1U)

/* The count of TRDC_MRC_GLBAC */
#define TRDC_MRC_GLBAC_COUNT2                    (8U)

/*! @name MRC_DOM0_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */
/*! @{ */

#define TRDC_MRC_DOM0_RGD_W_MRACSEL_MASK         (0x7U)
#define TRDC_MRC_DOM0_RGD_W_MRACSEL_SHIFT        (0U)
/*! MRACSEL - Memory Region Access Control Select
 *  0b000..Select MRC_GLBAC0 access control policy
 *  0b001..Select MRC_GLBAC1 access control policy
 *  0b010..Select MRC_GLBAC2 access control policy
 *  0b011..Select MRC_GLBAC3 access control policy
 *  0b100..Select MRC_GLBAC4 access control policy
 *  0b101..Select MRC_GLBAC5 access control policy
 *  0b110..Select MRC_GLBAC6 access control policy
 *  0b111..Select MRC_GLBAC7 access control policy
 */
#define TRDC_MRC_DOM0_RGD_W_MRACSEL(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM0_RGD_W_MRACSEL_SHIFT)) & TRDC_MRC_DOM0_RGD_W_MRACSEL_MASK)

#define TRDC_MRC_DOM0_RGD_W_VLD_MASK             (0x1U)
#define TRDC_MRC_DOM0_RGD_W_VLD_SHIFT            (0U)
/*! VLD - Valid
 */
#define TRDC_MRC_DOM0_RGD_W_VLD(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM0_RGD_W_VLD_SHIFT)) & TRDC_MRC_DOM0_RGD_W_VLD_MASK)

#define TRDC_MRC_DOM0_RGD_W_NSE_MASK             (0x10U)
#define TRDC_MRC_DOM0_RGD_W_NSE_SHIFT            (4U)
/*! NSE - NonSecure Enable
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM0_RGD_W_NSE(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM0_RGD_W_NSE_SHIFT)) & TRDC_MRC_DOM0_RGD_W_NSE_MASK)

#define TRDC_MRC_DOM0_RGD_W_END_ADDR_MASK        (0xFFFFF000U)
#define TRDC_MRC_DOM0_RGD_W_END_ADDR_SHIFT       (12U)
/*! END_ADDR - End Address
 */
#define TRDC_MRC_DOM0_RGD_W_END_ADDR(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM0_RGD_W_END_ADDR_SHIFT)) & TRDC_MRC_DOM0_RGD_W_END_ADDR_MASK)

#define TRDC_MRC_DOM0_RGD_W_STRT_ADDR_MASK       (0xFFFFF000U)
#define TRDC_MRC_DOM0_RGD_W_STRT_ADDR_SHIFT      (12U)
/*! STRT_ADDR - Start Address
 */
#define TRDC_MRC_DOM0_RGD_W_STRT_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM0_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MRC_DOM0_RGD_W_STRT_ADDR_MASK)
/*! @} */

/* The count of TRDC_MRC_DOM0_RGD_W */
#define TRDC_MRC_DOM0_RGD_W_COUNT                (1U)

/* The count of TRDC_MRC_DOM0_RGD_W */
#define TRDC_MRC_DOM0_RGD_W_COUNT2               (8U)

/* The count of TRDC_MRC_DOM0_RGD_W */
#define TRDC_MRC_DOM0_RGD_W_COUNT3               (2U)

/*! @name MRC_DOM0_RGD_NSE - MRC Region Descriptor NonSecure Enable */
/*! @{ */

#define TRDC_MRC_DOM0_RGD_NSE_BIT0_MASK          (0x1U)
#define TRDC_MRC_DOM0_RGD_NSE_BIT0_SHIFT         (0U)
/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM0_RGD_NSE_BIT0(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM0_RGD_NSE_BIT0_SHIFT)) & TRDC_MRC_DOM0_RGD_NSE_BIT0_MASK)

#define TRDC_MRC_DOM0_RGD_NSE_BIT1_MASK          (0x2U)
#define TRDC_MRC_DOM0_RGD_NSE_BIT1_SHIFT         (1U)
/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM0_RGD_NSE_BIT1(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM0_RGD_NSE_BIT1_SHIFT)) & TRDC_MRC_DOM0_RGD_NSE_BIT1_MASK)

#define TRDC_MRC_DOM0_RGD_NSE_BIT2_MASK          (0x4U)
#define TRDC_MRC_DOM0_RGD_NSE_BIT2_SHIFT         (2U)
/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM0_RGD_NSE_BIT2(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM0_RGD_NSE_BIT2_SHIFT)) & TRDC_MRC_DOM0_RGD_NSE_BIT2_MASK)

#define TRDC_MRC_DOM0_RGD_NSE_BIT3_MASK          (0x8U)
#define TRDC_MRC_DOM0_RGD_NSE_BIT3_SHIFT         (3U)
/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM0_RGD_NSE_BIT3(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM0_RGD_NSE_BIT3_SHIFT)) & TRDC_MRC_DOM0_RGD_NSE_BIT3_MASK)

#define TRDC_MRC_DOM0_RGD_NSE_BIT4_MASK          (0x10U)
#define TRDC_MRC_DOM0_RGD_NSE_BIT4_SHIFT         (4U)
/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM0_RGD_NSE_BIT4(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM0_RGD_NSE_BIT4_SHIFT)) & TRDC_MRC_DOM0_RGD_NSE_BIT4_MASK)

#define TRDC_MRC_DOM0_RGD_NSE_BIT5_MASK          (0x20U)
#define TRDC_MRC_DOM0_RGD_NSE_BIT5_SHIFT         (5U)
/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM0_RGD_NSE_BIT5(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM0_RGD_NSE_BIT5_SHIFT)) & TRDC_MRC_DOM0_RGD_NSE_BIT5_MASK)

#define TRDC_MRC_DOM0_RGD_NSE_BIT6_MASK          (0x40U)
#define TRDC_MRC_DOM0_RGD_NSE_BIT6_SHIFT         (6U)
/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM0_RGD_NSE_BIT6(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM0_RGD_NSE_BIT6_SHIFT)) & TRDC_MRC_DOM0_RGD_NSE_BIT6_MASK)

#define TRDC_MRC_DOM0_RGD_NSE_BIT7_MASK          (0x80U)
#define TRDC_MRC_DOM0_RGD_NSE_BIT7_SHIFT         (7U)
/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM0_RGD_NSE_BIT7(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM0_RGD_NSE_BIT7_SHIFT)) & TRDC_MRC_DOM0_RGD_NSE_BIT7_MASK)
/*! @} */

/* The count of TRDC_MRC_DOM0_RGD_NSE */
#define TRDC_MRC_DOM0_RGD_NSE_COUNT              (1U)

/*! @name MRC_DOM1_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */
/*! @{ */

#define TRDC_MRC_DOM1_RGD_W_MRACSEL_MASK         (0x7U)
#define TRDC_MRC_DOM1_RGD_W_MRACSEL_SHIFT        (0U)
/*! MRACSEL - Memory Region Access Control Select
 *  0b000..Select MRC_GLBAC0 access control policy
 *  0b001..Select MRC_GLBAC1 access control policy
 *  0b010..Select MRC_GLBAC2 access control policy
 *  0b011..Select MRC_GLBAC3 access control policy
 *  0b100..Select MRC_GLBAC4 access control policy
 *  0b101..Select MRC_GLBAC5 access control policy
 *  0b110..Select MRC_GLBAC6 access control policy
 *  0b111..Select MRC_GLBAC7 access control policy
 */
#define TRDC_MRC_DOM1_RGD_W_MRACSEL(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM1_RGD_W_MRACSEL_SHIFT)) & TRDC_MRC_DOM1_RGD_W_MRACSEL_MASK)

#define TRDC_MRC_DOM1_RGD_W_VLD_MASK             (0x1U)
#define TRDC_MRC_DOM1_RGD_W_VLD_SHIFT            (0U)
/*! VLD - Valid
 */
#define TRDC_MRC_DOM1_RGD_W_VLD(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM1_RGD_W_VLD_SHIFT)) & TRDC_MRC_DOM1_RGD_W_VLD_MASK)

#define TRDC_MRC_DOM1_RGD_W_NSE_MASK             (0x10U)
#define TRDC_MRC_DOM1_RGD_W_NSE_SHIFT            (4U)
/*! NSE - NonSecure Enable
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM1_RGD_W_NSE(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM1_RGD_W_NSE_SHIFT)) & TRDC_MRC_DOM1_RGD_W_NSE_MASK)

#define TRDC_MRC_DOM1_RGD_W_END_ADDR_MASK        (0xFFFFF000U)
#define TRDC_MRC_DOM1_RGD_W_END_ADDR_SHIFT       (12U)
/*! END_ADDR - End Address
 */
#define TRDC_MRC_DOM1_RGD_W_END_ADDR(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM1_RGD_W_END_ADDR_SHIFT)) & TRDC_MRC_DOM1_RGD_W_END_ADDR_MASK)

#define TRDC_MRC_DOM1_RGD_W_STRT_ADDR_MASK       (0xFFFFF000U)
#define TRDC_MRC_DOM1_RGD_W_STRT_ADDR_SHIFT      (12U)
/*! STRT_ADDR - Start Address
 */
#define TRDC_MRC_DOM1_RGD_W_STRT_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM1_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MRC_DOM1_RGD_W_STRT_ADDR_MASK)
/*! @} */

/* The count of TRDC_MRC_DOM1_RGD_W */
#define TRDC_MRC_DOM1_RGD_W_COUNT                (1U)

/* The count of TRDC_MRC_DOM1_RGD_W */
#define TRDC_MRC_DOM1_RGD_W_COUNT2               (8U)

/* The count of TRDC_MRC_DOM1_RGD_W */
#define TRDC_MRC_DOM1_RGD_W_COUNT3               (2U)

/*! @name MRC_DOM1_RGD_NSE - MRC Region Descriptor NonSecure Enable */
/*! @{ */

#define TRDC_MRC_DOM1_RGD_NSE_BIT0_MASK          (0x1U)
#define TRDC_MRC_DOM1_RGD_NSE_BIT0_SHIFT         (0U)
/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM1_RGD_NSE_BIT0(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM1_RGD_NSE_BIT0_SHIFT)) & TRDC_MRC_DOM1_RGD_NSE_BIT0_MASK)

#define TRDC_MRC_DOM1_RGD_NSE_BIT1_MASK          (0x2U)
#define TRDC_MRC_DOM1_RGD_NSE_BIT1_SHIFT         (1U)
/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM1_RGD_NSE_BIT1(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM1_RGD_NSE_BIT1_SHIFT)) & TRDC_MRC_DOM1_RGD_NSE_BIT1_MASK)

#define TRDC_MRC_DOM1_RGD_NSE_BIT2_MASK          (0x4U)
#define TRDC_MRC_DOM1_RGD_NSE_BIT2_SHIFT         (2U)
/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM1_RGD_NSE_BIT2(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM1_RGD_NSE_BIT2_SHIFT)) & TRDC_MRC_DOM1_RGD_NSE_BIT2_MASK)

#define TRDC_MRC_DOM1_RGD_NSE_BIT3_MASK          (0x8U)
#define TRDC_MRC_DOM1_RGD_NSE_BIT3_SHIFT         (3U)
/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM1_RGD_NSE_BIT3(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM1_RGD_NSE_BIT3_SHIFT)) & TRDC_MRC_DOM1_RGD_NSE_BIT3_MASK)

#define TRDC_MRC_DOM1_RGD_NSE_BIT4_MASK          (0x10U)
#define TRDC_MRC_DOM1_RGD_NSE_BIT4_SHIFT         (4U)
/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM1_RGD_NSE_BIT4(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM1_RGD_NSE_BIT4_SHIFT)) & TRDC_MRC_DOM1_RGD_NSE_BIT4_MASK)

#define TRDC_MRC_DOM1_RGD_NSE_BIT5_MASK          (0x20U)
#define TRDC_MRC_DOM1_RGD_NSE_BIT5_SHIFT         (5U)
/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM1_RGD_NSE_BIT5(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM1_RGD_NSE_BIT5_SHIFT)) & TRDC_MRC_DOM1_RGD_NSE_BIT5_MASK)

#define TRDC_MRC_DOM1_RGD_NSE_BIT6_MASK          (0x40U)
#define TRDC_MRC_DOM1_RGD_NSE_BIT6_SHIFT         (6U)
/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM1_RGD_NSE_BIT6(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM1_RGD_NSE_BIT6_SHIFT)) & TRDC_MRC_DOM1_RGD_NSE_BIT6_MASK)

#define TRDC_MRC_DOM1_RGD_NSE_BIT7_MASK          (0x80U)
#define TRDC_MRC_DOM1_RGD_NSE_BIT7_SHIFT         (7U)
/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM1_RGD_NSE_BIT7(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM1_RGD_NSE_BIT7_SHIFT)) & TRDC_MRC_DOM1_RGD_NSE_BIT7_MASK)
/*! @} */

/* The count of TRDC_MRC_DOM1_RGD_NSE */
#define TRDC_MRC_DOM1_RGD_NSE_COUNT              (1U)

/*! @name MRC_DOM2_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */
/*! @{ */

#define TRDC_MRC_DOM2_RGD_W_MRACSEL_MASK         (0x7U)
#define TRDC_MRC_DOM2_RGD_W_MRACSEL_SHIFT        (0U)
/*! MRACSEL - Memory Region Access Control Select
 *  0b000..Select MRC_GLBAC0 access control policy
 *  0b001..Select MRC_GLBAC1 access control policy
 *  0b010..Select MRC_GLBAC2 access control policy
 *  0b011..Select MRC_GLBAC3 access control policy
 *  0b100..Select MRC_GLBAC4 access control policy
 *  0b101..Select MRC_GLBAC5 access control policy
 *  0b110..Select MRC_GLBAC6 access control policy
 *  0b111..Select MRC_GLBAC7 access control policy
 */
#define TRDC_MRC_DOM2_RGD_W_MRACSEL(x)           (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM2_RGD_W_MRACSEL_SHIFT)) & TRDC_MRC_DOM2_RGD_W_MRACSEL_MASK)

#define TRDC_MRC_DOM2_RGD_W_VLD_MASK             (0x1U)
#define TRDC_MRC_DOM2_RGD_W_VLD_SHIFT            (0U)
/*! VLD - Valid
 */
#define TRDC_MRC_DOM2_RGD_W_VLD(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM2_RGD_W_VLD_SHIFT)) & TRDC_MRC_DOM2_RGD_W_VLD_MASK)

#define TRDC_MRC_DOM2_RGD_W_NSE_MASK             (0x10U)
#define TRDC_MRC_DOM2_RGD_W_NSE_SHIFT            (4U)
/*! NSE - NonSecure Enable
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in this register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM2_RGD_W_NSE(x)               (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM2_RGD_W_NSE_SHIFT)) & TRDC_MRC_DOM2_RGD_W_NSE_MASK)

#define TRDC_MRC_DOM2_RGD_W_END_ADDR_MASK        (0xFFFFF000U)
#define TRDC_MRC_DOM2_RGD_W_END_ADDR_SHIFT       (12U)
/*! END_ADDR - End Address
 */
#define TRDC_MRC_DOM2_RGD_W_END_ADDR(x)          (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM2_RGD_W_END_ADDR_SHIFT)) & TRDC_MRC_DOM2_RGD_W_END_ADDR_MASK)

#define TRDC_MRC_DOM2_RGD_W_STRT_ADDR_MASK       (0xFFFFF000U)
#define TRDC_MRC_DOM2_RGD_W_STRT_ADDR_SHIFT      (12U)
/*! STRT_ADDR - Start Address
 */
#define TRDC_MRC_DOM2_RGD_W_STRT_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM2_RGD_W_STRT_ADDR_SHIFT)) & TRDC_MRC_DOM2_RGD_W_STRT_ADDR_MASK)
/*! @} */

/* The count of TRDC_MRC_DOM2_RGD_W */
#define TRDC_MRC_DOM2_RGD_W_COUNT                (1U)

/* The count of TRDC_MRC_DOM2_RGD_W */
#define TRDC_MRC_DOM2_RGD_W_COUNT2               (8U)

/* The count of TRDC_MRC_DOM2_RGD_W */
#define TRDC_MRC_DOM2_RGD_W_COUNT3               (2U)

/*! @name MRC_DOM2_RGD_NSE - MRC Region Descriptor NonSecure Enable */
/*! @{ */

#define TRDC_MRC_DOM2_RGD_NSE_BIT0_MASK          (0x1U)
#define TRDC_MRC_DOM2_RGD_NSE_BIT0_SHIFT         (0U)
/*! BIT0 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM2_RGD_NSE_BIT0(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM2_RGD_NSE_BIT0_SHIFT)) & TRDC_MRC_DOM2_RGD_NSE_BIT0_MASK)

#define TRDC_MRC_DOM2_RGD_NSE_BIT1_MASK          (0x2U)
#define TRDC_MRC_DOM2_RGD_NSE_BIT1_SHIFT         (1U)
/*! BIT1 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM2_RGD_NSE_BIT1(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM2_RGD_NSE_BIT1_SHIFT)) & TRDC_MRC_DOM2_RGD_NSE_BIT1_MASK)

#define TRDC_MRC_DOM2_RGD_NSE_BIT2_MASK          (0x4U)
#define TRDC_MRC_DOM2_RGD_NSE_BIT2_SHIFT         (2U)
/*! BIT2 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM2_RGD_NSE_BIT2(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM2_RGD_NSE_BIT2_SHIFT)) & TRDC_MRC_DOM2_RGD_NSE_BIT2_MASK)

#define TRDC_MRC_DOM2_RGD_NSE_BIT3_MASK          (0x8U)
#define TRDC_MRC_DOM2_RGD_NSE_BIT3_SHIFT         (3U)
/*! BIT3 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM2_RGD_NSE_BIT3(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM2_RGD_NSE_BIT3_SHIFT)) & TRDC_MRC_DOM2_RGD_NSE_BIT3_MASK)

#define TRDC_MRC_DOM2_RGD_NSE_BIT4_MASK          (0x10U)
#define TRDC_MRC_DOM2_RGD_NSE_BIT4_SHIFT         (4U)
/*! BIT4 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM2_RGD_NSE_BIT4(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM2_RGD_NSE_BIT4_SHIFT)) & TRDC_MRC_DOM2_RGD_NSE_BIT4_MASK)

#define TRDC_MRC_DOM2_RGD_NSE_BIT5_MASK          (0x20U)
#define TRDC_MRC_DOM2_RGD_NSE_BIT5_SHIFT         (5U)
/*! BIT5 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM2_RGD_NSE_BIT5(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM2_RGD_NSE_BIT5_SHIFT)) & TRDC_MRC_DOM2_RGD_NSE_BIT5_MASK)

#define TRDC_MRC_DOM2_RGD_NSE_BIT6_MASK          (0x40U)
#define TRDC_MRC_DOM2_RGD_NSE_BIT6_SHIFT         (6U)
/*! BIT6 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM2_RGD_NSE_BIT6(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM2_RGD_NSE_BIT6_SHIFT)) & TRDC_MRC_DOM2_RGD_NSE_BIT6_MASK)

#define TRDC_MRC_DOM2_RGD_NSE_BIT7_MASK          (0x80U)
#define TRDC_MRC_DOM2_RGD_NSE_BIT7_SHIFT         (7U)
/*! BIT7 - Bit n NonSecure Enable [n = 0 - 15]
 *  0b0..Secure accesses to region r are not allowed, nonsecure accesses to region r are based on corresponding
 *       MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 *  0b1..Secure accesses to region r are are not allowed, nonsecure accesses to region r are based on
 *       corresponding MRACSEL field in register (MRCm_DOMd_RGDr_Ww[MRACSEL]).
 */
#define TRDC_MRC_DOM2_RGD_NSE_BIT7(x)            (((uint32_t)(((uint32_t)(x)) << TRDC_MRC_DOM2_RGD_NSE_BIT7_SHIFT)) & TRDC_MRC_DOM2_RGD_NSE_BIT7_MASK)
/*! @} */

/* The count of TRDC_MRC_DOM2_RGD_NSE */
#define TRDC_MRC_DOM2_RGD_NSE_COUNT              (1U)


/*!
 * @}
 */ /* end of group TRDC_Register_Masks */


/* TRDC - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral TRDC base address */
  #define TRDC_BASE                                (0x50026000u)
  /** Peripheral TRDC base address */
  #define TRDC_BASE_NS                             (0x40026000u)
  /** Peripheral TRDC base pointer */
  #define TRDC                                     ((TRDC_Type *)TRDC_BASE)
  /** Peripheral TRDC base pointer */
  #define TRDC_NS                                  ((TRDC_Type *)TRDC_BASE_NS)
  /** Array initializer of TRDC peripheral base addresses */
  #define TRDC_BASE_ADDRS                          { TRDC_BASE }
  /** Array initializer of TRDC peripheral base pointers */
  #define TRDC_BASE_PTRS                           { TRDC }
  /** Array initializer of TRDC peripheral base addresses */
  #define TRDC_BASE_ADDRS_NS                       { TRDC_BASE_NS }
  /** Array initializer of TRDC peripheral base pointers */
  #define TRDC_BASE_PTRS_NS                        { TRDC_NS }
#else
  /** Peripheral TRDC base address */
  #define TRDC_BASE                                (0x40026000u)
  /** Peripheral TRDC base pointer */
  #define TRDC                                     ((TRDC_Type *)TRDC_BASE)
  /** Array initializer of TRDC peripheral base addresses */
  #define TRDC_BASE_ADDRS                          { TRDC_BASE }
  /** Array initializer of TRDC peripheral base pointers */
  #define TRDC_BASE_PTRS                           { TRDC }
#endif
/** Interrupt vectors for the TRDC peripheral type */
#define TRDC_IRQS                                { TRDC0_IRQn }
#define MBC0_MEMORY_CFG_WORD_COUNT {4, 1, 1, 2}
#define MBC1_MEMORY_CFG_WORD_COUNT {1, 1, 1, 1}
#define MBC2_MEMORY_CFG_WORD_COUNT {10, 1, 2, 0}
#define MBC3_MEMORY_CFG_WORD_COUNT {0, 0, 0, 0}
#define MBC_MEMORY_CFG_WORD_COUNT {MBC0_MEMORY_CFG_WORD_COUNT , MBC1_MEMORY_CFG_WORD_COUNT, MBC2_MEMORY_CFG_WORD_COUNT, MBC3_MEMORY_CFG_WORD_COUNT}
#define MBC0_MEMORY_NSE_WORD_COUNT {1, 1, 1, 1}
#define MBC1_MEMORY_NSE_WORD_COUNT {1, 1, 1, 1}
#define MBC2_MEMORY_NSE_WORD_COUNT {3, 1, 1, 0}
#define MBC3_MEMORY_NSE_WORD_COUNT {0, 0, 0, 0}
#define MBC_MEMORY_NSE_WORD_COUNT {MBC0_MEMORY_NSE_WORD_COUNT , MBC1_MEMORY_NSE_WORD_COUNT, MBC2_MEMORY_NSE_WORD_COUNT, MBC3_MEMORY_NSE_WORD_COUNT}


/*!
 * @}
 */ /* end of group TRDC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- TRGMUX Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup TRGMUX_Peripheral_Access_Layer TRGMUX Peripheral Access Layer
 * @{
 */

/** TRGMUX - Register Layout Typedef */
typedef struct {
  __IO uint32_t TRGCFG[14];                        /**< TRGMUX TRGMUX_OUT0 Register..TRGMUX CMP_GP1 Register, array offset: 0x0, array step: 0x4 */
} TRGMUX_Type;

/* ----------------------------------------------------------------------------
   -- TRGMUX Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup TRGMUX_Register_Masks TRGMUX Register Masks
 * @{
 */

/*! @name TRGCFG - TRGMUX TRGMUX_OUT0 Register..TRGMUX CMP_GP1 Register */
/*! @{ */

#define TRGMUX_TRGCFG_SEL0_MASK                  (0x7FU)
#define TRGMUX_TRGCFG_SEL0_SHIFT                 (0U)
/*! SEL0 - Trigger MUX Input 0 Source Select
 */
#define TRGMUX_TRGCFG_SEL0(x)                    (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_SEL0_SHIFT)) & TRGMUX_TRGCFG_SEL0_MASK)

#define TRGMUX_TRGCFG_SEL1_MASK                  (0x7F00U)
#define TRGMUX_TRGCFG_SEL1_SHIFT                 (8U)
/*! SEL1 - Trigger MUX Input 1 Source Select
 */
#define TRGMUX_TRGCFG_SEL1(x)                    (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_SEL1_SHIFT)) & TRGMUX_TRGCFG_SEL1_MASK)

#define TRGMUX_TRGCFG_SEL2_MASK                  (0x7F0000U)
#define TRGMUX_TRGCFG_SEL2_SHIFT                 (16U)
/*! SEL2 - Trigger MUX Input 2 Source Select
 */
#define TRGMUX_TRGCFG_SEL2(x)                    (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_SEL2_SHIFT)) & TRGMUX_TRGCFG_SEL2_MASK)

#define TRGMUX_TRGCFG_SEL3_MASK                  (0x7F000000U)
#define TRGMUX_TRGCFG_SEL3_SHIFT                 (24U)
/*! SEL3 - Trigger MUX Input 3 Source Select
 */
#define TRGMUX_TRGCFG_SEL3(x)                    (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_SEL3_SHIFT)) & TRGMUX_TRGCFG_SEL3_MASK)

#define TRGMUX_TRGCFG_LK_MASK                    (0x80000000U)
#define TRGMUX_TRGCFG_LK_SHIFT                   (31U)
/*! LK - TRGMUX register lock.
 *  0b0..Register can be written.
 *  0b1..Register cannot be written until the next system Reset.
 */
#define TRGMUX_TRGCFG_LK(x)                      (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_LK_SHIFT)) & TRGMUX_TRGCFG_LK_MASK)
/*! @} */

/* The count of TRGMUX_TRGCFG */
#define TRGMUX_TRGCFG_COUNT                      (14U)


/*!
 * @}
 */ /* end of group TRGMUX_Register_Masks */


/* TRGMUX - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral TRGMUX0 base address */
  #define TRGMUX0_BASE                             (0x50018000u)
  /** Peripheral TRGMUX0 base address */
  #define TRGMUX0_BASE_NS                          (0x40018000u)
  /** Peripheral TRGMUX0 base pointer */
  #define TRGMUX0                                  ((TRGMUX_Type *)TRGMUX0_BASE)
  /** Peripheral TRGMUX0 base pointer */
  #define TRGMUX0_NS                               ((TRGMUX_Type *)TRGMUX0_BASE_NS)
  /** Array initializer of TRGMUX peripheral base addresses */
  #define TRGMUX_BASE_ADDRS                        { TRGMUX0_BASE }
  /** Array initializer of TRGMUX peripheral base pointers */
  #define TRGMUX_BASE_PTRS                         { TRGMUX0 }
  /** Array initializer of TRGMUX peripheral base addresses */
  #define TRGMUX_BASE_ADDRS_NS                     { TRGMUX0_BASE_NS }
  /** Array initializer of TRGMUX peripheral base pointers */
  #define TRGMUX_BASE_PTRS_NS                      { TRGMUX0_NS }
#else
  /** Peripheral TRGMUX0 base address */
  #define TRGMUX0_BASE                             (0x40018000u)
  /** Peripheral TRGMUX0 base pointer */
  #define TRGMUX0                                  ((TRGMUX_Type *)TRGMUX0_BASE)
  /** Array initializer of TRGMUX peripheral base addresses */
  #define TRGMUX_BASE_ADDRS                        { TRGMUX0_BASE }
  /** Array initializer of TRGMUX peripheral base pointers */
  #define TRGMUX_BASE_PTRS                         { TRGMUX0 }
#endif

/*!
 * @}
 */ /* end of group TRGMUX_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- TSTMR Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup TSTMR_Peripheral_Access_Layer TSTMR Peripheral Access Layer
 * @{
 */

/** TSTMR - Register Layout Typedef */
typedef struct {
  __I  uint32_t L;                                 /**< Time Stamp Timer Register Low, offset: 0x0 */
  __I  uint32_t H;                                 /**< Time Stamp Timer Register High, offset: 0x4 */
} TSTMR_Type;

/* ----------------------------------------------------------------------------
   -- TSTMR Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup TSTMR_Register_Masks TSTMR Register Masks
 * @{
 */

/*! @name L - Time Stamp Timer Register Low */
/*! @{ */

#define TSTMR_L_VALUE_MASK                       (0xFFFFFFFFU)
#define TSTMR_L_VALUE_SHIFT                      (0U)
/*! VALUE - Time Stamp Timer Low
 */
#define TSTMR_L_VALUE(x)                         (((uint32_t)(((uint32_t)(x)) << TSTMR_L_VALUE_SHIFT)) & TSTMR_L_VALUE_MASK)
/*! @} */

/*! @name H - Time Stamp Timer Register High */
/*! @{ */

#define TSTMR_H_VALUE_MASK                       (0xFFFFFFU)
#define TSTMR_H_VALUE_SHIFT                      (0U)
/*! VALUE - Time Stamp Timer High
 */
#define TSTMR_H_VALUE(x)                         (((uint32_t)(((uint32_t)(x)) << TSTMR_H_VALUE_SHIFT)) & TSTMR_H_VALUE_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group TSTMR_Register_Masks */


/* TSTMR - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral TSTMR0 base address */
  #define TSTMR0_BASE                              (0x50030000u)
  /** Peripheral TSTMR0 base address */
  #define TSTMR0_BASE_NS                           (0x40030000u)
  /** Peripheral TSTMR0 base pointer */
  #define TSTMR0                                   ((TSTMR_Type *)TSTMR0_BASE)
  /** Peripheral TSTMR0 base pointer */
  #define TSTMR0_NS                                ((TSTMR_Type *)TSTMR0_BASE_NS)
  /** Array initializer of TSTMR peripheral base addresses */
  #define TSTMR_BASE_ADDRS                         { TSTMR0_BASE }
  /** Array initializer of TSTMR peripheral base pointers */
  #define TSTMR_BASE_PTRS                          { TSTMR0 }
  /** Array initializer of TSTMR peripheral base addresses */
  #define TSTMR_BASE_ADDRS_NS                      { TSTMR0_BASE_NS }
  /** Array initializer of TSTMR peripheral base pointers */
  #define TSTMR_BASE_PTRS_NS                       { TSTMR0_NS }
#else
  /** Peripheral TSTMR0 base address */
  #define TSTMR0_BASE                              (0x40030000u)
  /** Peripheral TSTMR0 base pointer */
  #define TSTMR0                                   ((TSTMR_Type *)TSTMR0_BASE)
  /** Array initializer of TSTMR peripheral base addresses */
  #define TSTMR_BASE_ADDRS                         { TSTMR0_BASE }
  /** Array initializer of TSTMR peripheral base pointers */
  #define TSTMR_BASE_PTRS                          { TSTMR0 }
#endif

/*!
 * @}
 */ /* end of group TSTMR_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- TX_PACKET_RAM Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup TX_PACKET_RAM_Peripheral_Access_Layer TX_PACKET_RAM Peripheral Access Layer
 * @{
 */

/** TX_PACKET_RAM - Register Layout Typedef */
typedef struct {
  __IO uint32_t PACKET_RAM[1024];                  /**< Shared Packet RAM for multiple Link Layer usage., array offset: 0x0, array step: 0x4 */
} TX_PACKET_RAM_Type;

/* ----------------------------------------------------------------------------
   -- TX_PACKET_RAM Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup TX_PACKET_RAM_Register_Masks TX_PACKET_RAM Register Masks
 * @{
 */

/*! @name PACKET_RAM - Shared Packet RAM for multiple Link Layer usage. */
/*! @{ */

#define TX_PACKET_RAM_PACKET_RAM_RAM_MASK        (0xFFFFFFFFU)
#define TX_PACKET_RAM_PACKET_RAM_RAM_SHIFT       (0U)
/*! RAM - One entry in the packet RAM
 */
#define TX_PACKET_RAM_PACKET_RAM_RAM(x)          (((uint32_t)(((uint32_t)(x)) << TX_PACKET_RAM_PACKET_RAM_RAM_SHIFT)) & TX_PACKET_RAM_PACKET_RAM_RAM_MASK)
/*! @} */

/* The count of TX_PACKET_RAM_PACKET_RAM */
#define TX_PACKET_RAM_PACKET_RAM_COUNT           (1024U)


/*!
 * @}
 */ /* end of group TX_PACKET_RAM_Register_Masks */


/* TX_PACKET_RAM - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral TX_PACKET_RAM base address */
  #define TX_PACKET_RAM_BASE                       (0x58A08000u)
  /** Peripheral TX_PACKET_RAM base address */
  #define TX_PACKET_RAM_BASE_NS                    (0x48A08000u)
  /** Peripheral TX_PACKET_RAM base pointer */
  #define TX_PACKET_RAM                            ((TX_PACKET_RAM_Type *)TX_PACKET_RAM_BASE)
  /** Peripheral TX_PACKET_RAM base pointer */
  #define TX_PACKET_RAM_NS                         ((TX_PACKET_RAM_Type *)TX_PACKET_RAM_BASE_NS)
  /** Array initializer of TX_PACKET_RAM peripheral base addresses */
  #define TX_PACKET_RAM_BASE_ADDRS                 { TX_PACKET_RAM_BASE }
  /** Array initializer of TX_PACKET_RAM peripheral base pointers */
  #define TX_PACKET_RAM_BASE_PTRS                  { TX_PACKET_RAM }
  /** Array initializer of TX_PACKET_RAM peripheral base addresses */
  #define TX_PACKET_RAM_BASE_ADDRS_NS              { TX_PACKET_RAM_BASE_NS }
  /** Array initializer of TX_PACKET_RAM peripheral base pointers */
  #define TX_PACKET_RAM_BASE_PTRS_NS               { TX_PACKET_RAM_NS }
#else
  /** Peripheral TX_PACKET_RAM base address */
  #define TX_PACKET_RAM_BASE                       (0x48A08000u)
  /** Peripheral TX_PACKET_RAM base pointer */
  #define TX_PACKET_RAM                            ((TX_PACKET_RAM_Type *)TX_PACKET_RAM_BASE)
  /** Array initializer of TX_PACKET_RAM peripheral base addresses */
  #define TX_PACKET_RAM_BASE_ADDRS                 { TX_PACKET_RAM_BASE }
  /** Array initializer of TX_PACKET_RAM peripheral base pointers */
  #define TX_PACKET_RAM_BASE_PTRS                  { TX_PACKET_RAM }
#endif

/*!
 * @}
 */ /* end of group TX_PACKET_RAM_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- VBAT Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup VBAT_Peripheral_Access_Layer VBAT Peripheral Access Layer
 * @{
 */

/** VBAT - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
       uint8_t RESERVED_0[12];
  __IO uint32_t STATUSA;                           /**< Status A, offset: 0x10 */
       uint8_t RESERVED_1[4];
  __IO uint32_t IRQENA;                            /**< Interrupt Enable A, offset: 0x18 */
       uint8_t RESERVED_2[4];
  __IO uint32_t WAKENA;                            /**< Wakeup Enable A, offset: 0x20 */
       uint8_t RESERVED_3[12];
  __IO uint32_t LOCKA;                             /**< Lock A, offset: 0x30 */
       uint8_t RESERVED_4[460];
  __IO uint32_t FROCTLA;                           /**< FRO16K Control A, offset: 0x200 */
       uint8_t RESERVED_5[20];
  __IO uint32_t FROLCKA;                           /**< FRO16K Lock A, offset: 0x218 */
       uint8_t RESERVED_6[4];
  __IO uint32_t FROCLKE;                           /**< FRO16K Clock Enable, offset: 0x220 */
       uint8_t RESERVED_7[220];
  __IO uint32_t LDOCTLA;                           /**< LDO_RAM Control A, offset: 0x300 */
       uint8_t RESERVED_8[20];
  __IO uint32_t LDOLCKA;                           /**< LDO_RAM Lock A, offset: 0x318 */
       uint8_t RESERVED_9[4];
  __IO uint32_t LDORAMC;                           /**< RAM Control, offset: 0x320 */
       uint8_t RESERVED_10[12];
  __IO uint32_t LDOTIMER0;                         /**< Bandgap Timer 0, offset: 0x330 */
       uint8_t RESERVED_11[4];
  __IO uint32_t LDOTIMER1;                         /**< Bandgap Timer 1, offset: 0x338 */
} VBAT_Type;

/* ----------------------------------------------------------------------------
   -- VBAT Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup VBAT_Register_Masks VBAT Register Masks
 * @{
 */

/*! @name VERID - Version ID */
/*! @{ */

#define VBAT_VERID_FEATURE_MASK                  (0xFFFFU)
#define VBAT_VERID_FEATURE_SHIFT                 (0U)
/*! FEATURE - Feature Specification Number
 */
#define VBAT_VERID_FEATURE(x)                    (((uint32_t)(((uint32_t)(x)) << VBAT_VERID_FEATURE_SHIFT)) & VBAT_VERID_FEATURE_MASK)

#define VBAT_VERID_MINOR_MASK                    (0xFF0000U)
#define VBAT_VERID_MINOR_SHIFT                   (16U)
/*! MINOR - Minor Version Number
 */
#define VBAT_VERID_MINOR(x)                      (((uint32_t)(((uint32_t)(x)) << VBAT_VERID_MINOR_SHIFT)) & VBAT_VERID_MINOR_MASK)

#define VBAT_VERID_MAJOR_MASK                    (0xFF000000U)
#define VBAT_VERID_MAJOR_SHIFT                   (24U)
/*! MAJOR - Major Version Number
 */
#define VBAT_VERID_MAJOR(x)                      (((uint32_t)(((uint32_t)(x)) << VBAT_VERID_MAJOR_SHIFT)) & VBAT_VERID_MAJOR_MASK)
/*! @} */

/*! @name STATUSA - Status A */
/*! @{ */

#define VBAT_STATUSA_POR_DET_MASK                (0x1U)
#define VBAT_STATUSA_POR_DET_SHIFT               (0U)
/*! POR_DET - POR Detect
 *  0b0..VBAT domain has not been reset
 *  0b1..VBAT domain has been reset
 */
#define VBAT_STATUSA_POR_DET(x)                  (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_POR_DET_SHIFT)) & VBAT_STATUSA_POR_DET_MASK)

#define VBAT_STATUSA_WAKEUP_FLAG_MASK            (0x2U)
#define VBAT_STATUSA_WAKEUP_FLAG_SHIFT           (1U)
/*! WAKEUP_FLAG - Wakeup Pin Flag
 *  0b0..Wakeup pin not asserted
 *  0b1..Wakeup pin asserted
 */
#define VBAT_STATUSA_WAKEUP_FLAG(x)              (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_WAKEUP_FLAG_SHIFT)) & VBAT_STATUSA_WAKEUP_FLAG_MASK)

#define VBAT_STATUSA_TIMER0_FLAG_MASK            (0x4U)
#define VBAT_STATUSA_TIMER0_FLAG_SHIFT           (2U)
/*! TIMER0_FLAG - Bandgap Timer 0
 *  0b0..Timeout 0 period not reached
 *  0b1..Timeout 0 period reached
 */
#define VBAT_STATUSA_TIMER0_FLAG(x)              (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_TIMER0_FLAG_SHIFT)) & VBAT_STATUSA_TIMER0_FLAG_MASK)

#define VBAT_STATUSA_TIMER1_FLAG_MASK            (0x8U)
#define VBAT_STATUSA_TIMER1_FLAG_SHIFT           (3U)
/*! TIMER1_FLAG - Bandgap Timer 1
 *  0b0..Timeout 1 period not reached
 *  0b1..Timeout 1 period reached
 */
#define VBAT_STATUSA_TIMER1_FLAG(x)              (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_TIMER1_FLAG_SHIFT)) & VBAT_STATUSA_TIMER1_FLAG_MASK)

#define VBAT_STATUSA_LDO_RDY_MASK                (0x10U)
#define VBAT_STATUSA_LDO_RDY_SHIFT               (4U)
/*! LDO_RDY - LDO Ready
 *  0b0..LDO is disabled or not ready
 *  0b1..LDO is enabled and ready
 */
#define VBAT_STATUSA_LDO_RDY(x)                  (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_LDO_RDY_SHIFT)) & VBAT_STATUSA_LDO_RDY_MASK)
/*! @} */

/*! @name IRQENA - Interrupt Enable A */
/*! @{ */

#define VBAT_IRQENA_POR_DET_MASK                 (0x1U)
#define VBAT_IRQENA_POR_DET_SHIFT                (0U)
/*! POR_DET - POR Detect
 *  0b0..Interrupt disabled
 *  0b1..Interrupt enabled
 */
#define VBAT_IRQENA_POR_DET(x)                   (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_POR_DET_SHIFT)) & VBAT_IRQENA_POR_DET_MASK)

#define VBAT_IRQENA_WAKEUP_FLAG_MASK             (0x2U)
#define VBAT_IRQENA_WAKEUP_FLAG_SHIFT            (1U)
/*! WAKEUP_FLAG - Wakeup Pin Flag
 *  0b0..Interrupt disabled
 *  0b1..Interrupt enabled
 */
#define VBAT_IRQENA_WAKEUP_FLAG(x)               (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_WAKEUP_FLAG_SHIFT)) & VBAT_IRQENA_WAKEUP_FLAG_MASK)

#define VBAT_IRQENA_TIMER0_FLAG_MASK             (0x4U)
#define VBAT_IRQENA_TIMER0_FLAG_SHIFT            (2U)
/*! TIMER0_FLAG - Bandgap Timer 0
 *  0b0..Interrupt disabled
 *  0b1..Interrupt enabled
 */
#define VBAT_IRQENA_TIMER0_FLAG(x)               (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_TIMER0_FLAG_SHIFT)) & VBAT_IRQENA_TIMER0_FLAG_MASK)

#define VBAT_IRQENA_TIMER1_FLAG_MASK             (0x8U)
#define VBAT_IRQENA_TIMER1_FLAG_SHIFT            (3U)
/*! TIMER1_FLAG - Bandgap Timer 2
 *  0b0..Interrupt disabled
 *  0b1..Interrupt enabled
 */
#define VBAT_IRQENA_TIMER1_FLAG(x)               (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_TIMER1_FLAG_SHIFT)) & VBAT_IRQENA_TIMER1_FLAG_MASK)

#define VBAT_IRQENA_LDO_RDY_MASK                 (0x10U)
#define VBAT_IRQENA_LDO_RDY_SHIFT                (4U)
/*! LDO_RDY - LDO Ready
 *  0b0..Interrupt disabled
 *  0b1..Interrupt enabled
 */
#define VBAT_IRQENA_LDO_RDY(x)                   (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_LDO_RDY_SHIFT)) & VBAT_IRQENA_LDO_RDY_MASK)
/*! @} */

/*! @name WAKENA - Wakeup Enable A */
/*! @{ */

#define VBAT_WAKENA_POR_DET_MASK                 (0x1U)
#define VBAT_WAKENA_POR_DET_SHIFT                (0U)
/*! POR_DET - POR Detect
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define VBAT_WAKENA_POR_DET(x)                   (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_POR_DET_SHIFT)) & VBAT_WAKENA_POR_DET_MASK)

#define VBAT_WAKENA_WAKEUP_FLAG_MASK             (0x2U)
#define VBAT_WAKENA_WAKEUP_FLAG_SHIFT            (1U)
/*! WAKEUP_FLAG - Wakeup Pin Flag
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define VBAT_WAKENA_WAKEUP_FLAG(x)               (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_WAKEUP_FLAG_SHIFT)) & VBAT_WAKENA_WAKEUP_FLAG_MASK)

#define VBAT_WAKENA_TIMER0_FLAG_MASK             (0x4U)
#define VBAT_WAKENA_TIMER0_FLAG_SHIFT            (2U)
/*! TIMER0_FLAG - Bandgap Timer 0
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define VBAT_WAKENA_TIMER0_FLAG(x)               (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_TIMER0_FLAG_SHIFT)) & VBAT_WAKENA_TIMER0_FLAG_MASK)

#define VBAT_WAKENA_TIMER1_FLAG_MASK             (0x8U)
#define VBAT_WAKENA_TIMER1_FLAG_SHIFT            (3U)
/*! TIMER1_FLAG - Bandgap Timer 2
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define VBAT_WAKENA_TIMER1_FLAG(x)               (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_TIMER1_FLAG_SHIFT)) & VBAT_WAKENA_TIMER1_FLAG_MASK)

#define VBAT_WAKENA_LDO_RDY_MASK                 (0x10U)
#define VBAT_WAKENA_LDO_RDY_SHIFT                (4U)
/*! LDO_RDY - LDO Ready
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define VBAT_WAKENA_LDO_RDY(x)                   (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_LDO_RDY_SHIFT)) & VBAT_WAKENA_LDO_RDY_MASK)
/*! @} */

/*! @name LOCKA - Lock A */
/*! @{ */

#define VBAT_LOCKA_LOCK_MASK                     (0x1U)
#define VBAT_LOCKA_LOCK_SHIFT                    (0U)
/*! LOCK - Lock
 *  0b0..Disables lock
 *  0b1..Enables lock. Cleared by VBAT POR.
 */
#define VBAT_LOCKA_LOCK(x)                       (((uint32_t)(((uint32_t)(x)) << VBAT_LOCKA_LOCK_SHIFT)) & VBAT_LOCKA_LOCK_MASK)
/*! @} */

/*! @name FROCTLA - FRO16K Control A */
/*! @{ */

#define VBAT_FROCTLA_FRO_EN_MASK                 (0x1U)
#define VBAT_FROCTLA_FRO_EN_SHIFT                (0U)
/*! FRO_EN - FRO16K enable bit
 *  0b0..FRO16K is disabled
 *  0b1..FRO16K is enabled
 */
#define VBAT_FROCTLA_FRO_EN(x)                   (((uint32_t)(((uint32_t)(x)) << VBAT_FROCTLA_FRO_EN_SHIFT)) & VBAT_FROCTLA_FRO_EN_MASK)
/*! @} */

/*! @name FROLCKA - FRO16K Lock A */
/*! @{ */

#define VBAT_FROLCKA_LOCK_MASK                   (0x1U)
#define VBAT_FROLCKA_LOCK_SHIFT                  (0U)
/*! LOCK - Lock
 *  0b0..Disables lock
 *  0b1..Enables lock. Cleared by VBAT POR.
 */
#define VBAT_FROLCKA_LOCK(x)                     (((uint32_t)(((uint32_t)(x)) << VBAT_FROLCKA_LOCK_SHIFT)) & VBAT_FROLCKA_LOCK_MASK)
/*! @} */

/*! @name FROCLKE - FRO16K Clock Enable */
/*! @{ */

#define VBAT_FROCLKE_CLKE_MASK                   (0x1U)
#define VBAT_FROCLKE_CLKE_SHIFT                  (0U)
/*! CLKE - Clock Enable
 */
#define VBAT_FROCLKE_CLKE(x)                     (((uint32_t)(((uint32_t)(x)) << VBAT_FROCLKE_CLKE_SHIFT)) & VBAT_FROCLKE_CLKE_MASK)
/*! @} */

/*! @name LDOCTLA - LDO_RAM Control A */
/*! @{ */

#define VBAT_LDOCTLA_BG_EN_MASK                  (0x1U)
#define VBAT_LDOCTLA_BG_EN_SHIFT                 (0U)
/*! BG_EN - Bandgap Enable
 *  0b0..Bandgap is disabled
 *  0b1..Bandgap is enabled
 */
#define VBAT_LDOCTLA_BG_EN(x)                    (((uint32_t)(((uint32_t)(x)) << VBAT_LDOCTLA_BG_EN_SHIFT)) & VBAT_LDOCTLA_BG_EN_MASK)

#define VBAT_LDOCTLA_LDO_EN_MASK                 (0x2U)
#define VBAT_LDOCTLA_LDO_EN_SHIFT                (1U)
/*! LDO_EN - LDO Enable
 *  0b0..Regulator is disabled
 *  0b1..Regulator is enabled
 */
#define VBAT_LDOCTLA_LDO_EN(x)                   (((uint32_t)(((uint32_t)(x)) << VBAT_LDOCTLA_LDO_EN_SHIFT)) & VBAT_LDOCTLA_LDO_EN_MASK)

#define VBAT_LDOCTLA_REFRESH_EN_MASK             (0x4U)
#define VBAT_LDOCTLA_REFRESH_EN_SHIFT            (2U)
/*! REFRESH_EN - Refresh Enable
 *  0b0..Refresh mode is disabled
 *  0b1..Refresh mode is enabled
 */
#define VBAT_LDOCTLA_REFRESH_EN(x)               (((uint32_t)(((uint32_t)(x)) << VBAT_LDOCTLA_REFRESH_EN_SHIFT)) & VBAT_LDOCTLA_REFRESH_EN_MASK)
/*! @} */

/*! @name LDOLCKA - LDO_RAM Lock A */
/*! @{ */

#define VBAT_LDOLCKA_LOCK_MASK                   (0x1U)
#define VBAT_LDOLCKA_LOCK_SHIFT                  (0U)
/*! LOCK - Lock
 *  0b0..Disables lock
 *  0b1..Enables lock. Cleared by VBAT POR.
 */
#define VBAT_LDOLCKA_LOCK(x)                     (((uint32_t)(((uint32_t)(x)) << VBAT_LDOLCKA_LOCK_SHIFT)) & VBAT_LDOLCKA_LOCK_MASK)
/*! @} */

/*! @name LDORAMC - RAM Control */
/*! @{ */

#define VBAT_LDORAMC_ISO_MASK                    (0x1U)
#define VBAT_LDORAMC_ISO_SHIFT                   (0U)
/*! ISO - Isolate SRAM
 *  0b0..SRAM state follows the SoC power modes
 *  0b1..SRAM is isolated
 */
#define VBAT_LDORAMC_ISO(x)                      (((uint32_t)(((uint32_t)(x)) << VBAT_LDORAMC_ISO_SHIFT)) & VBAT_LDORAMC_ISO_MASK)

#define VBAT_LDORAMC_SWI_MASK                    (0x2U)
#define VBAT_LDORAMC_SWI_SHIFT                   (1U)
/*! SWI - Switch SRAM
 *  0b0..SRAM array supply follows the SoC power modes
 *  0b1..SRAM array is powered by LDO_RAM
 */
#define VBAT_LDORAMC_SWI(x)                      (((uint32_t)(((uint32_t)(x)) << VBAT_LDORAMC_SWI_SHIFT)) & VBAT_LDORAMC_SWI_MASK)

#define VBAT_LDORAMC_RET_MASK                    (0x100U)
#define VBAT_LDORAMC_RET_SHIFT                   (8U)
/*! RET - Retention
 *  0b0..SRAM array is retained in low power modes
 *  0b1..SRAM array is not retained in low power modes
 */
#define VBAT_LDORAMC_RET(x)                      (((uint32_t)(((uint32_t)(x)) << VBAT_LDORAMC_RET_SHIFT)) & VBAT_LDORAMC_RET_MASK)
/*! @} */

/*! @name LDOTIMER0 - Bandgap Timer 0 */
/*! @{ */

#define VBAT_LDOTIMER0_TIMCFG_MASK               (0x7U)
#define VBAT_LDOTIMER0_TIMCFG_SHIFT              (0U)
/*! TIMCFG - Timeout Configuration
 *  0b111..Timeout every 7.8125 ms
 *  0b110..Timeout every 15.625 ms
 *  0b101..Timeout every 31.25 ms
 *  0b100..Timeout every 62.5 ms
 *  0b011..Timeout every 125 ms
 *  0b010..Timeout every 250 ms
 *  0b001..Timeout every 500 ms
 *  0b000..Timeout every 1 sec
 */
#define VBAT_LDOTIMER0_TIMCFG(x)                 (((uint32_t)(((uint32_t)(x)) << VBAT_LDOTIMER0_TIMCFG_SHIFT)) & VBAT_LDOTIMER0_TIMCFG_MASK)

#define VBAT_LDOTIMER0_TIMEN_MASK                (0x80000000U)
#define VBAT_LDOTIMER0_TIMEN_SHIFT               (31U)
/*! TIMEN - Timeout Enable
 *  0b0..Timer is disabled
 *  0b1..Timer is enabled
 */
#define VBAT_LDOTIMER0_TIMEN(x)                  (((uint32_t)(((uint32_t)(x)) << VBAT_LDOTIMER0_TIMEN_SHIFT)) & VBAT_LDOTIMER0_TIMEN_MASK)
/*! @} */

/*! @name LDOTIMER1 - Bandgap Timer 1 */
/*! @{ */

#define VBAT_LDOTIMER1_TIMCFG_MASK               (0xFFFFFFU)
#define VBAT_LDOTIMER1_TIMCFG_SHIFT              (0U)
/*! TIMCFG - Timeout Configuration
 */
#define VBAT_LDOTIMER1_TIMCFG(x)                 (((uint32_t)(((uint32_t)(x)) << VBAT_LDOTIMER1_TIMCFG_SHIFT)) & VBAT_LDOTIMER1_TIMCFG_MASK)

#define VBAT_LDOTIMER1_TIMEN_MASK                (0x80000000U)
#define VBAT_LDOTIMER1_TIMEN_SHIFT               (31U)
/*! TIMEN - Timeout Enable
 *  0b0..Timer is disabled
 *  0b1..Timer is enabled
 */
#define VBAT_LDOTIMER1_TIMEN(x)                  (((uint32_t)(((uint32_t)(x)) << VBAT_LDOTIMER1_TIMEN_SHIFT)) & VBAT_LDOTIMER1_TIMEN_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group VBAT_Register_Masks */


/* VBAT - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral VBAT0 base address */
  #define VBAT0_BASE                               (0x5002B000u)
  /** Peripheral VBAT0 base address */
  #define VBAT0_BASE_NS                            (0x4002B000u)
  /** Peripheral VBAT0 base pointer */
  #define VBAT0                                    ((VBAT_Type *)VBAT0_BASE)
  /** Peripheral VBAT0 base pointer */
  #define VBAT0_NS                                 ((VBAT_Type *)VBAT0_BASE_NS)
  /** Array initializer of VBAT peripheral base addresses */
  #define VBAT_BASE_ADDRS                          { VBAT0_BASE }
  /** Array initializer of VBAT peripheral base pointers */
  #define VBAT_BASE_PTRS                           { VBAT0 }
  /** Array initializer of VBAT peripheral base addresses */
  #define VBAT_BASE_ADDRS_NS                       { VBAT0_BASE_NS }
  /** Array initializer of VBAT peripheral base pointers */
  #define VBAT_BASE_PTRS_NS                        { VBAT0_NS }
#else
  /** Peripheral VBAT0 base address */
  #define VBAT0_BASE                               (0x4002B000u)
  /** Peripheral VBAT0 base pointer */
  #define VBAT0                                    ((VBAT_Type *)VBAT0_BASE)
  /** Array initializer of VBAT peripheral base addresses */
  #define VBAT_BASE_ADDRS                          { VBAT0_BASE }
  /** Array initializer of VBAT peripheral base pointers */
  #define VBAT_BASE_PTRS                           { VBAT0 }
#endif

/*!
 * @}
 */ /* end of group VBAT_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- VREF Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
 * @{
 */

/** VREF - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
       uint32_t PARAM;                             /**< Parameters, offset: 0x4 */
  __IO uint32_t CSR;                               /**< Control and Status, offset: 0x8 */
       uint8_t RESERVED_0[4];
  __IO uint32_t UTRIM;                             /**< User Trim, offset: 0x10 */
} VREF_Type;

/* ----------------------------------------------------------------------------
   -- VREF Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup VREF_Register_Masks VREF Register Masks
 * @{
 */

/*! @name VERID - Version ID */
/*! @{ */

#define VREF_VERID_FEATURE_MASK                  (0xFFFFU)
#define VREF_VERID_FEATURE_SHIFT                 (0U)
/*! FEATURE - Feature Specification Number
 */
#define VREF_VERID_FEATURE(x)                    (((uint32_t)(((uint32_t)(x)) << VREF_VERID_FEATURE_SHIFT)) & VREF_VERID_FEATURE_MASK)

#define VREF_VERID_MINOR_MASK                    (0xFF0000U)
#define VREF_VERID_MINOR_SHIFT                   (16U)
/*! MINOR - Minor Version Number
 */
#define VREF_VERID_MINOR(x)                      (((uint32_t)(((uint32_t)(x)) << VREF_VERID_MINOR_SHIFT)) & VREF_VERID_MINOR_MASK)

#define VREF_VERID_MAJOR_MASK                    (0xFF000000U)
#define VREF_VERID_MAJOR_SHIFT                   (24U)
/*! MAJOR - Major Version Number
 */
#define VREF_VERID_MAJOR(x)                      (((uint32_t)(((uint32_t)(x)) << VREF_VERID_MAJOR_SHIFT)) & VREF_VERID_MAJOR_MASK)
/*! @} */

/*! @name CSR - Control and Status */
/*! @{ */

#define VREF_CSR_HCBGEN_MASK                     (0x1U)
#define VREF_CSR_HCBGEN_SHIFT                    (0U)
/*! HCBGEN - HC bandgap enabled
 *  0b0..Disables
 *  0b1..Enables
 */
#define VREF_CSR_HCBGEN(x)                       (((uint32_t)(((uint32_t)(x)) << VREF_CSR_HCBGEN_SHIFT)) & VREF_CSR_HCBGEN_MASK)

#define VREF_CSR_LPBGEN_MASK                     (0x2U)
#define VREF_CSR_LPBGEN_SHIFT                    (1U)
/*! LPBGEN - Low-power bandgap enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define VREF_CSR_LPBGEN(x)                       (((uint32_t)(((uint32_t)(x)) << VREF_CSR_LPBGEN_SHIFT)) & VREF_CSR_LPBGEN_MASK)

#define VREF_CSR_LPBG_BUF_EN_MASK                (0x4U)
#define VREF_CSR_LPBG_BUF_EN_SHIFT               (2U)
/*! LPBG_BUF_EN - Low-power bandgap buffer enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define VREF_CSR_LPBG_BUF_EN(x)                  (((uint32_t)(((uint32_t)(x)) << VREF_CSR_LPBG_BUF_EN_SHIFT)) & VREF_CSR_LPBG_BUF_EN_MASK)

#define VREF_CSR_CHOPEN_MASK                     (0x8U)
#define VREF_CSR_CHOPEN_SHIFT                    (3U)
/*! CHOPEN - Chop oscillator enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define VREF_CSR_CHOPEN(x)                       (((uint32_t)(((uint32_t)(x)) << VREF_CSR_CHOPEN_SHIFT)) & VREF_CSR_CHOPEN_MASK)

#define VREF_CSR_ICOMPEN_MASK                    (0x10U)
#define VREF_CSR_ICOMPEN_SHIFT                   (4U)
/*! ICOMPEN - Current compensation enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define VREF_CSR_ICOMPEN(x)                      (((uint32_t)(((uint32_t)(x)) << VREF_CSR_ICOMPEN_SHIFT)) & VREF_CSR_ICOMPEN_MASK)

#define VREF_CSR_REGEN_MASK                      (0x20U)
#define VREF_CSR_REGEN_SHIFT                     (5U)
/*! REGEN - Regulator enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define VREF_CSR_REGEN(x)                        (((uint32_t)(((uint32_t)(x)) << VREF_CSR_REGEN_SHIFT)) & VREF_CSR_REGEN_MASK)

#define VREF_CSR_REFCHSELN_EN_MASK               (0x40U)
#define VREF_CSR_REFCHSELN_EN_SHIFT              (6U)
/*! REFCHSELN_EN - Reference channel select negative enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define VREF_CSR_REFCHSELN_EN(x)                 (((uint32_t)(((uint32_t)(x)) << VREF_CSR_REFCHSELN_EN_SHIFT)) & VREF_CSR_REFCHSELN_EN_MASK)

#define VREF_CSR_REFCHSELP_EN_MASK               (0x80U)
#define VREF_CSR_REFCHSELP_EN_SHIFT              (7U)
/*! REFCHSELP_EN - Reference channel select positive enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define VREF_CSR_REFCHSELP_EN(x)                 (((uint32_t)(((uint32_t)(x)) << VREF_CSR_REFCHSELP_EN_SHIFT)) & VREF_CSR_REFCHSELP_EN_MASK)

#define VREF_CSR_VRSEL_MASK                      (0x300U)
#define VREF_CSR_VRSEL_SHIFT                     (8U)
/*! VRSEL - Voltage reference selection
 *  0b00..Internal bandgap
 *  0b01..Low power buffered 1v
 *  0b10..Buffer 2.1v output
 */
#define VREF_CSR_VRSEL(x)                        (((uint32_t)(((uint32_t)(x)) << VREF_CSR_VRSEL_SHIFT)) & VREF_CSR_VRSEL_MASK)

#define VREF_CSR_REFL_GRD_SEL_MASK               (0x400U)
#define VREF_CSR_REFL_GRD_SEL_SHIFT              (10U)
/*! REFL_GRD_SEL - Ground select
 *  0b0..vrefl_3v
 *  0b1..vssa
 */
#define VREF_CSR_REFL_GRD_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << VREF_CSR_REFL_GRD_SEL_SHIFT)) & VREF_CSR_REFL_GRD_SEL_MASK)

#define VREF_CSR_HI_PWR_LV_MASK                  (0x800U)
#define VREF_CSR_HI_PWR_LV_SHIFT                 (11U)
/*! HI_PWR_LV - High power level
 *  0b0..Low power
 *  0b1..High power
 */
#define VREF_CSR_HI_PWR_LV(x)                    (((uint32_t)(((uint32_t)(x)) << VREF_CSR_HI_PWR_LV_SHIFT)) & VREF_CSR_HI_PWR_LV_MASK)

#define VREF_CSR_BUF21EN_MASK                    (0x10000U)
#define VREF_CSR_BUF21EN_SHIFT                   (16U)
/*! BUF21EN - Internal Buffer21 enable
 *  0b0..Disables
 *  0b1..Enables
 */
#define VREF_CSR_BUF21EN(x)                      (((uint32_t)(((uint32_t)(x)) << VREF_CSR_BUF21EN_SHIFT)) & VREF_CSR_BUF21EN_MASK)

#define VREF_CSR_VREFST_MASK                     (0x80000000U)
#define VREF_CSR_VREFST_SHIFT                    (31U)
/*! VREFST - Internal HC Voltage Reference stable
 *  0b0..The module is disabled or not stable.
 *  0b1..The module is stable.
 */
#define VREF_CSR_VREFST(x)                       (((uint32_t)(((uint32_t)(x)) << VREF_CSR_VREFST_SHIFT)) & VREF_CSR_VREFST_MASK)
/*! @} */

/*! @name UTRIM - User Trim */
/*! @{ */

#define VREF_UTRIM_TRIM2V1_MASK                  (0xFU)
#define VREF_UTRIM_TRIM2V1_SHIFT                 (0U)
/*! TRIM2V1 - VREF 2.1V trim
 */
#define VREF_UTRIM_TRIM2V1(x)                    (((uint32_t)(((uint32_t)(x)) << VREF_UTRIM_TRIM2V1_SHIFT)) & VREF_UTRIM_TRIM2V1_MASK)

#define VREF_UTRIM_VREFTRIM_MASK                 (0x3F00U)
#define VREF_UTRIM_VREFTRIM_SHIFT                (8U)
/*! VREFTRIM - VREF trim
 */
#define VREF_UTRIM_VREFTRIM(x)                   (((uint32_t)(((uint32_t)(x)) << VREF_UTRIM_VREFTRIM_SHIFT)) & VREF_UTRIM_VREFTRIM_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group VREF_Register_Masks */


/* VREF - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral VREF0 base address */
  #define VREF0_BASE                               (0x5004A000u)
  /** Peripheral VREF0 base address */
  #define VREF0_BASE_NS                            (0x4004A000u)
  /** Peripheral VREF0 base pointer */
  #define VREF0                                    ((VREF_Type *)VREF0_BASE)
  /** Peripheral VREF0 base pointer */
  #define VREF0_NS                                 ((VREF_Type *)VREF0_BASE_NS)
  /** Array initializer of VREF peripheral base addresses */
  #define VREF_BASE_ADDRS                          { VREF0_BASE }
  /** Array initializer of VREF peripheral base pointers */
  #define VREF_BASE_PTRS                           { VREF0 }
  /** Array initializer of VREF peripheral base addresses */
  #define VREF_BASE_ADDRS_NS                       { VREF0_BASE_NS }
  /** Array initializer of VREF peripheral base pointers */
  #define VREF_BASE_PTRS_NS                        { VREF0_NS }
#else
  /** Peripheral VREF0 base address */
  #define VREF0_BASE                               (0x4004A000u)
  /** Peripheral VREF0 base pointer */
  #define VREF0                                    ((VREF_Type *)VREF0_BASE)
  /** Array initializer of VREF peripheral base addresses */
  #define VREF_BASE_ADDRS                          { VREF0_BASE }
  /** Array initializer of VREF peripheral base pointers */
  #define VREF_BASE_PTRS                           { VREF0 }
#endif

/*!
 * @}
 */ /* end of group VREF_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- WDOG Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
 * @{
 */

/** WDOG - Register Layout Typedef */
typedef struct {
  __IO uint32_t CS;                                /**< Watchdog Control and Status Register, offset: 0x0 */
  __IO uint32_t CNT;                               /**< Watchdog Counter Register, offset: 0x4 */
  __IO uint32_t TOVAL;                             /**< Watchdog Timeout Value Register, offset: 0x8 */
  __IO uint32_t WIN;                               /**< Watchdog Window Register, offset: 0xC */
} WDOG_Type;

/* ----------------------------------------------------------------------------
   -- WDOG Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup WDOG_Register_Masks WDOG Register Masks
 * @{
 */

/*! @name CS - Watchdog Control and Status Register */
/*! @{ */

#define WDOG_CS_STOP_MASK                        (0x1U)
#define WDOG_CS_STOP_SHIFT                       (0U)
/*! STOP - Stop Enable
 *  0b0..Watchdog disabled in chip stop mode.
 *  0b1..Watchdog enabled in chip stop mode.
 */
#define WDOG_CS_STOP(x)                          (((uint32_t)(((uint32_t)(x)) << WDOG_CS_STOP_SHIFT)) & WDOG_CS_STOP_MASK)

#define WDOG_CS_WAIT_MASK                        (0x2U)
#define WDOG_CS_WAIT_SHIFT                       (1U)
/*! WAIT - Wait Enable
 *  0b0..Watchdog disabled in chip wait mode.
 *  0b1..Watchdog enabled in chip wait mode.
 */
#define WDOG_CS_WAIT(x)                          (((uint32_t)(((uint32_t)(x)) << WDOG_CS_WAIT_SHIFT)) & WDOG_CS_WAIT_MASK)

#define WDOG_CS_DBG_MASK                         (0x4U)
#define WDOG_CS_DBG_SHIFT                        (2U)
/*! DBG - Debug Enable
 *  0b0..Watchdog disabled in chip debug mode.
 *  0b1..Watchdog enabled in chip debug mode.
 */
#define WDOG_CS_DBG(x)                           (((uint32_t)(((uint32_t)(x)) << WDOG_CS_DBG_SHIFT)) & WDOG_CS_DBG_MASK)

#define WDOG_CS_TST_MASK                         (0x18U)
#define WDOG_CS_TST_SHIFT                        (3U)
/*! TST - Watchdog Test
 *  0b00..Watchdog test mode disabled.
 *  0b01..Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should
 *        use this setting to indicate that the watchdog is functioning normally in user mode.
 *  0b10..Watchdog test mode enabled, only the low byte is used. CNT[CNTLOW] is compared with TOVAL[TOVALLOW].
 *  0b11..Watchdog test mode enabled, only the high byte is used. CNT[CNTHIGH] is compared with TOVAL[TOVALHIGH].
 */
#define WDOG_CS_TST(x)                           (((uint32_t)(((uint32_t)(x)) << WDOG_CS_TST_SHIFT)) & WDOG_CS_TST_MASK)

#define WDOG_CS_UPDATE_MASK                      (0x20U)
#define WDOG_CS_UPDATE_SHIFT                     (5U)
/*! UPDATE - Allow updates
 *  0b0..Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset.
 *  0b1..Updates allowed. Software can modify the watchdog configuration registers within 128 bus clocks after performing the unlock write sequence.
 */
#define WDOG_CS_UPDATE(x)                        (((uint32_t)(((uint32_t)(x)) << WDOG_CS_UPDATE_SHIFT)) & WDOG_CS_UPDATE_MASK)

#define WDOG_CS_INT_MASK                         (0x40U)
#define WDOG_CS_INT_SHIFT                        (6U)
/*! INT - Watchdog Interrupt
 *  0b0..Watchdog interrupts are disabled. Watchdog resets are not delayed.
 *  0b1..Watchdog interrupts are enabled. Watchdog resets are delayed by 128 bus clocks from the interrupt vector fetch.
 */
#define WDOG_CS_INT(x)                           (((uint32_t)(((uint32_t)(x)) << WDOG_CS_INT_SHIFT)) & WDOG_CS_INT_MASK)

#define WDOG_CS_EN_MASK                          (0x80U)
#define WDOG_CS_EN_SHIFT                         (7U)
/*! EN - Watchdog Enable
 *  0b0..Watchdog disabled.
 *  0b1..Watchdog enabled.
 */
#define WDOG_CS_EN(x)                            (((uint32_t)(((uint32_t)(x)) << WDOG_CS_EN_SHIFT)) & WDOG_CS_EN_MASK)

#define WDOG_CS_CLK_MASK                         (0x300U)
#define WDOG_CS_CLK_SHIFT                        (8U)
/*! CLK - Watchdog Clock
 */
#define WDOG_CS_CLK(x)                           (((uint32_t)(((uint32_t)(x)) << WDOG_CS_CLK_SHIFT)) & WDOG_CS_CLK_MASK)

#define WDOG_CS_RCS_MASK                         (0x400U)
#define WDOG_CS_RCS_SHIFT                        (10U)
/*! RCS - Reconfiguration Success
 *  0b0..Reconfiguring WDOG.
 *  0b1..Reconfiguration is successful.
 */
#define WDOG_CS_RCS(x)                           (((uint32_t)(((uint32_t)(x)) << WDOG_CS_RCS_SHIFT)) & WDOG_CS_RCS_MASK)

#define WDOG_CS_ULK_MASK                         (0x800U)
#define WDOG_CS_ULK_SHIFT                        (11U)
/*! ULK - Unlock status
 *  0b0..WDOG is locked.
 *  0b1..WDOG is unlocked.
 */
#define WDOG_CS_ULK(x)                           (((uint32_t)(((uint32_t)(x)) << WDOG_CS_ULK_SHIFT)) & WDOG_CS_ULK_MASK)

#define WDOG_CS_PRES_MASK                        (0x1000U)
#define WDOG_CS_PRES_SHIFT                       (12U)
/*! PRES - Watchdog prescaler
 *  0b0..256 prescaler disabled.
 *  0b1..256 prescaler enabled.
 */
#define WDOG_CS_PRES(x)                          (((uint32_t)(((uint32_t)(x)) << WDOG_CS_PRES_SHIFT)) & WDOG_CS_PRES_MASK)

#define WDOG_CS_CMD32EN_MASK                     (0x2000U)
#define WDOG_CS_CMD32EN_SHIFT                    (13U)
/*! CMD32EN - Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words
 *  0b0..Disables support for 32-bit refresh/unlock command write words. Only 16-bit or 8-bit is supported.
 *  0b1..Enables support for 32-bit refresh/unlock command write words. 16-bit or 8-bit is NOT supported.
 */
#define WDOG_CS_CMD32EN(x)                       (((uint32_t)(((uint32_t)(x)) << WDOG_CS_CMD32EN_SHIFT)) & WDOG_CS_CMD32EN_MASK)

#define WDOG_CS_FLG_MASK                         (0x4000U)
#define WDOG_CS_FLG_SHIFT                        (14U)
/*! FLG - Watchdog Interrupt Flag
 *  0b0..No interrupt occurred.
 *  0b1..An interrupt occurred.
 */
#define WDOG_CS_FLG(x)                           (((uint32_t)(((uint32_t)(x)) << WDOG_CS_FLG_SHIFT)) & WDOG_CS_FLG_MASK)

#define WDOG_CS_WIN_MASK                         (0x8000U)
#define WDOG_CS_WIN_SHIFT                        (15U)
/*! WIN - Watchdog Window
 *  0b0..Window mode disabled.
 *  0b1..Window mode enabled.
 */
#define WDOG_CS_WIN(x)                           (((uint32_t)(((uint32_t)(x)) << WDOG_CS_WIN_SHIFT)) & WDOG_CS_WIN_MASK)
/*! @} */

/*! @name CNT - Watchdog Counter Register */
/*! @{ */

#define WDOG_CNT_CNTLOW_MASK                     (0xFFU)
#define WDOG_CNT_CNTLOW_SHIFT                    (0U)
/*! CNTLOW - Low byte of the Watchdog Counter
 */
#define WDOG_CNT_CNTLOW(x)                       (((uint32_t)(((uint32_t)(x)) << WDOG_CNT_CNTLOW_SHIFT)) & WDOG_CNT_CNTLOW_MASK)

#define WDOG_CNT_CNTHIGH_MASK                    (0xFF00U)
#define WDOG_CNT_CNTHIGH_SHIFT                   (8U)
/*! CNTHIGH - High byte of the Watchdog Counter
 */
#define WDOG_CNT_CNTHIGH(x)                      (((uint32_t)(((uint32_t)(x)) << WDOG_CNT_CNTHIGH_SHIFT)) & WDOG_CNT_CNTHIGH_MASK)
/*! @} */

/*! @name TOVAL - Watchdog Timeout Value Register */
/*! @{ */

#define WDOG_TOVAL_TOVALLOW_MASK                 (0xFFU)
#define WDOG_TOVAL_TOVALLOW_SHIFT                (0U)
/*! TOVALLOW - Low byte of the timeout value
 */
#define WDOG_TOVAL_TOVALLOW(x)                   (((uint32_t)(((uint32_t)(x)) << WDOG_TOVAL_TOVALLOW_SHIFT)) & WDOG_TOVAL_TOVALLOW_MASK)

#define WDOG_TOVAL_TOVALHIGH_MASK                (0xFF00U)
#define WDOG_TOVAL_TOVALHIGH_SHIFT               (8U)
/*! TOVALHIGH - High byte of the timeout value
 */
#define WDOG_TOVAL_TOVALHIGH(x)                  (((uint32_t)(((uint32_t)(x)) << WDOG_TOVAL_TOVALHIGH_SHIFT)) & WDOG_TOVAL_TOVALHIGH_MASK)
/*! @} */

/*! @name WIN - Watchdog Window Register */
/*! @{ */

#define WDOG_WIN_WINLOW_MASK                     (0xFFU)
#define WDOG_WIN_WINLOW_SHIFT                    (0U)
/*! WINLOW - Low byte of Watchdog Window
 */
#define WDOG_WIN_WINLOW(x)                       (((uint32_t)(((uint32_t)(x)) << WDOG_WIN_WINLOW_SHIFT)) & WDOG_WIN_WINLOW_MASK)

#define WDOG_WIN_WINHIGH_MASK                    (0xFF00U)
#define WDOG_WIN_WINHIGH_SHIFT                   (8U)
/*! WINHIGH - High byte of Watchdog Window
 */
#define WDOG_WIN_WINHIGH(x)                      (((uint32_t)(((uint32_t)(x)) << WDOG_WIN_WINHIGH_SHIFT)) & WDOG_WIN_WINHIGH_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group WDOG_Register_Masks */


/* WDOG - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral WDOG0 base address */
  #define WDOG0_BASE                               (0x5001A000u)
  /** Peripheral WDOG0 base address */
  #define WDOG0_BASE_NS                            (0x4001A000u)
  /** Peripheral WDOG0 base pointer */
  #define WDOG0                                    ((WDOG_Type *)WDOG0_BASE)
  /** Peripheral WDOG0 base pointer */
  #define WDOG0_NS                                 ((WDOG_Type *)WDOG0_BASE_NS)
  /** Peripheral WDOG1 base address */
  #define WDOG1_BASE                               (0x5001B000u)
  /** Peripheral WDOG1 base address */
  #define WDOG1_BASE_NS                            (0x4001B000u)
  /** Peripheral WDOG1 base pointer */
  #define WDOG1                                    ((WDOG_Type *)WDOG1_BASE)
  /** Peripheral WDOG1 base pointer */
  #define WDOG1_NS                                 ((WDOG_Type *)WDOG1_BASE_NS)
  /** Array initializer of WDOG peripheral base addresses */
  #define WDOG_BASE_ADDRS                          { WDOG0_BASE, WDOG1_BASE }
  /** Array initializer of WDOG peripheral base pointers */
  #define WDOG_BASE_PTRS                           { WDOG0, WDOG1 }
  /** Array initializer of WDOG peripheral base addresses */
  #define WDOG_BASE_ADDRS_NS                       { WDOG0_BASE_NS, WDOG1_BASE_NS }
  /** Array initializer of WDOG peripheral base pointers */
  #define WDOG_BASE_PTRS_NS                        { WDOG0_NS, WDOG1_NS }
#else
  /** Peripheral WDOG0 base address */
  #define WDOG0_BASE                               (0x4001A000u)
  /** Peripheral WDOG0 base pointer */
  #define WDOG0                                    ((WDOG_Type *)WDOG0_BASE)
  /** Peripheral WDOG1 base address */
  #define WDOG1_BASE                               (0x4001B000u)
  /** Peripheral WDOG1 base pointer */
  #define WDOG1                                    ((WDOG_Type *)WDOG1_BASE)
  /** Array initializer of WDOG peripheral base addresses */
  #define WDOG_BASE_ADDRS                          { WDOG0_BASE, WDOG1_BASE }
  /** Array initializer of WDOG peripheral base pointers */
  #define WDOG_BASE_PTRS                           { WDOG0, WDOG1 }
#endif
/* Extra definition */
#define WDOG_UPDATE_KEY                          (0xD928C520U)
#define WDOG_REFRESH_KEY                         (0xB480A602U)


/*!
 * @}
 */ /* end of group WDOG_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- WOR Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup WOR_Peripheral_Access_Layer WOR Peripheral Access Layer
 * @{
 */

/** WOR - Register Layout Typedef */
typedef struct {
  __IO uint32_t CTRL;                              /**< WAKE-ON-RADIO CONTROL REGISTER, offset: 0x0 */
  __IO uint32_t TIMEOUT;                           /**< WAKE-ON-RADIO TIMEOUT REGISTER, offset: 0x4 */
  __I  uint32_t TIMESTAMP1;                        /**< WAKE-ON-RADIO TIMESTAMP 1, offset: 0x8 */
  __I  uint32_t TIMESTAMP2;                        /**< WAKE-ON-RADIO TIMESTAMP 2, offset: 0xC */
  __I  uint32_t TIMESTAMP3;                        /**< WAKE-ON-RADIO TIMESTAMP 3, offset: 0x10 */
  __IO uint32_t STATUS;                            /**< WAKE-ON-RADIO STATUS REGISTER, offset: 0x14 */
  __IO uint32_t WW_CTRL;                           /**< WINDOW-WIDENING CONTROL REGISTER, offset: 0x18 */
  __IO uint32_t HOP_CTRL;                          /**< FREQUENCY HOP CONTROL REGISTER, offset: 0x1C */
  __IO uint32_t SLOT0_DESC0;                       /**< SLOT 0 DESCRIPTOR (LSB), offset: 0x20 */
  __IO uint32_t SLOT0_DESC1;                       /**< SLOT 0 DESCRIPTOR (MSB), offset: 0x24 */
  __IO uint32_t SLOT1_DESC0;                       /**< SLOT 1 DESCRIPTOR (LSB), offset: 0x28 */
  __IO uint32_t SLOT1_DESC1;                       /**< SLOT 1 DESCRIPTOR (MSB), offset: 0x2C */
  __IO uint32_t SLOT2_DESC0;                       /**< SLOT 2 DESCRIPTOR (LSB), offset: 0x30 */
  __IO uint32_t SLOT2_DESC1;                       /**< SLOT 2 DESCRIPTOR (MSB), offset: 0x34 */
  __IO uint32_t SLOT3_DESC0;                       /**< SLOT 3 DESCRIPTOR (LSB), offset: 0x38 */
  __IO uint32_t SLOT3_DESC1;                       /**< SLOT 3 DESCRIPTOR (MSB), offset: 0x3C */
  __IO uint32_t AUTO_DRIFT1;                       /**< Auto Drift Calculation Register 1, offset: 0x40 */
  __IO uint32_t AUTO_DRIFT2;                       /**< Auto Drift Calculation Register 2, offset: 0x44 */
  __IO uint32_t AUTO_DRIFT3;                       /**< Auto Drift Calculation Register 3, offset: 0x48 */
  __IO uint32_t AUTO_DRIFT4;                       /**< Auto Drift Calculation Register 4, offset: 0x4C */
       uint8_t RESERVED_0[72];
  __I  uint32_t TIME;                              /**< Timer Count, offset: 0x98 */
  __I  uint32_t ENTER_TIME_CAPT;                   /**< MAN Low Power Entry Time Captured, offset: 0x9C */
  __I  uint32_t WKUP_TIME_CAPT;                    /**< MAN Low Power Wakeup Time Captured, offset: 0xA0 */
  __IO uint32_t ENTER_TIME;                        /**< MAN Low Power Entry Time Stamp, offset: 0xA4 */
  __IO uint32_t WKUP_TIME;                         /**< MAN Low Power Wakeup Time Stamp, offset: 0xA8 */
} WOR_Type;

/* ----------------------------------------------------------------------------
   -- WOR Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup WOR_Register_Masks WOR Register Masks
 * @{
 */

/*! @name CTRL - WAKE-ON-RADIO CONTROL REGISTER */
/*! @{ */

#define WOR_CTRL_WOR_EN_MASK                     (0x1U)
#define WOR_CTRL_WOR_EN_SHIFT                    (0U)
/*! WOR_EN - WAKE-ON-RADIO Enable
 */
#define WOR_CTRL_WOR_EN(x)                       (((uint32_t)(((uint32_t)(x)) << WOR_CTRL_WOR_EN_SHIFT)) & WOR_CTRL_WOR_EN_MASK)

#define WOR_CTRL_SCHEDULING_MODE_MASK            (0x2U)
#define WOR_CTRL_SCHEDULING_MODE_SHIFT           (1U)
/*! SCHEDULING_MODE - WAKE-ON-RADIO Scheduling Mode
 */
#define WOR_CTRL_SCHEDULING_MODE(x)              (((uint32_t)(((uint32_t)(x)) << WOR_CTRL_SCHEDULING_MODE_SHIFT)) & WOR_CTRL_SCHEDULING_MODE_MASK)

#define WOR_CTRL_WOR_PROTOCOL_MASK               (0xCU)
#define WOR_CTRL_WOR_PROTOCOL_SHIFT              (2U)
/*! WOR_PROTOCOL - WAKE-ON-RADIO Protocol Selector
 */
#define WOR_CTRL_WOR_PROTOCOL(x)                 (((uint32_t)(((uint32_t)(x)) << WOR_CTRL_WOR_PROTOCOL_SHIFT)) & WOR_CTRL_WOR_PROTOCOL_MASK)

#define WOR_CTRL_SLOTS_USED_MASK                 (0x70U)
#define WOR_CTRL_SLOTS_USED_SHIFT                (4U)
/*! SLOTS_USED - WAKE-ON-RADIO Number Of Slots Used
 */
#define WOR_CTRL_SLOTS_USED(x)                   (((uint32_t)(((uint32_t)(x)) << WOR_CTRL_SLOTS_USED_SHIFT)) & WOR_CTRL_SLOTS_USED_MASK)

#define WOR_CTRL_SKIP_FIRST_DSM_MASK             (0x80U)
#define WOR_CTRL_SKIP_FIRST_DSM_SHIFT            (7U)
/*! SKIP_FIRST_DSM - WAKE-ON-RADIO Skip DSM On First Slot
 */
#define WOR_CTRL_SKIP_FIRST_DSM(x)               (((uint32_t)(((uint32_t)(x)) << WOR_CTRL_SKIP_FIRST_DSM_SHIFT)) & WOR_CTRL_SKIP_FIRST_DSM_MASK)

#define WOR_CTRL_MAN_DSM_SEL_MASK                (0x300U)
#define WOR_CTRL_MAN_DSM_SEL_SHIFT               (8U)
/*! MAN_DSM_SEL - Manual DSM Selector
 */
#define WOR_CTRL_MAN_DSM_SEL(x)                  (((uint32_t)(((uint32_t)(x)) << WOR_CTRL_MAN_DSM_SEL_SHIFT)) & WOR_CTRL_MAN_DSM_SEL_MASK)

#define WOR_CTRL_RX_SLOT_FAIL_THRESH_MASK        (0x7C00U)
#define WOR_CTRL_RX_SLOT_FAIL_THRESH_SHIFT       (10U)
/*! RX_SLOT_FAIL_THRESH - RX Slot Fail Thresh
 */
#define WOR_CTRL_RX_SLOT_FAIL_THRESH(x)          (((uint32_t)(((uint32_t)(x)) << WOR_CTRL_RX_SLOT_FAIL_THRESH_SHIFT)) & WOR_CTRL_RX_SLOT_FAIL_THRESH_MASK)

#define WOR_CTRL_DSM_GUARDBAND_MASK              (0xF0000U)
#define WOR_CTRL_DSM_GUARDBAND_SHIFT             (16U)
/*! DSM_GUARDBAND - WAKE-ON-RADIO DSM Guardband
 */
#define WOR_CTRL_DSM_GUARDBAND(x)                (((uint32_t)(((uint32_t)(x)) << WOR_CTRL_DSM_GUARDBAND_SHIFT)) & WOR_CTRL_DSM_GUARDBAND_MASK)

#define WOR_CTRL_WOR_RESUME_MASK                 (0x1000000U)
#define WOR_CTRL_WOR_RESUME_SHIFT                (24U)
/*! WOR_RESUME - WAKE-ON-RADIO Resume
 */
#define WOR_CTRL_WOR_RESUME(x)                   (((uint32_t)(((uint32_t)(x)) << WOR_CTRL_WOR_RESUME_SHIFT)) & WOR_CTRL_WOR_RESUME_MASK)

#define WOR_CTRL_WOR_DEBUG_REG_MASK              (0x2000000U)
#define WOR_CTRL_WOR_DEBUG_REG_SHIFT             (25U)
/*! WOR_DEBUG_REG - WAKE-ON-RADIO Debug Register Enable
 */
#define WOR_CTRL_WOR_DEBUG_REG(x)                (((uint32_t)(((uint32_t)(x)) << WOR_CTRL_WOR_DEBUG_REG_SHIFT)) & WOR_CTRL_WOR_DEBUG_REG_MASK)

#define WOR_CTRL_AUTO_CAL_MASK                   (0x10000000U)
#define WOR_CTRL_AUTO_CAL_SHIFT                  (28U)
/*! AUTO_CAL - Auto calculate and track the drift enable
 */
#define WOR_CTRL_AUTO_CAL(x)                     (((uint32_t)(((uint32_t)(x)) << WOR_CTRL_AUTO_CAL_SHIFT)) & WOR_CTRL_AUTO_CAL_MASK)

#define WOR_CTRL_SW_CAL_MASK                     (0x20000000U)
#define WOR_CTRL_SW_CAL_SHIFT                    (29U)
/*! SW_CAL - Enable the WOR SW to calculate the drift. Only when AUTO_CAL is set.
 */
#define WOR_CTRL_SW_CAL(x)                       (((uint32_t)(((uint32_t)(x)) << WOR_CTRL_SW_CAL_SHIFT)) & WOR_CTRL_SW_CAL_MASK)

#define WOR_CTRL_TIME_REC_MASK                   (0x40000000U)
#define WOR_CTRL_TIME_REC_SHIFT                  (30U)
/*! TIME_REC - Enable the WOR HW to record the timing information to the Packet RAM.
 */
#define WOR_CTRL_TIME_REC(x)                     (((uint32_t)(((uint32_t)(x)) << WOR_CTRL_TIME_REC_SHIFT)) & WOR_CTRL_TIME_REC_MASK)

#define WOR_CTRL_WOR_RX_FAIL_IRQ_EN_MASK         (0x80000000U)
#define WOR_CTRL_WOR_RX_FAIL_IRQ_EN_SHIFT        (31U)
/*! WOR_RX_FAIL_IRQ_EN - WOR_RX_FAIL_IRQ Enable
 */
#define WOR_CTRL_WOR_RX_FAIL_IRQ_EN(x)           (((uint32_t)(((uint32_t)(x)) << WOR_CTRL_WOR_RX_FAIL_IRQ_EN_SHIFT)) & WOR_CTRL_WOR_RX_FAIL_IRQ_EN_MASK)
/*! @} */

/*! @name TIMEOUT - WAKE-ON-RADIO TIMEOUT REGISTER */
/*! @{ */

#define WOR_TIMEOUT_RECEIVE_TIMEOUT_MASK         (0xFFFFU)
#define WOR_TIMEOUT_RECEIVE_TIMEOUT_SHIFT        (0U)
/*! RECEIVE_TIMEOUT - WAKE-ON-RADIO Receive Timeout
 */
#define WOR_TIMEOUT_RECEIVE_TIMEOUT(x)           (((uint32_t)(((uint32_t)(x)) << WOR_TIMEOUT_RECEIVE_TIMEOUT_SHIFT)) & WOR_TIMEOUT_RECEIVE_TIMEOUT_MASK)

#define WOR_TIMEOUT_WAKE_ON_NTH_SLOT_MASK        (0xFF0000U)
#define WOR_TIMEOUT_WAKE_ON_NTH_SLOT_SHIFT       (16U)
/*! WAKE_ON_NTH_SLOT - WAKE-ON-RADIO Force Wake On Nth Slot
 */
#define WOR_TIMEOUT_WAKE_ON_NTH_SLOT(x)          (((uint32_t)(((uint32_t)(x)) << WOR_TIMEOUT_WAKE_ON_NTH_SLOT_SHIFT)) & WOR_TIMEOUT_WAKE_ON_NTH_SLOT_MASK)

#define WOR_TIMEOUT_WOR_SLOT_COUNT_MASK          (0xFF000000U)
#define WOR_TIMEOUT_WOR_SLOT_COUNT_SHIFT         (24U)
/*! WOR_SLOT_COUNT - WAKE-ON-RADIO Absolute Slot Count
 */
#define WOR_TIMEOUT_WOR_SLOT_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << WOR_TIMEOUT_WOR_SLOT_COUNT_SHIFT)) & WOR_TIMEOUT_WOR_SLOT_COUNT_MASK)
/*! @} */

/*! @name TIMESTAMP1 - WAKE-ON-RADIO TIMESTAMP 1 */
/*! @{ */

#define WOR_TIMESTAMP1_TIMESTAMP1_MASK           (0xFFFFFFFFU)
#define WOR_TIMESTAMP1_TIMESTAMP1_SHIFT          (0U)
/*! TIMESTAMP1 - WAKE-ON-RADIO TIMESTAMP1
 */
#define WOR_TIMESTAMP1_TIMESTAMP1(x)             (((uint32_t)(((uint32_t)(x)) << WOR_TIMESTAMP1_TIMESTAMP1_SHIFT)) & WOR_TIMESTAMP1_TIMESTAMP1_MASK)
/*! @} */

/*! @name TIMESTAMP2 - WAKE-ON-RADIO TIMESTAMP 2 */
/*! @{ */

#define WOR_TIMESTAMP2_TIMESTAMP2_MASK           (0xFFFFFFFFU)
#define WOR_TIMESTAMP2_TIMESTAMP2_SHIFT          (0U)
/*! TIMESTAMP2 - WAKE-ON-RADIO TIMESTAMP2
 */
#define WOR_TIMESTAMP2_TIMESTAMP2(x)             (((uint32_t)(((uint32_t)(x)) << WOR_TIMESTAMP2_TIMESTAMP2_SHIFT)) & WOR_TIMESTAMP2_TIMESTAMP2_MASK)
/*! @} */

/*! @name TIMESTAMP3 - WAKE-ON-RADIO TIMESTAMP 3 */
/*! @{ */

#define WOR_TIMESTAMP3_TIMESTAMP3_MASK           (0xFFFFFFFFU)
#define WOR_TIMESTAMP3_TIMESTAMP3_SHIFT          (0U)
/*! TIMESTAMP3 - WAKE-ON-RADIO TIMESTAMP3
 */
#define WOR_TIMESTAMP3_TIMESTAMP3(x)             (((uint32_t)(((uint32_t)(x)) << WOR_TIMESTAMP3_TIMESTAMP3_SHIFT)) & WOR_TIMESTAMP3_TIMESTAMP3_MASK)
/*! @} */

/*! @name STATUS - WAKE-ON-RADIO STATUS REGISTER */
/*! @{ */

#define WOR_STATUS_TIMESTAMP0_STS_MASK           (0x7U)
#define WOR_STATUS_TIMESTAMP0_STS_SHIFT          (0U)
/*! TIMESTAMP0_STS - WAKE-ON-RADIO Timestamp 0 Status
 */
#define WOR_STATUS_TIMESTAMP0_STS(x)             (((uint32_t)(((uint32_t)(x)) << WOR_STATUS_TIMESTAMP0_STS_SHIFT)) & WOR_STATUS_TIMESTAMP0_STS_MASK)

#define WOR_STATUS_TIMESTAMP1_STS_MASK           (0x38U)
#define WOR_STATUS_TIMESTAMP1_STS_SHIFT          (3U)
/*! TIMESTAMP1_STS - WAKE-ON-RADIO Timestamp 1 Status
 */
#define WOR_STATUS_TIMESTAMP1_STS(x)             (((uint32_t)(((uint32_t)(x)) << WOR_STATUS_TIMESTAMP1_STS_SHIFT)) & WOR_STATUS_TIMESTAMP1_STS_MASK)

#define WOR_STATUS_TIMESTAMP2_STS_MASK           (0x1C0U)
#define WOR_STATUS_TIMESTAMP2_STS_SHIFT          (6U)
/*! TIMESTAMP2_STS - WAKE-ON-RADIO Timestamp 2 Status
 */
#define WOR_STATUS_TIMESTAMP2_STS(x)             (((uint32_t)(((uint32_t)(x)) << WOR_STATUS_TIMESTAMP2_STS_SHIFT)) & WOR_STATUS_TIMESTAMP2_STS_MASK)

#define WOR_STATUS_TIMESTAMP3_STS_MASK           (0xE00U)
#define WOR_STATUS_TIMESTAMP3_STS_SHIFT          (9U)
/*! TIMESTAMP3_STS - WAKE-ON-RADIO Timestamp 3 Status
 */
#define WOR_STATUS_TIMESTAMP3_STS(x)             (((uint32_t)(((uint32_t)(x)) << WOR_STATUS_TIMESTAMP3_STS_SHIFT)) & WOR_STATUS_TIMESTAMP3_STS_MASK)

#define WOR_STATUS_SLOT_MASK                     (0x3000U)
#define WOR_STATUS_SLOT_SHIFT                    (12U)
/*! SLOT - WAKE-ON-RADIO Current Slot
 */
#define WOR_STATUS_SLOT(x)                       (((uint32_t)(((uint32_t)(x)) << WOR_STATUS_SLOT_SHIFT)) & WOR_STATUS_SLOT_MASK)

#define WOR_STATUS_WOR_NO_RF_FLAG_MASK           (0x10000U)
#define WOR_STATUS_WOR_NO_RF_FLAG_SHIFT          (16U)
/*! WOR_NO_RF_FLAG - WAKE-ON-RADIO NO_RF Slot Flag
 */
#define WOR_STATUS_WOR_NO_RF_FLAG(x)             (((uint32_t)(((uint32_t)(x)) << WOR_STATUS_WOR_NO_RF_FLAG_SHIFT)) & WOR_STATUS_WOR_NO_RF_FLAG_MASK)

#define WOR_STATUS_WOR_MAX_SLOT_FLAG_MASK        (0x20000U)
#define WOR_STATUS_WOR_MAX_SLOT_FLAG_SHIFT       (17U)
/*! WOR_MAX_SLOT_FLAG - WAKE-ON-RADIO Maximum Slot Count Reached Flag
 */
#define WOR_STATUS_WOR_MAX_SLOT_FLAG(x)          (((uint32_t)(((uint32_t)(x)) << WOR_STATUS_WOR_MAX_SLOT_FLAG_SHIFT)) & WOR_STATUS_WOR_MAX_SLOT_FLAG_MASK)

#define WOR_STATUS_WOR_DSM_EXIT_FLAG_MASK        (0x40000U)
#define WOR_STATUS_WOR_DSM_EXIT_FLAG_SHIFT       (18U)
/*! WOR_DSM_EXIT_FLAG - WAKE-ON-RADIO Early DSM Exit Flag
 */
#define WOR_STATUS_WOR_DSM_EXIT_FLAG(x)          (((uint32_t)(((uint32_t)(x)) << WOR_STATUS_WOR_DSM_EXIT_FLAG_SHIFT)) & WOR_STATUS_WOR_DSM_EXIT_FLAG_MASK)

#define WOR_STATUS_WOR_STATE_MASK                (0xF00000U)
#define WOR_STATUS_WOR_STATE_SHIFT               (20U)
/*! WOR_STATE - WAKE-ON-RADIO Current State
 */
#define WOR_STATUS_WOR_STATE(x)                  (((uint32_t)(((uint32_t)(x)) << WOR_STATUS_WOR_STATE_SHIFT)) & WOR_STATUS_WOR_STATE_MASK)

#define WOR_STATUS_WOR_RX_FAIL_IRQ_MASK          (0x80000000U)
#define WOR_STATUS_WOR_RX_FAIL_IRQ_SHIFT         (31U)
/*! WOR_RX_FAIL_IRQ - WOR RX Fail Interrupt Flag
 */
#define WOR_STATUS_WOR_RX_FAIL_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << WOR_STATUS_WOR_RX_FAIL_IRQ_SHIFT)) & WOR_STATUS_WOR_RX_FAIL_IRQ_MASK)
/*! @} */

/*! @name WW_CTRL - WINDOW-WIDENING CONTROL REGISTER */
/*! @{ */

#define WOR_WW_CTRL_WW_EN_MASK                   (0x1U)
#define WOR_WW_CTRL_WW_EN_SHIFT                  (0U)
/*! WW_EN - Window-widening Enable
 */
#define WOR_WW_CTRL_WW_EN(x)                     (((uint32_t)(((uint32_t)(x)) << WOR_WW_CTRL_WW_EN_SHIFT)) & WOR_WW_CTRL_WW_EN_MASK)

#define WOR_WW_CTRL_WW_RESET_ON_RX_MASK          (0x2U)
#define WOR_WW_CTRL_WW_RESET_ON_RX_SHIFT         (1U)
/*! WW_RESET_ON_RX - Window-widening Reset on Received Good Packet
 */
#define WOR_WW_CTRL_WW_RESET_ON_RX(x)            (((uint32_t)(((uint32_t)(x)) << WOR_WW_CTRL_WW_RESET_ON_RX_SHIFT)) & WOR_WW_CTRL_WW_RESET_ON_RX_MASK)

#define WOR_WW_CTRL_WW_NULL_MASK                 (0x4U)
#define WOR_WW_CTRL_WW_NULL_SHIFT                (2U)
/*! WW_NULL - Window-widening Null Command
 */
#define WOR_WW_CTRL_WW_NULL(x)                   (((uint32_t)(((uint32_t)(x)) << WOR_WW_CTRL_WW_NULL_SHIFT)) & WOR_WW_CTRL_WW_NULL_MASK)

#define WOR_WW_CTRL_WW_ADD_MASK                  (0x8U)
#define WOR_WW_CTRL_WW_ADD_SHIFT                 (3U)
/*! WW_ADD - Window-widening Add Command
 */
#define WOR_WW_CTRL_WW_ADD(x)                    (((uint32_t)(((uint32_t)(x)) << WOR_WW_CTRL_WW_ADD_SHIFT)) & WOR_WW_CTRL_WW_ADD_MASK)

#define WOR_WW_CTRL_WW_DSM_FACTOR_MASK           (0x3F00U)
#define WOR_WW_CTRL_WW_DSM_FACTOR_SHIFT          (8U)
/*! WW_DSM_FACTOR - Window-widening DSM Factor
 */
#define WOR_WW_CTRL_WW_DSM_FACTOR(x)             (((uint32_t)(((uint32_t)(x)) << WOR_WW_CTRL_WW_DSM_FACTOR_SHIFT)) & WOR_WW_CTRL_WW_DSM_FACTOR_MASK)

#define WOR_WW_CTRL_WW_RUN_FACTOR_MASK           (0x1F0000U)
#define WOR_WW_CTRL_WW_RUN_FACTOR_SHIFT          (16U)
/*! WW_RUN_FACTOR - Window-widening Runtime Factor
 */
#define WOR_WW_CTRL_WW_RUN_FACTOR(x)             (((uint32_t)(((uint32_t)(x)) << WOR_WW_CTRL_WW_RUN_FACTOR_SHIFT)) & WOR_WW_CTRL_WW_RUN_FACTOR_MASK)

#define WOR_WW_CTRL_WW_INCREASE_MASK             (0xFF000000U)
#define WOR_WW_CTRL_WW_INCREASE_SHIFT            (24U)
/*! WW_INCREASE - Window-widening Manual Increase Amount
 */
#define WOR_WW_CTRL_WW_INCREASE(x)               (((uint32_t)(((uint32_t)(x)) << WOR_WW_CTRL_WW_INCREASE_SHIFT)) & WOR_WW_CTRL_WW_INCREASE_MASK)
/*! @} */

/*! @name HOP_CTRL - FREQUENCY HOP CONTROL REGISTER */
/*! @{ */

#define WOR_HOP_CTRL_HOP_TBL_CFG_MASK            (0x7U)
#define WOR_HOP_CTRL_HOP_TBL_CFG_SHIFT           (0U)
/*! HOP_TBL_CFG - Hop Table Configuration
 */
#define WOR_HOP_CTRL_HOP_TBL_CFG(x)              (((uint32_t)(((uint32_t)(x)) << WOR_HOP_CTRL_HOP_TBL_CFG_SHIFT)) & WOR_HOP_CTRL_HOP_TBL_CFG_MASK)

#define WOR_HOP_CTRL_NEW_HOP_IDX_MASK            (0x7F00U)
#define WOR_HOP_CTRL_NEW_HOP_IDX_SHIFT           (8U)
/*! NEW_HOP_IDX - New Hop Table Index
 */
#define WOR_HOP_CTRL_NEW_HOP_IDX(x)              (((uint32_t)(((uint32_t)(x)) << WOR_HOP_CTRL_NEW_HOP_IDX_SHIFT)) & WOR_HOP_CTRL_NEW_HOP_IDX_MASK)

#define WOR_HOP_CTRL_UPDATE_HOP_IDX_MASK         (0x8000U)
#define WOR_HOP_CTRL_UPDATE_HOP_IDX_SHIFT        (15U)
/*! UPDATE_HOP_IDX - Update Hop Table Index
 */
#define WOR_HOP_CTRL_UPDATE_HOP_IDX(x)           (((uint32_t)(((uint32_t)(x)) << WOR_HOP_CTRL_UPDATE_HOP_IDX_SHIFT)) & WOR_HOP_CTRL_UPDATE_HOP_IDX_MASK)

#define WOR_HOP_CTRL_HOP_SEQ_LENGTH_MASK         (0xFF0000U)
#define WOR_HOP_CTRL_HOP_SEQ_LENGTH_SHIFT        (16U)
/*! HOP_SEQ_LENGTH - New Hop Table Index
 */
#define WOR_HOP_CTRL_HOP_SEQ_LENGTH(x)           (((uint32_t)(((uint32_t)(x)) << WOR_HOP_CTRL_HOP_SEQ_LENGTH_SHIFT)) & WOR_HOP_CTRL_HOP_SEQ_LENGTH_MASK)
/*! @} */

/*! @name SLOT0_DESC0 - SLOT 0 DESCRIPTOR (LSB) */
/*! @{ */

#define WOR_SLOT0_DESC0_SLOT0_DESC0_MASK         (0xFFFFFFFFU)
#define WOR_SLOT0_DESC0_SLOT0_DESC0_SHIFT        (0U)
/*! SLOT0_DESC0 - Slot 0 Descriptor (LSB's)
 */
#define WOR_SLOT0_DESC0_SLOT0_DESC0(x)           (((uint32_t)(((uint32_t)(x)) << WOR_SLOT0_DESC0_SLOT0_DESC0_SHIFT)) & WOR_SLOT0_DESC0_SLOT0_DESC0_MASK)
/*! @} */

/*! @name SLOT0_DESC1 - SLOT 0 DESCRIPTOR (MSB) */
/*! @{ */

#define WOR_SLOT0_DESC1_SLOT0_DESC1_MASK         (0x3FU)
#define WOR_SLOT0_DESC1_SLOT0_DESC1_SHIFT        (0U)
/*! SLOT0_DESC1 - Slot 0 Descriptor (MSB's)
 */
#define WOR_SLOT0_DESC1_SLOT0_DESC1(x)           (((uint32_t)(((uint32_t)(x)) << WOR_SLOT0_DESC1_SLOT0_DESC1_SHIFT)) & WOR_SLOT0_DESC1_SLOT0_DESC1_MASK)

#define WOR_SLOT0_DESC1_WOR_HOP_IDX_MASK         (0x7F00U)
#define WOR_SLOT0_DESC1_WOR_HOP_IDX_SHIFT        (8U)
/*! WOR_HOP_IDX - Current Hop Table Index
 */
#define WOR_SLOT0_DESC1_WOR_HOP_IDX(x)           (((uint32_t)(((uint32_t)(x)) << WOR_SLOT0_DESC1_WOR_HOP_IDX_SHIFT)) & WOR_SLOT0_DESC1_WOR_HOP_IDX_MASK)

#define WOR_SLOT0_DESC1_WOR_HOP_FREQ_WORD_MASK   (0xFFFF0000U)
#define WOR_SLOT0_DESC1_WOR_HOP_FREQ_WORD_SHIFT  (16U)
/*! WOR_HOP_FREQ_WORD - Current Hop Frequency Word
 */
#define WOR_SLOT0_DESC1_WOR_HOP_FREQ_WORD(x)     (((uint32_t)(((uint32_t)(x)) << WOR_SLOT0_DESC1_WOR_HOP_FREQ_WORD_SHIFT)) & WOR_SLOT0_DESC1_WOR_HOP_FREQ_WORD_MASK)
/*! @} */

/*! @name SLOT1_DESC0 - SLOT 1 DESCRIPTOR (LSB) */
/*! @{ */

#define WOR_SLOT1_DESC0_SLOT1_DESC0_MASK         (0xFFFFFFFFU)
#define WOR_SLOT1_DESC0_SLOT1_DESC0_SHIFT        (0U)
/*! SLOT1_DESC0 - Slot 1 Descriptor (LSB's)
 */
#define WOR_SLOT1_DESC0_SLOT1_DESC0(x)           (((uint32_t)(((uint32_t)(x)) << WOR_SLOT1_DESC0_SLOT1_DESC0_SHIFT)) & WOR_SLOT1_DESC0_SLOT1_DESC0_MASK)
/*! @} */

/*! @name SLOT1_DESC1 - SLOT 1 DESCRIPTOR (MSB) */
/*! @{ */

#define WOR_SLOT1_DESC1_SLOT1_DESC1_MASK         (0x3FU)
#define WOR_SLOT1_DESC1_SLOT1_DESC1_SHIFT        (0U)
/*! SLOT1_DESC1 - Slot 1 Descriptor (MSB's)
 */
#define WOR_SLOT1_DESC1_SLOT1_DESC1(x)           (((uint32_t)(((uint32_t)(x)) << WOR_SLOT1_DESC1_SLOT1_DESC1_SHIFT)) & WOR_SLOT1_DESC1_SLOT1_DESC1_MASK)
/*! @} */

/*! @name SLOT2_DESC0 - SLOT 2 DESCRIPTOR (LSB) */
/*! @{ */

#define WOR_SLOT2_DESC0_SLOT2_DESC0_MASK         (0xFFFFFFFFU)
#define WOR_SLOT2_DESC0_SLOT2_DESC0_SHIFT        (0U)
/*! SLOT2_DESC0 - Slot 2 Descriptor (LSB's)
 */
#define WOR_SLOT2_DESC0_SLOT2_DESC0(x)           (((uint32_t)(((uint32_t)(x)) << WOR_SLOT2_DESC0_SLOT2_DESC0_SHIFT)) & WOR_SLOT2_DESC0_SLOT2_DESC0_MASK)
/*! @} */

/*! @name SLOT2_DESC1 - SLOT 2 DESCRIPTOR (MSB) */
/*! @{ */

#define WOR_SLOT2_DESC1_SLOT2_DESC1_MASK         (0x3FU)
#define WOR_SLOT2_DESC1_SLOT2_DESC1_SHIFT        (0U)
/*! SLOT2_DESC1 - Slot 2 Descriptor (MSB's)
 */
#define WOR_SLOT2_DESC1_SLOT2_DESC1(x)           (((uint32_t)(((uint32_t)(x)) << WOR_SLOT2_DESC1_SLOT2_DESC1_SHIFT)) & WOR_SLOT2_DESC1_SLOT2_DESC1_MASK)
/*! @} */

/*! @name SLOT3_DESC0 - SLOT 3 DESCRIPTOR (LSB) */
/*! @{ */

#define WOR_SLOT3_DESC0_SLOT3_DESC0_MASK         (0xFFFFFFFFU)
#define WOR_SLOT3_DESC0_SLOT3_DESC0_SHIFT        (0U)
/*! SLOT3_DESC0 - Slot 3 Descriptor (LSB's)
 */
#define WOR_SLOT3_DESC0_SLOT3_DESC0(x)           (((uint32_t)(((uint32_t)(x)) << WOR_SLOT3_DESC0_SLOT3_DESC0_SHIFT)) & WOR_SLOT3_DESC0_SLOT3_DESC0_MASK)
/*! @} */

/*! @name SLOT3_DESC1 - SLOT 3 DESCRIPTOR (MSB) */
/*! @{ */

#define WOR_SLOT3_DESC1_SLOT3_DESC1_MASK         (0x3FU)
#define WOR_SLOT3_DESC1_SLOT3_DESC1_SHIFT        (0U)
/*! SLOT3_DESC1 - Slot 3 Descriptor (MSB's)
 */
#define WOR_SLOT3_DESC1_SLOT3_DESC1(x)           (((uint32_t)(((uint32_t)(x)) << WOR_SLOT3_DESC1_SLOT3_DESC1_SHIFT)) & WOR_SLOT3_DESC1_SLOT3_DESC1_MASK)
/*! @} */

/*! @name AUTO_DRIFT1 - Auto Drift Calculation Register 1 */
/*! @{ */

#define WOR_AUTO_DRIFT1_SW_DRIFT_SET_MASK        (0x7FU)
#define WOR_AUTO_DRIFT1_SW_DRIFT_SET_SHIFT       (0U)
/*! SW_DRIFT_SET - Software calculated drift.
 */
#define WOR_AUTO_DRIFT1_SW_DRIFT_SET(x)          (((uint32_t)(((uint32_t)(x)) << WOR_AUTO_DRIFT1_SW_DRIFT_SET_SHIFT)) & WOR_AUTO_DRIFT1_SW_DRIFT_SET_MASK)

#define WOR_AUTO_DRIFT1_CAL_DSM_FACTOR_MASK      (0x7F0000U)
#define WOR_AUTO_DRIFT1_CAL_DSM_FACTOR_SHIFT     (16U)
/*! CAL_DSM_FACTOR - Hardware calculated drift.
 */
#define WOR_AUTO_DRIFT1_CAL_DSM_FACTOR(x)        (((uint32_t)(((uint32_t)(x)) << WOR_AUTO_DRIFT1_CAL_DSM_FACTOR_SHIFT)) & WOR_AUTO_DRIFT1_CAL_DSM_FACTOR_MASK)
/*! @} */

/*! @name AUTO_DRIFT2 - Auto Drift Calculation Register 2 */
/*! @{ */

#define WOR_AUTO_DRIFT2_AA_SFD_DLY_MASK          (0xFFFFU)
#define WOR_AUTO_DRIFT2_AA_SFD_DLY_SHIFT         (0U)
/*! AA_SFD_DLY - The time duration of Preamble and Sync Address plus the RX warm up duration.
 */
#define WOR_AUTO_DRIFT2_AA_SFD_DLY(x)            (((uint32_t)(((uint32_t)(x)) << WOR_AUTO_DRIFT2_AA_SFD_DLY_SHIFT)) & WOR_AUTO_DRIFT2_AA_SFD_DLY_MASK)
/*! @} */

/*! @name AUTO_DRIFT3 - Auto Drift Calculation Register 3 */
/*! @{ */

#define WOR_AUTO_DRIFT3_TIME_MGN_MASK            (0xFFFFU)
#define WOR_AUTO_DRIFT3_TIME_MGN_SHIFT           (0U)
/*! TIME_MGN - The time margin applied to the start time and timeout.
 */
#define WOR_AUTO_DRIFT3_TIME_MGN(x)              (((uint32_t)(((uint32_t)(x)) << WOR_AUTO_DRIFT3_TIME_MGN_SHIFT)) & WOR_AUTO_DRIFT3_TIME_MGN_MASK)
/*! @} */

/*! @name AUTO_DRIFT4 - Auto Drift Calculation Register 4 */
/*! @{ */

#define WOR_AUTO_DRIFT4_TINT_DIV_MILLION_MASK    (0xFFFFFFU)
#define WOR_AUTO_DRIFT4_TINT_DIV_MILLION_SHIFT   (0U)
#define WOR_AUTO_DRIFT4_TINT_DIV_MILLION(x)      (((uint32_t)(((uint32_t)(x)) << WOR_AUTO_DRIFT4_TINT_DIV_MILLION_SHIFT)) & WOR_AUTO_DRIFT4_TINT_DIV_MILLION_MASK)
/*! @} */

/*! @name TIME - Timer Count */
/*! @{ */

#define WOR_TIME_TIME_MASK                       (0xFFFFFFU)
#define WOR_TIME_TIME_SHIFT                      (0U)
#define WOR_TIME_TIME(x)                         (((uint32_t)(((uint32_t)(x)) << WOR_TIME_TIME_SHIFT)) & WOR_TIME_TIME_MASK)
/*! @} */

/*! @name ENTER_TIME_CAPT - MAN Low Power Entry Time Captured */
/*! @{ */

#define WOR_ENTER_TIME_CAPT_ENTER_TIME_CAPT_MASK (0xFFFFFFU)
#define WOR_ENTER_TIME_CAPT_ENTER_TIME_CAPT_SHIFT (0U)
#define WOR_ENTER_TIME_CAPT_ENTER_TIME_CAPT(x)   (((uint32_t)(((uint32_t)(x)) << WOR_ENTER_TIME_CAPT_ENTER_TIME_CAPT_SHIFT)) & WOR_ENTER_TIME_CAPT_ENTER_TIME_CAPT_MASK)
/*! @} */

/*! @name WKUP_TIME_CAPT - MAN Low Power Wakeup Time Captured */
/*! @{ */

#define WOR_WKUP_TIME_CAPT_WKUP_TIME_CAPT_MASK   (0xFFFFFFU)
#define WOR_WKUP_TIME_CAPT_WKUP_TIME_CAPT_SHIFT  (0U)
#define WOR_WKUP_TIME_CAPT_WKUP_TIME_CAPT(x)     (((uint32_t)(((uint32_t)(x)) << WOR_WKUP_TIME_CAPT_WKUP_TIME_CAPT_SHIFT)) & WOR_WKUP_TIME_CAPT_WKUP_TIME_CAPT_MASK)
/*! @} */

/*! @name ENTER_TIME - MAN Low Power Entry Time Stamp */
/*! @{ */

#define WOR_ENTER_TIME_ENTER_TIME_MASK           (0xFFFFFFU)
#define WOR_ENTER_TIME_ENTER_TIME_SHIFT          (0U)
#define WOR_ENTER_TIME_ENTER_TIME(x)             (((uint32_t)(((uint32_t)(x)) << WOR_ENTER_TIME_ENTER_TIME_SHIFT)) & WOR_ENTER_TIME_ENTER_TIME_MASK)
/*! @} */

/*! @name WKUP_TIME - MAN Low Power Wakeup Time Stamp */
/*! @{ */

#define WOR_WKUP_TIME_WKUP_TIME_MASK             (0xFFFFFFU)
#define WOR_WKUP_TIME_WKUP_TIME_SHIFT            (0U)
#define WOR_WKUP_TIME_WKUP_TIME(x)               (((uint32_t)(((uint32_t)(x)) << WOR_WKUP_TIME_WKUP_TIME_SHIFT)) & WOR_WKUP_TIME_WKUP_TIME_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group WOR_Register_Masks */


/* WOR - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral WOR_REGS base address */
  #define WOR_REGS_BASE                            (0x58A06100u)
  /** Peripheral WOR_REGS base address */
  #define WOR_REGS_BASE_NS                         (0x48A06100u)
  /** Peripheral WOR_REGS base pointer */
  #define WOR_REGS                                 ((WOR_Type *)WOR_REGS_BASE)
  /** Peripheral WOR_REGS base pointer */
  #define WOR_REGS_NS                              ((WOR_Type *)WOR_REGS_BASE_NS)
  /** Array initializer of WOR peripheral base addresses */
  #define WOR_BASE_ADDRS                           { WOR_REGS_BASE }
  /** Array initializer of WOR peripheral base pointers */
  #define WOR_BASE_PTRS                            { WOR_REGS }
  /** Array initializer of WOR peripheral base addresses */
  #define WOR_BASE_ADDRS_NS                        { WOR_REGS_BASE_NS }
  /** Array initializer of WOR peripheral base pointers */
  #define WOR_BASE_PTRS_NS                         { WOR_REGS_NS }
#else
  /** Peripheral WOR_REGS base address */
  #define WOR_REGS_BASE                            (0x48A06100u)
  /** Peripheral WOR_REGS base pointer */
  #define WOR_REGS                                 ((WOR_Type *)WOR_REGS_BASE)
  /** Array initializer of WOR peripheral base addresses */
  #define WOR_BASE_ADDRS                           { WOR_REGS_BASE }
  /** Array initializer of WOR peripheral base pointers */
  #define WOR_BASE_PTRS                            { WOR_REGS }
#endif

/*!
 * @}
 */ /* end of group WOR_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- WUU Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup WUU_Peripheral_Access_Layer WUU Peripheral Access Layer
 * @{
 */

/** WUU - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
  __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
  __IO uint32_t PE1;                               /**< Pin Enable 1, offset: 0x8 */
  __IO uint32_t PE2;                               /**< Pin Enable 2, offset: 0xC */
       uint8_t RESERVED_0[8];
  __IO uint32_t ME;                                /**< Module Interrupt Enable, offset: 0x18 */
  __IO uint32_t DE;                                /**< Module DMA/Trigger Enable, offset: 0x1C */
  __IO uint32_t PF;                                /**< Pin Flag, offset: 0x20 */
       uint8_t RESERVED_1[12];
  __IO uint32_t FILT;                              /**< Pin Filter, offset: 0x30 */
       uint8_t RESERVED_2[4];
  __IO uint32_t PDC1;                              /**< Pin DMA/Trigger Configuration 1, offset: 0x38 */
  __IO uint32_t PDC2;                              /**< Pin DMA/Trigger Configuration 2, offset: 0x3C */
       uint8_t RESERVED_3[8];
  __IO uint32_t FDC;                               /**< Pin Filter DMA/Trigger Configuration, offset: 0x48 */
       uint8_t RESERVED_4[4];
  __IO uint32_t PMC;                               /**< Pin Mode Configuration, offset: 0x50 */
       uint8_t RESERVED_5[4];
  __IO uint32_t FMC;                               /**< Pin Filter Mode Configuration, offset: 0x58 */
} WUU_Type;

/* ----------------------------------------------------------------------------
   -- WUU Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup WUU_Register_Masks WUU Register Masks
 * @{
 */

/*! @name VERID - Version ID */
/*! @{ */

#define WUU_VERID_FEATURE_MASK                   (0xFFFFU)
#define WUU_VERID_FEATURE_SHIFT                  (0U)
/*! FEATURE - Feature Specification Number
 *  0b0000000000000000..Standard features implemented
 *  0b0000000000000001..Support for DMA/Trigger generation from wakeup pins and filters enabled. Support for
 *                      external pin/filter detection during all power modes enabled.
 */
#define WUU_VERID_FEATURE(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_VERID_FEATURE_SHIFT)) & WUU_VERID_FEATURE_MASK)

#define WUU_VERID_MINOR_MASK                     (0xFF0000U)
#define WUU_VERID_MINOR_SHIFT                    (16U)
/*! MINOR - Minor Version Number
 */
#define WUU_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_VERID_MINOR_SHIFT)) & WUU_VERID_MINOR_MASK)

#define WUU_VERID_MAJOR_MASK                     (0xFF000000U)
#define WUU_VERID_MAJOR_SHIFT                    (24U)
/*! MAJOR - Major Version Number
 */
#define WUU_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_VERID_MAJOR_SHIFT)) & WUU_VERID_MAJOR_MASK)
/*! @} */

/*! @name PARAM - Parameter */
/*! @{ */

#define WUU_PARAM_FILTERS_MASK                   (0xFFU)
#define WUU_PARAM_FILTERS_SHIFT                  (0U)
/*! FILTERS - Filter Number
 */
#define WUU_PARAM_FILTERS(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_PARAM_FILTERS_SHIFT)) & WUU_PARAM_FILTERS_MASK)

#define WUU_PARAM_DMAS_MASK                      (0xFF00U)
#define WUU_PARAM_DMAS_SHIFT                     (8U)
/*! DMAS - DMA Number
 */
#define WUU_PARAM_DMAS(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PARAM_DMAS_SHIFT)) & WUU_PARAM_DMAS_MASK)

#define WUU_PARAM_MODULES_MASK                   (0xFF0000U)
#define WUU_PARAM_MODULES_SHIFT                  (16U)
/*! MODULES - Module Number
 */
#define WUU_PARAM_MODULES(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_PARAM_MODULES_SHIFT)) & WUU_PARAM_MODULES_MASK)

#define WUU_PARAM_PINS_MASK                      (0xFF000000U)
#define WUU_PARAM_PINS_SHIFT                     (24U)
/*! PINS - Pin Number
 */
#define WUU_PARAM_PINS(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PARAM_PINS_SHIFT)) & WUU_PARAM_PINS_MASK)
/*! @} */

/*! @name PE1 - Pin Enable 1 */
/*! @{ */

#define WUU_PE1_WUPE0_MASK                       (0x3U)
#define WUU_PE1_WUPE0_SHIFT                      (0U)
/*! WUPE0 - Wakeup pin enable for WUU_Pn
 *  0b00..Disables as a wakeup pin
 *  0b01..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When
 *        configured as a trigger request: Detect on high level
 *  0b10..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When
 *        configured as a trigger request: Detect on low level
 *  0b11..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge
 */
#define WUU_PE1_WUPE0(x)                         (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE0_SHIFT)) & WUU_PE1_WUPE0_MASK)

#define WUU_PE1_WUPE1_MASK                       (0xCU)
#define WUU_PE1_WUPE1_SHIFT                      (2U)
/*! WUPE1 - Reserved
 *  0b00..Not supported
 *  0b01..Not supported
 *  0b10..Not supported
 *  0b11..Not supported
 */
#define WUU_PE1_WUPE1(x)                         (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE1_SHIFT)) & WUU_PE1_WUPE1_MASK)

#define WUU_PE1_WUPE2_MASK                       (0x30U)
#define WUU_PE1_WUPE2_SHIFT                      (4U)
/*! WUPE2 - Wakeup pin enable for WUU_Pn
 *  0b00..Disables as a wakeup pin
 *  0b01..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When
 *        configured as a trigger request: Detect on high level
 *  0b10..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When
 *        configured as a trigger request: Detect on low level
 *  0b11..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge
 */
#define WUU_PE1_WUPE2(x)                         (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE2_SHIFT)) & WUU_PE1_WUPE2_MASK)

#define WUU_PE1_WUPE3_MASK                       (0xC0U)
#define WUU_PE1_WUPE3_SHIFT                      (6U)
/*! WUPE3 - Wakeup pin enable for WUU_Pn
 *  0b00..Disables as a wakeup pin
 *  0b01..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When
 *        configured as a trigger request: Detect on high level
 *  0b10..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When
 *        configured as a trigger request: Detect on low level
 *  0b11..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge
 */
#define WUU_PE1_WUPE3(x)                         (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE3_SHIFT)) & WUU_PE1_WUPE3_MASK)

#define WUU_PE1_WUPE4_MASK                       (0x300U)
#define WUU_PE1_WUPE4_SHIFT                      (8U)
/*! WUPE4 - Wakeup pin enable for WUU_Pn
 *  0b00..Disables as a wakeup pin
 *  0b01..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When
 *        configured as a trigger request: Detect on high level
 *  0b10..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When
 *        configured as a trigger request: Detect on low level
 *  0b11..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge
 */
#define WUU_PE1_WUPE4(x)                         (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE4_SHIFT)) & WUU_PE1_WUPE4_MASK)

#define WUU_PE1_WUPE5_MASK                       (0xC00U)
#define WUU_PE1_WUPE5_SHIFT                      (10U)
/*! WUPE5 - Wakeup pin enable for WUU_Pn
 *  0b00..Disables as a wakeup pin
 *  0b01..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When
 *        configured as a trigger request: Detect on high level
 *  0b10..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When
 *        configured as a trigger request: Detect on low level
 *  0b11..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge
 */
#define WUU_PE1_WUPE5(x)                         (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE5_SHIFT)) & WUU_PE1_WUPE5_MASK)

#define WUU_PE1_WUPE6_MASK                       (0x3000U)
#define WUU_PE1_WUPE6_SHIFT                      (12U)
/*! WUPE6 - Reserved
 *  0b00..Not supported
 *  0b01..Not supported
 *  0b10..Not supported
 *  0b11..Not supported
 */
#define WUU_PE1_WUPE6(x)                         (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE6_SHIFT)) & WUU_PE1_WUPE6_MASK)

#define WUU_PE1_WUPE7_MASK                       (0xC000U)
#define WUU_PE1_WUPE7_SHIFT                      (14U)
/*! WUPE7 - Wakeup pin enable for WUU_Pn
 *  0b00..Disables as a wakeup pin
 *  0b01..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When
 *        configured as a trigger request: Detect on high level
 *  0b10..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When
 *        configured as a trigger request: Detect on low level
 *  0b11..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge
 */
#define WUU_PE1_WUPE7(x)                         (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE7_SHIFT)) & WUU_PE1_WUPE7_MASK)

#define WUU_PE1_WUPE8_MASK                       (0x30000U)
#define WUU_PE1_WUPE8_SHIFT                      (16U)
/*! WUPE8 - Wakeup pin enable for WUU_Pn
 *  0b00..Disables as a wakeup pin
 *  0b01..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When
 *        configured as a trigger request: Detect on high level
 *  0b10..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When
 *        configured as a trigger request: Detect on low level
 *  0b11..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge
 */
#define WUU_PE1_WUPE8(x)                         (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE8_SHIFT)) & WUU_PE1_WUPE8_MASK)

#define WUU_PE1_WUPE9_MASK                       (0xC0000U)
#define WUU_PE1_WUPE9_SHIFT                      (18U)
/*! WUPE9 - Wakeup pin enable for WUU_Pn
 *  0b00..Disables as a wakeup pin
 *  0b01..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When
 *        configured as a trigger request: Detect on high level
 *  0b10..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When
 *        configured as a trigger request: Detect on low level
 *  0b11..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge
 */
#define WUU_PE1_WUPE9(x)                         (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE9_SHIFT)) & WUU_PE1_WUPE9_MASK)

#define WUU_PE1_WUPE10_MASK                      (0x300000U)
#define WUU_PE1_WUPE10_SHIFT                     (20U)
/*! WUPE10 - Wakeup pin enable for WUU_Pn
 *  0b00..Disables as a wakeup pin
 *  0b01..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When
 *        configured as a trigger request: Detect on high level
 *  0b10..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When
 *        configured as a trigger request: Detect on low level
 *  0b11..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge
 */
#define WUU_PE1_WUPE10(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE10_SHIFT)) & WUU_PE1_WUPE10_MASK)

#define WUU_PE1_WUPE11_MASK                      (0xC00000U)
#define WUU_PE1_WUPE11_SHIFT                     (22U)
/*! WUPE11 - Wakeup pin enable for WUU_Pn
 *  0b00..Disables as a wakeup pin
 *  0b01..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When
 *        configured as a trigger request: Detect on high level
 *  0b10..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When
 *        configured as a trigger request: Detect on low level
 *  0b11..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge
 */
#define WUU_PE1_WUPE11(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE11_SHIFT)) & WUU_PE1_WUPE11_MASK)

#define WUU_PE1_WUPE12_MASK                      (0x3000000U)
#define WUU_PE1_WUPE12_SHIFT                     (24U)
/*! WUPE12 - Wakeup pin enable for WUU_Pn
 *  0b00..Disables as a wakeup pin
 *  0b01..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When
 *        configured as a trigger request: Detect on high level
 *  0b10..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When
 *        configured as a trigger request: Detect on low level
 *  0b11..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge
 */
#define WUU_PE1_WUPE12(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE12_SHIFT)) & WUU_PE1_WUPE12_MASK)

#define WUU_PE1_WUPE13_MASK                      (0xC000000U)
#define WUU_PE1_WUPE13_SHIFT                     (26U)
/*! WUPE13 - Wakeup pin enable for WUU_Pn
 *  0b00..Disables as a wakeup pin
 *  0b01..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When
 *        configured as a trigger request: Detect on high level
 *  0b10..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When
 *        configured as a trigger request: Detect on low level
 *  0b11..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge
 */
#define WUU_PE1_WUPE13(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE13_SHIFT)) & WUU_PE1_WUPE13_MASK)

#define WUU_PE1_WUPE14_MASK                      (0x30000000U)
#define WUU_PE1_WUPE14_SHIFT                     (28U)
/*! WUPE14 - Wakeup pin enable for WUU_Pn
 *  0b00..Disables as a wakeup pin
 *  0b01..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When
 *        configured as a trigger request: Detect on high level
 *  0b10..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When
 *        configured as a trigger request: Detect on low level
 *  0b11..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge
 */
#define WUU_PE1_WUPE14(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE14_SHIFT)) & WUU_PE1_WUPE14_MASK)

#define WUU_PE1_WUPE15_MASK                      (0xC0000000U)
#define WUU_PE1_WUPE15_SHIFT                     (30U)
/*! WUPE15 - Wakeup pin enable for WUU_Pn
 *  0b00..Disables as a wakeup pin
 *  0b01..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When
 *        configured as a trigger request: Detect on high level
 *  0b10..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When
 *        configured as a trigger request: Detect on low level
 *  0b11..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge
 */
#define WUU_PE1_WUPE15(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE15_SHIFT)) & WUU_PE1_WUPE15_MASK)
/*! @} */

/*! @name PE2 - Pin Enable 2 */
/*! @{ */

#define WUU_PE2_WUPE27_MASK                      (0xC00000U)
#define WUU_PE2_WUPE27_SHIFT                     (22U)
/*! WUPE27 - Wakeup pin enable for WUU_Pn
 *  0b00..Disables as a wakeup pin
 *  0b01..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When
 *        configured as a trigger request: Detect on high level
 *  0b10..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When
 *        configured as a trigger request: Detect on low level
 *  0b11..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge
 */
#define WUU_PE2_WUPE27(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE27_SHIFT)) & WUU_PE2_WUPE27_MASK)

#define WUU_PE2_WUPE28_MASK                      (0x3000000U)
#define WUU_PE2_WUPE28_SHIFT                     (24U)
/*! WUPE28 - Wakeup pin enable for WUU_Pn
 *  0b00..Disables as a wakeup pin
 *  0b01..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on rising edge. When
 *        configured as a trigger request: Detect on high level
 *  0b10..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on falling edge. When
 *        configured as a trigger request: Detect on low level
 *  0b11..Enables as a wakeup pin. When configured as an interrupt/DMA request: Detect on any edge
 */
#define WUU_PE2_WUPE28(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE28_SHIFT)) & WUU_PE2_WUPE28_MASK)
/*! @} */

/*! @name ME - Module Interrupt Enable */
/*! @{ */

#define WUU_ME_WUME0_MASK                        (0x1U)
#define WUU_ME_WUME0_SHIFT                       (0U)
/*! WUME0 - Module iterrupt wakeup enable for module n
 *  0b0..Disables
 *  0b1..Enables
 */
#define WUU_ME_WUME0(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME0_SHIFT)) & WUU_ME_WUME0_MASK)

#define WUU_ME_WUME1_MASK                        (0x2U)
#define WUU_ME_WUME1_SHIFT                       (1U)
/*! WUME1 - Module iterrupt wakeup enable for module n
 *  0b0..Disables
 *  0b1..Enables
 */
#define WUU_ME_WUME1(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME1_SHIFT)) & WUU_ME_WUME1_MASK)

#define WUU_ME_WUME2_MASK                        (0x4U)
#define WUU_ME_WUME2_SHIFT                       (2U)
/*! WUME2 - Module iterrupt wakeup enable for module n
 *  0b0..Disables
 *  0b1..Enables
 */
#define WUU_ME_WUME2(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME2_SHIFT)) & WUU_ME_WUME2_MASK)

#define WUU_ME_WUME3_MASK                        (0x8U)
#define WUU_ME_WUME3_SHIFT                       (3U)
/*! WUME3 - Module iterrupt wakeup enable for module n
 *  0b0..Disables
 *  0b1..Enables
 */
#define WUU_ME_WUME3(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME3_SHIFT)) & WUU_ME_WUME3_MASK)

#define WUU_ME_WUME4_MASK                        (0x10U)
#define WUU_ME_WUME4_SHIFT                       (4U)
/*! WUME4 - Module iterrupt wakeup enable for module n
 *  0b0..Disables
 *  0b1..Enables
 */
#define WUU_ME_WUME4(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME4_SHIFT)) & WUU_ME_WUME4_MASK)

#define WUU_ME_WUME5_MASK                        (0x20U)
#define WUU_ME_WUME5_SHIFT                       (5U)
/*! WUME5 - Module iterrupt wakeup enable for module n
 *  0b0..Disables
 *  0b1..Enables
 */
#define WUU_ME_WUME5(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME5_SHIFT)) & WUU_ME_WUME5_MASK)

#define WUU_ME_WUME6_MASK                        (0x40U)
#define WUU_ME_WUME6_SHIFT                       (6U)
/*! WUME6 - Module iterrupt wakeup enable for module n
 *  0b0..Disables
 *  0b1..Enables
 */
#define WUU_ME_WUME6(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME6_SHIFT)) & WUU_ME_WUME6_MASK)

#define WUU_ME_WUME7_MASK                        (0x80U)
#define WUU_ME_WUME7_SHIFT                       (7U)
/*! WUME7 - Module iterrupt wakeup enable for module n
 *  0b0..Disables
 *  0b1..Enables
 */
#define WUU_ME_WUME7(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME7_SHIFT)) & WUU_ME_WUME7_MASK)
/*! @} */

/*! @name DE - Module DMA/Trigger Enable */
/*! @{ */

#define WUU_DE_WUDE0_MASK                        (0x1U)
#define WUU_DE_WUDE0_SHIFT                       (0U)
/*! WUDE0 - DMA/Trigger wakeup enable for module n
 *  0b0..Disables
 *  0b1..Enables
 */
#define WUU_DE_WUDE0(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE0_SHIFT)) & WUU_DE_WUDE0_MASK)

#define WUU_DE_WUDE1_MASK                        (0x2U)
#define WUU_DE_WUDE1_SHIFT                       (1U)
/*! WUDE1 - DMA/Trigger wakeup enable for module n
 *  0b0..Disables
 *  0b1..Enables
 */
#define WUU_DE_WUDE1(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE1_SHIFT)) & WUU_DE_WUDE1_MASK)

#define WUU_DE_WUDE2_MASK                        (0x4U)
#define WUU_DE_WUDE2_SHIFT                       (2U)
/*! WUDE2 - DMA/Trigger wakeup enable for module n
 *  0b0..Disables
 *  0b1..Enables
 */
#define WUU_DE_WUDE2(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE2_SHIFT)) & WUU_DE_WUDE2_MASK)

#define WUU_DE_WUDE4_MASK                        (0x10U)
#define WUU_DE_WUDE4_SHIFT                       (4U)
/*! WUDE4 - DMA/Trigger wakeup enable for module n
 *  0b0..Disables
 *  0b1..Enables
 */
#define WUU_DE_WUDE4(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE4_SHIFT)) & WUU_DE_WUDE4_MASK)

#define WUU_DE_WUDE5_MASK                        (0x20U)
#define WUU_DE_WUDE5_SHIFT                       (5U)
/*! WUDE5 - DMA/Trigger wakeup enable for module n
 *  0b0..Disables
 *  0b1..Enables
 */
#define WUU_DE_WUDE5(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE5_SHIFT)) & WUU_DE_WUDE5_MASK)

#define WUU_DE_WUDE8_MASK                        (0x100U)
#define WUU_DE_WUDE8_SHIFT                       (8U)
/*! WUDE8 - DMA/Trigger wakeup enable for module n
 *  0b0..Disables
 *  0b1..Enables
 */
#define WUU_DE_WUDE8(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE8_SHIFT)) & WUU_DE_WUDE8_MASK)

#define WUU_DE_WUDE9_MASK                        (0x200U)
#define WUU_DE_WUDE9_SHIFT                       (9U)
/*! WUDE9 - DMA/Trigger wakeup enable for module n
 *  0b0..Disables
 *  0b1..Enables
 */
#define WUU_DE_WUDE9(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE9_SHIFT)) & WUU_DE_WUDE9_MASK)
/*! @} */

/*! @name PF - Pin Flag */
/*! @{ */

#define WUU_PF_WUF0_MASK                         (0x1U)
#define WUU_PF_WUF0_SHIFT                        (0U)
/*! WUF0 - Wakeup flag for WUU_Pn
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_PF_WUF0(x)                           (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF0_SHIFT)) & WUU_PF_WUF0_MASK)

#define WUU_PF_WUF2_MASK                         (0x4U)
#define WUU_PF_WUF2_SHIFT                        (2U)
/*! WUF2 - Wakeup flag for WUU_Pn
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_PF_WUF2(x)                           (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF2_SHIFT)) & WUU_PF_WUF2_MASK)

#define WUU_PF_WUF3_MASK                         (0x8U)
#define WUU_PF_WUF3_SHIFT                        (3U)
/*! WUF3 - Wakeup flag for WUU_Pn
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_PF_WUF3(x)                           (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF3_SHIFT)) & WUU_PF_WUF3_MASK)

#define WUU_PF_WUF4_MASK                         (0x10U)
#define WUU_PF_WUF4_SHIFT                        (4U)
/*! WUF4 - Wakeup flag for WUU_Pn
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_PF_WUF4(x)                           (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF4_SHIFT)) & WUU_PF_WUF4_MASK)

#define WUU_PF_WUF5_MASK                         (0x20U)
#define WUU_PF_WUF5_SHIFT                        (5U)
/*! WUF5 - Wakeup flag for WUU_Pn
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_PF_WUF5(x)                           (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF5_SHIFT)) & WUU_PF_WUF5_MASK)

#define WUU_PF_WUF7_MASK                         (0x80U)
#define WUU_PF_WUF7_SHIFT                        (7U)
/*! WUF7 - Wakeup flag for WUU_Pn
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_PF_WUF7(x)                           (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF7_SHIFT)) & WUU_PF_WUF7_MASK)

#define WUU_PF_WUF8_MASK                         (0x100U)
#define WUU_PF_WUF8_SHIFT                        (8U)
/*! WUF8 - Wakeup flag for WUU_Pn
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_PF_WUF8(x)                           (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF8_SHIFT)) & WUU_PF_WUF8_MASK)

#define WUU_PF_WUF9_MASK                         (0x200U)
#define WUU_PF_WUF9_SHIFT                        (9U)
/*! WUF9 - Wakeup flag for WUU_Pn
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_PF_WUF9(x)                           (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF9_SHIFT)) & WUU_PF_WUF9_MASK)

#define WUU_PF_WUF10_MASK                        (0x400U)
#define WUU_PF_WUF10_SHIFT                       (10U)
/*! WUF10 - Wakeup flag for WUU_Pn
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_PF_WUF10(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF10_SHIFT)) & WUU_PF_WUF10_MASK)

#define WUU_PF_WUF11_MASK                        (0x800U)
#define WUU_PF_WUF11_SHIFT                       (11U)
/*! WUF11 - Wakeup flag for WUU_Pn
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_PF_WUF11(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF11_SHIFT)) & WUU_PF_WUF11_MASK)

#define WUU_PF_WUF12_MASK                        (0x1000U)
#define WUU_PF_WUF12_SHIFT                       (12U)
/*! WUF12 - Wakeup flag for WUU_Pn
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_PF_WUF12(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF12_SHIFT)) & WUU_PF_WUF12_MASK)

#define WUU_PF_WUF13_MASK                        (0x2000U)
#define WUU_PF_WUF13_SHIFT                       (13U)
/*! WUF13 - Wakeup flag for WUU_Pn
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_PF_WUF13(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF13_SHIFT)) & WUU_PF_WUF13_MASK)

#define WUU_PF_WUF14_MASK                        (0x4000U)
#define WUU_PF_WUF14_SHIFT                       (14U)
/*! WUF14 - Wakeup flag for WUU_Pn
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_PF_WUF14(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF14_SHIFT)) & WUU_PF_WUF14_MASK)

#define WUU_PF_WUF15_MASK                        (0x8000U)
#define WUU_PF_WUF15_SHIFT                       (15U)
/*! WUF15 - Wakeup flag for WUU_Pn
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_PF_WUF15(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF15_SHIFT)) & WUU_PF_WUF15_MASK)

#define WUU_PF_WUF27_MASK                        (0x8000000U)
#define WUU_PF_WUF27_SHIFT                       (27U)
/*! WUF27 - Wakeup flag for WUU_Pn
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_PF_WUF27(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF27_SHIFT)) & WUU_PF_WUF27_MASK)

#define WUU_PF_WUF28_MASK                        (0x10000000U)
#define WUU_PF_WUF28_SHIFT                       (28U)
/*! WUF28 - Wakeup flag for WUU_Pn
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_PF_WUF28(x)                          (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF28_SHIFT)) & WUU_PF_WUF28_MASK)
/*! @} */

/*! @name FILT - Pin Filter */
/*! @{ */

#define WUU_FILT_FILTSEL1_MASK                   (0x1FU)
#define WUU_FILT_FILTSEL1_SHIFT                  (0U)
/*! FILTSEL1 - Filter 1 Pin Select
 */
#define WUU_FILT_FILTSEL1(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTSEL1_SHIFT)) & WUU_FILT_FILTSEL1_MASK)

#define WUU_FILT_FILTE1_MASK                     (0x60U)
#define WUU_FILT_FILTE1_SHIFT                    (5U)
/*! FILTE1 - Filter 1 Enable
 *  0b00..Disable filter
 *  0b01..Enable filter. When configured as an interrupt/DMA request: Detect on rising edge. When configured as a
 *        trigger request: Detect on high level
 *  0b10..Enable filter. When configured as an interrupt/DMA request: Detect on falling edge. When configured as a
 *        trigger request: Detect on low level
 *  0b11..Enable filter. When configured as an interrupt/DMA request: Detect on any edge
 */
#define WUU_FILT_FILTE1(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTE1_SHIFT)) & WUU_FILT_FILTE1_MASK)

#define WUU_FILT_FILTF1_MASK                     (0x80U)
#define WUU_FILT_FILTF1_SHIFT                    (7U)
/*! FILTF1 - Filter 1 Flag
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_FILT_FILTF1(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTF1_SHIFT)) & WUU_FILT_FILTF1_MASK)

#define WUU_FILT_FILTSEL2_MASK                   (0x1F00U)
#define WUU_FILT_FILTSEL2_SHIFT                  (8U)
/*! FILTSEL2 - Filter 2 Pin Select
 */
#define WUU_FILT_FILTSEL2(x)                     (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTSEL2_SHIFT)) & WUU_FILT_FILTSEL2_MASK)

#define WUU_FILT_FILTE2_MASK                     (0x6000U)
#define WUU_FILT_FILTE2_SHIFT                    (13U)
/*! FILTE2 - Filter 2 Enable
 *  0b00..Disable filter
 *  0b01..Enable filter. When configured as an interrupt/DMA request: Detect on rising edge. When configured as a
 *        trigger request: Detect on high level
 *  0b10..Enable filter. When configured as an interrupt/DMA request: Detect on falling edge. When configured as a
 *        trigger request: Detect on low level
 *  0b11..Enable filter. When configured as an interrupt/DMA request: Detect on any edge
 */
#define WUU_FILT_FILTE2(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTE2_SHIFT)) & WUU_FILT_FILTE2_MASK)

#define WUU_FILT_FILTF2_MASK                     (0x8000U)
#define WUU_FILT_FILTF2_SHIFT                    (15U)
/*! FILTF2 - Filter 2 Flag
 *  0b0..No
 *  0b1..Yes
 */
#define WUU_FILT_FILTF2(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTF2_SHIFT)) & WUU_FILT_FILTF2_MASK)
/*! @} */

/*! @name PDC1 - Pin DMA/Trigger Configuration 1 */
/*! @{ */

#define WUU_PDC1_WUPDC0_MASK                     (0x3U)
#define WUU_PDC1_WUPDC0_SHIFT                    (0U)
/*! WUPDC0 - Wakeup pin configuration for WUU_Pn
 *  0b00..Interrupt
 *  0b01..DMA request
 *  0b10..Trigger event
 *  0b11..Reserved
 */
#define WUU_PDC1_WUPDC0(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC0_SHIFT)) & WUU_PDC1_WUPDC0_MASK)

#define WUU_PDC1_WUPDC1_MASK                     (0xCU)
#define WUU_PDC1_WUPDC1_SHIFT                    (2U)
/*! WUPDC1 - Reserved
 *  0b00..Not supported
 *  0b01..Not supported
 *  0b10..Not supported
 *  0b11..Reserved
 */
#define WUU_PDC1_WUPDC1(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC1_SHIFT)) & WUU_PDC1_WUPDC1_MASK)

#define WUU_PDC1_WUPDC2_MASK                     (0x30U)
#define WUU_PDC1_WUPDC2_SHIFT                    (4U)
/*! WUPDC2 - Wakeup pin configuration for WUU_Pn
 *  0b00..Interrupt
 *  0b01..DMA request
 *  0b10..Trigger event
 *  0b11..Reserved
 */
#define WUU_PDC1_WUPDC2(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC2_SHIFT)) & WUU_PDC1_WUPDC2_MASK)

#define WUU_PDC1_WUPDC3_MASK                     (0xC0U)
#define WUU_PDC1_WUPDC3_SHIFT                    (6U)
/*! WUPDC3 - Wakeup pin configuration for WUU_Pn
 *  0b00..Interrupt
 *  0b01..DMA request
 *  0b10..Trigger event
 *  0b11..Reserved
 */
#define WUU_PDC1_WUPDC3(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC3_SHIFT)) & WUU_PDC1_WUPDC3_MASK)

#define WUU_PDC1_WUPDC4_MASK                     (0x300U)
#define WUU_PDC1_WUPDC4_SHIFT                    (8U)
/*! WUPDC4 - Wakeup pin configuration for WUU_Pn
 *  0b00..Interrupt
 *  0b01..DMA request
 *  0b10..Trigger event
 *  0b11..Reserved
 */
#define WUU_PDC1_WUPDC4(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC4_SHIFT)) & WUU_PDC1_WUPDC4_MASK)

#define WUU_PDC1_WUPDC5_MASK                     (0xC00U)
#define WUU_PDC1_WUPDC5_SHIFT                    (10U)
/*! WUPDC5 - Wakeup pin configuration for WUU_Pn
 *  0b00..Interrupt
 *  0b01..DMA request
 *  0b10..Trigger event
 *  0b11..Reserved
 */
#define WUU_PDC1_WUPDC5(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC5_SHIFT)) & WUU_PDC1_WUPDC5_MASK)

#define WUU_PDC1_WUPDC6_MASK                     (0x3000U)
#define WUU_PDC1_WUPDC6_SHIFT                    (12U)
/*! WUPDC6 - Reserved
 *  0b00..Not supported
 *  0b01..Not supported
 *  0b10..Not supported
 *  0b11..Reserved
 */
#define WUU_PDC1_WUPDC6(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC6_SHIFT)) & WUU_PDC1_WUPDC6_MASK)

#define WUU_PDC1_WUPDC7_MASK                     (0xC000U)
#define WUU_PDC1_WUPDC7_SHIFT                    (14U)
/*! WUPDC7 - Wakeup pin configuration for WUU_Pn
 *  0b00..Interrupt
 *  0b01..DMA request
 *  0b10..Trigger event
 *  0b11..Reserved
 */
#define WUU_PDC1_WUPDC7(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC7_SHIFT)) & WUU_PDC1_WUPDC7_MASK)

#define WUU_PDC1_WUPDC8_MASK                     (0x30000U)
#define WUU_PDC1_WUPDC8_SHIFT                    (16U)
/*! WUPDC8 - Wakeup pin configuration for WUU_Pn
 *  0b00..Interrupt
 *  0b01..DMA request
 *  0b10..Trigger event
 *  0b11..Reserved
 */
#define WUU_PDC1_WUPDC8(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC8_SHIFT)) & WUU_PDC1_WUPDC8_MASK)

#define WUU_PDC1_WUPDC9_MASK                     (0xC0000U)
#define WUU_PDC1_WUPDC9_SHIFT                    (18U)
/*! WUPDC9 - Wakeup pin configuration for WUU_Pn
 *  0b00..Interrupt
 *  0b01..DMA request
 *  0b10..Trigger event
 *  0b11..Reserved
 */
#define WUU_PDC1_WUPDC9(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC9_SHIFT)) & WUU_PDC1_WUPDC9_MASK)

#define WUU_PDC1_WUPDC10_MASK                    (0x300000U)
#define WUU_PDC1_WUPDC10_SHIFT                   (20U)
/*! WUPDC10 - Wakeup pin configuration for WUU_Pn
 *  0b00..Interrupt
 *  0b01..DMA request
 *  0b10..Trigger event
 *  0b11..Reserved
 */
#define WUU_PDC1_WUPDC10(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC10_SHIFT)) & WUU_PDC1_WUPDC10_MASK)

#define WUU_PDC1_WUPDC11_MASK                    (0xC00000U)
#define WUU_PDC1_WUPDC11_SHIFT                   (22U)
/*! WUPDC11 - Wakeup pin configuration for WUU_Pn
 *  0b00..Interrupt
 *  0b01..DMA request
 *  0b10..Trigger event
 *  0b11..Reserved
 */
#define WUU_PDC1_WUPDC11(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC11_SHIFT)) & WUU_PDC1_WUPDC11_MASK)

#define WUU_PDC1_WUPDC12_MASK                    (0x3000000U)
#define WUU_PDC1_WUPDC12_SHIFT                   (24U)
/*! WUPDC12 - Wakeup pin configuration for WUU_Pn
 *  0b00..Interrupt
 *  0b01..DMA request
 *  0b10..Trigger event
 *  0b11..Reserved
 */
#define WUU_PDC1_WUPDC12(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC12_SHIFT)) & WUU_PDC1_WUPDC12_MASK)

#define WUU_PDC1_WUPDC13_MASK                    (0xC000000U)
#define WUU_PDC1_WUPDC13_SHIFT                   (26U)
/*! WUPDC13 - Wakeup pin configuration for WUU_Pn
 *  0b00..Interrupt
 *  0b01..DMA request
 *  0b10..Trigger event
 *  0b11..Reserved
 */
#define WUU_PDC1_WUPDC13(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC13_SHIFT)) & WUU_PDC1_WUPDC13_MASK)

#define WUU_PDC1_WUPDC14_MASK                    (0x30000000U)
#define WUU_PDC1_WUPDC14_SHIFT                   (28U)
/*! WUPDC14 - Wakeup pin configuration for WUU_Pn
 *  0b00..Interrupt
 *  0b01..DMA request
 *  0b10..Trigger event
 *  0b11..Reserved
 */
#define WUU_PDC1_WUPDC14(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC14_SHIFT)) & WUU_PDC1_WUPDC14_MASK)

#define WUU_PDC1_WUPDC15_MASK                    (0xC0000000U)
#define WUU_PDC1_WUPDC15_SHIFT                   (30U)
/*! WUPDC15 - Wakeup pin configuration for WUU_Pn
 *  0b00..Interrupt
 *  0b01..DMA request
 *  0b10..Trigger event
 *  0b11..Reserved
 */
#define WUU_PDC1_WUPDC15(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC15_SHIFT)) & WUU_PDC1_WUPDC15_MASK)
/*! @} */

/*! @name PDC2 - Pin DMA/Trigger Configuration 2 */
/*! @{ */

#define WUU_PDC2_WUPDC27_MASK                    (0xC00000U)
#define WUU_PDC2_WUPDC27_SHIFT                   (22U)
/*! WUPDC27 - Wakeup pin configuration for WUU_Pn
 *  0b00..Interrupt
 *  0b01..DMA request
 *  0b10..Trigger event
 *  0b11..Reserved
 */
#define WUU_PDC2_WUPDC27(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC27_SHIFT)) & WUU_PDC2_WUPDC27_MASK)

#define WUU_PDC2_WUPDC28_MASK                    (0x3000000U)
#define WUU_PDC2_WUPDC28_SHIFT                   (24U)
/*! WUPDC28 - Wakeup pin configuration for WUU_Pn
 *  0b00..Interrupt
 *  0b01..DMA request
 *  0b10..Trigger event
 *  0b11..Reserved
 */
#define WUU_PDC2_WUPDC28(x)                      (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC28_SHIFT)) & WUU_PDC2_WUPDC28_MASK)
/*! @} */

/*! @name FDC - Pin Filter DMA/Trigger Configuration */
/*! @{ */

#define WUU_FDC_FILTC1_MASK                      (0x3U)
#define WUU_FDC_FILTC1_SHIFT                     (0U)
/*! FILTC1 - Filter configuration for FILTn
 *  0b00..Interrupt
 *  0b01..DMA request
 *  0b10..Trigger event
 *  0b11..Reserved
 */
#define WUU_FDC_FILTC1(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_FDC_FILTC1_SHIFT)) & WUU_FDC_FILTC1_MASK)

#define WUU_FDC_FILTC2_MASK                      (0xCU)
#define WUU_FDC_FILTC2_SHIFT                     (2U)
/*! FILTC2 - Filter configuration for FILTn
 *  0b00..Interrupt
 *  0b01..DMA request
 *  0b10..Trigger event
 *  0b11..Reserved
 */
#define WUU_FDC_FILTC2(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_FDC_FILTC2_SHIFT)) & WUU_FDC_FILTC2_MASK)
/*! @} */

/*! @name PMC - Pin Mode Configuration */
/*! @{ */

#define WUU_PMC_WUPMC0_MASK                      (0x1U)
#define WUU_PMC_WUPMC0_SHIFT                     (0U)
/*! WUPMC0 - Wakeup pin mode configuration for WUU_Pn
 *  0b0..Active only during a low-leakage mode. Software can modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 *  0b1..Active during all power modes. Software must not modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 */
#define WUU_PMC_WUPMC0(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC0_SHIFT)) & WUU_PMC_WUPMC0_MASK)

#define WUU_PMC_WUPMC2_MASK                      (0x4U)
#define WUU_PMC_WUPMC2_SHIFT                     (2U)
/*! WUPMC2 - Wakeup pin mode configuration for WUU_Pn
 *  0b0..Active only during a low-leakage mode. Software can modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 *  0b1..Active during all power modes. Software must not modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 */
#define WUU_PMC_WUPMC2(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC2_SHIFT)) & WUU_PMC_WUPMC2_MASK)

#define WUU_PMC_WUPMC3_MASK                      (0x8U)
#define WUU_PMC_WUPMC3_SHIFT                     (3U)
/*! WUPMC3 - Wakeup pin mode configuration for WUU_Pn
 *  0b0..Active only during a low-leakage mode. Software can modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 *  0b1..Active during all power modes. Software must not modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 */
#define WUU_PMC_WUPMC3(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC3_SHIFT)) & WUU_PMC_WUPMC3_MASK)

#define WUU_PMC_WUPMC4_MASK                      (0x10U)
#define WUU_PMC_WUPMC4_SHIFT                     (4U)
/*! WUPMC4 - Wakeup pin mode configuration for WUU_Pn
 *  0b0..Active only during a low-leakage mode. Software can modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 *  0b1..Active during all power modes. Software must not modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 */
#define WUU_PMC_WUPMC4(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC4_SHIFT)) & WUU_PMC_WUPMC4_MASK)

#define WUU_PMC_WUPMC5_MASK                      (0x20U)
#define WUU_PMC_WUPMC5_SHIFT                     (5U)
/*! WUPMC5 - Wakeup pin mode configuration for WUU_Pn
 *  0b0..Active only during a low-leakage mode. Software can modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 *  0b1..Active during all power modes. Software must not modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 */
#define WUU_PMC_WUPMC5(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC5_SHIFT)) & WUU_PMC_WUPMC5_MASK)

#define WUU_PMC_WUPMC7_MASK                      (0x80U)
#define WUU_PMC_WUPMC7_SHIFT                     (7U)
/*! WUPMC7 - Wakeup pin mode configuration for WUU_Pn
 *  0b0..Active only during a low-leakage mode. Software can modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 *  0b1..Active during all power modes. Software must not modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 */
#define WUU_PMC_WUPMC7(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC7_SHIFT)) & WUU_PMC_WUPMC7_MASK)

#define WUU_PMC_WUPMC8_MASK                      (0x100U)
#define WUU_PMC_WUPMC8_SHIFT                     (8U)
/*! WUPMC8 - Wakeup pin mode configuration for WUU_Pn
 *  0b0..Active only during a low-leakage mode. Software can modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 *  0b1..Active during all power modes. Software must not modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 */
#define WUU_PMC_WUPMC8(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC8_SHIFT)) & WUU_PMC_WUPMC8_MASK)

#define WUU_PMC_WUPMC9_MASK                      (0x200U)
#define WUU_PMC_WUPMC9_SHIFT                     (9U)
/*! WUPMC9 - Wakeup pin mode configuration for WUU_Pn
 *  0b0..Active only during a low-leakage mode. Software can modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 *  0b1..Active during all power modes. Software must not modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 */
#define WUU_PMC_WUPMC9(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC9_SHIFT)) & WUU_PMC_WUPMC9_MASK)

#define WUU_PMC_WUPMC10_MASK                     (0x400U)
#define WUU_PMC_WUPMC10_SHIFT                    (10U)
/*! WUPMC10 - Wakeup pin mode configuration for WUU_Pn
 *  0b0..Active only during a low-leakage mode. Software can modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 *  0b1..Active during all power modes. Software must not modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 */
#define WUU_PMC_WUPMC10(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC10_SHIFT)) & WUU_PMC_WUPMC10_MASK)

#define WUU_PMC_WUPMC11_MASK                     (0x800U)
#define WUU_PMC_WUPMC11_SHIFT                    (11U)
/*! WUPMC11 - Wakeup pin mode configuration for WUU_Pn
 *  0b0..Active only during a low-leakage mode. Software can modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 *  0b1..Active during all power modes. Software must not modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 */
#define WUU_PMC_WUPMC11(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC11_SHIFT)) & WUU_PMC_WUPMC11_MASK)

#define WUU_PMC_WUPMC12_MASK                     (0x1000U)
#define WUU_PMC_WUPMC12_SHIFT                    (12U)
/*! WUPMC12 - Wakeup pin mode configuration for WUU_Pn
 *  0b0..Active only during a low-leakage mode. Software can modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 *  0b1..Active during all power modes. Software must not modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 */
#define WUU_PMC_WUPMC12(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC12_SHIFT)) & WUU_PMC_WUPMC12_MASK)

#define WUU_PMC_WUPMC13_MASK                     (0x2000U)
#define WUU_PMC_WUPMC13_SHIFT                    (13U)
/*! WUPMC13 - Wakeup pin mode configuration for WUU_Pn
 *  0b0..Active only during a low-leakage mode. Software can modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 *  0b1..Active during all power modes. Software must not modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 */
#define WUU_PMC_WUPMC13(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC13_SHIFT)) & WUU_PMC_WUPMC13_MASK)

#define WUU_PMC_WUPMC14_MASK                     (0x4000U)
#define WUU_PMC_WUPMC14_SHIFT                    (14U)
/*! WUPMC14 - Wakeup pin mode configuration for WUU_Pn
 *  0b0..Active only during a low-leakage mode. Software can modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 *  0b1..Active during all power modes. Software must not modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 */
#define WUU_PMC_WUPMC14(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC14_SHIFT)) & WUU_PMC_WUPMC14_MASK)

#define WUU_PMC_WUPMC15_MASK                     (0x8000U)
#define WUU_PMC_WUPMC15_SHIFT                    (15U)
/*! WUPMC15 - Wakeup pin mode configuration for WUU_Pn
 *  0b0..Active only during a low-leakage mode. Software can modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 *  0b1..Active during all power modes. Software must not modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 */
#define WUU_PMC_WUPMC15(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC15_SHIFT)) & WUU_PMC_WUPMC15_MASK)

#define WUU_PMC_WUPMC27_MASK                     (0x8000000U)
#define WUU_PMC_WUPMC27_SHIFT                    (27U)
/*! WUPMC27 - Wakeup pin mode configuration for WUU_Pn
 *  0b0..Active only during a low-leakage mode. Software can modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 *  0b1..Active during all power modes. Software must not modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 */
#define WUU_PMC_WUPMC27(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC27_SHIFT)) & WUU_PMC_WUPMC27_MASK)

#define WUU_PMC_WUPMC28_MASK                     (0x10000000U)
#define WUU_PMC_WUPMC28_SHIFT                    (28U)
/*! WUPMC28 - Wakeup pin mode configuration for WUU_Pn
 *  0b0..Active only during a low-leakage mode. Software can modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 *  0b1..Active during all power modes. Software must not modify the corresponding fields within the Pin Enable
 *       (PEn) or Pin DMA/Trigger Configuration (PDCn) registers.
 */
#define WUU_PMC_WUPMC28(x)                       (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC28_SHIFT)) & WUU_PMC_WUPMC28_MASK)
/*! @} */

/*! @name FMC - Pin Filter Mode Configuration */
/*! @{ */

#define WUU_FMC_FILTM1_MASK                      (0x1U)
#define WUU_FMC_FILTM1_SHIFT                     (0U)
/*! FILTM1 - Filter Mode for FILTn
 *  0b0..Active only during Deep Sleep/Power Down mode
 *  0b1..Active during all power modes
 */
#define WUU_FMC_FILTM1(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_FMC_FILTM1_SHIFT)) & WUU_FMC_FILTM1_MASK)

#define WUU_FMC_FILTM2_MASK                      (0x2U)
#define WUU_FMC_FILTM2_SHIFT                     (1U)
/*! FILTM2 - Filter Mode for FILTn
 *  0b0..Active only during Deep Sleep/Power Down mode
 *  0b1..Active during all power modes
 */
#define WUU_FMC_FILTM2(x)                        (((uint32_t)(((uint32_t)(x)) << WUU_FMC_FILTM2_SHIFT)) & WUU_FMC_FILTM2_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group WUU_Register_Masks */


/* WUU - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral WUU0 base address */
  #define WUU0_BASE                                (0x50019000u)
  /** Peripheral WUU0 base address */
  #define WUU0_BASE_NS                             (0x40019000u)
  /** Peripheral WUU0 base pointer */
  #define WUU0                                     ((WUU_Type *)WUU0_BASE)
  /** Peripheral WUU0 base pointer */
  #define WUU0_NS                                  ((WUU_Type *)WUU0_BASE_NS)
  /** Array initializer of WUU peripheral base addresses */
  #define WUU_BASE_ADDRS                           { WUU0_BASE }
  /** Array initializer of WUU peripheral base pointers */
  #define WUU_BASE_PTRS                            { WUU0 }
  /** Array initializer of WUU peripheral base addresses */
  #define WUU_BASE_ADDRS_NS                        { WUU0_BASE_NS }
  /** Array initializer of WUU peripheral base pointers */
  #define WUU_BASE_PTRS_NS                         { WUU0_NS }
#else
  /** Peripheral WUU0 base address */
  #define WUU0_BASE                                (0x40019000u)
  /** Peripheral WUU0 base pointer */
  #define WUU0                                     ((WUU_Type *)WUU0_BASE)
  /** Array initializer of WUU peripheral base addresses */
  #define WUU_BASE_ADDRS                           { WUU0_BASE }
  /** Array initializer of WUU peripheral base pointers */
  #define WUU_BASE_PTRS                            { WUU0 }
#endif
/** Interrupt vectors for the WUU peripheral type */
#define WUU_IRQS                                 { WUU0_IRQn }

/*!
 * @}
 */ /* end of group WUU_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- XCVR_ANALOG Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup XCVR_ANALOG_Peripheral_Access_Layer XCVR_ANALOG Peripheral Access Layer
 * @{
 */

/** XCVR_ANALOG - Register Layout Typedef */
typedef struct {
  __IO uint32_t LDO_0;                             /**< RF Analog Baseband LDO Control 1, offset: 0x0 */
  __IO uint32_t LDO_1;                             /**< RF Analog Baseband LDO Control 2, offset: 0x4 */
  __IO uint32_t XO_DIST;                           /**< RF Analog XO DIST Control, offset: 0x8 */
  __IO uint32_t PLL;                               /**< RF Analog PLL Control, offset: 0xC */
  __IO uint32_t RX_0;                              /**< RF Analog RX Control0, offset: 0x10 */
  __IO uint32_t RX_1;                              /**< RF Analog RX Control1, offset: 0x14 */
  __IO uint32_t TX_DAC_PA;                         /**< RF Analog TX DAC PA Control, offset: 0x18 */
  __IO uint32_t DIAG;                              /**< RF Analog DIAG Control 1, offset: 0x1C */
  __IO uint32_t SPARE;                             /**< RF Analog SPARE Control, offset: 0x20 */
} XCVR_ANALOG_Type;

/* ----------------------------------------------------------------------------
   -- XCVR_ANALOG Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup XCVR_ANALOG_Register_Masks XCVR_ANALOG Register Masks
 * @{
 */

/*! @name LDO_0 - RF Analog Baseband LDO Control 1 */
/*! @{ */

#define XCVR_ANALOG_LDO_0_BG_FORCE_MASK          (0x8U)
#define XCVR_ANALOG_LDO_0_BG_FORCE_SHIFT         (3U)
/*! BG_FORCE - reg_bg_force_dig
 *  0b0..force disable
 *  0b1..force enable
 */
#define XCVR_ANALOG_LDO_0_BG_FORCE(x)            (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_LDO_0_BG_FORCE_SHIFT)) & XCVR_ANALOG_LDO_0_BG_FORCE_MASK)

#define XCVR_ANALOG_LDO_0_LDO_LV_TRIM_MASK       (0x30U)
#define XCVR_ANALOG_LDO_0_LDO_LV_TRIM_SHIFT      (4U)
/*! LDO_LV_TRIM - reg_ldo_lv_trim_dig[1:0]
 *  0b00..0.91V Default LDO output
 *  0b01..0.86V
 *  0b10..0.97V
 *  0b11..1.3V
 */
#define XCVR_ANALOG_LDO_0_LDO_LV_TRIM(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_LDO_0_LDO_LV_TRIM_SHIFT)) & XCVR_ANALOG_LDO_0_LDO_LV_TRIM_MASK)

#define XCVR_ANALOG_LDO_0_LDO_LV_BYPASS_MASK     (0x40U)
#define XCVR_ANALOG_LDO_0_LDO_LV_BYPASS_SHIFT    (6U)
/*! LDO_LV_BYPASS - reg_ldo_lv_bypass_dig
 *  0b0..disable bypass for ldo_lv
 *  0b1..enable bypass for ldo_lv
 */
#define XCVR_ANALOG_LDO_0_LDO_LV_BYPASS(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_LDO_0_LDO_LV_BYPASS_SHIFT)) & XCVR_ANALOG_LDO_0_LDO_LV_BYPASS_MASK)

#define XCVR_ANALOG_LDO_0_LDO_RXTXHF_FORCE_MASK  (0x100U)
#define XCVR_ANALOG_LDO_0_LDO_RXTXHF_FORCE_SHIFT (8U)
/*! LDO_RXTXHF_FORCE - reg_ldo_rxtxhf_force_dig
 *  0b0..Force disabled.
 *  0b1..Force enabled
 */
#define XCVR_ANALOG_LDO_0_LDO_RXTXHF_FORCE(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_LDO_0_LDO_RXTXHF_FORCE_SHIFT)) & XCVR_ANALOG_LDO_0_LDO_RXTXHF_FORCE_MASK)

#define XCVR_ANALOG_LDO_0_LDO_RXTXHF_PTAT_BUMP_MASK (0x600U)
#define XCVR_ANALOG_LDO_0_LDO_RXTXHF_PTAT_BUMP_SHIFT (9U)
/*! LDO_RXTXHF_PTAT_BUMP - reg_ldo_rxtxhf_ptat_bump_dig
 *  0b00..nominal
 *  0b01..+30%
 *  0b10..nominal
 *  0b11..+30%
 */
#define XCVR_ANALOG_LDO_0_LDO_RXTXHF_PTAT_BUMP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_LDO_0_LDO_RXTXHF_PTAT_BUMP_SHIFT)) & XCVR_ANALOG_LDO_0_LDO_RXTXHF_PTAT_BUMP_MASK)

#define XCVR_ANALOG_LDO_0_LDO_RXTXHF_BYPASS_MASK (0x800U)
#define XCVR_ANALOG_LDO_0_LDO_RXTXHF_BYPASS_SHIFT (11U)
/*! LDO_RXTXHF_BYPASS - reg_ldo_rxtxihf_bypass_dig
 */
#define XCVR_ANALOG_LDO_0_LDO_RXTXHF_BYPASS(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_LDO_0_LDO_RXTXHF_BYPASS_SHIFT)) & XCVR_ANALOG_LDO_0_LDO_RXTXHF_BYPASS_MASK)

#define XCVR_ANALOG_LDO_0_LDO_RXTXLF_FORCE_MASK  (0x1000U)
#define XCVR_ANALOG_LDO_0_LDO_RXTXLF_FORCE_SHIFT (12U)
/*! LDO_RXTXLF_FORCE - reg_ldo_rxtxlf_force_dig
 *  0b0..disable force
 *  0b1..enable force
 */
#define XCVR_ANALOG_LDO_0_LDO_RXTXLF_FORCE(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_LDO_0_LDO_RXTXLF_FORCE_SHIFT)) & XCVR_ANALOG_LDO_0_LDO_RXTXLF_FORCE_MASK)

#define XCVR_ANALOG_LDO_0_LDO_RXTXLF_PTAT_BUMP_MASK (0x6000U)
#define XCVR_ANALOG_LDO_0_LDO_RXTXLF_PTAT_BUMP_SHIFT (13U)
/*! LDO_RXTXLF_PTAT_BUMP - reg_ldo_rxtxlf_ptat_bump_dig[1:0]
 *  0b00..nominal
 *  0b01..+30%
 *  0b10..nominal
 *  0b11..+30%
 */
#define XCVR_ANALOG_LDO_0_LDO_RXTXLF_PTAT_BUMP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_LDO_0_LDO_RXTXLF_PTAT_BUMP_SHIFT)) & XCVR_ANALOG_LDO_0_LDO_RXTXLF_PTAT_BUMP_MASK)

#define XCVR_ANALOG_LDO_0_LDO_RXTXLF_BYPASS_MASK (0x8000U)
#define XCVR_ANALOG_LDO_0_LDO_RXTXLF_BYPASS_SHIFT (15U)
/*! LDO_RXTXLF_BYPASS - reg_ldo_rxtxlf_bypass_dig
 *  0b0..Bypass disable
 *  0b1..Bypass enable
 */
#define XCVR_ANALOG_LDO_0_LDO_RXTXLF_BYPASS(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_LDO_0_LDO_RXTXLF_BYPASS_SHIFT)) & XCVR_ANALOG_LDO_0_LDO_RXTXLF_BYPASS_MASK)

#define XCVR_ANALOG_LDO_0_LDO_PLL_FORCE_MASK     (0x10000U)
#define XCVR_ANALOG_LDO_0_LDO_PLL_FORCE_SHIFT    (16U)
/*! LDO_PLL_FORCE - reg_ldo_pll_force_dig
 *  0b0..force disable
 *  0b1..force enable
 */
#define XCVR_ANALOG_LDO_0_LDO_PLL_FORCE(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_LDO_0_LDO_PLL_FORCE_SHIFT)) & XCVR_ANALOG_LDO_0_LDO_PLL_FORCE_MASK)

#define XCVR_ANALOG_LDO_0_LDO_PLL_PTAT_BUMP_MASK (0x60000U)
#define XCVR_ANALOG_LDO_0_LDO_PLL_PTAT_BUMP_SHIFT (17U)
/*! LDO_PLL_PTAT_BUMP - reg_ldo_pll_ptat_bump_dig[1:0]
 *  0b00..nominal
 *  0b01..+30%
 *  0b10..nominal
 *  0b11..+30%
 */
#define XCVR_ANALOG_LDO_0_LDO_PLL_PTAT_BUMP(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_LDO_0_LDO_PLL_PTAT_BUMP_SHIFT)) & XCVR_ANALOG_LDO_0_LDO_PLL_PTAT_BUMP_MASK)

#define XCVR_ANALOG_LDO_0_LDO_PLL_BYPASS_MASK    (0x80000U)
#define XCVR_ANALOG_LDO_0_LDO_PLL_BYPASS_SHIFT   (19U)
/*! LDO_PLL_BYPASS - reg_ldo_pll_bypass_dig
 *  0b0..Bypass disabled.
 *  0b1..Bypass enabled
 */
#define XCVR_ANALOG_LDO_0_LDO_PLL_BYPASS(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_LDO_0_LDO_PLL_BYPASS_SHIFT)) & XCVR_ANALOG_LDO_0_LDO_PLL_BYPASS_MASK)

#define XCVR_ANALOG_LDO_0_LDO_VCO_FORCE_MASK     (0x100000U)
#define XCVR_ANALOG_LDO_0_LDO_VCO_FORCE_SHIFT    (20U)
/*! LDO_VCO_FORCE - reg_ldo_vco_force_dig
 *  0b0..Force disable
 *  0b1..Force enable
 */
#define XCVR_ANALOG_LDO_0_LDO_VCO_FORCE(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_LDO_0_LDO_VCO_FORCE_SHIFT)) & XCVR_ANALOG_LDO_0_LDO_VCO_FORCE_MASK)

#define XCVR_ANALOG_LDO_0_LDO_VCO_PTAT_BUMP_MASK (0x600000U)
#define XCVR_ANALOG_LDO_0_LDO_VCO_PTAT_BUMP_SHIFT (21U)
/*! LDO_VCO_PTAT_BUMP - reg_ldo_vco_ptat_bump_dig[1:0]
 *  0b00..nominal
 *  0b01..+30%
 *  0b10..nominal
 *  0b11..+30%
 */
#define XCVR_ANALOG_LDO_0_LDO_VCO_PTAT_BUMP(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_LDO_0_LDO_VCO_PTAT_BUMP_SHIFT)) & XCVR_ANALOG_LDO_0_LDO_VCO_PTAT_BUMP_MASK)

#define XCVR_ANALOG_LDO_0_LDO_VCO_BYPASS_MASK    (0x800000U)
#define XCVR_ANALOG_LDO_0_LDO_VCO_BYPASS_SHIFT   (23U)
/*! LDO_VCO_BYPASS - reg_ldo_vco_bypass_dig
 *  0b0..disable VCO bypass
 *  0b1..eable VCO bypass
 */
#define XCVR_ANALOG_LDO_0_LDO_VCO_BYPASS(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_LDO_0_LDO_VCO_BYPASS_SHIFT)) & XCVR_ANALOG_LDO_0_LDO_VCO_BYPASS_MASK)

#define XCVR_ANALOG_LDO_0_LDO_CAL_FORCE_MASK     (0x1000000U)
#define XCVR_ANALOG_LDO_0_LDO_CAL_FORCE_SHIFT    (24U)
/*! LDO_CAL_FORCE - reg_ldo_cal_force_dig
 *  0b0..Force disable
 *  0b1..Force enable
 */
#define XCVR_ANALOG_LDO_0_LDO_CAL_FORCE(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_LDO_0_LDO_CAL_FORCE_SHIFT)) & XCVR_ANALOG_LDO_0_LDO_CAL_FORCE_MASK)

#define XCVR_ANALOG_LDO_0_LDO_CAL_PTAT_BUMP_MASK (0x6000000U)
#define XCVR_ANALOG_LDO_0_LDO_CAL_PTAT_BUMP_SHIFT (25U)
/*! LDO_CAL_PTAT_BUMP - reg_ldo_vco_ptat_bump_dig[1:0]
 *  0b00..nominal
 *  0b01..+30%
 *  0b10..nominal
 *  0b11..+30%
 */
#define XCVR_ANALOG_LDO_0_LDO_CAL_PTAT_BUMP(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_LDO_0_LDO_CAL_PTAT_BUMP_SHIFT)) & XCVR_ANALOG_LDO_0_LDO_CAL_PTAT_BUMP_MASK)

#define XCVR_ANALOG_LDO_0_LDO_CAL_BYPASS_MASK    (0x8000000U)
#define XCVR_ANALOG_LDO_0_LDO_CAL_BYPASS_SHIFT   (27U)
/*! LDO_CAL_BYPASS - reg_ldo_cal_bypass_dig
 *  0b0..disable CAL bypass
 *  0b1..eable CAL bypass
 */
#define XCVR_ANALOG_LDO_0_LDO_CAL_BYPASS(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_LDO_0_LDO_CAL_BYPASS_SHIFT)) & XCVR_ANALOG_LDO_0_LDO_CAL_BYPASS_MASK)

#define XCVR_ANALOG_LDO_0_LDOTRIM_TRIM_VREF_MASK (0x30000000U)
#define XCVR_ANALOG_LDO_0_LDOTRIM_TRIM_VREF_SHIFT (28U)
/*! LDOTRIM_TRIM_VREF - reg_ldotrim_trim_vref_dig[1:0]
 *  0b00..0.810
 *  0b01..0.832
 *  0b10..0.854
 *  0b11..0.788
 */
#define XCVR_ANALOG_LDO_0_LDOTRIM_TRIM_VREF(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_LDO_0_LDOTRIM_TRIM_VREF_SHIFT)) & XCVR_ANALOG_LDO_0_LDOTRIM_TRIM_VREF_MASK)
/*! @} */

/*! @name LDO_1 - RF Analog Baseband LDO Control 2 */
/*! @{ */

#define XCVR_ANALOG_LDO_1_LDO_ANT_TRIM_MASK      (0xFU)
#define XCVR_ANALOG_LDO_1_LDO_ANT_TRIM_SHIFT     (0U)
/*! LDO_ANT_TRIM - reg_ldo_ant_trim_dig[3:0]
 *  0b0000..0.91 V ( Default )
 *  0b0001..0.97 V
 *  0b0010..1.04 V
 *  0b0011..1.12 V
 *  0b0100..1.21 V
 *  0b0101..1.32 V
 *  0b0110..1.45 V
 *  0b0111..1.52 V
 *  0b1000..1.61 V
 *  0b1001..1.80 V
 *  0b1010..2.06 V
 *  0b1011..2.13 V
 *  0b1100..2.21 V
 *  0b1101..2.30 V
 *  0b1110..2.39 V
 *  0b1111..2.50 V
 */
#define XCVR_ANALOG_LDO_1_LDO_ANT_TRIM(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_LDO_1_LDO_ANT_TRIM_SHIFT)) & XCVR_ANALOG_LDO_1_LDO_ANT_TRIM_MASK)

#define XCVR_ANALOG_LDO_1_LDO_ANT_HIZ_MASK       (0x80U)
#define XCVR_ANALOG_LDO_1_LDO_ANT_HIZ_SHIFT      (7U)
/*! LDO_ANT_HIZ - reg_ldo_ant_hiz_dig
 *  0b0..high-impedance disabled.
 *  0b1..high-impedance enabled
 */
#define XCVR_ANALOG_LDO_1_LDO_ANT_HIZ(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_LDO_1_LDO_ANT_HIZ_SHIFT)) & XCVR_ANALOG_LDO_1_LDO_ANT_HIZ_MASK)

#define XCVR_ANALOG_LDO_1_LDO_ANT_BYPASS_MASK    (0x100U)
#define XCVR_ANALOG_LDO_1_LDO_ANT_BYPASS_SHIFT   (8U)
/*! LDO_ANT_BYPASS - reg_ldo_ant_bypass_dig
 *  0b0..ANT bypass disable
 *  0b1..ANT bypass enable
 */
#define XCVR_ANALOG_LDO_1_LDO_ANT_BYPASS(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_LDO_1_LDO_ANT_BYPASS_SHIFT)) & XCVR_ANALOG_LDO_1_LDO_ANT_BYPASS_MASK)

#define XCVR_ANALOG_LDO_1_LDO_ANT_REF_SEL_MASK   (0x200U)
#define XCVR_ANALOG_LDO_1_LDO_ANT_REF_SEL_SHIFT  (9U)
/*! LDO_ANT_REF_SEL - reg_ldo_ant_ref_sel_dig
 *  0b0..sel type disable ( Default )
 *  0b1..sel type enable
 */
#define XCVR_ANALOG_LDO_1_LDO_ANT_REF_SEL(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_LDO_1_LDO_ANT_REF_SEL_SHIFT)) & XCVR_ANALOG_LDO_1_LDO_ANT_REF_SEL_MASK)
/*! @} */

/*! @name XO_DIST - RF Analog XO DIST Control */
/*! @{ */

#define XCVR_ANALOG_XO_DIST_XO_DIST_TRIM_MASK    (0x3U)
#define XCVR_ANALOG_XO_DIST_XO_DIST_TRIM_SHIFT   (0U)
/*! XO_DIST_TRIM - reg_xo_dist_trim_dig[1:0]
 *  0b00..0.9 V ( Default )
 *  0b01..0.86 V
 *  0b10..0.95 V
 *  0b11..1.21 V
 */
#define XCVR_ANALOG_XO_DIST_XO_DIST_TRIM(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_XO_DIST_XO_DIST_TRIM_SHIFT)) & XCVR_ANALOG_XO_DIST_XO_DIST_TRIM_MASK)

#define XCVR_ANALOG_XO_DIST_XO_DIST_FLIP_MASK    (0x4U)
#define XCVR_ANALOG_XO_DIST_XO_DIST_FLIP_SHIFT   (2U)
/*! XO_DIST_FLIP - reg_xo_dist_flip_dig
 *  0b0..XO DIST doesn't flip the output clock relative to input clock
 *  0b1..XO DIST flip the output clock relative to input clock
 */
#define XCVR_ANALOG_XO_DIST_XO_DIST_FLIP(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_XO_DIST_XO_DIST_FLIP_SHIFT)) & XCVR_ANALOG_XO_DIST_XO_DIST_FLIP_MASK)

#define XCVR_ANALOG_XO_DIST_XO_DIST_BYPASS_MASK  (0x8U)
#define XCVR_ANALOG_XO_DIST_XO_DIST_BYPASS_SHIFT (3U)
/*! XO_DIST_BYPASS - reg_xo_dist_bypass
 *  0b0..XO DIST not bypass
 *  0b1..XO DIST bypass
 */
#define XCVR_ANALOG_XO_DIST_XO_DIST_BYPASS(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_XO_DIST_XO_DIST_BYPASS_SHIFT)) & XCVR_ANALOG_XO_DIST_XO_DIST_BYPASS_MASK)
/*! @} */

/*! @name PLL - RF Analog PLL Control */
/*! @{ */

#define XCVR_ANALOG_PLL_PLL_VCO_TRIM_KVT_MASK    (0x70U)
#define XCVR_ANALOG_PLL_PLL_VCO_TRIM_KVT_SHIFT   (4U)
/*! PLL_VCO_TRIM_KVT - reg_vco_trim_kvt_dig[2:0]
 *  0b000..50MHz/V
 *  0b100..60MHz/V for fref = 32M
 *  0b110..70MHz/V
 *  0b111..80MHz/V for fref = 26M
 */
#define XCVR_ANALOG_PLL_PLL_VCO_TRIM_KVT(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_PLL_PLL_VCO_TRIM_KVT_SHIFT)) & XCVR_ANALOG_PLL_PLL_VCO_TRIM_KVT_MASK)

#define XCVR_ANALOG_PLL_PLL_VCO_EN_PKDET_MASK    (0x100U)
#define XCVR_ANALOG_PLL_PLL_VCO_EN_PKDET_SHIFT   (8U)
/*! PLL_VCO_EN_PKDET - reg_vco_en_pkdet_dig
 *  0b0..PKDET disable
 *  0b1..PKDET enable
 */
#define XCVR_ANALOG_PLL_PLL_VCO_EN_PKDET(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_PLL_PLL_VCO_EN_PKDET_SHIFT)) & XCVR_ANALOG_PLL_PLL_VCO_EN_PKDET_MASK)

#define XCVR_ANALOG_PLL_PLL_PD_EN_VPD_PULLDN_MASK (0x400000U)
#define XCVR_ANALOG_PLL_PLL_PD_EN_VPD_PULLDN_SHIFT (22U)
/*! PLL_PD_EN_VPD_PULLDN - reg_pd_en_vpd_pulldn_dig
 *  0b0..not pull down vpd output
 *  0b1..pull down vpd output
 */
#define XCVR_ANALOG_PLL_PLL_PD_EN_VPD_PULLDN(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_PLL_PLL_PD_EN_VPD_PULLDN_SHIFT)) & XCVR_ANALOG_PLL_PLL_PD_EN_VPD_PULLDN_MASK)

#define XCVR_ANALOG_PLL_PLL_PD_EN_VPD_PULLUP_MASK (0x800000U)
#define XCVR_ANALOG_PLL_PLL_PD_EN_VPD_PULLUP_SHIFT (23U)
/*! PLL_PD_EN_VPD_PULLUP - reg_pd_en_vpd_pullup_dig
 *  0b0..not pull up vpd output
 *  0b1..pull up vpd output
 */
#define XCVR_ANALOG_PLL_PLL_PD_EN_VPD_PULLUP(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_PLL_PLL_PD_EN_VPD_PULLUP_SHIFT)) & XCVR_ANALOG_PLL_PLL_PD_EN_VPD_PULLUP_MASK)

#define XCVR_ANALOG_PLL_PLL_PD_TRIM_FCAL_BIAS_MASK (0xC000000U)
#define XCVR_ANALOG_PLL_PLL_PD_TRIM_FCAL_BIAS_SHIFT (26U)
/*! PLL_PD_TRIM_FCAL_BIAS - reg_pd_trim_fcal_bias_dig[1:0]
 *  0b00..0.276V
 *  0b01..0.164V
 *  0b10..0.320V
 *  0b11..0.391V
 */
#define XCVR_ANALOG_PLL_PLL_PD_TRIM_FCAL_BIAS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_PLL_PLL_PD_TRIM_FCAL_BIAS_SHIFT)) & XCVR_ANALOG_PLL_PLL_PD_TRIM_FCAL_BIAS_MASK)

#define XCVR_ANALOG_PLL_PLL_FCAL_EN_STATIC_RES_MASK (0x80000000U)
#define XCVR_ANALOG_PLL_PLL_FCAL_EN_STATIC_RES_SHIFT (31U)
/*! PLL_FCAL_EN_STATIC_RES - reg_fcal_en_static_res_dig
 *  0b0..resistor is dynamically switched during FCAL operation
 *  0b1..resistor is always on during FCAL operation
 */
#define XCVR_ANALOG_PLL_PLL_FCAL_EN_STATIC_RES(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_PLL_PLL_FCAL_EN_STATIC_RES_SHIFT)) & XCVR_ANALOG_PLL_PLL_FCAL_EN_STATIC_RES_MASK)
/*! @} */

/*! @name RX_0 - RF Analog RX Control0 */
/*! @{ */

#define XCVR_ANALOG_RX_0_RX_LNA_ITRIM_MASK       (0x3U)
#define XCVR_ANALOG_RX_0_RX_LNA_ITRIM_SHIFT      (0U)
/*! RX_LNA_ITRIM - reg_rx_lna_itrim_dig[1:0]
 *  0b00..3.7u -25%
 *  0b01..4.4u -15%
 *  0b10..5.1u Default
 *  0b11..5.6u +10%
 */
#define XCVR_ANALOG_RX_0_RX_LNA_ITRIM(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_0_RX_LNA_ITRIM_SHIFT)) & XCVR_ANALOG_RX_0_RX_LNA_ITRIM_MASK)

#define XCVR_ANALOG_RX_0_RX_LNA_PTAT_FORCE_START_MASK (0x1000U)
#define XCVR_ANALOG_RX_0_RX_LNA_PTAT_FORCE_START_SHIFT (12U)
/*! RX_LNA_PTAT_FORCE_START - reg_rtfe_ptat_force_dig
 */
#define XCVR_ANALOG_RX_0_RX_LNA_PTAT_FORCE_START(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_0_RX_LNA_PTAT_FORCE_START_SHIFT)) & XCVR_ANALOG_RX_0_RX_LNA_PTAT_FORCE_START_MASK)

#define XCVR_ANALOG_RX_0_RX_MIX_VBIAS_MASK       (0x300000U)
#define XCVR_ANALOG_RX_0_RX_MIX_VBIAS_SHIFT      (20U)
/*! RX_MIX_VBIAS - reg_rx_mix_vbias_dig[1:0]
 *  0b00..0.800V
 *  0b01..0.742V
 *  0b10..0.689V
 *  0b11..0.857V
 */
#define XCVR_ANALOG_RX_0_RX_MIX_VBIAS(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_0_RX_MIX_VBIAS_SHIFT)) & XCVR_ANALOG_RX_0_RX_MIX_VBIAS_MASK)

#define XCVR_ANALOG_RX_0_ADC_TRIM_MASK           (0x3000000U)
#define XCVR_ANALOG_RX_0_ADC_TRIM_SHIFT          (24U)
/*! ADC_TRIM - reg_adc_trim_dig[1:0]
 *  0b00..0.965V
 *  0b01..0.935V
 *  0b10..0.905V
 *  0b11..0.875V
 */
#define XCVR_ANALOG_RX_0_ADC_TRIM(x)             (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_0_ADC_TRIM_SHIFT)) & XCVR_ANALOG_RX_0_ADC_TRIM_MASK)

#define XCVR_ANALOG_RX_0_ADC_INVERT_CLK_MASK     (0x8000000U)
#define XCVR_ANALOG_RX_0_ADC_INVERT_CLK_SHIFT    (27U)
/*! ADC_INVERT_CLK - reg_adc_invert_clk_dig
 *  0b0..not invert clk
 *  0b1..invert clk
 */
#define XCVR_ANALOG_RX_0_ADC_INVERT_CLK(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_0_ADC_INVERT_CLK_SHIFT)) & XCVR_ANALOG_RX_0_ADC_INVERT_CLK_MASK)
/*! @} */

/*! @name RX_1 - RF Analog RX Control1 */
/*! @{ */

#define XCVR_ANALOG_RX_1_CBPF_TYPE_MASK          (0x8U)
#define XCVR_ANALOG_RX_1_CBPF_TYPE_SHIFT         (3U)
/*! CBPF_TYPE - reg_cbpf_type_dig
 *  0b0..Real
 *  0b1..Complex,
 */
#define XCVR_ANALOG_RX_1_CBPF_TYPE(x)            (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_1_CBPF_TYPE_SHIFT)) & XCVR_ANALOG_RX_1_CBPF_TYPE_MASK)

#define XCVR_ANALOG_RX_1_CBPF_TRIM_I_MASK        (0x30U)
#define XCVR_ANALOG_RX_1_CBPF_TRIM_I_SHIFT       (4U)
/*! CBPF_TRIM_I - reg_cbpf_trim_i_dig[1:0]
 *  0b00..5u (Default)
 *  0b01..6.25u
 *  0b10..7.5u
 *  0b11..8.75u
 */
#define XCVR_ANALOG_RX_1_CBPF_TRIM_I(x)          (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_1_CBPF_TRIM_I_SHIFT)) & XCVR_ANALOG_RX_1_CBPF_TRIM_I_MASK)

#define XCVR_ANALOG_RX_1_CBPF_TRIM_Q_MASK        (0x300U)
#define XCVR_ANALOG_RX_1_CBPF_TRIM_Q_SHIFT       (8U)
/*! CBPF_TRIM_Q - reg_cbpf_trim_q_dig[1:0]
 *  0b00..5u (Default)
 *  0b01..6.25u
 *  0b10..7.5u
 *  0b11..8.75u
 */
#define XCVR_ANALOG_RX_1_CBPF_TRIM_Q(x)          (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_1_CBPF_TRIM_Q_SHIFT)) & XCVR_ANALOG_RX_1_CBPF_TRIM_Q_MASK)

#define XCVR_ANALOG_RX_1_CBPF_VCM_TRIM_MASK      (0x3000U)
#define XCVR_ANALOG_RX_1_CBPF_VCM_TRIM_SHIFT     (12U)
/*! CBPF_VCM_TRIM - reg_cbpf_vcm_trim_dig[1:0]
 *  0b00..480mV
 *  0b01..453mV
 *  0b10..426mV
 *  0b11..401mV
 */
#define XCVR_ANALOG_RX_1_CBPF_VCM_TRIM(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_1_CBPF_VCM_TRIM_SHIFT)) & XCVR_ANALOG_RX_1_CBPF_VCM_TRIM_MASK)

#define XCVR_ANALOG_RX_1_CBPF_TRIM_SHORT_DCBIAS_MASK (0x30000U)
#define XCVR_ANALOG_RX_1_CBPF_TRIM_SHORT_DCBIAS_SHIFT (16U)
/*! CBPF_TRIM_SHORT_DCBIAS - reg_cbpf_trim_short_dcbias_dig[1:0]
 *  0b00..470mV
 *  0b01..438mV
 *  0b10..413mV
 *  0b11..385mV
 */
#define XCVR_ANALOG_RX_1_CBPF_TRIM_SHORT_DCBIAS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_1_CBPF_TRIM_SHORT_DCBIAS_SHIFT)) & XCVR_ANALOG_RX_1_CBPF_TRIM_SHORT_DCBIAS_MASK)
/*! @} */

/*! @name TX_DAC_PA - RF Analog TX DAC PA Control */
/*! @{ */

#define XCVR_ANALOG_TX_DAC_PA_DAC_INVERT_CLK_MASK (0x8U)
#define XCVR_ANALOG_TX_DAC_PA_DAC_INVERT_CLK_SHIFT (3U)
/*! DAC_INVERT_CLK - reg_dac_invert_clk_dig
 */
#define XCVR_ANALOG_TX_DAC_PA_DAC_INVERT_CLK(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_DAC_INVERT_CLK_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_DAC_INVERT_CLK_MASK)

#define XCVR_ANALOG_TX_DAC_PA_DAC_TRIM_RLOAD_MASK (0x300U)
#define XCVR_ANALOG_TX_DAC_PA_DAC_TRIM_RLOAD_SHIFT (8U)
/*! DAC_TRIM_RLOAD - reg_dac_trim_rload_dig[1:0]
 *  0b00..3K
 *  0b01..2.25K
 *  0b10..3.75K
 *  0b11..4.5K
 */
#define XCVR_ANALOG_TX_DAC_PA_DAC_TRIM_RLOAD(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_DAC_TRIM_RLOAD_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_DAC_TRIM_RLOAD_MASK)

#define XCVR_ANALOG_TX_DAC_PA_DAC_TRIM_IBIAS_MASK (0xC00U)
#define XCVR_ANALOG_TX_DAC_PA_DAC_TRIM_IBIAS_SHIFT (10U)
/*! DAC_TRIM_IBIAS - reg_dac_trim_ibias_dig[1:0]
 *  0b00..3.0uA (I_lsb=250nA)
 *  0b01..2.5uA
 *  0b10..3.8uA
 *  0b11..5.0uA
 */
#define XCVR_ANALOG_TX_DAC_PA_DAC_TRIM_IBIAS(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_DAC_TRIM_IBIAS_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_DAC_TRIM_IBIAS_MASK)

#define XCVR_ANALOG_TX_DAC_PA_TX_PA_VBIAS_MASK   (0x30000U)
#define XCVR_ANALOG_TX_DAC_PA_TX_PA_VBIAS_SHIFT  (16U)
/*! TX_PA_VBIAS - reg_tx_pa_vbias_dig[1:0]
 *  0b00..0.460V
 *  0b01..0.431V
 *  0b10..0.403V
 *  0b11..0.375V
 */
#define XCVR_ANALOG_TX_DAC_PA_TX_PA_VBIAS(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_TX_PA_VBIAS_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_TX_PA_VBIAS_MASK)

#define XCVR_ANALOG_TX_DAC_PA_DAC_TRIM_CFBK_MASK (0x3000000U)
#define XCVR_ANALOG_TX_DAC_PA_DAC_TRIM_CFBK_SHIFT (24U)
/*! DAC_TRIM_CFBK - reg_dac_trim_cfbk_dig[1:0]
 *  0b00..675fF
 *  0b01..1.35pF
 *  0b10..1.35pF
 *  0b11..2.025pF
 */
#define XCVR_ANALOG_TX_DAC_PA_DAC_TRIM_CFBK(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_DAC_TRIM_CFBK_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_DAC_TRIM_CFBK_MASK)

#define XCVR_ANALOG_TX_DAC_PA_DAC_TRIM_CFBK_DRS_MASK (0xC000000U)
#define XCVR_ANALOG_TX_DAC_PA_DAC_TRIM_CFBK_DRS_SHIFT (26U)
/*! DAC_TRIM_CFBK_DRS - reg_dac_trim_cfbk_dig[1:0]
 *  0b00..675fF
 *  0b01..1.35pF
 *  0b10..1.35pF
 *  0b11..2.025pF
 */
#define XCVR_ANALOG_TX_DAC_PA_DAC_TRIM_CFBK_DRS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_DAC_TRIM_CFBK_DRS_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_DAC_TRIM_CFBK_DRS_MASK)
/*! @} */

/*! @name DIAG - RF Analog DIAG Control 1 */
/*! @{ */

#define XCVR_ANALOG_DIAG_DIAG_CODE_MASK          (0x7U)
#define XCVR_ANALOG_DIAG_DIAG_CODE_SHIFT         (0U)
/*! DIAG_CODE - reg_diag_code_dig[2:0]
 */
#define XCVR_ANALOG_DIAG_DIAG_CODE(x)            (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DIAG_DIAG_CODE_SHIFT)) & XCVR_ANALOG_DIAG_DIAG_CODE_MASK)

#define XCVR_ANALOG_DIAG_LDO_CAL_DIAG_SEL_MASK   (0x8U)
#define XCVR_ANALOG_DIAG_LDO_CAL_DIAG_SEL_SHIFT  (3U)
/*! LDO_CAL_DIAG_SEL - reg_ldo_cal_diag_sel_dig
 */
#define XCVR_ANALOG_DIAG_LDO_CAL_DIAG_SEL(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DIAG_LDO_CAL_DIAG_SEL_SHIFT)) & XCVR_ANALOG_DIAG_LDO_CAL_DIAG_SEL_MASK)

#define XCVR_ANALOG_DIAG_LDO_VCO_DIAG_SEL_MASK   (0x10U)
#define XCVR_ANALOG_DIAG_LDO_VCO_DIAG_SEL_SHIFT  (4U)
/*! LDO_VCO_DIAG_SEL - reg_ldo_vco_diag_sel_dig
 */
#define XCVR_ANALOG_DIAG_LDO_VCO_DIAG_SEL(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DIAG_LDO_VCO_DIAG_SEL_SHIFT)) & XCVR_ANALOG_DIAG_LDO_VCO_DIAG_SEL_MASK)

#define XCVR_ANALOG_DIAG_LDO_PLL_DIAG_SEL_MASK   (0x20U)
#define XCVR_ANALOG_DIAG_LDO_PLL_DIAG_SEL_SHIFT  (5U)
/*! LDO_PLL_DIAG_SEL - reg_ldo_pll_diag_sel_dig
 */
#define XCVR_ANALOG_DIAG_LDO_PLL_DIAG_SEL(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DIAG_LDO_PLL_DIAG_SEL_SHIFT)) & XCVR_ANALOG_DIAG_LDO_PLL_DIAG_SEL_MASK)

#define XCVR_ANALOG_DIAG_LDO_RXTXLF_DIAG_SEL_MASK (0x100U)
#define XCVR_ANALOG_DIAG_LDO_RXTXLF_DIAG_SEL_SHIFT (8U)
/*! LDO_RXTXLF_DIAG_SEL - reg_ldo_rxtxlf_diag_sel_dig
 */
#define XCVR_ANALOG_DIAG_LDO_RXTXLF_DIAG_SEL(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DIAG_LDO_RXTXLF_DIAG_SEL_SHIFT)) & XCVR_ANALOG_DIAG_LDO_RXTXLF_DIAG_SEL_MASK)

#define XCVR_ANALOG_DIAG_LDO_RXTXHF_DIAG_SEL_MASK (0x200U)
#define XCVR_ANALOG_DIAG_LDO_RXTXHF_DIAG_SEL_SHIFT (9U)
/*! LDO_RXTXHF_DIAG_SEL - reg_ldo_rxtxhf_diag_sel_dig
 */
#define XCVR_ANALOG_DIAG_LDO_RXTXHF_DIAG_SEL(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DIAG_LDO_RXTXHF_DIAG_SEL_SHIFT)) & XCVR_ANALOG_DIAG_LDO_RXTXHF_DIAG_SEL_MASK)

#define XCVR_ANALOG_DIAG_LDO_LV_DIAG_SEL_MASK    (0x400U)
#define XCVR_ANALOG_DIAG_LDO_LV_DIAG_SEL_SHIFT   (10U)
/*! LDO_LV_DIAG_SEL - reg_ldo_lv_diag_sel_dig
 */
#define XCVR_ANALOG_DIAG_LDO_LV_DIAG_SEL(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DIAG_LDO_LV_DIAG_SEL_SHIFT)) & XCVR_ANALOG_DIAG_LDO_LV_DIAG_SEL_MASK)

#define XCVR_ANALOG_DIAG_BG_DIAG_SEL_MASK        (0x800U)
#define XCVR_ANALOG_DIAG_BG_DIAG_SEL_SHIFT       (11U)
/*! BG_DIAG_SEL - reg_bg_diag_sel_dig
 */
#define XCVR_ANALOG_DIAG_BG_DIAG_SEL(x)          (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DIAG_BG_DIAG_SEL_SHIFT)) & XCVR_ANALOG_DIAG_BG_DIAG_SEL_MASK)

#define XCVR_ANALOG_DIAG_LDOTRIM_DIAG_SEL_MASK   (0x1000U)
#define XCVR_ANALOG_DIAG_LDOTRIM_DIAG_SEL_SHIFT  (12U)
/*! LDOTRIM_DIAG_SEL - reg_ldotrim_diag_sel_dig
 */
#define XCVR_ANALOG_DIAG_LDOTRIM_DIAG_SEL(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DIAG_LDOTRIM_DIAG_SEL_SHIFT)) & XCVR_ANALOG_DIAG_LDOTRIM_DIAG_SEL_MASK)

#define XCVR_ANALOG_DIAG_PROC_MON_DIAG_SEL_MASK  (0x2000U)
#define XCVR_ANALOG_DIAG_PROC_MON_DIAG_SEL_SHIFT (13U)
/*! PROC_MON_DIAG_SEL - reg_proc_mon_diag_sel_dig
 */
#define XCVR_ANALOG_DIAG_PROC_MON_DIAG_SEL(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DIAG_PROC_MON_DIAG_SEL_SHIFT)) & XCVR_ANALOG_DIAG_PROC_MON_DIAG_SEL_MASK)

#define XCVR_ANALOG_DIAG_RTFE_DIAG_SEL_MASK      (0x8000U)
#define XCVR_ANALOG_DIAG_RTFE_DIAG_SEL_SHIFT     (15U)
/*! RTFE_DIAG_SEL - reg_rtfe_diag_sel_dig
 */
#define XCVR_ANALOG_DIAG_RTFE_DIAG_SEL(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DIAG_RTFE_DIAG_SEL_SHIFT)) & XCVR_ANALOG_DIAG_RTFE_DIAG_SEL_MASK)

#define XCVR_ANALOG_DIAG_CBPF_I_DIAG_SEL_1_MASK  (0x10000U)
#define XCVR_ANALOG_DIAG_CBPF_I_DIAG_SEL_1_SHIFT (16U)
/*! CBPF_I_DIAG_SEL_1 - reg_cbpf_i_diag_sel_1_dig
 */
#define XCVR_ANALOG_DIAG_CBPF_I_DIAG_SEL_1(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DIAG_CBPF_I_DIAG_SEL_1_SHIFT)) & XCVR_ANALOG_DIAG_CBPF_I_DIAG_SEL_1_MASK)

#define XCVR_ANALOG_DIAG_CBPF_I_DIAG_SEL_2_MASK  (0x20000U)
#define XCVR_ANALOG_DIAG_CBPF_I_DIAG_SEL_2_SHIFT (17U)
/*! CBPF_I_DIAG_SEL_2 - reg_cbpf_i_diag_sel_2_dig
 */
#define XCVR_ANALOG_DIAG_CBPF_I_DIAG_SEL_2(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DIAG_CBPF_I_DIAG_SEL_2_SHIFT)) & XCVR_ANALOG_DIAG_CBPF_I_DIAG_SEL_2_MASK)

#define XCVR_ANALOG_DIAG_CBPF_Q_DIAG_SEL_1_MASK  (0x40000U)
#define XCVR_ANALOG_DIAG_CBPF_Q_DIAG_SEL_1_SHIFT (18U)
/*! CBPF_Q_DIAG_SEL_1 - reg_cbpf_q_diag_sel_1_dig
 */
#define XCVR_ANALOG_DIAG_CBPF_Q_DIAG_SEL_1(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DIAG_CBPF_Q_DIAG_SEL_1_SHIFT)) & XCVR_ANALOG_DIAG_CBPF_Q_DIAG_SEL_1_MASK)

#define XCVR_ANALOG_DIAG_CBPF_Q_DIAG_SEL_2_MASK  (0x80000U)
#define XCVR_ANALOG_DIAG_CBPF_Q_DIAG_SEL_2_SHIFT (19U)
/*! CBPF_Q_DIAG_SEL_2 - reg_cbpf_q_diag_sel_2_dig
 */
#define XCVR_ANALOG_DIAG_CBPF_Q_DIAG_SEL_2(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DIAG_CBPF_Q_DIAG_SEL_2_SHIFT)) & XCVR_ANALOG_DIAG_CBPF_Q_DIAG_SEL_2_MASK)

#define XCVR_ANALOG_DIAG_CBPF_EN_DIAG_MEAS_MASK  (0x100000U)
#define XCVR_ANALOG_DIAG_CBPF_EN_DIAG_MEAS_SHIFT (20U)
/*! CBPF_EN_DIAG_MEAS - reg_cbpf_en_diag_meas_dig
 */
#define XCVR_ANALOG_DIAG_CBPF_EN_DIAG_MEAS(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DIAG_CBPF_EN_DIAG_MEAS_SHIFT)) & XCVR_ANALOG_DIAG_CBPF_EN_DIAG_MEAS_MASK)

#define XCVR_ANALOG_DIAG_ADC_DIAG_SEL_MASK       (0x200000U)
#define XCVR_ANALOG_DIAG_ADC_DIAG_SEL_SHIFT      (21U)
/*! ADC_DIAG_SEL - reg_adc_diag_sel_dig
 */
#define XCVR_ANALOG_DIAG_ADC_DIAG_SEL(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DIAG_ADC_DIAG_SEL_SHIFT)) & XCVR_ANALOG_DIAG_ADC_DIAG_SEL_MASK)

#define XCVR_ANALOG_DIAG_PD_DIAG_SEL_MASK        (0x800000U)
#define XCVR_ANALOG_DIAG_PD_DIAG_SEL_SHIFT       (23U)
/*! PD_DIAG_SEL - reg_pd_diag_sel_dig
 */
#define XCVR_ANALOG_DIAG_PD_DIAG_SEL(x)          (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DIAG_PD_DIAG_SEL_SHIFT)) & XCVR_ANALOG_DIAG_PD_DIAG_SEL_MASK)

#define XCVR_ANALOG_DIAG_VCO_DIAG_SEL_MASK       (0x1000000U)
#define XCVR_ANALOG_DIAG_VCO_DIAG_SEL_SHIFT      (24U)
/*! VCO_DIAG_SEL - reg_vco_diag_sel_dig
 */
#define XCVR_ANALOG_DIAG_VCO_DIAG_SEL(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DIAG_VCO_DIAG_SEL_SHIFT)) & XCVR_ANALOG_DIAG_VCO_DIAG_SEL_MASK)

#define XCVR_ANALOG_DIAG_DAC_DIAG_SEL_MASK       (0x2000000U)
#define XCVR_ANALOG_DIAG_DAC_DIAG_SEL_SHIFT      (25U)
/*! DAC_DIAG_SEL - reg_dac_diag_sel_dig
 */
#define XCVR_ANALOG_DIAG_DAC_DIAG_SEL(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DIAG_DAC_DIAG_SEL_SHIFT)) & XCVR_ANALOG_DIAG_DAC_DIAG_SEL_MASK)

#define XCVR_ANALOG_DIAG_XO_DIST_DIAG_SEL_MASK   (0x8000000U)
#define XCVR_ANALOG_DIAG_XO_DIST_DIAG_SEL_SHIFT  (27U)
/*! XO_DIST_DIAG_SEL - reg_xo_dist_diag_sel_dig
 */
#define XCVR_ANALOG_DIAG_XO_DIST_DIAG_SEL(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DIAG_XO_DIST_DIAG_SEL_SHIFT)) & XCVR_ANALOG_DIAG_XO_DIST_DIAG_SEL_MASK)

#define XCVR_ANALOG_DIAG_LDO_ANT_DIAG_SEL_MASK   (0x10000000U)
#define XCVR_ANALOG_DIAG_LDO_ANT_DIAG_SEL_SHIFT  (28U)
/*! LDO_ANT_DIAG_SEL - reg_ldo_ant_diag_sel_dig
 */
#define XCVR_ANALOG_DIAG_LDO_ANT_DIAG_SEL(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DIAG_LDO_ANT_DIAG_SEL_SHIFT)) & XCVR_ANALOG_DIAG_LDO_ANT_DIAG_SEL_MASK)

#define XCVR_ANALOG_DIAG_DAC_AMP_DIAG_SEL_MASK   (0x20000000U)
#define XCVR_ANALOG_DIAG_DAC_AMP_DIAG_SEL_SHIFT  (29U)
/*! DAC_AMP_DIAG_SEL - reg_dac_amp_diag_sel_dig
 */
#define XCVR_ANALOG_DIAG_DAC_AMP_DIAG_SEL(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DIAG_DAC_AMP_DIAG_SEL_SHIFT)) & XCVR_ANALOG_DIAG_DAC_AMP_DIAG_SEL_MASK)

#define XCVR_ANALOG_DIAG_DIAG_DIS_MASK           (0x40000000U)
#define XCVR_ANALOG_DIAG_DIAG_DIS_SHIFT          (30U)
/*! DIAG_DIS - reg_diag_dis_dig
 */
#define XCVR_ANALOG_DIAG_DIAG_DIS(x)             (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DIAG_DIAG_DIS_SHIFT)) & XCVR_ANALOG_DIAG_DIAG_DIS_MASK)

#define XCVR_ANALOG_DIAG_ATX_ON_2P4GHZ_MASK      (0x80000000U)
#define XCVR_ANALOG_DIAG_ATX_ON_2P4GHZ_SHIFT     (31U)
/*! ATX_ON_2P4GHZ - reg_2p4ghz_atx_on_dig
 */
#define XCVR_ANALOG_DIAG_ATX_ON_2P4GHZ(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DIAG_ATX_ON_2P4GHZ_SHIFT)) & XCVR_ANALOG_DIAG_ATX_ON_2P4GHZ_MASK)
/*! @} */

/*! @name SPARE - RF Analog SPARE Control */
/*! @{ */

#define XCVR_ANALOG_SPARE_SPARELV_MASK           (0x7FU)
#define XCVR_ANALOG_SPARE_SPARELV_SHIFT          (0U)
/*! SPARELV - reg_sparelv_dig[1:0]
 */
#define XCVR_ANALOG_SPARE_SPARELV(x)             (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SPARE_SPARELV_SHIFT)) & XCVR_ANALOG_SPARE_SPARELV_MASK)

#define XCVR_ANALOG_SPARE_SPARE_DIAG_SEL_MASK    (0x3000U)
#define XCVR_ANALOG_SPARE_SPARE_DIAG_SEL_SHIFT   (12U)
/*! SPARE_DIAG_SEL - reg_spare_diag_sel_dig[1:0]
 */
#define XCVR_ANALOG_SPARE_SPARE_DIAG_SEL(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SPARE_SPARE_DIAG_SEL_SHIFT)) & XCVR_ANALOG_SPARE_SPARE_DIAG_SEL_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group XCVR_ANALOG_Register_Masks */


/* XCVR_ANALOG - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral XCVR_ANALOG base address */
  #define XCVR_ANALOG_BASE                         (0x58A07C00u)
  /** Peripheral XCVR_ANALOG base address */
  #define XCVR_ANALOG_BASE_NS                      (0x48A07C00u)
  /** Peripheral XCVR_ANALOG base pointer */
  #define XCVR_ANALOG                              ((XCVR_ANALOG_Type *)XCVR_ANALOG_BASE)
  /** Peripheral XCVR_ANALOG base pointer */
  #define XCVR_ANALOG_NS                           ((XCVR_ANALOG_Type *)XCVR_ANALOG_BASE_NS)
  /** Array initializer of XCVR_ANALOG peripheral base addresses */
  #define XCVR_ANALOG_BASE_ADDRS                   { XCVR_ANALOG_BASE }
  /** Array initializer of XCVR_ANALOG peripheral base pointers */
  #define XCVR_ANALOG_BASE_PTRS                    { XCVR_ANALOG }
  /** Array initializer of XCVR_ANALOG peripheral base addresses */
  #define XCVR_ANALOG_BASE_ADDRS_NS                { XCVR_ANALOG_BASE_NS }
  /** Array initializer of XCVR_ANALOG peripheral base pointers */
  #define XCVR_ANALOG_BASE_PTRS_NS                 { XCVR_ANALOG_NS }
#else
  /** Peripheral XCVR_ANALOG base address */
  #define XCVR_ANALOG_BASE                         (0x48A07C00u)
  /** Peripheral XCVR_ANALOG base pointer */
  #define XCVR_ANALOG                              ((XCVR_ANALOG_Type *)XCVR_ANALOG_BASE)
  /** Array initializer of XCVR_ANALOG peripheral base addresses */
  #define XCVR_ANALOG_BASE_ADDRS                   { XCVR_ANALOG_BASE }
  /** Array initializer of XCVR_ANALOG peripheral base pointers */
  #define XCVR_ANALOG_BASE_PTRS                    { XCVR_ANALOG }
#endif

/*!
 * @}
 */ /* end of group XCVR_ANALOG_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- XCVR_MISC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup XCVR_MISC_Peripheral_Access_Layer XCVR_MISC Peripheral Access Layer
 * @{
 */

/** XCVR_MISC - Register Layout Typedef */
typedef struct {
  __IO uint32_t XCVR_CTRL;                         /**< TRANSCEIVER CONTROL, offset: 0x0 */
  __IO uint32_t XCVR_STATUS;                       /**< TRANSCEIVER STATUS, offset: 0x4 */
  __IO uint32_t FAD_CTRL;                          /**< FAD CONTROL, offset: 0x8 */
  __IO uint32_t DMA_CTRL;                          /**< TRANSCEIVER DMA CONTROL, offset: 0xC */
  __IO uint32_t DBG_RAM_CTRL;                      /**< DBG Ram control register, offset: 0x10 */
  __IO uint32_t DBG_RAM_ADDR;                      /**< DBG RAM ADDRESS, offset: 0x14 */
  __I  uint32_t DBG_RAM_STOP_ADDR;                 /**< DBG RAM STOP ADDRESS, offset: 0x18 */
  __IO uint32_t LDO_TRIM_0;                        /**< LDO TRIM Configuration 0, offset: 0x1C */
  __IO uint32_t LDO_TRIM_1;                        /**< LDO TRIM Configuration 1, offset: 0x20 */
  __I  uint32_t LDO_TRIM_RES_0;                    /**< RF Analog LDO Trim Res Control 0, offset: 0x24 */
  __I  uint32_t LDO_TRIM_RES_1;                    /**< RF Analog LDO Trim Res Control 1, offset: 0x28 */
  __IO uint32_t LCL_CFG0;                          /**< LCL CTRL CFG 0, offset: 0x2C */
  __IO uint32_t LCL_CFG1;                          /**< LCL CTRL CFG 1, offset: 0x30 */
  __IO uint32_t LCL_TX_CFG0;                       /**< LCL CTRL TX CONFIG0, offset: 0x34 */
  __IO uint32_t LCL_TX_CFG1;                       /**< LCL CTRL TX CONFIG1, offset: 0x38 */
  __IO uint32_t LCL_TX_CFG2;                       /**< LCL CTRL TX CONFIG2, offset: 0x3C */
  __IO uint32_t LCL_RX_CFG0;                       /**< LCL CTRL RX CONFIG0, offset: 0x40 */
  __IO uint32_t LCL_RX_CFG1;                       /**< LCL CTRL RX CONFIG1, offset: 0x44 */
  __IO uint32_t LCL_RX_CFG2;                       /**< LCL CTRL RX CONFIG2, offset: 0x48 */
  __IO uint32_t LCL_PM_MSB;                        /**< LCL CTRL PM MSB, offset: 0x4C */
  __IO uint32_t LCL_PM_LSB;                        /**< LCL CTRL PM LSB, offset: 0x50 */
  __IO uint32_t LCL_GPIO_CTRL0;                    /**< LCL GPIO CTRL 0, offset: 0x54 */
  __IO uint32_t LCL_GPIO_CTRL1;                    /**< LCL GPIO CTRL 1, offset: 0x58 */
  __IO uint32_t LCL_GPIO_CTRL2;                    /**< LCL GPIO CTRL 2, offset: 0x5C */
  __IO uint32_t LCL_GPIO_CTRL3;                    /**< LCL GPIO CTRL 3, offset: 0x60 */
  __IO uint32_t LCL_GPIO_CTRL4;                    /**< LCL GPIO CTRL 4, offset: 0x64 */
  __IO uint32_t LCL_DMA_MASK_DELAY;                /**< LCL_DMA_MASK_DELAY, offset: 0x68 */
  __IO uint32_t LCL_DMA_MASK_PERIOD;               /**< LCL_DMA_MASK_PERIOD, offset: 0x6C */
  __IO uint32_t RSM_CSR;                           /**< Ranging Sequence Manager Control and Status, offset: 0x70 */
  __IO uint32_t RSM_CTRL0;                         /**< Ranging Sequence Manager Control, offset: 0x74 */
  __IO uint32_t RSM_CTRL1;                         /**< Ranging Sequence Manager Control, offset: 0x78 */
  __IO uint32_t RSM_CTRL2;                         /**< Ranging Sequence Manager Control, offset: 0x7C */
  __IO uint32_t RSM_CTRL3;                         /**< Ranging Sequence Manager Control, offset: 0x80 */
  __IO uint32_t RSM_CTRL4;                         /**< Ranging Sequence Manager Control, offset: 0x84 */
       uint8_t RESERVED_0[20];
  __IO uint32_t RF_DFT_CTRL;                       /**< RF DFT CTRL, offset: 0x9C */
  __IO uint32_t IPS_FO_ADDR[8];                    /**< IPS FAST OVERWRITE ADDRESS, array offset: 0xA0, array step: 0x4 */
  __IO uint32_t IPS_FO_DRS0_DATA[8];               /**< IPS FAST OVERWRITE DRS0 DATA, array offset: 0xC0, array step: 0x4 */
  __IO uint32_t IPS_FO_DRS1_DATA[8];               /**< IPS FAST OVERWRITE DRS1 DATA, array offset: 0xE0, array step: 0x4 */
} XCVR_MISC_Type;

/* ----------------------------------------------------------------------------
   -- XCVR_MISC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup XCVR_MISC_Register_Masks XCVR_MISC Register Masks
 * @{
 */

/*! @name XCVR_CTRL - TRANSCEIVER CONTROL */
/*! @{ */

#define XCVR_MISC_XCVR_CTRL_XCVR_SOFT_RESET_MASK (0x1U)
#define XCVR_MISC_XCVR_CTRL_XCVR_SOFT_RESET_SHIFT (0U)
/*! XCVR_SOFT_RESET - transciever soft reset control
 *  0b0..no soft reset
 *  0b1..enable soft reset on transciever
 */
#define XCVR_MISC_XCVR_CTRL_XCVR_SOFT_RESET(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_XCVR_CTRL_XCVR_SOFT_RESET_SHIFT)) & XCVR_MISC_XCVR_CTRL_XCVR_SOFT_RESET_MASK)

#define XCVR_MISC_XCVR_CTRL_LPPS_ENABLE_MASK     (0x2U)
#define XCVR_MISC_XCVR_CTRL_LPPS_ENABLE_SHIFT    (1U)
/*! LPPS_ENABLE - transciever lpps enable control
 *  0b0..no lpps feature
 *  0b1..enable lpps feature
 */
#define XCVR_MISC_XCVR_CTRL_LPPS_ENABLE(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_XCVR_CTRL_LPPS_ENABLE_SHIFT)) & XCVR_MISC_XCVR_CTRL_LPPS_ENABLE_MASK)

#define XCVR_MISC_XCVR_CTRL_SDCLK_OUT_EN_MASK    (0x8U)
#define XCVR_MISC_XCVR_CTRL_SDCLK_OUT_EN_SHIFT   (3U)
/*! SDCLK_OUT_EN - sdclk out control
 *  0b0..no sdclk out
 *  0b1..enable sdclk out
 */
#define XCVR_MISC_XCVR_CTRL_SDCLK_OUT_EN(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_XCVR_CTRL_SDCLK_OUT_EN_SHIFT)) & XCVR_MISC_XCVR_CTRL_SDCLK_OUT_EN_MASK)

#define XCVR_MISC_XCVR_CTRL_DEMOD_SEL_MASK       (0xC0U)
#define XCVR_MISC_XCVR_CTRL_DEMOD_SEL_SHIFT      (6U)
/*! DEMOD_SEL - Demodulator Selector
 *  0b00..No demodulator selected
 *  0b01..Use NXP Multi-standard PHY demodulator
 *  0b10..Use Legacy 802.15.4 demodulator
 *  0b11..Reserved
 */
#define XCVR_MISC_XCVR_CTRL_DEMOD_SEL(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_XCVR_CTRL_DEMOD_SEL_SHIFT)) & XCVR_MISC_XCVR_CTRL_DEMOD_SEL_MASK)

#define XCVR_MISC_XCVR_CTRL_DATA_RATE_MASK       (0x700U)
#define XCVR_MISC_XCVR_CTRL_DATA_RATE_SHIFT      (8U)
/*! DATA_RATE - Radio data rate setting
 *  0b000..2Mbps
 *  0b001..1Mbps
 *  0b010..500Kbps
 *  0b011..250Kbps
 *  0b1xx..Reserved
 */
#define XCVR_MISC_XCVR_CTRL_DATA_RATE(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_XCVR_CTRL_DATA_RATE_SHIFT)) & XCVR_MISC_XCVR_CTRL_DATA_RATE_MASK)

#define XCVR_MISC_XCVR_CTRL_DATA_RATE_DRS_MASK   (0x3800U)
#define XCVR_MISC_XCVR_CTRL_DATA_RATE_DRS_SHIFT  (11U)
/*! DATA_RATE_DRS - Radio data rate setting, Data Rate Switch
 *  0b000..2Mbps
 *  0b001..1Mbps
 *  0b010..500Kbps
 *  0b011..250Kbps
 *  0b1xx..Reserved
 */
#define XCVR_MISC_XCVR_CTRL_DATA_RATE_DRS(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_XCVR_CTRL_DATA_RATE_DRS_SHIFT)) & XCVR_MISC_XCVR_CTRL_DATA_RATE_DRS_MASK)

#define XCVR_MISC_XCVR_CTRL_REF_CLK_FREQ_MASK    (0x8000U)
#define XCVR_MISC_XCVR_CTRL_REF_CLK_FREQ_SHIFT   (15U)
/*! REF_CLK_FREQ - transciever ref clk freq control
 *  0b0..32MHz
 *  0b1..26MHz
 */
#define XCVR_MISC_XCVR_CTRL_REF_CLK_FREQ(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_XCVR_CTRL_REF_CLK_FREQ_SHIFT)) & XCVR_MISC_XCVR_CTRL_REF_CLK_FREQ_MASK)

#define XCVR_MISC_XCVR_CTRL_FO_RX_EN_MASK        (0x10000U)
#define XCVR_MISC_XCVR_CTRL_FO_RX_EN_SHIFT       (16U)
/*! FO_RX_EN - Fast Overwrite RX Enable
 */
#define XCVR_MISC_XCVR_CTRL_FO_RX_EN(x)          (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_XCVR_CTRL_FO_RX_EN_SHIFT)) & XCVR_MISC_XCVR_CTRL_FO_RX_EN_MASK)

#define XCVR_MISC_XCVR_CTRL_FO_TX_EN_MASK        (0x20000U)
#define XCVR_MISC_XCVR_CTRL_FO_TX_EN_SHIFT       (17U)
/*! FO_TX_EN - Fast Overwrite TX Enable
 */
#define XCVR_MISC_XCVR_CTRL_FO_TX_EN(x)          (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_XCVR_CTRL_FO_TX_EN_SHIFT)) & XCVR_MISC_XCVR_CTRL_FO_TX_EN_MASK)

#define XCVR_MISC_XCVR_CTRL_TOF_RX_SEL_MASK      (0x40000U)
#define XCVR_MISC_XCVR_CTRL_TOF_RX_SEL_SHIFT     (18U)
/*! TOF_RX_SEL - Time-of-Flight RX Select
 *  0b0..PHY: aa_fnd_to_ll
 *  0b1..Localization Control: pattern_found
 */
#define XCVR_MISC_XCVR_CTRL_TOF_RX_SEL(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_XCVR_CTRL_TOF_RX_SEL_SHIFT)) & XCVR_MISC_XCVR_CTRL_TOF_RX_SEL_MASK)

#define XCVR_MISC_XCVR_CTRL_TOF_TX_SEL_MASK      (0x80000U)
#define XCVR_MISC_XCVR_CTRL_TOF_TX_SEL_SHIFT     (19U)
/*! TOF_TX_SEL - Time-of-Flight TX Select
 *  0b0..TSM: tx_dig_en
 *  0b1..TXDIG: pa_wu_complete
 */
#define XCVR_MISC_XCVR_CTRL_TOF_TX_SEL(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_XCVR_CTRL_TOF_TX_SEL_SHIFT)) & XCVR_MISC_XCVR_CTRL_TOF_TX_SEL_MASK)

#define XCVR_MISC_XCVR_CTRL_LL_CFG_CAPT_DIS_MASK (0x100000U)
#define XCVR_MISC_XCVR_CTRL_LL_CFG_CAPT_DIS_SHIFT (20U)
/*! LL_CFG_CAPT_DIS - Link Layer Configuration Capture Disable
 *  0b0..Enabled: Link Layer configuration inputs are captured.
 *  0b1..Disabled: Link Layer configurations are not captured.
 */
#define XCVR_MISC_XCVR_CTRL_LL_CFG_CAPT_DIS(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_XCVR_CTRL_LL_CFG_CAPT_DIS_SHIFT)) & XCVR_MISC_XCVR_CTRL_LL_CFG_CAPT_DIS_MASK)
/*! @} */

/*! @name XCVR_STATUS - TRANSCEIVER STATUS */
/*! @{ */

#define XCVR_MISC_XCVR_STATUS_TSM_COUNT_MASK     (0xFFU)
#define XCVR_MISC_XCVR_STATUS_TSM_COUNT_SHIFT    (0U)
/*! TSM_COUNT - TSM_COUNT
 */
#define XCVR_MISC_XCVR_STATUS_TSM_COUNT(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_XCVR_STATUS_TSM_COUNT_SHIFT)) & XCVR_MISC_XCVR_STATUS_TSM_COUNT_MASK)

#define XCVR_MISC_XCVR_STATUS_TSM_IRQ0_MASK      (0x100U)
#define XCVR_MISC_XCVR_STATUS_TSM_IRQ0_SHIFT     (8U)
/*! TSM_IRQ0 - TSM Interrupt #0
 *  0b0..TSM Interrupt #0 is not asserted.
 *  0b1..TSM Interrupt #0 is asserted. Write '1' to this bit to clear it.
 */
#define XCVR_MISC_XCVR_STATUS_TSM_IRQ0(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_XCVR_STATUS_TSM_IRQ0_SHIFT)) & XCVR_MISC_XCVR_STATUS_TSM_IRQ0_MASK)

#define XCVR_MISC_XCVR_STATUS_TSM_IRQ1_MASK      (0x200U)
#define XCVR_MISC_XCVR_STATUS_TSM_IRQ1_SHIFT     (9U)
/*! TSM_IRQ1 - TSM Interrupt #1
 *  0b0..TSM Interrupt #1 is not asserted.
 *  0b1..TSM Interrupt #1 is asserted. Write '1' to this bit to clear it.
 */
#define XCVR_MISC_XCVR_STATUS_TSM_IRQ1(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_XCVR_STATUS_TSM_IRQ1_SHIFT)) & XCVR_MISC_XCVR_STATUS_TSM_IRQ1_MASK)

#define XCVR_MISC_XCVR_STATUS_TSM_BUSY_MASK      (0x2000U)
#define XCVR_MISC_XCVR_STATUS_TSM_BUSY_SHIFT     (13U)
/*! TSM_BUSY - tsm busy status
 */
#define XCVR_MISC_XCVR_STATUS_TSM_BUSY(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_XCVR_STATUS_TSM_BUSY_SHIFT)) & XCVR_MISC_XCVR_STATUS_TSM_BUSY_MASK)

#define XCVR_MISC_XCVR_STATUS_RX_MODE_MASK       (0x4000U)
#define XCVR_MISC_XCVR_STATUS_RX_MODE_SHIFT      (14U)
/*! RX_MODE - Receive Mode
 */
#define XCVR_MISC_XCVR_STATUS_RX_MODE(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_XCVR_STATUS_RX_MODE_SHIFT)) & XCVR_MISC_XCVR_STATUS_RX_MODE_MASK)

#define XCVR_MISC_XCVR_STATUS_TX_MODE_MASK       (0x8000U)
#define XCVR_MISC_XCVR_STATUS_TX_MODE_SHIFT      (15U)
/*! TX_MODE - Transmit Mode
 */
#define XCVR_MISC_XCVR_STATUS_TX_MODE(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_XCVR_STATUS_TX_MODE_SHIFT)) & XCVR_MISC_XCVR_STATUS_TX_MODE_MASK)
/*! @} */

/*! @name FAD_CTRL - FAD CONTROL */
/*! @{ */

#define XCVR_MISC_FAD_CTRL_ANTX_MASK             (0x2U)
#define XCVR_MISC_FAD_CTRL_ANTX_SHIFT            (1U)
/*! ANTX - Antenna Selection State
 */
#define XCVR_MISC_FAD_CTRL_ANTX(x)               (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_FAD_CTRL_ANTX_SHIFT)) & XCVR_MISC_FAD_CTRL_ANTX_MASK)

#define XCVR_MISC_FAD_CTRL_ANTX_OVRD_EN_MASK     (0x4U)
#define XCVR_MISC_FAD_CTRL_ANTX_OVRD_EN_SHIFT    (2U)
/*! ANTX_OVRD_EN - Antenna State Override Enable
 */
#define XCVR_MISC_FAD_CTRL_ANTX_OVRD_EN(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_FAD_CTRL_ANTX_OVRD_EN_SHIFT)) & XCVR_MISC_FAD_CTRL_ANTX_OVRD_EN_MASK)

#define XCVR_MISC_FAD_CTRL_ANTX_OVRD_MASK        (0x8U)
#define XCVR_MISC_FAD_CTRL_ANTX_OVRD_SHIFT       (3U)
/*! ANTX_OVRD - Antenna State Override Value
 */
#define XCVR_MISC_FAD_CTRL_ANTX_OVRD(x)          (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_FAD_CTRL_ANTX_OVRD_SHIFT)) & XCVR_MISC_FAD_CTRL_ANTX_OVRD_MASK)

#define XCVR_MISC_FAD_CTRL_ANTX_EN_MASK          (0x30U)
#define XCVR_MISC_FAD_CTRL_ANTX_EN_SHIFT         (4U)
/*! ANTX_EN - FAD Antenna Controls Enable
 *  0b00..all disabled (held low)
 *  0b01..only RX/TX_SWITCH enabled
 *  0b10..only ANT_A/B enabled
 *  0b11..all enabled
 */
#define XCVR_MISC_FAD_CTRL_ANTX_EN(x)            (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_FAD_CTRL_ANTX_EN_SHIFT)) & XCVR_MISC_FAD_CTRL_ANTX_EN_MASK)

#define XCVR_MISC_FAD_CTRL_ANTX_CTRLMODE_MASK    (0x80U)
#define XCVR_MISC_FAD_CTRL_ANTX_CTRLMODE_SHIFT   (7U)
/*! ANTX_CTRLMODE - Antenna Diversity Control Mode
 */
#define XCVR_MISC_FAD_CTRL_ANTX_CTRLMODE(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_FAD_CTRL_ANTX_CTRLMODE_SHIFT)) & XCVR_MISC_FAD_CTRL_ANTX_CTRLMODE_MASK)

#define XCVR_MISC_FAD_CTRL_ANTX_POL_MASK         (0xF00U)
#define XCVR_MISC_FAD_CTRL_ANTX_POL_SHIFT        (8U)
/*! ANTX_POL - FAD Antenna Controls Polarity
 */
#define XCVR_MISC_FAD_CTRL_ANTX_POL(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_FAD_CTRL_ANTX_POL_SHIFT)) & XCVR_MISC_FAD_CTRL_ANTX_POL_MASK)

#define XCVR_MISC_FAD_CTRL_FAD_NOT_GPIO_MASK     (0xF000U)
#define XCVR_MISC_FAD_CTRL_FAD_NOT_GPIO_SHIFT    (12U)
/*! FAD_NOT_GPIO - FAD versus GPIO Mode Selector
 */
#define XCVR_MISC_FAD_CTRL_FAD_NOT_GPIO(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_FAD_CTRL_FAD_NOT_GPIO_SHIFT)) & XCVR_MISC_FAD_CTRL_FAD_NOT_GPIO_MASK)

#define XCVR_MISC_FAD_CTRL_FAD_LANT_SEL_MASK     (0x10000U)
#define XCVR_MISC_FAD_CTRL_FAD_LANT_SEL_SHIFT    (16U)
/*! FAD_LANT_SEL - FAD versus LANT_LUT_GPIO Selector
 *  0b0..LANT_LUT_GPIO[3:0]
 *  0b1..{ANT_B, ANT_A, RX_SWITCH, TX_SWITCH}
 */
#define XCVR_MISC_FAD_CTRL_FAD_LANT_SEL(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_FAD_CTRL_FAD_LANT_SEL_SHIFT)) & XCVR_MISC_FAD_CTRL_FAD_LANT_SEL_MASK)
/*! @} */

/*! @name DMA_CTRL - TRANSCEIVER DMA CONTROL */
/*! @{ */

#define XCVR_MISC_DMA_CTRL_DMA_PAGE_MASK         (0xFU)
#define XCVR_MISC_DMA_CTRL_DMA_PAGE_SHIFT        (0U)
/*! DMA_PAGE - Transceiver DMA Page Selector
 *  0b0000..DMA idle
 *  0b0001..RXDIG-IQ: Select from (mixer, decimator, pd channel filter, src, cfo-mixer, demod chan filter) in RXDIG. 11bit signed data, MSB aligned
 *  0b0010..RXDIG-IQ-ALT: Same as above + signals on unused LSBs : {antenna switch, GenLL or 802.15.4LL CRC_FAIL}
 *          on "Q" LSBs, {preamble_found, aa_sfd_matched} on "I" LSBs.
 *  0b0011..ADC-IQ: 11bit samples are MSB aligned in each 16bit half-word
 *  0b0100..PHASE: Select from (sync phase, demod phase) within RXDIG. MSB aligned
 *  0b0101..RSSI-PHASE: select from 8bit Narrowband (rssi, rssi raw, lqi, snr, noise) and Wideband(rssi, rssi raw) + 8bit high-resolution PHASE
 *  0b0110..MAG-PHASE: RSSI magnitude + 8bit high-resolution PHASE
 *  0b0111..GEN4-PHY
 *  0b1000..DETERMINISTIC
 */
#define XCVR_MISC_DMA_CTRL_DMA_PAGE(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_DMA_CTRL_DMA_PAGE_SHIFT)) & XCVR_MISC_DMA_CTRL_DMA_PAGE_MASK)

#define XCVR_MISC_DMA_CTRL_DMA_START_TRG_MASK    (0xF0U)
#define XCVR_MISC_DMA_CTRL_DMA_START_TRG_SHIFT   (4U)
/*! DMA_START_TRG - DMA Start Trigger Selector
 *  0b0000..no trigger
 *  0b0001..PHY: pd found
 *  0b0010..PHY: aa found
 *  0b0011..Reserved
 *  0b0100..Reserved
 *  0b0101..RXDIG: agc_gain_chg
 *  0b0110..TSM: rx_dig_en
 *  0b0111..TSM: tsm_irq0_start_trig
 *  0b1000..CRC pass
 *  0b1001..CRC done
 *  0b1010..Localization control: pattern match
 *  0b1011..GenericLL: cte_present, Bluetooth LE: cte_en
 *  0b1100..Ranging sequence manager: dma_trigger
 */
#define XCVR_MISC_DMA_CTRL_DMA_START_TRG(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_DMA_CTRL_DMA_START_TRG_SHIFT)) & XCVR_MISC_DMA_CTRL_DMA_START_TRG_MASK)

#define XCVR_MISC_DMA_CTRL_DMA_START_EDGE_MASK   (0x100U)
#define XCVR_MISC_DMA_CTRL_DMA_START_EDGE_SHIFT  (8U)
/*! DMA_START_EDGE - DMA Start Trigger Edge Selector
 *  0b0..Trigger fires on a rising edge of the selected trigger source
 *  0b1..Trigger fires on a falling edge of the selected trigger source
 */
#define XCVR_MISC_DMA_CTRL_DMA_START_EDGE(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_DMA_CTRL_DMA_START_EDGE_SHIFT)) & XCVR_MISC_DMA_CTRL_DMA_START_EDGE_MASK)

#define XCVR_MISC_DMA_CTRL_DMA_DEC_MASK          (0xC00U)
#define XCVR_MISC_DMA_CTRL_DMA_DEC_SHIFT         (10U)
/*! DMA_DEC - DMA Decimation Rate
 *  0b00..Data is captured on every data valid
 *  0b01..Data is captured on every 2nd data valid
 *  0b10..Data is captured on every 4th data valid
 *  0b11..Data is captured on every 8th data valid
 */
#define XCVR_MISC_DMA_CTRL_DMA_DEC(x)            (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_DMA_CTRL_DMA_DEC_SHIFT)) & XCVR_MISC_DMA_CTRL_DMA_DEC_MASK)

#define XCVR_MISC_DMA_CTRL_DMA_START_DLY_MASK    (0x7FF000U)
#define XCVR_MISC_DMA_CTRL_DMA_START_DLY_SHIFT   (12U)
/*! DMA_START_DLY - DMA Start Trigger Delay
 */
#define XCVR_MISC_DMA_CTRL_DMA_START_DLY(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_DMA_CTRL_DMA_START_DLY_SHIFT)) & XCVR_MISC_DMA_CTRL_DMA_START_DLY_MASK)

#define XCVR_MISC_DMA_CTRL_DMA_EN_MASK           (0x800000U)
#define XCVR_MISC_DMA_CTRL_DMA_EN_SHIFT          (23U)
/*! DMA_EN - DMA Enable
 */
#define XCVR_MISC_DMA_CTRL_DMA_EN(x)             (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_DMA_CTRL_DMA_EN_SHIFT)) & XCVR_MISC_DMA_CTRL_DMA_EN_MASK)

#define XCVR_MISC_DMA_CTRL_DMA_AA_TRIGGERED_MASK (0x1000000U)
#define XCVR_MISC_DMA_CTRL_DMA_AA_TRIGGERED_SHIFT (24U)
/*! DMA_AA_TRIGGERED - DMA Access Address triggered
 */
#define XCVR_MISC_DMA_CTRL_DMA_AA_TRIGGERED(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_DMA_CTRL_DMA_AA_TRIGGERED_SHIFT)) & XCVR_MISC_DMA_CTRL_DMA_AA_TRIGGERED_MASK)

#define XCVR_MISC_DMA_CTRL_DMA_START_TRIGGERED_MASK (0x2000000U)
#define XCVR_MISC_DMA_CTRL_DMA_START_TRIGGERED_SHIFT (25U)
/*! DMA_START_TRIGGERED - DMA Start Trigger Occurred
 */
#define XCVR_MISC_DMA_CTRL_DMA_START_TRIGGERED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_DMA_CTRL_DMA_START_TRIGGERED_SHIFT)) & XCVR_MISC_DMA_CTRL_DMA_START_TRIGGERED_MASK)

#define XCVR_MISC_DMA_CTRL_DMA_SIGNAL_VALID_MASK_EN_MASK (0x80000000U)
#define XCVR_MISC_DMA_CTRL_DMA_SIGNAL_VALID_MASK_EN_SHIFT (31U)
/*! DMA_SIGNAL_VALID_MASK_EN - DMA Signal Valid Mask Enable
 *  0b0..Disable use of dma_signal_valid_mask.
 *  0b1..Enable use of dma_signal_valid_mask.
 */
#define XCVR_MISC_DMA_CTRL_DMA_SIGNAL_VALID_MASK_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_DMA_CTRL_DMA_SIGNAL_VALID_MASK_EN_SHIFT)) & XCVR_MISC_DMA_CTRL_DMA_SIGNAL_VALID_MASK_EN_MASK)
/*! @} */

/*! @name DBG_RAM_CTRL - DBG Ram control register */
/*! @{ */

#define XCVR_MISC_DBG_RAM_CTRL_DBG_PAGE_MASK     (0x7U)
#define XCVR_MISC_DBG_RAM_CTRL_DBG_PAGE_SHIFT    (0U)
/*! DBG_PAGE - Packet RAM Debug Page Selector
 *  0b000..DMA idle
 *  0b001..RXDIG-IQ: Select from (mixer, decimator, pd channel filter, src, cfo-mixer, demod chan filter) in RXDIG. 11bit signed data, MSB aligned
 *  0b010..RXDIG-IQ-ALT: Same as above + signals on unused LSBs : {antenna switch, GenLL or 802.15.4LL CRC_FAIL}
 *         on "Q" LSBs, {preamble_found, aa_sfd_matched} on "I" LSBs.
 *  0b011..ADC-IQ: 11bit samples are MSB aligned in each 16bit half-word
 *  0b100..PHASE: Select from (sync phase, demod phase) within RXDIG. MSB aligned
 *  0b101..RSSI-PHASE: select from 8bit Narrowband (rssi, rssi raw, lqi, snr, noise) and Wideband(rssi, rssi raw) + 8bit high-resolution PHASE
 *  0b110..MAG-PHASE: RSSI magnitude + 8bit high-resolution PHASE
 *  0b111..GEN4-PHY
 */
#define XCVR_MISC_DBG_RAM_CTRL_DBG_PAGE(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_DBG_RAM_CTRL_DBG_PAGE_SHIFT)) & XCVR_MISC_DBG_RAM_CTRL_DBG_PAGE_MASK)

#define XCVR_MISC_DBG_RAM_CTRL_DBG_SIGNAL_VALID_MASK_EN_MASK (0x8U)
#define XCVR_MISC_DBG_RAM_CTRL_DBG_SIGNAL_VALID_MASK_EN_SHIFT (3U)
/*! DBG_SIGNAL_VALID_MASK_EN - DBG Signal Valid Mask Enable
 *  0b0..Disable use of dbg_signal_valid_mask.
 *  0b1..Enable use of dbg_signal_valid_mask.
 */
#define XCVR_MISC_DBG_RAM_CTRL_DBG_SIGNAL_VALID_MASK_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_DBG_RAM_CTRL_DBG_SIGNAL_VALID_MASK_EN_SHIFT)) & XCVR_MISC_DBG_RAM_CTRL_DBG_SIGNAL_VALID_MASK_EN_MASK)

#define XCVR_MISC_DBG_RAM_CTRL_DBG_START_TRG_MASK (0xF0U)
#define XCVR_MISC_DBG_RAM_CTRL_DBG_START_TRG_SHIFT (4U)
/*! DBG_START_TRG - DMA Start Trigger Selector
 *  0b0000..no trigger
 *  0b0001..PHY: pd found
 *  0b0010..PHY: aa found
 *  0b0011..Reserved
 *  0b0100..Reserved
 *  0b0101..RXDIG: agc_gain_chg
 *  0b0110..TSM: rx_dig_en
 *  0b0111..TSM: tsm_irq0_start_trig
 *  0b1000..CRC pass
 *  0b1001..CRC done
 *  0b1010..Localization control: pattern match
 *  0b1011..GenericLL: cte_present, Bluetooth LE: cte_en
 *  0b1100..Ranging sequence manager: dma_trigger
 */
#define XCVR_MISC_DBG_RAM_CTRL_DBG_START_TRG(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_DBG_RAM_CTRL_DBG_START_TRG_SHIFT)) & XCVR_MISC_DBG_RAM_CTRL_DBG_START_TRG_MASK)

#define XCVR_MISC_DBG_RAM_CTRL_DBG_START_EDGE_MASK (0x100U)
#define XCVR_MISC_DBG_RAM_CTRL_DBG_START_EDGE_SHIFT (8U)
/*! DBG_START_EDGE - DBG Start Trigger Edge Selector
 *  0b0..Trigger fires on a rising edge of the selected trigger source
 *  0b1..Trigger fires on a falling edge of the selected trigger source
 */
#define XCVR_MISC_DBG_RAM_CTRL_DBG_START_EDGE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_DBG_RAM_CTRL_DBG_START_EDGE_SHIFT)) & XCVR_MISC_DBG_RAM_CTRL_DBG_START_EDGE_MASK)

#define XCVR_MISC_DBG_RAM_CTRL_DBG_STOP_EDGE_MASK (0x200U)
#define XCVR_MISC_DBG_RAM_CTRL_DBG_STOP_EDGE_SHIFT (9U)
/*! DBG_STOP_EDGE - DBG Stop Trigger Edge Selector
 *  0b0..Trigger stops on a rising edge of the selected trigger source
 *  0b1..Trigger stops on a falling edge of the selected trigger source
 */
#define XCVR_MISC_DBG_RAM_CTRL_DBG_STOP_EDGE(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_DBG_RAM_CTRL_DBG_STOP_EDGE_SHIFT)) & XCVR_MISC_DBG_RAM_CTRL_DBG_STOP_EDGE_MASK)

#define XCVR_MISC_DBG_RAM_CTRL_DBG_DEC_MASK      (0xC00U)
#define XCVR_MISC_DBG_RAM_CTRL_DBG_DEC_SHIFT     (10U)
/*! DBG_DEC - DBG Decimation Rate
 *  0b00..Data is captured on every data valid
 *  0b01..Data is captured on every 2nd data valid
 *  0b10..Data is captured on every 4th data valid
 *  0b11..Data is captured on every 8th data valid
 */
#define XCVR_MISC_DBG_RAM_CTRL_DBG_DEC(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_DBG_RAM_CTRL_DBG_DEC_SHIFT)) & XCVR_MISC_DBG_RAM_CTRL_DBG_DEC_MASK)

#define XCVR_MISC_DBG_RAM_CTRL_DBG_START_DLY_MASK (0x7FF000U)
#define XCVR_MISC_DBG_RAM_CTRL_DBG_START_DLY_SHIFT (12U)
/*! DBG_START_DLY - DBG Start Trigger Delay
 */
#define XCVR_MISC_DBG_RAM_CTRL_DBG_START_DLY(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_DBG_RAM_CTRL_DBG_START_DLY_SHIFT)) & XCVR_MISC_DBG_RAM_CTRL_DBG_START_DLY_MASK)

#define XCVR_MISC_DBG_RAM_CTRL_DBG_EN_MASK       (0x800000U)
#define XCVR_MISC_DBG_RAM_CTRL_DBG_EN_SHIFT      (23U)
/*! DBG_EN - DBG Enable
 */
#define XCVR_MISC_DBG_RAM_CTRL_DBG_EN(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_DBG_RAM_CTRL_DBG_EN_SHIFT)) & XCVR_MISC_DBG_RAM_CTRL_DBG_EN_MASK)

#define XCVR_MISC_DBG_RAM_CTRL_DBG_AA_TRIGGERED_MASK (0x1000000U)
#define XCVR_MISC_DBG_RAM_CTRL_DBG_AA_TRIGGERED_SHIFT (24U)
/*! DBG_AA_TRIGGERED - DBG Access Address triggered
 */
#define XCVR_MISC_DBG_RAM_CTRL_DBG_AA_TRIGGERED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_DBG_RAM_CTRL_DBG_AA_TRIGGERED_SHIFT)) & XCVR_MISC_DBG_RAM_CTRL_DBG_AA_TRIGGERED_MASK)

#define XCVR_MISC_DBG_RAM_CTRL_DBG_START_TRIGGERED_MASK (0x2000000U)
#define XCVR_MISC_DBG_RAM_CTRL_DBG_START_TRIGGERED_SHIFT (25U)
/*! DBG_START_TRIGGERED - DBG Start Trigger Occurred
 */
#define XCVR_MISC_DBG_RAM_CTRL_DBG_START_TRIGGERED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_DBG_RAM_CTRL_DBG_START_TRIGGERED_SHIFT)) & XCVR_MISC_DBG_RAM_CTRL_DBG_START_TRIGGERED_MASK)

#define XCVR_MISC_DBG_RAM_CTRL_DBG_STOP_TRIGGERED_MASK (0x4000000U)
#define XCVR_MISC_DBG_RAM_CTRL_DBG_STOP_TRIGGERED_SHIFT (26U)
/*! DBG_STOP_TRIGGERED - DBG Stop Trigger Occurred
 */
#define XCVR_MISC_DBG_RAM_CTRL_DBG_STOP_TRIGGERED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_DBG_RAM_CTRL_DBG_STOP_TRIGGERED_SHIFT)) & XCVR_MISC_DBG_RAM_CTRL_DBG_STOP_TRIGGERED_MASK)

#define XCVR_MISC_DBG_RAM_CTRL_DBG_RAM_FULL_MASK (0x8000000U)
#define XCVR_MISC_DBG_RAM_CTRL_DBG_RAM_FULL_SHIFT (27U)
/*! DBG_RAM_FULL - DBG_RAM_FULL
 *  0b0..Packet RAM is not full
 *  0b1..Packet RAM is full
 */
#define XCVR_MISC_DBG_RAM_CTRL_DBG_RAM_FULL(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_DBG_RAM_CTRL_DBG_RAM_FULL_SHIFT)) & XCVR_MISC_DBG_RAM_CTRL_DBG_RAM_FULL_MASK)

#define XCVR_MISC_DBG_RAM_CTRL_DBG_STOP_TRG_MASK (0xF0000000U)
#define XCVR_MISC_DBG_RAM_CTRL_DBG_STOP_TRG_SHIFT (28U)
/*! DBG_STOP_TRG - Packet RAM Debug Stop Trigger Selector
 *  0b0000..no trigger
 *  0b0001..PHY: pd found
 *  0b0010..PHY: aa found
 *  0b0011..Reserved
 *  0b0100..Reserved
 *  0b0101..RXDIG: agc_gain_chg
 *  0b0110..TSM: rx_dig_en
 *  0b0111..TSM: tsm_irq1_stop_trig
 *  0b1000..CRC fail
 *  0b1001..CRC done
 *  0b1010..RBME: error
 *  0b1011..GenericLL header fail
 *  0b1100..PLL unlock
 */
#define XCVR_MISC_DBG_RAM_CTRL_DBG_STOP_TRG(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_DBG_RAM_CTRL_DBG_STOP_TRG_SHIFT)) & XCVR_MISC_DBG_RAM_CTRL_DBG_STOP_TRG_MASK)
/*! @} */

/*! @name DBG_RAM_ADDR - DBG RAM ADDRESS */
/*! @{ */

#define XCVR_MISC_DBG_RAM_ADDR_DBG_RAM_FIRST_MASK (0x7FFFU)
#define XCVR_MISC_DBG_RAM_ADDR_DBG_RAM_FIRST_SHIFT (0U)
/*! DBG_RAM_FIRST - DBG RAM First Address
 */
#define XCVR_MISC_DBG_RAM_ADDR_DBG_RAM_FIRST(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_DBG_RAM_ADDR_DBG_RAM_FIRST_SHIFT)) & XCVR_MISC_DBG_RAM_ADDR_DBG_RAM_FIRST_MASK)

#define XCVR_MISC_DBG_RAM_ADDR_DBG_RAM_LAST_MASK (0x7FFF0000U)
#define XCVR_MISC_DBG_RAM_ADDR_DBG_RAM_LAST_SHIFT (16U)
/*! DBG_RAM_LAST - DBG RAM Last Address
 */
#define XCVR_MISC_DBG_RAM_ADDR_DBG_RAM_LAST(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_DBG_RAM_ADDR_DBG_RAM_LAST_SHIFT)) & XCVR_MISC_DBG_RAM_ADDR_DBG_RAM_LAST_MASK)
/*! @} */

/*! @name DBG_RAM_STOP_ADDR - DBG RAM STOP ADDRESS */
/*! @{ */

#define XCVR_MISC_DBG_RAM_STOP_ADDR_DBG_RAM_STOP_MASK (0x7FFFU)
#define XCVR_MISC_DBG_RAM_STOP_ADDR_DBG_RAM_STOP_SHIFT (0U)
/*! DBG_RAM_STOP - DBG RAM Stop Address
 */
#define XCVR_MISC_DBG_RAM_STOP_ADDR_DBG_RAM_STOP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_DBG_RAM_STOP_ADDR_DBG_RAM_STOP_SHIFT)) & XCVR_MISC_DBG_RAM_STOP_ADDR_DBG_RAM_STOP_MASK)
/*! @} */

/*! @name LDO_TRIM_0 - LDO TRIM Configuration 0 */
/*! @{ */

#define XCVR_MISC_LDO_TRIM_0_LDO_PLL_TRIM_OFFSET_MASK (0xFU)
#define XCVR_MISC_LDO_TRIM_0_LDO_PLL_TRIM_OFFSET_SHIFT (0U)
/*! LDO_PLL_TRIM_OFFSET - LDO PLL TRIM Offset
 */
#define XCVR_MISC_LDO_TRIM_0_LDO_PLL_TRIM_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LDO_TRIM_0_LDO_PLL_TRIM_OFFSET_SHIFT)) & XCVR_MISC_LDO_TRIM_0_LDO_PLL_TRIM_OFFSET_MASK)

#define XCVR_MISC_LDO_TRIM_0_LDO_VCO_TRIM_OFFSET_MASK (0xF0U)
#define XCVR_MISC_LDO_TRIM_0_LDO_VCO_TRIM_OFFSET_SHIFT (4U)
/*! LDO_VCO_TRIM_OFFSET - LDO VCO TRIM Offset
 */
#define XCVR_MISC_LDO_TRIM_0_LDO_VCO_TRIM_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LDO_TRIM_0_LDO_VCO_TRIM_OFFSET_SHIFT)) & XCVR_MISC_LDO_TRIM_0_LDO_VCO_TRIM_OFFSET_MASK)

#define XCVR_MISC_LDO_TRIM_0_LDO_RXTXLF_TRIM_OFFSET_MASK (0xF00U)
#define XCVR_MISC_LDO_TRIM_0_LDO_RXTXLF_TRIM_OFFSET_SHIFT (8U)
/*! LDO_RXTXLF_TRIM_OFFSET - LDO RXTXLF TRIM Offset
 */
#define XCVR_MISC_LDO_TRIM_0_LDO_RXTXLF_TRIM_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LDO_TRIM_0_LDO_RXTXLF_TRIM_OFFSET_SHIFT)) & XCVR_MISC_LDO_TRIM_0_LDO_RXTXLF_TRIM_OFFSET_MASK)

#define XCVR_MISC_LDO_TRIM_0_LDO_RXTXHF_TRIM_OFFSET_MASK (0xF000U)
#define XCVR_MISC_LDO_TRIM_0_LDO_RXTXHF_TRIM_OFFSET_SHIFT (12U)
/*! LDO_RXTXHF_TRIM_OFFSET - LDO RXTXHF TRIM Offset
 */
#define XCVR_MISC_LDO_TRIM_0_LDO_RXTXHF_TRIM_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LDO_TRIM_0_LDO_RXTXHF_TRIM_OFFSET_SHIFT)) & XCVR_MISC_LDO_TRIM_0_LDO_RXTXHF_TRIM_OFFSET_MASK)

#define XCVR_MISC_LDO_TRIM_0_LDO_TRIM_SMPL_DLY_MASK (0x30000U)
#define XCVR_MISC_LDO_TRIM_0_LDO_TRIM_SMPL_DLY_SHIFT (16U)
/*! LDO_TRIM_SMPL_DLY - LDO TRIM Sample Delay
 */
#define XCVR_MISC_LDO_TRIM_0_LDO_TRIM_SMPL_DLY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LDO_TRIM_0_LDO_TRIM_SMPL_DLY_SHIFT)) & XCVR_MISC_LDO_TRIM_0_LDO_TRIM_SMPL_DLY_MASK)

#define XCVR_MISC_LDO_TRIM_0_LDO_TRIM_CMPOUT_INV_MASK (0x80000U)
#define XCVR_MISC_LDO_TRIM_0_LDO_TRIM_CMPOUT_INV_SHIFT (19U)
/*! LDO_TRIM_CMPOUT_INV - LDO TRIM CMPOUT Invert
 */
#define XCVR_MISC_LDO_TRIM_0_LDO_TRIM_CMPOUT_INV(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LDO_TRIM_0_LDO_TRIM_CMPOUT_INV_SHIFT)) & XCVR_MISC_LDO_TRIM_0_LDO_TRIM_CMPOUT_INV_MASK)

#define XCVR_MISC_LDO_TRIM_0_LDO_CAL_TRIMSEL_OVRD_MASK (0x1000000U)
#define XCVR_MISC_LDO_TRIM_0_LDO_CAL_TRIMSEL_OVRD_SHIFT (24U)
/*! LDO_CAL_TRIMSEL_OVRD - LDO_CAL_TRIMSEL Override Value
 */
#define XCVR_MISC_LDO_TRIM_0_LDO_CAL_TRIMSEL_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LDO_TRIM_0_LDO_CAL_TRIMSEL_OVRD_SHIFT)) & XCVR_MISC_LDO_TRIM_0_LDO_CAL_TRIMSEL_OVRD_MASK)

#define XCVR_MISC_LDO_TRIM_0_LDO_PLL_TRIMSEL_OVRD_MASK (0x2000000U)
#define XCVR_MISC_LDO_TRIM_0_LDO_PLL_TRIMSEL_OVRD_SHIFT (25U)
/*! LDO_PLL_TRIMSEL_OVRD - LDO_PLL_TRIMSEL Override Value
 */
#define XCVR_MISC_LDO_TRIM_0_LDO_PLL_TRIMSEL_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LDO_TRIM_0_LDO_PLL_TRIMSEL_OVRD_SHIFT)) & XCVR_MISC_LDO_TRIM_0_LDO_PLL_TRIMSEL_OVRD_MASK)

#define XCVR_MISC_LDO_TRIM_0_LDO_VCO_TRIMSEL_OVRD_MASK (0x4000000U)
#define XCVR_MISC_LDO_TRIM_0_LDO_VCO_TRIMSEL_OVRD_SHIFT (26U)
/*! LDO_VCO_TRIMSEL_OVRD - LDO_VCO_TRIMSEL Override Value
 */
#define XCVR_MISC_LDO_TRIM_0_LDO_VCO_TRIMSEL_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LDO_TRIM_0_LDO_VCO_TRIMSEL_OVRD_SHIFT)) & XCVR_MISC_LDO_TRIM_0_LDO_VCO_TRIMSEL_OVRD_MASK)

#define XCVR_MISC_LDO_TRIM_0_LDO_RXTXHF_TRIMSEL_OVRD_MASK (0x10000000U)
#define XCVR_MISC_LDO_TRIM_0_LDO_RXTXHF_TRIMSEL_OVRD_SHIFT (28U)
/*! LDO_RXTXHF_TRIMSEL_OVRD - LDO_RXTXHF_TRIMSEL Override Value
 */
#define XCVR_MISC_LDO_TRIM_0_LDO_RXTXHF_TRIMSEL_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LDO_TRIM_0_LDO_RXTXHF_TRIMSEL_OVRD_SHIFT)) & XCVR_MISC_LDO_TRIM_0_LDO_RXTXHF_TRIMSEL_OVRD_MASK)

#define XCVR_MISC_LDO_TRIM_0_LDO_TRIM_SAMPLE_OVRD_MASK (0x20000000U)
#define XCVR_MISC_LDO_TRIM_0_LDO_TRIM_SAMPLE_OVRD_SHIFT (29U)
/*! LDO_TRIM_SAMPLE_OVRD - LDO_TRIM_SAMPLE Override Value
 */
#define XCVR_MISC_LDO_TRIM_0_LDO_TRIM_SAMPLE_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LDO_TRIM_0_LDO_TRIM_SAMPLE_OVRD_SHIFT)) & XCVR_MISC_LDO_TRIM_0_LDO_TRIM_SAMPLE_OVRD_MASK)

#define XCVR_MISC_LDO_TRIM_0_LDO_SAMPLE_TRIMSEL_OVRD_EN_MASK (0x40000000U)
#define XCVR_MISC_LDO_TRIM_0_LDO_SAMPLE_TRIMSEL_OVRD_EN_SHIFT (30U)
/*! LDO_SAMPLE_TRIMSEL_OVRD_EN - LDO SAMPLE TRIMSEL Override Enable
 */
#define XCVR_MISC_LDO_TRIM_0_LDO_SAMPLE_TRIMSEL_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LDO_TRIM_0_LDO_SAMPLE_TRIMSEL_OVRD_EN_SHIFT)) & XCVR_MISC_LDO_TRIM_0_LDO_SAMPLE_TRIMSEL_OVRD_EN_MASK)
/*! @} */

/*! @name LDO_TRIM_1 - LDO TRIM Configuration 1 */
/*! @{ */

#define XCVR_MISC_LDO_TRIM_1_LDO_PLL_TRIM_OVRD_MASK (0x3FU)
#define XCVR_MISC_LDO_TRIM_1_LDO_PLL_TRIM_OVRD_SHIFT (0U)
/*! LDO_PLL_TRIM_OVRD - LDO PLL TRIM Override Value
 */
#define XCVR_MISC_LDO_TRIM_1_LDO_PLL_TRIM_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LDO_TRIM_1_LDO_PLL_TRIM_OVRD_SHIFT)) & XCVR_MISC_LDO_TRIM_1_LDO_PLL_TRIM_OVRD_MASK)

#define XCVR_MISC_LDO_TRIM_1_LDO_PLL_TRIM_OVRD_EN_MASK (0x40U)
#define XCVR_MISC_LDO_TRIM_1_LDO_PLL_TRIM_OVRD_EN_SHIFT (6U)
/*! LDO_PLL_TRIM_OVRD_EN - LDO PLL TRIM Override Enable
 */
#define XCVR_MISC_LDO_TRIM_1_LDO_PLL_TRIM_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LDO_TRIM_1_LDO_PLL_TRIM_OVRD_EN_SHIFT)) & XCVR_MISC_LDO_TRIM_1_LDO_PLL_TRIM_OVRD_EN_MASK)

#define XCVR_MISC_LDO_TRIM_1_LDO_VCO_TRIM_OVRD_MASK (0x3F00U)
#define XCVR_MISC_LDO_TRIM_1_LDO_VCO_TRIM_OVRD_SHIFT (8U)
/*! LDO_VCO_TRIM_OVRD - LDO VCO TRIM Override Value
 */
#define XCVR_MISC_LDO_TRIM_1_LDO_VCO_TRIM_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LDO_TRIM_1_LDO_VCO_TRIM_OVRD_SHIFT)) & XCVR_MISC_LDO_TRIM_1_LDO_VCO_TRIM_OVRD_MASK)

#define XCVR_MISC_LDO_TRIM_1_LDO_VCO_TRIM_OVRD_EN_MASK (0x4000U)
#define XCVR_MISC_LDO_TRIM_1_LDO_VCO_TRIM_OVRD_EN_SHIFT (14U)
/*! LDO_VCO_TRIM_OVRD_EN - VCO TRIM Override Enable
 */
#define XCVR_MISC_LDO_TRIM_1_LDO_VCO_TRIM_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LDO_TRIM_1_LDO_VCO_TRIM_OVRD_EN_SHIFT)) & XCVR_MISC_LDO_TRIM_1_LDO_VCO_TRIM_OVRD_EN_MASK)

#define XCVR_MISC_LDO_TRIM_1_LDO_RXTXLF_TRIM_OVRD_MASK (0x3F0000U)
#define XCVR_MISC_LDO_TRIM_1_LDO_RXTXLF_TRIM_OVRD_SHIFT (16U)
/*! LDO_RXTXLF_TRIM_OVRD - LDO RXTXLF TRIM Override Value
 */
#define XCVR_MISC_LDO_TRIM_1_LDO_RXTXLF_TRIM_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LDO_TRIM_1_LDO_RXTXLF_TRIM_OVRD_SHIFT)) & XCVR_MISC_LDO_TRIM_1_LDO_RXTXLF_TRIM_OVRD_MASK)

#define XCVR_MISC_LDO_TRIM_1_LDO_RXTXLF_TRIM_OVRD_EN_MASK (0x400000U)
#define XCVR_MISC_LDO_TRIM_1_LDO_RXTXLF_TRIM_OVRD_EN_SHIFT (22U)
/*! LDO_RXTXLF_TRIM_OVRD_EN - LDO RXTXLF TRIM Override Enable
 */
#define XCVR_MISC_LDO_TRIM_1_LDO_RXTXLF_TRIM_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LDO_TRIM_1_LDO_RXTXLF_TRIM_OVRD_EN_SHIFT)) & XCVR_MISC_LDO_TRIM_1_LDO_RXTXLF_TRIM_OVRD_EN_MASK)

#define XCVR_MISC_LDO_TRIM_1_LDO_RXTXHF_TRIM_OVRD_MASK (0x3F000000U)
#define XCVR_MISC_LDO_TRIM_1_LDO_RXTXHF_TRIM_OVRD_SHIFT (24U)
/*! LDO_RXTXHF_TRIM_OVRD - LDO RXTXHF TRIM Override Value
 */
#define XCVR_MISC_LDO_TRIM_1_LDO_RXTXHF_TRIM_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LDO_TRIM_1_LDO_RXTXHF_TRIM_OVRD_SHIFT)) & XCVR_MISC_LDO_TRIM_1_LDO_RXTXHF_TRIM_OVRD_MASK)

#define XCVR_MISC_LDO_TRIM_1_LDO_RXTXHF_TRIM_OVRD_EN_MASK (0x40000000U)
#define XCVR_MISC_LDO_TRIM_1_LDO_RXTXHF_TRIM_OVRD_EN_SHIFT (30U)
/*! LDO_RXTXHF_TRIM_OVRD_EN - LDO RXTXHF TRIM Override Enable
 */
#define XCVR_MISC_LDO_TRIM_1_LDO_RXTXHF_TRIM_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LDO_TRIM_1_LDO_RXTXHF_TRIM_OVRD_EN_SHIFT)) & XCVR_MISC_LDO_TRIM_1_LDO_RXTXHF_TRIM_OVRD_EN_MASK)
/*! @} */

/*! @name LDO_TRIM_RES_0 - RF Analog LDO Trim Res Control 0 */
/*! @{ */

#define XCVR_MISC_LDO_TRIM_RES_0_LDO_PLL_TRIM_MASK (0x3FU)
#define XCVR_MISC_LDO_TRIM_RES_0_LDO_PLL_TRIM_SHIFT (0U)
/*! LDO_PLL_TRIM - LDO_PLL_TRIM Result
 */
#define XCVR_MISC_LDO_TRIM_RES_0_LDO_PLL_TRIM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LDO_TRIM_RES_0_LDO_PLL_TRIM_SHIFT)) & XCVR_MISC_LDO_TRIM_RES_0_LDO_PLL_TRIM_MASK)

#define XCVR_MISC_LDO_TRIM_RES_0_LDO_VCO_TRIM_MASK (0x3F00U)
#define XCVR_MISC_LDO_TRIM_RES_0_LDO_VCO_TRIM_SHIFT (8U)
/*! LDO_VCO_TRIM - LDO_VCO_TRIM Result
 */
#define XCVR_MISC_LDO_TRIM_RES_0_LDO_VCO_TRIM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LDO_TRIM_RES_0_LDO_VCO_TRIM_SHIFT)) & XCVR_MISC_LDO_TRIM_RES_0_LDO_VCO_TRIM_MASK)

#define XCVR_MISC_LDO_TRIM_RES_0_LDO_RXTXLF_TRIM_MASK (0x3F0000U)
#define XCVR_MISC_LDO_TRIM_RES_0_LDO_RXTXLF_TRIM_SHIFT (16U)
/*! LDO_RXTXLF_TRIM - LDO_RXTXLF_TRIM Result
 */
#define XCVR_MISC_LDO_TRIM_RES_0_LDO_RXTXLF_TRIM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LDO_TRIM_RES_0_LDO_RXTXLF_TRIM_SHIFT)) & XCVR_MISC_LDO_TRIM_RES_0_LDO_RXTXLF_TRIM_MASK)

#define XCVR_MISC_LDO_TRIM_RES_0_LDO_RXTXHF_TRIM_MASK (0x3F000000U)
#define XCVR_MISC_LDO_TRIM_RES_0_LDO_RXTXHF_TRIM_SHIFT (24U)
/*! LDO_RXTXHF_TRIM - LDO_RXTXHF_TRIM Result
 */
#define XCVR_MISC_LDO_TRIM_RES_0_LDO_RXTXHF_TRIM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LDO_TRIM_RES_0_LDO_RXTXHF_TRIM_SHIFT)) & XCVR_MISC_LDO_TRIM_RES_0_LDO_RXTXHF_TRIM_MASK)
/*! @} */

/*! @name LDO_TRIM_RES_1 - RF Analog LDO Trim Res Control 1 */
/*! @{ */

#define XCVR_MISC_LDO_TRIM_RES_1_LDO_CAL_TRIM_MASK (0x3FU)
#define XCVR_MISC_LDO_TRIM_RES_1_LDO_CAL_TRIM_SHIFT (0U)
/*! LDO_CAL_TRIM - LDO_CAL_TRIM Result
 */
#define XCVR_MISC_LDO_TRIM_RES_1_LDO_CAL_TRIM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LDO_TRIM_RES_1_LDO_CAL_TRIM_SHIFT)) & XCVR_MISC_LDO_TRIM_RES_1_LDO_CAL_TRIM_MASK)

#define XCVR_MISC_LDO_TRIM_RES_1_LDO_TRIM_CMPOUT_MASK (0x100U)
#define XCVR_MISC_LDO_TRIM_RES_1_LDO_TRIM_CMPOUT_SHIFT (8U)
/*! LDO_TRIM_CMPOUT - LDO TRIM CMPOUT
 */
#define XCVR_MISC_LDO_TRIM_RES_1_LDO_TRIM_CMPOUT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LDO_TRIM_RES_1_LDO_TRIM_CMPOUT_SHIFT)) & XCVR_MISC_LDO_TRIM_RES_1_LDO_TRIM_CMPOUT_MASK)
/*! @} */

/*! @name LCL_CFG0 - LCL CTRL CFG 0 */
/*! @{ */

#define XCVR_MISC_LCL_CFG0_LCL_EN_MASK           (0x1U)
#define XCVR_MISC_LCL_CFG0_LCL_EN_SHIFT          (0U)
/*! LCL_EN - Localization Control Module Enable
 */
#define XCVR_MISC_LCL_CFG0_LCL_EN(x)             (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_CFG0_LCL_EN_SHIFT)) & XCVR_MISC_LCL_CFG0_LCL_EN_MASK)

#define XCVR_MISC_LCL_CFG0_TX_LCL_EN_MASK        (0x2U)
#define XCVR_MISC_LCL_CFG0_TX_LCL_EN_SHIFT       (1U)
/*! TX_LCL_EN - Enable Switching in TX
 */
#define XCVR_MISC_LCL_CFG0_TX_LCL_EN(x)          (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_CFG0_TX_LCL_EN_SHIFT)) & XCVR_MISC_LCL_CFG0_TX_LCL_EN_MASK)

#define XCVR_MISC_LCL_CFG0_RX_LCL_EN_MASK        (0x4U)
#define XCVR_MISC_LCL_CFG0_RX_LCL_EN_SHIFT       (2U)
/*! RX_LCL_EN - Enable Switching in RX
 */
#define XCVR_MISC_LCL_CFG0_RX_LCL_EN(x)          (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_CFG0_RX_LCL_EN_SHIFT)) & XCVR_MISC_LCL_CFG0_RX_LCL_EN_MASK)

#define XCVR_MISC_LCL_CFG0_LANT_INV_MASK         (0x8U)
#define XCVR_MISC_LCL_CFG0_LANT_INV_SHIFT        (3U)
/*! LANT_INV - Invert Antenna Switch Output
 */
#define XCVR_MISC_LCL_CFG0_LANT_INV(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_CFG0_LANT_INV_SHIFT)) & XCVR_MISC_LCL_CFG0_LANT_INV_MASK)

#define XCVR_MISC_LCL_CFG0_COMP_EN_MASK          (0x10U)
#define XCVR_MISC_LCL_CFG0_COMP_EN_SHIFT         (4U)
/*! COMP_EN - Pattern Matching Enable
 */
#define XCVR_MISC_LCL_CFG0_COMP_EN(x)            (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_CFG0_COMP_EN_SHIFT)) & XCVR_MISC_LCL_CFG0_COMP_EN_MASK)

#define XCVR_MISC_LCL_CFG0_COMP_TX_EN_MASK       (0x20U)
#define XCVR_MISC_LCL_CFG0_COMP_TX_EN_SHIFT      (5U)
/*! COMP_TX_EN - Pattern Matching Enable in TX
 */
#define XCVR_MISC_LCL_CFG0_COMP_TX_EN(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_CFG0_COMP_TX_EN_SHIFT)) & XCVR_MISC_LCL_CFG0_COMP_TX_EN_MASK)

#define XCVR_MISC_LCL_CFG0_SW_TRIG_MASK          (0x40U)
#define XCVR_MISC_LCL_CFG0_SW_TRIG_SHIFT         (6U)
/*! SW_TRIG - Software Trigger. Can be used with either RX or TX
 */
#define XCVR_MISC_LCL_CFG0_SW_TRIG(x)            (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_CFG0_SW_TRIG_SHIFT)) & XCVR_MISC_LCL_CFG0_SW_TRIG_MASK)

#define XCVR_MISC_LCL_CFG0_LANT_SW_WIGGLE_MASK   (0x80U)
#define XCVR_MISC_LCL_CFG0_LANT_SW_WIGGLE_SHIFT  (7U)
/*! LANT_SW_WIGGLE - LANT_SW Wiggle
 */
#define XCVR_MISC_LCL_CFG0_LANT_SW_WIGGLE(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_CFG0_LANT_SW_WIGGLE_SHIFT)) & XCVR_MISC_LCL_CFG0_LANT_SW_WIGGLE_MASK)

#define XCVR_MISC_LCL_CFG0_PM_NUM_BYTES_MASK     (0x300U)
#define XCVR_MISC_LCL_CFG0_PM_NUM_BYTES_SHIFT    (8U)
/*! PM_NUM_BYTES - Number of Bytes to Match
 *  0b00..4 bytes
 *  0b01..5 bytes
 *  0b10..6 bytes
 *  0b11..8 bytes
 */
#define XCVR_MISC_LCL_CFG0_PM_NUM_BYTES(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_CFG0_PM_NUM_BYTES_SHIFT)) & XCVR_MISC_LCL_CFG0_PM_NUM_BYTES_MASK)

#define XCVR_MISC_LCL_CFG0_LANT_BLOCK_TX_MASK    (0x400U)
#define XCVR_MISC_LCL_CFG0_LANT_BLOCK_TX_SHIFT   (10U)
/*! LANT_BLOCK_TX - Block LANT_SW for TX
 */
#define XCVR_MISC_LCL_CFG0_LANT_BLOCK_TX(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_CFG0_LANT_BLOCK_TX_SHIFT)) & XCVR_MISC_LCL_CFG0_LANT_BLOCK_TX_MASK)

#define XCVR_MISC_LCL_CFG0_LANT_BLOCK_RX_MASK    (0x800U)
#define XCVR_MISC_LCL_CFG0_LANT_BLOCK_RX_SHIFT   (11U)
/*! LANT_BLOCK_RX - Block LANT_SW for RX
 */
#define XCVR_MISC_LCL_CFG0_LANT_BLOCK_RX(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_CFG0_LANT_BLOCK_RX_SHIFT)) & XCVR_MISC_LCL_CFG0_LANT_BLOCK_RX_MASK)

#define XCVR_MISC_LCL_CFG0_CTE_DUR_MASK          (0x1FF0000U)
#define XCVR_MISC_LCL_CFG0_CTE_DUR_SHIFT         (16U)
/*! CTE_DUR - Total Switching Duration
 */
#define XCVR_MISC_LCL_CFG0_CTE_DUR(x)            (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_CFG0_CTE_DUR_SHIFT)) & XCVR_MISC_LCL_CFG0_CTE_DUR_MASK)

#define XCVR_MISC_LCL_CFG0_LCL_GPIO_SEL_MASK     (0x40000000U)
#define XCVR_MISC_LCL_CFG0_LCL_GPIO_SEL_SHIFT    (30U)
/*! LCL_GPIO_SEL - Localization GPIO Select
 */
#define XCVR_MISC_LCL_CFG0_LCL_GPIO_SEL(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_CFG0_LCL_GPIO_SEL_SHIFT)) & XCVR_MISC_LCL_CFG0_LCL_GPIO_SEL_MASK)

#define XCVR_MISC_LCL_CFG0_LCL_MODE_MASK         (0x80000000U)
#define XCVR_MISC_LCL_CFG0_LCL_MODE_SHIFT        (31U)
/*! LCL_MODE - Localization Mode
 *  0b0..GenLL configuration.
 *  0b1..Bluetooth LE LL configuration.
 */
#define XCVR_MISC_LCL_CFG0_LCL_MODE(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_CFG0_LCL_MODE_SHIFT)) & XCVR_MISC_LCL_CFG0_LCL_MODE_MASK)
/*! @} */

/*! @name LCL_CFG1 - LCL CTRL CFG 1 */
/*! @{ */

#define XCVR_MISC_LCL_CFG1_M_ON_DELAY_MASK       (0x3FFU)
#define XCVR_MISC_LCL_CFG1_M_ON_DELAY_SHIFT      (0U)
/*! M_ON_DELAY - M on Delay
 */
#define XCVR_MISC_LCL_CFG1_M_ON_DELAY(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_CFG1_M_ON_DELAY_SHIFT)) & XCVR_MISC_LCL_CFG1_M_ON_DELAY_MASK)

#define XCVR_MISC_LCL_CFG1_N_ON_DELAY_MASK       (0xF000U)
#define XCVR_MISC_LCL_CFG1_N_ON_DELAY_SHIFT      (12U)
/*! N_ON_DELAY - N on Delay
 */
#define XCVR_MISC_LCL_CFG1_N_ON_DELAY(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_CFG1_N_ON_DELAY_SHIFT)) & XCVR_MISC_LCL_CFG1_N_ON_DELAY_MASK)

#define XCVR_MISC_LCL_CFG1_LANT_SW_IE_MASK       (0x40000000U)
#define XCVR_MISC_LCL_CFG1_LANT_SW_IE_SHIFT      (30U)
/*! LANT_SW_IE - Localization Antenna Switch Interrupt Enable
 *  0b0..Localization Antenna Switch interrupt disabled
 *  0b1..Localization Antenna Switch interrupt enabled
 */
#define XCVR_MISC_LCL_CFG1_LANT_SW_IE(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_CFG1_LANT_SW_IE_SHIFT)) & XCVR_MISC_LCL_CFG1_LANT_SW_IE_MASK)

#define XCVR_MISC_LCL_CFG1_LANT_SW_FLAG_MASK     (0x80000000U)
#define XCVR_MISC_LCL_CFG1_LANT_SW_FLAG_SHIFT    (31U)
/*! LANT_SW_FLAG - Localization Antenna Switch Flag
 */
#define XCVR_MISC_LCL_CFG1_LANT_SW_FLAG(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_CFG1_LANT_SW_FLAG_SHIFT)) & XCVR_MISC_LCL_CFG1_LANT_SW_FLAG_MASK)
/*! @} */

/*! @name LCL_TX_CFG0 - LCL CTRL TX CONFIG0 */
/*! @{ */

#define XCVR_MISC_LCL_TX_CFG0_TX_DELAY_MASK      (0x7FFU)
#define XCVR_MISC_LCL_TX_CFG0_TX_DELAY_SHIFT     (0U)
/*! TX_DELAY - Interval delay before TX switching begins.
 */
#define XCVR_MISC_LCL_TX_CFG0_TX_DELAY(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_TX_CFG0_TX_DELAY_SHIFT)) & XCVR_MISC_LCL_TX_CFG0_TX_DELAY_MASK)

#define XCVR_MISC_LCL_TX_CFG0_TX_DELAY_OFF_MASK  (0x1F0000U)
#define XCVR_MISC_LCL_TX_CFG0_TX_DELAY_OFF_SHIFT (16U)
/*! TX_DELAY_OFF - Fine sample delay after TX_DELAY.
 */
#define XCVR_MISC_LCL_TX_CFG0_TX_DELAY_OFF(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_TX_CFG0_TX_DELAY_OFF_SHIFT)) & XCVR_MISC_LCL_TX_CFG0_TX_DELAY_OFF_MASK)
/*! @} */

/*! @name LCL_TX_CFG1 - LCL CTRL TX CONFIG1 */
/*! @{ */

#define XCVR_MISC_LCL_TX_CFG1_TX_SPINT_MASK      (0x1FU)
#define XCVR_MISC_LCL_TX_CFG1_TX_SPINT_SHIFT     (0U)
/*! TX_SPINT - Number of TX Samples that define the length of an Interval, where 0=1sample, 1=2sample, etc.
 */
#define XCVR_MISC_LCL_TX_CFG1_TX_SPINT(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_TX_CFG1_TX_SPINT_SHIFT)) & XCVR_MISC_LCL_TX_CFG1_TX_SPINT_MASK)

#define XCVR_MISC_LCL_TX_CFG1_TX_ANT_TRIG_SEL_MASK (0xE0U)
#define XCVR_MISC_LCL_TX_CFG1_TX_ANT_TRIG_SEL_SHIFT (5U)
/*! TX_ANT_TRIG_SEL - Selects Trigger for TX
 *  0b000..Software Trigger
 *  0b001..LCL Pattern Found
 *  0b010..CRC Complete
 *  0b011..PA Warmup Complete
 *  0b100..RBME tx_done_pre
 *  0b101..Bluetooth LE cte_en
 *  0b110..Ranging sequence manager lcl_tx_trigger
 */
#define XCVR_MISC_LCL_TX_CFG1_TX_ANT_TRIG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_TX_CFG1_TX_ANT_TRIG_SEL_SHIFT)) & XCVR_MISC_LCL_TX_CFG1_TX_ANT_TRIG_SEL_MASK)

#define XCVR_MISC_LCL_TX_CFG1_TX_LO_PER_MASK     (0x1F000U)
#define XCVR_MISC_LCL_TX_CFG1_TX_LO_PER_SHIFT    (12U)
/*! TX_LO_PER - Primary Number of intervals for antenna LOW
 */
#define XCVR_MISC_LCL_TX_CFG1_TX_LO_PER(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_TX_CFG1_TX_LO_PER_SHIFT)) & XCVR_MISC_LCL_TX_CFG1_TX_LO_PER_MASK)

#define XCVR_MISC_LCL_TX_CFG1_TX_HI_PER_MASK     (0x3E0000U)
#define XCVR_MISC_LCL_TX_CFG1_TX_HI_PER_SHIFT    (17U)
/*! TX_HI_PER - Primary Number of intervals for antenna HIGH
 */
#define XCVR_MISC_LCL_TX_CFG1_TX_HI_PER(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_TX_CFG1_TX_HI_PER_SHIFT)) & XCVR_MISC_LCL_TX_CFG1_TX_HI_PER_MASK)

#define XCVR_MISC_LCL_TX_CFG1_TX_LO_PER_1_MASK   (0x7C00000U)
#define XCVR_MISC_LCL_TX_CFG1_TX_LO_PER_1_SHIFT  (22U)
/*! TX_LO_PER_1 - Alternate Number of intervals for antenna LOW. Used only in conjunction with RSM.
 */
#define XCVR_MISC_LCL_TX_CFG1_TX_LO_PER_1(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_TX_CFG1_TX_LO_PER_1_SHIFT)) & XCVR_MISC_LCL_TX_CFG1_TX_LO_PER_1_MASK)

#define XCVR_MISC_LCL_TX_CFG1_TX_HI_PER_1_MASK   (0xF8000000U)
#define XCVR_MISC_LCL_TX_CFG1_TX_HI_PER_1_SHIFT  (27U)
/*! TX_HI_PER_1 - Alternate Number of intervals for antenna HIGH. Used only in conjunction with RSM.
 */
#define XCVR_MISC_LCL_TX_CFG1_TX_HI_PER_1(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_TX_CFG1_TX_HI_PER_1_SHIFT)) & XCVR_MISC_LCL_TX_CFG1_TX_HI_PER_1_MASK)
/*! @} */

/*! @name LCL_TX_CFG2 - LCL CTRL TX CONFIG2 */
/*! @{ */

#define XCVR_MISC_LCL_TX_CFG2_TX_LO_PER_2_MASK   (0x1F000U)
#define XCVR_MISC_LCL_TX_CFG2_TX_LO_PER_2_SHIFT  (12U)
/*! TX_LO_PER_2 - Alternate Number of intervals for antenna LOW. Used only in conjunction with RSM.
 */
#define XCVR_MISC_LCL_TX_CFG2_TX_LO_PER_2(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_TX_CFG2_TX_LO_PER_2_SHIFT)) & XCVR_MISC_LCL_TX_CFG2_TX_LO_PER_2_MASK)

#define XCVR_MISC_LCL_TX_CFG2_TX_HI_PER_2_MASK   (0x3E0000U)
#define XCVR_MISC_LCL_TX_CFG2_TX_HI_PER_2_SHIFT  (17U)
/*! TX_HI_PER_2 - Alternate Number of intervals for antenna HIGH. Used only in conjunction with RSM.
 */
#define XCVR_MISC_LCL_TX_CFG2_TX_HI_PER_2(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_TX_CFG2_TX_HI_PER_2_SHIFT)) & XCVR_MISC_LCL_TX_CFG2_TX_HI_PER_2_MASK)

#define XCVR_MISC_LCL_TX_CFG2_TX_LO_PER_3_MASK   (0x7C00000U)
#define XCVR_MISC_LCL_TX_CFG2_TX_LO_PER_3_SHIFT  (22U)
/*! TX_LO_PER_3 - Alternate Number of intervals for antenna LOW. Used only in conjunction with RSM.
 */
#define XCVR_MISC_LCL_TX_CFG2_TX_LO_PER_3(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_TX_CFG2_TX_LO_PER_3_SHIFT)) & XCVR_MISC_LCL_TX_CFG2_TX_LO_PER_3_MASK)

#define XCVR_MISC_LCL_TX_CFG2_TX_HI_PER_3_MASK   (0xF8000000U)
#define XCVR_MISC_LCL_TX_CFG2_TX_HI_PER_3_SHIFT  (27U)
/*! TX_HI_PER_3 - Alternate Number of intervals for antenna HIGH. Used only in conjunction with RSM.
 */
#define XCVR_MISC_LCL_TX_CFG2_TX_HI_PER_3(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_TX_CFG2_TX_HI_PER_3_SHIFT)) & XCVR_MISC_LCL_TX_CFG2_TX_HI_PER_3_MASK)
/*! @} */

/*! @name LCL_RX_CFG0 - LCL CTRL RX CONFIG0 */
/*! @{ */

#define XCVR_MISC_LCL_RX_CFG0_RX_DELAY_MASK      (0x7FFU)
#define XCVR_MISC_LCL_RX_CFG0_RX_DELAY_SHIFT     (0U)
/*! RX_DELAY - Interval delay before RX switching begins.
 */
#define XCVR_MISC_LCL_RX_CFG0_RX_DELAY(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_RX_CFG0_RX_DELAY_SHIFT)) & XCVR_MISC_LCL_RX_CFG0_RX_DELAY_MASK)

#define XCVR_MISC_LCL_RX_CFG0_RX_DELAY_OFF_MASK  (0x1F0000U)
#define XCVR_MISC_LCL_RX_CFG0_RX_DELAY_OFF_SHIFT (16U)
/*! RX_DELAY_OFF - Fine sample delay after RX_DELAY.
 */
#define XCVR_MISC_LCL_RX_CFG0_RX_DELAY_OFF(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_RX_CFG0_RX_DELAY_OFF_SHIFT)) & XCVR_MISC_LCL_RX_CFG0_RX_DELAY_OFF_MASK)
/*! @} */

/*! @name LCL_RX_CFG1 - LCL CTRL RX CONFIG1 */
/*! @{ */

#define XCVR_MISC_LCL_RX_CFG1_RX_SPINT_MASK      (0x1FU)
#define XCVR_MISC_LCL_RX_CFG1_RX_SPINT_SHIFT     (0U)
/*! RX_SPINT - Number of RX Samples that define the length of an Interval, where 0=1sample, 1=2sample, etc.
 */
#define XCVR_MISC_LCL_RX_CFG1_RX_SPINT(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_RX_CFG1_RX_SPINT_SHIFT)) & XCVR_MISC_LCL_RX_CFG1_RX_SPINT_MASK)

#define XCVR_MISC_LCL_RX_CFG1_RX_ANT_TRIG_SEL_MASK (0xE0U)
#define XCVR_MISC_LCL_RX_CFG1_RX_ANT_TRIG_SEL_SHIFT (5U)
/*! RX_ANT_TRIG_SEL - Selects Trigger for RX
 *  0b000..Software Trigger
 *  0b001..LCL Pattern Found
 *  0b010..CRC Complete
 *  0b011..CRC Pass
 *  0b100..GenericLL: cte_present, Bluetooth LE: cte_en
 *  0b101..aa_fnd_to_ll
 *  0b110..Ranging sequence manager lcl_rx_trigger
 */
#define XCVR_MISC_LCL_RX_CFG1_RX_ANT_TRIG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_RX_CFG1_RX_ANT_TRIG_SEL_SHIFT)) & XCVR_MISC_LCL_RX_CFG1_RX_ANT_TRIG_SEL_MASK)

#define XCVR_MISC_LCL_RX_CFG1_RX_LO_PER_MASK     (0x1F000U)
#define XCVR_MISC_LCL_RX_CFG1_RX_LO_PER_SHIFT    (12U)
/*! RX_LO_PER - Primary Number of intervals for antenna LOW
 */
#define XCVR_MISC_LCL_RX_CFG1_RX_LO_PER(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_RX_CFG1_RX_LO_PER_SHIFT)) & XCVR_MISC_LCL_RX_CFG1_RX_LO_PER_MASK)

#define XCVR_MISC_LCL_RX_CFG1_RX_HI_PER_MASK     (0x3E0000U)
#define XCVR_MISC_LCL_RX_CFG1_RX_HI_PER_SHIFT    (17U)
/*! RX_HI_PER - Primary Number of intervals for antenna HIGH
 */
#define XCVR_MISC_LCL_RX_CFG1_RX_HI_PER(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_RX_CFG1_RX_HI_PER_SHIFT)) & XCVR_MISC_LCL_RX_CFG1_RX_HI_PER_MASK)

#define XCVR_MISC_LCL_RX_CFG1_RX_LO_PER_1_MASK   (0x7C00000U)
#define XCVR_MISC_LCL_RX_CFG1_RX_LO_PER_1_SHIFT  (22U)
/*! RX_LO_PER_1 - Alternate Number of intervals for antenna LOW. Used only in conjunction with RSM.
 */
#define XCVR_MISC_LCL_RX_CFG1_RX_LO_PER_1(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_RX_CFG1_RX_LO_PER_1_SHIFT)) & XCVR_MISC_LCL_RX_CFG1_RX_LO_PER_1_MASK)

#define XCVR_MISC_LCL_RX_CFG1_RX_HI_PER_1_MASK   (0xF8000000U)
#define XCVR_MISC_LCL_RX_CFG1_RX_HI_PER_1_SHIFT  (27U)
/*! RX_HI_PER_1 - Alternate Number of intervals for antenna HIGH. Used only in conjunction with RSM.
 */
#define XCVR_MISC_LCL_RX_CFG1_RX_HI_PER_1(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_RX_CFG1_RX_HI_PER_1_SHIFT)) & XCVR_MISC_LCL_RX_CFG1_RX_HI_PER_1_MASK)
/*! @} */

/*! @name LCL_RX_CFG2 - LCL CTRL RX CONFIG2 */
/*! @{ */

#define XCVR_MISC_LCL_RX_CFG2_RX_LO_PER_2_MASK   (0x1F000U)
#define XCVR_MISC_LCL_RX_CFG2_RX_LO_PER_2_SHIFT  (12U)
/*! RX_LO_PER_2 - Alternate Number of intervals for antenna LOW. Used only in conjunction with RSM.
 */
#define XCVR_MISC_LCL_RX_CFG2_RX_LO_PER_2(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_RX_CFG2_RX_LO_PER_2_SHIFT)) & XCVR_MISC_LCL_RX_CFG2_RX_LO_PER_2_MASK)

#define XCVR_MISC_LCL_RX_CFG2_RX_HI_PER_2_MASK   (0x3E0000U)
#define XCVR_MISC_LCL_RX_CFG2_RX_HI_PER_2_SHIFT  (17U)
/*! RX_HI_PER_2 - Alternate Number of intervals for antenna HIGH. Used only in conjunction with RSM.
 */
#define XCVR_MISC_LCL_RX_CFG2_RX_HI_PER_2(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_RX_CFG2_RX_HI_PER_2_SHIFT)) & XCVR_MISC_LCL_RX_CFG2_RX_HI_PER_2_MASK)

#define XCVR_MISC_LCL_RX_CFG2_RX_LO_PER_3_MASK   (0x7C00000U)
#define XCVR_MISC_LCL_RX_CFG2_RX_LO_PER_3_SHIFT  (22U)
/*! RX_LO_PER_3 - Alternate Number of intervals for antenna LOW. Used only in conjunction with RSM.
 */
#define XCVR_MISC_LCL_RX_CFG2_RX_LO_PER_3(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_RX_CFG2_RX_LO_PER_3_SHIFT)) & XCVR_MISC_LCL_RX_CFG2_RX_LO_PER_3_MASK)

#define XCVR_MISC_LCL_RX_CFG2_RX_HI_PER_3_MASK   (0xF8000000U)
#define XCVR_MISC_LCL_RX_CFG2_RX_HI_PER_3_SHIFT  (27U)
/*! RX_HI_PER_3 - Alternate Number of intervals for antenna HIGH. Used only in conjunction with RSM.
 */
#define XCVR_MISC_LCL_RX_CFG2_RX_HI_PER_3(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_RX_CFG2_RX_HI_PER_3_SHIFT)) & XCVR_MISC_LCL_RX_CFG2_RX_HI_PER_3_MASK)
/*! @} */

/*! @name LCL_PM_MSB - LCL CTRL PM MSB */
/*! @{ */

#define XCVR_MISC_LCL_PM_MSB_COMP_PATTERN_MSB_MASK (0xFFFFFFFFU)
#define XCVR_MISC_LCL_PM_MSB_COMP_PATTERN_MSB_SHIFT (0U)
/*! COMP_PATTERN_MSB - Upper bytes of pattern to be matched, bits 63:32
 */
#define XCVR_MISC_LCL_PM_MSB_COMP_PATTERN_MSB(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_PM_MSB_COMP_PATTERN_MSB_SHIFT)) & XCVR_MISC_LCL_PM_MSB_COMP_PATTERN_MSB_MASK)
/*! @} */

/*! @name LCL_PM_LSB - LCL CTRL PM LSB */
/*! @{ */

#define XCVR_MISC_LCL_PM_LSB_COMP_PATTERN_LSB_MASK (0xFFFFFFFFU)
#define XCVR_MISC_LCL_PM_LSB_COMP_PATTERN_LSB_SHIFT (0U)
/*! COMP_PATTERN_LSB - Lower bytes of pattern to be matched, bits 31:0
 */
#define XCVR_MISC_LCL_PM_LSB_COMP_PATTERN_LSB(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_PM_LSB_COMP_PATTERN_LSB_SHIFT)) & XCVR_MISC_LCL_PM_LSB_COMP_PATTERN_LSB_MASK)
/*! @} */

/*! @name LCL_GPIO_CTRL0 - LCL GPIO CTRL 0 */
/*! @{ */

#define XCVR_MISC_LCL_GPIO_CTRL0_LUT_0_MASK      (0xFU)
#define XCVR_MISC_LCL_GPIO_CTRL0_LUT_0_SHIFT     (0U)
/*! LUT_0 - GPIO antenna state LUT entry
 */
#define XCVR_MISC_LCL_GPIO_CTRL0_LUT_0(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_GPIO_CTRL0_LUT_0_SHIFT)) & XCVR_MISC_LCL_GPIO_CTRL0_LUT_0_MASK)

#define XCVR_MISC_LCL_GPIO_CTRL0_LUT_1_MASK      (0xF0U)
#define XCVR_MISC_LCL_GPIO_CTRL0_LUT_1_SHIFT     (4U)
/*! LUT_1 - GPIO antenna state LUT entry
 */
#define XCVR_MISC_LCL_GPIO_CTRL0_LUT_1(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_GPIO_CTRL0_LUT_1_SHIFT)) & XCVR_MISC_LCL_GPIO_CTRL0_LUT_1_MASK)

#define XCVR_MISC_LCL_GPIO_CTRL0_LUT_2_MASK      (0xF00U)
#define XCVR_MISC_LCL_GPIO_CTRL0_LUT_2_SHIFT     (8U)
/*! LUT_2 - GPIO antenna state LUT entry
 */
#define XCVR_MISC_LCL_GPIO_CTRL0_LUT_2(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_GPIO_CTRL0_LUT_2_SHIFT)) & XCVR_MISC_LCL_GPIO_CTRL0_LUT_2_MASK)

#define XCVR_MISC_LCL_GPIO_CTRL0_LUT_3_MASK      (0xF000U)
#define XCVR_MISC_LCL_GPIO_CTRL0_LUT_3_SHIFT     (12U)
/*! LUT_3 - GPIO antenna state LUT entry
 */
#define XCVR_MISC_LCL_GPIO_CTRL0_LUT_3(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_GPIO_CTRL0_LUT_3_SHIFT)) & XCVR_MISC_LCL_GPIO_CTRL0_LUT_3_MASK)

#define XCVR_MISC_LCL_GPIO_CTRL0_LUT_4_MASK      (0xF0000U)
#define XCVR_MISC_LCL_GPIO_CTRL0_LUT_4_SHIFT     (16U)
/*! LUT_4 - GPIO antenna state LUT entry
 */
#define XCVR_MISC_LCL_GPIO_CTRL0_LUT_4(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_GPIO_CTRL0_LUT_4_SHIFT)) & XCVR_MISC_LCL_GPIO_CTRL0_LUT_4_MASK)

#define XCVR_MISC_LCL_GPIO_CTRL0_LUT_5_MASK      (0xF00000U)
#define XCVR_MISC_LCL_GPIO_CTRL0_LUT_5_SHIFT     (20U)
/*! LUT_5 - GPIO antenna state LUT entry
 */
#define XCVR_MISC_LCL_GPIO_CTRL0_LUT_5(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_GPIO_CTRL0_LUT_5_SHIFT)) & XCVR_MISC_LCL_GPIO_CTRL0_LUT_5_MASK)

#define XCVR_MISC_LCL_GPIO_CTRL0_LUT_6_MASK      (0xF000000U)
#define XCVR_MISC_LCL_GPIO_CTRL0_LUT_6_SHIFT     (24U)
/*! LUT_6 - GPIO antenna state LUT entry
 */
#define XCVR_MISC_LCL_GPIO_CTRL0_LUT_6(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_GPIO_CTRL0_LUT_6_SHIFT)) & XCVR_MISC_LCL_GPIO_CTRL0_LUT_6_MASK)

#define XCVR_MISC_LCL_GPIO_CTRL0_LUT_7_MASK      (0xF0000000U)
#define XCVR_MISC_LCL_GPIO_CTRL0_LUT_7_SHIFT     (28U)
/*! LUT_7 - GPIO antenna state LUT entry
 */
#define XCVR_MISC_LCL_GPIO_CTRL0_LUT_7(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_GPIO_CTRL0_LUT_7_SHIFT)) & XCVR_MISC_LCL_GPIO_CTRL0_LUT_7_MASK)
/*! @} */

/*! @name LCL_GPIO_CTRL1 - LCL GPIO CTRL 1 */
/*! @{ */

#define XCVR_MISC_LCL_GPIO_CTRL1_LUT_8_MASK      (0xFU)
#define XCVR_MISC_LCL_GPIO_CTRL1_LUT_8_SHIFT     (0U)
/*! LUT_8 - GPIO antenna state LUT entry
 */
#define XCVR_MISC_LCL_GPIO_CTRL1_LUT_8(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_GPIO_CTRL1_LUT_8_SHIFT)) & XCVR_MISC_LCL_GPIO_CTRL1_LUT_8_MASK)

#define XCVR_MISC_LCL_GPIO_CTRL1_LUT_9_MASK      (0xF0U)
#define XCVR_MISC_LCL_GPIO_CTRL1_LUT_9_SHIFT     (4U)
/*! LUT_9 - GPIO antenna state LUT entry
 */
#define XCVR_MISC_LCL_GPIO_CTRL1_LUT_9(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_GPIO_CTRL1_LUT_9_SHIFT)) & XCVR_MISC_LCL_GPIO_CTRL1_LUT_9_MASK)

#define XCVR_MISC_LCL_GPIO_CTRL1_LUT_10_MASK     (0xF00U)
#define XCVR_MISC_LCL_GPIO_CTRL1_LUT_10_SHIFT    (8U)
/*! LUT_10 - GPIO antenna state LUT entry
 */
#define XCVR_MISC_LCL_GPIO_CTRL1_LUT_10(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_GPIO_CTRL1_LUT_10_SHIFT)) & XCVR_MISC_LCL_GPIO_CTRL1_LUT_10_MASK)

#define XCVR_MISC_LCL_GPIO_CTRL1_LUT_11_MASK     (0xF000U)
#define XCVR_MISC_LCL_GPIO_CTRL1_LUT_11_SHIFT    (12U)
/*! LUT_11 - GPIO antenna state LUT entry
 */
#define XCVR_MISC_LCL_GPIO_CTRL1_LUT_11(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_GPIO_CTRL1_LUT_11_SHIFT)) & XCVR_MISC_LCL_GPIO_CTRL1_LUT_11_MASK)

#define XCVR_MISC_LCL_GPIO_CTRL1_LUT_12_MASK     (0xF0000U)
#define XCVR_MISC_LCL_GPIO_CTRL1_LUT_12_SHIFT    (16U)
/*! LUT_12 - GPIO antenna state LUT entry
 */
#define XCVR_MISC_LCL_GPIO_CTRL1_LUT_12(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_GPIO_CTRL1_LUT_12_SHIFT)) & XCVR_MISC_LCL_GPIO_CTRL1_LUT_12_MASK)

#define XCVR_MISC_LCL_GPIO_CTRL1_LUT_13_MASK     (0xF00000U)
#define XCVR_MISC_LCL_GPIO_CTRL1_LUT_13_SHIFT    (20U)
/*! LUT_13 - GPIO antenna state LUT entry
 */
#define XCVR_MISC_LCL_GPIO_CTRL1_LUT_13(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_GPIO_CTRL1_LUT_13_SHIFT)) & XCVR_MISC_LCL_GPIO_CTRL1_LUT_13_MASK)

#define XCVR_MISC_LCL_GPIO_CTRL1_LUT_14_MASK     (0xF000000U)
#define XCVR_MISC_LCL_GPIO_CTRL1_LUT_14_SHIFT    (24U)
/*! LUT_14 - GPIO antenna state LUT entry
 */
#define XCVR_MISC_LCL_GPIO_CTRL1_LUT_14(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_GPIO_CTRL1_LUT_14_SHIFT)) & XCVR_MISC_LCL_GPIO_CTRL1_LUT_14_MASK)

#define XCVR_MISC_LCL_GPIO_CTRL1_LUT_15_MASK     (0xF0000000U)
#define XCVR_MISC_LCL_GPIO_CTRL1_LUT_15_SHIFT    (28U)
/*! LUT_15 - GPIO antenna state LUT entry
 */
#define XCVR_MISC_LCL_GPIO_CTRL1_LUT_15(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_GPIO_CTRL1_LUT_15_SHIFT)) & XCVR_MISC_LCL_GPIO_CTRL1_LUT_15_MASK)
/*! @} */

/*! @name LCL_GPIO_CTRL2 - LCL GPIO CTRL 2 */
/*! @{ */

#define XCVR_MISC_LCL_GPIO_CTRL2_LUT_16_MASK     (0xFU)
#define XCVR_MISC_LCL_GPIO_CTRL2_LUT_16_SHIFT    (0U)
/*! LUT_16 - GPIO antenna state LUT entry
 */
#define XCVR_MISC_LCL_GPIO_CTRL2_LUT_16(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_GPIO_CTRL2_LUT_16_SHIFT)) & XCVR_MISC_LCL_GPIO_CTRL2_LUT_16_MASK)

#define XCVR_MISC_LCL_GPIO_CTRL2_LUT_17_MASK     (0xF0U)
#define XCVR_MISC_LCL_GPIO_CTRL2_LUT_17_SHIFT    (4U)
/*! LUT_17 - GPIO antenna state LUT entry
 */
#define XCVR_MISC_LCL_GPIO_CTRL2_LUT_17(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_GPIO_CTRL2_LUT_17_SHIFT)) & XCVR_MISC_LCL_GPIO_CTRL2_LUT_17_MASK)

#define XCVR_MISC_LCL_GPIO_CTRL2_LUT_18_MASK     (0xF00U)
#define XCVR_MISC_LCL_GPIO_CTRL2_LUT_18_SHIFT    (8U)
/*! LUT_18 - GPIO antenna state LUT entry
 */
#define XCVR_MISC_LCL_GPIO_CTRL2_LUT_18(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_GPIO_CTRL2_LUT_18_SHIFT)) & XCVR_MISC_LCL_GPIO_CTRL2_LUT_18_MASK)

#define XCVR_MISC_LCL_GPIO_CTRL2_LUT_19_MASK     (0xF000U)
#define XCVR_MISC_LCL_GPIO_CTRL2_LUT_19_SHIFT    (12U)
/*! LUT_19 - GPIO antenna state LUT entry
 */
#define XCVR_MISC_LCL_GPIO_CTRL2_LUT_19(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_GPIO_CTRL2_LUT_19_SHIFT)) & XCVR_MISC_LCL_GPIO_CTRL2_LUT_19_MASK)

#define XCVR_MISC_LCL_GPIO_CTRL2_LUT_20_MASK     (0xF0000U)
#define XCVR_MISC_LCL_GPIO_CTRL2_LUT_20_SHIFT    (16U)
/*! LUT_20 - GPIO antenna state LUT entry
 */
#define XCVR_MISC_LCL_GPIO_CTRL2_LUT_20(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_GPIO_CTRL2_LUT_20_SHIFT)) & XCVR_MISC_LCL_GPIO_CTRL2_LUT_20_MASK)

#define XCVR_MISC_LCL_GPIO_CTRL2_LUT_21_MASK     (0xF00000U)
#define XCVR_MISC_LCL_GPIO_CTRL2_LUT_21_SHIFT    (20U)
/*! LUT_21 - GPIO antenna state LUT entry
 */
#define XCVR_MISC_LCL_GPIO_CTRL2_LUT_21(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_GPIO_CTRL2_LUT_21_SHIFT)) & XCVR_MISC_LCL_GPIO_CTRL2_LUT_21_MASK)

#define XCVR_MISC_LCL_GPIO_CTRL2_LUT_22_MASK     (0xF000000U)
#define XCVR_MISC_LCL_GPIO_CTRL2_LUT_22_SHIFT    (24U)
/*! LUT_22 - GPIO antenna state LUT entry
 */
#define XCVR_MISC_LCL_GPIO_CTRL2_LUT_22(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_GPIO_CTRL2_LUT_22_SHIFT)) & XCVR_MISC_LCL_GPIO_CTRL2_LUT_22_MASK)

#define XCVR_MISC_LCL_GPIO_CTRL2_LUT_23_MASK     (0xF0000000U)
#define XCVR_MISC_LCL_GPIO_CTRL2_LUT_23_SHIFT    (28U)
/*! LUT_23 - GPIO antenna state LUT entry
 */
#define XCVR_MISC_LCL_GPIO_CTRL2_LUT_23(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_GPIO_CTRL2_LUT_23_SHIFT)) & XCVR_MISC_LCL_GPIO_CTRL2_LUT_23_MASK)
/*! @} */

/*! @name LCL_GPIO_CTRL3 - LCL GPIO CTRL 3 */
/*! @{ */

#define XCVR_MISC_LCL_GPIO_CTRL3_LUT_24_MASK     (0xFU)
#define XCVR_MISC_LCL_GPIO_CTRL3_LUT_24_SHIFT    (0U)
/*! LUT_24 - GPIO antenna state LUT entry
 */
#define XCVR_MISC_LCL_GPIO_CTRL3_LUT_24(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_GPIO_CTRL3_LUT_24_SHIFT)) & XCVR_MISC_LCL_GPIO_CTRL3_LUT_24_MASK)

#define XCVR_MISC_LCL_GPIO_CTRL3_LUT_25_MASK     (0xF0U)
#define XCVR_MISC_LCL_GPIO_CTRL3_LUT_25_SHIFT    (4U)
/*! LUT_25 - GPIO antenna state LUT entry
 */
#define XCVR_MISC_LCL_GPIO_CTRL3_LUT_25(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_GPIO_CTRL3_LUT_25_SHIFT)) & XCVR_MISC_LCL_GPIO_CTRL3_LUT_25_MASK)

#define XCVR_MISC_LCL_GPIO_CTRL3_LUT_26_MASK     (0xF00U)
#define XCVR_MISC_LCL_GPIO_CTRL3_LUT_26_SHIFT    (8U)
/*! LUT_26 - GPIO antenna state LUT entry
 */
#define XCVR_MISC_LCL_GPIO_CTRL3_LUT_26(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_GPIO_CTRL3_LUT_26_SHIFT)) & XCVR_MISC_LCL_GPIO_CTRL3_LUT_26_MASK)

#define XCVR_MISC_LCL_GPIO_CTRL3_LUT_27_MASK     (0xF000U)
#define XCVR_MISC_LCL_GPIO_CTRL3_LUT_27_SHIFT    (12U)
/*! LUT_27 - GPIO antenna state LUT entry
 */
#define XCVR_MISC_LCL_GPIO_CTRL3_LUT_27(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_GPIO_CTRL3_LUT_27_SHIFT)) & XCVR_MISC_LCL_GPIO_CTRL3_LUT_27_MASK)

#define XCVR_MISC_LCL_GPIO_CTRL3_LUT_28_MASK     (0xF0000U)
#define XCVR_MISC_LCL_GPIO_CTRL3_LUT_28_SHIFT    (16U)
/*! LUT_28 - GPIO antenna state LUT entry
 */
#define XCVR_MISC_LCL_GPIO_CTRL3_LUT_28(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_GPIO_CTRL3_LUT_28_SHIFT)) & XCVR_MISC_LCL_GPIO_CTRL3_LUT_28_MASK)

#define XCVR_MISC_LCL_GPIO_CTRL3_LUT_29_MASK     (0xF00000U)
#define XCVR_MISC_LCL_GPIO_CTRL3_LUT_29_SHIFT    (20U)
/*! LUT_29 - GPIO antenna state LUT entry
 */
#define XCVR_MISC_LCL_GPIO_CTRL3_LUT_29(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_GPIO_CTRL3_LUT_29_SHIFT)) & XCVR_MISC_LCL_GPIO_CTRL3_LUT_29_MASK)

#define XCVR_MISC_LCL_GPIO_CTRL3_LUT_30_MASK     (0xF000000U)
#define XCVR_MISC_LCL_GPIO_CTRL3_LUT_30_SHIFT    (24U)
/*! LUT_30 - GPIO antenna state LUT entry
 */
#define XCVR_MISC_LCL_GPIO_CTRL3_LUT_30(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_GPIO_CTRL3_LUT_30_SHIFT)) & XCVR_MISC_LCL_GPIO_CTRL3_LUT_30_MASK)

#define XCVR_MISC_LCL_GPIO_CTRL3_LUT_31_MASK     (0xF0000000U)
#define XCVR_MISC_LCL_GPIO_CTRL3_LUT_31_SHIFT    (28U)
/*! LUT_31 - GPIO antenna state LUT entry
 */
#define XCVR_MISC_LCL_GPIO_CTRL3_LUT_31(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_GPIO_CTRL3_LUT_31_SHIFT)) & XCVR_MISC_LCL_GPIO_CTRL3_LUT_31_MASK)
/*! @} */

/*! @name LCL_GPIO_CTRL4 - LCL GPIO CTRL 4 */
/*! @{ */

#define XCVR_MISC_LCL_GPIO_CTRL4_LUT_WRAP_PTR_MASK (0x1FU)
#define XCVR_MISC_LCL_GPIO_CTRL4_LUT_WRAP_PTR_SHIFT (0U)
/*! LUT_WRAP_PTR - Wrap point for the LUT table in generating the 4 antenna GPIO wire states.
 */
#define XCVR_MISC_LCL_GPIO_CTRL4_LUT_WRAP_PTR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_GPIO_CTRL4_LUT_WRAP_PTR_SHIFT)) & XCVR_MISC_LCL_GPIO_CTRL4_LUT_WRAP_PTR_MASK)
/*! @} */

/*! @name LCL_DMA_MASK_DELAY - LCL_DMA_MASK_DELAY */
/*! @{ */

#define XCVR_MISC_LCL_DMA_MASK_DELAY_DMA_MASK_DELAY_OFF_MASK (0x1FU)
#define XCVR_MISC_LCL_DMA_MASK_DELAY_DMA_MASK_DELAY_OFF_SHIFT (0U)
/*! DMA_MASK_DELAY_OFF - DMA_MASK_DELAY_OFF
 */
#define XCVR_MISC_LCL_DMA_MASK_DELAY_DMA_MASK_DELAY_OFF(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_DMA_MASK_DELAY_DMA_MASK_DELAY_OFF_SHIFT)) & XCVR_MISC_LCL_DMA_MASK_DELAY_DMA_MASK_DELAY_OFF_MASK)

#define XCVR_MISC_LCL_DMA_MASK_DELAY_DMA_MASK_DELAY_MASK (0xFFE0U)
#define XCVR_MISC_LCL_DMA_MASK_DELAY_DMA_MASK_DELAY_SHIFT (5U)
/*! DMA_MASK_DELAY - DMA_MASK_DELAY
 */
#define XCVR_MISC_LCL_DMA_MASK_DELAY_DMA_MASK_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_DMA_MASK_DELAY_DMA_MASK_DELAY_SHIFT)) & XCVR_MISC_LCL_DMA_MASK_DELAY_DMA_MASK_DELAY_MASK)
/*! @} */

/*! @name LCL_DMA_MASK_PERIOD - LCL_DMA_MASK_PERIOD */
/*! @{ */

#define XCVR_MISC_LCL_DMA_MASK_PERIOD_DMA_MASK_REF_PER_MASK (0x1FU)
#define XCVR_MISC_LCL_DMA_MASK_PERIOD_DMA_MASK_REF_PER_SHIFT (0U)
/*! DMA_MASK_REF_PER - DMA_MASK_REF_PER
 */
#define XCVR_MISC_LCL_DMA_MASK_PERIOD_DMA_MASK_REF_PER(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_LCL_DMA_MASK_PERIOD_DMA_MASK_REF_PER_SHIFT)) & XCVR_MISC_LCL_DMA_MASK_PERIOD_DMA_MASK_REF_PER_MASK)
/*! @} */

/*! @name RSM_CSR - Ranging Sequence Manager Control and Status */
/*! @{ */

#define XCVR_MISC_RSM_CSR_RSM_IRQ_IP1_EN_MASK    (0x1U)
#define XCVR_MISC_RSM_CSR_RSM_IRQ_IP1_EN_SHIFT   (0U)
/*! RSM_IRQ_IP1_EN - RSM_IRQ_IP1_EN
 */
#define XCVR_MISC_RSM_CSR_RSM_IRQ_IP1_EN(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CSR_RSM_IRQ_IP1_EN_SHIFT)) & XCVR_MISC_RSM_CSR_RSM_IRQ_IP1_EN_MASK)

#define XCVR_MISC_RSM_CSR_RSM_IRQ_IP1_MASK       (0x2U)
#define XCVR_MISC_RSM_CSR_RSM_IRQ_IP1_SHIFT      (1U)
/*! RSM_IRQ_IP1 - RSM_IRQ_IP1 Flag
 */
#define XCVR_MISC_RSM_CSR_RSM_IRQ_IP1(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CSR_RSM_IRQ_IP1_SHIFT)) & XCVR_MISC_RSM_CSR_RSM_IRQ_IP1_MASK)

#define XCVR_MISC_RSM_CSR_RSM_IRQ_IP2_EN_MASK    (0x4U)
#define XCVR_MISC_RSM_CSR_RSM_IRQ_IP2_EN_SHIFT   (2U)
/*! RSM_IRQ_IP2_EN - RSM_IRQ_IP2_EN
 */
#define XCVR_MISC_RSM_CSR_RSM_IRQ_IP2_EN(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CSR_RSM_IRQ_IP2_EN_SHIFT)) & XCVR_MISC_RSM_CSR_RSM_IRQ_IP2_EN_MASK)

#define XCVR_MISC_RSM_CSR_RSM_IRQ_IP2_MASK       (0x8U)
#define XCVR_MISC_RSM_CSR_RSM_IRQ_IP2_SHIFT      (3U)
/*! RSM_IRQ_IP2 - RSM_IRQ_IP2 Flag
 */
#define XCVR_MISC_RSM_CSR_RSM_IRQ_IP2(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CSR_RSM_IRQ_IP2_SHIFT)) & XCVR_MISC_RSM_CSR_RSM_IRQ_IP2_MASK)

#define XCVR_MISC_RSM_CSR_RSM_IRQ_FC_EN_MASK     (0x10U)
#define XCVR_MISC_RSM_CSR_RSM_IRQ_FC_EN_SHIFT    (4U)
/*! RSM_IRQ_FC_EN - RSM_IRQ_FC_EN
 */
#define XCVR_MISC_RSM_CSR_RSM_IRQ_FC_EN(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CSR_RSM_IRQ_FC_EN_SHIFT)) & XCVR_MISC_RSM_CSR_RSM_IRQ_FC_EN_MASK)

#define XCVR_MISC_RSM_CSR_RSM_IRQ_FC_MASK        (0x20U)
#define XCVR_MISC_RSM_CSR_RSM_IRQ_FC_SHIFT       (5U)
/*! RSM_IRQ_FC - RSM_IRQ_FC Flag
 */
#define XCVR_MISC_RSM_CSR_RSM_IRQ_FC(x)          (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CSR_RSM_IRQ_FC_SHIFT)) & XCVR_MISC_RSM_CSR_RSM_IRQ_FC_MASK)

#define XCVR_MISC_RSM_CSR_RSM_IRQ_EOS_EN_MASK    (0x40U)
#define XCVR_MISC_RSM_CSR_RSM_IRQ_EOS_EN_SHIFT   (6U)
/*! RSM_IRQ_EOS_EN - RSM_IRQ_EOS_EN
 */
#define XCVR_MISC_RSM_CSR_RSM_IRQ_EOS_EN(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CSR_RSM_IRQ_EOS_EN_SHIFT)) & XCVR_MISC_RSM_CSR_RSM_IRQ_EOS_EN_MASK)

#define XCVR_MISC_RSM_CSR_RSM_IRQ_EOS_MASK       (0x80U)
#define XCVR_MISC_RSM_CSR_RSM_IRQ_EOS_SHIFT      (7U)
/*! RSM_IRQ_EOS - RSM_IRQ_EOS Flag
 */
#define XCVR_MISC_RSM_CSR_RSM_IRQ_EOS(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CSR_RSM_IRQ_EOS_SHIFT)) & XCVR_MISC_RSM_CSR_RSM_IRQ_EOS_MASK)

#define XCVR_MISC_RSM_CSR_RSM_IRQ_ABORT_EN_MASK  (0x100U)
#define XCVR_MISC_RSM_CSR_RSM_IRQ_ABORT_EN_SHIFT (8U)
/*! RSM_IRQ_ABORT_EN - RSM_IRQ_ABORT_EN
 */
#define XCVR_MISC_RSM_CSR_RSM_IRQ_ABORT_EN(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CSR_RSM_IRQ_ABORT_EN_SHIFT)) & XCVR_MISC_RSM_CSR_RSM_IRQ_ABORT_EN_MASK)

#define XCVR_MISC_RSM_CSR_RSM_IRQ_ABORT_MASK     (0x200U)
#define XCVR_MISC_RSM_CSR_RSM_IRQ_ABORT_SHIFT    (9U)
/*! RSM_IRQ_ABORT - RSM_IRQ_ABORT Flag
 */
#define XCVR_MISC_RSM_CSR_RSM_IRQ_ABORT(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CSR_RSM_IRQ_ABORT_SHIFT)) & XCVR_MISC_RSM_CSR_RSM_IRQ_ABORT_MASK)

#define XCVR_MISC_RSM_CSR_RSM_STATE_MASK         (0x1F0000U)
#define XCVR_MISC_RSM_CSR_RSM_STATE_SHIFT        (16U)
/*! RSM_STATE - RSM_STATE
 *  0b00000..IDLE
 *  0b00001..DELAY. Used only for the trigger delay in SQTE
 *  0b00010..EXT_TX (Extend TX). Used only for PDE
 *  0b00011..EXT_RX (Extend RX). Used only for PDE
 *  0b00100..WU (Warmup). Used only for SQTE
 *  0b00101..DT_TX (Packet TX). Used only for SQTE
 *  0b00110..DT_RX (Packet RX). Used only for SQTE
 *  0b00111..DT_RX_SYNC (Packet RX Sync). Used only for SQTE
 *  0b01000..FM_TX (Frequency Measurement TX). Used only for SQTE
 *  0b01001..FM_RX (Frequency Measurement RX). Used only for SQTE
 *  0b01010..PM_TX (Phase Measurement TX).
 *  0b01011..PM_RX (Phase Measurement RX).
 *  0b01100..IP1_RX2TX (Interlude Period 1 RX2TX). Used only for SQTE
 *  0b01101..IP1_TX2RX (Interlude Period 1 TX2RX). Used only for SQTE
 *  0b01110..S_RX2RX (Short Period RX2RX). Used only for SQTE
 *  0b01111..S_TX2TX (Short Period TX2TX). Used only for SQTE
 *  0b10000..IP2_RX2TX (Interlude Period 2 RX2TX).
 *  0b10001..IP2_TX2RX (Interlude Period 2 TX2RX).
 *  0b10010..FC_RX2TX (Frequency Change RX2TX).
 *  0b10011..FC_TX2RX (Frequency Change TX2RX).
 *  0b10100..WD (Warmdown)
 */
#define XCVR_MISC_RSM_CSR_RSM_STATE(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CSR_RSM_STATE_SHIFT)) & XCVR_MISC_RSM_CSR_RSM_STATE_MASK)

#define XCVR_MISC_RSM_CSR_RSM_STEP_FORMAT_MASK   (0x600000U)
#define XCVR_MISC_RSM_CSR_RSM_STEP_FORMAT_SHIFT  (21U)
/*! RSM_STEP_FORMAT - RSM_STEP_FORMAT
 */
#define XCVR_MISC_RSM_CSR_RSM_STEP_FORMAT(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CSR_RSM_STEP_FORMAT_SHIFT)) & XCVR_MISC_RSM_CSR_RSM_STEP_FORMAT_MASK)

#define XCVR_MISC_RSM_CSR_RSM_CURRENT_STEPS_MASK (0xFF000000U)
#define XCVR_MISC_RSM_CSR_RSM_CURRENT_STEPS_SHIFT (24U)
/*! RSM_CURRENT_STEPS - RSM_CURRENT_STEPS
 */
#define XCVR_MISC_RSM_CSR_RSM_CURRENT_STEPS(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CSR_RSM_CURRENT_STEPS_SHIFT)) & XCVR_MISC_RSM_CSR_RSM_CURRENT_STEPS_MASK)
/*! @} */

/*! @name RSM_CTRL0 - Ranging Sequence Manager Control */
/*! @{ */

#define XCVR_MISC_RSM_CTRL0_RSM_MODE_MASK        (0x1U)
#define XCVR_MISC_RSM_CTRL0_RSM_MODE_SHIFT       (0U)
/*! RSM_MODE - RSM_MODE
 *  0b0..SQTE
 *  0b1..PDE
 */
#define XCVR_MISC_RSM_CTRL0_RSM_MODE(x)          (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CTRL0_RSM_MODE_SHIFT)) & XCVR_MISC_RSM_CTRL0_RSM_MODE_MASK)

#define XCVR_MISC_RSM_CTRL0_RSM_RATE_MASK        (0x2U)
#define XCVR_MISC_RSM_CTRL0_RSM_RATE_SHIFT       (1U)
/*! RSM_RATE - RSM_RATE
 *  0b0..1Mbps
 *  0b1..2Mbps
 */
#define XCVR_MISC_RSM_CTRL0_RSM_RATE(x)          (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CTRL0_RSM_RATE_SHIFT)) & XCVR_MISC_RSM_CTRL0_RSM_RATE_MASK)

#define XCVR_MISC_RSM_CTRL0_RSM_RX_EN_MASK       (0x4U)
#define XCVR_MISC_RSM_CTRL0_RSM_RX_EN_SHIFT      (2U)
/*! RSM_RX_EN - RSM_RX_EN
 */
#define XCVR_MISC_RSM_CTRL0_RSM_RX_EN(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CTRL0_RSM_RX_EN_SHIFT)) & XCVR_MISC_RSM_CTRL0_RSM_RX_EN_MASK)

#define XCVR_MISC_RSM_CTRL0_RSM_TX_EN_MASK       (0x8U)
#define XCVR_MISC_RSM_CTRL0_RSM_TX_EN_SHIFT      (3U)
/*! RSM_TX_EN - RSM_TX_EN
 */
#define XCVR_MISC_RSM_CTRL0_RSM_TX_EN(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CTRL0_RSM_TX_EN_SHIFT)) & XCVR_MISC_RSM_CTRL0_RSM_TX_EN_MASK)

#define XCVR_MISC_RSM_CTRL0_RSM_FAST_IP_RX_WU_MASK (0x10U)
#define XCVR_MISC_RSM_CTRL0_RSM_FAST_IP_RX_WU_SHIFT (4U)
/*! RSM_FAST_IP_RX_WU - RSM_FAST_IP_RX_WU
 */
#define XCVR_MISC_RSM_CTRL0_RSM_FAST_IP_RX_WU(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CTRL0_RSM_FAST_IP_RX_WU_SHIFT)) & XCVR_MISC_RSM_CTRL0_RSM_FAST_IP_RX_WU_MASK)

#define XCVR_MISC_RSM_CTRL0_RSM_FAST_IP_TX_WU_MASK (0x20U)
#define XCVR_MISC_RSM_CTRL0_RSM_FAST_IP_TX_WU_SHIFT (5U)
/*! RSM_FAST_IP_TX_WU - RSM_FAST_IP_TX_WU
 */
#define XCVR_MISC_RSM_CTRL0_RSM_FAST_IP_TX_WU(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CTRL0_RSM_FAST_IP_TX_WU_SHIFT)) & XCVR_MISC_RSM_CTRL0_RSM_FAST_IP_TX_WU_MASK)

#define XCVR_MISC_RSM_CTRL0_RSM_FAST_FC_RX_WU_MASK (0x40U)
#define XCVR_MISC_RSM_CTRL0_RSM_FAST_FC_RX_WU_SHIFT (6U)
/*! RSM_FAST_FC_RX_WU - RSM_FAST_FC_RX_WU
 */
#define XCVR_MISC_RSM_CTRL0_RSM_FAST_FC_RX_WU(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CTRL0_RSM_FAST_FC_RX_WU_SHIFT)) & XCVR_MISC_RSM_CTRL0_RSM_FAST_FC_RX_WU_MASK)

#define XCVR_MISC_RSM_CTRL0_RSM_FAST_FC_TX_WU_MASK (0x80U)
#define XCVR_MISC_RSM_CTRL0_RSM_FAST_FC_TX_WU_SHIFT (7U)
/*! RSM_FAST_FC_TX_WU - RSM_FAST_FC_TX_WU
 */
#define XCVR_MISC_RSM_CTRL0_RSM_FAST_FC_TX_WU(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CTRL0_RSM_FAST_FC_TX_WU_SHIFT)) & XCVR_MISC_RSM_CTRL0_RSM_FAST_FC_TX_WU_MASK)

#define XCVR_MISC_RSM_CTRL0_RSM_SW_ABORT_MASK    (0x100U)
#define XCVR_MISC_RSM_CTRL0_RSM_SW_ABORT_SHIFT   (8U)
/*! RSM_SW_ABORT - RSM_SW_ABORT
 */
#define XCVR_MISC_RSM_CTRL0_RSM_SW_ABORT(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CTRL0_RSM_SW_ABORT_SHIFT)) & XCVR_MISC_RSM_CTRL0_RSM_SW_ABORT_MASK)

#define XCVR_MISC_RSM_CTRL0_RSM_TRIG_SEL_MASK    (0x1C00U)
#define XCVR_MISC_RSM_CTRL0_RSM_TRIG_SEL_SHIFT   (10U)
/*! RSM_TRIG_SEL - RSM_TRIG_SEL
 *  0b000..software trigger
 *  0b001..crc_vld
 *  0b010..aa_fnd_to_ll
 *  0b011..tx_dig_en
 *  0b100..seq_spare3
 *  0b101..lcl pattern_match
 *  0b110-0b111..Reserved
 */
#define XCVR_MISC_RSM_CTRL0_RSM_TRIG_SEL(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CTRL0_RSM_TRIG_SEL_SHIFT)) & XCVR_MISC_RSM_CTRL0_RSM_TRIG_SEL_MASK)

#define XCVR_MISC_RSM_CTRL0_RSM_TRIG_DLY_MASK    (0xFFE000U)
#define XCVR_MISC_RSM_CTRL0_RSM_TRIG_DLY_SHIFT   (13U)
/*! RSM_TRIG_DLY - RSM_TRIG_DLY
 */
#define XCVR_MISC_RSM_CTRL0_RSM_TRIG_DLY(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CTRL0_RSM_TRIG_DLY_SHIFT)) & XCVR_MISC_RSM_CTRL0_RSM_TRIG_DLY_MASK)

#define XCVR_MISC_RSM_CTRL0_RSM_STEPS_MASK       (0xFF000000U)
#define XCVR_MISC_RSM_CTRL0_RSM_STEPS_SHIFT      (24U)
/*! RSM_STEPS - RSM_FREQUENCY_STEP
 */
#define XCVR_MISC_RSM_CTRL0_RSM_STEPS(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CTRL0_RSM_STEPS_SHIFT)) & XCVR_MISC_RSM_CTRL0_RSM_STEPS_MASK)
/*! @} */

/*! @name RSM_CTRL1 - Ranging Sequence Manager Control */
/*! @{ */

#define XCVR_MISC_RSM_CTRL1_RSM_T_FM0_MASK       (0x1FU)
#define XCVR_MISC_RSM_CTRL1_RSM_T_FM0_SHIFT      (0U)
/*! RSM_T_FM0 - RSM_T_FM0
 */
#define XCVR_MISC_RSM_CTRL1_RSM_T_FM0(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CTRL1_RSM_T_FM0_SHIFT)) & XCVR_MISC_RSM_CTRL1_RSM_T_FM0_MASK)

#define XCVR_MISC_RSM_CTRL1_RSM_T_FM1_MASK       (0x3E0U)
#define XCVR_MISC_RSM_CTRL1_RSM_T_FM1_SHIFT      (5U)
/*! RSM_T_FM1 - RSM_T_FM1
 */
#define XCVR_MISC_RSM_CTRL1_RSM_T_FM1(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CTRL1_RSM_T_FM1_SHIFT)) & XCVR_MISC_RSM_CTRL1_RSM_T_FM1_MASK)

#define XCVR_MISC_RSM_CTRL1_RSM_T_FC_MASK        (0xF800U)
#define XCVR_MISC_RSM_CTRL1_RSM_T_FC_SHIFT       (11U)
/*! RSM_T_FC - RSM_T_FC
 */
#define XCVR_MISC_RSM_CTRL1_RSM_T_FC(x)          (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CTRL1_RSM_T_FC_SHIFT)) & XCVR_MISC_RSM_CTRL1_RSM_T_FC_MASK)

#define XCVR_MISC_RSM_CTRL1_RSM_T_IP1_MASK       (0x1F0000U)
#define XCVR_MISC_RSM_CTRL1_RSM_T_IP1_SHIFT      (16U)
/*! RSM_T_IP1 - RSM_T_IP1
 */
#define XCVR_MISC_RSM_CTRL1_RSM_T_IP1(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CTRL1_RSM_T_IP1_SHIFT)) & XCVR_MISC_RSM_CTRL1_RSM_T_IP1_MASK)

#define XCVR_MISC_RSM_CTRL1_RSM_T_IP2_MASK       (0x3E00000U)
#define XCVR_MISC_RSM_CTRL1_RSM_T_IP2_SHIFT      (21U)
/*! RSM_T_IP2 - RSM_T_IP2
 */
#define XCVR_MISC_RSM_CTRL1_RSM_T_IP2(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CTRL1_RSM_T_IP2_SHIFT)) & XCVR_MISC_RSM_CTRL1_RSM_T_IP2_MASK)

#define XCVR_MISC_RSM_CTRL1_RSM_T_S_MASK         (0xC000000U)
#define XCVR_MISC_RSM_CTRL1_RSM_T_S_SHIFT        (26U)
/*! RSM_T_S - RSM_T_S
 */
#define XCVR_MISC_RSM_CTRL1_RSM_T_S(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CTRL1_RSM_T_S_SHIFT)) & XCVR_MISC_RSM_CTRL1_RSM_T_S_MASK)
/*! @} */

/*! @name RSM_CTRL2 - Ranging Sequence Manager Control */
/*! @{ */

#define XCVR_MISC_RSM_CTRL2_RSM_T_PM0_MASK       (0x3FU)
#define XCVR_MISC_RSM_CTRL2_RSM_T_PM0_SHIFT      (0U)
/*! RSM_T_PM0 - RSM_T_PM0
 */
#define XCVR_MISC_RSM_CTRL2_RSM_T_PM0(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CTRL2_RSM_T_PM0_SHIFT)) & XCVR_MISC_RSM_CTRL2_RSM_T_PM0_MASK)

#define XCVR_MISC_RSM_CTRL2_RSM_T_PM1_MASK       (0xFC0U)
#define XCVR_MISC_RSM_CTRL2_RSM_T_PM1_SHIFT      (6U)
/*! RSM_T_PM1 - RSM_T_PM1
 */
#define XCVR_MISC_RSM_CTRL2_RSM_T_PM1(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CTRL2_RSM_T_PM1_SHIFT)) & XCVR_MISC_RSM_CTRL2_RSM_T_PM1_MASK)

#define XCVR_MISC_RSM_CTRL2_RSM_T_PM2_MASK       (0x3F000U)
#define XCVR_MISC_RSM_CTRL2_RSM_T_PM2_SHIFT      (12U)
/*! RSM_T_PM2 - RSM_T_PM2
 */
#define XCVR_MISC_RSM_CTRL2_RSM_T_PM2(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CTRL2_RSM_T_PM2_SHIFT)) & XCVR_MISC_RSM_CTRL2_RSM_T_PM2_MASK)

#define XCVR_MISC_RSM_CTRL2_RSM_T_PM3_MASK       (0xFC0000U)
#define XCVR_MISC_RSM_CTRL2_RSM_T_PM3_SHIFT      (18U)
/*! RSM_T_PM3 - RSM_T_PM3
 */
#define XCVR_MISC_RSM_CTRL2_RSM_T_PM3(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CTRL2_RSM_T_PM3_SHIFT)) & XCVR_MISC_RSM_CTRL2_RSM_T_PM3_MASK)

#define XCVR_MISC_RSM_CTRL2_RSM_ACTIVE_OVRD_LCL_MASK (0x4000000U)
#define XCVR_MISC_RSM_CTRL2_RSM_ACTIVE_OVRD_LCL_SHIFT (26U)
/*! RSM_ACTIVE_OVRD_LCL - RSM_ACTIVE_OVRD_LCL
 */
#define XCVR_MISC_RSM_CTRL2_RSM_ACTIVE_OVRD_LCL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CTRL2_RSM_ACTIVE_OVRD_LCL_SHIFT)) & XCVR_MISC_RSM_CTRL2_RSM_ACTIVE_OVRD_LCL_MASK)

#define XCVR_MISC_RSM_CTRL2_RSM_ACTIVE_OVRD_EN_LCL_MASK (0x8000000U)
#define XCVR_MISC_RSM_CTRL2_RSM_ACTIVE_OVRD_EN_LCL_SHIFT (27U)
/*! RSM_ACTIVE_OVRD_EN_LCL - RSM_ACTIVE_OVRD_EN_LCL
 *  0b0..Disable override rsm_active of LCL_CTRL module.
 *  0b1..Enable override rsm_active of LCL_CTRL module.
 */
#define XCVR_MISC_RSM_CTRL2_RSM_ACTIVE_OVRD_EN_LCL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CTRL2_RSM_ACTIVE_OVRD_EN_LCL_SHIFT)) & XCVR_MISC_RSM_CTRL2_RSM_ACTIVE_OVRD_EN_LCL_MASK)

#define XCVR_MISC_RSM_CTRL2_RSM_ACTIVE_OVRD_TXDIG_MASK (0x10000000U)
#define XCVR_MISC_RSM_CTRL2_RSM_ACTIVE_OVRD_TXDIG_SHIFT (28U)
/*! RSM_ACTIVE_OVRD_TXDIG - RSM_ACTIVE_OVRD_TXDIG
 */
#define XCVR_MISC_RSM_CTRL2_RSM_ACTIVE_OVRD_TXDIG(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CTRL2_RSM_ACTIVE_OVRD_TXDIG_SHIFT)) & XCVR_MISC_RSM_CTRL2_RSM_ACTIVE_OVRD_TXDIG_MASK)

#define XCVR_MISC_RSM_CTRL2_RSM_ACTIVE_OVRD_EN_TXDIG_MASK (0x20000000U)
#define XCVR_MISC_RSM_CTRL2_RSM_ACTIVE_OVRD_EN_TXDIG_SHIFT (29U)
/*! RSM_ACTIVE_OVRD_EN_TXDIG - RSM_ACTIVE_OVRD_EN_TXDIG
 *  0b0..Disable override rsm_active of TXDIG module.
 *  0b1..Enable override rsm_active of TXDIG module.
 */
#define XCVR_MISC_RSM_CTRL2_RSM_ACTIVE_OVRD_EN_TXDIG(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CTRL2_RSM_ACTIVE_OVRD_EN_TXDIG_SHIFT)) & XCVR_MISC_RSM_CTRL2_RSM_ACTIVE_OVRD_EN_TXDIG_MASK)

#define XCVR_MISC_RSM_CTRL2_RSM_ACTIVE_OVRD_RXDIG_MASK (0x40000000U)
#define XCVR_MISC_RSM_CTRL2_RSM_ACTIVE_OVRD_RXDIG_SHIFT (30U)
/*! RSM_ACTIVE_OVRD_RXDIG - RSM_ACTIVE_OVRD_RXDIG
 */
#define XCVR_MISC_RSM_CTRL2_RSM_ACTIVE_OVRD_RXDIG(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CTRL2_RSM_ACTIVE_OVRD_RXDIG_SHIFT)) & XCVR_MISC_RSM_CTRL2_RSM_ACTIVE_OVRD_RXDIG_MASK)

#define XCVR_MISC_RSM_CTRL2_RSM_ACTIVE_OVRD_EN_RXDIG_MASK (0x80000000U)
#define XCVR_MISC_RSM_CTRL2_RSM_ACTIVE_OVRD_EN_RXDIG_SHIFT (31U)
/*! RSM_ACTIVE_OVRD_EN_RXDIG - RSM_ACTIVE_OVRD_EN_RXDIG
 *  0b0..Disable override rsm_active of RXDIG module.
 *  0b1..Enable override rsm_active of RXDIG module.
 */
#define XCVR_MISC_RSM_CTRL2_RSM_ACTIVE_OVRD_EN_RXDIG(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CTRL2_RSM_ACTIVE_OVRD_EN_RXDIG_SHIFT)) & XCVR_MISC_RSM_CTRL2_RSM_ACTIVE_OVRD_EN_RXDIG_MASK)
/*! @} */

/*! @name RSM_CTRL3 - Ranging Sequence Manager Control */
/*! @{ */

#define XCVR_MISC_RSM_CTRL3_RSM_DT_RX_SYNC_DLY_MASK (0xFU)
#define XCVR_MISC_RSM_CTRL3_RSM_DT_RX_SYNC_DLY_SHIFT (0U)
/*! RSM_DT_RX_SYNC_DLY - RSM_DT_RX_SYNC_DLY
 */
#define XCVR_MISC_RSM_CTRL3_RSM_DT_RX_SYNC_DLY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CTRL3_RSM_DT_RX_SYNC_DLY_SHIFT)) & XCVR_MISC_RSM_CTRL3_RSM_DT_RX_SYNC_DLY_MASK)

#define XCVR_MISC_RSM_CTRL3_RSM_DT_RX_SYNC_DIS_MASK (0x10U)
#define XCVR_MISC_RSM_CTRL3_RSM_DT_RX_SYNC_DIS_SHIFT (4U)
/*! RSM_DT_RX_SYNC_DIS - RSM_DT_RX_SYNC_DIS
 */
#define XCVR_MISC_RSM_CTRL3_RSM_DT_RX_SYNC_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CTRL3_RSM_DT_RX_SYNC_DIS_SHIFT)) & XCVR_MISC_RSM_CTRL3_RSM_DT_RX_SYNC_DIS_MASK)

#define XCVR_MISC_RSM_CTRL3_RSM_AA_HAMM_MASK     (0xE0U)
#define XCVR_MISC_RSM_CTRL3_RSM_AA_HAMM_SHIFT    (5U)
/*! RSM_AA_HAMM - RSM_AA_HAMM
 */
#define XCVR_MISC_RSM_CTRL3_RSM_AA_HAMM(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CTRL3_RSM_AA_HAMM_SHIFT)) & XCVR_MISC_RSM_CTRL3_RSM_AA_HAMM_MASK)

#define XCVR_MISC_RSM_CTRL3_RSM_HPM_CAL_MASK     (0x100U)
#define XCVR_MISC_RSM_CTRL3_RSM_HPM_CAL_SHIFT    (8U)
/*! RSM_HPM_CAL - RSM_HPM_CAL
 */
#define XCVR_MISC_RSM_CTRL3_RSM_HPM_CAL(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CTRL3_RSM_HPM_CAL_SHIFT)) & XCVR_MISC_RSM_CTRL3_RSM_HPM_CAL_MASK)

#define XCVR_MISC_RSM_CTRL3_RSM_CTUNE_MASK       (0x200U)
#define XCVR_MISC_RSM_CTRL3_RSM_CTUNE_SHIFT      (9U)
/*! RSM_CTUNE - RSM_CTUNE
 */
#define XCVR_MISC_RSM_CTRL3_RSM_CTUNE(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CTRL3_RSM_CTUNE_SHIFT)) & XCVR_MISC_RSM_CTRL3_RSM_CTUNE_MASK)

#define XCVR_MISC_RSM_CTRL3_RSM_DMA_RX_EN_MASK   (0x400U)
#define XCVR_MISC_RSM_CTRL3_RSM_DMA_RX_EN_SHIFT  (10U)
/*! RSM_DMA_RX_EN - RSM_DMA_RX_EN
 */
#define XCVR_MISC_RSM_CTRL3_RSM_DMA_RX_EN(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CTRL3_RSM_DMA_RX_EN_SHIFT)) & XCVR_MISC_RSM_CTRL3_RSM_DMA_RX_EN_MASK)

#define XCVR_MISC_RSM_CTRL3_RSM_RX_PHY_EN_MASK_DIS_MASK (0x800U)
#define XCVR_MISC_RSM_CTRL3_RSM_RX_PHY_EN_MASK_DIS_SHIFT (11U)
/*! RSM_RX_PHY_EN_MASK_DIS - RSM_RX_PHY_EN_MASK_DIS
 */
#define XCVR_MISC_RSM_CTRL3_RSM_RX_PHY_EN_MASK_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CTRL3_RSM_RX_PHY_EN_MASK_DIS_SHIFT)) & XCVR_MISC_RSM_CTRL3_RSM_RX_PHY_EN_MASK_DIS_MASK)

#define XCVR_MISC_RSM_CTRL3_RSM_RX_SIGNALS_MASK_DIS_MASK (0x1000U)
#define XCVR_MISC_RSM_CTRL3_RSM_RX_SIGNALS_MASK_DIS_SHIFT (12U)
/*! RSM_RX_SIGNALS_MASK_DIS - RSM_RX_SIGNALS_MASK_DIS
 */
#define XCVR_MISC_RSM_CTRL3_RSM_RX_SIGNALS_MASK_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CTRL3_RSM_RX_SIGNALS_MASK_DIS_SHIFT)) & XCVR_MISC_RSM_CTRL3_RSM_RX_SIGNALS_MASK_DIS_MASK)

#define XCVR_MISC_RSM_CTRL3_RSM_SEQ_RCCAL_PUP_MASK_DIS_MASK (0x2000U)
#define XCVR_MISC_RSM_CTRL3_RSM_SEQ_RCCAL_PUP_MASK_DIS_SHIFT (13U)
/*! RSM_SEQ_RCCAL_PUP_MASK_DIS - RSM_SEQ_RCCAL_PUP_MASK_DIS
 */
#define XCVR_MISC_RSM_CTRL3_RSM_SEQ_RCCAL_PUP_MASK_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CTRL3_RSM_SEQ_RCCAL_PUP_MASK_DIS_SHIFT)) & XCVR_MISC_RSM_CTRL3_RSM_SEQ_RCCAL_PUP_MASK_DIS_MASK)

#define XCVR_MISC_RSM_CTRL3_RSM_DMA_DUR_MASK     (0x3FF0000U)
#define XCVR_MISC_RSM_CTRL3_RSM_DMA_DUR_SHIFT    (16U)
/*! RSM_DMA_DUR - DMA Duration
 */
#define XCVR_MISC_RSM_CTRL3_RSM_DMA_DUR(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CTRL3_RSM_DMA_DUR_SHIFT)) & XCVR_MISC_RSM_CTRL3_RSM_DMA_DUR_MASK)
/*! @} */

/*! @name RSM_CTRL4 - Ranging Sequence Manager Control */
/*! @{ */

#define XCVR_MISC_RSM_CTRL4_RSM_DMA_DLY0_MASK    (0xFFU)
#define XCVR_MISC_RSM_CTRL4_RSM_DMA_DLY0_SHIFT   (0U)
/*! RSM_DMA_DLY0 - DMA Delay 0
 */
#define XCVR_MISC_RSM_CTRL4_RSM_DMA_DLY0(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CTRL4_RSM_DMA_DLY0_SHIFT)) & XCVR_MISC_RSM_CTRL4_RSM_DMA_DLY0_MASK)

#define XCVR_MISC_RSM_CTRL4_RSM_DMA_DLY_MASK     (0xFF00U)
#define XCVR_MISC_RSM_CTRL4_RSM_DMA_DLY_SHIFT    (8U)
/*! RSM_DMA_DLY - DMA Delay
 */
#define XCVR_MISC_RSM_CTRL4_RSM_DMA_DLY(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CTRL4_RSM_DMA_DLY_SHIFT)) & XCVR_MISC_RSM_CTRL4_RSM_DMA_DLY_MASK)

#define XCVR_MISC_RSM_CTRL4_RSM_DMA_DUR0_MASK    (0x3FF0000U)
#define XCVR_MISC_RSM_CTRL4_RSM_DMA_DUR0_SHIFT   (16U)
/*! RSM_DMA_DUR0 - DMA Duration 0
 */
#define XCVR_MISC_RSM_CTRL4_RSM_DMA_DUR0(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RSM_CTRL4_RSM_DMA_DUR0_SHIFT)) & XCVR_MISC_RSM_CTRL4_RSM_DMA_DUR0_MASK)
/*! @} */

/*! @name RF_DFT_CTRL - RF DFT CTRL */
/*! @{ */

#define XCVR_MISC_RF_DFT_CTRL_RADIO_DFT_MODE_MASK (0xFU)
#define XCVR_MISC_RF_DFT_CTRL_RADIO_DFT_MODE_SHIFT (0U)
/*! RADIO_DFT_MODE - Radio DFT mode control
 *  0b0000..Normal Mode
 *  0b0001..Carrier Only
 *  0b0010..Pattern Register
 *  0b0011..LFSR
 *  0b0100..RAM Modulation
 *  0b1010..Coarse Tune BIST, no modulation
 *  0b1011..PLL Locking BIST, no modulation
 *  0b1100..HPM DAC Cal BIST, no modulation
 */
#define XCVR_MISC_RF_DFT_CTRL_RADIO_DFT_MODE(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_RF_DFT_CTRL_RADIO_DFT_MODE_SHIFT)) & XCVR_MISC_RF_DFT_CTRL_RADIO_DFT_MODE_MASK)
/*! @} */

/*! @name IPS_FO_ADDR - IPS FAST OVERWRITE ADDRESS */
/*! @{ */

#define XCVR_MISC_IPS_FO_ADDR_ADDR_MASK          (0xFFFU)
#define XCVR_MISC_IPS_FO_ADDR_ADDR_SHIFT         (0U)
/*! ADDR - IPS Address
 */
#define XCVR_MISC_IPS_FO_ADDR_ADDR(x)            (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_IPS_FO_ADDR_ADDR_SHIFT)) & XCVR_MISC_IPS_FO_ADDR_ADDR_MASK)

#define XCVR_MISC_IPS_FO_ADDR_ENTRY_RX_MASK      (0x1000U)
#define XCVR_MISC_IPS_FO_ADDR_ENTRY_RX_SHIFT     (12U)
/*! ENTRY_RX - Enable Entry for RX
 */
#define XCVR_MISC_IPS_FO_ADDR_ENTRY_RX(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_IPS_FO_ADDR_ENTRY_RX_SHIFT)) & XCVR_MISC_IPS_FO_ADDR_ENTRY_RX_MASK)

#define XCVR_MISC_IPS_FO_ADDR_ENTRY_TX_MASK      (0x2000U)
#define XCVR_MISC_IPS_FO_ADDR_ENTRY_TX_SHIFT     (13U)
/*! ENTRY_TX - Enable Entry for TX
 */
#define XCVR_MISC_IPS_FO_ADDR_ENTRY_TX(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_IPS_FO_ADDR_ENTRY_TX_SHIFT)) & XCVR_MISC_IPS_FO_ADDR_ENTRY_TX_MASK)
/*! @} */

/* The count of XCVR_MISC_IPS_FO_ADDR */
#define XCVR_MISC_IPS_FO_ADDR_COUNT              (8U)

/*! @name IPS_FO_DRS0_DATA - IPS FAST OVERWRITE DRS0 DATA */
/*! @{ */

#define XCVR_MISC_IPS_FO_DRS0_DATA_DRS0_DATA_MASK (0xFFFFFFFFU)
#define XCVR_MISC_IPS_FO_DRS0_DATA_DRS0_DATA_SHIFT (0U)
/*! DRS0_DATA - Fast Overwrite DRS0 data
 */
#define XCVR_MISC_IPS_FO_DRS0_DATA_DRS0_DATA(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_IPS_FO_DRS0_DATA_DRS0_DATA_SHIFT)) & XCVR_MISC_IPS_FO_DRS0_DATA_DRS0_DATA_MASK)
/*! @} */

/* The count of XCVR_MISC_IPS_FO_DRS0_DATA */
#define XCVR_MISC_IPS_FO_DRS0_DATA_COUNT         (8U)

/*! @name IPS_FO_DRS1_DATA - IPS FAST OVERWRITE DRS1 DATA */
/*! @{ */

#define XCVR_MISC_IPS_FO_DRS1_DATA_DRS1_DATA_MASK (0xFFFFFFFFU)
#define XCVR_MISC_IPS_FO_DRS1_DATA_DRS1_DATA_SHIFT (0U)
/*! DRS1_DATA - Fast Overwrite DRS1 data
 */
#define XCVR_MISC_IPS_FO_DRS1_DATA_DRS1_DATA(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_MISC_IPS_FO_DRS1_DATA_DRS1_DATA_SHIFT)) & XCVR_MISC_IPS_FO_DRS1_DATA_DRS1_DATA_MASK)
/*! @} */

/* The count of XCVR_MISC_IPS_FO_DRS1_DATA */
#define XCVR_MISC_IPS_FO_DRS1_DATA_COUNT         (8U)


/*!
 * @}
 */ /* end of group XCVR_MISC_Register_Masks */


/* XCVR_MISC - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral XCVR_MISC base address */
  #define XCVR_MISC_BASE                           (0x58A07D00u)
  /** Peripheral XCVR_MISC base address */
  #define XCVR_MISC_BASE_NS                        (0x48A07D00u)
  /** Peripheral XCVR_MISC base pointer */
  #define XCVR_MISC                                ((XCVR_MISC_Type *)XCVR_MISC_BASE)
  /** Peripheral XCVR_MISC base pointer */
  #define XCVR_MISC_NS                             ((XCVR_MISC_Type *)XCVR_MISC_BASE_NS)
  /** Array initializer of XCVR_MISC peripheral base addresses */
  #define XCVR_MISC_BASE_ADDRS                     { XCVR_MISC_BASE }
  /** Array initializer of XCVR_MISC peripheral base pointers */
  #define XCVR_MISC_BASE_PTRS                      { XCVR_MISC }
  /** Array initializer of XCVR_MISC peripheral base addresses */
  #define XCVR_MISC_BASE_ADDRS_NS                  { XCVR_MISC_BASE_NS }
  /** Array initializer of XCVR_MISC peripheral base pointers */
  #define XCVR_MISC_BASE_PTRS_NS                   { XCVR_MISC_NS }
#else
  /** Peripheral XCVR_MISC base address */
  #define XCVR_MISC_BASE                           (0x48A07D00u)
  /** Peripheral XCVR_MISC base pointer */
  #define XCVR_MISC                                ((XCVR_MISC_Type *)XCVR_MISC_BASE)
  /** Array initializer of XCVR_MISC peripheral base addresses */
  #define XCVR_MISC_BASE_ADDRS                     { XCVR_MISC_BASE }
  /** Array initializer of XCVR_MISC peripheral base pointers */
  #define XCVR_MISC_BASE_PTRS                      { XCVR_MISC }
#endif

/*!
 * @}
 */ /* end of group XCVR_MISC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- XCVR_PLL_DIG Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup XCVR_PLL_DIG_Peripheral_Access_Layer XCVR_PLL_DIG Peripheral Access Layer
 * @{
 */

/** XCVR_PLL_DIG - Register Layout Typedef */
typedef struct {
  __IO uint32_t HPM_BUMP;                          /**< PLL HPM Analog Bump Control, offset: 0x0 */
  __IO uint32_t MOD_CTRL;                          /**< PLL Modulation Control, offset: 0x4 */
  __IO uint32_t CHAN_MAP;                          /**< PLL Channel Mapping, offset: 0x8 */
       uint8_t RESERVED_0[4];
  __IO uint32_t CHAN_MAP_EXT;                      /**< PLL Channel Mapping Extended, offset: 0x10 */
       uint8_t RESERVED_1[4];
  __IO uint32_t LOCK_DETECT;                       /**< PLL Lock Detect Control, offset: 0x18 */
  __IO uint32_t HPM_CTRL;                          /**< PLL High Port Modulator Control, offset: 0x1C */
  __IO uint32_t HPMCAL_CTRL;                       /**< PLL High Port Calibration Control, offset: 0x20 */
  __I  uint32_t HPM_CAL1;                          /**< PLL High Port Calibration Result 1, offset: 0x24 */
  __I  uint32_t HPM_CAL2;                          /**< PLL High Port Calibration Result 2, offset: 0x28 */
  __IO uint32_t HPM_SDM_RES;                       /**< PLL High Port Sigma Delta Results, offset: 0x2C */
  __IO uint32_t LPM_CTRL;                          /**< PLL Low Port Modulator Control, offset: 0x30 */
  __IO uint32_t LPM_SDM_CTRL1;                     /**< PLL Low Port Sigma Delta Control 1, offset: 0x34 */
  __IO uint32_t LPM_SDM_CTRL2;                     /**< PLL Low Port Sigma Delta Control 2, offset: 0x38 */
  __IO uint32_t LPM_SDM_CTRL3;                     /**< PLL Low Port Sigma Delta Control 3, offset: 0x3C */
  __I  uint32_t LPM_SDM_RES1;                      /**< PLL Low Port Sigma Delta Result 1, offset: 0x40 */
  __I  uint32_t LPM_SDM_RES2;                      /**< PLL Low Port Sigma Delta Result 2, offset: 0x44 */
  __IO uint32_t DELAY_MATCH;                       /**< PLL Delay Matching, offset: 0x48 */
  __IO uint32_t TUNING_CAP_TX_CTRL;                /**< Tuning Cap Settings in Transmit Mode, offset: 0x4C */
  __IO uint32_t TUNING_CAP_RX_CTRL;                /**< Tuning Cap Settings in Receive Mode, offset: 0x50 */
       uint8_t RESERVED_2[4];
  __IO uint32_t MAX_TX_CFG1_FREQ;                  /**< Max Transmit Frequency For TX Configuration 1, offset: 0x58 */
  __IO uint32_t CTUNE_CTRL;                        /**< PLL Coarse Tune Control, offset: 0x5C */
  __IO uint32_t DATA_RATE_OVRD_CTRL1;              /**< PLL Data Rate Override Control, offset: 0x60 */
  __IO uint32_t DATA_RATE_OVRD_CTRL2;              /**< PLL Data Rate Override Control, offset: 0x64 */
       uint8_t RESERVED_3[28];
  __I  uint32_t CTUNE_RES;                         /**< PLL Coarse Tune Results, offset: 0x84 */
       uint8_t RESERVED_4[24];
  __IO uint32_t HPM_CAL_TIMING;                    /**< PLL HPM Calibration Timing Attributes, offset: 0xA0 */
  __IO uint32_t PLL_OFFSET_CTRL;                   /**< PLL Offset Control, offset: 0xA4 */
  __IO uint32_t PLL_DATARATE_CTRL;                 /**< PLL Data Rate Switch Control, offset: 0xA8 */
} XCVR_PLL_DIG_Type;

/* ----------------------------------------------------------------------------
   -- XCVR_PLL_DIG Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup XCVR_PLL_DIG_Register_Masks XCVR_PLL_DIG Register Masks
 * @{
 */

/*! @name HPM_BUMP - PLL HPM Analog Bump Control */
/*! @{ */

#define XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_TX_MASK    (0x7U)
#define XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_TX_SHIFT   (0U)
/*! HPM_VCM_TX - a_ip_2p4ghz_reg_dac_trim_vcm_dig[2:0] during Transmission
 *  0b000..0.120 (0.122)
 *  0b001..0.153 (0.189)
 *  0b010..0.182 (0.247)
 *  0b011..0.209 (0.300)
 *  0b100..0.234 (0.348)
 *  0b101..0.258 (0.393)
 *  0b110..0.279 (0.434)
 *  0b111..0.318 (0.509)
 */
#define XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_TX(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_TX_SHIFT)) & XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_TX_MASK)

#define XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_CAL_MASK   (0x70U)
#define XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_CAL_SHIFT  (4U)
/*! HPM_VCM_CAL - a_ip_2p4ghz_reg_dac_trim_vcm_dig[2:0] during Calibration
 *  0b000..0.120 (0.122)
 *  0b001..0.153 (0.189)
 *  0b010..0.182 (0.247)
 *  0b011..0.209 (0.300)
 *  0b100..0.234 (0.348)
 *  0b101..0.258 (0.393)
 *  0b110..0.279 (0.434)
 *  0b111..0.318 (0.509)
 */
#define XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_CAL(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_CAL_SHIFT)) & XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_CAL_MASK)

#define XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_TX_MASK (0x300U)
#define XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_TX_SHIFT (8U)
/*! HPM_FDB_RES_TX - a_ip_2p4ghz_reg_dac_trim_rfbk_dig[1:0] during Transmission
 *  0b00..38.0k (1.0)
 *  0b01..76.0k (0.5)
 *  0b10..32.5k (1.14)
 *  0b11..25.3k (1.4)
 */
#define XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_TX(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_TX_SHIFT)) & XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_TX_MASK)

#define XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_CAL_MASK (0x3000U)
#define XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_CAL_SHIFT (12U)
/*! HPM_FDB_RES_CAL - a_ip_2p4ghz_reg_dac_trim_rfbk_dig[1:0] during Calibration
 *  0b00..38.0k (1.0)
 *  0b01..76.0k (0.5)
 *  0b10..32.5k (1.14)
 *  0b11..25.3k (1.4)
 */
#define XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_CAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_CAL_SHIFT)) & XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_CAL_MASK)

#define XCVR_PLL_DIG_HPM_BUMP_PLL_VCO_TRIM_KVM_TX_MASK (0x70000U)
#define XCVR_PLL_DIG_HPM_BUMP_PLL_VCO_TRIM_KVM_TX_SHIFT (16U)
/*! PLL_VCO_TRIM_KVM_TX - reg_vco_trim_kvm_dig[2:0] for transmitt
 *  0b000..10MHz/V
 *  0b100..20MHz/V
 *  0b110..30MHz/V
 *  0b111..40MHz/V
 */
#define XCVR_PLL_DIG_HPM_BUMP_PLL_VCO_TRIM_KVM_TX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_BUMP_PLL_VCO_TRIM_KVM_TX_SHIFT)) & XCVR_PLL_DIG_HPM_BUMP_PLL_VCO_TRIM_KVM_TX_MASK)

#define XCVR_PLL_DIG_HPM_BUMP_PLL_VCO_TRIM_KVM_CAL_MASK (0x700000U)
#define XCVR_PLL_DIG_HPM_BUMP_PLL_VCO_TRIM_KVM_CAL_SHIFT (20U)
/*! PLL_VCO_TRIM_KVM_CAL - reg_vco_trim_kvm_dig[2:0] for calibration
 *  0b000..10MHz/V
 *  0b100..20MHz/V
 *  0b110..30MHz/V
 *  0b111..40MHz/V
 */
#define XCVR_PLL_DIG_HPM_BUMP_PLL_VCO_TRIM_KVM_CAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_BUMP_PLL_VCO_TRIM_KVM_CAL_SHIFT)) & XCVR_PLL_DIG_HPM_BUMP_PLL_VCO_TRIM_KVM_CAL_MASK)
/*! @} */

/*! @name MOD_CTRL - PLL Modulation Control */
/*! @{ */

#define XCVR_PLL_DIG_MOD_CTRL_MODULATION_WORD_MANUAL_MASK (0x1FFFU)
#define XCVR_PLL_DIG_MOD_CTRL_MODULATION_WORD_MANUAL_SHIFT (0U)
/*! MODULATION_WORD_MANUAL - Manual Modulation Word
 */
#define XCVR_PLL_DIG_MOD_CTRL_MODULATION_WORD_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_MOD_CTRL_MODULATION_WORD_MANUAL_SHIFT)) & XCVR_PLL_DIG_MOD_CTRL_MODULATION_WORD_MANUAL_MASK)

#define XCVR_PLL_DIG_MOD_CTRL_MOD_DISABLE_MASK   (0x8000U)
#define XCVR_PLL_DIG_MOD_CTRL_MOD_DISABLE_SHIFT  (15U)
/*! MOD_DISABLE - Disable Modulation Word
 */
#define XCVR_PLL_DIG_MOD_CTRL_MOD_DISABLE(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_MOD_CTRL_MOD_DISABLE_SHIFT)) & XCVR_PLL_DIG_MOD_CTRL_MOD_DISABLE_MASK)

#define XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_MANUAL_MASK (0xFF0000U)
#define XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_MANUAL_SHIFT (16U)
/*! HPM_MOD_MANUAL - Manual HPM Modulation
 */
#define XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_MANUAL(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_MANUAL_SHIFT)) & XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_MANUAL_MASK)

#define XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_DISABLE_MASK (0x8000000U)
#define XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_DISABLE_SHIFT (27U)
/*! HPM_MOD_DISABLE - Disable HPM Modulation
 */
#define XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_DISABLE_SHIFT)) & XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_DISABLE_MASK)

#define XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_MANUAL_MASK (0x30000000U)
#define XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_MANUAL_SHIFT (28U)
/*! HPM_SDM_OUT_MANUAL - Manual HPM SDM out
 */
#define XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_MANUAL_SHIFT)) & XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_MANUAL_MASK)

#define XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_DISABLE_MASK (0x80000000U)
#define XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_DISABLE_SHIFT (31U)
/*! HPM_SDM_OUT_DISABLE - Disable HPM SDM out
 */
#define XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_DISABLE_SHIFT)) & XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_DISABLE_MASK)
/*! @} */

/*! @name CHAN_MAP - PLL Channel Mapping */
/*! @{ */

#define XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM_OVRD_MASK (0xFFFFU)
#define XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM_OVRD_SHIFT (0U)
/*! CHANNEL_NUM_OVRD - Channel Selection Override
 */
#define XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM_OVRD_SHIFT)) & XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM_OVRD_MASK)

#define XCVR_PLL_DIG_CHAN_MAP_BAND_SELECT_MASK   (0x70000U)
#define XCVR_PLL_DIG_CHAN_MAP_BAND_SELECT_SHIFT  (16U)
/*! BAND_SELECT - Channel Mapping Band Select
 *  0b000..Bluetooth Low Energy
 *  0b001..Bluetooth Low Energy in MBAN
 *  0b010..Bluetooth Low Energy overlap MBAN
 *  0b011..RESERVED
 *  0b100..RESERVED
 *  0b101..RESERVED
 *  0b110-0b111..Radio Channels 0-127 selectable
 */
#define XCVR_PLL_DIG_CHAN_MAP_BAND_SELECT(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CHAN_MAP_BAND_SELECT_SHIFT)) & XCVR_PLL_DIG_CHAN_MAP_BAND_SELECT_MASK)

#define XCVR_PLL_DIG_CHAN_MAP_BMR_MASK           (0x80000U)
#define XCVR_PLL_DIG_CHAN_MAP_BMR_SHIFT          (19U)
/*! BMR - Bluetooth Low Energy MBAN Channel Remap
 *  0b0..Bluetooth Low Energy channel 39 is mapped to Bluetooth Low Energy channel 39, 2.480 GHz
 *  0b1..Bluetooth Low Energy channel 39 is mapped to MBAN channel 39, 2.399 GHz
 */
#define XCVR_PLL_DIG_CHAN_MAP_BMR(x)             (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CHAN_MAP_BMR_SHIFT)) & XCVR_PLL_DIG_CHAN_MAP_BMR_MASK)

#define XCVR_PLL_DIG_CHAN_MAP_HOP_TBL_CFG_OVRD_MASK (0x7000000U)
#define XCVR_PLL_DIG_CHAN_MAP_HOP_TBL_CFG_OVRD_SHIFT (24U)
/*! HOP_TBL_CFG_OVRD - Hop Table Configuration Override
 *  0b000-0b001..CHANNEL_NUM_OVRD[6:0] is used as the mapped channel number. CHANNEL_NUM_OVRD[15:7] is unused.
 *  0b010..CHANNEL_NUM_OVRD[15:7] is signed Numerator offset to CHANNEL_NUM_OVRD[6:0] mapped channel number
 *  0b011..CHANNEL_NUM_OVRD[15:1] is selected as the signed Numerator, CHANNEL_NUM_OVRD[0] is integer selection
 */
#define XCVR_PLL_DIG_CHAN_MAP_HOP_TBL_CFG_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CHAN_MAP_HOP_TBL_CFG_OVRD_SHIFT)) & XCVR_PLL_DIG_CHAN_MAP_HOP_TBL_CFG_OVRD_MASK)

#define XCVR_PLL_DIG_CHAN_MAP_HOP_TBL_CFG_OVRD_EN_MASK (0x8000000U)
#define XCVR_PLL_DIG_CHAN_MAP_HOP_TBL_CFG_OVRD_EN_SHIFT (27U)
/*! HOP_TBL_CFG_OVRD_EN - Hop Table Configuration Override Enable
 */
#define XCVR_PLL_DIG_CHAN_MAP_HOP_TBL_CFG_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CHAN_MAP_HOP_TBL_CFG_OVRD_EN_SHIFT)) & XCVR_PLL_DIG_CHAN_MAP_HOP_TBL_CFG_OVRD_EN_MASK)
/*! @} */

/*! @name CHAN_MAP_EXT - PLL Channel Mapping Extended */
/*! @{ */

#define XCVR_PLL_DIG_CHAN_MAP_EXT_NUM_OFFSET_MASK (0xFFFFFFFU)
#define XCVR_PLL_DIG_CHAN_MAP_EXT_NUM_OFFSET_SHIFT (0U)
/*! NUM_OFFSET - Numerator Offset
 */
#define XCVR_PLL_DIG_CHAN_MAP_EXT_NUM_OFFSET(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CHAN_MAP_EXT_NUM_OFFSET_SHIFT)) & XCVR_PLL_DIG_CHAN_MAP_EXT_NUM_OFFSET_MASK)

#define XCVR_PLL_DIG_CHAN_MAP_EXT_CTUNE_TGT_OFFSET_MASK (0x70000000U)
#define XCVR_PLL_DIG_CHAN_MAP_EXT_CTUNE_TGT_OFFSET_SHIFT (28U)
/*! CTUNE_TGT_OFFSET - Coarse Tune Target Frequency Offset
 */
#define XCVR_PLL_DIG_CHAN_MAP_EXT_CTUNE_TGT_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CHAN_MAP_EXT_CTUNE_TGT_OFFSET_SHIFT)) & XCVR_PLL_DIG_CHAN_MAP_EXT_CTUNE_TGT_OFFSET_MASK)
/*! @} */

/*! @name LOCK_DETECT - PLL Lock Detect Control */
/*! @{ */

#define XCVR_PLL_DIG_LOCK_DETECT_CT_FAIL_MASK    (0x1U)
#define XCVR_PLL_DIG_LOCK_DETECT_CT_FAIL_SHIFT   (0U)
/*! CT_FAIL - Real time status of Coarse Tune Fail signal
 */
#define XCVR_PLL_DIG_LOCK_DETECT_CT_FAIL(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_CT_FAIL_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_CT_FAIL_MASK)

#define XCVR_PLL_DIG_LOCK_DETECT_CTFF_MASK       (0x2U)
#define XCVR_PLL_DIG_LOCK_DETECT_CTFF_SHIFT      (1U)
/*! CTFF - CTUNE Failure Flag, held until cleared
 */
#define XCVR_PLL_DIG_LOCK_DETECT_CTFF(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_CTFF_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_CTFF_MASK)

#define XCVR_PLL_DIG_LOCK_DETECT_FT_FAIL_MASK    (0x10U)
#define XCVR_PLL_DIG_LOCK_DETECT_FT_FAIL_SHIFT   (4U)
/*! FT_FAIL - Real time status of Frequency Target Failure
 */
#define XCVR_PLL_DIG_LOCK_DETECT_FT_FAIL(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FT_FAIL_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FT_FAIL_MASK)

#define XCVR_PLL_DIG_LOCK_DETECT_FTFF_MASK       (0x20U)
#define XCVR_PLL_DIG_LOCK_DETECT_FTFF_SHIFT      (5U)
/*! FTFF - Frequency Target Failure Flag
 */
#define XCVR_PLL_DIG_LOCK_DETECT_FTFF(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FTFF_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FTFF_MASK)

#define XCVR_PLL_DIG_LOCK_DETECT_CTUNE_LDF_LEV_MASK (0xF00U)
#define XCVR_PLL_DIG_LOCK_DETECT_CTUNE_LDF_LEV_SHIFT (8U)
/*! CTUNE_LDF_LEV - CTUNE Lock Detect Fail Level
 */
#define XCVR_PLL_DIG_LOCK_DETECT_CTUNE_LDF_LEV(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_CTUNE_LDF_LEV_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_CTUNE_LDF_LEV_MASK)

#define XCVR_PLL_DIG_LOCK_DETECT_FTF_RX_THRSH_MASK (0x3F000U)
#define XCVR_PLL_DIG_LOCK_DETECT_FTF_RX_THRSH_SHIFT (12U)
/*! FTF_RX_THRSH - RX Frequency Target Fail Threshold
 */
#define XCVR_PLL_DIG_LOCK_DETECT_FTF_RX_THRSH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FTF_RX_THRSH_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FTF_RX_THRSH_MASK)

#define XCVR_PLL_DIG_LOCK_DETECT_FTF_TX_THRSH_MASK (0xFC0000U)
#define XCVR_PLL_DIG_LOCK_DETECT_FTF_TX_THRSH_SHIFT (18U)
/*! FTF_TX_THRSH - TX Frequency Target Fail Threshold
 */
#define XCVR_PLL_DIG_LOCK_DETECT_FTF_TX_THRSH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FTF_TX_THRSH_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FTF_TX_THRSH_MASK)

#define XCVR_PLL_DIG_LOCK_DETECT_FCAL_HOLD_EN_MASK (0x1000000U)
#define XCVR_PLL_DIG_LOCK_DETECT_FCAL_HOLD_EN_SHIFT (24U)
/*! FCAL_HOLD_EN - Frequency Counter Hold Enable
 *  0b0..The frequency counter is turned off after CTUNE (RX Mode) or HPM CAL (TX Mode)
 *  0b1..The frequency counter is held on after CTUNE (RX Mode) or HPM CAL (TX Mode) for an optional lock detect sequence.
 */
#define XCVR_PLL_DIG_LOCK_DETECT_FCAL_HOLD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FCAL_HOLD_EN_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FCAL_HOLD_EN_MASK)

#define XCVR_PLL_DIG_LOCK_DETECT_FTW_TXRX_MASK   (0xE000000U)
#define XCVR_PLL_DIG_LOCK_DETECT_FTW_TXRX_SHIFT  (25U)
/*! FTW_TXRX - TX and RX Frequency Target Window time select
 *  0b000..FTW_TX = 4us ; FTW_RX = 4us
 *  0b001..FTW_TX = 4us ; FTW_RX = 8us
 *  0b010..FTW_TX = 8us ; FTW_RX = 4us
 *  0b011..FTW_TX = 8us ; FTW_RX = 8us
 *  0b100..FTW_TX = 16us ; FTW_RX = 16us
 *  0b101..FTW_TX = 16us ; FTW_RX = 32us
 *  0b110..FTW_TX = 32us ; FTW_RX = 16us
 *  0b111..FTW_TX = 32us ; FTW_RX = 32us
 */
#define XCVR_PLL_DIG_LOCK_DETECT_FTW_TXRX(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FTW_TXRX_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FTW_TXRX_MASK)

#define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_GO_MASK (0x10000000U)
#define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_GO_SHIFT (28U)
/*! FREQ_COUNT_GO - Start the Frequency Meter
 */
#define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_GO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_GO_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_GO_MASK)

#define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_FINISHED_MASK (0x20000000U)
#define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_FINISHED_SHIFT (29U)
/*! FREQ_COUNT_FINISHED - Frequency Meter has finished the Count Time
 */
#define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_FINISHED_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_FINISHED_MASK)

#define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_TIME_MASK (0xC0000000U)
#define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_TIME_SHIFT (30U)
/*! FREQ_COUNT_TIME - Frequency Meter Count Time
 *  0b00..800 us
 *  0b01..25 us
 *  0b10..50 us
 *  0b11..100 us
 */
#define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_TIME(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_TIME_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_TIME_MASK)
/*! @} */

/*! @name HPM_CTRL - PLL High Port Modulator Control */
/*! @{ */

#define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_MANUAL_MASK (0x3FFU)
#define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_MANUAL_SHIFT (0U)
/*! HPM_SDM_IN_MANUAL - Manual High Port SDM Fractional value
 */
#define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_MANUAL_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_MANUAL_MASK)

#define XCVR_PLL_DIG_HPM_CTRL_HPM_CLK_CONFIG_MASK (0x1000U)
#define XCVR_PLL_DIG_HPM_CTRL_HPM_CLK_CONFIG_SHIFT (12U)
/*! HPM_CLK_CONFIG - HPM Clock Config
 */
#define XCVR_PLL_DIG_HPM_CTRL_HPM_CLK_CONFIG(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_CLK_CONFIG_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_CLK_CONFIG_MASK)

#define XCVR_PLL_DIG_HPM_CTRL_HPFF_MASK          (0x2000U)
#define XCVR_PLL_DIG_HPM_CTRL_HPFF_SHIFT         (13U)
/*! HPFF - HPM SDM Invalid Flag
 */
#define XCVR_PLL_DIG_HPM_CTRL_HPFF(x)            (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPFF_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPFF_MASK)

#define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_OUT_INVERT_MASK (0x4000U)
#define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_OUT_INVERT_SHIFT (14U)
/*! HPM_SDM_OUT_INVERT - Invert HPM SDM Output
 */
#define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_OUT_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_OUT_INVERT_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_OUT_INVERT_MASK)

#define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_DISABLE_MASK (0x8000U)
#define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_DISABLE_SHIFT (15U)
/*! HPM_SDM_IN_DISABLE - Disable HPM SDM Input
 */
#define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_DISABLE_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_DISABLE_MASK)

#define XCVR_PLL_DIG_HPM_CTRL_HPM_LFSR_SIZE_MASK (0x70000U)
#define XCVR_PLL_DIG_HPM_CTRL_HPM_LFSR_SIZE_SHIFT (16U)
/*! HPM_LFSR_SIZE - HPM LFSR Length
 *  0b000..LFSR 9, tap mask 100010000
 *  0b001..LFSR 10, tap mask 1001000000
 *  0b010..LFSR 11, tap mask 11101000000
 *  0b011..LFSR 13, tap mask 1101100000000
 *  0b100..LFSR 15, tap mask 111010000000000
 *  0b101..LFSR 17, tap mask 11110000000000000
 *  0b110..Reserved
 *  0b111..Reserved
 */
#define XCVR_PLL_DIG_HPM_CTRL_HPM_LFSR_SIZE(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_LFSR_SIZE_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_LFSR_SIZE_MASK)

#define XCVR_PLL_DIG_HPM_CTRL_RX_HPM_CAL_EN_MASK (0x80000U)
#define XCVR_PLL_DIG_HPM_CTRL_RX_HPM_CAL_EN_SHIFT (19U)
/*! RX_HPM_CAL_EN - Receive HPM Calibration Enable
 */
#define XCVR_PLL_DIG_HPM_CTRL_RX_HPM_CAL_EN(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_RX_HPM_CAL_EN_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_RX_HPM_CAL_EN_MASK)

#define XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_SCL_MASK   (0x100000U)
#define XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_SCL_SHIFT  (20U)
/*! HPM_DTH_SCL - HPM Dither Scale
 */
#define XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_SCL(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_SCL_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_SCL_MASK)

#define XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_EN_MASK    (0x800000U)
#define XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_EN_SHIFT   (23U)
/*! HPM_DTH_EN - Dither Enable for HPM LFSR
 */
#define XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_EN(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_EN_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_EN_MASK)

#define XCVR_PLL_DIG_HPM_CTRL_HPM_SCALE_MASK     (0x7000000U)
#define XCVR_PLL_DIG_HPM_CTRL_HPM_SCALE_SHIFT    (24U)
/*! HPM_SCALE - High Port Modulation Scale
 *  0b000..No Scaling
 *  0b001..Divide by 2
 *  0b010..Multiply by 2
 *  0b011..Multiply by 4
 *  0b100..Divide by 4
 *  0b101..Multiply by 8
 *  0b110..Divide by 8
 *  0b111..N/A
 */
#define XCVR_PLL_DIG_HPM_CTRL_HPM_SCALE(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_SCALE_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_SCALE_MASK)

#define XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_INVERT_MASK (0x8000000U)
#define XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_INVERT_SHIFT (27U)
/*! HPM_INTEGER_INVERT - Invert High Port Modulation Integer
 */
#define XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_INVERT_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_INVERT_MASK)

#define XCVR_PLL_DIG_HPM_CTRL_HPM_CAL_INVERT_MASK (0x10000000U)
#define XCVR_PLL_DIG_HPM_CTRL_HPM_CAL_INVERT_SHIFT (28U)
/*! HPM_CAL_INVERT - Invert High Port Modulator Calibration
 */
#define XCVR_PLL_DIG_HPM_CTRL_HPM_CAL_INVERT(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_CAL_INVERT_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_CAL_INVERT_MASK)

#define XCVR_PLL_DIG_HPM_CTRL_HPM_CAL_TIME_MASK  (0x60000000U)
#define XCVR_PLL_DIG_HPM_CTRL_HPM_CAL_TIME_SHIFT (29U)
/*! HPM_CAL_TIME - High Port Modulation Calibration Time
 *  0b00..25 us
 *  0b01..50 us
 *  0b10..100 us
 *  0b11..N/A
 */
#define XCVR_PLL_DIG_HPM_CTRL_HPM_CAL_TIME(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_CAL_TIME_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_CAL_TIME_MASK)

#define XCVR_PLL_DIG_HPM_CTRL_HPM_MOD_IN_INVERT_MASK (0x80000000U)
#define XCVR_PLL_DIG_HPM_CTRL_HPM_MOD_IN_INVERT_SHIFT (31U)
/*! HPM_MOD_IN_INVERT - Invert High Port Modulation
 */
#define XCVR_PLL_DIG_HPM_CTRL_HPM_MOD_IN_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_MOD_IN_INVERT_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_MOD_IN_INVERT_MASK)
/*! @} */

/*! @name HPMCAL_CTRL - PLL High Port Calibration Control */
/*! @{ */

#define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_FACTOR_MASK (0x1FFFU)
#define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_FACTOR_SHIFT (0U)
/*! HPM_CAL_FACTOR - High Port Modulation Calibration Factor
 */
#define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_FACTOR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_FACTOR_SHIFT)) & XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_FACTOR_MASK)

#define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_ARRAY_SIZE_MASK (0x2000U)
#define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_ARRAY_SIZE_SHIFT (13U)
/*! HPM_CAL_ARRAY_SIZE - High Port Modulation Calibration Array Size
 *  0b0..128
 *  0b1..256
 */
#define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_ARRAY_SIZE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_ARRAY_SIZE_SHIFT)) & XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_ARRAY_SIZE_MASK)

#define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_COUNT_SCALE_MASK (0x4000U)
#define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_COUNT_SCALE_SHIFT (14U)
/*! HPM_CAL_COUNT_SCALE - HPM_CAL_COUNT_SCALE
 */
#define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_COUNT_SCALE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_COUNT_SCALE_SHIFT)) & XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_COUNT_SCALE_MASK)

#define XCVR_PLL_DIG_HPMCAL_CTRL_HP_CAL_DISABLE_MASK (0x8000U)
#define XCVR_PLL_DIG_HPMCAL_CTRL_HP_CAL_DISABLE_SHIFT (15U)
/*! HP_CAL_DISABLE - Disable HPM Manual Calibration
 */
#define XCVR_PLL_DIG_HPMCAL_CTRL_HP_CAL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPMCAL_CTRL_HP_CAL_DISABLE_SHIFT)) & XCVR_PLL_DIG_HPMCAL_CTRL_HP_CAL_DISABLE_MASK)

#define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_FACTOR_MANUAL_MASK (0x1FFF0000U)
#define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_FACTOR_MANUAL_SHIFT (16U)
/*! HPM_CAL_FACTOR_MANUAL - Manual HPM Calibration Factor
 */
#define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_FACTOR_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_FACTOR_MANUAL_SHIFT)) & XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_FACTOR_MANUAL_MASK)

#define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_SKIP_MASK (0x20000000U)
#define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_SKIP_SHIFT (29U)
/*! HPM_CAL_SKIP - HPM_CAL_SKIP
 */
#define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_SKIP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_SKIP_SHIFT)) & XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_SKIP_MASK)

#define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_BUMPED_MASK (0xC0000000U)
#define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_BUMPED_SHIFT (30U)
/*! HPM_CAL_BUMPED - HPM_CAL_BUMPED
 *  0b00..No calibration boost
 *  0b01..x2
 *  0b10..x4
 *  0b11..x8
 */
#define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_BUMPED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_BUMPED_SHIFT)) & XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_BUMPED_MASK)
/*! @} */

/*! @name HPM_CAL1 - PLL High Port Calibration Result 1 */
/*! @{ */

#define XCVR_PLL_DIG_HPM_CAL1_HPM_COUNT_1_MASK   (0x7FFFFU)
#define XCVR_PLL_DIG_HPM_CAL1_HPM_COUNT_1_SHIFT  (0U)
/*! HPM_COUNT_1 - High Port Modulation Counter Value 1
 */
#define XCVR_PLL_DIG_HPM_CAL1_HPM_COUNT_1(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CAL1_HPM_COUNT_1_SHIFT)) & XCVR_PLL_DIG_HPM_CAL1_HPM_COUNT_1_MASK)
/*! @} */

/*! @name HPM_CAL2 - PLL High Port Calibration Result 2 */
/*! @{ */

#define XCVR_PLL_DIG_HPM_CAL2_HPM_COUNT_2_MASK   (0x7FFFFU)
#define XCVR_PLL_DIG_HPM_CAL2_HPM_COUNT_2_SHIFT  (0U)
/*! HPM_COUNT_2 - High Port Modulation Counter Value 2
 */
#define XCVR_PLL_DIG_HPM_CAL2_HPM_COUNT_2(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CAL2_HPM_COUNT_2_SHIFT)) & XCVR_PLL_DIG_HPM_CAL2_HPM_COUNT_2_MASK)
/*! @} */

/*! @name HPM_SDM_RES - PLL High Port Sigma Delta Results */
/*! @{ */

#define XCVR_PLL_DIG_HPM_SDM_RES_HPM_NUM_SELECTED_MASK (0x3FFU)
#define XCVR_PLL_DIG_HPM_SDM_RES_HPM_NUM_SELECTED_SHIFT (0U)
/*! HPM_NUM_SELECTED - High Port Modulator SDM Numerator
 */
#define XCVR_PLL_DIG_HPM_SDM_RES_HPM_NUM_SELECTED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_SDM_RES_HPM_NUM_SELECTED_SHIFT)) & XCVR_PLL_DIG_HPM_SDM_RES_HPM_NUM_SELECTED_MASK)

#define XCVR_PLL_DIG_HPM_SDM_RES_HPM_DENOM_MASK  (0x3FF0000U)
#define XCVR_PLL_DIG_HPM_SDM_RES_HPM_DENOM_SHIFT (16U)
/*! HPM_DENOM - High Port Modulator SDM Denominator
 */
#define XCVR_PLL_DIG_HPM_SDM_RES_HPM_DENOM(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_SDM_RES_HPM_DENOM_SHIFT)) & XCVR_PLL_DIG_HPM_SDM_RES_HPM_DENOM_MASK)

#define XCVR_PLL_DIG_HPM_SDM_RES_HPM_COUNT_ADJUST_MASK (0xF0000000U)
#define XCVR_PLL_DIG_HPM_SDM_RES_HPM_COUNT_ADJUST_SHIFT (28U)
/*! HPM_COUNT_ADJUST - HPM_COUNT_ADJUST
 */
#define XCVR_PLL_DIG_HPM_SDM_RES_HPM_COUNT_ADJUST(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_SDM_RES_HPM_COUNT_ADJUST_SHIFT)) & XCVR_PLL_DIG_HPM_SDM_RES_HPM_COUNT_ADJUST_MASK)
/*! @} */

/*! @name LPM_CTRL - PLL Low Port Modulator Control */
/*! @{ */

#define XCVR_PLL_DIG_LPM_CTRL_PLL_LD_MANUAL_MASK (0x1FU)
#define XCVR_PLL_DIG_LPM_CTRL_PLL_LD_MANUAL_SHIFT (0U)
/*! PLL_LD_MANUAL - Manual PLL Loop Divider value
 */
#define XCVR_PLL_DIG_LPM_CTRL_PLL_LD_MANUAL(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_PLL_LD_MANUAL_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_PLL_LD_MANUAL_MASK)

#define XCVR_PLL_DIG_LPM_CTRL_HPM_CAL_SCALE_MASK (0xF00U)
#define XCVR_PLL_DIG_LPM_CTRL_HPM_CAL_SCALE_SHIFT (8U)
/*! HPM_CAL_SCALE - High Port Calibration Word Scaling
 *  0b0000-0b0010..No Scaling
 *  0b0011..Divide by 32
 *  0b0100..Divide by 16
 *  0b0101..Divide by 8
 *  0b0110..Divide by 4
 *  0b0111..Divide by 2
 *  0b1000..No Scaling
 *  0b1001..Multiply by 2
 *  0b1010..Multiply by 4
 *  0b1011..Multiply by 8
 *  0b1011-0b1111..No Scaling
 */
#define XCVR_PLL_DIG_LPM_CTRL_HPM_CAL_SCALE(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_HPM_CAL_SCALE_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_HPM_CAL_SCALE_MASK)

#define XCVR_PLL_DIG_LPM_CTRL_PLL_LD_DISABLE_MASK (0x1000U)
#define XCVR_PLL_DIG_LPM_CTRL_PLL_LD_DISABLE_SHIFT (12U)
/*! PLL_LD_DISABLE - Disable PLL Loop Divider
 */
#define XCVR_PLL_DIG_LPM_CTRL_PLL_LD_DISABLE(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_PLL_LD_DISABLE_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_PLL_LD_DISABLE_MASK)

#define XCVR_PLL_DIG_LPM_CTRL_LPFF_MASK          (0x2000U)
#define XCVR_PLL_DIG_LPM_CTRL_LPFF_SHIFT         (13U)
/*! LPFF - LPM SDM Invalid Flag
 */
#define XCVR_PLL_DIG_LPM_CTRL_LPFF(x)            (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_LPFF_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_LPFF_MASK)

#define XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_INV_MASK   (0x4000U)
#define XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_INV_SHIFT  (14U)
/*! LPM_SDM_INV - Invert LPM SDM
 */
#define XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_INV(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_INV_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_INV_MASK)

#define XCVR_PLL_DIG_LPM_CTRL_LPM_DISABLE_MASK   (0x8000U)
#define XCVR_PLL_DIG_LPM_CTRL_LPM_DISABLE_SHIFT  (15U)
/*! LPM_DISABLE - Disable LPM SDM
 */
#define XCVR_PLL_DIG_LPM_CTRL_LPM_DISABLE(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_LPM_DISABLE_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_LPM_DISABLE_MASK)

#define XCVR_PLL_DIG_LPM_CTRL_LPM_DTH_SCL_MASK   (0xF0000U)
#define XCVR_PLL_DIG_LPM_CTRL_LPM_DTH_SCL_SHIFT  (16U)
/*! LPM_DTH_SCL - LPM Dither Scale
 *  0b0000..Reserved
 *  0b0001..Reserved
 *  0b0010..Reserved
 *  0b0011..Reserved
 *  0b0100..Reserved
 *  0b0101..-128 to 96
 *  0b0110..-256 to 192
 *  0b0111..-512 to 384
 *  0b1000..-1024 to 768
 *  0b1001..-2048 to 1536
 *  0b1010..-4096 to 3072
 *  0b1011..-8192 to 6144
 *  0b1100..Reserved
 *  0b1101..Reserved
 *  0b1110..Reserved
 *  0b1111..Reserved
 */
#define XCVR_PLL_DIG_LPM_CTRL_LPM_DTH_SCL(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_LPM_DTH_SCL_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_LPM_DTH_SCL_MASK)

#define XCVR_PLL_DIG_LPM_CTRL_LPM_D_CTRL_MASK    (0x400000U)
#define XCVR_PLL_DIG_LPM_CTRL_LPM_D_CTRL_SHIFT   (22U)
/*! LPM_D_CTRL - LPM Dither Control in Override Mode
 */
#define XCVR_PLL_DIG_LPM_CTRL_LPM_D_CTRL(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_LPM_D_CTRL_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_LPM_D_CTRL_MASK)

#define XCVR_PLL_DIG_LPM_CTRL_LPM_D_OVRD_MASK    (0x800000U)
#define XCVR_PLL_DIG_LPM_CTRL_LPM_D_OVRD_SHIFT   (23U)
/*! LPM_D_OVRD - LPM Dither Override Mode Select
 */
#define XCVR_PLL_DIG_LPM_CTRL_LPM_D_OVRD(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_LPM_D_OVRD_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_LPM_D_OVRD_MASK)

#define XCVR_PLL_DIG_LPM_CTRL_LPM_SCALE_MASK     (0xF000000U)
#define XCVR_PLL_DIG_LPM_CTRL_LPM_SCALE_SHIFT    (24U)
/*! LPM_SCALE - LPM Scale Factor
 *  0b0000..No Scaling
 *  0b0001..Multiply by 2
 *  0b0010..Multiply by 4
 *  0b0011..Multiply by 8
 *  0b0100..Multiply by 16
 *  0b0101..Multiply by 32
 *  0b0110..Multiply by 64
 *  0b0111..Multiply by 128
 *  0b1000..Multiply by 256
 *  0b1001..Multiply by 512
 *  0b1010..Multiply by 1024
 *  0b1011..Multiply by 2048
 *  0b1100..Reserved
 *  0b1101..Reserved
 *  0b1110..Reserved
 *  0b1111..Reserved
 */
#define XCVR_PLL_DIG_LPM_CTRL_LPM_SCALE(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_LPM_SCALE_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_LPM_SCALE_MASK)

#define XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_USE_NEG_MASK (0x80000000U)
#define XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_USE_NEG_SHIFT (31U)
/*! LPM_SDM_USE_NEG - Use the Negedge of the Sigma Delta clock
 */
#define XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_USE_NEG(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_USE_NEG_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_USE_NEG_MASK)
/*! @} */

/*! @name LPM_SDM_CTRL1 - PLL Low Port Sigma Delta Control 1 */
/*! @{ */

#define XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SELECTED_MASK (0x7FU)
#define XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SELECTED_SHIFT (0U)
/*! LPM_INTG_SELECTED - Low Port Modulation Integer Value Selected
 */
#define XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SELECTED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SELECTED_SHIFT)) & XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SELECTED_MASK)

#define XCVR_PLL_DIG_LPM_SDM_CTRL1_HPM_ARRAY_BIAS_MASK (0x7F00U)
#define XCVR_PLL_DIG_LPM_SDM_CTRL1_HPM_ARRAY_BIAS_SHIFT (8U)
/*! HPM_ARRAY_BIAS - Bias value for High Port DAC Array Midpoint
 */
#define XCVR_PLL_DIG_LPM_SDM_CTRL1_HPM_ARRAY_BIAS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_SDM_CTRL1_HPM_ARRAY_BIAS_SHIFT)) & XCVR_PLL_DIG_LPM_SDM_CTRL1_HPM_ARRAY_BIAS_MASK)

#define XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_MASK (0x7F0000U)
#define XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SHIFT (16U)
/*! LPM_INTG - Manual Low Port Modulation Integer Value
 */
#define XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SHIFT)) & XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_MASK)

#define XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_MASK (0x80000000U)
#define XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_SHIFT (31U)
/*! SDM_MAP_DISABLE - Disable SDM Mapping
 */
#define XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_SHIFT)) & XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_MASK)
/*! @} */

/*! @name LPM_SDM_CTRL2 - PLL Low Port Sigma Delta Control 2 */
/*! @{ */

#define XCVR_PLL_DIG_LPM_SDM_CTRL2_LPM_NUM_MASK  (0xFFFFFFFU)
#define XCVR_PLL_DIG_LPM_SDM_CTRL2_LPM_NUM_SHIFT (0U)
/*! LPM_NUM - Low Port Modulation Numerator
 */
#define XCVR_PLL_DIG_LPM_SDM_CTRL2_LPM_NUM(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_SDM_CTRL2_LPM_NUM_SHIFT)) & XCVR_PLL_DIG_LPM_SDM_CTRL2_LPM_NUM_MASK)
/*! @} */

/*! @name LPM_SDM_CTRL3 - PLL Low Port Sigma Delta Control 3 */
/*! @{ */

#define XCVR_PLL_DIG_LPM_SDM_CTRL3_LPM_DENOM_MASK (0xFFFFFFFU)
#define XCVR_PLL_DIG_LPM_SDM_CTRL3_LPM_DENOM_SHIFT (0U)
/*! LPM_DENOM - Low Port Modulation Denominator
 */
#define XCVR_PLL_DIG_LPM_SDM_CTRL3_LPM_DENOM(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_SDM_CTRL3_LPM_DENOM_SHIFT)) & XCVR_PLL_DIG_LPM_SDM_CTRL3_LPM_DENOM_MASK)
/*! @} */

/*! @name LPM_SDM_RES1 - PLL Low Port Sigma Delta Result 1 */
/*! @{ */

#define XCVR_PLL_DIG_LPM_SDM_RES1_LPM_NUM_SELECTED_MASK (0xFFFFFFFU)
#define XCVR_PLL_DIG_LPM_SDM_RES1_LPM_NUM_SELECTED_SHIFT (0U)
/*! LPM_NUM_SELECTED - Low Port Modulation Numerator Applied
 */
#define XCVR_PLL_DIG_LPM_SDM_RES1_LPM_NUM_SELECTED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_SDM_RES1_LPM_NUM_SELECTED_SHIFT)) & XCVR_PLL_DIG_LPM_SDM_RES1_LPM_NUM_SELECTED_MASK)
/*! @} */

/*! @name LPM_SDM_RES2 - PLL Low Port Sigma Delta Result 2 */
/*! @{ */

#define XCVR_PLL_DIG_LPM_SDM_RES2_LPM_DENOM_SELECTED_MASK (0xFFFFFFFU)
#define XCVR_PLL_DIG_LPM_SDM_RES2_LPM_DENOM_SELECTED_SHIFT (0U)
/*! LPM_DENOM_SELECTED - Low Port Modulation Denominator Selected
 */
#define XCVR_PLL_DIG_LPM_SDM_RES2_LPM_DENOM_SELECTED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_SDM_RES2_LPM_DENOM_SELECTED_SHIFT)) & XCVR_PLL_DIG_LPM_SDM_RES2_LPM_DENOM_SELECTED_MASK)
/*! @} */

/*! @name DELAY_MATCH - PLL Delay Matching */
/*! @{ */

#define XCVR_PLL_DIG_DELAY_MATCH_LPM_SDM_DELAY_MASK (0xFU)
#define XCVR_PLL_DIG_DELAY_MATCH_LPM_SDM_DELAY_SHIFT (0U)
/*! LPM_SDM_DELAY - Low Port SDM Delay Matching
 */
#define XCVR_PLL_DIG_DELAY_MATCH_LPM_SDM_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_DELAY_MATCH_LPM_SDM_DELAY_SHIFT)) & XCVR_PLL_DIG_DELAY_MATCH_LPM_SDM_DELAY_MASK)

#define XCVR_PLL_DIG_DELAY_MATCH_HPM_SDM_DELAY_MASK (0xF00U)
#define XCVR_PLL_DIG_DELAY_MATCH_HPM_SDM_DELAY_SHIFT (8U)
/*! HPM_SDM_DELAY - High Port SDM Delay Matching
 */
#define XCVR_PLL_DIG_DELAY_MATCH_HPM_SDM_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_DELAY_MATCH_HPM_SDM_DELAY_SHIFT)) & XCVR_PLL_DIG_DELAY_MATCH_HPM_SDM_DELAY_MASK)

#define XCVR_PLL_DIG_DELAY_MATCH_HPM_INTEGER_DELAY_MASK (0xF0000U)
#define XCVR_PLL_DIG_DELAY_MATCH_HPM_INTEGER_DELAY_SHIFT (16U)
/*! HPM_INTEGER_DELAY - High Port Integer Delay Matching
 */
#define XCVR_PLL_DIG_DELAY_MATCH_HPM_INTEGER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_DELAY_MATCH_HPM_INTEGER_DELAY_SHIFT)) & XCVR_PLL_DIG_DELAY_MATCH_HPM_INTEGER_DELAY_MASK)
/*! @} */

/*! @name TUNING_CAP_TX_CTRL - Tuning Cap Settings in Transmit Mode */
/*! @{ */

#define XCVR_PLL_DIG_TUNING_CAP_TX_CTRL_TUNING_RANGE_0_MASK (0x7U)
#define XCVR_PLL_DIG_TUNING_CAP_TX_CTRL_TUNING_RANGE_0_SHIFT (0U)
/*! TUNING_RANGE_0 - Tuning Range 0
 */
#define XCVR_PLL_DIG_TUNING_CAP_TX_CTRL_TUNING_RANGE_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_TUNING_CAP_TX_CTRL_TUNING_RANGE_0_SHIFT)) & XCVR_PLL_DIG_TUNING_CAP_TX_CTRL_TUNING_RANGE_0_MASK)

#define XCVR_PLL_DIG_TUNING_CAP_TX_CTRL_TUNING_RANGE_1_MASK (0x38U)
#define XCVR_PLL_DIG_TUNING_CAP_TX_CTRL_TUNING_RANGE_1_SHIFT (3U)
/*! TUNING_RANGE_1 - Tuning Range 1
 */
#define XCVR_PLL_DIG_TUNING_CAP_TX_CTRL_TUNING_RANGE_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_TUNING_CAP_TX_CTRL_TUNING_RANGE_1_SHIFT)) & XCVR_PLL_DIG_TUNING_CAP_TX_CTRL_TUNING_RANGE_1_MASK)

#define XCVR_PLL_DIG_TUNING_CAP_TX_CTRL_TUNING_RANGE_2_MASK (0x1C0U)
#define XCVR_PLL_DIG_TUNING_CAP_TX_CTRL_TUNING_RANGE_2_SHIFT (6U)
/*! TUNING_RANGE_2 - Tuning Range 2
 */
#define XCVR_PLL_DIG_TUNING_CAP_TX_CTRL_TUNING_RANGE_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_TUNING_CAP_TX_CTRL_TUNING_RANGE_2_SHIFT)) & XCVR_PLL_DIG_TUNING_CAP_TX_CTRL_TUNING_RANGE_2_MASK)

#define XCVR_PLL_DIG_TUNING_CAP_TX_CTRL_TUNING_RANGE_3_MASK (0xE00U)
#define XCVR_PLL_DIG_TUNING_CAP_TX_CTRL_TUNING_RANGE_3_SHIFT (9U)
/*! TUNING_RANGE_3 - Tuning Range 3
 */
#define XCVR_PLL_DIG_TUNING_CAP_TX_CTRL_TUNING_RANGE_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_TUNING_CAP_TX_CTRL_TUNING_RANGE_3_SHIFT)) & XCVR_PLL_DIG_TUNING_CAP_TX_CTRL_TUNING_RANGE_3_MASK)

#define XCVR_PLL_DIG_TUNING_CAP_TX_CTRL_TUNING_RANGE_4_MASK (0x7000U)
#define XCVR_PLL_DIG_TUNING_CAP_TX_CTRL_TUNING_RANGE_4_SHIFT (12U)
/*! TUNING_RANGE_4 - Tuning Range 4
 */
#define XCVR_PLL_DIG_TUNING_CAP_TX_CTRL_TUNING_RANGE_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_TUNING_CAP_TX_CTRL_TUNING_RANGE_4_SHIFT)) & XCVR_PLL_DIG_TUNING_CAP_TX_CTRL_TUNING_RANGE_4_MASK)

#define XCVR_PLL_DIG_TUNING_CAP_TX_CTRL_TUNING_RANGE_5_MASK (0x38000U)
#define XCVR_PLL_DIG_TUNING_CAP_TX_CTRL_TUNING_RANGE_5_SHIFT (15U)
/*! TUNING_RANGE_5 - Tuning Range 5
 */
#define XCVR_PLL_DIG_TUNING_CAP_TX_CTRL_TUNING_RANGE_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_TUNING_CAP_TX_CTRL_TUNING_RANGE_5_SHIFT)) & XCVR_PLL_DIG_TUNING_CAP_TX_CTRL_TUNING_RANGE_5_MASK)

#define XCVR_PLL_DIG_TUNING_CAP_TX_CTRL_TUNING_RANGE_6_MASK (0x1C0000U)
#define XCVR_PLL_DIG_TUNING_CAP_TX_CTRL_TUNING_RANGE_6_SHIFT (18U)
/*! TUNING_RANGE_6 - Tuning Range 6
 */
#define XCVR_PLL_DIG_TUNING_CAP_TX_CTRL_TUNING_RANGE_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_TUNING_CAP_TX_CTRL_TUNING_RANGE_6_SHIFT)) & XCVR_PLL_DIG_TUNING_CAP_TX_CTRL_TUNING_RANGE_6_MASK)

#define XCVR_PLL_DIG_TUNING_CAP_TX_CTRL_TUNING_RANGE_7_MASK (0xE00000U)
#define XCVR_PLL_DIG_TUNING_CAP_TX_CTRL_TUNING_RANGE_7_SHIFT (21U)
/*! TUNING_RANGE_7 - Tuning Range 7
 */
#define XCVR_PLL_DIG_TUNING_CAP_TX_CTRL_TUNING_RANGE_7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_TUNING_CAP_TX_CTRL_TUNING_RANGE_7_SHIFT)) & XCVR_PLL_DIG_TUNING_CAP_TX_CTRL_TUNING_RANGE_7_MASK)
/*! @} */

/*! @name TUNING_CAP_RX_CTRL - Tuning Cap Settings in Receive Mode */
/*! @{ */

#define XCVR_PLL_DIG_TUNING_CAP_RX_CTRL_TUNING_RANGE_0_MASK (0x7U)
#define XCVR_PLL_DIG_TUNING_CAP_RX_CTRL_TUNING_RANGE_0_SHIFT (0U)
/*! TUNING_RANGE_0 - Tuning Range 0
 */
#define XCVR_PLL_DIG_TUNING_CAP_RX_CTRL_TUNING_RANGE_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_TUNING_CAP_RX_CTRL_TUNING_RANGE_0_SHIFT)) & XCVR_PLL_DIG_TUNING_CAP_RX_CTRL_TUNING_RANGE_0_MASK)

#define XCVR_PLL_DIG_TUNING_CAP_RX_CTRL_TUNING_RANGE_1_MASK (0x38U)
#define XCVR_PLL_DIG_TUNING_CAP_RX_CTRL_TUNING_RANGE_1_SHIFT (3U)
/*! TUNING_RANGE_1 - Tuning Range 1
 */
#define XCVR_PLL_DIG_TUNING_CAP_RX_CTRL_TUNING_RANGE_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_TUNING_CAP_RX_CTRL_TUNING_RANGE_1_SHIFT)) & XCVR_PLL_DIG_TUNING_CAP_RX_CTRL_TUNING_RANGE_1_MASK)

#define XCVR_PLL_DIG_TUNING_CAP_RX_CTRL_TUNING_RANGE_2_MASK (0x1C0U)
#define XCVR_PLL_DIG_TUNING_CAP_RX_CTRL_TUNING_RANGE_2_SHIFT (6U)
/*! TUNING_RANGE_2 - Tuning Range 2
 */
#define XCVR_PLL_DIG_TUNING_CAP_RX_CTRL_TUNING_RANGE_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_TUNING_CAP_RX_CTRL_TUNING_RANGE_2_SHIFT)) & XCVR_PLL_DIG_TUNING_CAP_RX_CTRL_TUNING_RANGE_2_MASK)

#define XCVR_PLL_DIG_TUNING_CAP_RX_CTRL_TUNING_RANGE_3_MASK (0xE00U)
#define XCVR_PLL_DIG_TUNING_CAP_RX_CTRL_TUNING_RANGE_3_SHIFT (9U)
/*! TUNING_RANGE_3 - Tuning Range 3
 */
#define XCVR_PLL_DIG_TUNING_CAP_RX_CTRL_TUNING_RANGE_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_TUNING_CAP_RX_CTRL_TUNING_RANGE_3_SHIFT)) & XCVR_PLL_DIG_TUNING_CAP_RX_CTRL_TUNING_RANGE_3_MASK)

#define XCVR_PLL_DIG_TUNING_CAP_RX_CTRL_TUNING_RANGE_4_MASK (0x7000U)
#define XCVR_PLL_DIG_TUNING_CAP_RX_CTRL_TUNING_RANGE_4_SHIFT (12U)
/*! TUNING_RANGE_4 - Tuning Range 4
 */
#define XCVR_PLL_DIG_TUNING_CAP_RX_CTRL_TUNING_RANGE_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_TUNING_CAP_RX_CTRL_TUNING_RANGE_4_SHIFT)) & XCVR_PLL_DIG_TUNING_CAP_RX_CTRL_TUNING_RANGE_4_MASK)

#define XCVR_PLL_DIG_TUNING_CAP_RX_CTRL_TUNING_RANGE_5_MASK (0x38000U)
#define XCVR_PLL_DIG_TUNING_CAP_RX_CTRL_TUNING_RANGE_5_SHIFT (15U)
/*! TUNING_RANGE_5 - Tuning Range 5
 */
#define XCVR_PLL_DIG_TUNING_CAP_RX_CTRL_TUNING_RANGE_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_TUNING_CAP_RX_CTRL_TUNING_RANGE_5_SHIFT)) & XCVR_PLL_DIG_TUNING_CAP_RX_CTRL_TUNING_RANGE_5_MASK)

#define XCVR_PLL_DIG_TUNING_CAP_RX_CTRL_TUNING_RANGE_6_MASK (0x1C0000U)
#define XCVR_PLL_DIG_TUNING_CAP_RX_CTRL_TUNING_RANGE_6_SHIFT (18U)
/*! TUNING_RANGE_6 - Tuning Range 6
 */
#define XCVR_PLL_DIG_TUNING_CAP_RX_CTRL_TUNING_RANGE_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_TUNING_CAP_RX_CTRL_TUNING_RANGE_6_SHIFT)) & XCVR_PLL_DIG_TUNING_CAP_RX_CTRL_TUNING_RANGE_6_MASK)

#define XCVR_PLL_DIG_TUNING_CAP_RX_CTRL_TUNING_RANGE_7_MASK (0xE00000U)
#define XCVR_PLL_DIG_TUNING_CAP_RX_CTRL_TUNING_RANGE_7_SHIFT (21U)
/*! TUNING_RANGE_7 - Tuning Range 7
 */
#define XCVR_PLL_DIG_TUNING_CAP_RX_CTRL_TUNING_RANGE_7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_TUNING_CAP_RX_CTRL_TUNING_RANGE_7_SHIFT)) & XCVR_PLL_DIG_TUNING_CAP_RX_CTRL_TUNING_RANGE_7_MASK)
/*! @} */

/*! @name MAX_TX_CFG1_FREQ - Max Transmit Frequency For TX Configuration 1 */
/*! @{ */

#define XCVR_PLL_DIG_MAX_TX_CFG1_FREQ_MAX_TX_CFG1_FREQ_MASK (0xFFFU)
#define XCVR_PLL_DIG_MAX_TX_CFG1_FREQ_MAX_TX_CFG1_FREQ_SHIFT (0U)
/*! MAX_TX_CFG1_FREQ - Maximum Transmit Frequency for Standard TX Settings
 */
#define XCVR_PLL_DIG_MAX_TX_CFG1_FREQ_MAX_TX_CFG1_FREQ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_MAX_TX_CFG1_FREQ_MAX_TX_CFG1_FREQ_SHIFT)) & XCVR_PLL_DIG_MAX_TX_CFG1_FREQ_MAX_TX_CFG1_FREQ_MASK)
/*! @} */

/*! @name CTUNE_CTRL - PLL Coarse Tune Control */
/*! @{ */

#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL_MASK (0xFFFU)
#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL_SHIFT (0U)
/*! CTUNE_TARGET_MANUAL - Manual Coarse Tune Target
 */
#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL_SHIFT)) & XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL_MASK)

#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_CNTR_RLS_RST_MASK (0x7000U)
#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_CNTR_RLS_RST_SHIFT (12U)
/*! CTUNE_CNTR_RLS_RST - Coarse Tune Counter Release Reset
 */
#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_CNTR_RLS_RST(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_CNTR_RLS_RST_SHIFT)) & XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_CNTR_RLS_RST_MASK)

#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_DISABLE_MASK (0x8000U)
#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_DISABLE_SHIFT (15U)
/*! CTUNE_TARGET_DISABLE - Disable Coarse Tune Target
 */
#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_DISABLE_SHIFT)) & XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_DISABLE_MASK)

#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_ADJUST_MASK (0xF0000U)
#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_ADJUST_SHIFT (16U)
/*! CTUNE_ADJUST - Coarse Tune Count Adjustment
 */
#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_ADJUST(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_ADJUST_SHIFT)) & XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_ADJUST_MASK)

#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_MANUAL_MASK (0xFF00000U)
#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_MANUAL_SHIFT (20U)
/*! CTUNE_MANUAL - Manual Coarse Tune Setting
 */
#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_MANUAL(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_MANUAL_SHIFT)) & XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_MANUAL_MASK)

#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_DISABLE_MASK (0x80000000U)
#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_DISABLE_SHIFT (31U)
/*! CTUNE_DISABLE - Coarse Tune Disable
 */
#define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_DISABLE_SHIFT)) & XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_DISABLE_MASK)
/*! @} */

/*! @name DATA_RATE_OVRD_CTRL1 - PLL Data Rate Override Control */
/*! @{ */

#define XCVR_PLL_DIG_DATA_RATE_OVRD_CTRL1_HPM_CAL_SCALE_CFG1_MASK (0xFU)
#define XCVR_PLL_DIG_DATA_RATE_OVRD_CTRL1_HPM_CAL_SCALE_CFG1_SHIFT (0U)
/*! HPM_CAL_SCALE_CFG1 - HPM Scale Configuration1
 */
#define XCVR_PLL_DIG_DATA_RATE_OVRD_CTRL1_HPM_CAL_SCALE_CFG1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_DATA_RATE_OVRD_CTRL1_HPM_CAL_SCALE_CFG1_SHIFT)) & XCVR_PLL_DIG_DATA_RATE_OVRD_CTRL1_HPM_CAL_SCALE_CFG1_MASK)

#define XCVR_PLL_DIG_DATA_RATE_OVRD_CTRL1_LPM_SCALE_CFG1_MASK (0xF0U)
#define XCVR_PLL_DIG_DATA_RATE_OVRD_CTRL1_LPM_SCALE_CFG1_SHIFT (4U)
/*! LPM_SCALE_CFG1 - LPM Scale Configuration1
 */
#define XCVR_PLL_DIG_DATA_RATE_OVRD_CTRL1_LPM_SCALE_CFG1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_DATA_RATE_OVRD_CTRL1_LPM_SCALE_CFG1_SHIFT)) & XCVR_PLL_DIG_DATA_RATE_OVRD_CTRL1_LPM_SCALE_CFG1_MASK)

#define XCVR_PLL_DIG_DATA_RATE_OVRD_CTRL1_HPM_FDB_RES_CAL_CFG1_MASK (0x300U)
#define XCVR_PLL_DIG_DATA_RATE_OVRD_CTRL1_HPM_FDB_RES_CAL_CFG1_SHIFT (8U)
/*! HPM_FDB_RES_CAL_CFG1 - HPM FDB RES Calibration Configuration1
 */
#define XCVR_PLL_DIG_DATA_RATE_OVRD_CTRL1_HPM_FDB_RES_CAL_CFG1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_DATA_RATE_OVRD_CTRL1_HPM_FDB_RES_CAL_CFG1_SHIFT)) & XCVR_PLL_DIG_DATA_RATE_OVRD_CTRL1_HPM_FDB_RES_CAL_CFG1_MASK)

#define XCVR_PLL_DIG_DATA_RATE_OVRD_CTRL1_HPM_FDB_RES_TX_CFG1_MASK (0xC00U)
#define XCVR_PLL_DIG_DATA_RATE_OVRD_CTRL1_HPM_FDB_RES_TX_CFG1_SHIFT (10U)
/*! HPM_FDB_RES_TX_CFG1 - HPM FDB RES Transmit Configuration1
 */
#define XCVR_PLL_DIG_DATA_RATE_OVRD_CTRL1_HPM_FDB_RES_TX_CFG1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_DATA_RATE_OVRD_CTRL1_HPM_FDB_RES_TX_CFG1_SHIFT)) & XCVR_PLL_DIG_DATA_RATE_OVRD_CTRL1_HPM_FDB_RES_TX_CFG1_MASK)
/*! @} */

/*! @name DATA_RATE_OVRD_CTRL2 - PLL Data Rate Override Control */
/*! @{ */

#define XCVR_PLL_DIG_DATA_RATE_OVRD_CTRL2_NUM_OFFSET_CFG1_MASK (0xFFFFFFFU)
#define XCVR_PLL_DIG_DATA_RATE_OVRD_CTRL2_NUM_OFFSET_CFG1_SHIFT (0U)
/*! NUM_OFFSET_CFG1 - Numerator Offset Configuration1
 */
#define XCVR_PLL_DIG_DATA_RATE_OVRD_CTRL2_NUM_OFFSET_CFG1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_DATA_RATE_OVRD_CTRL2_NUM_OFFSET_CFG1_SHIFT)) & XCVR_PLL_DIG_DATA_RATE_OVRD_CTRL2_NUM_OFFSET_CFG1_MASK)
/*! @} */

/*! @name CTUNE_RES - PLL Coarse Tune Results */
/*! @{ */

#define XCVR_PLL_DIG_CTUNE_RES_CTUNE_SELECTED_MASK (0xFFU)
#define XCVR_PLL_DIG_CTUNE_RES_CTUNE_SELECTED_SHIFT (0U)
/*! CTUNE_SELECTED - Coarse Tune Setting to VCO
 */
#define XCVR_PLL_DIG_CTUNE_RES_CTUNE_SELECTED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_RES_CTUNE_SELECTED_SHIFT)) & XCVR_PLL_DIG_CTUNE_RES_CTUNE_SELECTED_MASK)

#define XCVR_PLL_DIG_CTUNE_RES_CTUNE_BEST_DIFF_MASK (0x3FC00U)
#define XCVR_PLL_DIG_CTUNE_RES_CTUNE_BEST_DIFF_SHIFT (10U)
/*! CTUNE_BEST_DIFF - Coarse Tune Absolute Best Difference
 */
#define XCVR_PLL_DIG_CTUNE_RES_CTUNE_BEST_DIFF(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_RES_CTUNE_BEST_DIFF_SHIFT)) & XCVR_PLL_DIG_CTUNE_RES_CTUNE_BEST_DIFF_MASK)

#define XCVR_PLL_DIG_CTUNE_RES_CTUNE_FREQ_SELECTED_MASK (0x3FFC0000U)
#define XCVR_PLL_DIG_CTUNE_RES_CTUNE_FREQ_SELECTED_SHIFT (18U)
/*! CTUNE_FREQ_SELECTED - Coarse Tune Frequency Selected
 */
#define XCVR_PLL_DIG_CTUNE_RES_CTUNE_FREQ_SELECTED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_RES_CTUNE_FREQ_SELECTED_SHIFT)) & XCVR_PLL_DIG_CTUNE_RES_CTUNE_FREQ_SELECTED_MASK)
/*! @} */

/*! @name HPM_CAL_TIMING - PLL HPM Calibration Timing Attributes */
/*! @{ */

#define XCVR_PLL_DIG_HPM_CAL_TIMING_HPM_CTUNE_SETTLE_TIME_MASK (0xFU)
#define XCVR_PLL_DIG_HPM_CAL_TIMING_HPM_CTUNE_SETTLE_TIME_SHIFT (0U)
/*! HPM_CTUNE_SETTLE_TIME - CTUNE Settling Time
 */
#define XCVR_PLL_DIG_HPM_CAL_TIMING_HPM_CTUNE_SETTLE_TIME(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CAL_TIMING_HPM_CTUNE_SETTLE_TIME_SHIFT)) & XCVR_PLL_DIG_HPM_CAL_TIMING_HPM_CTUNE_SETTLE_TIME_MASK)

#define XCVR_PLL_DIG_HPM_CAL_TIMING_HPM_CAL1_SETTLE_TIME_MASK (0xF0U)
#define XCVR_PLL_DIG_HPM_CAL_TIMING_HPM_CAL1_SETTLE_TIME_SHIFT (4U)
/*! HPM_CAL1_SETTLE_TIME - HPM Calibration1 Settling Time
 */
#define XCVR_PLL_DIG_HPM_CAL_TIMING_HPM_CAL1_SETTLE_TIME(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CAL_TIMING_HPM_CAL1_SETTLE_TIME_SHIFT)) & XCVR_PLL_DIG_HPM_CAL_TIMING_HPM_CAL1_SETTLE_TIME_MASK)

#define XCVR_PLL_DIG_HPM_CAL_TIMING_HPM_CAL2_SETTLE_TIME_MASK (0xF00U)
#define XCVR_PLL_DIG_HPM_CAL_TIMING_HPM_CAL2_SETTLE_TIME_SHIFT (8U)
/*! HPM_CAL2_SETTLE_TIME - HPM Calibration2 Settling Time
 */
#define XCVR_PLL_DIG_HPM_CAL_TIMING_HPM_CAL2_SETTLE_TIME(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CAL_TIMING_HPM_CAL2_SETTLE_TIME_SHIFT)) & XCVR_PLL_DIG_HPM_CAL_TIMING_HPM_CAL2_SETTLE_TIME_MASK)

#define XCVR_PLL_DIG_HPM_CAL_TIMING_HPM_VCO_MOD_DELAY_MASK (0xFFFF0000U)
#define XCVR_PLL_DIG_HPM_CAL_TIMING_HPM_VCO_MOD_DELAY_SHIFT (16U)
/*! HPM_VCO_MOD_DELAY - HPM VCO Modification Output Delay
 */
#define XCVR_PLL_DIG_HPM_CAL_TIMING_HPM_VCO_MOD_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CAL_TIMING_HPM_VCO_MOD_DELAY_SHIFT)) & XCVR_PLL_DIG_HPM_CAL_TIMING_HPM_VCO_MOD_DELAY_MASK)
/*! @} */

/*! @name PLL_OFFSET_CTRL - PLL Offset Control */
/*! @{ */

#define XCVR_PLL_DIG_PLL_OFFSET_CTRL_PLL_NUMERATOR_OFFSET_MASK (0xFFFFFFFU)
#define XCVR_PLL_DIG_PLL_OFFSET_CTRL_PLL_NUMERATOR_OFFSET_SHIFT (0U)
/*! PLL_NUMERATOR_OFFSET - PLL Numerator Offset
 */
#define XCVR_PLL_DIG_PLL_OFFSET_CTRL_PLL_NUMERATOR_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_PLL_OFFSET_CTRL_PLL_NUMERATOR_OFFSET_SHIFT)) & XCVR_PLL_DIG_PLL_OFFSET_CTRL_PLL_NUMERATOR_OFFSET_MASK)
/*! @} */

/*! @name PLL_DATARATE_CTRL - PLL Data Rate Switch Control */
/*! @{ */

#define XCVR_PLL_DIG_PLL_DATARATE_CTRL_HPM_VCM_TX_DRS_MASK (0x7U)
#define XCVR_PLL_DIG_PLL_DATARATE_CTRL_HPM_VCM_TX_DRS_SHIFT (0U)
/*! HPM_VCM_TX_DRS - Data Rate Switch for hpm_vcm_tx
 *  0b000..432 mV
 *  0b001..328 mV
 *  0b010..456 mV
 *  0b011..473 mV
 *  0b100..488 mV
 *  0b101..408 mV
 *  0b110..392 mV
 *  0b111..376 mV
 */
#define XCVR_PLL_DIG_PLL_DATARATE_CTRL_HPM_VCM_TX_DRS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_PLL_DATARATE_CTRL_HPM_VCM_TX_DRS_SHIFT)) & XCVR_PLL_DIG_PLL_DATARATE_CTRL_HPM_VCM_TX_DRS_MASK)

#define XCVR_PLL_DIG_PLL_DATARATE_CTRL_HPM_VCM_CAL_DRS_MASK (0x70U)
#define XCVR_PLL_DIG_PLL_DATARATE_CTRL_HPM_VCM_CAL_DRS_SHIFT (4U)
/*! HPM_VCM_CAL_DRS - Data Rate Switch for hpm_vcm_cal
 *  0b000..432 mV
 *  0b001..328 mV
 *  0b010..456 mV
 *  0b011..473 mV
 *  0b100..488 mV
 *  0b101..408 mV
 *  0b110..392 mV
 *  0b111..376 mV
 */
#define XCVR_PLL_DIG_PLL_DATARATE_CTRL_HPM_VCM_CAL_DRS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_PLL_DATARATE_CTRL_HPM_VCM_CAL_DRS_SHIFT)) & XCVR_PLL_DIG_PLL_DATARATE_CTRL_HPM_VCM_CAL_DRS_MASK)

#define XCVR_PLL_DIG_PLL_DATARATE_CTRL_PLL_VCO_TRIM_KVM_TX_DRS_MASK (0x700U)
#define XCVR_PLL_DIG_PLL_DATARATE_CTRL_PLL_VCO_TRIM_KVM_TX_DRS_SHIFT (8U)
/*! PLL_VCO_TRIM_KVM_TX_DRS - Data Rate Switch for pll_vco_trim_kvm_tx.
 *  0b000..10MHz/V
 *  0b100..20MHz/V
 *  0b110..30MHz/V
 *  0b111..40MHz/V
 */
#define XCVR_PLL_DIG_PLL_DATARATE_CTRL_PLL_VCO_TRIM_KVM_TX_DRS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_PLL_DATARATE_CTRL_PLL_VCO_TRIM_KVM_TX_DRS_SHIFT)) & XCVR_PLL_DIG_PLL_DATARATE_CTRL_PLL_VCO_TRIM_KVM_TX_DRS_MASK)

#define XCVR_PLL_DIG_PLL_DATARATE_CTRL_PLL_VCO_TRIM_KVM_CAL_DRS_MASK (0x7000U)
#define XCVR_PLL_DIG_PLL_DATARATE_CTRL_PLL_VCO_TRIM_KVM_CAL_DRS_SHIFT (12U)
/*! PLL_VCO_TRIM_KVM_CAL_DRS - Data Rate Switch for pll_vco_trim_kvm_cal
 *  0b000..10MHz/V
 *  0b100..20MHz/V
 *  0b110..30MHz/V
 *  0b111..40MHz/V
 */
#define XCVR_PLL_DIG_PLL_DATARATE_CTRL_PLL_VCO_TRIM_KVM_CAL_DRS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_PLL_DATARATE_CTRL_PLL_VCO_TRIM_KVM_CAL_DRS_SHIFT)) & XCVR_PLL_DIG_PLL_DATARATE_CTRL_PLL_VCO_TRIM_KVM_CAL_DRS_MASK)

#define XCVR_PLL_DIG_PLL_DATARATE_CTRL_LPM_SDM_DELAY_DRS_MASK (0xF0000U)
#define XCVR_PLL_DIG_PLL_DATARATE_CTRL_LPM_SDM_DELAY_DRS_SHIFT (16U)
/*! LPM_SDM_DELAY_DRS - DRS LPM_SDM_DELAY
 */
#define XCVR_PLL_DIG_PLL_DATARATE_CTRL_LPM_SDM_DELAY_DRS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_PLL_DATARATE_CTRL_LPM_SDM_DELAY_DRS_SHIFT)) & XCVR_PLL_DIG_PLL_DATARATE_CTRL_LPM_SDM_DELAY_DRS_MASK)

#define XCVR_PLL_DIG_PLL_DATARATE_CTRL_HPM_SDM_DELAY_DRS_MASK (0xF00000U)
#define XCVR_PLL_DIG_PLL_DATARATE_CTRL_HPM_SDM_DELAY_DRS_SHIFT (20U)
/*! HPM_SDM_DELAY_DRS - DRS HPM_SDM_DELAY
 */
#define XCVR_PLL_DIG_PLL_DATARATE_CTRL_HPM_SDM_DELAY_DRS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_PLL_DATARATE_CTRL_HPM_SDM_DELAY_DRS_SHIFT)) & XCVR_PLL_DIG_PLL_DATARATE_CTRL_HPM_SDM_DELAY_DRS_MASK)

#define XCVR_PLL_DIG_PLL_DATARATE_CTRL_HPM_INTEGER_DELAY_DRS_MASK (0xF000000U)
#define XCVR_PLL_DIG_PLL_DATARATE_CTRL_HPM_INTEGER_DELAY_DRS_SHIFT (24U)
/*! HPM_INTEGER_DELAY_DRS - DRS HPM_SDM_DELAY
 */
#define XCVR_PLL_DIG_PLL_DATARATE_CTRL_HPM_INTEGER_DELAY_DRS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_PLL_DATARATE_CTRL_HPM_INTEGER_DELAY_DRS_SHIFT)) & XCVR_PLL_DIG_PLL_DATARATE_CTRL_HPM_INTEGER_DELAY_DRS_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group XCVR_PLL_DIG_Register_Masks */


/* XCVR_PLL_DIG - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral XCVR_PLL_DIG base address */
  #define XCVR_PLL_DIG_BASE                        (0x58A07300u)
  /** Peripheral XCVR_PLL_DIG base address */
  #define XCVR_PLL_DIG_BASE_NS                     (0x48A07300u)
  /** Peripheral XCVR_PLL_DIG base pointer */
  #define XCVR_PLL_DIG                             ((XCVR_PLL_DIG_Type *)XCVR_PLL_DIG_BASE)
  /** Peripheral XCVR_PLL_DIG base pointer */
  #define XCVR_PLL_DIG_NS                          ((XCVR_PLL_DIG_Type *)XCVR_PLL_DIG_BASE_NS)
  /** Array initializer of XCVR_PLL_DIG peripheral base addresses */
  #define XCVR_PLL_DIG_BASE_ADDRS                  { XCVR_PLL_DIG_BASE }
  /** Array initializer of XCVR_PLL_DIG peripheral base pointers */
  #define XCVR_PLL_DIG_BASE_PTRS                   { XCVR_PLL_DIG }
  /** Array initializer of XCVR_PLL_DIG peripheral base addresses */
  #define XCVR_PLL_DIG_BASE_ADDRS_NS               { XCVR_PLL_DIG_BASE_NS }
  /** Array initializer of XCVR_PLL_DIG peripheral base pointers */
  #define XCVR_PLL_DIG_BASE_PTRS_NS                { XCVR_PLL_DIG_NS }
#else
  /** Peripheral XCVR_PLL_DIG base address */
  #define XCVR_PLL_DIG_BASE                        (0x48A07300u)
  /** Peripheral XCVR_PLL_DIG base pointer */
  #define XCVR_PLL_DIG                             ((XCVR_PLL_DIG_Type *)XCVR_PLL_DIG_BASE)
  /** Array initializer of XCVR_PLL_DIG peripheral base addresses */
  #define XCVR_PLL_DIG_BASE_ADDRS                  { XCVR_PLL_DIG_BASE }
  /** Array initializer of XCVR_PLL_DIG peripheral base pointers */
  #define XCVR_PLL_DIG_BASE_PTRS                   { XCVR_PLL_DIG }
#endif

/*!
 * @}
 */ /* end of group XCVR_PLL_DIG_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- XCVR_RX_DIG Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup XCVR_RX_DIG_Peripheral_Access_Layer XCVR_RX_DIG Peripheral Access Layer
 * @{
 */

/** XCVR_RX_DIG - Register Layout Typedef */
typedef struct {
  __IO uint32_t CTRL0;                             /**< RXDIG Control 0, offset: 0x0 */
  __IO uint32_t CTRL0_DRS;                         /**< RXDIG Control 0 DRS, offset: 0x4 */
  __IO uint32_t CTRL1;                             /**< RXDIG Control 1, offset: 0x8 */
  __IO uint32_t DFT_CTRL;                          /**< RXDIG DFT Control, offset: 0xC */
  __IO uint32_t RCCAL_CTRL0;                       /**< RCCAL Control 0, offset: 0x10 */
  __IO uint32_t RCCAL_CTRL1;                       /**< RCCAL Control 1, offset: 0x14 */
  __I  uint32_t RCCAL_RES;                         /**< RCCAL Result, offset: 0x18 */
  __IO uint32_t DCOC_CTRL0;                        /**< DCOC Control 0, offset: 0x1C */
  __IO uint32_t DCOC_CTRL0_DRS;                    /**< DCOC Control 0 DRS, offset: 0x20 */
  __IO uint32_t DCOC_CTRL1;                        /**< DCOC CONTROL 1, offset: 0x24 */
  __IO uint32_t DCOC_CTRL2;                        /**< DCOC CONTROL 2, offset: 0x28 */
  __I  uint32_t DCOC_STAT;                         /**< DCOC Status, offset: 0x2C */
  __IO uint32_t IQMC_CTRL0;                        /**< IQ Mismatch Control 0, offset: 0x30 */
  __IO uint32_t IQMC_CTRL1;                        /**< IQ Mismatch Control 1, offset: 0x34 */
  __IO uint32_t ACQ_FILT_0_3;                      /**< Acquisition Filter Coeffs 0~3, offset: 0x38 */
  __IO uint32_t ACQ_FILT_4_7;                      /**< Acquisition Filter Coeffs 4~7, offset: 0x3C */
  __IO uint32_t ACQ_FILT_8_9;                      /**< Acquisition Filter Coeffs 8~9, offset: 0x40 */
  __IO uint32_t ACQ_FILT_10_11;                    /**< Acquisition Filter Coeffs 10~11, offset: 0x44 */
  __IO uint32_t DEMOD_FILT_0_1;                    /**< Demod Filter Coeffs 0~1, offset: 0x48 */
  __IO uint32_t DEMOD_FILT_2_4;                    /**< Demod Filter Coeffs 2~4, offset: 0x4C */
  __IO uint32_t ACQ_FILT_0_3_DRS;                  /**< Acquisition Filter Coeffs 0~3 DRS, offset: 0x50 */
  __IO uint32_t ACQ_FILT_4_7_DRS;                  /**< Acquisition Filter Coeffs 4~7 DRS, offset: 0x54 */
  __IO uint32_t ACQ_FILT_8_9_DRS;                  /**< Acquisition Filter Coeffs 8~9 DRS, offset: 0x58 */
  __IO uint32_t ACQ_FILT_10_11_DRS;                /**< Acquisition Filter Coeffs 10~11 DRS, offset: 0x5C */
  __IO uint32_t DEMOD_FILT_0_1_DRS;                /**< Demod Filter Coeffs 0~1 DRS, offset: 0x60 */
  __IO uint32_t DEMOD_FILT_2_4_DRS;                /**< Demod Filter Coeffs 2~4 DRS, offset: 0x64 */
  __IO uint32_t RSSI_GLOBAL_CTRL;                  /**< RSSI Global Control, offset: 0x68 */
  __IO uint32_t WB_RSSI_CTRL;                      /**< Wide-Band RSSI Control, offset: 0x6C */
  __IO uint32_t WB_RSSI_RES0;                      /**< Wide-Band RSSI Result 0, offset: 0x70 */
  __I  uint32_t WB_RSSI_RES1;                      /**< Wide-Band RSSI Result 1, offset: 0x74 */
  __I  uint32_t WB_RSSI_DFT;                       /**< Wide-Band RSSI DFT Result, offset: 0x78 */
  __IO uint32_t NB_RSSI_CTRL0;                     /**< Narrow-Band RSSI Control 0, offset: 0x7C */
  __IO uint32_t NB_RSSI_CTRL1;                     /**< Narrow-Band RSSI Control 1, offset: 0x80 */
  __IO uint32_t NB_RSSI_RES0;                      /**< Narrow-Band RSSI Result 0, offset: 0x84 */
  __I  uint32_t NB_RSSI_RES1;                      /**< Narrow-Band RSSI Result 1, offset: 0x88 */
  __I  uint32_t NB_RSSI_DFT;                       /**< Narrow-Band RSSI DFT Result, offset: 0x8C */
  __IO uint32_t AGC_CTRL;                          /**< AGC Control, offset: 0x90 */
  __IO uint32_t AGC_CTRL_STAT;                     /**< AGC Control Status, offset: 0x94 */
  __IO uint32_t AGC_TIMING0;                       /**< AGC Timing Control 0, offset: 0x98 */
  __IO uint32_t AGC_TIMING1;                       /**< AGC Timing Control 1, offset: 0x9C */
  __IO uint32_t AGC_TIMING2;                       /**< AGC Timing Control 2, offset: 0xA0 */
  __IO uint32_t AGC_TIMING0_DRS;                   /**< AGC Timing Control 0 DRS, offset: 0xA4 */
  __IO uint32_t AGC_TIMING1_DRS;                   /**< AGC Timing Control 1 DRS, offset: 0xA8 */
  __IO uint32_t AGC_TIMING2_DRS;                   /**< AGC Timing Control 2 DRS, offset: 0xAC */
  __IO uint32_t AGC_IDX11_GAIN_CFG;                /**< AGC IDX11 Gain Config, offset: 0xB0 */
  __IO uint32_t AGC_IDX10_GAIN_CFG;                /**< AGC IDX10 Gain Config, offset: 0xB4 */
  __IO uint32_t AGC_IDX9_GAIN_CFG;                 /**< AGC IDX9 Gain Config, offset: 0xB8 */
  __IO uint32_t AGC_IDX8_GAIN_CFG;                 /**< AGC IDX8 Gain Config, offset: 0xBC */
  __IO uint32_t AGC_IDX7_GAIN_CFG;                 /**< AGC IDX7 Gain Config, offset: 0xC0 */
  __IO uint32_t AGC_IDX6_GAIN_CFG;                 /**< AGC IDX6 Gain Config, offset: 0xC4 */
  __IO uint32_t AGC_IDX5_GAIN_CFG;                 /**< AGC IDX5 Gain Config, offset: 0xC8 */
  __IO uint32_t AGC_IDX4_GAIN_CFG;                 /**< AGC IDX4 Gain Config, offset: 0xCC */
  __IO uint32_t AGC_IDX3_GAIN_CFG;                 /**< AGC IDX3 Gain Config, offset: 0xD0 */
  __IO uint32_t AGC_IDX2_GAIN_CFG;                 /**< AGC IDX2 Gain Config, offset: 0xD4 */
  __IO uint32_t AGC_IDX1_GAIN_CFG;                 /**< AGC IDX1 Gain Config, offset: 0xD8 */
  __IO uint32_t AGC_IDX0_GAIN_CFG;                 /**< AGC IDX0 Gain Config, offset: 0xDC */
  __IO uint32_t AGC_MIS_GAIN_CFG;                  /**< AGC Miscellaneous Gain Config, offset: 0xE0 */
  __IO uint32_t AGC_IDX11_GAIN_VAL;                /**< AGC IDX11 Gain Value, offset: 0xE4 */
  __IO uint32_t AGC_IDX10_GAIN_VAL;                /**< AGC_IDX10_GAIN_VAL, offset: 0xE8 */
  __IO uint32_t AGC_IDX9_GAIN_VAL;                 /**< AGC_IDX9_GAIN_VAL, offset: 0xEC */
  __IO uint32_t AGC_IDX8_GAIN_VAL;                 /**< AGC_IDX8_GAIN_VAL, offset: 0xF0 */
  __IO uint32_t AGC_IDX7_GAIN_VAL;                 /**< AGC_IDX7_GAIN_VAL, offset: 0xF4 */
  __IO uint32_t AGC_IDX6_GAIN_VAL;                 /**< AGC_IDX6_GAIN_VAL, offset: 0xF8 */
  __IO uint32_t AGC_IDX5_GAIN_VAL;                 /**< AGC_IDX5_GAIN_VAL, offset: 0xFC */
  __IO uint32_t AGC_IDX4_GAIN_VAL;                 /**< AGC_IDX4_GAIN_VAL, offset: 0x100 */
  __IO uint32_t AGC_IDX3_GAIN_VAL;                 /**< AGC_IDX3_GAIN_VAL, offset: 0x104 */
  __IO uint32_t AGC_IDX2_GAIN_VAL;                 /**< AGC_IDX2_GAIN_VAL, offset: 0x108 */
  __IO uint32_t AGC_IDX1_GAIN_VAL;                 /**< AGC_IDX1_GAIN_VAL, offset: 0x10C */
  __IO uint32_t AGC_IDX0_GAIN_VAL;                 /**< AGC_IDX0_GAIN_VAL, offset: 0x110 */
  __IO uint32_t AGC_THR_FAST;                      /**< AGC Fast Mode Threshold, offset: 0x114 */
  __IO uint32_t AGC_THR_FAST_DRS;                  /**< AGC Fast Mode Threshold DRS, offset: 0x118 */
  __IO uint32_t AGC_IDX11_THR;                     /**< AGC IDX11 Slow Mode Threshold, offset: 0x11C */
  __IO uint32_t AGC_IDX10_THR;                     /**< AGC IDX10 Slow Mode Threshold, offset: 0x120 */
  __IO uint32_t AGC_IDX9_THR;                      /**< AGC IDX9 Slow Mode Threshold, offset: 0x124 */
  __IO uint32_t AGC_IDX8_THR;                      /**< AGC IDX8 Slow Mode Threshold, offset: 0x128 */
  __IO uint32_t AGC_IDX7_THR;                      /**< AGC IDX7 Slow Mode Threshold, offset: 0x12C */
  __IO uint32_t AGC_IDX6_THR;                      /**< AGC IDX6 Slow Mode Threshold, offset: 0x130 */
  __IO uint32_t AGC_IDX5_THR;                      /**< AGC IDX5 Slow Mode Threshold, offset: 0x134 */
  __IO uint32_t AGC_IDX4_THR;                      /**< AGC IDX4 Slow Mode Threshold, offset: 0x138 */
  __IO uint32_t AGC_IDX3_THR;                      /**< AGC IDX3 Slow Mode Threshold, offset: 0x13C */
  __IO uint32_t AGC_IDX2_THR;                      /**< AGC IDX2 Slow Mode Threshold, offset: 0x140 */
  __IO uint32_t AGC_IDX1_THR;                      /**< AGC IDX1 Slow Mode Threshold, offset: 0x144 */
  __IO uint32_t AGC_IDX0_THR;                      /**< AGC IDX0 Slow Mode Threshold, offset: 0x148 */
  __IO uint32_t AGC_THR_MIS;                       /**< AGC Miscellaneous Thresholds, offset: 0x14C */
  __IO uint32_t AGC_OVRD;                          /**< AGC Override Control, offset: 0x150 */
  __IO uint32_t DC_RESID_CTRL;                     /**< DC Residual Control, offset: 0x154 */
  __IO uint32_t DC_RESID_CTRL2;                    /**< DC Residual Control2, offset: 0x158 */
  __IO uint32_t DC_RESID_CTRL_DRS;                 /**< DC Residual Control DataRate1, offset: 0x15C */
  __I  uint32_t DC_RESID_EST;                      /**< DC Residual Estimate, offset: 0x160 */
  __IO uint32_t DFT_TONE_ANALYZER0;                /**< DfT tone analyzer, offset: 0x164 */
  __IO uint32_t DFT_TONE_ANALYZER1;                /**< DfT tone analyzer, offset: 0x168 */
  __I  uint32_t DFT_TONE_ANALYZER2;                /**< DfT tone analyzer, offset: 0x16C */
  __IO uint32_t DFT_TONE_ANALYZER3;                /**< DfT tone analyzer, offset: 0x170 */
  __I  uint32_t DCOC_DIG_CORR_RESULT;              /**< DCOC Digital Correction Result, offset: 0x174 */
} XCVR_RX_DIG_Type;

/* ----------------------------------------------------------------------------
   -- XCVR_RX_DIG Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup XCVR_RX_DIG_Register_Masks XCVR_RX_DIG Register Masks
 * @{
 */

/*! @name CTRL0 - RXDIG Control 0 */
/*! @{ */

#define XCVR_RX_DIG_CTRL0_ADC_CLIP_EN_MASK       (0x1U)
#define XCVR_RX_DIG_CTRL0_ADC_CLIP_EN_SHIFT      (0U)
/*! ADC_CLIP_EN - ADC Output Clip Enable
 *  0b0..ADC clip is disabled.
 *  0b1..ADC clip is enabled.
 */
#define XCVR_RX_DIG_CTRL0_ADC_CLIP_EN(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CTRL0_ADC_CLIP_EN_SHIFT)) & XCVR_RX_DIG_CTRL0_ADC_CLIP_EN_MASK)

#define XCVR_RX_DIG_CTRL0_RX_IQMC_EN_MASK        (0x2U)
#define XCVR_RX_DIG_CTRL0_RX_IQMC_EN_SHIFT       (1U)
/*! RX_IQMC_EN - IQ Mismatch Compensation Enable
 *  0b1..IQ mismatch compensation is enabled.
 *  0b0..IQ mismatch compensation is disabled.
 */
#define XCVR_RX_DIG_CTRL0_RX_IQMC_EN(x)          (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CTRL0_RX_IQMC_EN_SHIFT)) & XCVR_RX_DIG_CTRL0_RX_IQMC_EN_MASK)

#define XCVR_RX_DIG_CTRL0_DIG_MIXER_FREQ_MASK    (0x7FCU)
#define XCVR_RX_DIG_CTRL0_DIG_MIXER_FREQ_SHIFT   (2U)
/*! DIG_MIXER_FREQ - Digital Mixer Frequency
 */
#define XCVR_RX_DIG_CTRL0_DIG_MIXER_FREQ(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CTRL0_DIG_MIXER_FREQ_SHIFT)) & XCVR_RX_DIG_CTRL0_DIG_MIXER_FREQ_MASK)

#define XCVR_RX_DIG_CTRL0_CIC_ORDER_MASK         (0x800U)
#define XCVR_RX_DIG_CTRL0_CIC_ORDER_SHIFT        (11U)
/*! CIC_ORDER - CIC Order(Stage) Selection
 *  0b0..4-stage CIC
 *  0b1..3-stage CIC
 */
#define XCVR_RX_DIG_CTRL0_CIC_ORDER(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CTRL0_CIC_ORDER_SHIFT)) & XCVR_RX_DIG_CTRL0_CIC_ORDER_MASK)

#define XCVR_RX_DIG_CTRL0_CIC_RATE_MASK          (0x7000U)
#define XCVR_RX_DIG_CTRL0_CIC_RATE_SHIFT         (12U)
/*! CIC_RATE - CIC Decimation Rate
 *  0b111..Reserved
 *  0b110..Reserved
 *  0b101..Decimation Rate is 32.
 *  0b100..Decimation Rate is 16.
 *  0b011..Decimation Rate is 8.
 *  0b010..Decimation Rate is 4.
 *  0b001..Decimation Rate is 2.
 *  0b000..Decimation Rate is 1.
 */
#define XCVR_RX_DIG_CTRL0_CIC_RATE(x)            (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CTRL0_CIC_RATE_SHIFT)) & XCVR_RX_DIG_CTRL0_CIC_RATE_MASK)

#define XCVR_RX_DIG_CTRL0_RX_DIG_GAIN_MASK       (0x70000U)
#define XCVR_RX_DIG_CTRL0_RX_DIG_GAIN_SHIFT      (16U)
/*! RX_DIG_GAIN - RX Digital Gain Value
 *  0b000..Digital gain value is 1.000.
 *  0b001..Digital gain value is 1.125.
 *  0b010..Digital gain value is 1.250.
 *  0b011..Digital gain value is 1.375.
 *  0b100..Digital gain value is 1.500.
 *  0b101..Digital gain value is 1.625.
 *  0b110..Digital gain value is 1.750.
 *  0b111..Digital gain value is 1.875.
 */
#define XCVR_RX_DIG_CTRL0_RX_DIG_GAIN(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CTRL0_RX_DIG_GAIN_SHIFT)) & XCVR_RX_DIG_CTRL0_RX_DIG_GAIN_MASK)

#define XCVR_RX_DIG_CTRL0_RX_ACQ_FILT_LEN_MASK   (0x100000U)
#define XCVR_RX_DIG_CTRL0_RX_ACQ_FILT_LEN_SHIFT  (20U)
/*! RX_ACQ_FILT_LEN - Acquisition Filter Length
 *  0b0..Acquisition filter length is 24.
 *  0b1..Acquisition filter length is 16.
 */
#define XCVR_RX_DIG_CTRL0_RX_ACQ_FILT_LEN(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CTRL0_RX_ACQ_FILT_LEN_SHIFT)) & XCVR_RX_DIG_CTRL0_RX_ACQ_FILT_LEN_MASK)

#define XCVR_RX_DIG_CTRL0_RX_ACQ_FILT_BYPASS_MASK (0x200000U)
#define XCVR_RX_DIG_CTRL0_RX_ACQ_FILT_BYPASS_SHIFT (21U)
/*! RX_ACQ_FILT_BYPASS - Acquisition Filter Bypass
 *  0b0..Acquisition filter is enabled
 *  0b1..Acquisition filter is bypassed
 */
#define XCVR_RX_DIG_CTRL0_RX_ACQ_FILT_BYPASS(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CTRL0_RX_ACQ_FILT_BYPASS_SHIFT)) & XCVR_RX_DIG_CTRL0_RX_ACQ_FILT_BYPASS_MASK)

#define XCVR_RX_DIG_CTRL0_RX_SRC_EN_MASK         (0x400000U)
#define XCVR_RX_DIG_CTRL0_RX_SRC_EN_SHIFT        (22U)
/*! RX_SRC_EN - RX Sample Rate Converter Enable
 *  0b0..SRC is disabled.
 *  0b1..SRC is enabled.
 */
#define XCVR_RX_DIG_CTRL0_RX_SRC_EN(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CTRL0_RX_SRC_EN_SHIFT)) & XCVR_RX_DIG_CTRL0_RX_SRC_EN_MASK)

#define XCVR_RX_DIG_CTRL0_RX_IQ_8B_OUT_MODE_MASK (0x3800000U)
#define XCVR_RX_DIG_CTRL0_RX_IQ_8B_OUT_MODE_SHIFT (23U)
/*! RX_IQ_8B_OUT_MODE - RX 8-bit IQ Output Mode
 *  0b000..Disable 8-bit IQ output
 *  0b001..{I[10],I[9:3]}, {Q[10],Q[9:3]}
 *  0b010..{I[10],I[8:2]}, {Q[10],Q[8:2]}
 *  0b011..{I[10],I[7:1]}, {Q[10],Q[7:1]}
 *  0b100..Dynamic scaling
 */
#define XCVR_RX_DIG_CTRL0_RX_IQ_8B_OUT_MODE(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CTRL0_RX_IQ_8B_OUT_MODE_SHIFT)) & XCVR_RX_DIG_CTRL0_RX_IQ_8B_OUT_MODE_MASK)

#define XCVR_RX_DIG_CTRL0_RX_FSK_ZB_SEL_MASK     (0x8000000U)
#define XCVR_RX_DIG_CTRL0_RX_FSK_ZB_SEL_SHIFT    (27U)
/*! RX_FSK_ZB_SEL
 *  0b0..2.4GHz PHY is selected
 *  0b1..15.4 PHY is selected
 */
#define XCVR_RX_DIG_CTRL0_RX_FSK_ZB_SEL(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CTRL0_RX_FSK_ZB_SEL_SHIFT)) & XCVR_RX_DIG_CTRL0_RX_FSK_ZB_SEL_MASK)

#define XCVR_RX_DIG_CTRL0_CIC_CNTR_FREE_RUN_EN_MASK (0x20000000U)
#define XCVR_RX_DIG_CTRL0_CIC_CNTR_FREE_RUN_EN_SHIFT (29U)
/*! CIC_CNTR_FREE_RUN_EN - CIC Dec Counter Free Run Enable
 */
#define XCVR_RX_DIG_CTRL0_CIC_CNTR_FREE_RUN_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CTRL0_CIC_CNTR_FREE_RUN_EN_SHIFT)) & XCVR_RX_DIG_CTRL0_CIC_CNTR_FREE_RUN_EN_MASK)

#define XCVR_RX_DIG_CTRL0_RX_AGC_EN_MASK         (0x40000000U)
#define XCVR_RX_DIG_CTRL0_RX_AGC_EN_SHIFT        (30U)
/*! RX_AGC_EN - AGC Enable
 *  0b0..AGC is disabled
 *  0b1..AGC is enabled
 */
#define XCVR_RX_DIG_CTRL0_RX_AGC_EN(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CTRL0_RX_AGC_EN_SHIFT)) & XCVR_RX_DIG_CTRL0_RX_AGC_EN_MASK)

#define XCVR_RX_DIG_CTRL0_DR_OVRD_IN_CTE_MASK    (0x80000000U)
#define XCVR_RX_DIG_CTRL0_DR_OVRD_IN_CTE_SHIFT   (31U)
/*! DR_OVRD_IN_CTE - DATARATE_CONFIG_SEL Override In CTE
 */
#define XCVR_RX_DIG_CTRL0_DR_OVRD_IN_CTE(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CTRL0_DR_OVRD_IN_CTE_SHIFT)) & XCVR_RX_DIG_CTRL0_DR_OVRD_IN_CTE_MASK)
/*! @} */

/*! @name CTRL0_DRS - RXDIG Control 0 DRS */
/*! @{ */

#define XCVR_RX_DIG_CTRL0_DRS_DIG_MIXER_FREQ_MASK (0x7FCU)
#define XCVR_RX_DIG_CTRL0_DRS_DIG_MIXER_FREQ_SHIFT (2U)
/*! DIG_MIXER_FREQ - Digital Mixer Frequency
 */
#define XCVR_RX_DIG_CTRL0_DRS_DIG_MIXER_FREQ(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CTRL0_DRS_DIG_MIXER_FREQ_SHIFT)) & XCVR_RX_DIG_CTRL0_DRS_DIG_MIXER_FREQ_MASK)

#define XCVR_RX_DIG_CTRL0_DRS_CIC_ORDER_MASK     (0x800U)
#define XCVR_RX_DIG_CTRL0_DRS_CIC_ORDER_SHIFT    (11U)
/*! CIC_ORDER - CIC Order(Stage) Selection
 *  0b0..4-stage CIC
 *  0b1..3-stage CIC
 */
#define XCVR_RX_DIG_CTRL0_DRS_CIC_ORDER(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CTRL0_DRS_CIC_ORDER_SHIFT)) & XCVR_RX_DIG_CTRL0_DRS_CIC_ORDER_MASK)

#define XCVR_RX_DIG_CTRL0_DRS_CIC_RATE_MASK      (0x7000U)
#define XCVR_RX_DIG_CTRL0_DRS_CIC_RATE_SHIFT     (12U)
/*! CIC_RATE - CIC Decimation Rate
 *  0b111..Reserved
 *  0b110..Reserved
 *  0b101..Decimation Rate is 32.
 *  0b100..Decimation Rate is 16.
 *  0b011..Decimation Rate is 8.
 *  0b010..Decimation Rate is 4.
 *  0b001..Decimation Rate is 2.
 *  0b000..Decimation Rate is 1.
 */
#define XCVR_RX_DIG_CTRL0_DRS_CIC_RATE(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CTRL0_DRS_CIC_RATE_SHIFT)) & XCVR_RX_DIG_CTRL0_DRS_CIC_RATE_MASK)
/*! @} */

/*! @name CTRL1 - RXDIG Control 1 */
/*! @{ */

#define XCVR_RX_DIG_CTRL1_RX_SAMPLE_BUF_BYPASS_MASK (0x1U)
#define XCVR_RX_DIG_CTRL1_RX_SAMPLE_BUF_BYPASS_SHIFT (0U)
/*! RX_SAMPLE_BUF_BYPASS - Bypass Sample Buffer
 */
#define XCVR_RX_DIG_CTRL1_RX_SAMPLE_BUF_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CTRL1_RX_SAMPLE_BUF_BYPASS_SHIFT)) & XCVR_RX_DIG_CTRL1_RX_SAMPLE_BUF_BYPASS_MASK)

#define XCVR_RX_DIG_CTRL1_RX_SAMPLE_BUF_BYPASS_IN_CTE_MASK (0x10U)
#define XCVR_RX_DIG_CTRL1_RX_SAMPLE_BUF_BYPASS_IN_CTE_SHIFT (4U)
/*! RX_SAMPLE_BUF_BYPASS_IN_CTE - Bypass Sample Buffer During CTE
 */
#define XCVR_RX_DIG_CTRL1_RX_SAMPLE_BUF_BYPASS_IN_CTE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CTRL1_RX_SAMPLE_BUF_BYPASS_IN_CTE_SHIFT)) & XCVR_RX_DIG_CTRL1_RX_SAMPLE_BUF_BYPASS_IN_CTE_MASK)

#define XCVR_RX_DIG_CTRL1_RX_SAMPLE_BUF_AUTO_GATE_MASK (0x20U)
#define XCVR_RX_DIG_CTRL1_RX_SAMPLE_BUF_AUTO_GATE_SHIFT (5U)
/*! RX_SAMPLE_BUF_AUTO_GATE - Sample Buffer Automatically Gate Off
 */
#define XCVR_RX_DIG_CTRL1_RX_SAMPLE_BUF_AUTO_GATE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CTRL1_RX_SAMPLE_BUF_AUTO_GATE_SHIFT)) & XCVR_RX_DIG_CTRL1_RX_SAMPLE_BUF_AUTO_GATE_MASK)

#define XCVR_RX_DIG_CTRL1_DC_RESID_EN_MASK       (0x40U)
#define XCVR_RX_DIG_CTRL1_DC_RESID_EN_SHIFT      (6U)
/*! DC_RESID_EN - DC_RESID Enable
 */
#define XCVR_RX_DIG_CTRL1_DC_RESID_EN(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CTRL1_DC_RESID_EN_SHIFT)) & XCVR_RX_DIG_CTRL1_DC_RESID_EN_MASK)

#define XCVR_RX_DIG_CTRL1_DIS_WB_NORM_AA_FOUND_MASK (0x80U)
#define XCVR_RX_DIG_CTRL1_DIS_WB_NORM_AA_FOUND_SHIFT (7U)
/*! DIS_WB_NORM_AA_FOUND - Disable WB-NORM when AA found
 */
#define XCVR_RX_DIG_CTRL1_DIS_WB_NORM_AA_FOUND(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CTRL1_DIS_WB_NORM_AA_FOUND_SHIFT)) & XCVR_RX_DIG_CTRL1_DIS_WB_NORM_AA_FOUND_MASK)

#define XCVR_RX_DIG_CTRL1_RX_NB_NORM_EN_MASK     (0x100U)
#define XCVR_RX_DIG_CTRL1_RX_NB_NORM_EN_SHIFT    (8U)
/*! RX_NB_NORM_EN - Narrow-Band Normalizer Enable
 *  0b0..Narrow-Band normalizer is disabled.
 *  0b1..Narrow-Band normalizer is enabled.
 */
#define XCVR_RX_DIG_CTRL1_RX_NB_NORM_EN(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CTRL1_RX_NB_NORM_EN_SHIFT)) & XCVR_RX_DIG_CTRL1_RX_NB_NORM_EN_MASK)

#define XCVR_RX_DIG_CTRL1_RX_HIGH_RES_NORM_SEL_MASK (0x200U)
#define XCVR_RX_DIG_CTRL1_RX_HIGH_RES_NORM_SEL_SHIFT (9U)
/*! RX_HIGH_RES_NORM_SEL - High Resolution Phase Source Select
 *  0b0..From RX_NORM_NB
 *  0b1..From RX_NORM_WB
 */
#define XCVR_RX_DIG_CTRL1_RX_HIGH_RES_NORM_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CTRL1_RX_HIGH_RES_NORM_SEL_SHIFT)) & XCVR_RX_DIG_CTRL1_RX_HIGH_RES_NORM_SEL_MASK)

#define XCVR_RX_DIG_CTRL1_RX_DEMOD_FILT_BYPASS_MASK (0x400U)
#define XCVR_RX_DIG_CTRL1_RX_DEMOD_FILT_BYPASS_SHIFT (10U)
/*! RX_DEMOD_FILT_BYPASS - Demod Channel Filter Bypass
 *  0b0..Demod channel filter is enabled.
 *  0b1..Demod channel filter is bypassed.
 */
#define XCVR_RX_DIG_CTRL1_RX_DEMOD_FILT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CTRL1_RX_DEMOD_FILT_BYPASS_SHIFT)) & XCVR_RX_DIG_CTRL1_RX_DEMOD_FILT_BYPASS_MASK)

#define XCVR_RX_DIG_CTRL1_RX_FRAC_CORR_OVRD_MASK (0x7000U)
#define XCVR_RX_DIG_CTRL1_RX_FRAC_CORR_OVRD_SHIFT (12U)
/*! RX_FRAC_CORR_OVRD - Fractional Correction Coefficient Override Value
 */
#define XCVR_RX_DIG_CTRL1_RX_FRAC_CORR_OVRD(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CTRL1_RX_FRAC_CORR_OVRD_SHIFT)) & XCVR_RX_DIG_CTRL1_RX_FRAC_CORR_OVRD_MASK)

#define XCVR_RX_DIG_CTRL1_RX_FRAC_CORR_OVRD_EN_MASK (0x8000U)
#define XCVR_RX_DIG_CTRL1_RX_FRAC_CORR_OVRD_EN_SHIFT (15U)
/*! RX_FRAC_CORR_OVRD_EN - Fractional Correction Coefficient Override Enable
 */
#define XCVR_RX_DIG_CTRL1_RX_FRAC_CORR_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CTRL1_RX_FRAC_CORR_OVRD_EN_SHIFT)) & XCVR_RX_DIG_CTRL1_RX_FRAC_CORR_OVRD_EN_MASK)

#define XCVR_RX_DIG_CTRL1_RX_CFO_EST_OVRD_MASK   (0x3FF0000U)
#define XCVR_RX_DIG_CTRL1_RX_CFO_EST_OVRD_SHIFT  (16U)
/*! RX_CFO_EST_OVRD - CFO Estimation Override Value
 */
#define XCVR_RX_DIG_CTRL1_RX_CFO_EST_OVRD(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CTRL1_RX_CFO_EST_OVRD_SHIFT)) & XCVR_RX_DIG_CTRL1_RX_CFO_EST_OVRD_MASK)

#define XCVR_RX_DIG_CTRL1_RX_CFO_EST_OVRD_EN_MASK (0x4000000U)
#define XCVR_RX_DIG_CTRL1_RX_CFO_EST_OVRD_EN_SHIFT (26U)
/*! RX_CFO_EST_OVRD_EN - CFO Estimation Override Enable
 *  0b0..CFO override is enabled
 *  0b1..CFO override is disabled
 */
#define XCVR_RX_DIG_CTRL1_RX_CFO_EST_OVRD_EN(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CTRL1_RX_CFO_EST_OVRD_EN_SHIFT)) & XCVR_RX_DIG_CTRL1_RX_CFO_EST_OVRD_EN_MASK)

#define XCVR_RX_DIG_CTRL1_RX_MIXER_IDX_OUT_MODE_MASK (0x8000000U)
#define XCVR_RX_DIG_CTRL1_RX_MIXER_IDX_OUT_MODE_SHIFT (27U)
/*! RX_MIXER_IDX_OUT_MODE - RX_DIG Mixer Index Output Mode
 */
#define XCVR_RX_DIG_CTRL1_RX_MIXER_IDX_OUT_MODE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CTRL1_RX_MIXER_IDX_OUT_MODE_SHIFT)) & XCVR_RX_DIG_CTRL1_RX_MIXER_IDX_OUT_MODE_MASK)

#define XCVR_RX_DIG_CTRL1_RX_IQ_PH_AVG_WIN_MASK  (0x70000000U)
#define XCVR_RX_DIG_CTRL1_RX_IQ_PH_AVG_WIN_SHIFT (28U)
/*! RX_IQ_PH_AVG_WIN - RX IQ Phase Output Average Window Config
 *  0b000..Disable RX IQ and/or Phase output average function
 *  0b001..Average window size = 4
 *  0b010..Average window size = 8
 *  0b011..Average window size = 16
 *  0b100..Average window size = 32
 *  0b101..Average window size = 64
 *  0b110..Average window size = 128
 *  0b111..Average window size = 256
 */
#define XCVR_RX_DIG_CTRL1_RX_IQ_PH_AVG_WIN(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CTRL1_RX_IQ_PH_AVG_WIN_SHIFT)) & XCVR_RX_DIG_CTRL1_RX_IQ_PH_AVG_WIN_MASK)

#define XCVR_RX_DIG_CTRL1_RX_IQ_PH_OUTPUT_COND_MASK (0x80000000U)
#define XCVR_RX_DIG_CTRL1_RX_IQ_PH_OUTPUT_COND_SHIFT (31U)
/*! RX_IQ_PH_OUTPUT_COND - RX IQ or Phase Output Conditioning
 *  0b0..Output IQ and/or Phase all-time
 *  0b1..Only output IQ and/or Phase during localization sample slot
 */
#define XCVR_RX_DIG_CTRL1_RX_IQ_PH_OUTPUT_COND(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CTRL1_RX_IQ_PH_OUTPUT_COND_SHIFT)) & XCVR_RX_DIG_CTRL1_RX_IQ_PH_OUTPUT_COND_MASK)
/*! @} */

/*! @name DFT_CTRL - RXDIG DFT Control */
/*! @{ */

#define XCVR_RX_DIG_DFT_CTRL_DFT_RX_PH_OUT_SEL_MASK (0x300U)
#define XCVR_RX_DIG_DFT_CTRL_DFT_RX_PH_OUT_SEL_SHIFT (8U)
/*! DFT_RX_PH_OUT_SEL - DFT RXDIG Phase Output Selection
 *  0b00..Disable DFT phase output
 *  0b01..Sel wide-band phase output
 *  0b10..Sel narrow-band phase output
 *  0b11..Disable DFT phase output
 */
#define XCVR_RX_DIG_DFT_CTRL_DFT_RX_PH_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DFT_CTRL_DFT_RX_PH_OUT_SEL_SHIFT)) & XCVR_RX_DIG_DFT_CTRL_DFT_RX_PH_OUT_SEL_MASK)

#define XCVR_RX_DIG_DFT_CTRL_DFT_RX_IQ_OUT_SEL_MASK (0x1C00U)
#define XCVR_RX_DIG_DFT_CTRL_DFT_RX_IQ_OUT_SEL_SHIFT (10U)
/*! DFT_RX_IQ_OUT_SEL - DFT I/Q Output Selection
 *  0b000..Disabled
 *  0b001..Select IF_MIXER
 *  0b010..Select CIC
 *  0b011..Select ACQ channel filter
 *  0b100..Select SRC
 *  0b101..Select CFO_MIXER
 *  0b110..Select FRAC_CORR
 *  0b111..Select DC_RESID
 */
#define XCVR_RX_DIG_DFT_CTRL_DFT_RX_IQ_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DFT_CTRL_DFT_RX_IQ_OUT_SEL_SHIFT)) & XCVR_RX_DIG_DFT_CTRL_DFT_RX_IQ_OUT_SEL_MASK)

#define XCVR_RX_DIG_DFT_CTRL_DFT_RSSI_MAG_OUT_SEL_MASK (0xE000U)
#define XCVR_RX_DIG_DFT_CTRL_DFT_RSSI_MAG_OUT_SEL_SHIFT (13U)
/*! DFT_RSSI_MAG_OUT_SEL - DFT RSSI Magnitude Output Selection
 *  0b000..Disabled
 *  0b001..WB-RSSI fast magnitude
 *  0b010..WB-RSSI slow magnitude
 *  0b011..NB-RSSI mag IIR
 *  0b100..NB-RSSI mag avg
 *  0b101..NB-RSSI noise mag IIR
 *  0b110..NB-RSSI noise mag avg
 *  0b111..DFT_RX_IQ_OUT mag
 */
#define XCVR_RX_DIG_DFT_CTRL_DFT_RSSI_MAG_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DFT_CTRL_DFT_RSSI_MAG_OUT_SEL_SHIFT)) & XCVR_RX_DIG_DFT_CTRL_DFT_RSSI_MAG_OUT_SEL_MASK)

#define XCVR_RX_DIG_DFT_CTRL_DFT_RSSI_OUT_SEL_MASK (0x70000U)
#define XCVR_RX_DIG_DFT_CTRL_DFT_RSSI_OUT_SEL_SHIFT (16U)
/*! DFT_RSSI_OUT_SEL - DFT RSSI Result Output Selection
 *  0b000..Disable RSSI output
 *  0b001..Wide-band RSSI_RAW output
 *  0b010..Wide-band RSSI output
 *  0b011..Narrow-band RSSI_RAW output
 *  0b100..Narrow-band RSSI output
 *  0b101..Narrow-band NOISE_RAW output
 *  0b110..Narrow-band SNR output
 *  0b111..Narrow-band LQI output
 */
#define XCVR_RX_DIG_DFT_CTRL_DFT_RSSI_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DFT_CTRL_DFT_RSSI_OUT_SEL_SHIFT)) & XCVR_RX_DIG_DFT_CTRL_DFT_RSSI_OUT_SEL_MASK)

#define XCVR_RX_DIG_DFT_CTRL_CGM_OVRD_MASK       (0xFFF00000U)
#define XCVR_RX_DIG_DFT_CTRL_CGM_OVRD_SHIFT      (20U)
/*! CGM_OVRD - CGM Override
 *  0b000000000001..RCCAL
 *  0b000000000010..DCOC
 *  0b000000000100..IF_MIXER
 *  0b000000001000..CIC
 *  0b000000010000..ACQ_CHF
 *  0b000000100000..SRC
 *  0b000001000000..SAMPLE_BUF and CFO_MIXER
 *  0b000010000000..DEMOD_CHF and FRAC_CORR
 *  0b000100000000..NB_NORM and HIGH_RES_NORM
 *  0b001000000000..AGC
 *  0b010000000000..IQ_MISMATCH
 *  0b100000000000..DIG_GAIN
 */
#define XCVR_RX_DIG_DFT_CTRL_CGM_OVRD(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DFT_CTRL_CGM_OVRD_SHIFT)) & XCVR_RX_DIG_DFT_CTRL_CGM_OVRD_MASK)
/*! @} */

/*! @name RCCAL_CTRL0 - RCCAL Control 0 */
/*! @{ */

#define XCVR_RX_DIG_RCCAL_CTRL0_CBPF_BW_CODE_MASK (0x7U)
#define XCVR_RX_DIG_RCCAL_CTRL0_CBPF_BW_CODE_SHIFT (0U)
/*! CBPF_BW_CODE - CBPF BW_CODE
 */
#define XCVR_RX_DIG_RCCAL_CTRL0_CBPF_BW_CODE(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RCCAL_CTRL0_CBPF_BW_CODE_SHIFT)) & XCVR_RX_DIG_RCCAL_CTRL0_CBPF_BW_CODE_MASK)

#define XCVR_RX_DIG_RCCAL_CTRL0_CBPF_SC_CODE_MASK (0x8U)
#define XCVR_RX_DIG_RCCAL_CTRL0_CBPF_SC_CODE_SHIFT (3U)
#define XCVR_RX_DIG_RCCAL_CTRL0_CBPF_SC_CODE(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RCCAL_CTRL0_CBPF_SC_CODE_SHIFT)) & XCVR_RX_DIG_RCCAL_CTRL0_CBPF_SC_CODE_MASK)

#define XCVR_RX_DIG_RCCAL_CTRL0_CBPF_BW_CODE_DRS_MASK (0x70U)
#define XCVR_RX_DIG_RCCAL_CTRL0_CBPF_BW_CODE_DRS_SHIFT (4U)
#define XCVR_RX_DIG_RCCAL_CTRL0_CBPF_BW_CODE_DRS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RCCAL_CTRL0_CBPF_BW_CODE_DRS_SHIFT)) & XCVR_RX_DIG_RCCAL_CTRL0_CBPF_BW_CODE_DRS_MASK)

#define XCVR_RX_DIG_RCCAL_CTRL0_CBPF_SC_CODE_DRS_MASK (0x80U)
#define XCVR_RX_DIG_RCCAL_CTRL0_CBPF_SC_CODE_DRS_SHIFT (7U)
#define XCVR_RX_DIG_RCCAL_CTRL0_CBPF_SC_CODE_DRS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RCCAL_CTRL0_CBPF_SC_CODE_DRS_SHIFT)) & XCVR_RX_DIG_RCCAL_CTRL0_CBPF_SC_CODE_DRS_MASK)

#define XCVR_RX_DIG_RCCAL_CTRL0_CBPF_CCODE_OFFSET_MASK (0x1F00U)
#define XCVR_RX_DIG_RCCAL_CTRL0_CBPF_CCODE_OFFSET_SHIFT (8U)
/*! CBPF_CCODE_OFFSET - CBPF_CCODE Offset
 */
#define XCVR_RX_DIG_RCCAL_CTRL0_CBPF_CCODE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RCCAL_CTRL0_CBPF_CCODE_OFFSET_SHIFT)) & XCVR_RX_DIG_RCCAL_CTRL0_CBPF_CCODE_OFFSET_MASK)

#define XCVR_RX_DIG_RCCAL_CTRL0_RCCAL_CODE_OFFSET_MASK (0xF0000U)
#define XCVR_RX_DIG_RCCAL_CTRL0_RCCAL_CODE_OFFSET_SHIFT (16U)
/*! RCCAL_CODE_OFFSET - RCCAL_CODE Offset
 */
#define XCVR_RX_DIG_RCCAL_CTRL0_RCCAL_CODE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RCCAL_CTRL0_RCCAL_CODE_OFFSET_SHIFT)) & XCVR_RX_DIG_RCCAL_CTRL0_RCCAL_CODE_OFFSET_MASK)

#define XCVR_RX_DIG_RCCAL_CTRL0_RCCAL_SMPL_DLY_MASK (0x300000U)
#define XCVR_RX_DIG_RCCAL_CTRL0_RCCAL_SMPL_DLY_SHIFT (20U)
/*! RCCAL_SMPL_DLY - RCCAL Sample Delay
 *  0b00..2 cycles (default)
 *  0b01..1 cycle
 *  0b10..2 cycles
 *  0b11..3 cycles
 */
#define XCVR_RX_DIG_RCCAL_CTRL0_RCCAL_SMPL_DLY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RCCAL_CTRL0_RCCAL_SMPL_DLY_SHIFT)) & XCVR_RX_DIG_RCCAL_CTRL0_RCCAL_SMPL_DLY_MASK)

#define XCVR_RX_DIG_RCCAL_CTRL0_RCCAL_CMPOUT_INV_MASK (0x400000U)
#define XCVR_RX_DIG_RCCAL_CTRL0_RCCAL_CMPOUT_INV_SHIFT (22U)
/*! RCCAL_CMPOUT_INV - RCCAL Comparator Output Invert
 */
#define XCVR_RX_DIG_RCCAL_CTRL0_RCCAL_CMPOUT_INV(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RCCAL_CTRL0_RCCAL_CMPOUT_INV_SHIFT)) & XCVR_RX_DIG_RCCAL_CTRL0_RCCAL_CMPOUT_INV_MASK)
/*! @} */

/*! @name RCCAL_CTRL1 - RCCAL Control 1 */
/*! @{ */

#define XCVR_RX_DIG_RCCAL_CTRL1_CBPF_CCODE_OVRD_MASK (0x7FU)
#define XCVR_RX_DIG_RCCAL_CTRL1_CBPF_CCODE_OVRD_SHIFT (0U)
/*! CBPF_CCODE_OVRD - CBPF_CCODE Override Value
 */
#define XCVR_RX_DIG_RCCAL_CTRL1_CBPF_CCODE_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RCCAL_CTRL1_CBPF_CCODE_OVRD_SHIFT)) & XCVR_RX_DIG_RCCAL_CTRL1_CBPF_CCODE_OVRD_MASK)

#define XCVR_RX_DIG_RCCAL_CTRL1_CBPF_CCODE_OVRD_EN_MASK (0x80U)
#define XCVR_RX_DIG_RCCAL_CTRL1_CBPF_CCODE_OVRD_EN_SHIFT (7U)
/*! CBPF_CCODE_OVRD_EN - CBPF_CCODE Override Enable
 */
#define XCVR_RX_DIG_RCCAL_CTRL1_CBPF_CCODE_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RCCAL_CTRL1_CBPF_CCODE_OVRD_EN_SHIFT)) & XCVR_RX_DIG_RCCAL_CTRL1_CBPF_CCODE_OVRD_EN_MASK)

#define XCVR_RX_DIG_RCCAL_CTRL1_RCCAL_CODE_OVRD_MASK (0x1F00U)
#define XCVR_RX_DIG_RCCAL_CTRL1_RCCAL_CODE_OVRD_SHIFT (8U)
/*! RCCAL_CODE_OVRD - RCCAL_CODE Override Value
 */
#define XCVR_RX_DIG_RCCAL_CTRL1_RCCAL_CODE_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RCCAL_CTRL1_RCCAL_CODE_OVRD_SHIFT)) & XCVR_RX_DIG_RCCAL_CTRL1_RCCAL_CODE_OVRD_MASK)

#define XCVR_RX_DIG_RCCAL_CTRL1_RCCAL_CODE_OVRD_EN_MASK (0x2000U)
#define XCVR_RX_DIG_RCCAL_CTRL1_RCCAL_CODE_OVRD_EN_SHIFT (13U)
/*! RCCAL_CODE_OVRD_EN - RCCAL_CODE Override Enable
 */
#define XCVR_RX_DIG_RCCAL_CTRL1_RCCAL_CODE_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RCCAL_CTRL1_RCCAL_CODE_OVRD_EN_SHIFT)) & XCVR_RX_DIG_RCCAL_CTRL1_RCCAL_CODE_OVRD_EN_MASK)

#define XCVR_RX_DIG_RCCAL_CTRL1_RCCAL_SAMPLE_OVRD_MASK (0x10000U)
#define XCVR_RX_DIG_RCCAL_CTRL1_RCCAL_SAMPLE_OVRD_SHIFT (16U)
/*! RCCAL_SAMPLE_OVRD - RCCAL_SAMPLE Override Value
 */
#define XCVR_RX_DIG_RCCAL_CTRL1_RCCAL_SAMPLE_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RCCAL_CTRL1_RCCAL_SAMPLE_OVRD_SHIFT)) & XCVR_RX_DIG_RCCAL_CTRL1_RCCAL_SAMPLE_OVRD_MASK)

#define XCVR_RX_DIG_RCCAL_CTRL1_RCCAL_CHARGE_OVRD_MASK (0x20000U)
#define XCVR_RX_DIG_RCCAL_CTRL1_RCCAL_CHARGE_OVRD_SHIFT (17U)
/*! RCCAL_CHARGE_OVRD - RCCAL_CHARGE Override Value
 */
#define XCVR_RX_DIG_RCCAL_CTRL1_RCCAL_CHARGE_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RCCAL_CTRL1_RCCAL_CHARGE_OVRD_SHIFT)) & XCVR_RX_DIG_RCCAL_CTRL1_RCCAL_CHARGE_OVRD_MASK)

#define XCVR_RX_DIG_RCCAL_CTRL1_RCCAL_DISCHARGE_OVRD_MASK (0x40000U)
#define XCVR_RX_DIG_RCCAL_CTRL1_RCCAL_DISCHARGE_OVRD_SHIFT (18U)
/*! RCCAL_DISCHARGE_OVRD - RCCAL_DISCHARGE Override Value
 */
#define XCVR_RX_DIG_RCCAL_CTRL1_RCCAL_DISCHARGE_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RCCAL_CTRL1_RCCAL_DISCHARGE_OVRD_SHIFT)) & XCVR_RX_DIG_RCCAL_CTRL1_RCCAL_DISCHARGE_OVRD_MASK)

#define XCVR_RX_DIG_RCCAL_CTRL1_RCCAL_CTRL_OVRD_EN_MASK (0x80000U)
#define XCVR_RX_DIG_RCCAL_CTRL1_RCCAL_CTRL_OVRD_EN_SHIFT (19U)
/*! RCCAL_CTRL_OVRD_EN - RCCAL Control Signals Override Enable
 */
#define XCVR_RX_DIG_RCCAL_CTRL1_RCCAL_CTRL_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RCCAL_CTRL1_RCCAL_CTRL_OVRD_EN_SHIFT)) & XCVR_RX_DIG_RCCAL_CTRL1_RCCAL_CTRL_OVRD_EN_MASK)
/*! @} */

/*! @name RCCAL_RES - RCCAL Result */
/*! @{ */

#define XCVR_RX_DIG_RCCAL_RES_RCCAL_CODE_MASK    (0x1FU)
#define XCVR_RX_DIG_RCCAL_RES_RCCAL_CODE_SHIFT   (0U)
/*! RCCAL_CODE - RCCAL_CODE
 */
#define XCVR_RX_DIG_RCCAL_RES_RCCAL_CODE(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RCCAL_RES_RCCAL_CODE_SHIFT)) & XCVR_RX_DIG_RCCAL_RES_RCCAL_CODE_MASK)

#define XCVR_RX_DIG_RCCAL_RES_CBPF_CCODE_MASK    (0x7F00U)
#define XCVR_RX_DIG_RCCAL_RES_CBPF_CCODE_SHIFT   (8U)
/*! CBPF_CCODE - CBPF_CCODE
 */
#define XCVR_RX_DIG_RCCAL_RES_CBPF_CCODE(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RCCAL_RES_CBPF_CCODE_SHIFT)) & XCVR_RX_DIG_RCCAL_RES_CBPF_CCODE_MASK)

#define XCVR_RX_DIG_RCCAL_RES_RCCAL_CMPOUT_MASK  (0x10000U)
#define XCVR_RX_DIG_RCCAL_RES_RCCAL_CMPOUT_SHIFT (16U)
/*! RCCAL_CMPOUT - RCCAL CMPOUT
 */
#define XCVR_RX_DIG_RCCAL_RES_RCCAL_CMPOUT(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RCCAL_RES_RCCAL_CMPOUT_SHIFT)) & XCVR_RX_DIG_RCCAL_RES_RCCAL_CMPOUT_MASK)
/*! @} */

/*! @name DCOC_CTRL0 - DCOC Control 0 */
/*! @{ */

#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_SFII_MASK    (0xFU)
#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_SFII_SHIFT   (0U)
/*! DCOC_SFII - DCOC_SFII
 */
#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_SFII(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL0_DCOC_SFII_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL0_DCOC_SFII_MASK)

#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_SFQQ_MASK    (0xF0U)
#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_SFQQ_SHIFT   (4U)
/*! DCOC_SFQQ - DCOC_SFQQ
 */
#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_SFQQ(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL0_DCOC_SFQQ_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL0_DCOC_SFQQ_MASK)

#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_SFIIP_MASK   (0x100U)
#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_SFIIP_SHIFT  (8U)
/*! DCOC_SFIIP - DCOC_SFIIP
 */
#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_SFIIP(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL0_DCOC_SFIIP_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL0_DCOC_SFIIP_MASK)

#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_SFQQP_MASK   (0x200U)
#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_SFQQP_SHIFT  (9U)
/*! DCOC_SFQQP - DCOC_SFQQP
 */
#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_SFQQP(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL0_DCOC_SFQQP_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL0_DCOC_SFQQP_MASK)

#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_SFIQ_MASK    (0x400U)
#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_SFIQ_SHIFT   (10U)
/*! DCOC_SFIQ - DCOC_SFIQ
 */
#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_SFIQ(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL0_DCOC_SFIQ_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL0_DCOC_SFIQ_MASK)

#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_SFQI_MASK    (0x800U)
#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_SFQI_SHIFT   (11U)
/*! DCOC_SFQI - DCOC_SFQI
 */
#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_SFQI(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL0_DCOC_SFQI_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL0_DCOC_SFQI_MASK)

#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_I_CAL_POL_MASK (0x1000U)
#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_I_CAL_POL_SHIFT (12U)
/*! DCOC_I_CAL_POL - DCOC_I_CAL_POL
 */
#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_I_CAL_POL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL0_DCOC_I_CAL_POL_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL0_DCOC_I_CAL_POL_MASK)

#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_Q_CAL_POL_MASK (0x2000U)
#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_Q_CAL_POL_SHIFT (13U)
/*! DCOC_Q_CAL_POL - DCOC_Q_CAL_POL
 */
#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_Q_CAL_POL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL0_DCOC_Q_CAL_POL_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL0_DCOC_Q_CAL_POL_MASK)

#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_DAC_ORDER_MASK (0x4000U)
#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_DAC_ORDER_SHIFT (14U)
/*! DCOC_DAC_ORDER - DCOC_DAC_ORDER
 *  0b0..DCOC I DAC is calibrated first
 *  0b1..DCOC Q DAC is calibrated first
 */
#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_DAC_ORDER(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL0_DCOC_DAC_ORDER_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL0_DCOC_DAC_ORDER_MASK)

#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_PULSE_CAPCODE_MASK (0x8000U)
#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_PULSE_CAPCODE_SHIFT (15U)
#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_PULSE_CAPCODE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL0_DCOC_PULSE_CAPCODE_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL0_DCOC_PULSE_CAPCODE_MASK)

#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_CBPF_STL_TIME_MASK (0xF0000U)
#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_CBPF_STL_TIME_SHIFT (16U)
/*! DCOC_CBPF_STL_TIME - DCOC CBPF Settle Time
 */
#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_CBPF_STL_TIME(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL0_DCOC_CBPF_STL_TIME_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL0_DCOC_CBPF_STL_TIME_MASK)

#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_SAR_STL_TIME_MASK (0xF00000U)
#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_SAR_STL_TIME_SHIFT (20U)
/*! DCOC_SAR_STL_TIME - DCOC CBPF Settle Time
 */
#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_SAR_STL_TIME(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL0_DCOC_SAR_STL_TIME_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL0_DCOC_SAR_STL_TIME_MASK)

#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_CAL_USE_OFFSET_MASK (0x1000000U)
#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_CAL_USE_OFFSET_SHIFT (24U)
/*! DCOC_CAL_USE_OFFSET
 *  0b0..Do not apply dcoc_i/qcbpf_offset during DCOC calibration
 *  0b1..Apply dcoc_i/qcbpf_offset during DCOC calibration
 */
#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_CAL_USE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL0_DCOC_CAL_USE_OFFSET_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL0_DCOC_CAL_USE_OFFSET_MASK)

#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_AVG_WIN_MASK (0x2000000U)
#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_AVG_WIN_SHIFT (25U)
/*! DCOC_AVG_WIN - DCOC Average Window Select
 *  0b0..4-sample
 *  0b1..8-sample
 */
#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_AVG_WIN(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL0_DCOC_AVG_WIN_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL0_DCOC_AVG_WIN_MASK)

#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_DIG_CORR_EN_MASK (0x4000000U)
#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_DIG_CORR_EN_SHIFT (26U)
/*! DCOC_DIG_CORR_EN - DCOC Digital Correction Enable
 */
#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_DIG_CORR_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL0_DCOC_DIG_CORR_EN_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL0_DCOC_DIG_CORR_EN_MASK)

#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_DAC_OVRD_EN_MASK (0x8000000U)
#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_DAC_OVRD_EN_SHIFT (27U)
/*! DCOC_DAC_OVRD_EN - DCOC_DAC_OVRD_EN
 */
#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_DAC_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL0_DCOC_DAC_OVRD_EN_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL0_DCOC_DAC_OVRD_EN_MASK)

#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_ADC_OFFSET_OVRD_EN_MASK (0x10000000U)
#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_ADC_OFFSET_OVRD_EN_SHIFT (28U)
/*! DCOC_ADC_OFFSET_OVRD_EN - DCOC_ADC_OFFSET_OVRD_EN
 */
#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_ADC_OFFSET_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL0_DCOC_ADC_OFFSET_OVRD_EN_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL0_DCOC_ADC_OFFSET_OVRD_EN_MASK)

#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_CBPF_SHORT_OVRD_MASK (0x20000000U)
#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_CBPF_SHORT_OVRD_SHIFT (29U)
/*! DCOC_CBPF_SHORT_OVRD - DCOC CBPF_SHORT Override Value
 */
#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_CBPF_SHORT_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL0_DCOC_CBPF_SHORT_OVRD_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL0_DCOC_CBPF_SHORT_OVRD_MASK)

#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_CBPF_HIZ_OVRD_MASK (0x40000000U)
#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_CBPF_HIZ_OVRD_SHIFT (30U)
/*! DCOC_CBPF_HIZ_OVRD - DCOC CBPF_HIZ Override Value
 */
#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_CBPF_HIZ_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL0_DCOC_CBPF_HIZ_OVRD_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL0_DCOC_CBPF_HIZ_OVRD_MASK)

#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_CBPF_HIZ_SHORT_OVRD_EN_MASK (0x80000000U)
#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_CBPF_HIZ_SHORT_OVRD_EN_SHIFT (31U)
/*! DCOC_CBPF_HIZ_SHORT_OVRD_EN - DCOC CBPF HIZ SHORT Override Enable
 */
#define XCVR_RX_DIG_DCOC_CTRL0_DCOC_CBPF_HIZ_SHORT_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL0_DCOC_CBPF_HIZ_SHORT_OVRD_EN_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL0_DCOC_CBPF_HIZ_SHORT_OVRD_EN_MASK)
/*! @} */

/*! @name DCOC_CTRL0_DRS - DCOC Control 0 DRS */
/*! @{ */

#define XCVR_RX_DIG_DCOC_CTRL0_DRS_DCOC_SFII_MASK (0xFU)
#define XCVR_RX_DIG_DCOC_CTRL0_DRS_DCOC_SFII_SHIFT (0U)
/*! DCOC_SFII - DCOC_SFII
 */
#define XCVR_RX_DIG_DCOC_CTRL0_DRS_DCOC_SFII(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL0_DRS_DCOC_SFII_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL0_DRS_DCOC_SFII_MASK)

#define XCVR_RX_DIG_DCOC_CTRL0_DRS_DCOC_SFQQ_MASK (0xF0U)
#define XCVR_RX_DIG_DCOC_CTRL0_DRS_DCOC_SFQQ_SHIFT (4U)
/*! DCOC_SFQQ - DCOC_SFQQ
 */
#define XCVR_RX_DIG_DCOC_CTRL0_DRS_DCOC_SFQQ(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL0_DRS_DCOC_SFQQ_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL0_DRS_DCOC_SFQQ_MASK)

#define XCVR_RX_DIG_DCOC_CTRL0_DRS_DCOC_SFIIP_MASK (0x100U)
#define XCVR_RX_DIG_DCOC_CTRL0_DRS_DCOC_SFIIP_SHIFT (8U)
/*! DCOC_SFIIP - DCOC_SFIIP
 */
#define XCVR_RX_DIG_DCOC_CTRL0_DRS_DCOC_SFIIP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL0_DRS_DCOC_SFIIP_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL0_DRS_DCOC_SFIIP_MASK)

#define XCVR_RX_DIG_DCOC_CTRL0_DRS_DCOC_SFQQP_MASK (0x200U)
#define XCVR_RX_DIG_DCOC_CTRL0_DRS_DCOC_SFQQP_SHIFT (9U)
/*! DCOC_SFQQP - DCOC_SFQQP
 */
#define XCVR_RX_DIG_DCOC_CTRL0_DRS_DCOC_SFQQP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL0_DRS_DCOC_SFQQP_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL0_DRS_DCOC_SFQQP_MASK)
/*! @} */

/*! @name DCOC_CTRL1 - DCOC CONTROL 1 */
/*! @{ */

#define XCVR_RX_DIG_DCOC_CTRL1_DCOC_ILNA_OFFSET_MASK (0x3FU)
#define XCVR_RX_DIG_DCOC_CTRL1_DCOC_ILNA_OFFSET_SHIFT (0U)
/*! DCOC_ILNA_OFFSET - DCOC_ILNA_OFFSET
 */
#define XCVR_RX_DIG_DCOC_CTRL1_DCOC_ILNA_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL1_DCOC_ILNA_OFFSET_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL1_DCOC_ILNA_OFFSET_MASK)

#define XCVR_RX_DIG_DCOC_CTRL1_DCOC_QLNA_OFFSET_MASK (0x3F00U)
#define XCVR_RX_DIG_DCOC_CTRL1_DCOC_QLNA_OFFSET_SHIFT (8U)
/*! DCOC_QLNA_OFFSET - DCOC_QLNA_OFFSET
 */
#define XCVR_RX_DIG_DCOC_CTRL1_DCOC_QLNA_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL1_DCOC_QLNA_OFFSET_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL1_DCOC_QLNA_OFFSET_MASK)

#define XCVR_RX_DIG_DCOC_CTRL1_DCOC_ICBPF_OFFSET_MASK (0x3F0000U)
#define XCVR_RX_DIG_DCOC_CTRL1_DCOC_ICBPF_OFFSET_SHIFT (16U)
/*! DCOC_ICBPF_OFFSET - DCOC_ICBPF_OFFSET
 */
#define XCVR_RX_DIG_DCOC_CTRL1_DCOC_ICBPF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL1_DCOC_ICBPF_OFFSET_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL1_DCOC_ICBPF_OFFSET_MASK)

#define XCVR_RX_DIG_DCOC_CTRL1_DCOC_QCBPF_OFFSET_MASK (0x3F000000U)
#define XCVR_RX_DIG_DCOC_CTRL1_DCOC_QCBPF_OFFSET_SHIFT (24U)
/*! DCOC_QCBPF_OFFSET - DCOC_QCBPF_OFFSET
 */
#define XCVR_RX_DIG_DCOC_CTRL1_DCOC_QCBPF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL1_DCOC_QCBPF_OFFSET_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL1_DCOC_QCBPF_OFFSET_MASK)
/*! @} */

/*! @name DCOC_CTRL2 - DCOC CONTROL 2 */
/*! @{ */

#define XCVR_RX_DIG_DCOC_CTRL2_DCOC_DAC_OVRD_I_MASK (0x3FU)
#define XCVR_RX_DIG_DCOC_CTRL2_DCOC_DAC_OVRD_I_SHIFT (0U)
/*! DCOC_DAC_OVRD_I - DCOC_DAC_OVRD_I
 */
#define XCVR_RX_DIG_DCOC_CTRL2_DCOC_DAC_OVRD_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL2_DCOC_DAC_OVRD_I_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL2_DCOC_DAC_OVRD_I_MASK)

#define XCVR_RX_DIG_DCOC_CTRL2_DCOC_DAC_OVRD_Q_MASK (0x3F00U)
#define XCVR_RX_DIG_DCOC_CTRL2_DCOC_DAC_OVRD_Q_SHIFT (8U)
/*! DCOC_DAC_OVRD_Q - DCOC_DAC_OVRD_Q
 */
#define XCVR_RX_DIG_DCOC_CTRL2_DCOC_DAC_OVRD_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL2_DCOC_DAC_OVRD_Q_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL2_DCOC_DAC_OVRD_Q_MASK)

#define XCVR_RX_DIG_DCOC_CTRL2_DCOC_ADC_OFFSET_OVRD_I_MASK (0x7F0000U)
#define XCVR_RX_DIG_DCOC_CTRL2_DCOC_ADC_OFFSET_OVRD_I_SHIFT (16U)
/*! DCOC_ADC_OFFSET_OVRD_I - DCOC_ADC_OFFSET_OVRD_I
 */
#define XCVR_RX_DIG_DCOC_CTRL2_DCOC_ADC_OFFSET_OVRD_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL2_DCOC_ADC_OFFSET_OVRD_I_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL2_DCOC_ADC_OFFSET_OVRD_I_MASK)

#define XCVR_RX_DIG_DCOC_CTRL2_DCOC_ADC_OFFSET_OVRD_Q_MASK (0x7F000000U)
#define XCVR_RX_DIG_DCOC_CTRL2_DCOC_ADC_OFFSET_OVRD_Q_SHIFT (24U)
/*! DCOC_ADC_OFFSET_OVRD_Q - DCOC_ADC_OFFSET_OVRD_Q
 */
#define XCVR_RX_DIG_DCOC_CTRL2_DCOC_ADC_OFFSET_OVRD_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL2_DCOC_ADC_OFFSET_OVRD_Q_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL2_DCOC_ADC_OFFSET_OVRD_Q_MASK)
/*! @} */

/*! @name DCOC_STAT - DCOC Status */
/*! @{ */

#define XCVR_RX_DIG_DCOC_STAT_CBPF_CODE_DCOC_I_MASK (0x3FU)
#define XCVR_RX_DIG_DCOC_STAT_CBPF_CODE_DCOC_I_SHIFT (0U)
/*! CBPF_CODE_DCOC_I - CBPF_CODE_DCOC_I
 */
#define XCVR_RX_DIG_DCOC_STAT_CBPF_CODE_DCOC_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_STAT_CBPF_CODE_DCOC_I_SHIFT)) & XCVR_RX_DIG_DCOC_STAT_CBPF_CODE_DCOC_I_MASK)

#define XCVR_RX_DIG_DCOC_STAT_CBPF_CODE_DCOC_Q_MASK (0x3F00U)
#define XCVR_RX_DIG_DCOC_STAT_CBPF_CODE_DCOC_Q_SHIFT (8U)
/*! CBPF_CODE_DCOC_Q - CBPF_CODE_DCOC_Q
 */
#define XCVR_RX_DIG_DCOC_STAT_CBPF_CODE_DCOC_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_STAT_CBPF_CODE_DCOC_Q_SHIFT)) & XCVR_RX_DIG_DCOC_STAT_CBPF_CODE_DCOC_Q_MASK)

#define XCVR_RX_DIG_DCOC_STAT_DCOC_ADC_OFFSET_I_MASK (0x7F0000U)
#define XCVR_RX_DIG_DCOC_STAT_DCOC_ADC_OFFSET_I_SHIFT (16U)
/*! DCOC_ADC_OFFSET_I - DCOC_ADC_OFFSET_I
 */
#define XCVR_RX_DIG_DCOC_STAT_DCOC_ADC_OFFSET_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_STAT_DCOC_ADC_OFFSET_I_SHIFT)) & XCVR_RX_DIG_DCOC_STAT_DCOC_ADC_OFFSET_I_MASK)

#define XCVR_RX_DIG_DCOC_STAT_DCOC_ADC_OFFSET_Q_MASK (0x7F000000U)
#define XCVR_RX_DIG_DCOC_STAT_DCOC_ADC_OFFSET_Q_SHIFT (24U)
/*! DCOC_ADC_OFFSET_Q - DCOC_ADC_OFFSET_Q
 */
#define XCVR_RX_DIG_DCOC_STAT_DCOC_ADC_OFFSET_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_STAT_DCOC_ADC_OFFSET_Q_SHIFT)) & XCVR_RX_DIG_DCOC_STAT_DCOC_ADC_OFFSET_Q_MASK)
/*! @} */

/*! @name IQMC_CTRL0 - IQ Mismatch Control 0 */
/*! @{ */

#define XCVR_RX_DIG_IQMC_CTRL0_IQMC_CAL_EN_MASK  (0x1U)
#define XCVR_RX_DIG_IQMC_CTRL0_IQMC_CAL_EN_SHIFT (0U)
/*! IQMC_CAL_EN - IQ Mismatch Cal Enable
 */
#define XCVR_RX_DIG_IQMC_CTRL0_IQMC_CAL_EN(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_IQMC_CTRL0_IQMC_CAL_EN_SHIFT)) & XCVR_RX_DIG_IQMC_CTRL0_IQMC_CAL_EN_MASK)

#define XCVR_RX_DIG_IQMC_CTRL0_IQMC_CAL_FREQ_SEL_MASK (0x2U)
#define XCVR_RX_DIG_IQMC_CTRL0_IQMC_CAL_FREQ_SEL_SHIFT (1U)
/*! IQMC_CAL_FREQ_SEL - IQMC_CAL_FREQ_SEL
 *  0b0..Reference clk divided by 2
 *  0b1..Reference clk divided by 4
 */
#define XCVR_RX_DIG_IQMC_CTRL0_IQMC_CAL_FREQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_IQMC_CTRL0_IQMC_CAL_FREQ_SEL_SHIFT)) & XCVR_RX_DIG_IQMC_CTRL0_IQMC_CAL_FREQ_SEL_MASK)

#define XCVR_RX_DIG_IQMC_CTRL0_IQMC_NUM_ITER_MASK (0xFF00U)
#define XCVR_RX_DIG_IQMC_CTRL0_IQMC_NUM_ITER_SHIFT (8U)
/*! IQMC_NUM_ITER - IQ Mismatch Cal Num Iter
 */
#define XCVR_RX_DIG_IQMC_CTRL0_IQMC_NUM_ITER(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_IQMC_CTRL0_IQMC_NUM_ITER_SHIFT)) & XCVR_RX_DIG_IQMC_CTRL0_IQMC_NUM_ITER_MASK)

#define XCVR_RX_DIG_IQMC_CTRL0_IQMC_DC_GAIN_ADJ_MASK (0x7FF0000U)
#define XCVR_RX_DIG_IQMC_CTRL0_IQMC_DC_GAIN_ADJ_SHIFT (16U)
#define XCVR_RX_DIG_IQMC_CTRL0_IQMC_DC_GAIN_ADJ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_IQMC_CTRL0_IQMC_DC_GAIN_ADJ_SHIFT)) & XCVR_RX_DIG_IQMC_CTRL0_IQMC_DC_GAIN_ADJ_MASK)
/*! @} */

/*! @name IQMC_CTRL1 - IQ Mismatch Control 1 */
/*! @{ */

#define XCVR_RX_DIG_IQMC_CTRL1_IQMC_GAIN_ADJ_MASK (0x7FFU)
#define XCVR_RX_DIG_IQMC_CTRL1_IQMC_GAIN_ADJ_SHIFT (0U)
/*! IQMC_GAIN_ADJ - IQ Mismatch Correction Gain Coeff
 */
#define XCVR_RX_DIG_IQMC_CTRL1_IQMC_GAIN_ADJ(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_IQMC_CTRL1_IQMC_GAIN_ADJ_SHIFT)) & XCVR_RX_DIG_IQMC_CTRL1_IQMC_GAIN_ADJ_MASK)

#define XCVR_RX_DIG_IQMC_CTRL1_IQMC_PHASE_ADJ_MASK (0xFFF0000U)
#define XCVR_RX_DIG_IQMC_CTRL1_IQMC_PHASE_ADJ_SHIFT (16U)
/*! IQMC_PHASE_ADJ - IQ Mismatch Correction Phase Coeff
 */
#define XCVR_RX_DIG_IQMC_CTRL1_IQMC_PHASE_ADJ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_IQMC_CTRL1_IQMC_PHASE_ADJ_SHIFT)) & XCVR_RX_DIG_IQMC_CTRL1_IQMC_PHASE_ADJ_MASK)
/*! @} */

/*! @name ACQ_FILT_0_3 - Acquisition Filter Coeffs 0~3 */
/*! @{ */

#define XCVR_RX_DIG_ACQ_FILT_0_3_H0_MASK         (0x3FU)
#define XCVR_RX_DIG_ACQ_FILT_0_3_H0_SHIFT        (0U)
/*! H0 - Acquisition Filter Coefficient 0
 */
#define XCVR_RX_DIG_ACQ_FILT_0_3_H0(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_ACQ_FILT_0_3_H0_SHIFT)) & XCVR_RX_DIG_ACQ_FILT_0_3_H0_MASK)

#define XCVR_RX_DIG_ACQ_FILT_0_3_H1_MASK         (0x3F00U)
#define XCVR_RX_DIG_ACQ_FILT_0_3_H1_SHIFT        (8U)
/*! H1 - Acquisition Filter Coefficient 1
 */
#define XCVR_RX_DIG_ACQ_FILT_0_3_H1(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_ACQ_FILT_0_3_H1_SHIFT)) & XCVR_RX_DIG_ACQ_FILT_0_3_H1_MASK)

#define XCVR_RX_DIG_ACQ_FILT_0_3_H2_MASK         (0x7F0000U)
#define XCVR_RX_DIG_ACQ_FILT_0_3_H2_SHIFT        (16U)
/*! H2 - Acquisition Filter Coefficient 2
 */
#define XCVR_RX_DIG_ACQ_FILT_0_3_H2(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_ACQ_FILT_0_3_H2_SHIFT)) & XCVR_RX_DIG_ACQ_FILT_0_3_H2_MASK)

#define XCVR_RX_DIG_ACQ_FILT_0_3_H3_MASK         (0x7F000000U)
#define XCVR_RX_DIG_ACQ_FILT_0_3_H3_SHIFT        (24U)
/*! H3 - Acquisition Filter Coefficient 3
 */
#define XCVR_RX_DIG_ACQ_FILT_0_3_H3(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_ACQ_FILT_0_3_H3_SHIFT)) & XCVR_RX_DIG_ACQ_FILT_0_3_H3_MASK)
/*! @} */

/*! @name ACQ_FILT_4_7 - Acquisition Filter Coeffs 4~7 */
/*! @{ */

#define XCVR_RX_DIG_ACQ_FILT_4_7_H4_MASK         (0x7FU)
#define XCVR_RX_DIG_ACQ_FILT_4_7_H4_SHIFT        (0U)
/*! H4 - Acquisition Filter Coefficient 4
 */
#define XCVR_RX_DIG_ACQ_FILT_4_7_H4(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_ACQ_FILT_4_7_H4_SHIFT)) & XCVR_RX_DIG_ACQ_FILT_4_7_H4_MASK)

#define XCVR_RX_DIG_ACQ_FILT_4_7_H5_MASK         (0x7F00U)
#define XCVR_RX_DIG_ACQ_FILT_4_7_H5_SHIFT        (8U)
/*! H5 - Acquisition Filter Coefficient 5
 */
#define XCVR_RX_DIG_ACQ_FILT_4_7_H5(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_ACQ_FILT_4_7_H5_SHIFT)) & XCVR_RX_DIG_ACQ_FILT_4_7_H5_MASK)

#define XCVR_RX_DIG_ACQ_FILT_4_7_H6_MASK         (0xFF0000U)
#define XCVR_RX_DIG_ACQ_FILT_4_7_H6_SHIFT        (16U)
/*! H6 - Acquisition Filter Coefficient 6
 */
#define XCVR_RX_DIG_ACQ_FILT_4_7_H6(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_ACQ_FILT_4_7_H6_SHIFT)) & XCVR_RX_DIG_ACQ_FILT_4_7_H6_MASK)

#define XCVR_RX_DIG_ACQ_FILT_4_7_H7_MASK         (0xFF000000U)
#define XCVR_RX_DIG_ACQ_FILT_4_7_H7_SHIFT        (24U)
/*! H7 - Acquisition Filter Coefficient 7
 */
#define XCVR_RX_DIG_ACQ_FILT_4_7_H7(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_ACQ_FILT_4_7_H7_SHIFT)) & XCVR_RX_DIG_ACQ_FILT_4_7_H7_MASK)
/*! @} */

/*! @name ACQ_FILT_8_9 - Acquisition Filter Coeffs 8~9 */
/*! @{ */

#define XCVR_RX_DIG_ACQ_FILT_8_9_H8_MASK         (0x1FFU)
#define XCVR_RX_DIG_ACQ_FILT_8_9_H8_SHIFT        (0U)
/*! H8 - Acquisition Filter Coefficient 8
 */
#define XCVR_RX_DIG_ACQ_FILT_8_9_H8(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_ACQ_FILT_8_9_H8_SHIFT)) & XCVR_RX_DIG_ACQ_FILT_8_9_H8_MASK)

#define XCVR_RX_DIG_ACQ_FILT_8_9_H9_MASK         (0x1FF0000U)
#define XCVR_RX_DIG_ACQ_FILT_8_9_H9_SHIFT        (16U)
/*! H9 - Acquisition Filter Coefficient 9
 */
#define XCVR_RX_DIG_ACQ_FILT_8_9_H9(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_ACQ_FILT_8_9_H9_SHIFT)) & XCVR_RX_DIG_ACQ_FILT_8_9_H9_MASK)
/*! @} */

/*! @name ACQ_FILT_10_11 - Acquisition Filter Coeffs 10~11 */
/*! @{ */

#define XCVR_RX_DIG_ACQ_FILT_10_11_H10_MASK      (0x3FFU)
#define XCVR_RX_DIG_ACQ_FILT_10_11_H10_SHIFT     (0U)
/*! H10 - Acquisition Filter Coefficient 10
 */
#define XCVR_RX_DIG_ACQ_FILT_10_11_H10(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_ACQ_FILT_10_11_H10_SHIFT)) & XCVR_RX_DIG_ACQ_FILT_10_11_H10_MASK)

#define XCVR_RX_DIG_ACQ_FILT_10_11_H11_MASK      (0x3FF0000U)
#define XCVR_RX_DIG_ACQ_FILT_10_11_H11_SHIFT     (16U)
/*! H11 - Acquisition Filter Coefficient 11
 */
#define XCVR_RX_DIG_ACQ_FILT_10_11_H11(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_ACQ_FILT_10_11_H11_SHIFT)) & XCVR_RX_DIG_ACQ_FILT_10_11_H11_MASK)
/*! @} */

/*! @name DEMOD_FILT_0_1 - Demod Filter Coeffs 0~1 */
/*! @{ */

#define XCVR_RX_DIG_DEMOD_FILT_0_1_H0_MASK       (0x1FFU)
#define XCVR_RX_DIG_DEMOD_FILT_0_1_H0_SHIFT      (0U)
/*! H0 - Demod Channel Filter Coefficient 0
 */
#define XCVR_RX_DIG_DEMOD_FILT_0_1_H0(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DEMOD_FILT_0_1_H0_SHIFT)) & XCVR_RX_DIG_DEMOD_FILT_0_1_H0_MASK)

#define XCVR_RX_DIG_DEMOD_FILT_0_1_H1_MASK       (0x1FF0000U)
#define XCVR_RX_DIG_DEMOD_FILT_0_1_H1_SHIFT      (16U)
/*! H1 - Demod Channel Filter Coefficient 1
 */
#define XCVR_RX_DIG_DEMOD_FILT_0_1_H1(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DEMOD_FILT_0_1_H1_SHIFT)) & XCVR_RX_DIG_DEMOD_FILT_0_1_H1_MASK)
/*! @} */

/*! @name DEMOD_FILT_2_4 - Demod Filter Coeffs 2~4 */
/*! @{ */

#define XCVR_RX_DIG_DEMOD_FILT_2_4_H2_MASK       (0x3FFU)
#define XCVR_RX_DIG_DEMOD_FILT_2_4_H2_SHIFT      (0U)
/*! H2 - Demod Channel Filter Coefficient 2
 */
#define XCVR_RX_DIG_DEMOD_FILT_2_4_H2(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DEMOD_FILT_2_4_H2_SHIFT)) & XCVR_RX_DIG_DEMOD_FILT_2_4_H2_MASK)

#define XCVR_RX_DIG_DEMOD_FILT_2_4_H3_MASK       (0xFFC00U)
#define XCVR_RX_DIG_DEMOD_FILT_2_4_H3_SHIFT      (10U)
/*! H3 - Demod Channel Filter Coefficient 3
 */
#define XCVR_RX_DIG_DEMOD_FILT_2_4_H3(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DEMOD_FILT_2_4_H3_SHIFT)) & XCVR_RX_DIG_DEMOD_FILT_2_4_H3_MASK)

#define XCVR_RX_DIG_DEMOD_FILT_2_4_H4_MASK       (0x3FF00000U)
#define XCVR_RX_DIG_DEMOD_FILT_2_4_H4_SHIFT      (20U)
/*! H4 - Demod Channel Filter Coefficient 4
 */
#define XCVR_RX_DIG_DEMOD_FILT_2_4_H4(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DEMOD_FILT_2_4_H4_SHIFT)) & XCVR_RX_DIG_DEMOD_FILT_2_4_H4_MASK)
/*! @} */

/*! @name ACQ_FILT_0_3_DRS - Acquisition Filter Coeffs 0~3 DRS */
/*! @{ */

#define XCVR_RX_DIG_ACQ_FILT_0_3_DRS_H0_MASK     (0x3FU)
#define XCVR_RX_DIG_ACQ_FILT_0_3_DRS_H0_SHIFT    (0U)
/*! H0 - Acquisition Filter Coefficient 0
 */
#define XCVR_RX_DIG_ACQ_FILT_0_3_DRS_H0(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_ACQ_FILT_0_3_DRS_H0_SHIFT)) & XCVR_RX_DIG_ACQ_FILT_0_3_DRS_H0_MASK)

#define XCVR_RX_DIG_ACQ_FILT_0_3_DRS_H1_MASK     (0x3F00U)
#define XCVR_RX_DIG_ACQ_FILT_0_3_DRS_H1_SHIFT    (8U)
/*! H1 - Acquisition Filter Coefficient 1
 */
#define XCVR_RX_DIG_ACQ_FILT_0_3_DRS_H1(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_ACQ_FILT_0_3_DRS_H1_SHIFT)) & XCVR_RX_DIG_ACQ_FILT_0_3_DRS_H1_MASK)

#define XCVR_RX_DIG_ACQ_FILT_0_3_DRS_H2_MASK     (0x7F0000U)
#define XCVR_RX_DIG_ACQ_FILT_0_3_DRS_H2_SHIFT    (16U)
/*! H2 - Acquisition Filter Coefficient 2
 */
#define XCVR_RX_DIG_ACQ_FILT_0_3_DRS_H2(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_ACQ_FILT_0_3_DRS_H2_SHIFT)) & XCVR_RX_DIG_ACQ_FILT_0_3_DRS_H2_MASK)

#define XCVR_RX_DIG_ACQ_FILT_0_3_DRS_H3_MASK     (0x7F000000U)
#define XCVR_RX_DIG_ACQ_FILT_0_3_DRS_H3_SHIFT    (24U)
/*! H3 - Acquisition Filter Coefficient 3
 */
#define XCVR_RX_DIG_ACQ_FILT_0_3_DRS_H3(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_ACQ_FILT_0_3_DRS_H3_SHIFT)) & XCVR_RX_DIG_ACQ_FILT_0_3_DRS_H3_MASK)
/*! @} */

/*! @name ACQ_FILT_4_7_DRS - Acquisition Filter Coeffs 4~7 DRS */
/*! @{ */

#define XCVR_RX_DIG_ACQ_FILT_4_7_DRS_H4_MASK     (0x7FU)
#define XCVR_RX_DIG_ACQ_FILT_4_7_DRS_H4_SHIFT    (0U)
/*! H4 - Acquisition Filter Coefficient 4
 */
#define XCVR_RX_DIG_ACQ_FILT_4_7_DRS_H4(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_ACQ_FILT_4_7_DRS_H4_SHIFT)) & XCVR_RX_DIG_ACQ_FILT_4_7_DRS_H4_MASK)

#define XCVR_RX_DIG_ACQ_FILT_4_7_DRS_H5_MASK     (0x7F00U)
#define XCVR_RX_DIG_ACQ_FILT_4_7_DRS_H5_SHIFT    (8U)
/*! H5 - Acquisition Filter Coefficient 5
 */
#define XCVR_RX_DIG_ACQ_FILT_4_7_DRS_H5(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_ACQ_FILT_4_7_DRS_H5_SHIFT)) & XCVR_RX_DIG_ACQ_FILT_4_7_DRS_H5_MASK)

#define XCVR_RX_DIG_ACQ_FILT_4_7_DRS_H6_MASK     (0xFF0000U)
#define XCVR_RX_DIG_ACQ_FILT_4_7_DRS_H6_SHIFT    (16U)
/*! H6 - Acquisition Filter Coefficient 6
 */
#define XCVR_RX_DIG_ACQ_FILT_4_7_DRS_H6(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_ACQ_FILT_4_7_DRS_H6_SHIFT)) & XCVR_RX_DIG_ACQ_FILT_4_7_DRS_H6_MASK)

#define XCVR_RX_DIG_ACQ_FILT_4_7_DRS_H7_MASK     (0xFF000000U)
#define XCVR_RX_DIG_ACQ_FILT_4_7_DRS_H7_SHIFT    (24U)
/*! H7 - Acquisition Filter Coefficient 7
 */
#define XCVR_RX_DIG_ACQ_FILT_4_7_DRS_H7(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_ACQ_FILT_4_7_DRS_H7_SHIFT)) & XCVR_RX_DIG_ACQ_FILT_4_7_DRS_H7_MASK)
/*! @} */

/*! @name ACQ_FILT_8_9_DRS - Acquisition Filter Coeffs 8~9 DRS */
/*! @{ */

#define XCVR_RX_DIG_ACQ_FILT_8_9_DRS_H8_MASK     (0x1FFU)
#define XCVR_RX_DIG_ACQ_FILT_8_9_DRS_H8_SHIFT    (0U)
/*! H8 - Acquisition Filter Coefficient 8
 */
#define XCVR_RX_DIG_ACQ_FILT_8_9_DRS_H8(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_ACQ_FILT_8_9_DRS_H8_SHIFT)) & XCVR_RX_DIG_ACQ_FILT_8_9_DRS_H8_MASK)

#define XCVR_RX_DIG_ACQ_FILT_8_9_DRS_H9_MASK     (0x1FF0000U)
#define XCVR_RX_DIG_ACQ_FILT_8_9_DRS_H9_SHIFT    (16U)
/*! H9 - Acquisition Filter Coefficient 9
 */
#define XCVR_RX_DIG_ACQ_FILT_8_9_DRS_H9(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_ACQ_FILT_8_9_DRS_H9_SHIFT)) & XCVR_RX_DIG_ACQ_FILT_8_9_DRS_H9_MASK)
/*! @} */

/*! @name ACQ_FILT_10_11_DRS - Acquisition Filter Coeffs 10~11 DRS */
/*! @{ */

#define XCVR_RX_DIG_ACQ_FILT_10_11_DRS_H10_MASK  (0x3FFU)
#define XCVR_RX_DIG_ACQ_FILT_10_11_DRS_H10_SHIFT (0U)
/*! H10 - Acquisition Filter Coefficient 10
 */
#define XCVR_RX_DIG_ACQ_FILT_10_11_DRS_H10(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_ACQ_FILT_10_11_DRS_H10_SHIFT)) & XCVR_RX_DIG_ACQ_FILT_10_11_DRS_H10_MASK)

#define XCVR_RX_DIG_ACQ_FILT_10_11_DRS_H11_MASK  (0x3FF0000U)
#define XCVR_RX_DIG_ACQ_FILT_10_11_DRS_H11_SHIFT (16U)
/*! H11 - Acquisition Filter Coefficient 11
 */
#define XCVR_RX_DIG_ACQ_FILT_10_11_DRS_H11(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_ACQ_FILT_10_11_DRS_H11_SHIFT)) & XCVR_RX_DIG_ACQ_FILT_10_11_DRS_H11_MASK)
/*! @} */

/*! @name DEMOD_FILT_0_1_DRS - Demod Filter Coeffs 0~1 DRS */
/*! @{ */

#define XCVR_RX_DIG_DEMOD_FILT_0_1_DRS_H0_MASK   (0x1FFU)
#define XCVR_RX_DIG_DEMOD_FILT_0_1_DRS_H0_SHIFT  (0U)
/*! H0 - Demod Channel Filter Coefficient 0
 */
#define XCVR_RX_DIG_DEMOD_FILT_0_1_DRS_H0(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DEMOD_FILT_0_1_DRS_H0_SHIFT)) & XCVR_RX_DIG_DEMOD_FILT_0_1_DRS_H0_MASK)

#define XCVR_RX_DIG_DEMOD_FILT_0_1_DRS_H1_MASK   (0x1FF0000U)
#define XCVR_RX_DIG_DEMOD_FILT_0_1_DRS_H1_SHIFT  (16U)
/*! H1 - Demod Channel Filter Coefficient 1
 */
#define XCVR_RX_DIG_DEMOD_FILT_0_1_DRS_H1(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DEMOD_FILT_0_1_DRS_H1_SHIFT)) & XCVR_RX_DIG_DEMOD_FILT_0_1_DRS_H1_MASK)
/*! @} */

/*! @name DEMOD_FILT_2_4_DRS - Demod Filter Coeffs 2~4 DRS */
/*! @{ */

#define XCVR_RX_DIG_DEMOD_FILT_2_4_DRS_H2_MASK   (0x3FFU)
#define XCVR_RX_DIG_DEMOD_FILT_2_4_DRS_H2_SHIFT  (0U)
/*! H2 - Demod Channel Filter Coefficient 2
 */
#define XCVR_RX_DIG_DEMOD_FILT_2_4_DRS_H2(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DEMOD_FILT_2_4_DRS_H2_SHIFT)) & XCVR_RX_DIG_DEMOD_FILT_2_4_DRS_H2_MASK)

#define XCVR_RX_DIG_DEMOD_FILT_2_4_DRS_H3_MASK   (0xFFC00U)
#define XCVR_RX_DIG_DEMOD_FILT_2_4_DRS_H3_SHIFT  (10U)
/*! H3 - Demod Channel Filter Coefficient 3
 */
#define XCVR_RX_DIG_DEMOD_FILT_2_4_DRS_H3(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DEMOD_FILT_2_4_DRS_H3_SHIFT)) & XCVR_RX_DIG_DEMOD_FILT_2_4_DRS_H3_MASK)

#define XCVR_RX_DIG_DEMOD_FILT_2_4_DRS_H4_MASK   (0x3FF00000U)
#define XCVR_RX_DIG_DEMOD_FILT_2_4_DRS_H4_SHIFT  (20U)
/*! H4 - Demod Channel Filter Coefficient 4
 */
#define XCVR_RX_DIG_DEMOD_FILT_2_4_DRS_H4(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DEMOD_FILT_2_4_DRS_H4_SHIFT)) & XCVR_RX_DIG_DEMOD_FILT_2_4_DRS_H4_MASK)
/*! @} */

/*! @name RSSI_GLOBAL_CTRL - RSSI Global Control */
/*! @{ */

#define XCVR_RX_DIG_RSSI_GLOBAL_CTRL_NB_RSSI_INPUT_SEL_MASK (0x3U)
#define XCVR_RX_DIG_RSSI_GLOBAL_CTRL_NB_RSSI_INPUT_SEL_SHIFT (0U)
/*! NB_RSSI_INPUT_SEL - NB RSSI Input Select
 *  0b00..ACQ_CHF output I/Q
 *  0b01..SRC output I/Q
 *  0b10..DEMOD_CHF output I/Q
 *  0b11..
 */
#define XCVR_RX_DIG_RSSI_GLOBAL_CTRL_NB_RSSI_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_GLOBAL_CTRL_NB_RSSI_INPUT_SEL_SHIFT)) & XCVR_RX_DIG_RSSI_GLOBAL_CTRL_NB_RSSI_INPUT_SEL_MASK)

#define XCVR_RX_DIG_RSSI_GLOBAL_CTRL_NB_RSSI_AA_MATCH_OVRD_MASK (0x4U)
#define XCVR_RX_DIG_RSSI_GLOBAL_CTRL_NB_RSSI_AA_MATCH_OVRD_SHIFT (2U)
/*! NB_RSSI_AA_MATCH_OVRD - NB RSSI PHY Trigger Override
 */
#define XCVR_RX_DIG_RSSI_GLOBAL_CTRL_NB_RSSI_AA_MATCH_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_GLOBAL_CTRL_NB_RSSI_AA_MATCH_OVRD_SHIFT)) & XCVR_RX_DIG_RSSI_GLOBAL_CTRL_NB_RSSI_AA_MATCH_OVRD_MASK)

#define XCVR_RX_DIG_RSSI_GLOBAL_CTRL_NB_RSSI_AA_MATCH_OVRD_EN_MASK (0x8U)
#define XCVR_RX_DIG_RSSI_GLOBAL_CTRL_NB_RSSI_AA_MATCH_OVRD_EN_SHIFT (3U)
/*! NB_RSSI_AA_MATCH_OVRD_EN - NB RSSI PHY Trigger Override Enable
 */
#define XCVR_RX_DIG_RSSI_GLOBAL_CTRL_NB_RSSI_AA_MATCH_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_GLOBAL_CTRL_NB_RSSI_AA_MATCH_OVRD_EN_SHIFT)) & XCVR_RX_DIG_RSSI_GLOBAL_CTRL_NB_RSSI_AA_MATCH_OVRD_EN_MASK)

#define XCVR_RX_DIG_RSSI_GLOBAL_CTRL_NB_RSSI_PA_AA_MATCH_SEL_MASK (0x10U)
#define XCVR_RX_DIG_RSSI_GLOBAL_CTRL_NB_RSSI_PA_AA_MATCH_SEL_SHIFT (4U)
/*! NB_RSSI_PA_AA_MATCH_SEL - NB RSSI PHY Trigger Select
 *  0b0..NB-RSSI starts work when PHY_PD_FOUND asserted
 *  0b1..NB-RSSI starts work when PHY_AA_MATCH asserted
 */
#define XCVR_RX_DIG_RSSI_GLOBAL_CTRL_NB_RSSI_PA_AA_MATCH_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_GLOBAL_CTRL_NB_RSSI_PA_AA_MATCH_SEL_SHIFT)) & XCVR_RX_DIG_RSSI_GLOBAL_CTRL_NB_RSSI_PA_AA_MATCH_SEL_MASK)

#define XCVR_RX_DIG_RSSI_GLOBAL_CTRL_NB_CCA1_ED_EN_MASK (0x20U)
#define XCVR_RX_DIG_RSSI_GLOBAL_CTRL_NB_CCA1_ED_EN_SHIFT (5U)
/*! NB_CCA1_ED_EN - NB RSSI CCA1 ED Enable
 *  0b0..NB-RSSI CCA1/ED is disabled
 *  0b1..NB-RSSI CCA1/ED is enabled
 */
#define XCVR_RX_DIG_RSSI_GLOBAL_CTRL_NB_CCA1_ED_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_GLOBAL_CTRL_NB_CCA1_ED_EN_SHIFT)) & XCVR_RX_DIG_RSSI_GLOBAL_CTRL_NB_CCA1_ED_EN_MASK)

#define XCVR_RX_DIG_RSSI_GLOBAL_CTRL_NB_CONT_MEAS_OVRD_MASK (0x40U)
#define XCVR_RX_DIG_RSSI_GLOBAL_CTRL_NB_CONT_MEAS_OVRD_SHIFT (6U)
/*! NB_CONT_MEAS_OVRD - NB RSSI Onetime Measure Override
 */
#define XCVR_RX_DIG_RSSI_GLOBAL_CTRL_NB_CONT_MEAS_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_GLOBAL_CTRL_NB_CONT_MEAS_OVRD_SHIFT)) & XCVR_RX_DIG_RSSI_GLOBAL_CTRL_NB_CONT_MEAS_OVRD_MASK)

#define XCVR_RX_DIG_RSSI_GLOBAL_CTRL_NB_CONT_MEAS_OVRD_EN_MASK (0x80U)
#define XCVR_RX_DIG_RSSI_GLOBAL_CTRL_NB_CONT_MEAS_OVRD_EN_SHIFT (7U)
/*! NB_CONT_MEAS_OVRD_EN - NB RSSI One-time Measure Override Enable
 */
#define XCVR_RX_DIG_RSSI_GLOBAL_CTRL_NB_CONT_MEAS_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_GLOBAL_CTRL_NB_CONT_MEAS_OVRD_EN_SHIFT)) & XCVR_RX_DIG_RSSI_GLOBAL_CTRL_NB_CONT_MEAS_OVRD_EN_MASK)

#define XCVR_RX_DIG_RSSI_GLOBAL_CTRL_NB_SNR_LQI_ENABLE_MASK (0x100U)
#define XCVR_RX_DIG_RSSI_GLOBAL_CTRL_NB_SNR_LQI_ENABLE_SHIFT (8U)
/*! NB_SNR_LQI_ENABLE - NB RSSI SNR LQI Enable
 *  0b0..NB-RSSI SNR/LQI calculation is disabled
 *  0b1..NB-RSSI SNR/LQI calculation is enabled
 */
#define XCVR_RX_DIG_RSSI_GLOBAL_CTRL_NB_SNR_LQI_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_GLOBAL_CTRL_NB_SNR_LQI_ENABLE_SHIFT)) & XCVR_RX_DIG_RSSI_GLOBAL_CTRL_NB_SNR_LQI_ENABLE_MASK)

#define XCVR_RX_DIG_RSSI_GLOBAL_CTRL_CCA1_ED_FROM_NB_MASK (0x200U)
#define XCVR_RX_DIG_RSSI_GLOBAL_CTRL_CCA1_ED_FROM_NB_SHIFT (9U)
/*! CCA1_ED_FROM_NB - CCA1/ED Result Selection
 *  0b0..WB-RSSI's CCA1/ED result is selected
 *  0b1..NB-RSSI's CCA1/ED result is selected
 */
#define XCVR_RX_DIG_RSSI_GLOBAL_CTRL_CCA1_ED_FROM_NB(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_GLOBAL_CTRL_CCA1_ED_FROM_NB_SHIFT)) & XCVR_RX_DIG_RSSI_GLOBAL_CTRL_CCA1_ED_FROM_NB_MASK)

#define XCVR_RX_DIG_RSSI_GLOBAL_CTRL_NB_RSSI_EN_MASK (0x8000U)
#define XCVR_RX_DIG_RSSI_GLOBAL_CTRL_NB_RSSI_EN_SHIFT (15U)
/*! NB_RSSI_EN - NB RSSI Enable
 *  0b0..NB-RSSI is disabled
 *  0b1..NB-RSSI is enabled
 */
#define XCVR_RX_DIG_RSSI_GLOBAL_CTRL_NB_RSSI_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_GLOBAL_CTRL_NB_RSSI_EN_SHIFT)) & XCVR_RX_DIG_RSSI_GLOBAL_CTRL_NB_RSSI_EN_MASK)

#define XCVR_RX_DIG_RSSI_GLOBAL_CTRL_WB_RSSI_INPUT_SEL_MASK (0x10000U)
#define XCVR_RX_DIG_RSSI_GLOBAL_CTRL_WB_RSSI_INPUT_SEL_SHIFT (16U)
/*! WB_RSSI_INPUT_SEL - WB RSSI Input Select
 *  0b0..DCOC output I/Q
 *  0b1..CIC output I/Q
 */
#define XCVR_RX_DIG_RSSI_GLOBAL_CTRL_WB_RSSI_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_GLOBAL_CTRL_WB_RSSI_INPUT_SEL_SHIFT)) & XCVR_RX_DIG_RSSI_GLOBAL_CTRL_WB_RSSI_INPUT_SEL_MASK)

#define XCVR_RX_DIG_RSSI_GLOBAL_CTRL_WB_CCA1_ED_EN_MASK (0x100000U)
#define XCVR_RX_DIG_RSSI_GLOBAL_CTRL_WB_CCA1_ED_EN_SHIFT (20U)
/*! WB_CCA1_ED_EN - WB RSSI CCA1 ED Enable
 *  0b0..WB-RSSI CCA1/ED disabled
 *  0b1..WB-RSSI CCA1/ED enabled
 */
#define XCVR_RX_DIG_RSSI_GLOBAL_CTRL_WB_CCA1_ED_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_GLOBAL_CTRL_WB_CCA1_ED_EN_SHIFT)) & XCVR_RX_DIG_RSSI_GLOBAL_CTRL_WB_CCA1_ED_EN_MASK)

#define XCVR_RX_DIG_RSSI_GLOBAL_CTRL_WB_CONT_MEAS_OVRD_MASK (0x200000U)
#define XCVR_RX_DIG_RSSI_GLOBAL_CTRL_WB_CONT_MEAS_OVRD_SHIFT (21U)
/*! WB_CONT_MEAS_OVRD - WB RSSI Continuous Measurment Override Value
 */
#define XCVR_RX_DIG_RSSI_GLOBAL_CTRL_WB_CONT_MEAS_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_GLOBAL_CTRL_WB_CONT_MEAS_OVRD_SHIFT)) & XCVR_RX_DIG_RSSI_GLOBAL_CTRL_WB_CONT_MEAS_OVRD_MASK)

#define XCVR_RX_DIG_RSSI_GLOBAL_CTRL_WB_CONT_MEAS_OVRD_EN_MASK (0x400000U)
#define XCVR_RX_DIG_RSSI_GLOBAL_CTRL_WB_CONT_MEAS_OVRD_EN_SHIFT (22U)
/*! WB_CONT_MEAS_OVRD_EN - WB RSSI Continuous Measurment Override Enable
 */
#define XCVR_RX_DIG_RSSI_GLOBAL_CTRL_WB_CONT_MEAS_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_GLOBAL_CTRL_WB_CONT_MEAS_OVRD_EN_SHIFT)) & XCVR_RX_DIG_RSSI_GLOBAL_CTRL_WB_CONT_MEAS_OVRD_EN_MASK)

#define XCVR_RX_DIG_RSSI_GLOBAL_CTRL_WB_RSSI_EN_MASK (0x80000000U)
#define XCVR_RX_DIG_RSSI_GLOBAL_CTRL_WB_RSSI_EN_SHIFT (31U)
/*! WB_RSSI_EN - WB RSSI Enable
 *  0b0..WB-RSSI is disabled
 *  0b1..WB-RSSI is enabled
 */
#define XCVR_RX_DIG_RSSI_GLOBAL_CTRL_WB_RSSI_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_GLOBAL_CTRL_WB_RSSI_EN_SHIFT)) & XCVR_RX_DIG_RSSI_GLOBAL_CTRL_WB_RSSI_EN_MASK)
/*! @} */

/*! @name WB_RSSI_CTRL - Wide-Band RSSI Control */
/*! @{ */

#define XCVR_RX_DIG_WB_RSSI_CTRL_RSSI_N_WINDOW_WB_MASK (0x7U)
#define XCVR_RX_DIG_WB_RSSI_CTRL_RSSI_N_WINDOW_WB_SHIFT (0U)
/*! RSSI_N_WINDOW_WB - WB RSSI N Window Averager Factor
 */
#define XCVR_RX_DIG_WB_RSSI_CTRL_RSSI_N_WINDOW_WB(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_WB_RSSI_CTRL_RSSI_N_WINDOW_WB_SHIFT)) & XCVR_RX_DIG_WB_RSSI_CTRL_RSSI_N_WINDOW_WB_MASK)

#define XCVR_RX_DIG_WB_RSSI_CTRL_RSSI_M_WINDOW_WB_MASK (0x70U)
#define XCVR_RX_DIG_WB_RSSI_CTRL_RSSI_M_WINDOW_WB_SHIFT (4U)
/*! RSSI_M_WINDOW_WB - WB RSSI M Window Averager Factor
 */
#define XCVR_RX_DIG_WB_RSSI_CTRL_RSSI_M_WINDOW_WB(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_WB_RSSI_CTRL_RSSI_M_WINDOW_WB_SHIFT)) & XCVR_RX_DIG_WB_RSSI_CTRL_RSSI_M_WINDOW_WB_MASK)

#define XCVR_RX_DIG_WB_RSSI_CTRL_RSSI_F_WINDOW_WB_MASK (0x700U)
#define XCVR_RX_DIG_WB_RSSI_CTRL_RSSI_F_WINDOW_WB_SHIFT (8U)
/*! RSSI_F_WINDOW_WB - WB RSSI F Window Averager Factor
 */
#define XCVR_RX_DIG_WB_RSSI_CTRL_RSSI_F_WINDOW_WB(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_WB_RSSI_CTRL_RSSI_F_WINDOW_WB_SHIFT)) & XCVR_RX_DIG_WB_RSSI_CTRL_RSSI_F_WINDOW_WB_MASK)

#define XCVR_RX_DIG_WB_RSSI_CTRL_RSSI_DB_EN_WB_MASK (0x1000U)
#define XCVR_RX_DIG_WB_RSSI_CTRL_RSSI_DB_EN_WB_SHIFT (12U)
/*! RSSI_DB_EN_WB - WB RSSI dB Calculate Enable
 */
#define XCVR_RX_DIG_WB_RSSI_CTRL_RSSI_DB_EN_WB(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_WB_RSSI_CTRL_RSSI_DB_EN_WB_SHIFT)) & XCVR_RX_DIG_WB_RSSI_CTRL_RSSI_DB_EN_WB_MASK)

#define XCVR_RX_DIG_WB_RSSI_CTRL_KEEP_RSSI_RESULT_WB_MASK (0x2000U)
#define XCVR_RX_DIG_WB_RSSI_CTRL_KEEP_RSSI_RESULT_WB_SHIFT (13U)
#define XCVR_RX_DIG_WB_RSSI_CTRL_KEEP_RSSI_RESULT_WB(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_WB_RSSI_CTRL_KEEP_RSSI_RESULT_WB_SHIFT)) & XCVR_RX_DIG_WB_RSSI_CTRL_KEEP_RSSI_RESULT_WB_MASK)

#define XCVR_RX_DIG_WB_RSSI_CTRL_RSSI_N_WINDOW_WB_DRS_MASK (0x70000U)
#define XCVR_RX_DIG_WB_RSSI_CTRL_RSSI_N_WINDOW_WB_DRS_SHIFT (16U)
#define XCVR_RX_DIG_WB_RSSI_CTRL_RSSI_N_WINDOW_WB_DRS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_WB_RSSI_CTRL_RSSI_N_WINDOW_WB_DRS_SHIFT)) & XCVR_RX_DIG_WB_RSSI_CTRL_RSSI_N_WINDOW_WB_DRS_MASK)

#define XCVR_RX_DIG_WB_RSSI_CTRL_RSSI_F_WINDOW_WB_DRS_MASK (0x700000U)
#define XCVR_RX_DIG_WB_RSSI_CTRL_RSSI_F_WINDOW_WB_DRS_SHIFT (20U)
#define XCVR_RX_DIG_WB_RSSI_CTRL_RSSI_F_WINDOW_WB_DRS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_WB_RSSI_CTRL_RSSI_F_WINDOW_WB_DRS_SHIFT)) & XCVR_RX_DIG_WB_RSSI_CTRL_RSSI_F_WINDOW_WB_DRS_MASK)

#define XCVR_RX_DIG_WB_RSSI_CTRL_RSSI_ADJ_WB_MASK (0xFF000000U)
#define XCVR_RX_DIG_WB_RSSI_CTRL_RSSI_ADJ_WB_SHIFT (24U)
/*! RSSI_ADJ_WB - WB RSSI Adjust Value
 */
#define XCVR_RX_DIG_WB_RSSI_CTRL_RSSI_ADJ_WB(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_WB_RSSI_CTRL_RSSI_ADJ_WB_SHIFT)) & XCVR_RX_DIG_WB_RSSI_CTRL_RSSI_ADJ_WB_MASK)
/*! @} */

/*! @name WB_RSSI_RES0 - Wide-Band RSSI Result 0 */
/*! @{ */

#define XCVR_RX_DIG_WB_RSSI_RES0_RSSI_WB_MASK    (0x1FFU)
#define XCVR_RX_DIG_WB_RSSI_RES0_RSSI_WB_SHIFT   (0U)
/*! RSSI_WB - WB RSSI Result
 */
#define XCVR_RX_DIG_WB_RSSI_RES0_RSSI_WB(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_WB_RSSI_RES0_RSSI_WB_SHIFT)) & XCVR_RX_DIG_WB_RSSI_RES0_RSSI_WB_MASK)

#define XCVR_RX_DIG_WB_RSSI_RES0_RSSI_RDY_WB_MASK (0x8000U)
#define XCVR_RX_DIG_WB_RSSI_RES0_RSSI_RDY_WB_SHIFT (15U)
#define XCVR_RX_DIG_WB_RSSI_RES0_RSSI_RDY_WB(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_WB_RSSI_RES0_RSSI_RDY_WB_SHIFT)) & XCVR_RX_DIG_WB_RSSI_RES0_RSSI_RDY_WB_MASK)

#define XCVR_RX_DIG_WB_RSSI_RES0_RSSI_RAW_WB_MASK (0xFF0000U)
#define XCVR_RX_DIG_WB_RSSI_RES0_RSSI_RAW_WB_SHIFT (16U)
/*! RSSI_RAW_WB - WB Raw RSSI Result
 */
#define XCVR_RX_DIG_WB_RSSI_RES0_RSSI_RAW_WB(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_WB_RSSI_RES0_RSSI_RAW_WB_SHIFT)) & XCVR_RX_DIG_WB_RSSI_RES0_RSSI_RAW_WB_MASK)
/*! @} */

/*! @name WB_RSSI_RES1 - Wide-Band RSSI Result 1 */
/*! @{ */

#define XCVR_RX_DIG_WB_RSSI_RES1_ED_WB_MASK      (0xFFU)
#define XCVR_RX_DIG_WB_RSSI_RES1_ED_WB_SHIFT     (0U)
/*! ED_WB - WB RSSI ED Result
 */
#define XCVR_RX_DIG_WB_RSSI_RES1_ED_WB(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_WB_RSSI_RES1_ED_WB_SHIFT)) & XCVR_RX_DIG_WB_RSSI_RES1_ED_WB_MASK)

#define XCVR_RX_DIG_WB_RSSI_RES1_CCA1_STATE_WB_MASK (0x40000000U)
#define XCVR_RX_DIG_WB_RSSI_RES1_CCA1_STATE_WB_SHIFT (30U)
/*! CCA1_STATE_WB - WB RSSI CCA1 State
 */
#define XCVR_RX_DIG_WB_RSSI_RES1_CCA1_STATE_WB(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_WB_RSSI_RES1_CCA1_STATE_WB_SHIFT)) & XCVR_RX_DIG_WB_RSSI_RES1_CCA1_STATE_WB_MASK)

#define XCVR_RX_DIG_WB_RSSI_RES1_MEAS_COMPLETE_WB_MASK (0x80000000U)
#define XCVR_RX_DIG_WB_RSSI_RES1_MEAS_COMPLETE_WB_SHIFT (31U)
/*! MEAS_COMPLETE_WB - WB RSSI Measure Complete
 */
#define XCVR_RX_DIG_WB_RSSI_RES1_MEAS_COMPLETE_WB(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_WB_RSSI_RES1_MEAS_COMPLETE_WB_SHIFT)) & XCVR_RX_DIG_WB_RSSI_RES1_MEAS_COMPLETE_WB_MASK)
/*! @} */

/*! @name WB_RSSI_DFT - Wide-Band RSSI DFT Result */
/*! @{ */

#define XCVR_RX_DIG_WB_RSSI_DFT_SLOW_MAG_MASK    (0x3FFU)
#define XCVR_RX_DIG_WB_RSSI_DFT_SLOW_MAG_SHIFT   (0U)
/*! SLOW_MAG - WB RSSI Slow Magnitude Value
 */
#define XCVR_RX_DIG_WB_RSSI_DFT_SLOW_MAG(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_WB_RSSI_DFT_SLOW_MAG_SHIFT)) & XCVR_RX_DIG_WB_RSSI_DFT_SLOW_MAG_MASK)

#define XCVR_RX_DIG_WB_RSSI_DFT_FAST_MAG_MASK    (0xFFC00U)
#define XCVR_RX_DIG_WB_RSSI_DFT_FAST_MAG_SHIFT   (10U)
/*! FAST_MAG - WB RSSI Fast Magnitude Value
 */
#define XCVR_RX_DIG_WB_RSSI_DFT_FAST_MAG(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_WB_RSSI_DFT_FAST_MAG_SHIFT)) & XCVR_RX_DIG_WB_RSSI_DFT_FAST_MAG_MASK)
/*! @} */

/*! @name NB_RSSI_CTRL0 - Narrow-Band RSSI Control 0 */
/*! @{ */

#define XCVR_RX_DIG_NB_RSSI_CTRL0_RSSI_N_WINDOW_NB_MASK (0xFU)
#define XCVR_RX_DIG_NB_RSSI_CTRL0_RSSI_N_WINDOW_NB_SHIFT (0U)
/*! RSSI_N_WINDOW_NB - NB RSSI N Window Averager Factor
 */
#define XCVR_RX_DIG_NB_RSSI_CTRL0_RSSI_N_WINDOW_NB(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_NB_RSSI_CTRL0_RSSI_N_WINDOW_NB_SHIFT)) & XCVR_RX_DIG_NB_RSSI_CTRL0_RSSI_N_WINDOW_NB_MASK)

#define XCVR_RX_DIG_NB_RSSI_CTRL0_RSSI_M_WINDOW_NB_MASK (0xF0U)
#define XCVR_RX_DIG_NB_RSSI_CTRL0_RSSI_M_WINDOW_NB_SHIFT (4U)
/*! RSSI_M_WINDOW_NB - NB RSSI M Window Averager Factor
 */
#define XCVR_RX_DIG_NB_RSSI_CTRL0_RSSI_M_WINDOW_NB(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_NB_RSSI_CTRL0_RSSI_M_WINDOW_NB_SHIFT)) & XCVR_RX_DIG_NB_RSSI_CTRL0_RSSI_M_WINDOW_NB_MASK)

#define XCVR_RX_DIG_NB_RSSI_CTRL0_RSSI_IIR_WAIT_NB_MASK (0x700U)
#define XCVR_RX_DIG_NB_RSSI_CTRL0_RSSI_IIR_WAIT_NB_SHIFT (8U)
/*! RSSI_IIR_WAIT_NB - NB RSSI IIR Filter Initial Wait Time
 */
#define XCVR_RX_DIG_NB_RSSI_CTRL0_RSSI_IIR_WAIT_NB(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_NB_RSSI_CTRL0_RSSI_IIR_WAIT_NB_SHIFT)) & XCVR_RX_DIG_NB_RSSI_CTRL0_RSSI_IIR_WAIT_NB_MASK)

#define XCVR_RX_DIG_NB_RSSI_CTRL0_RSSI_IIR_WT_NB_MASK (0x7000U)
#define XCVR_RX_DIG_NB_RSSI_CTRL0_RSSI_IIR_WT_NB_SHIFT (12U)
/*! RSSI_IIR_WT_NB - NB RSSI IIR Filter Factor
 */
#define XCVR_RX_DIG_NB_RSSI_CTRL0_RSSI_IIR_WT_NB(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_NB_RSSI_CTRL0_RSSI_IIR_WT_NB_SHIFT)) & XCVR_RX_DIG_NB_RSSI_CTRL0_RSSI_IIR_WT_NB_MASK)

#define XCVR_RX_DIG_NB_RSSI_CTRL0_SNR_ADJ_NB_MASK (0x3F0000U)
#define XCVR_RX_DIG_NB_RSSI_CTRL0_SNR_ADJ_NB_SHIFT (16U)
/*! SNR_ADJ_NB - NB RSSI SNR Adjust Value
 */
#define XCVR_RX_DIG_NB_RSSI_CTRL0_SNR_ADJ_NB(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_NB_RSSI_CTRL0_SNR_ADJ_NB_SHIFT)) & XCVR_RX_DIG_NB_RSSI_CTRL0_SNR_ADJ_NB_MASK)

#define XCVR_RX_DIG_NB_RSSI_CTRL0_KEEP_RSSI_RESULT_NB_MASK (0x400000U)
#define XCVR_RX_DIG_NB_RSSI_CTRL0_KEEP_RSSI_RESULT_NB_SHIFT (22U)
#define XCVR_RX_DIG_NB_RSSI_CTRL0_KEEP_RSSI_RESULT_NB(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_NB_RSSI_CTRL0_KEEP_RSSI_RESULT_NB_SHIFT)) & XCVR_RX_DIG_NB_RSSI_CTRL0_KEEP_RSSI_RESULT_NB_MASK)

#define XCVR_RX_DIG_NB_RSSI_CTRL0_RSSI_ADJ_NB_MASK (0xFF000000U)
#define XCVR_RX_DIG_NB_RSSI_CTRL0_RSSI_ADJ_NB_SHIFT (24U)
/*! RSSI_ADJ_NB - NB RSSI Adjust Value
 */
#define XCVR_RX_DIG_NB_RSSI_CTRL0_RSSI_ADJ_NB(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_NB_RSSI_CTRL0_RSSI_ADJ_NB_SHIFT)) & XCVR_RX_DIG_NB_RSSI_CTRL0_RSSI_ADJ_NB_MASK)
/*! @} */

/*! @name NB_RSSI_CTRL1 - Narrow-Band RSSI Control 1 */
/*! @{ */

#define XCVR_RX_DIG_NB_RSSI_CTRL1_LQI_RSSI_WEIGHT_MASK (0x70000U)
#define XCVR_RX_DIG_NB_RSSI_CTRL1_LQI_RSSI_WEIGHT_SHIFT (16U)
/*! LQI_RSSI_WEIGHT - RSSI Weight For LQI Calulation
 */
#define XCVR_RX_DIG_NB_RSSI_CTRL1_LQI_RSSI_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_NB_RSSI_CTRL1_LQI_RSSI_WEIGHT_SHIFT)) & XCVR_RX_DIG_NB_RSSI_CTRL1_LQI_RSSI_WEIGHT_MASK)

#define XCVR_RX_DIG_NB_RSSI_CTRL1_LQI_SNR_WEIGHT_MASK (0xF00000U)
#define XCVR_RX_DIG_NB_RSSI_CTRL1_LQI_SNR_WEIGHT_SHIFT (20U)
/*! LQI_SNR_WEIGHT - SNR Weight For LQI Calulation
 */
#define XCVR_RX_DIG_NB_RSSI_CTRL1_LQI_SNR_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_NB_RSSI_CTRL1_LQI_SNR_WEIGHT_SHIFT)) & XCVR_RX_DIG_NB_RSSI_CTRL1_LQI_SNR_WEIGHT_MASK)

#define XCVR_RX_DIG_NB_RSSI_CTRL1_LQI_RSSI_SENS_ADJ_MASK (0xF000000U)
#define XCVR_RX_DIG_NB_RSSI_CTRL1_LQI_RSSI_SENS_ADJ_SHIFT (24U)
/*! LQI_RSSI_SENS_ADJ - LQI Sensitivity Adjust Value
 */
#define XCVR_RX_DIG_NB_RSSI_CTRL1_LQI_RSSI_SENS_ADJ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_NB_RSSI_CTRL1_LQI_RSSI_SENS_ADJ_SHIFT)) & XCVR_RX_DIG_NB_RSSI_CTRL1_LQI_RSSI_SENS_ADJ_MASK)

#define XCVR_RX_DIG_NB_RSSI_CTRL1_LQI_BIAS_MASK  (0xF0000000U)
#define XCVR_RX_DIG_NB_RSSI_CTRL1_LQI_BIAS_SHIFT (28U)
/*! LQI_BIAS - LQI Bias Value
 */
#define XCVR_RX_DIG_NB_RSSI_CTRL1_LQI_BIAS(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_NB_RSSI_CTRL1_LQI_BIAS_SHIFT)) & XCVR_RX_DIG_NB_RSSI_CTRL1_LQI_BIAS_MASK)
/*! @} */

/*! @name NB_RSSI_RES0 - Narrow-Band RSSI Result 0 */
/*! @{ */

#define XCVR_RX_DIG_NB_RSSI_RES0_RSSI_NB_MASK    (0x1FFU)
#define XCVR_RX_DIG_NB_RSSI_RES0_RSSI_NB_SHIFT   (0U)
/*! RSSI_NB - NB RSSI Result
 */
#define XCVR_RX_DIG_NB_RSSI_RES0_RSSI_NB(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_NB_RSSI_RES0_RSSI_NB_SHIFT)) & XCVR_RX_DIG_NB_RSSI_RES0_RSSI_NB_MASK)

#define XCVR_RX_DIG_NB_RSSI_RES0_RSSI_RDY_NB_MASK (0x8000U)
#define XCVR_RX_DIG_NB_RSSI_RES0_RSSI_RDY_NB_SHIFT (15U)
#define XCVR_RX_DIG_NB_RSSI_RES0_RSSI_RDY_NB(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_NB_RSSI_RES0_RSSI_RDY_NB_SHIFT)) & XCVR_RX_DIG_NB_RSSI_RES0_RSSI_RDY_NB_MASK)

#define XCVR_RX_DIG_NB_RSSI_RES0_RSSI_RAW_NB_MASK (0xFF0000U)
#define XCVR_RX_DIG_NB_RSSI_RES0_RSSI_RAW_NB_SHIFT (16U)
/*! RSSI_RAW_NB - Raw NB RSSI Result
 */
#define XCVR_RX_DIG_NB_RSSI_RES0_RSSI_RAW_NB(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_NB_RSSI_RES0_RSSI_RAW_NB_SHIFT)) & XCVR_RX_DIG_NB_RSSI_RES0_RSSI_RAW_NB_MASK)

#define XCVR_RX_DIG_NB_RSSI_RES0_NOISE_RSSI_RAW_NB_MASK (0xFF000000U)
#define XCVR_RX_DIG_NB_RSSI_RES0_NOISE_RSSI_RAW_NB_SHIFT (24U)
/*! NOISE_RSSI_RAW_NB - Raw Noise Result
 */
#define XCVR_RX_DIG_NB_RSSI_RES0_NOISE_RSSI_RAW_NB(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_NB_RSSI_RES0_NOISE_RSSI_RAW_NB_SHIFT)) & XCVR_RX_DIG_NB_RSSI_RES0_NOISE_RSSI_RAW_NB_MASK)
/*! @} */

/*! @name NB_RSSI_RES1 - Narrow-Band RSSI Result 1 */
/*! @{ */

#define XCVR_RX_DIG_NB_RSSI_RES1_ED_NB_MASK      (0xFFU)
#define XCVR_RX_DIG_NB_RSSI_RES1_ED_NB_SHIFT     (0U)
/*! ED_NB - NB RSSI ED Result
 */
#define XCVR_RX_DIG_NB_RSSI_RES1_ED_NB(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_NB_RSSI_RES1_ED_NB_SHIFT)) & XCVR_RX_DIG_NB_RSSI_RES1_ED_NB_MASK)

#define XCVR_RX_DIG_NB_RSSI_RES1_LQI_NB_MASK     (0xFF00U)
#define XCVR_RX_DIG_NB_RSSI_RES1_LQI_NB_SHIFT    (8U)
/*! LQI_NB - NB RSSI LQI Result
 */
#define XCVR_RX_DIG_NB_RSSI_RES1_LQI_NB(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_NB_RSSI_RES1_LQI_NB_SHIFT)) & XCVR_RX_DIG_NB_RSSI_RES1_LQI_NB_MASK)

#define XCVR_RX_DIG_NB_RSSI_RES1_SNR_NB_MASK     (0x3F0000U)
#define XCVR_RX_DIG_NB_RSSI_RES1_SNR_NB_SHIFT    (16U)
/*! SNR_NB - NB RSSI SNR Result
 */
#define XCVR_RX_DIG_NB_RSSI_RES1_SNR_NB(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_NB_RSSI_RES1_SNR_NB_SHIFT)) & XCVR_RX_DIG_NB_RSSI_RES1_SNR_NB_MASK)

#define XCVR_RX_DIG_NB_RSSI_RES1_CCA1_STATE_NB_MASK (0x40000000U)
#define XCVR_RX_DIG_NB_RSSI_RES1_CCA1_STATE_NB_SHIFT (30U)
/*! CCA1_STATE_NB - NB RSSI CCA1 State
 */
#define XCVR_RX_DIG_NB_RSSI_RES1_CCA1_STATE_NB(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_NB_RSSI_RES1_CCA1_STATE_NB_SHIFT)) & XCVR_RX_DIG_NB_RSSI_RES1_CCA1_STATE_NB_MASK)

#define XCVR_RX_DIG_NB_RSSI_RES1_MEAS_COMPLETE_NB_MASK (0x80000000U)
#define XCVR_RX_DIG_NB_RSSI_RES1_MEAS_COMPLETE_NB_SHIFT (31U)
/*! MEAS_COMPLETE_NB - NB RSSI Measure Complete
 */
#define XCVR_RX_DIG_NB_RSSI_RES1_MEAS_COMPLETE_NB(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_NB_RSSI_RES1_MEAS_COMPLETE_NB_SHIFT)) & XCVR_RX_DIG_NB_RSSI_RES1_MEAS_COMPLETE_NB_MASK)
/*! @} */

/*! @name NB_RSSI_DFT - Narrow-Band RSSI DFT Result */
/*! @{ */

#define XCVR_RX_DIG_NB_RSSI_DFT_AVG_NOISE_MAG_NB_MASK (0xFFFU)
#define XCVR_RX_DIG_NB_RSSI_DFT_AVG_NOISE_MAG_NB_SHIFT (0U)
/*! AVG_NOISE_MAG_NB - NB RSSI Averaged Noise Magnitude Value
 */
#define XCVR_RX_DIG_NB_RSSI_DFT_AVG_NOISE_MAG_NB(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_NB_RSSI_DFT_AVG_NOISE_MAG_NB_SHIFT)) & XCVR_RX_DIG_NB_RSSI_DFT_AVG_NOISE_MAG_NB_MASK)

#define XCVR_RX_DIG_NB_RSSI_DFT_AVG_MAG_NB_MASK  (0xFFF0000U)
#define XCVR_RX_DIG_NB_RSSI_DFT_AVG_MAG_NB_SHIFT (16U)
/*! AVG_MAG_NB - NB RSSI Averaged Magnitude Value
 */
#define XCVR_RX_DIG_NB_RSSI_DFT_AVG_MAG_NB(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_NB_RSSI_DFT_AVG_MAG_NB_SHIFT)) & XCVR_RX_DIG_NB_RSSI_DFT_AVG_MAG_NB_MASK)
/*! @} */

/*! @name AGC_CTRL - AGC Control */
/*! @{ */

#define XCVR_RX_DIG_AGC_CTRL_AGC_UNHOLD_FEAT_EN_MASK (0x3U)
#define XCVR_RX_DIG_AGC_CTRL_AGC_UNHOLD_FEAT_EN_SHIFT (0U)
/*! AGC_UNHOLD_FEAT_EN - AGC Unhold Enalbe
 */
#define XCVR_RX_DIG_AGC_CTRL_AGC_UNHOLD_FEAT_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_AGC_UNHOLD_FEAT_EN_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_AGC_UNHOLD_FEAT_EN_MASK)

#define XCVR_RX_DIG_AGC_CTRL_AGC_HOLD_EN_MASK    (0xCU)
#define XCVR_RX_DIG_AGC_CTRL_AGC_HOLD_EN_SHIFT   (2U)
/*! AGC_HOLD_EN - AGC Hold Mode Enable
 *  0b00..Disable AGC hold mode
 *  0b01..AGC hold when preamble found
 *  0b10..AGC hold when AGC hold timeout matched
 *  0b11..AGC hold when preamble found or hold timeout matched
 */
#define XCVR_RX_DIG_AGC_CTRL_AGC_HOLD_EN(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_AGC_HOLD_EN_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_AGC_HOLD_EN_MASK)

#define XCVR_RX_DIG_AGC_CTRL_AGC_DELTA_SLOW_STEP_MASK (0x70U)
#define XCVR_RX_DIG_AGC_CTRL_AGC_DELTA_SLOW_STEP_SHIFT (4U)
/*! AGC_DELTA_SLOW_STEP - AGC Delta Slow Mode Gain Step Up Value
 */
#define XCVR_RX_DIG_AGC_CTRL_AGC_DELTA_SLOW_STEP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_AGC_DELTA_SLOW_STEP_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_AGC_DELTA_SLOW_STEP_MASK)

#define XCVR_RX_DIG_AGC_CTRL_AGC_DELTA_SLOW_EN_MASK (0x80U)
#define XCVR_RX_DIG_AGC_CTRL_AGC_DELTA_SLOW_EN_SHIFT (7U)
/*! AGC_DELTA_SLOW_EN - AGC Delta Slow Magitude Mode Enable
 *  0b0..Disable AGC delta slow magnitude mode
 *  0b1..Enable AGC delta slow magnitude mode
 */
#define XCVR_RX_DIG_AGC_CTRL_AGC_DELTA_SLOW_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_AGC_DELTA_SLOW_EN_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_AGC_DELTA_SLOW_EN_MASK)

#define XCVR_RX_DIG_AGC_CTRL_AGC_SLOW_EN_MASK    (0x100U)
#define XCVR_RX_DIG_AGC_CTRL_AGC_SLOW_EN_SHIFT   (8U)
/*! AGC_SLOW_EN - AGC Slow Magitude Mode Enable
 *  0b0..Disable AGC slow magnitude mode
 *  0b1..Enable AGC slow magnitude mode
 */
#define XCVR_RX_DIG_AGC_CTRL_AGC_SLOW_EN(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_AGC_SLOW_EN_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_AGC_SLOW_EN_MASK)

#define XCVR_RX_DIG_AGC_CTRL_AGC_FAST_STEP_UP_EN_MASK (0x200U)
#define XCVR_RX_DIG_AGC_CTRL_AGC_FAST_STEP_UP_EN_SHIFT (9U)
/*! AGC_FAST_STEP_UP_EN - AGC Fast Magitude Mode Step Up Enable
 *  0b0..Fast magnitude mode can only make AGC gain index step down
 *  0b1..Fast magnitude mode can make AGC gain index step down or step up
 */
#define XCVR_RX_DIG_AGC_CTRL_AGC_FAST_STEP_UP_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_AGC_FAST_STEP_UP_EN_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_AGC_FAST_STEP_UP_EN_MASK)

#define XCVR_RX_DIG_AGC_CTRL_AGC_FAST_EN_MASK    (0x400U)
#define XCVR_RX_DIG_AGC_CTRL_AGC_FAST_EN_SHIFT   (10U)
/*! AGC_FAST_EN - AGC Fast Magitude Mode Enable
 *  0b0..Disable fast magnitude mode
 *  0b1..Enable fast magnitude mode
 */
#define XCVR_RX_DIG_AGC_CTRL_AGC_FAST_EN(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_AGC_FAST_EN_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_AGC_FAST_EN_MASK)

#define XCVR_RX_DIG_AGC_CTRL_AGC_WBD_STEP2_SZ_MASK (0x3800U)
#define XCVR_RX_DIG_AGC_CTRL_AGC_WBD_STEP2_SZ_SHIFT (11U)
/*! AGC_WBD_STEP2_SZ - AGC WBD Step2 Gain Decreas Value
 */
#define XCVR_RX_DIG_AGC_CTRL_AGC_WBD_STEP2_SZ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_AGC_WBD_STEP2_SZ_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_AGC_WBD_STEP2_SZ_MASK)

#define XCVR_RX_DIG_AGC_CTRL_AGC_WBD_STEP1_SZ_MASK (0x1C000U)
#define XCVR_RX_DIG_AGC_CTRL_AGC_WBD_STEP1_SZ_SHIFT (14U)
/*! AGC_WBD_STEP1_SZ - AGC WBD Step1 Gain Decreas Value
 */
#define XCVR_RX_DIG_AGC_CTRL_AGC_WBD_STEP1_SZ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_AGC_WBD_STEP1_SZ_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_AGC_WBD_STEP1_SZ_MASK)

#define XCVR_RX_DIG_AGC_CTRL_AGC_WBD_THR2_MASK   (0x1E0000U)
#define XCVR_RX_DIG_AGC_CTRL_AGC_WBD_THR2_SHIFT  (17U)
/*! AGC_WBD_THR2 - AGC WBD Step2 threshold
 */
#define XCVR_RX_DIG_AGC_CTRL_AGC_WBD_THR2(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_AGC_WBD_THR2_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_AGC_WBD_THR2_MASK)

#define XCVR_RX_DIG_AGC_CTRL_AGC_WBD_THR1_MASK   (0x1E00000U)
#define XCVR_RX_DIG_AGC_CTRL_AGC_WBD_THR1_SHIFT  (21U)
/*! AGC_WBD_THR1 - AGC WBD Step1 threshold
 *  0b0000..49.31
 *  0b0001..67.56
 *  0b0010..90.98
 *  0b0011..117.42
 *  0b0100..150.66
 *  0b0101..180.98
 *  0b0110..211.87
 *  0b0111..245.2
 *  0b1000..288.31
 *  0b1001..336.02
 *  0b1010..394.34
 *  0b1011..462.71
 *  0b1100..548.04
 *  0b1101..650.13
 *  0b1110..771.65
 *  0b1111..918.12
 */
#define XCVR_RX_DIG_AGC_CTRL_AGC_WBD_THR1(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_AGC_WBD_THR1_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_AGC_WBD_THR1_MASK)

#define XCVR_RX_DIG_AGC_CTRL_AGC_WBD_STEP2_DUAL_CLIP_EN_MASK (0x2000000U)
#define XCVR_RX_DIG_AGC_CTRL_AGC_WBD_STEP2_DUAL_CLIP_EN_SHIFT (25U)
/*! AGC_WBD_STEP2_DUAL_CLIP_EN - AGC WBD Step2 Dual Clip Enable
 */
#define XCVR_RX_DIG_AGC_CTRL_AGC_WBD_STEP2_DUAL_CLIP_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_AGC_WBD_STEP2_DUAL_CLIP_EN_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_AGC_WBD_STEP2_DUAL_CLIP_EN_MASK)

#define XCVR_RX_DIG_AGC_CTRL_AGC_WBD_STEP1_DUAL_CLIP_EN_MASK (0x4000000U)
#define XCVR_RX_DIG_AGC_CTRL_AGC_WBD_STEP1_DUAL_CLIP_EN_SHIFT (26U)
/*! AGC_WBD_STEP1_DUAL_CLIP_EN - AGC WBD Step1 Dual Clip Enable
 */
#define XCVR_RX_DIG_AGC_CTRL_AGC_WBD_STEP1_DUAL_CLIP_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_AGC_WBD_STEP1_DUAL_CLIP_EN_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_AGC_WBD_STEP1_DUAL_CLIP_EN_MASK)

#define XCVR_RX_DIG_AGC_CTRL_AGC_WBD_GAIN_LIMIT_EN_MASK (0x8000000U)
#define XCVR_RX_DIG_AGC_CTRL_AGC_WBD_GAIN_LIMIT_EN_SHIFT (27U)
/*! AGC_WBD_GAIN_LIMIT_EN - AGC WBD Gain Limit
 */
#define XCVR_RX_DIG_AGC_CTRL_AGC_WBD_GAIN_LIMIT_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_AGC_WBD_GAIN_LIMIT_EN_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_AGC_WBD_GAIN_LIMIT_EN_MASK)

#define XCVR_RX_DIG_AGC_CTRL_AGC_WBD_AUTO_DIS_CFG_MASK (0x30000000U)
#define XCVR_RX_DIG_AGC_CTRL_AGC_WBD_AUTO_DIS_CFG_SHIFT (28U)
/*! AGC_WBD_AUTO_DIS_CFG - AGC WBD Auto Disable
 */
#define XCVR_RX_DIG_AGC_CTRL_AGC_WBD_AUTO_DIS_CFG(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_AGC_WBD_AUTO_DIS_CFG_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_AGC_WBD_AUTO_DIS_CFG_MASK)

#define XCVR_RX_DIG_AGC_CTRL_AGC_WBD_EN_MASK     (0xC0000000U)
#define XCVR_RX_DIG_AGC_CTRL_AGC_WBD_EN_SHIFT    (30U)
/*! AGC_WBD_EN - AGC WBD Enable
 *  0b00..AGC WBD is disabled
 *  0b01..AGC WBD step1 is enabled
 *  0b10..AGC WBD step1 and step2 is enabled
 *  0b11..Reserved
 */
#define XCVR_RX_DIG_AGC_CTRL_AGC_WBD_EN(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_AGC_WBD_EN_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_AGC_WBD_EN_MASK)
/*! @} */

/*! @name AGC_CTRL_STAT - AGC Control Status */
/*! @{ */

#define XCVR_RX_DIG_AGC_CTRL_STAT_AGC_MAX_IDX_MASK (0x3U)
#define XCVR_RX_DIG_AGC_CTRL_STAT_AGC_MAX_IDX_SHIFT (0U)
/*! AGC_MAX_IDX - AGC Max Gain Index
 */
#define XCVR_RX_DIG_AGC_CTRL_STAT_AGC_MAX_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_STAT_AGC_MAX_IDX_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_STAT_AGC_MAX_IDX_MASK)

#define XCVR_RX_DIG_AGC_CTRL_STAT_AGC_INIT_IDX_MASK (0x3CU)
#define XCVR_RX_DIG_AGC_CTRL_STAT_AGC_INIT_IDX_SHIFT (2U)
/*! AGC_INIT_IDX - AGC Initial Gain Index
 */
#define XCVR_RX_DIG_AGC_CTRL_STAT_AGC_INIT_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_STAT_AGC_INIT_IDX_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_STAT_AGC_INIT_IDX_MASK)

#define XCVR_RX_DIG_AGC_CTRL_STAT_AGC_PHY_HOLD_TRIG_SEL_MASK (0x40U)
#define XCVR_RX_DIG_AGC_CTRL_STAT_AGC_PHY_HOLD_TRIG_SEL_SHIFT (6U)
/*! AGC_PHY_HOLD_TRIG_SEL - AGC PHY Hold Trigger Select
 *  0b0..PHY_AGC_HOLD_TRIG is select as AGC hold trig.
 *  0b1..PHY_AGC_FREEZE_TRIG is select as AGC hold trig.
 */
#define XCVR_RX_DIG_AGC_CTRL_STAT_AGC_PHY_HOLD_TRIG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_STAT_AGC_PHY_HOLD_TRIG_SEL_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_STAT_AGC_PHY_HOLD_TRIG_SEL_MASK)

#define XCVR_RX_DIG_AGC_CTRL_STAT_AGC_PHY_FREEZE_TRIG_SEL_MASK (0x80U)
#define XCVR_RX_DIG_AGC_CTRL_STAT_AGC_PHY_FREEZE_TRIG_SEL_SHIFT (7U)
/*! AGC_PHY_FREEZE_TRIG_SEL - AGC PHY Freeze Trigger Select
 *  0b0..PHY_AGC_FREEZE_TRIG is select as AGC freeze trig.
 *  0b1..PHY_AGC_HOLD_TRIG is select as AGC freeze trig.
 */
#define XCVR_RX_DIG_AGC_CTRL_STAT_AGC_PHY_FREEZE_TRIG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_STAT_AGC_PHY_FREEZE_TRIG_SEL_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_STAT_AGC_PHY_FREEZE_TRIG_SEL_MASK)

#define XCVR_RX_DIG_AGC_CTRL_STAT_AGC_CALC_MAG_IN_FRZ_MASK (0x100U)
#define XCVR_RX_DIG_AGC_CTRL_STAT_AGC_CALC_MAG_IN_FRZ_SHIFT (8U)
/*! AGC_CALC_MAG_IN_FRZ - AGC Calucate Magnitude In Freeze Mode
 */
#define XCVR_RX_DIG_AGC_CTRL_STAT_AGC_CALC_MAG_IN_FRZ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_STAT_AGC_CALC_MAG_IN_FRZ_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_STAT_AGC_CALC_MAG_IN_FRZ_MASK)

#define XCVR_RX_DIG_AGC_CTRL_STAT_AGC_UNFREEZE_FEAT_EN_MASK (0x200U)
#define XCVR_RX_DIG_AGC_CTRL_STAT_AGC_UNFREEZE_FEAT_EN_SHIFT (9U)
/*! AGC_UNFREEZE_FEAT_EN - AGC Unfreeze Feature Enable
 *  0b0..AGC unfreeze function is disabled
 *  0b1..AGC will exit FREEZE mode when AGC_UNFREEZE_TMEOUT matched and aa_found not be asserted
 */
#define XCVR_RX_DIG_AGC_CTRL_STAT_AGC_UNFREEZE_FEAT_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_STAT_AGC_UNFREEZE_FEAT_EN_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_STAT_AGC_UNFREEZE_FEAT_EN_MASK)

#define XCVR_RX_DIG_AGC_CTRL_STAT_AGC_FREEZE_EN_MASK (0xC00U)
#define XCVR_RX_DIG_AGC_CTRL_STAT_AGC_FREEZE_EN_SHIFT (10U)
/*! AGC_FREEZE_EN - AGC Freeze Mode Enable
 *  0b00..Disable AGC freeze mode
 *  0b01..AGC freeze when AA/SFD matched
 *  0b10..AGC freeze when AGC freeze timeout matched
 *  0b11..AGC freeze when AA/SFD matched or freeze timeout matched
 */
#define XCVR_RX_DIG_AGC_CTRL_STAT_AGC_FREEZE_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_STAT_AGC_FREEZE_EN_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_STAT_AGC_FREEZE_EN_MASK)

#define XCVR_RX_DIG_AGC_CTRL_STAT_AGC_GAIN_IDX_STORE_MASK (0x3000U)
#define XCVR_RX_DIG_AGC_CTRL_STAT_AGC_GAIN_IDX_STORE_SHIFT (12U)
/*! AGC_GAIN_IDX_STORE
 *  0b00..AGC gain index stroe function is disabled
 *  0b01..Store AGC gain index when AGC enter into HOLD mode
 *  0b10..Store AGC gain index when AGC enter into FREEZE mode
 *  0b11..Store AGC gain index when AA matched
 */
#define XCVR_RX_DIG_AGC_CTRL_STAT_AGC_GAIN_IDX_STORE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_STAT_AGC_GAIN_IDX_STORE_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_STAT_AGC_GAIN_IDX_STORE_MASK)

#define XCVR_RX_DIG_AGC_CTRL_STAT_AGC_SOFT_RST_GAIN_SEL_MASK (0x4000U)
#define XCVR_RX_DIG_AGC_CTRL_STAT_AGC_SOFT_RST_GAIN_SEL_SHIFT (14U)
/*! AGC_SOFT_RST_GAIN_SEL - PHY AGC Soft Reset Gain Sel
 *  0b0..AGC keep current gain index when PHY AGC soft reset trigged,
 *  0b1..AGC return to AGC_INIT_IDX when PHY AGC soft reset trigged,
 */
#define XCVR_RX_DIG_AGC_CTRL_STAT_AGC_SOFT_RST_GAIN_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_STAT_AGC_SOFT_RST_GAIN_SEL_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_STAT_AGC_SOFT_RST_GAIN_SEL_MASK)

#define XCVR_RX_DIG_AGC_CTRL_STAT_AGC_SOFT_RST_SRC_SEL_MASK (0x18000U)
#define XCVR_RX_DIG_AGC_CTRL_STAT_AGC_SOFT_RST_SRC_SEL_SHIFT (15U)
/*! AGC_SOFT_RST_SRC_SEL - PHY AGC Soft Reset Sel
 *  0b00..Disable PHY AGC soft reset function
 *  0b01..Use posedge phy_soft_rst to reset AGC
 *  0b10..Use negedge phy_soft_rst to reset AGC
 *  0b11..Use negedge phy_agc_freeze_trig to reset AGC
 */
#define XCVR_RX_DIG_AGC_CTRL_STAT_AGC_SOFT_RST_SRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_STAT_AGC_SOFT_RST_SRC_SEL_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_STAT_AGC_SOFT_RST_SRC_SEL_MASK)

#define XCVR_RX_DIG_AGC_CTRL_STAT_AGC_PREV_GAIN_IDX_MASK (0x1E0000U)
#define XCVR_RX_DIG_AGC_CTRL_STAT_AGC_PREV_GAIN_IDX_SHIFT (17U)
/*! AGC_PREV_GAIN_IDX - AGC Previous Gain Index
 */
#define XCVR_RX_DIG_AGC_CTRL_STAT_AGC_PREV_GAIN_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_STAT_AGC_PREV_GAIN_IDX_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_STAT_AGC_PREV_GAIN_IDX_MASK)

#define XCVR_RX_DIG_AGC_CTRL_STAT_AGC_GAIN_IDX_MASK (0x1E00000U)
#define XCVR_RX_DIG_AGC_CTRL_STAT_AGC_GAIN_IDX_SHIFT (21U)
/*! AGC_GAIN_IDX - AGC Gain Index
 */
#define XCVR_RX_DIG_AGC_CTRL_STAT_AGC_GAIN_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_STAT_AGC_GAIN_IDX_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_STAT_AGC_GAIN_IDX_MASK)

#define XCVR_RX_DIG_AGC_CTRL_STAT_AGC_GAIN_CHANGE_MASK (0x2000000U)
#define XCVR_RX_DIG_AGC_CTRL_STAT_AGC_GAIN_CHANGE_SHIFT (25U)
/*! AGC_GAIN_CHANGE - AGC Gain Change
 */
#define XCVR_RX_DIG_AGC_CTRL_STAT_AGC_GAIN_CHANGE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_STAT_AGC_GAIN_CHANGE_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_STAT_AGC_GAIN_CHANGE_MASK)

#define XCVR_RX_DIG_AGC_CTRL_STAT_AGC_GAIN_CHANGE_STATUS_MASK (0x1C000000U)
#define XCVR_RX_DIG_AGC_CTRL_STAT_AGC_GAIN_CHANGE_STATUS_SHIFT (26U)
/*! AGC_GAIN_CHANGE_STATUS - AGC Gain Change Status
 *  0b000..No gain change
 *  0b001..Gain decreased by WBD step1
 *  0b010..Gain decreased by WBD step2
 *  0b011..Gain decreased by fast mode
 *  0b100..Gain increased by fast mode
 *  0b101..Gain decreased by slow mode
 *  0b110..Gain increased by slow mode
 *  0b111..Gain increased by delta slow mode
 */
#define XCVR_RX_DIG_AGC_CTRL_STAT_AGC_GAIN_CHANGE_STATUS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_STAT_AGC_GAIN_CHANGE_STATUS_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_STAT_AGC_GAIN_CHANGE_STATUS_MASK)

#define XCVR_RX_DIG_AGC_CTRL_STAT_AGC_STATUS_MASK (0xE0000000U)
#define XCVR_RX_DIG_AGC_CTRL_STAT_AGC_STATUS_SHIFT (29U)
/*! AGC_STATUS - AGC FSM Status
 *  0b000..AGC_IDLE
 *  0b001..AGC_WB_ONLY
 *  0b010..AGC_WB_MAG
 *  0b011..AGC_WB_DEBOUNCE
 *  0b100..AGC_MAG_ONLY
 *  0b101..AGC_HOLD
 *  0b110..AGC_FREEZE
 *  0b111..AGC_WAIT_GAIN_SETTLE
 */
#define XCVR_RX_DIG_AGC_CTRL_STAT_AGC_STATUS(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_STAT_AGC_STATUS_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_STAT_AGC_STATUS_MASK)
/*! @} */

/*! @name AGC_TIMING0 - AGC Timing Control 0 */
/*! @{ */

#define XCVR_RX_DIG_AGC_TIMING0_AGC_DELTA_SLOW_WAIT_MASK (0x3U)
#define XCVR_RX_DIG_AGC_TIMING0_AGC_DELTA_SLOW_WAIT_SHIFT (0U)
/*! AGC_DELTA_SLOW_WAIT - AGC Delta Slow Mode Timing
 */
#define XCVR_RX_DIG_AGC_TIMING0_AGC_DELTA_SLOW_WAIT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_TIMING0_AGC_DELTA_SLOW_WAIT_SHIFT)) & XCVR_RX_DIG_AGC_TIMING0_AGC_DELTA_SLOW_WAIT_MASK)

#define XCVR_RX_DIG_AGC_TIMING0_AGC_WBD_STEP2_TIMEOUT_MASK (0x7CU)
#define XCVR_RX_DIG_AGC_TIMING0_AGC_WBD_STEP2_TIMEOUT_SHIFT (2U)
/*! AGC_WBD_STEP2_TIMEOUT - AGC WBD Step2 Timeout
 */
#define XCVR_RX_DIG_AGC_TIMING0_AGC_WBD_STEP2_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_TIMING0_AGC_WBD_STEP2_TIMEOUT_SHIFT)) & XCVR_RX_DIG_AGC_TIMING0_AGC_WBD_STEP2_TIMEOUT_MASK)

#define XCVR_RX_DIG_AGC_TIMING0_AGC_WBD_STEP1_TIMEOUT_MASK (0x380U)
#define XCVR_RX_DIG_AGC_TIMING0_AGC_WBD_STEP1_TIMEOUT_SHIFT (7U)
/*! AGC_WBD_STEP1_TIMEOUT - AGC WBD Timeout
 */
#define XCVR_RX_DIG_AGC_TIMING0_AGC_WBD_STEP1_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_TIMING0_AGC_WBD_STEP1_TIMEOUT_SHIFT)) & XCVR_RX_DIG_AGC_TIMING0_AGC_WBD_STEP1_TIMEOUT_MASK)

#define XCVR_RX_DIG_AGC_TIMING0_AGC_GAIN_STEP_WAIT_MASK (0xFC00U)
#define XCVR_RX_DIG_AGC_TIMING0_AGC_GAIN_STEP_WAIT_SHIFT (10U)
/*! AGC_GAIN_STEP_WAIT - AGC Gain Change Wait Time
 */
#define XCVR_RX_DIG_AGC_TIMING0_AGC_GAIN_STEP_WAIT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_TIMING0_AGC_GAIN_STEP_WAIT_SHIFT)) & XCVR_RX_DIG_AGC_TIMING0_AGC_GAIN_STEP_WAIT_MASK)

#define XCVR_RX_DIG_AGC_TIMING0_AGC_MAG_INIT_WAIT_MASK (0x7F0000U)
#define XCVR_RX_DIG_AGC_TIMING0_AGC_MAG_INIT_WAIT_SHIFT (16U)
/*! AGC_MAG_INIT_WAIT - AGC Magnitude Mode Initial Wait Time
 */
#define XCVR_RX_DIG_AGC_TIMING0_AGC_MAG_INIT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_TIMING0_AGC_MAG_INIT_WAIT_SHIFT)) & XCVR_RX_DIG_AGC_TIMING0_AGC_MAG_INIT_WAIT_MASK)

#define XCVR_RX_DIG_AGC_TIMING0_AGC_WBD_INIT_WAIT_MASK (0x7F000000U)
#define XCVR_RX_DIG_AGC_TIMING0_AGC_WBD_INIT_WAIT_SHIFT (24U)
/*! AGC_WBD_INIT_WAIT - AGC WBD Mode Initial Wait Time
 */
#define XCVR_RX_DIG_AGC_TIMING0_AGC_WBD_INIT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_TIMING0_AGC_WBD_INIT_WAIT_SHIFT)) & XCVR_RX_DIG_AGC_TIMING0_AGC_WBD_INIT_WAIT_MASK)
/*! @} */

/*! @name AGC_TIMING1 - AGC Timing Control 1 */
/*! @{ */

#define XCVR_RX_DIG_AGC_TIMING1_AGC_FREEZE_TIMEOUT_MASK (0x7FU)
#define XCVR_RX_DIG_AGC_TIMING1_AGC_FREEZE_TIMEOUT_SHIFT (0U)
/*! AGC_FREEZE_TIMEOUT - AGC FREEZE Mode Wait Time
 */
#define XCVR_RX_DIG_AGC_TIMING1_AGC_FREEZE_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_TIMING1_AGC_FREEZE_TIMEOUT_SHIFT)) & XCVR_RX_DIG_AGC_TIMING1_AGC_FREEZE_TIMEOUT_MASK)

#define XCVR_RX_DIG_AGC_TIMING1_AGC_HOLD_TIMEOUT_MASK (0x3F80U)
#define XCVR_RX_DIG_AGC_TIMING1_AGC_HOLD_TIMEOUT_SHIFT (7U)
/*! AGC_HOLD_TIMEOUT - AGC HOLD Mode Wait Time
 */
#define XCVR_RX_DIG_AGC_TIMING1_AGC_HOLD_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_TIMING1_AGC_HOLD_TIMEOUT_SHIFT)) & XCVR_RX_DIG_AGC_TIMING1_AGC_HOLD_TIMEOUT_MASK)

#define XCVR_RX_DIG_AGC_TIMING1_AGC_WBD_STEP2_DUAL_CLIP_WAIT_MASK (0x1C000U)
#define XCVR_RX_DIG_AGC_TIMING1_AGC_WBD_STEP2_DUAL_CLIP_WAIT_SHIFT (14U)
/*! AGC_WBD_STEP2_DUAL_CLIP_WAIT - AGC WBD step2 Debounce Wait Time
 */
#define XCVR_RX_DIG_AGC_TIMING1_AGC_WBD_STEP2_DUAL_CLIP_WAIT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_TIMING1_AGC_WBD_STEP2_DUAL_CLIP_WAIT_SHIFT)) & XCVR_RX_DIG_AGC_TIMING1_AGC_WBD_STEP2_DUAL_CLIP_WAIT_MASK)

#define XCVR_RX_DIG_AGC_TIMING1_AGC_WBD_STEP1_DUAL_CLIP_WAIT_MASK (0xE0000U)
#define XCVR_RX_DIG_AGC_TIMING1_AGC_WBD_STEP1_DUAL_CLIP_WAIT_SHIFT (17U)
/*! AGC_WBD_STEP1_DUAL_CLIP_WAIT - AGC WBD step1 Debounce Wait Time
 */
#define XCVR_RX_DIG_AGC_TIMING1_AGC_WBD_STEP1_DUAL_CLIP_WAIT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_TIMING1_AGC_WBD_STEP1_DUAL_CLIP_WAIT_SHIFT)) & XCVR_RX_DIG_AGC_TIMING1_AGC_WBD_STEP1_DUAL_CLIP_WAIT_MASK)

#define XCVR_RX_DIG_AGC_TIMING1_AGC_WBD_STEP2_WAIT_MASK (0x3F00000U)
#define XCVR_RX_DIG_AGC_TIMING1_AGC_WBD_STEP2_WAIT_SHIFT (20U)
/*! AGC_WBD_STEP2_WAIT - AGC Gain Change Wait For WBD step2
 */
#define XCVR_RX_DIG_AGC_TIMING1_AGC_WBD_STEP2_WAIT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_TIMING1_AGC_WBD_STEP2_WAIT_SHIFT)) & XCVR_RX_DIG_AGC_TIMING1_AGC_WBD_STEP2_WAIT_MASK)

#define XCVR_RX_DIG_AGC_TIMING1_AGC_WBD_DUAL_CLIP_TIMEOUT_MASK (0x3C000000U)
#define XCVR_RX_DIG_AGC_TIMING1_AGC_WBD_DUAL_CLIP_TIMEOUT_SHIFT (26U)
#define XCVR_RX_DIG_AGC_TIMING1_AGC_WBD_DUAL_CLIP_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_TIMING1_AGC_WBD_DUAL_CLIP_TIMEOUT_SHIFT)) & XCVR_RX_DIG_AGC_TIMING1_AGC_WBD_DUAL_CLIP_TIMEOUT_MASK)
/*! @} */

/*! @name AGC_TIMING2 - AGC Timing Control 2 */
/*! @{ */

#define XCVR_RX_DIG_AGC_TIMING2_AGC_UNFREEZE_FEAT_TIMEOUT_MASK (0x7FFU)
#define XCVR_RX_DIG_AGC_TIMING2_AGC_UNFREEZE_FEAT_TIMEOUT_SHIFT (0U)
/*! AGC_UNFREEZE_FEAT_TIMEOUT - AGC Unfreeze Feature Timeout
 */
#define XCVR_RX_DIG_AGC_TIMING2_AGC_UNFREEZE_FEAT_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_TIMING2_AGC_UNFREEZE_FEAT_TIMEOUT_SHIFT)) & XCVR_RX_DIG_AGC_TIMING2_AGC_UNFREEZE_FEAT_TIMEOUT_MASK)

#define XCVR_RX_DIG_AGC_TIMING2_AGC_UNHOLD_FEAT_TIMEOUT_MASK (0x1FF800U)
#define XCVR_RX_DIG_AGC_TIMING2_AGC_UNHOLD_FEAT_TIMEOUT_SHIFT (11U)
/*! AGC_UNHOLD_FEAT_TIMEOUT - AGC Unhold Feature Timeout
 */
#define XCVR_RX_DIG_AGC_TIMING2_AGC_UNHOLD_FEAT_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_TIMING2_AGC_UNHOLD_FEAT_TIMEOUT_SHIFT)) & XCVR_RX_DIG_AGC_TIMING2_AGC_UNHOLD_FEAT_TIMEOUT_MASK)

#define XCVR_RX_DIG_AGC_TIMING2_AGC_UNHOLD_GAIN_CHG_MASK (0x20000000U)
#define XCVR_RX_DIG_AGC_TIMING2_AGC_UNHOLD_GAIN_CHG_SHIFT (29U)
/*! AGC_UNHOLD_GAIN_CHG - AGC Gain Index Change When UNHOLD
 */
#define XCVR_RX_DIG_AGC_TIMING2_AGC_UNHOLD_GAIN_CHG(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_TIMING2_AGC_UNHOLD_GAIN_CHG_SHIFT)) & XCVR_RX_DIG_AGC_TIMING2_AGC_UNHOLD_GAIN_CHG_MASK)

#define XCVR_RX_DIG_AGC_TIMING2_AGC_UNHOLD_MAG_CNT_MASK (0x40000000U)
#define XCVR_RX_DIG_AGC_TIMING2_AGC_UNHOLD_MAG_CNT_SHIFT (30U)
/*! AGC_UNHOLD_MAG_CNT - AGC Unhold Magnitude Count Selection
 */
#define XCVR_RX_DIG_AGC_TIMING2_AGC_UNHOLD_MAG_CNT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_TIMING2_AGC_UNHOLD_MAG_CNT_SHIFT)) & XCVR_RX_DIG_AGC_TIMING2_AGC_UNHOLD_MAG_CNT_MASK)

#define XCVR_RX_DIG_AGC_TIMING2_AGC_UNHOLD_MAG_SRC_MASK (0x80000000U)
#define XCVR_RX_DIG_AGC_TIMING2_AGC_UNHOLD_MAG_SRC_SHIFT (31U)
/*! AGC_UNHOLD_MAG_SRC - AGC Magnitude Unhold Feature Source Selection
 *  0b0..fast_mag
 *  0b1..slow_mag
 */
#define XCVR_RX_DIG_AGC_TIMING2_AGC_UNHOLD_MAG_SRC(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_TIMING2_AGC_UNHOLD_MAG_SRC_SHIFT)) & XCVR_RX_DIG_AGC_TIMING2_AGC_UNHOLD_MAG_SRC_MASK)
/*! @} */

/*! @name AGC_TIMING0_DRS - AGC Timing Control 0 DRS */
/*! @{ */

#define XCVR_RX_DIG_AGC_TIMING0_DRS_AGC_GAIN_STEP_WAIT_MASK (0xFC00U)
#define XCVR_RX_DIG_AGC_TIMING0_DRS_AGC_GAIN_STEP_WAIT_SHIFT (10U)
/*! AGC_GAIN_STEP_WAIT - AGC Gain Change Wait Time
 */
#define XCVR_RX_DIG_AGC_TIMING0_DRS_AGC_GAIN_STEP_WAIT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_TIMING0_DRS_AGC_GAIN_STEP_WAIT_SHIFT)) & XCVR_RX_DIG_AGC_TIMING0_DRS_AGC_GAIN_STEP_WAIT_MASK)

#define XCVR_RX_DIG_AGC_TIMING0_DRS_AGC_WBD_EN_DRS_MASK (0xC0000000U)
#define XCVR_RX_DIG_AGC_TIMING0_DRS_AGC_WBD_EN_DRS_SHIFT (30U)
#define XCVR_RX_DIG_AGC_TIMING0_DRS_AGC_WBD_EN_DRS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_TIMING0_DRS_AGC_WBD_EN_DRS_SHIFT)) & XCVR_RX_DIG_AGC_TIMING0_DRS_AGC_WBD_EN_DRS_MASK)
/*! @} */

/*! @name AGC_TIMING1_DRS - AGC Timing Control 1 DRS */
/*! @{ */

#define XCVR_RX_DIG_AGC_TIMING1_DRS_AGC_FREEZE_TIMEOUT_MASK (0x7FU)
#define XCVR_RX_DIG_AGC_TIMING1_DRS_AGC_FREEZE_TIMEOUT_SHIFT (0U)
/*! AGC_FREEZE_TIMEOUT - AGC FREEZE Mode Wait Time
 */
#define XCVR_RX_DIG_AGC_TIMING1_DRS_AGC_FREEZE_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_TIMING1_DRS_AGC_FREEZE_TIMEOUT_SHIFT)) & XCVR_RX_DIG_AGC_TIMING1_DRS_AGC_FREEZE_TIMEOUT_MASK)

#define XCVR_RX_DIG_AGC_TIMING1_DRS_AGC_HOLD_TIMEOUT_MASK (0x3F80U)
#define XCVR_RX_DIG_AGC_TIMING1_DRS_AGC_HOLD_TIMEOUT_SHIFT (7U)
/*! AGC_HOLD_TIMEOUT - AGC HOLD Mode Wait Time
 */
#define XCVR_RX_DIG_AGC_TIMING1_DRS_AGC_HOLD_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_TIMING1_DRS_AGC_HOLD_TIMEOUT_SHIFT)) & XCVR_RX_DIG_AGC_TIMING1_DRS_AGC_HOLD_TIMEOUT_MASK)
/*! @} */

/*! @name AGC_TIMING2_DRS - AGC Timing Control 2 DRS */
/*! @{ */

#define XCVR_RX_DIG_AGC_TIMING2_DRS_AGC_UNFREEZE_FEAT_TIMEOUT_MASK (0x7FFU)
#define XCVR_RX_DIG_AGC_TIMING2_DRS_AGC_UNFREEZE_FEAT_TIMEOUT_SHIFT (0U)
/*! AGC_UNFREEZE_FEAT_TIMEOUT - AGC Unfreeze Feature Timeout
 */
#define XCVR_RX_DIG_AGC_TIMING2_DRS_AGC_UNFREEZE_FEAT_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_TIMING2_DRS_AGC_UNFREEZE_FEAT_TIMEOUT_SHIFT)) & XCVR_RX_DIG_AGC_TIMING2_DRS_AGC_UNFREEZE_FEAT_TIMEOUT_MASK)

#define XCVR_RX_DIG_AGC_TIMING2_DRS_AGC_UNHOLD_FEAT_TIMEOUT_MASK (0x1FF800U)
#define XCVR_RX_DIG_AGC_TIMING2_DRS_AGC_UNHOLD_FEAT_TIMEOUT_SHIFT (11U)
/*! AGC_UNHOLD_FEAT_TIMEOUT - AGC Unhold Feature Timeout
 */
#define XCVR_RX_DIG_AGC_TIMING2_DRS_AGC_UNHOLD_FEAT_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_TIMING2_DRS_AGC_UNHOLD_FEAT_TIMEOUT_SHIFT)) & XCVR_RX_DIG_AGC_TIMING2_DRS_AGC_UNHOLD_FEAT_TIMEOUT_MASK)
/*! @} */

/*! @name AGC_IDX11_GAIN_CFG - AGC IDX11 Gain Config */
/*! @{ */

#define XCVR_RX_DIG_AGC_IDX11_GAIN_CFG_CBPF_GAIN_11_MASK (0x1U)
#define XCVR_RX_DIG_AGC_IDX11_GAIN_CFG_CBPF_GAIN_11_SHIFT (0U)
/*! CBPF_GAIN_11 - CBPF_GAIN_11
 *  0b0..-6 dB
 *  0b1..0 dB
 */
#define XCVR_RX_DIG_AGC_IDX11_GAIN_CFG_CBPF_GAIN_11(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX11_GAIN_CFG_CBPF_GAIN_11_SHIFT)) & XCVR_RX_DIG_AGC_IDX11_GAIN_CFG_CBPF_GAIN_11_MASK)

#define XCVR_RX_DIG_AGC_IDX11_GAIN_CFG_LNA_RTRIM_11_MASK (0xEU)
#define XCVR_RX_DIG_AGC_IDX11_GAIN_CFG_LNA_RTRIM_11_SHIFT (1U)
/*! LNA_RTRIM_11 - LNA_RTRIM_11
 */
#define XCVR_RX_DIG_AGC_IDX11_GAIN_CFG_LNA_RTRIM_11(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX11_GAIN_CFG_LNA_RTRIM_11_SHIFT)) & XCVR_RX_DIG_AGC_IDX11_GAIN_CFG_LNA_RTRIM_11_MASK)

#define XCVR_RX_DIG_AGC_IDX11_GAIN_CFG_LNA_ATTN_11_MASK (0x30U)
#define XCVR_RX_DIG_AGC_IDX11_GAIN_CFG_LNA_ATTN_11_SHIFT (4U)
/*! LNA_ATTN_11 - LNA_ATTN_11
 */
#define XCVR_RX_DIG_AGC_IDX11_GAIN_CFG_LNA_ATTN_11(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX11_GAIN_CFG_LNA_ATTN_11_SHIFT)) & XCVR_RX_DIG_AGC_IDX11_GAIN_CFG_LNA_ATTN_11_MASK)

#define XCVR_RX_DIG_AGC_IDX11_GAIN_CFG_LNA_HATTN_11_MASK (0x40U)
#define XCVR_RX_DIG_AGC_IDX11_GAIN_CFG_LNA_HATTN_11_SHIFT (6U)
/*! LNA_HATTN_11 - LNA_HATTN_11
 */
#define XCVR_RX_DIG_AGC_IDX11_GAIN_CFG_LNA_HATTN_11(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX11_GAIN_CFG_LNA_HATTN_11_SHIFT)) & XCVR_RX_DIG_AGC_IDX11_GAIN_CFG_LNA_HATTN_11_MASK)

#define XCVR_RX_DIG_AGC_IDX11_GAIN_CFG_LNA_LGAIN_11_MASK (0x180U)
#define XCVR_RX_DIG_AGC_IDX11_GAIN_CFG_LNA_LGAIN_11_SHIFT (7U)
/*! LNA_LGAIN_11 - LNA_LGAIN_11
 */
#define XCVR_RX_DIG_AGC_IDX11_GAIN_CFG_LNA_LGAIN_11(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX11_GAIN_CFG_LNA_LGAIN_11_SHIFT)) & XCVR_RX_DIG_AGC_IDX11_GAIN_CFG_LNA_LGAIN_11_MASK)

#define XCVR_RX_DIG_AGC_IDX11_GAIN_CFG_LNA_HGAIN_11_MASK (0x7E00U)
#define XCVR_RX_DIG_AGC_IDX11_GAIN_CFG_LNA_HGAIN_11_SHIFT (9U)
/*! LNA_HGAIN_11 - LNA_HGAIN_11
 */
#define XCVR_RX_DIG_AGC_IDX11_GAIN_CFG_LNA_HGAIN_11(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX11_GAIN_CFG_LNA_HGAIN_11_SHIFT)) & XCVR_RX_DIG_AGC_IDX11_GAIN_CFG_LNA_HGAIN_11_MASK)

#define XCVR_RX_DIG_AGC_IDX11_GAIN_CFG_ANT_EN_RLOAD_11_MASK (0x8000U)
#define XCVR_RX_DIG_AGC_IDX11_GAIN_CFG_ANT_EN_RLOAD_11_SHIFT (15U)
/*! ANT_EN_RLOAD_11 - ANT_EN_RLOAD_11
 */
#define XCVR_RX_DIG_AGC_IDX11_GAIN_CFG_ANT_EN_RLOAD_11(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX11_GAIN_CFG_ANT_EN_RLOAD_11_SHIFT)) & XCVR_RX_DIG_AGC_IDX11_GAIN_CFG_ANT_EN_RLOAD_11_MASK)

#define XCVR_RX_DIG_AGC_IDX11_GAIN_CFG_MAG_THR_HI_11_DRS_OFS_MASK (0xFF0000U)
#define XCVR_RX_DIG_AGC_IDX11_GAIN_CFG_MAG_THR_HI_11_DRS_OFS_SHIFT (16U)
/*! MAG_THR_HI_11_DRS_OFS - Mag Thresh High DRS for AGC Gain Index 11
 */
#define XCVR_RX_DIG_AGC_IDX11_GAIN_CFG_MAG_THR_HI_11_DRS_OFS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX11_GAIN_CFG_MAG_THR_HI_11_DRS_OFS_SHIFT)) & XCVR_RX_DIG_AGC_IDX11_GAIN_CFG_MAG_THR_HI_11_DRS_OFS_MASK)

#define XCVR_RX_DIG_AGC_IDX11_GAIN_CFG_MAG_THR_11_DRS_OFS_MASK (0xFF000000U)
#define XCVR_RX_DIG_AGC_IDX11_GAIN_CFG_MAG_THR_11_DRS_OFS_SHIFT (24U)
/*! MAG_THR_11_DRS_OFS - Mag Thresh High DRS for AGC Gain Index 11
 */
#define XCVR_RX_DIG_AGC_IDX11_GAIN_CFG_MAG_THR_11_DRS_OFS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX11_GAIN_CFG_MAG_THR_11_DRS_OFS_SHIFT)) & XCVR_RX_DIG_AGC_IDX11_GAIN_CFG_MAG_THR_11_DRS_OFS_MASK)
/*! @} */

/*! @name AGC_IDX10_GAIN_CFG - AGC IDX10 Gain Config */
/*! @{ */

#define XCVR_RX_DIG_AGC_IDX10_GAIN_CFG_CBPF_GAIN_10_MASK (0x1U)
#define XCVR_RX_DIG_AGC_IDX10_GAIN_CFG_CBPF_GAIN_10_SHIFT (0U)
/*! CBPF_GAIN_10 - CBPF_GAIN_10
 *  0b0..-6 dB
 *  0b1..0 dB
 */
#define XCVR_RX_DIG_AGC_IDX10_GAIN_CFG_CBPF_GAIN_10(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX10_GAIN_CFG_CBPF_GAIN_10_SHIFT)) & XCVR_RX_DIG_AGC_IDX10_GAIN_CFG_CBPF_GAIN_10_MASK)

#define XCVR_RX_DIG_AGC_IDX10_GAIN_CFG_LNA_RTRIM_10_MASK (0xEU)
#define XCVR_RX_DIG_AGC_IDX10_GAIN_CFG_LNA_RTRIM_10_SHIFT (1U)
/*! LNA_RTRIM_10 - LNA_RTRIM_10
 */
#define XCVR_RX_DIG_AGC_IDX10_GAIN_CFG_LNA_RTRIM_10(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX10_GAIN_CFG_LNA_RTRIM_10_SHIFT)) & XCVR_RX_DIG_AGC_IDX10_GAIN_CFG_LNA_RTRIM_10_MASK)

#define XCVR_RX_DIG_AGC_IDX10_GAIN_CFG_LNA_ATTN_10_MASK (0x30U)
#define XCVR_RX_DIG_AGC_IDX10_GAIN_CFG_LNA_ATTN_10_SHIFT (4U)
/*! LNA_ATTN_10 - LNA_ATTN_10
 */
#define XCVR_RX_DIG_AGC_IDX10_GAIN_CFG_LNA_ATTN_10(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX10_GAIN_CFG_LNA_ATTN_10_SHIFT)) & XCVR_RX_DIG_AGC_IDX10_GAIN_CFG_LNA_ATTN_10_MASK)

#define XCVR_RX_DIG_AGC_IDX10_GAIN_CFG_LNA_HATTN_10_MASK (0x40U)
#define XCVR_RX_DIG_AGC_IDX10_GAIN_CFG_LNA_HATTN_10_SHIFT (6U)
/*! LNA_HATTN_10 - LNA_HATTN_10
 */
#define XCVR_RX_DIG_AGC_IDX10_GAIN_CFG_LNA_HATTN_10(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX10_GAIN_CFG_LNA_HATTN_10_SHIFT)) & XCVR_RX_DIG_AGC_IDX10_GAIN_CFG_LNA_HATTN_10_MASK)

#define XCVR_RX_DIG_AGC_IDX10_GAIN_CFG_LNA_LGAIN_10_MASK (0x180U)
#define XCVR_RX_DIG_AGC_IDX10_GAIN_CFG_LNA_LGAIN_10_SHIFT (7U)
/*! LNA_LGAIN_10 - LNA_LGAIN_10
 */
#define XCVR_RX_DIG_AGC_IDX10_GAIN_CFG_LNA_LGAIN_10(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX10_GAIN_CFG_LNA_LGAIN_10_SHIFT)) & XCVR_RX_DIG_AGC_IDX10_GAIN_CFG_LNA_LGAIN_10_MASK)

#define XCVR_RX_DIG_AGC_IDX10_GAIN_CFG_LNA_HGAIN_10_MASK (0x7E00U)
#define XCVR_RX_DIG_AGC_IDX10_GAIN_CFG_LNA_HGAIN_10_SHIFT (9U)
/*! LNA_HGAIN_10 - LNA_HGAIN_10
 */
#define XCVR_RX_DIG_AGC_IDX10_GAIN_CFG_LNA_HGAIN_10(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX10_GAIN_CFG_LNA_HGAIN_10_SHIFT)) & XCVR_RX_DIG_AGC_IDX10_GAIN_CFG_LNA_HGAIN_10_MASK)

#define XCVR_RX_DIG_AGC_IDX10_GAIN_CFG_ANT_EN_RLOAD_10_MASK (0x8000U)
#define XCVR_RX_DIG_AGC_IDX10_GAIN_CFG_ANT_EN_RLOAD_10_SHIFT (15U)
/*! ANT_EN_RLOAD_10 - ANT_EN_RLOAD_10
 */
#define XCVR_RX_DIG_AGC_IDX10_GAIN_CFG_ANT_EN_RLOAD_10(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX10_GAIN_CFG_ANT_EN_RLOAD_10_SHIFT)) & XCVR_RX_DIG_AGC_IDX10_GAIN_CFG_ANT_EN_RLOAD_10_MASK)

#define XCVR_RX_DIG_AGC_IDX10_GAIN_CFG_MAG_THR_HI_10_DRS_OFS_MASK (0xFF0000U)
#define XCVR_RX_DIG_AGC_IDX10_GAIN_CFG_MAG_THR_HI_10_DRS_OFS_SHIFT (16U)
#define XCVR_RX_DIG_AGC_IDX10_GAIN_CFG_MAG_THR_HI_10_DRS_OFS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX10_GAIN_CFG_MAG_THR_HI_10_DRS_OFS_SHIFT)) & XCVR_RX_DIG_AGC_IDX10_GAIN_CFG_MAG_THR_HI_10_DRS_OFS_MASK)

#define XCVR_RX_DIG_AGC_IDX10_GAIN_CFG_MAG_THR_10_DRS_OFS_MASK (0xFF000000U)
#define XCVR_RX_DIG_AGC_IDX10_GAIN_CFG_MAG_THR_10_DRS_OFS_SHIFT (24U)
#define XCVR_RX_DIG_AGC_IDX10_GAIN_CFG_MAG_THR_10_DRS_OFS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX10_GAIN_CFG_MAG_THR_10_DRS_OFS_SHIFT)) & XCVR_RX_DIG_AGC_IDX10_GAIN_CFG_MAG_THR_10_DRS_OFS_MASK)
/*! @} */

/*! @name AGC_IDX9_GAIN_CFG - AGC IDX9 Gain Config */
/*! @{ */

#define XCVR_RX_DIG_AGC_IDX9_GAIN_CFG_CBPF_GAIN_9_MASK (0x1U)
#define XCVR_RX_DIG_AGC_IDX9_GAIN_CFG_CBPF_GAIN_9_SHIFT (0U)
/*! CBPF_GAIN_9 - CBPF_GAIN_9
 *  0b0..-6 dB
 *  0b1..0 dB
 */
#define XCVR_RX_DIG_AGC_IDX9_GAIN_CFG_CBPF_GAIN_9(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX9_GAIN_CFG_CBPF_GAIN_9_SHIFT)) & XCVR_RX_DIG_AGC_IDX9_GAIN_CFG_CBPF_GAIN_9_MASK)

#define XCVR_RX_DIG_AGC_IDX9_GAIN_CFG_LNA_RTRIM_9_MASK (0xEU)
#define XCVR_RX_DIG_AGC_IDX9_GAIN_CFG_LNA_RTRIM_9_SHIFT (1U)
/*! LNA_RTRIM_9 - LNA_RTRIM_9
 */
#define XCVR_RX_DIG_AGC_IDX9_GAIN_CFG_LNA_RTRIM_9(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX9_GAIN_CFG_LNA_RTRIM_9_SHIFT)) & XCVR_RX_DIG_AGC_IDX9_GAIN_CFG_LNA_RTRIM_9_MASK)

#define XCVR_RX_DIG_AGC_IDX9_GAIN_CFG_LNA_ATTN_9_MASK (0x30U)
#define XCVR_RX_DIG_AGC_IDX9_GAIN_CFG_LNA_ATTN_9_SHIFT (4U)
/*! LNA_ATTN_9 - LNA_ATTN_9
 */
#define XCVR_RX_DIG_AGC_IDX9_GAIN_CFG_LNA_ATTN_9(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX9_GAIN_CFG_LNA_ATTN_9_SHIFT)) & XCVR_RX_DIG_AGC_IDX9_GAIN_CFG_LNA_ATTN_9_MASK)

#define XCVR_RX_DIG_AGC_IDX9_GAIN_CFG_LNA_HATTN_9_MASK (0x40U)
#define XCVR_RX_DIG_AGC_IDX9_GAIN_CFG_LNA_HATTN_9_SHIFT (6U)
/*! LNA_HATTN_9 - LNA_HATTN_9
 */
#define XCVR_RX_DIG_AGC_IDX9_GAIN_CFG_LNA_HATTN_9(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX9_GAIN_CFG_LNA_HATTN_9_SHIFT)) & XCVR_RX_DIG_AGC_IDX9_GAIN_CFG_LNA_HATTN_9_MASK)

#define XCVR_RX_DIG_AGC_IDX9_GAIN_CFG_LNA_LGAIN_9_MASK (0x180U)
#define XCVR_RX_DIG_AGC_IDX9_GAIN_CFG_LNA_LGAIN_9_SHIFT (7U)
/*! LNA_LGAIN_9 - LNA_LGAIN_9
 */
#define XCVR_RX_DIG_AGC_IDX9_GAIN_CFG_LNA_LGAIN_9(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX9_GAIN_CFG_LNA_LGAIN_9_SHIFT)) & XCVR_RX_DIG_AGC_IDX9_GAIN_CFG_LNA_LGAIN_9_MASK)

#define XCVR_RX_DIG_AGC_IDX9_GAIN_CFG_LNA_HGAIN_9_MASK (0x7E00U)
#define XCVR_RX_DIG_AGC_IDX9_GAIN_CFG_LNA_HGAIN_9_SHIFT (9U)
/*! LNA_HGAIN_9 - LNA_HGAIN_9
 */
#define XCVR_RX_DIG_AGC_IDX9_GAIN_CFG_LNA_HGAIN_9(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX9_GAIN_CFG_LNA_HGAIN_9_SHIFT)) & XCVR_RX_DIG_AGC_IDX9_GAIN_CFG_LNA_HGAIN_9_MASK)

#define XCVR_RX_DIG_AGC_IDX9_GAIN_CFG_ANT_EN_RLOAD_9_MASK (0x8000U)
#define XCVR_RX_DIG_AGC_IDX9_GAIN_CFG_ANT_EN_RLOAD_9_SHIFT (15U)
/*! ANT_EN_RLOAD_9 - ANT_EN_RLOAD_9
 */
#define XCVR_RX_DIG_AGC_IDX9_GAIN_CFG_ANT_EN_RLOAD_9(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX9_GAIN_CFG_ANT_EN_RLOAD_9_SHIFT)) & XCVR_RX_DIG_AGC_IDX9_GAIN_CFG_ANT_EN_RLOAD_9_MASK)

#define XCVR_RX_DIG_AGC_IDX9_GAIN_CFG_MAG_THR_HI_9_DRS_OFS_MASK (0xFF0000U)
#define XCVR_RX_DIG_AGC_IDX9_GAIN_CFG_MAG_THR_HI_9_DRS_OFS_SHIFT (16U)
#define XCVR_RX_DIG_AGC_IDX9_GAIN_CFG_MAG_THR_HI_9_DRS_OFS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX9_GAIN_CFG_MAG_THR_HI_9_DRS_OFS_SHIFT)) & XCVR_RX_DIG_AGC_IDX9_GAIN_CFG_MAG_THR_HI_9_DRS_OFS_MASK)

#define XCVR_RX_DIG_AGC_IDX9_GAIN_CFG_MAG_THR_9_DRS_OFS_MASK (0xFF000000U)
#define XCVR_RX_DIG_AGC_IDX9_GAIN_CFG_MAG_THR_9_DRS_OFS_SHIFT (24U)
#define XCVR_RX_DIG_AGC_IDX9_GAIN_CFG_MAG_THR_9_DRS_OFS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX9_GAIN_CFG_MAG_THR_9_DRS_OFS_SHIFT)) & XCVR_RX_DIG_AGC_IDX9_GAIN_CFG_MAG_THR_9_DRS_OFS_MASK)
/*! @} */

/*! @name AGC_IDX8_GAIN_CFG - AGC IDX8 Gain Config */
/*! @{ */

#define XCVR_RX_DIG_AGC_IDX8_GAIN_CFG_CBPF_GAIN_8_MASK (0x1U)
#define XCVR_RX_DIG_AGC_IDX8_GAIN_CFG_CBPF_GAIN_8_SHIFT (0U)
/*! CBPF_GAIN_8 - CBPF_GAIN_8
 *  0b0..-6 dB
 *  0b1..0 dB
 */
#define XCVR_RX_DIG_AGC_IDX8_GAIN_CFG_CBPF_GAIN_8(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX8_GAIN_CFG_CBPF_GAIN_8_SHIFT)) & XCVR_RX_DIG_AGC_IDX8_GAIN_CFG_CBPF_GAIN_8_MASK)

#define XCVR_RX_DIG_AGC_IDX8_GAIN_CFG_LNA_RTRIM_8_MASK (0xEU)
#define XCVR_RX_DIG_AGC_IDX8_GAIN_CFG_LNA_RTRIM_8_SHIFT (1U)
/*! LNA_RTRIM_8 - LNA_RTRIM_8
 */
#define XCVR_RX_DIG_AGC_IDX8_GAIN_CFG_LNA_RTRIM_8(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX8_GAIN_CFG_LNA_RTRIM_8_SHIFT)) & XCVR_RX_DIG_AGC_IDX8_GAIN_CFG_LNA_RTRIM_8_MASK)

#define XCVR_RX_DIG_AGC_IDX8_GAIN_CFG_LNA_ATTN_8_MASK (0x30U)
#define XCVR_RX_DIG_AGC_IDX8_GAIN_CFG_LNA_ATTN_8_SHIFT (4U)
/*! LNA_ATTN_8 - LNA_ATTN_8
 */
#define XCVR_RX_DIG_AGC_IDX8_GAIN_CFG_LNA_ATTN_8(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX8_GAIN_CFG_LNA_ATTN_8_SHIFT)) & XCVR_RX_DIG_AGC_IDX8_GAIN_CFG_LNA_ATTN_8_MASK)

#define XCVR_RX_DIG_AGC_IDX8_GAIN_CFG_LNA_HATTN_8_MASK (0x40U)
#define XCVR_RX_DIG_AGC_IDX8_GAIN_CFG_LNA_HATTN_8_SHIFT (6U)
/*! LNA_HATTN_8 - LNA_HATTN_8
 */
#define XCVR_RX_DIG_AGC_IDX8_GAIN_CFG_LNA_HATTN_8(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX8_GAIN_CFG_LNA_HATTN_8_SHIFT)) & XCVR_RX_DIG_AGC_IDX8_GAIN_CFG_LNA_HATTN_8_MASK)

#define XCVR_RX_DIG_AGC_IDX8_GAIN_CFG_LNA_LGAIN_8_MASK (0x180U)
#define XCVR_RX_DIG_AGC_IDX8_GAIN_CFG_LNA_LGAIN_8_SHIFT (7U)
/*! LNA_LGAIN_8 - LNA_LGAIN_8
 */
#define XCVR_RX_DIG_AGC_IDX8_GAIN_CFG_LNA_LGAIN_8(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX8_GAIN_CFG_LNA_LGAIN_8_SHIFT)) & XCVR_RX_DIG_AGC_IDX8_GAIN_CFG_LNA_LGAIN_8_MASK)

#define XCVR_RX_DIG_AGC_IDX8_GAIN_CFG_LNA_HGAIN_8_MASK (0x7E00U)
#define XCVR_RX_DIG_AGC_IDX8_GAIN_CFG_LNA_HGAIN_8_SHIFT (9U)
/*! LNA_HGAIN_8 - LNA_HGAIN_8
 */
#define XCVR_RX_DIG_AGC_IDX8_GAIN_CFG_LNA_HGAIN_8(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX8_GAIN_CFG_LNA_HGAIN_8_SHIFT)) & XCVR_RX_DIG_AGC_IDX8_GAIN_CFG_LNA_HGAIN_8_MASK)

#define XCVR_RX_DIG_AGC_IDX8_GAIN_CFG_ANT_EN_RLOAD_8_MASK (0x8000U)
#define XCVR_RX_DIG_AGC_IDX8_GAIN_CFG_ANT_EN_RLOAD_8_SHIFT (15U)
/*! ANT_EN_RLOAD_8 - ANT_EN_RLOAD_8
 */
#define XCVR_RX_DIG_AGC_IDX8_GAIN_CFG_ANT_EN_RLOAD_8(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX8_GAIN_CFG_ANT_EN_RLOAD_8_SHIFT)) & XCVR_RX_DIG_AGC_IDX8_GAIN_CFG_ANT_EN_RLOAD_8_MASK)

#define XCVR_RX_DIG_AGC_IDX8_GAIN_CFG_MAG_THR_HI_8_DRS_OFS_MASK (0xFF0000U)
#define XCVR_RX_DIG_AGC_IDX8_GAIN_CFG_MAG_THR_HI_8_DRS_OFS_SHIFT (16U)
#define XCVR_RX_DIG_AGC_IDX8_GAIN_CFG_MAG_THR_HI_8_DRS_OFS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX8_GAIN_CFG_MAG_THR_HI_8_DRS_OFS_SHIFT)) & XCVR_RX_DIG_AGC_IDX8_GAIN_CFG_MAG_THR_HI_8_DRS_OFS_MASK)

#define XCVR_RX_DIG_AGC_IDX8_GAIN_CFG_MAG_THR_8_DRS_OFS_MASK (0xFF000000U)
#define XCVR_RX_DIG_AGC_IDX8_GAIN_CFG_MAG_THR_8_DRS_OFS_SHIFT (24U)
#define XCVR_RX_DIG_AGC_IDX8_GAIN_CFG_MAG_THR_8_DRS_OFS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX8_GAIN_CFG_MAG_THR_8_DRS_OFS_SHIFT)) & XCVR_RX_DIG_AGC_IDX8_GAIN_CFG_MAG_THR_8_DRS_OFS_MASK)
/*! @} */

/*! @name AGC_IDX7_GAIN_CFG - AGC IDX7 Gain Config */
/*! @{ */

#define XCVR_RX_DIG_AGC_IDX7_GAIN_CFG_CBPF_GAIN_7_MASK (0x1U)
#define XCVR_RX_DIG_AGC_IDX7_GAIN_CFG_CBPF_GAIN_7_SHIFT (0U)
/*! CBPF_GAIN_7 - CBPF_GAIN_7
 *  0b0..-6 dB
 *  0b1..0 dB
 */
#define XCVR_RX_DIG_AGC_IDX7_GAIN_CFG_CBPF_GAIN_7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX7_GAIN_CFG_CBPF_GAIN_7_SHIFT)) & XCVR_RX_DIG_AGC_IDX7_GAIN_CFG_CBPF_GAIN_7_MASK)

#define XCVR_RX_DIG_AGC_IDX7_GAIN_CFG_LNA_RTRIM_7_MASK (0xEU)
#define XCVR_RX_DIG_AGC_IDX7_GAIN_CFG_LNA_RTRIM_7_SHIFT (1U)
/*! LNA_RTRIM_7 - LNA_RTRIM_7
 */
#define XCVR_RX_DIG_AGC_IDX7_GAIN_CFG_LNA_RTRIM_7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX7_GAIN_CFG_LNA_RTRIM_7_SHIFT)) & XCVR_RX_DIG_AGC_IDX7_GAIN_CFG_LNA_RTRIM_7_MASK)

#define XCVR_RX_DIG_AGC_IDX7_GAIN_CFG_LNA_ATTN_7_MASK (0x30U)
#define XCVR_RX_DIG_AGC_IDX7_GAIN_CFG_LNA_ATTN_7_SHIFT (4U)
/*! LNA_ATTN_7 - LNA_ATTN_7
 */
#define XCVR_RX_DIG_AGC_IDX7_GAIN_CFG_LNA_ATTN_7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX7_GAIN_CFG_LNA_ATTN_7_SHIFT)) & XCVR_RX_DIG_AGC_IDX7_GAIN_CFG_LNA_ATTN_7_MASK)

#define XCVR_RX_DIG_AGC_IDX7_GAIN_CFG_LNA_HATTN_7_MASK (0x40U)
#define XCVR_RX_DIG_AGC_IDX7_GAIN_CFG_LNA_HATTN_7_SHIFT (6U)
/*! LNA_HATTN_7 - LNA_HATTN_7
 */
#define XCVR_RX_DIG_AGC_IDX7_GAIN_CFG_LNA_HATTN_7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX7_GAIN_CFG_LNA_HATTN_7_SHIFT)) & XCVR_RX_DIG_AGC_IDX7_GAIN_CFG_LNA_HATTN_7_MASK)

#define XCVR_RX_DIG_AGC_IDX7_GAIN_CFG_LNA_LGAIN_7_MASK (0x180U)
#define XCVR_RX_DIG_AGC_IDX7_GAIN_CFG_LNA_LGAIN_7_SHIFT (7U)
/*! LNA_LGAIN_7 - LNA_LGAIN_7
 */
#define XCVR_RX_DIG_AGC_IDX7_GAIN_CFG_LNA_LGAIN_7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX7_GAIN_CFG_LNA_LGAIN_7_SHIFT)) & XCVR_RX_DIG_AGC_IDX7_GAIN_CFG_LNA_LGAIN_7_MASK)

#define XCVR_RX_DIG_AGC_IDX7_GAIN_CFG_LNA_HGAIN_7_MASK (0x7E00U)
#define XCVR_RX_DIG_AGC_IDX7_GAIN_CFG_LNA_HGAIN_7_SHIFT (9U)
/*! LNA_HGAIN_7 - LNA_HGAIN_7
 */
#define XCVR_RX_DIG_AGC_IDX7_GAIN_CFG_LNA_HGAIN_7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX7_GAIN_CFG_LNA_HGAIN_7_SHIFT)) & XCVR_RX_DIG_AGC_IDX7_GAIN_CFG_LNA_HGAIN_7_MASK)

#define XCVR_RX_DIG_AGC_IDX7_GAIN_CFG_ANT_EN_RLOAD_7_MASK (0x8000U)
#define XCVR_RX_DIG_AGC_IDX7_GAIN_CFG_ANT_EN_RLOAD_7_SHIFT (15U)
/*! ANT_EN_RLOAD_7 - ANT_EN_RLOAD_7
 */
#define XCVR_RX_DIG_AGC_IDX7_GAIN_CFG_ANT_EN_RLOAD_7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX7_GAIN_CFG_ANT_EN_RLOAD_7_SHIFT)) & XCVR_RX_DIG_AGC_IDX7_GAIN_CFG_ANT_EN_RLOAD_7_MASK)

#define XCVR_RX_DIG_AGC_IDX7_GAIN_CFG_MAG_THR_HI_7_DRS_OFS_MASK (0xFF0000U)
#define XCVR_RX_DIG_AGC_IDX7_GAIN_CFG_MAG_THR_HI_7_DRS_OFS_SHIFT (16U)
#define XCVR_RX_DIG_AGC_IDX7_GAIN_CFG_MAG_THR_HI_7_DRS_OFS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX7_GAIN_CFG_MAG_THR_HI_7_DRS_OFS_SHIFT)) & XCVR_RX_DIG_AGC_IDX7_GAIN_CFG_MAG_THR_HI_7_DRS_OFS_MASK)

#define XCVR_RX_DIG_AGC_IDX7_GAIN_CFG_MAG_THR_7_DRS_OFS_MASK (0xFF000000U)
#define XCVR_RX_DIG_AGC_IDX7_GAIN_CFG_MAG_THR_7_DRS_OFS_SHIFT (24U)
#define XCVR_RX_DIG_AGC_IDX7_GAIN_CFG_MAG_THR_7_DRS_OFS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX7_GAIN_CFG_MAG_THR_7_DRS_OFS_SHIFT)) & XCVR_RX_DIG_AGC_IDX7_GAIN_CFG_MAG_THR_7_DRS_OFS_MASK)
/*! @} */

/*! @name AGC_IDX6_GAIN_CFG - AGC IDX6 Gain Config */
/*! @{ */

#define XCVR_RX_DIG_AGC_IDX6_GAIN_CFG_CBPF_GAIN_6_MASK (0x1U)
#define XCVR_RX_DIG_AGC_IDX6_GAIN_CFG_CBPF_GAIN_6_SHIFT (0U)
/*! CBPF_GAIN_6 - CBPF_GAIN_6
 *  0b0..-6 dB
 *  0b1..0 dB
 */
#define XCVR_RX_DIG_AGC_IDX6_GAIN_CFG_CBPF_GAIN_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX6_GAIN_CFG_CBPF_GAIN_6_SHIFT)) & XCVR_RX_DIG_AGC_IDX6_GAIN_CFG_CBPF_GAIN_6_MASK)

#define XCVR_RX_DIG_AGC_IDX6_GAIN_CFG_LNA_RTRIM_6_MASK (0xEU)
#define XCVR_RX_DIG_AGC_IDX6_GAIN_CFG_LNA_RTRIM_6_SHIFT (1U)
/*! LNA_RTRIM_6 - LNA_RTRIM_6
 */
#define XCVR_RX_DIG_AGC_IDX6_GAIN_CFG_LNA_RTRIM_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX6_GAIN_CFG_LNA_RTRIM_6_SHIFT)) & XCVR_RX_DIG_AGC_IDX6_GAIN_CFG_LNA_RTRIM_6_MASK)

#define XCVR_RX_DIG_AGC_IDX6_GAIN_CFG_LNA_ATTN_6_MASK (0x30U)
#define XCVR_RX_DIG_AGC_IDX6_GAIN_CFG_LNA_ATTN_6_SHIFT (4U)
/*! LNA_ATTN_6 - LNA_ATTN_6
 */
#define XCVR_RX_DIG_AGC_IDX6_GAIN_CFG_LNA_ATTN_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX6_GAIN_CFG_LNA_ATTN_6_SHIFT)) & XCVR_RX_DIG_AGC_IDX6_GAIN_CFG_LNA_ATTN_6_MASK)

#define XCVR_RX_DIG_AGC_IDX6_GAIN_CFG_LNA_HATTN_6_MASK (0x40U)
#define XCVR_RX_DIG_AGC_IDX6_GAIN_CFG_LNA_HATTN_6_SHIFT (6U)
/*! LNA_HATTN_6 - LNA_HATTN_6
 */
#define XCVR_RX_DIG_AGC_IDX6_GAIN_CFG_LNA_HATTN_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX6_GAIN_CFG_LNA_HATTN_6_SHIFT)) & XCVR_RX_DIG_AGC_IDX6_GAIN_CFG_LNA_HATTN_6_MASK)

#define XCVR_RX_DIG_AGC_IDX6_GAIN_CFG_LNA_LGAIN_6_MASK (0x180U)
#define XCVR_RX_DIG_AGC_IDX6_GAIN_CFG_LNA_LGAIN_6_SHIFT (7U)
/*! LNA_LGAIN_6 - LNA_LGAIN_6
 */
#define XCVR_RX_DIG_AGC_IDX6_GAIN_CFG_LNA_LGAIN_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX6_GAIN_CFG_LNA_LGAIN_6_SHIFT)) & XCVR_RX_DIG_AGC_IDX6_GAIN_CFG_LNA_LGAIN_6_MASK)

#define XCVR_RX_DIG_AGC_IDX6_GAIN_CFG_LNA_HGAIN_6_MASK (0x7E00U)
#define XCVR_RX_DIG_AGC_IDX6_GAIN_CFG_LNA_HGAIN_6_SHIFT (9U)
/*! LNA_HGAIN_6 - LNA_HGAIN_6
 */
#define XCVR_RX_DIG_AGC_IDX6_GAIN_CFG_LNA_HGAIN_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX6_GAIN_CFG_LNA_HGAIN_6_SHIFT)) & XCVR_RX_DIG_AGC_IDX6_GAIN_CFG_LNA_HGAIN_6_MASK)

#define XCVR_RX_DIG_AGC_IDX6_GAIN_CFG_ANT_EN_RLOAD_6_MASK (0x8000U)
#define XCVR_RX_DIG_AGC_IDX6_GAIN_CFG_ANT_EN_RLOAD_6_SHIFT (15U)
/*! ANT_EN_RLOAD_6 - ANT_EN_RLOAD_6
 */
#define XCVR_RX_DIG_AGC_IDX6_GAIN_CFG_ANT_EN_RLOAD_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX6_GAIN_CFG_ANT_EN_RLOAD_6_SHIFT)) & XCVR_RX_DIG_AGC_IDX6_GAIN_CFG_ANT_EN_RLOAD_6_MASK)

#define XCVR_RX_DIG_AGC_IDX6_GAIN_CFG_MAG_THR_HI_6_DRS_OFS_MASK (0xFF0000U)
#define XCVR_RX_DIG_AGC_IDX6_GAIN_CFG_MAG_THR_HI_6_DRS_OFS_SHIFT (16U)
#define XCVR_RX_DIG_AGC_IDX6_GAIN_CFG_MAG_THR_HI_6_DRS_OFS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX6_GAIN_CFG_MAG_THR_HI_6_DRS_OFS_SHIFT)) & XCVR_RX_DIG_AGC_IDX6_GAIN_CFG_MAG_THR_HI_6_DRS_OFS_MASK)

#define XCVR_RX_DIG_AGC_IDX6_GAIN_CFG_MAG_THR_6_DRS_OFS_MASK (0xFF000000U)
#define XCVR_RX_DIG_AGC_IDX6_GAIN_CFG_MAG_THR_6_DRS_OFS_SHIFT (24U)
#define XCVR_RX_DIG_AGC_IDX6_GAIN_CFG_MAG_THR_6_DRS_OFS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX6_GAIN_CFG_MAG_THR_6_DRS_OFS_SHIFT)) & XCVR_RX_DIG_AGC_IDX6_GAIN_CFG_MAG_THR_6_DRS_OFS_MASK)
/*! @} */

/*! @name AGC_IDX5_GAIN_CFG - AGC IDX5 Gain Config */
/*! @{ */

#define XCVR_RX_DIG_AGC_IDX5_GAIN_CFG_CBPF_GAIN_5_MASK (0x1U)
#define XCVR_RX_DIG_AGC_IDX5_GAIN_CFG_CBPF_GAIN_5_SHIFT (0U)
/*! CBPF_GAIN_5 - CBPF_GAIN_5
 *  0b0..-6 dB
 *  0b1..0 dB
 */
#define XCVR_RX_DIG_AGC_IDX5_GAIN_CFG_CBPF_GAIN_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX5_GAIN_CFG_CBPF_GAIN_5_SHIFT)) & XCVR_RX_DIG_AGC_IDX5_GAIN_CFG_CBPF_GAIN_5_MASK)

#define XCVR_RX_DIG_AGC_IDX5_GAIN_CFG_LNA_RTRIM_5_MASK (0xEU)
#define XCVR_RX_DIG_AGC_IDX5_GAIN_CFG_LNA_RTRIM_5_SHIFT (1U)
/*! LNA_RTRIM_5 - LNA_RTRIM_5
 */
#define XCVR_RX_DIG_AGC_IDX5_GAIN_CFG_LNA_RTRIM_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX5_GAIN_CFG_LNA_RTRIM_5_SHIFT)) & XCVR_RX_DIG_AGC_IDX5_GAIN_CFG_LNA_RTRIM_5_MASK)

#define XCVR_RX_DIG_AGC_IDX5_GAIN_CFG_LNA_ATTN_5_MASK (0x30U)
#define XCVR_RX_DIG_AGC_IDX5_GAIN_CFG_LNA_ATTN_5_SHIFT (4U)
/*! LNA_ATTN_5 - LNA_ATTN_5
 */
#define XCVR_RX_DIG_AGC_IDX5_GAIN_CFG_LNA_ATTN_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX5_GAIN_CFG_LNA_ATTN_5_SHIFT)) & XCVR_RX_DIG_AGC_IDX5_GAIN_CFG_LNA_ATTN_5_MASK)

#define XCVR_RX_DIG_AGC_IDX5_GAIN_CFG_LNA_HATTN_5_MASK (0x40U)
#define XCVR_RX_DIG_AGC_IDX5_GAIN_CFG_LNA_HATTN_5_SHIFT (6U)
/*! LNA_HATTN_5 - LNA_HATTN_5
 */
#define XCVR_RX_DIG_AGC_IDX5_GAIN_CFG_LNA_HATTN_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX5_GAIN_CFG_LNA_HATTN_5_SHIFT)) & XCVR_RX_DIG_AGC_IDX5_GAIN_CFG_LNA_HATTN_5_MASK)

#define XCVR_RX_DIG_AGC_IDX5_GAIN_CFG_LNA_LGAIN_5_MASK (0x180U)
#define XCVR_RX_DIG_AGC_IDX5_GAIN_CFG_LNA_LGAIN_5_SHIFT (7U)
/*! LNA_LGAIN_5 - LNA_LGAIN_5
 */
#define XCVR_RX_DIG_AGC_IDX5_GAIN_CFG_LNA_LGAIN_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX5_GAIN_CFG_LNA_LGAIN_5_SHIFT)) & XCVR_RX_DIG_AGC_IDX5_GAIN_CFG_LNA_LGAIN_5_MASK)

#define XCVR_RX_DIG_AGC_IDX5_GAIN_CFG_LNA_HGAIN_5_MASK (0x7E00U)
#define XCVR_RX_DIG_AGC_IDX5_GAIN_CFG_LNA_HGAIN_5_SHIFT (9U)
/*! LNA_HGAIN_5 - LNA_HGAIN_5
 */
#define XCVR_RX_DIG_AGC_IDX5_GAIN_CFG_LNA_HGAIN_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX5_GAIN_CFG_LNA_HGAIN_5_SHIFT)) & XCVR_RX_DIG_AGC_IDX5_GAIN_CFG_LNA_HGAIN_5_MASK)

#define XCVR_RX_DIG_AGC_IDX5_GAIN_CFG_ANT_EN_RLOAD_5_MASK (0x8000U)
#define XCVR_RX_DIG_AGC_IDX5_GAIN_CFG_ANT_EN_RLOAD_5_SHIFT (15U)
/*! ANT_EN_RLOAD_5 - ANT_EN_RLOAD_5
 */
#define XCVR_RX_DIG_AGC_IDX5_GAIN_CFG_ANT_EN_RLOAD_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX5_GAIN_CFG_ANT_EN_RLOAD_5_SHIFT)) & XCVR_RX_DIG_AGC_IDX5_GAIN_CFG_ANT_EN_RLOAD_5_MASK)

#define XCVR_RX_DIG_AGC_IDX5_GAIN_CFG_MAG_THR_HI_5_DRS_OFS_MASK (0xFF0000U)
#define XCVR_RX_DIG_AGC_IDX5_GAIN_CFG_MAG_THR_HI_5_DRS_OFS_SHIFT (16U)
#define XCVR_RX_DIG_AGC_IDX5_GAIN_CFG_MAG_THR_HI_5_DRS_OFS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX5_GAIN_CFG_MAG_THR_HI_5_DRS_OFS_SHIFT)) & XCVR_RX_DIG_AGC_IDX5_GAIN_CFG_MAG_THR_HI_5_DRS_OFS_MASK)

#define XCVR_RX_DIG_AGC_IDX5_GAIN_CFG_MAG_THR_5_DRS_OFS_MASK (0xFF000000U)
#define XCVR_RX_DIG_AGC_IDX5_GAIN_CFG_MAG_THR_5_DRS_OFS_SHIFT (24U)
#define XCVR_RX_DIG_AGC_IDX5_GAIN_CFG_MAG_THR_5_DRS_OFS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX5_GAIN_CFG_MAG_THR_5_DRS_OFS_SHIFT)) & XCVR_RX_DIG_AGC_IDX5_GAIN_CFG_MAG_THR_5_DRS_OFS_MASK)
/*! @} */

/*! @name AGC_IDX4_GAIN_CFG - AGC IDX4 Gain Config */
/*! @{ */

#define XCVR_RX_DIG_AGC_IDX4_GAIN_CFG_CBPF_GAIN_4_MASK (0x1U)
#define XCVR_RX_DIG_AGC_IDX4_GAIN_CFG_CBPF_GAIN_4_SHIFT (0U)
/*! CBPF_GAIN_4 - CBPF_GAIN_4
 *  0b0..-6 dB
 *  0b1..0 dB
 */
#define XCVR_RX_DIG_AGC_IDX4_GAIN_CFG_CBPF_GAIN_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX4_GAIN_CFG_CBPF_GAIN_4_SHIFT)) & XCVR_RX_DIG_AGC_IDX4_GAIN_CFG_CBPF_GAIN_4_MASK)

#define XCVR_RX_DIG_AGC_IDX4_GAIN_CFG_LNA_RTRIM_4_MASK (0xEU)
#define XCVR_RX_DIG_AGC_IDX4_GAIN_CFG_LNA_RTRIM_4_SHIFT (1U)
/*! LNA_RTRIM_4 - LNA_RTRIM_4
 */
#define XCVR_RX_DIG_AGC_IDX4_GAIN_CFG_LNA_RTRIM_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX4_GAIN_CFG_LNA_RTRIM_4_SHIFT)) & XCVR_RX_DIG_AGC_IDX4_GAIN_CFG_LNA_RTRIM_4_MASK)

#define XCVR_RX_DIG_AGC_IDX4_GAIN_CFG_LNA_ATTN_4_MASK (0x30U)
#define XCVR_RX_DIG_AGC_IDX4_GAIN_CFG_LNA_ATTN_4_SHIFT (4U)
/*! LNA_ATTN_4 - LNA_ATTN_4
 */
#define XCVR_RX_DIG_AGC_IDX4_GAIN_CFG_LNA_ATTN_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX4_GAIN_CFG_LNA_ATTN_4_SHIFT)) & XCVR_RX_DIG_AGC_IDX4_GAIN_CFG_LNA_ATTN_4_MASK)

#define XCVR_RX_DIG_AGC_IDX4_GAIN_CFG_LNA_HATTN_4_MASK (0x40U)
#define XCVR_RX_DIG_AGC_IDX4_GAIN_CFG_LNA_HATTN_4_SHIFT (6U)
/*! LNA_HATTN_4 - LNA_HATTN_4
 */
#define XCVR_RX_DIG_AGC_IDX4_GAIN_CFG_LNA_HATTN_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX4_GAIN_CFG_LNA_HATTN_4_SHIFT)) & XCVR_RX_DIG_AGC_IDX4_GAIN_CFG_LNA_HATTN_4_MASK)

#define XCVR_RX_DIG_AGC_IDX4_GAIN_CFG_LNA_LGAIN_4_MASK (0x180U)
#define XCVR_RX_DIG_AGC_IDX4_GAIN_CFG_LNA_LGAIN_4_SHIFT (7U)
/*! LNA_LGAIN_4 - LNA_LGAIN_4
 */
#define XCVR_RX_DIG_AGC_IDX4_GAIN_CFG_LNA_LGAIN_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX4_GAIN_CFG_LNA_LGAIN_4_SHIFT)) & XCVR_RX_DIG_AGC_IDX4_GAIN_CFG_LNA_LGAIN_4_MASK)

#define XCVR_RX_DIG_AGC_IDX4_GAIN_CFG_LNA_HGAIN_4_MASK (0x7E00U)
#define XCVR_RX_DIG_AGC_IDX4_GAIN_CFG_LNA_HGAIN_4_SHIFT (9U)
/*! LNA_HGAIN_4 - LNA_HGAIN_4
 */
#define XCVR_RX_DIG_AGC_IDX4_GAIN_CFG_LNA_HGAIN_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX4_GAIN_CFG_LNA_HGAIN_4_SHIFT)) & XCVR_RX_DIG_AGC_IDX4_GAIN_CFG_LNA_HGAIN_4_MASK)

#define XCVR_RX_DIG_AGC_IDX4_GAIN_CFG_ANT_EN_RLOAD_4_MASK (0x8000U)
#define XCVR_RX_DIG_AGC_IDX4_GAIN_CFG_ANT_EN_RLOAD_4_SHIFT (15U)
/*! ANT_EN_RLOAD_4 - ANT_EN_RLOAD_4
 */
#define XCVR_RX_DIG_AGC_IDX4_GAIN_CFG_ANT_EN_RLOAD_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX4_GAIN_CFG_ANT_EN_RLOAD_4_SHIFT)) & XCVR_RX_DIG_AGC_IDX4_GAIN_CFG_ANT_EN_RLOAD_4_MASK)

#define XCVR_RX_DIG_AGC_IDX4_GAIN_CFG_MAG_THR_HI_4_DRS_OFS_MASK (0xFF0000U)
#define XCVR_RX_DIG_AGC_IDX4_GAIN_CFG_MAG_THR_HI_4_DRS_OFS_SHIFT (16U)
#define XCVR_RX_DIG_AGC_IDX4_GAIN_CFG_MAG_THR_HI_4_DRS_OFS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX4_GAIN_CFG_MAG_THR_HI_4_DRS_OFS_SHIFT)) & XCVR_RX_DIG_AGC_IDX4_GAIN_CFG_MAG_THR_HI_4_DRS_OFS_MASK)

#define XCVR_RX_DIG_AGC_IDX4_GAIN_CFG_MAG_THR_4_DRS_OFS_MASK (0xFF000000U)
#define XCVR_RX_DIG_AGC_IDX4_GAIN_CFG_MAG_THR_4_DRS_OFS_SHIFT (24U)
#define XCVR_RX_DIG_AGC_IDX4_GAIN_CFG_MAG_THR_4_DRS_OFS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX4_GAIN_CFG_MAG_THR_4_DRS_OFS_SHIFT)) & XCVR_RX_DIG_AGC_IDX4_GAIN_CFG_MAG_THR_4_DRS_OFS_MASK)
/*! @} */

/*! @name AGC_IDX3_GAIN_CFG - AGC IDX3 Gain Config */
/*! @{ */

#define XCVR_RX_DIG_AGC_IDX3_GAIN_CFG_CBPF_GAIN_3_MASK (0x1U)
#define XCVR_RX_DIG_AGC_IDX3_GAIN_CFG_CBPF_GAIN_3_SHIFT (0U)
/*! CBPF_GAIN_3 - CBPF_GAIN_3
 *  0b0..-6 dB
 *  0b1..0 dB
 */
#define XCVR_RX_DIG_AGC_IDX3_GAIN_CFG_CBPF_GAIN_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX3_GAIN_CFG_CBPF_GAIN_3_SHIFT)) & XCVR_RX_DIG_AGC_IDX3_GAIN_CFG_CBPF_GAIN_3_MASK)

#define XCVR_RX_DIG_AGC_IDX3_GAIN_CFG_LNA_RTRIM_3_MASK (0xEU)
#define XCVR_RX_DIG_AGC_IDX3_GAIN_CFG_LNA_RTRIM_3_SHIFT (1U)
/*! LNA_RTRIM_3 - LNA_RTRIM_3
 */
#define XCVR_RX_DIG_AGC_IDX3_GAIN_CFG_LNA_RTRIM_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX3_GAIN_CFG_LNA_RTRIM_3_SHIFT)) & XCVR_RX_DIG_AGC_IDX3_GAIN_CFG_LNA_RTRIM_3_MASK)

#define XCVR_RX_DIG_AGC_IDX3_GAIN_CFG_LNA_ATTN_3_MASK (0x30U)
#define XCVR_RX_DIG_AGC_IDX3_GAIN_CFG_LNA_ATTN_3_SHIFT (4U)
/*! LNA_ATTN_3 - LNA_ATTN_3
 */
#define XCVR_RX_DIG_AGC_IDX3_GAIN_CFG_LNA_ATTN_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX3_GAIN_CFG_LNA_ATTN_3_SHIFT)) & XCVR_RX_DIG_AGC_IDX3_GAIN_CFG_LNA_ATTN_3_MASK)

#define XCVR_RX_DIG_AGC_IDX3_GAIN_CFG_LNA_HATTN_3_MASK (0x40U)
#define XCVR_RX_DIG_AGC_IDX3_GAIN_CFG_LNA_HATTN_3_SHIFT (6U)
/*! LNA_HATTN_3 - LNA_HATTN_3
 */
#define XCVR_RX_DIG_AGC_IDX3_GAIN_CFG_LNA_HATTN_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX3_GAIN_CFG_LNA_HATTN_3_SHIFT)) & XCVR_RX_DIG_AGC_IDX3_GAIN_CFG_LNA_HATTN_3_MASK)

#define XCVR_RX_DIG_AGC_IDX3_GAIN_CFG_LNA_LGAIN_3_MASK (0x180U)
#define XCVR_RX_DIG_AGC_IDX3_GAIN_CFG_LNA_LGAIN_3_SHIFT (7U)
/*! LNA_LGAIN_3 - LNA_LGAIN_3
 */
#define XCVR_RX_DIG_AGC_IDX3_GAIN_CFG_LNA_LGAIN_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX3_GAIN_CFG_LNA_LGAIN_3_SHIFT)) & XCVR_RX_DIG_AGC_IDX3_GAIN_CFG_LNA_LGAIN_3_MASK)

#define XCVR_RX_DIG_AGC_IDX3_GAIN_CFG_LNA_HGAIN_3_MASK (0x7E00U)
#define XCVR_RX_DIG_AGC_IDX3_GAIN_CFG_LNA_HGAIN_3_SHIFT (9U)
/*! LNA_HGAIN_3 - LNA_HGAIN_3
 */
#define XCVR_RX_DIG_AGC_IDX3_GAIN_CFG_LNA_HGAIN_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX3_GAIN_CFG_LNA_HGAIN_3_SHIFT)) & XCVR_RX_DIG_AGC_IDX3_GAIN_CFG_LNA_HGAIN_3_MASK)

#define XCVR_RX_DIG_AGC_IDX3_GAIN_CFG_ANT_EN_RLOAD_3_MASK (0x8000U)
#define XCVR_RX_DIG_AGC_IDX3_GAIN_CFG_ANT_EN_RLOAD_3_SHIFT (15U)
/*! ANT_EN_RLOAD_3 - ANT_EN_RLOAD_3
 */
#define XCVR_RX_DIG_AGC_IDX3_GAIN_CFG_ANT_EN_RLOAD_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX3_GAIN_CFG_ANT_EN_RLOAD_3_SHIFT)) & XCVR_RX_DIG_AGC_IDX3_GAIN_CFG_ANT_EN_RLOAD_3_MASK)

#define XCVR_RX_DIG_AGC_IDX3_GAIN_CFG_MAG_THR_HI_3_DRS_OFS_MASK (0xFF0000U)
#define XCVR_RX_DIG_AGC_IDX3_GAIN_CFG_MAG_THR_HI_3_DRS_OFS_SHIFT (16U)
#define XCVR_RX_DIG_AGC_IDX3_GAIN_CFG_MAG_THR_HI_3_DRS_OFS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX3_GAIN_CFG_MAG_THR_HI_3_DRS_OFS_SHIFT)) & XCVR_RX_DIG_AGC_IDX3_GAIN_CFG_MAG_THR_HI_3_DRS_OFS_MASK)

#define XCVR_RX_DIG_AGC_IDX3_GAIN_CFG_MAG_THR_3_DRS_OFS_MASK (0xFF000000U)
#define XCVR_RX_DIG_AGC_IDX3_GAIN_CFG_MAG_THR_3_DRS_OFS_SHIFT (24U)
#define XCVR_RX_DIG_AGC_IDX3_GAIN_CFG_MAG_THR_3_DRS_OFS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX3_GAIN_CFG_MAG_THR_3_DRS_OFS_SHIFT)) & XCVR_RX_DIG_AGC_IDX3_GAIN_CFG_MAG_THR_3_DRS_OFS_MASK)
/*! @} */

/*! @name AGC_IDX2_GAIN_CFG - AGC IDX2 Gain Config */
/*! @{ */

#define XCVR_RX_DIG_AGC_IDX2_GAIN_CFG_CBPF_GAIN_2_MASK (0x1U)
#define XCVR_RX_DIG_AGC_IDX2_GAIN_CFG_CBPF_GAIN_2_SHIFT (0U)
/*! CBPF_GAIN_2 - CBPF_GAIN_2
 *  0b0..-6 dB
 *  0b1..0 dB
 */
#define XCVR_RX_DIG_AGC_IDX2_GAIN_CFG_CBPF_GAIN_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX2_GAIN_CFG_CBPF_GAIN_2_SHIFT)) & XCVR_RX_DIG_AGC_IDX2_GAIN_CFG_CBPF_GAIN_2_MASK)

#define XCVR_RX_DIG_AGC_IDX2_GAIN_CFG_LNA_RTRIM_2_MASK (0xEU)
#define XCVR_RX_DIG_AGC_IDX2_GAIN_CFG_LNA_RTRIM_2_SHIFT (1U)
/*! LNA_RTRIM_2 - LNA_RTRIM_2
 */
#define XCVR_RX_DIG_AGC_IDX2_GAIN_CFG_LNA_RTRIM_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX2_GAIN_CFG_LNA_RTRIM_2_SHIFT)) & XCVR_RX_DIG_AGC_IDX2_GAIN_CFG_LNA_RTRIM_2_MASK)

#define XCVR_RX_DIG_AGC_IDX2_GAIN_CFG_LNA_ATTN_2_MASK (0x30U)
#define XCVR_RX_DIG_AGC_IDX2_GAIN_CFG_LNA_ATTN_2_SHIFT (4U)
/*! LNA_ATTN_2 - LNA_ATTN_2
 */
#define XCVR_RX_DIG_AGC_IDX2_GAIN_CFG_LNA_ATTN_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX2_GAIN_CFG_LNA_ATTN_2_SHIFT)) & XCVR_RX_DIG_AGC_IDX2_GAIN_CFG_LNA_ATTN_2_MASK)

#define XCVR_RX_DIG_AGC_IDX2_GAIN_CFG_LNA_HATTN_2_MASK (0x40U)
#define XCVR_RX_DIG_AGC_IDX2_GAIN_CFG_LNA_HATTN_2_SHIFT (6U)
/*! LNA_HATTN_2 - LNA_HATTN_2
 */
#define XCVR_RX_DIG_AGC_IDX2_GAIN_CFG_LNA_HATTN_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX2_GAIN_CFG_LNA_HATTN_2_SHIFT)) & XCVR_RX_DIG_AGC_IDX2_GAIN_CFG_LNA_HATTN_2_MASK)

#define XCVR_RX_DIG_AGC_IDX2_GAIN_CFG_LNA_LGAIN_2_MASK (0x180U)
#define XCVR_RX_DIG_AGC_IDX2_GAIN_CFG_LNA_LGAIN_2_SHIFT (7U)
/*! LNA_LGAIN_2 - LNA_LGAIN_2
 */
#define XCVR_RX_DIG_AGC_IDX2_GAIN_CFG_LNA_LGAIN_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX2_GAIN_CFG_LNA_LGAIN_2_SHIFT)) & XCVR_RX_DIG_AGC_IDX2_GAIN_CFG_LNA_LGAIN_2_MASK)

#define XCVR_RX_DIG_AGC_IDX2_GAIN_CFG_LNA_HGAIN_2_MASK (0x7E00U)
#define XCVR_RX_DIG_AGC_IDX2_GAIN_CFG_LNA_HGAIN_2_SHIFT (9U)
/*! LNA_HGAIN_2 - LNA_HGAIN_2
 */
#define XCVR_RX_DIG_AGC_IDX2_GAIN_CFG_LNA_HGAIN_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX2_GAIN_CFG_LNA_HGAIN_2_SHIFT)) & XCVR_RX_DIG_AGC_IDX2_GAIN_CFG_LNA_HGAIN_2_MASK)

#define XCVR_RX_DIG_AGC_IDX2_GAIN_CFG_ANT_EN_RLOAD_2_MASK (0x8000U)
#define XCVR_RX_DIG_AGC_IDX2_GAIN_CFG_ANT_EN_RLOAD_2_SHIFT (15U)
/*! ANT_EN_RLOAD_2 - ANT_EN_RLOAD_2
 */
#define XCVR_RX_DIG_AGC_IDX2_GAIN_CFG_ANT_EN_RLOAD_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX2_GAIN_CFG_ANT_EN_RLOAD_2_SHIFT)) & XCVR_RX_DIG_AGC_IDX2_GAIN_CFG_ANT_EN_RLOAD_2_MASK)

#define XCVR_RX_DIG_AGC_IDX2_GAIN_CFG_MAG_THR_HI_2_DRS_OFS_MASK (0xFF0000U)
#define XCVR_RX_DIG_AGC_IDX2_GAIN_CFG_MAG_THR_HI_2_DRS_OFS_SHIFT (16U)
#define XCVR_RX_DIG_AGC_IDX2_GAIN_CFG_MAG_THR_HI_2_DRS_OFS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX2_GAIN_CFG_MAG_THR_HI_2_DRS_OFS_SHIFT)) & XCVR_RX_DIG_AGC_IDX2_GAIN_CFG_MAG_THR_HI_2_DRS_OFS_MASK)

#define XCVR_RX_DIG_AGC_IDX2_GAIN_CFG_MAG_THR_2_DRS_OFS_MASK (0xFF000000U)
#define XCVR_RX_DIG_AGC_IDX2_GAIN_CFG_MAG_THR_2_DRS_OFS_SHIFT (24U)
#define XCVR_RX_DIG_AGC_IDX2_GAIN_CFG_MAG_THR_2_DRS_OFS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX2_GAIN_CFG_MAG_THR_2_DRS_OFS_SHIFT)) & XCVR_RX_DIG_AGC_IDX2_GAIN_CFG_MAG_THR_2_DRS_OFS_MASK)
/*! @} */

/*! @name AGC_IDX1_GAIN_CFG - AGC IDX1 Gain Config */
/*! @{ */

#define XCVR_RX_DIG_AGC_IDX1_GAIN_CFG_CBPF_GAIN_1_MASK (0x1U)
#define XCVR_RX_DIG_AGC_IDX1_GAIN_CFG_CBPF_GAIN_1_SHIFT (0U)
/*! CBPF_GAIN_1 - CBPF_GAIN_1
 *  0b0..-6 dB
 *  0b1..0 dB
 */
#define XCVR_RX_DIG_AGC_IDX1_GAIN_CFG_CBPF_GAIN_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX1_GAIN_CFG_CBPF_GAIN_1_SHIFT)) & XCVR_RX_DIG_AGC_IDX1_GAIN_CFG_CBPF_GAIN_1_MASK)

#define XCVR_RX_DIG_AGC_IDX1_GAIN_CFG_LNA_RTRIM_1_MASK (0xEU)
#define XCVR_RX_DIG_AGC_IDX1_GAIN_CFG_LNA_RTRIM_1_SHIFT (1U)
/*! LNA_RTRIM_1 - LNA_RTRIM_1
 */
#define XCVR_RX_DIG_AGC_IDX1_GAIN_CFG_LNA_RTRIM_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX1_GAIN_CFG_LNA_RTRIM_1_SHIFT)) & XCVR_RX_DIG_AGC_IDX1_GAIN_CFG_LNA_RTRIM_1_MASK)

#define XCVR_RX_DIG_AGC_IDX1_GAIN_CFG_LNA_ATTN_1_MASK (0x30U)
#define XCVR_RX_DIG_AGC_IDX1_GAIN_CFG_LNA_ATTN_1_SHIFT (4U)
/*! LNA_ATTN_1 - LNA_ATTN_1
 */
#define XCVR_RX_DIG_AGC_IDX1_GAIN_CFG_LNA_ATTN_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX1_GAIN_CFG_LNA_ATTN_1_SHIFT)) & XCVR_RX_DIG_AGC_IDX1_GAIN_CFG_LNA_ATTN_1_MASK)

#define XCVR_RX_DIG_AGC_IDX1_GAIN_CFG_LNA_HATTN_1_MASK (0x40U)
#define XCVR_RX_DIG_AGC_IDX1_GAIN_CFG_LNA_HATTN_1_SHIFT (6U)
/*! LNA_HATTN_1 - LNA_HATTN_1
 */
#define XCVR_RX_DIG_AGC_IDX1_GAIN_CFG_LNA_HATTN_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX1_GAIN_CFG_LNA_HATTN_1_SHIFT)) & XCVR_RX_DIG_AGC_IDX1_GAIN_CFG_LNA_HATTN_1_MASK)

#define XCVR_RX_DIG_AGC_IDX1_GAIN_CFG_LNA_LGAIN_1_MASK (0x180U)
#define XCVR_RX_DIG_AGC_IDX1_GAIN_CFG_LNA_LGAIN_1_SHIFT (7U)
/*! LNA_LGAIN_1 - LNA_LGAIN_1
 */
#define XCVR_RX_DIG_AGC_IDX1_GAIN_CFG_LNA_LGAIN_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX1_GAIN_CFG_LNA_LGAIN_1_SHIFT)) & XCVR_RX_DIG_AGC_IDX1_GAIN_CFG_LNA_LGAIN_1_MASK)

#define XCVR_RX_DIG_AGC_IDX1_GAIN_CFG_LNA_HGAIN_1_MASK (0x7E00U)
#define XCVR_RX_DIG_AGC_IDX1_GAIN_CFG_LNA_HGAIN_1_SHIFT (9U)
/*! LNA_HGAIN_1 - LNA_HGAIN_1
 */
#define XCVR_RX_DIG_AGC_IDX1_GAIN_CFG_LNA_HGAIN_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX1_GAIN_CFG_LNA_HGAIN_1_SHIFT)) & XCVR_RX_DIG_AGC_IDX1_GAIN_CFG_LNA_HGAIN_1_MASK)

#define XCVR_RX_DIG_AGC_IDX1_GAIN_CFG_ANT_EN_RLOAD_1_MASK (0x8000U)
#define XCVR_RX_DIG_AGC_IDX1_GAIN_CFG_ANT_EN_RLOAD_1_SHIFT (15U)
/*! ANT_EN_RLOAD_1 - ANT_EN_RLOAD_1
 */
#define XCVR_RX_DIG_AGC_IDX1_GAIN_CFG_ANT_EN_RLOAD_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX1_GAIN_CFG_ANT_EN_RLOAD_1_SHIFT)) & XCVR_RX_DIG_AGC_IDX1_GAIN_CFG_ANT_EN_RLOAD_1_MASK)

#define XCVR_RX_DIG_AGC_IDX1_GAIN_CFG_MAG_THR_HI_1_DRS_OFS_MASK (0xFF0000U)
#define XCVR_RX_DIG_AGC_IDX1_GAIN_CFG_MAG_THR_HI_1_DRS_OFS_SHIFT (16U)
#define XCVR_RX_DIG_AGC_IDX1_GAIN_CFG_MAG_THR_HI_1_DRS_OFS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX1_GAIN_CFG_MAG_THR_HI_1_DRS_OFS_SHIFT)) & XCVR_RX_DIG_AGC_IDX1_GAIN_CFG_MAG_THR_HI_1_DRS_OFS_MASK)

#define XCVR_RX_DIG_AGC_IDX1_GAIN_CFG_MAG_THR_1_DRS_OFS_MASK (0xFF000000U)
#define XCVR_RX_DIG_AGC_IDX1_GAIN_CFG_MAG_THR_1_DRS_OFS_SHIFT (24U)
#define XCVR_RX_DIG_AGC_IDX1_GAIN_CFG_MAG_THR_1_DRS_OFS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX1_GAIN_CFG_MAG_THR_1_DRS_OFS_SHIFT)) & XCVR_RX_DIG_AGC_IDX1_GAIN_CFG_MAG_THR_1_DRS_OFS_MASK)
/*! @} */

/*! @name AGC_IDX0_GAIN_CFG - AGC IDX0 Gain Config */
/*! @{ */

#define XCVR_RX_DIG_AGC_IDX0_GAIN_CFG_CBPF_GAIN_0_MASK (0x1U)
#define XCVR_RX_DIG_AGC_IDX0_GAIN_CFG_CBPF_GAIN_0_SHIFT (0U)
/*! CBPF_GAIN_0 - CBPF_GAIN_0
 *  0b0..-6 dB
 *  0b1..0 dB
 */
#define XCVR_RX_DIG_AGC_IDX0_GAIN_CFG_CBPF_GAIN_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX0_GAIN_CFG_CBPF_GAIN_0_SHIFT)) & XCVR_RX_DIG_AGC_IDX0_GAIN_CFG_CBPF_GAIN_0_MASK)

#define XCVR_RX_DIG_AGC_IDX0_GAIN_CFG_LNA_RTRIM_0_MASK (0xEU)
#define XCVR_RX_DIG_AGC_IDX0_GAIN_CFG_LNA_RTRIM_0_SHIFT (1U)
/*! LNA_RTRIM_0 - LNA_RTRIM_0
 */
#define XCVR_RX_DIG_AGC_IDX0_GAIN_CFG_LNA_RTRIM_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX0_GAIN_CFG_LNA_RTRIM_0_SHIFT)) & XCVR_RX_DIG_AGC_IDX0_GAIN_CFG_LNA_RTRIM_0_MASK)

#define XCVR_RX_DIG_AGC_IDX0_GAIN_CFG_LNA_ATTN_0_MASK (0x30U)
#define XCVR_RX_DIG_AGC_IDX0_GAIN_CFG_LNA_ATTN_0_SHIFT (4U)
/*! LNA_ATTN_0 - LNA_ATTN_0
 */
#define XCVR_RX_DIG_AGC_IDX0_GAIN_CFG_LNA_ATTN_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX0_GAIN_CFG_LNA_ATTN_0_SHIFT)) & XCVR_RX_DIG_AGC_IDX0_GAIN_CFG_LNA_ATTN_0_MASK)

#define XCVR_RX_DIG_AGC_IDX0_GAIN_CFG_LNA_HATTN_0_MASK (0x40U)
#define XCVR_RX_DIG_AGC_IDX0_GAIN_CFG_LNA_HATTN_0_SHIFT (6U)
/*! LNA_HATTN_0 - LNA_HATTN_0
 */
#define XCVR_RX_DIG_AGC_IDX0_GAIN_CFG_LNA_HATTN_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX0_GAIN_CFG_LNA_HATTN_0_SHIFT)) & XCVR_RX_DIG_AGC_IDX0_GAIN_CFG_LNA_HATTN_0_MASK)

#define XCVR_RX_DIG_AGC_IDX0_GAIN_CFG_LNA_LGAIN_0_MASK (0x180U)
#define XCVR_RX_DIG_AGC_IDX0_GAIN_CFG_LNA_LGAIN_0_SHIFT (7U)
/*! LNA_LGAIN_0 - LNA_LGAIN_0
 */
#define XCVR_RX_DIG_AGC_IDX0_GAIN_CFG_LNA_LGAIN_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX0_GAIN_CFG_LNA_LGAIN_0_SHIFT)) & XCVR_RX_DIG_AGC_IDX0_GAIN_CFG_LNA_LGAIN_0_MASK)

#define XCVR_RX_DIG_AGC_IDX0_GAIN_CFG_LNA_HGAIN_0_MASK (0x7E00U)
#define XCVR_RX_DIG_AGC_IDX0_GAIN_CFG_LNA_HGAIN_0_SHIFT (9U)
/*! LNA_HGAIN_0 - LNA_HGAIN_0
 */
#define XCVR_RX_DIG_AGC_IDX0_GAIN_CFG_LNA_HGAIN_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX0_GAIN_CFG_LNA_HGAIN_0_SHIFT)) & XCVR_RX_DIG_AGC_IDX0_GAIN_CFG_LNA_HGAIN_0_MASK)

#define XCVR_RX_DIG_AGC_IDX0_GAIN_CFG_ANT_EN_RLOAD_0_MASK (0x8000U)
#define XCVR_RX_DIG_AGC_IDX0_GAIN_CFG_ANT_EN_RLOAD_0_SHIFT (15U)
/*! ANT_EN_RLOAD_0 - ANT_EN_RLOAD_0
 */
#define XCVR_RX_DIG_AGC_IDX0_GAIN_CFG_ANT_EN_RLOAD_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX0_GAIN_CFG_ANT_EN_RLOAD_0_SHIFT)) & XCVR_RX_DIG_AGC_IDX0_GAIN_CFG_ANT_EN_RLOAD_0_MASK)

#define XCVR_RX_DIG_AGC_IDX0_GAIN_CFG_MAG_THR_HI_0_DRS_OFS_MASK (0xFF0000U)
#define XCVR_RX_DIG_AGC_IDX0_GAIN_CFG_MAG_THR_HI_0_DRS_OFS_SHIFT (16U)
#define XCVR_RX_DIG_AGC_IDX0_GAIN_CFG_MAG_THR_HI_0_DRS_OFS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX0_GAIN_CFG_MAG_THR_HI_0_DRS_OFS_SHIFT)) & XCVR_RX_DIG_AGC_IDX0_GAIN_CFG_MAG_THR_HI_0_DRS_OFS_MASK)

#define XCVR_RX_DIG_AGC_IDX0_GAIN_CFG_MAG_THR_0_DRS_OFS_MASK (0xFF000000U)
#define XCVR_RX_DIG_AGC_IDX0_GAIN_CFG_MAG_THR_0_DRS_OFS_SHIFT (24U)
#define XCVR_RX_DIG_AGC_IDX0_GAIN_CFG_MAG_THR_0_DRS_OFS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX0_GAIN_CFG_MAG_THR_0_DRS_OFS_SHIFT)) & XCVR_RX_DIG_AGC_IDX0_GAIN_CFG_MAG_THR_0_DRS_OFS_MASK)
/*! @} */

/*! @name AGC_MIS_GAIN_CFG - AGC Miscellaneous Gain Config */
/*! @{ */

#define XCVR_RX_DIG_AGC_MIS_GAIN_CFG_LNA_RTRIM_IN_DCOC_CAL_MASK (0x7U)
#define XCVR_RX_DIG_AGC_MIS_GAIN_CFG_LNA_RTRIM_IN_DCOC_CAL_SHIFT (0U)
#define XCVR_RX_DIG_AGC_MIS_GAIN_CFG_LNA_RTRIM_IN_DCOC_CAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_MIS_GAIN_CFG_LNA_RTRIM_IN_DCOC_CAL_SHIFT)) & XCVR_RX_DIG_AGC_MIS_GAIN_CFG_LNA_RTRIM_IN_DCOC_CAL_MASK)

#define XCVR_RX_DIG_AGC_MIS_GAIN_CFG_LNA_RTRIM_IN_TX_MODE_MASK (0x38U)
#define XCVR_RX_DIG_AGC_MIS_GAIN_CFG_LNA_RTRIM_IN_TX_MODE_SHIFT (3U)
#define XCVR_RX_DIG_AGC_MIS_GAIN_CFG_LNA_RTRIM_IN_TX_MODE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_MIS_GAIN_CFG_LNA_RTRIM_IN_TX_MODE_SHIFT)) & XCVR_RX_DIG_AGC_MIS_GAIN_CFG_LNA_RTRIM_IN_TX_MODE_MASK)

#define XCVR_RX_DIG_AGC_MIS_GAIN_CFG_LNA_HATTN_IN_TX_MODE_MASK (0x40U)
#define XCVR_RX_DIG_AGC_MIS_GAIN_CFG_LNA_HATTN_IN_TX_MODE_SHIFT (6U)
#define XCVR_RX_DIG_AGC_MIS_GAIN_CFG_LNA_HATTN_IN_TX_MODE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_MIS_GAIN_CFG_LNA_HATTN_IN_TX_MODE_SHIFT)) & XCVR_RX_DIG_AGC_MIS_GAIN_CFG_LNA_HATTN_IN_TX_MODE_MASK)
/*! @} */

/*! @name AGC_IDX11_GAIN_VAL - AGC IDX11 Gain Value */
/*! @{ */

#define XCVR_RX_DIG_AGC_IDX11_GAIN_VAL_LOG_GAIN_11_MASK (0x3FFU)
#define XCVR_RX_DIG_AGC_IDX11_GAIN_VAL_LOG_GAIN_11_SHIFT (0U)
/*! LOG_GAIN_11 - LOG_GAIN_11
 */
#define XCVR_RX_DIG_AGC_IDX11_GAIN_VAL_LOG_GAIN_11(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX11_GAIN_VAL_LOG_GAIN_11_SHIFT)) & XCVR_RX_DIG_AGC_IDX11_GAIN_VAL_LOG_GAIN_11_MASK)

#define XCVR_RX_DIG_AGC_IDX11_GAIN_VAL_MAG_THR_HI_11_MASK (0x1FFC00U)
#define XCVR_RX_DIG_AGC_IDX11_GAIN_VAL_MAG_THR_HI_11_SHIFT (10U)
#define XCVR_RX_DIG_AGC_IDX11_GAIN_VAL_MAG_THR_HI_11(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX11_GAIN_VAL_MAG_THR_HI_11_SHIFT)) & XCVR_RX_DIG_AGC_IDX11_GAIN_VAL_MAG_THR_HI_11_MASK)

#define XCVR_RX_DIG_AGC_IDX11_GAIN_VAL_MAG_THR_11_MASK (0xFFE00000U)
#define XCVR_RX_DIG_AGC_IDX11_GAIN_VAL_MAG_THR_11_SHIFT (21U)
#define XCVR_RX_DIG_AGC_IDX11_GAIN_VAL_MAG_THR_11(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX11_GAIN_VAL_MAG_THR_11_SHIFT)) & XCVR_RX_DIG_AGC_IDX11_GAIN_VAL_MAG_THR_11_MASK)
/*! @} */

/*! @name AGC_IDX10_GAIN_VAL - AGC_IDX10_GAIN_VAL */
/*! @{ */

#define XCVR_RX_DIG_AGC_IDX10_GAIN_VAL_LOG_GAIN_10_MASK (0x3FFU)
#define XCVR_RX_DIG_AGC_IDX10_GAIN_VAL_LOG_GAIN_10_SHIFT (0U)
/*! LOG_GAIN_10 - LOG_GAIN_10
 */
#define XCVR_RX_DIG_AGC_IDX10_GAIN_VAL_LOG_GAIN_10(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX10_GAIN_VAL_LOG_GAIN_10_SHIFT)) & XCVR_RX_DIG_AGC_IDX10_GAIN_VAL_LOG_GAIN_10_MASK)

#define XCVR_RX_DIG_AGC_IDX10_GAIN_VAL_MAG_THR_HI_10_MASK (0x1FFC00U)
#define XCVR_RX_DIG_AGC_IDX10_GAIN_VAL_MAG_THR_HI_10_SHIFT (10U)
#define XCVR_RX_DIG_AGC_IDX10_GAIN_VAL_MAG_THR_HI_10(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX10_GAIN_VAL_MAG_THR_HI_10_SHIFT)) & XCVR_RX_DIG_AGC_IDX10_GAIN_VAL_MAG_THR_HI_10_MASK)

#define XCVR_RX_DIG_AGC_IDX10_GAIN_VAL_MAG_THR_10_MASK (0xFFE00000U)
#define XCVR_RX_DIG_AGC_IDX10_GAIN_VAL_MAG_THR_10_SHIFT (21U)
#define XCVR_RX_DIG_AGC_IDX10_GAIN_VAL_MAG_THR_10(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX10_GAIN_VAL_MAG_THR_10_SHIFT)) & XCVR_RX_DIG_AGC_IDX10_GAIN_VAL_MAG_THR_10_MASK)
/*! @} */

/*! @name AGC_IDX9_GAIN_VAL - AGC_IDX9_GAIN_VAL */
/*! @{ */

#define XCVR_RX_DIG_AGC_IDX9_GAIN_VAL_LOG_GAIN_9_MASK (0x3FFU)
#define XCVR_RX_DIG_AGC_IDX9_GAIN_VAL_LOG_GAIN_9_SHIFT (0U)
/*! LOG_GAIN_9 - LOG_GAIN_9
 */
#define XCVR_RX_DIG_AGC_IDX9_GAIN_VAL_LOG_GAIN_9(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX9_GAIN_VAL_LOG_GAIN_9_SHIFT)) & XCVR_RX_DIG_AGC_IDX9_GAIN_VAL_LOG_GAIN_9_MASK)

#define XCVR_RX_DIG_AGC_IDX9_GAIN_VAL_MAG_THR_HI_9_MASK (0x1FFC00U)
#define XCVR_RX_DIG_AGC_IDX9_GAIN_VAL_MAG_THR_HI_9_SHIFT (10U)
#define XCVR_RX_DIG_AGC_IDX9_GAIN_VAL_MAG_THR_HI_9(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX9_GAIN_VAL_MAG_THR_HI_9_SHIFT)) & XCVR_RX_DIG_AGC_IDX9_GAIN_VAL_MAG_THR_HI_9_MASK)

#define XCVR_RX_DIG_AGC_IDX9_GAIN_VAL_MAG_THR_9_MASK (0xFFE00000U)
#define XCVR_RX_DIG_AGC_IDX9_GAIN_VAL_MAG_THR_9_SHIFT (21U)
#define XCVR_RX_DIG_AGC_IDX9_GAIN_VAL_MAG_THR_9(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX9_GAIN_VAL_MAG_THR_9_SHIFT)) & XCVR_RX_DIG_AGC_IDX9_GAIN_VAL_MAG_THR_9_MASK)
/*! @} */

/*! @name AGC_IDX8_GAIN_VAL - AGC_IDX8_GAIN_VAL */
/*! @{ */

#define XCVR_RX_DIG_AGC_IDX8_GAIN_VAL_LOG_GAIN_8_MASK (0x3FFU)
#define XCVR_RX_DIG_AGC_IDX8_GAIN_VAL_LOG_GAIN_8_SHIFT (0U)
/*! LOG_GAIN_8 - LOG_GAIN_8
 */
#define XCVR_RX_DIG_AGC_IDX8_GAIN_VAL_LOG_GAIN_8(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX8_GAIN_VAL_LOG_GAIN_8_SHIFT)) & XCVR_RX_DIG_AGC_IDX8_GAIN_VAL_LOG_GAIN_8_MASK)

#define XCVR_RX_DIG_AGC_IDX8_GAIN_VAL_MAG_THR_HI_8_MASK (0x1FFC00U)
#define XCVR_RX_DIG_AGC_IDX8_GAIN_VAL_MAG_THR_HI_8_SHIFT (10U)
#define XCVR_RX_DIG_AGC_IDX8_GAIN_VAL_MAG_THR_HI_8(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX8_GAIN_VAL_MAG_THR_HI_8_SHIFT)) & XCVR_RX_DIG_AGC_IDX8_GAIN_VAL_MAG_THR_HI_8_MASK)

#define XCVR_RX_DIG_AGC_IDX8_GAIN_VAL_MAG_THR_8_MASK (0xFFE00000U)
#define XCVR_RX_DIG_AGC_IDX8_GAIN_VAL_MAG_THR_8_SHIFT (21U)
#define XCVR_RX_DIG_AGC_IDX8_GAIN_VAL_MAG_THR_8(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX8_GAIN_VAL_MAG_THR_8_SHIFT)) & XCVR_RX_DIG_AGC_IDX8_GAIN_VAL_MAG_THR_8_MASK)
/*! @} */

/*! @name AGC_IDX7_GAIN_VAL - AGC_IDX7_GAIN_VAL */
/*! @{ */

#define XCVR_RX_DIG_AGC_IDX7_GAIN_VAL_LOG_GAIN_7_MASK (0x3FFU)
#define XCVR_RX_DIG_AGC_IDX7_GAIN_VAL_LOG_GAIN_7_SHIFT (0U)
/*! LOG_GAIN_7 - LOG_GAIN_7
 */
#define XCVR_RX_DIG_AGC_IDX7_GAIN_VAL_LOG_GAIN_7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX7_GAIN_VAL_LOG_GAIN_7_SHIFT)) & XCVR_RX_DIG_AGC_IDX7_GAIN_VAL_LOG_GAIN_7_MASK)

#define XCVR_RX_DIG_AGC_IDX7_GAIN_VAL_MAG_THR_HI_7_MASK (0x1FFC00U)
#define XCVR_RX_DIG_AGC_IDX7_GAIN_VAL_MAG_THR_HI_7_SHIFT (10U)
#define XCVR_RX_DIG_AGC_IDX7_GAIN_VAL_MAG_THR_HI_7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX7_GAIN_VAL_MAG_THR_HI_7_SHIFT)) & XCVR_RX_DIG_AGC_IDX7_GAIN_VAL_MAG_THR_HI_7_MASK)

#define XCVR_RX_DIG_AGC_IDX7_GAIN_VAL_MAG_THR_7_MASK (0xFFE00000U)
#define XCVR_RX_DIG_AGC_IDX7_GAIN_VAL_MAG_THR_7_SHIFT (21U)
#define XCVR_RX_DIG_AGC_IDX7_GAIN_VAL_MAG_THR_7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX7_GAIN_VAL_MAG_THR_7_SHIFT)) & XCVR_RX_DIG_AGC_IDX7_GAIN_VAL_MAG_THR_7_MASK)
/*! @} */

/*! @name AGC_IDX6_GAIN_VAL - AGC_IDX6_GAIN_VAL */
/*! @{ */

#define XCVR_RX_DIG_AGC_IDX6_GAIN_VAL_LOG_GAIN_6_MASK (0x3FFU)
#define XCVR_RX_DIG_AGC_IDX6_GAIN_VAL_LOG_GAIN_6_SHIFT (0U)
/*! LOG_GAIN_6 - LOG_GAIN_6
 */
#define XCVR_RX_DIG_AGC_IDX6_GAIN_VAL_LOG_GAIN_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX6_GAIN_VAL_LOG_GAIN_6_SHIFT)) & XCVR_RX_DIG_AGC_IDX6_GAIN_VAL_LOG_GAIN_6_MASK)

#define XCVR_RX_DIG_AGC_IDX6_GAIN_VAL_MAG_THR_HI_6_MASK (0x1FFC00U)
#define XCVR_RX_DIG_AGC_IDX6_GAIN_VAL_MAG_THR_HI_6_SHIFT (10U)
#define XCVR_RX_DIG_AGC_IDX6_GAIN_VAL_MAG_THR_HI_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX6_GAIN_VAL_MAG_THR_HI_6_SHIFT)) & XCVR_RX_DIG_AGC_IDX6_GAIN_VAL_MAG_THR_HI_6_MASK)

#define XCVR_RX_DIG_AGC_IDX6_GAIN_VAL_MAG_THR_6_MASK (0xFFE00000U)
#define XCVR_RX_DIG_AGC_IDX6_GAIN_VAL_MAG_THR_6_SHIFT (21U)
#define XCVR_RX_DIG_AGC_IDX6_GAIN_VAL_MAG_THR_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX6_GAIN_VAL_MAG_THR_6_SHIFT)) & XCVR_RX_DIG_AGC_IDX6_GAIN_VAL_MAG_THR_6_MASK)
/*! @} */

/*! @name AGC_IDX5_GAIN_VAL - AGC_IDX5_GAIN_VAL */
/*! @{ */

#define XCVR_RX_DIG_AGC_IDX5_GAIN_VAL_LOG_GAIN_5_MASK (0x3FFU)
#define XCVR_RX_DIG_AGC_IDX5_GAIN_VAL_LOG_GAIN_5_SHIFT (0U)
/*! LOG_GAIN_5 - LOG_GAIN_5
 */
#define XCVR_RX_DIG_AGC_IDX5_GAIN_VAL_LOG_GAIN_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX5_GAIN_VAL_LOG_GAIN_5_SHIFT)) & XCVR_RX_DIG_AGC_IDX5_GAIN_VAL_LOG_GAIN_5_MASK)

#define XCVR_RX_DIG_AGC_IDX5_GAIN_VAL_MAG_THR_HI_5_MASK (0x1FFC00U)
#define XCVR_RX_DIG_AGC_IDX5_GAIN_VAL_MAG_THR_HI_5_SHIFT (10U)
#define XCVR_RX_DIG_AGC_IDX5_GAIN_VAL_MAG_THR_HI_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX5_GAIN_VAL_MAG_THR_HI_5_SHIFT)) & XCVR_RX_DIG_AGC_IDX5_GAIN_VAL_MAG_THR_HI_5_MASK)

#define XCVR_RX_DIG_AGC_IDX5_GAIN_VAL_MAG_THR_5_MASK (0xFFE00000U)
#define XCVR_RX_DIG_AGC_IDX5_GAIN_VAL_MAG_THR_5_SHIFT (21U)
#define XCVR_RX_DIG_AGC_IDX5_GAIN_VAL_MAG_THR_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX5_GAIN_VAL_MAG_THR_5_SHIFT)) & XCVR_RX_DIG_AGC_IDX5_GAIN_VAL_MAG_THR_5_MASK)
/*! @} */

/*! @name AGC_IDX4_GAIN_VAL - AGC_IDX4_GAIN_VAL */
/*! @{ */

#define XCVR_RX_DIG_AGC_IDX4_GAIN_VAL_LOG_GAIN_4_MASK (0x3FFU)
#define XCVR_RX_DIG_AGC_IDX4_GAIN_VAL_LOG_GAIN_4_SHIFT (0U)
/*! LOG_GAIN_4 - LOG_GAIN_4
 */
#define XCVR_RX_DIG_AGC_IDX4_GAIN_VAL_LOG_GAIN_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX4_GAIN_VAL_LOG_GAIN_4_SHIFT)) & XCVR_RX_DIG_AGC_IDX4_GAIN_VAL_LOG_GAIN_4_MASK)

#define XCVR_RX_DIG_AGC_IDX4_GAIN_VAL_MAG_THR_HI_4_MASK (0x1FFC00U)
#define XCVR_RX_DIG_AGC_IDX4_GAIN_VAL_MAG_THR_HI_4_SHIFT (10U)
#define XCVR_RX_DIG_AGC_IDX4_GAIN_VAL_MAG_THR_HI_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX4_GAIN_VAL_MAG_THR_HI_4_SHIFT)) & XCVR_RX_DIG_AGC_IDX4_GAIN_VAL_MAG_THR_HI_4_MASK)

#define XCVR_RX_DIG_AGC_IDX4_GAIN_VAL_MAG_THR_4_MASK (0xFFE00000U)
#define XCVR_RX_DIG_AGC_IDX4_GAIN_VAL_MAG_THR_4_SHIFT (21U)
#define XCVR_RX_DIG_AGC_IDX4_GAIN_VAL_MAG_THR_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX4_GAIN_VAL_MAG_THR_4_SHIFT)) & XCVR_RX_DIG_AGC_IDX4_GAIN_VAL_MAG_THR_4_MASK)
/*! @} */

/*! @name AGC_IDX3_GAIN_VAL - AGC_IDX3_GAIN_VAL */
/*! @{ */

#define XCVR_RX_DIG_AGC_IDX3_GAIN_VAL_LOG_GAIN_3_MASK (0x3FFU)
#define XCVR_RX_DIG_AGC_IDX3_GAIN_VAL_LOG_GAIN_3_SHIFT (0U)
/*! LOG_GAIN_3 - LOG_GAIN_3
 */
#define XCVR_RX_DIG_AGC_IDX3_GAIN_VAL_LOG_GAIN_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX3_GAIN_VAL_LOG_GAIN_3_SHIFT)) & XCVR_RX_DIG_AGC_IDX3_GAIN_VAL_LOG_GAIN_3_MASK)

#define XCVR_RX_DIG_AGC_IDX3_GAIN_VAL_MAG_THR_HI_3_MASK (0x1FFC00U)
#define XCVR_RX_DIG_AGC_IDX3_GAIN_VAL_MAG_THR_HI_3_SHIFT (10U)
#define XCVR_RX_DIG_AGC_IDX3_GAIN_VAL_MAG_THR_HI_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX3_GAIN_VAL_MAG_THR_HI_3_SHIFT)) & XCVR_RX_DIG_AGC_IDX3_GAIN_VAL_MAG_THR_HI_3_MASK)

#define XCVR_RX_DIG_AGC_IDX3_GAIN_VAL_MAG_THR_3_MASK (0xFFE00000U)
#define XCVR_RX_DIG_AGC_IDX3_GAIN_VAL_MAG_THR_3_SHIFT (21U)
#define XCVR_RX_DIG_AGC_IDX3_GAIN_VAL_MAG_THR_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX3_GAIN_VAL_MAG_THR_3_SHIFT)) & XCVR_RX_DIG_AGC_IDX3_GAIN_VAL_MAG_THR_3_MASK)
/*! @} */

/*! @name AGC_IDX2_GAIN_VAL - AGC_IDX2_GAIN_VAL */
/*! @{ */

#define XCVR_RX_DIG_AGC_IDX2_GAIN_VAL_LOG_GAIN_2_MASK (0x3FFU)
#define XCVR_RX_DIG_AGC_IDX2_GAIN_VAL_LOG_GAIN_2_SHIFT (0U)
/*! LOG_GAIN_2 - LOG_GAIN_2
 */
#define XCVR_RX_DIG_AGC_IDX2_GAIN_VAL_LOG_GAIN_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX2_GAIN_VAL_LOG_GAIN_2_SHIFT)) & XCVR_RX_DIG_AGC_IDX2_GAIN_VAL_LOG_GAIN_2_MASK)

#define XCVR_RX_DIG_AGC_IDX2_GAIN_VAL_MAG_THR_HI_2_MASK (0x1FFC00U)
#define XCVR_RX_DIG_AGC_IDX2_GAIN_VAL_MAG_THR_HI_2_SHIFT (10U)
#define XCVR_RX_DIG_AGC_IDX2_GAIN_VAL_MAG_THR_HI_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX2_GAIN_VAL_MAG_THR_HI_2_SHIFT)) & XCVR_RX_DIG_AGC_IDX2_GAIN_VAL_MAG_THR_HI_2_MASK)

#define XCVR_RX_DIG_AGC_IDX2_GAIN_VAL_MAG_THR_2_MASK (0xFFE00000U)
#define XCVR_RX_DIG_AGC_IDX2_GAIN_VAL_MAG_THR_2_SHIFT (21U)
#define XCVR_RX_DIG_AGC_IDX2_GAIN_VAL_MAG_THR_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX2_GAIN_VAL_MAG_THR_2_SHIFT)) & XCVR_RX_DIG_AGC_IDX2_GAIN_VAL_MAG_THR_2_MASK)
/*! @} */

/*! @name AGC_IDX1_GAIN_VAL - AGC_IDX1_GAIN_VAL */
/*! @{ */

#define XCVR_RX_DIG_AGC_IDX1_GAIN_VAL_LOG_GAIN_1_MASK (0x3FFU)
#define XCVR_RX_DIG_AGC_IDX1_GAIN_VAL_LOG_GAIN_1_SHIFT (0U)
/*! LOG_GAIN_1 - LOG_GAIN_1
 */
#define XCVR_RX_DIG_AGC_IDX1_GAIN_VAL_LOG_GAIN_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX1_GAIN_VAL_LOG_GAIN_1_SHIFT)) & XCVR_RX_DIG_AGC_IDX1_GAIN_VAL_LOG_GAIN_1_MASK)

#define XCVR_RX_DIG_AGC_IDX1_GAIN_VAL_MAG_THR_HI_1_MASK (0x1FFC00U)
#define XCVR_RX_DIG_AGC_IDX1_GAIN_VAL_MAG_THR_HI_1_SHIFT (10U)
#define XCVR_RX_DIG_AGC_IDX1_GAIN_VAL_MAG_THR_HI_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX1_GAIN_VAL_MAG_THR_HI_1_SHIFT)) & XCVR_RX_DIG_AGC_IDX1_GAIN_VAL_MAG_THR_HI_1_MASK)

#define XCVR_RX_DIG_AGC_IDX1_GAIN_VAL_MAG_THR_1_MASK (0xFFE00000U)
#define XCVR_RX_DIG_AGC_IDX1_GAIN_VAL_MAG_THR_1_SHIFT (21U)
#define XCVR_RX_DIG_AGC_IDX1_GAIN_VAL_MAG_THR_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX1_GAIN_VAL_MAG_THR_1_SHIFT)) & XCVR_RX_DIG_AGC_IDX1_GAIN_VAL_MAG_THR_1_MASK)
/*! @} */

/*! @name AGC_IDX0_GAIN_VAL - AGC_IDX0_GAIN_VAL */
/*! @{ */

#define XCVR_RX_DIG_AGC_IDX0_GAIN_VAL_LOG_GAIN_0_MASK (0x3FFU)
#define XCVR_RX_DIG_AGC_IDX0_GAIN_VAL_LOG_GAIN_0_SHIFT (0U)
/*! LOG_GAIN_0 - LOG_GAIN_0
 */
#define XCVR_RX_DIG_AGC_IDX0_GAIN_VAL_LOG_GAIN_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX0_GAIN_VAL_LOG_GAIN_0_SHIFT)) & XCVR_RX_DIG_AGC_IDX0_GAIN_VAL_LOG_GAIN_0_MASK)

#define XCVR_RX_DIG_AGC_IDX0_GAIN_VAL_MAG_THR_HI_0_MASK (0x1FFC00U)
#define XCVR_RX_DIG_AGC_IDX0_GAIN_VAL_MAG_THR_HI_0_SHIFT (10U)
#define XCVR_RX_DIG_AGC_IDX0_GAIN_VAL_MAG_THR_HI_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX0_GAIN_VAL_MAG_THR_HI_0_SHIFT)) & XCVR_RX_DIG_AGC_IDX0_GAIN_VAL_MAG_THR_HI_0_MASK)

#define XCVR_RX_DIG_AGC_IDX0_GAIN_VAL_MAG_THR_0_MASK (0xFFE00000U)
#define XCVR_RX_DIG_AGC_IDX0_GAIN_VAL_MAG_THR_0_SHIFT (21U)
#define XCVR_RX_DIG_AGC_IDX0_GAIN_VAL_MAG_THR_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX0_GAIN_VAL_MAG_THR_0_SHIFT)) & XCVR_RX_DIG_AGC_IDX0_GAIN_VAL_MAG_THR_0_MASK)
/*! @} */

/*! @name AGC_THR_FAST - AGC Fast Mode Threshold */
/*! @{ */

#define XCVR_RX_DIG_AGC_THR_FAST_STEP_UP_THR_FAST_MASK (0x1FFU)
#define XCVR_RX_DIG_AGC_THR_FAST_STEP_UP_THR_FAST_SHIFT (0U)
/*! STEP_UP_THR_FAST - STEP_UP_THR_FAST
 */
#define XCVR_RX_DIG_AGC_THR_FAST_STEP_UP_THR_FAST(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_THR_FAST_STEP_UP_THR_FAST_SHIFT)) & XCVR_RX_DIG_AGC_THR_FAST_STEP_UP_THR_FAST_MASK)

#define XCVR_RX_DIG_AGC_THR_FAST_STEP_DOWN_THR_FAST_MASK (0x1FF0000U)
#define XCVR_RX_DIG_AGC_THR_FAST_STEP_DOWN_THR_FAST_SHIFT (16U)
/*! STEP_DOWN_THR_FAST - STEP_DOWN_THR_FAST
 */
#define XCVR_RX_DIG_AGC_THR_FAST_STEP_DOWN_THR_FAST(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_THR_FAST_STEP_DOWN_THR_FAST_SHIFT)) & XCVR_RX_DIG_AGC_THR_FAST_STEP_DOWN_THR_FAST_MASK)
/*! @} */

/*! @name AGC_THR_FAST_DRS - AGC Fast Mode Threshold DRS */
/*! @{ */

#define XCVR_RX_DIG_AGC_THR_FAST_DRS_STEP_UP_THR_FAST_MASK (0x1FFU)
#define XCVR_RX_DIG_AGC_THR_FAST_DRS_STEP_UP_THR_FAST_SHIFT (0U)
/*! STEP_UP_THR_FAST - STEP_UP_THR_FAST
 */
#define XCVR_RX_DIG_AGC_THR_FAST_DRS_STEP_UP_THR_FAST(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_THR_FAST_DRS_STEP_UP_THR_FAST_SHIFT)) & XCVR_RX_DIG_AGC_THR_FAST_DRS_STEP_UP_THR_FAST_MASK)

#define XCVR_RX_DIG_AGC_THR_FAST_DRS_STEP_DOWN_THR_FAST_MASK (0x1FF0000U)
#define XCVR_RX_DIG_AGC_THR_FAST_DRS_STEP_DOWN_THR_FAST_SHIFT (16U)
/*! STEP_DOWN_THR_FAST - STEP_DOWN_THR_FAST
 */
#define XCVR_RX_DIG_AGC_THR_FAST_DRS_STEP_DOWN_THR_FAST(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_THR_FAST_DRS_STEP_DOWN_THR_FAST_SHIFT)) & XCVR_RX_DIG_AGC_THR_FAST_DRS_STEP_DOWN_THR_FAST_MASK)
/*! @} */

/*! @name AGC_IDX11_THR - AGC IDX11 Slow Mode Threshold */
/*! @{ */

#define XCVR_RX_DIG_AGC_IDX11_THR_STEP_DOWN_THR_11_MASK (0x1FF0000U)
#define XCVR_RX_DIG_AGC_IDX11_THR_STEP_DOWN_THR_11_SHIFT (16U)
/*! STEP_DOWN_THR_11 - STEP_DOWN_THR_11
 */
#define XCVR_RX_DIG_AGC_IDX11_THR_STEP_DOWN_THR_11(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX11_THR_STEP_DOWN_THR_11_SHIFT)) & XCVR_RX_DIG_AGC_IDX11_THR_STEP_DOWN_THR_11_MASK)

#define XCVR_RX_DIG_AGC_IDX11_THR_STEP_DOWN_THR_11_DRS_OFS_MASK (0xFE000000U)
#define XCVR_RX_DIG_AGC_IDX11_THR_STEP_DOWN_THR_11_DRS_OFS_SHIFT (25U)
/*! STEP_DOWN_THR_11_DRS_OFS - STEP_DOWN_THR_11 DRS Offset
 */
#define XCVR_RX_DIG_AGC_IDX11_THR_STEP_DOWN_THR_11_DRS_OFS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX11_THR_STEP_DOWN_THR_11_DRS_OFS_SHIFT)) & XCVR_RX_DIG_AGC_IDX11_THR_STEP_DOWN_THR_11_DRS_OFS_MASK)
/*! @} */

/*! @name AGC_IDX10_THR - AGC IDX10 Slow Mode Threshold */
/*! @{ */

#define XCVR_RX_DIG_AGC_IDX10_THR_STEP_UP_THR_10_MASK (0x1FFU)
#define XCVR_RX_DIG_AGC_IDX10_THR_STEP_UP_THR_10_SHIFT (0U)
/*! STEP_UP_THR_10 - STEP_UP_THR_10
 */
#define XCVR_RX_DIG_AGC_IDX10_THR_STEP_UP_THR_10(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX10_THR_STEP_UP_THR_10_SHIFT)) & XCVR_RX_DIG_AGC_IDX10_THR_STEP_UP_THR_10_MASK)

#define XCVR_RX_DIG_AGC_IDX10_THR_STEP_DOWN_THR_10_MASK (0x1FF0000U)
#define XCVR_RX_DIG_AGC_IDX10_THR_STEP_DOWN_THR_10_SHIFT (16U)
/*! STEP_DOWN_THR_10 - STEP_DOWN_THR_10
 */
#define XCVR_RX_DIG_AGC_IDX10_THR_STEP_DOWN_THR_10(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX10_THR_STEP_DOWN_THR_10_SHIFT)) & XCVR_RX_DIG_AGC_IDX10_THR_STEP_DOWN_THR_10_MASK)

#define XCVR_RX_DIG_AGC_IDX10_THR_STEP_DOWN_THR_10_DRS_OFS_MASK (0xFE000000U)
#define XCVR_RX_DIG_AGC_IDX10_THR_STEP_DOWN_THR_10_DRS_OFS_SHIFT (25U)
/*! STEP_DOWN_THR_10_DRS_OFS - STEP_DOWN_THR_10 DRS Offset
 */
#define XCVR_RX_DIG_AGC_IDX10_THR_STEP_DOWN_THR_10_DRS_OFS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX10_THR_STEP_DOWN_THR_10_DRS_OFS_SHIFT)) & XCVR_RX_DIG_AGC_IDX10_THR_STEP_DOWN_THR_10_DRS_OFS_MASK)
/*! @} */

/*! @name AGC_IDX9_THR - AGC IDX9 Slow Mode Threshold */
/*! @{ */

#define XCVR_RX_DIG_AGC_IDX9_THR_STEP_UP_THR_9_MASK (0x1FFU)
#define XCVR_RX_DIG_AGC_IDX9_THR_STEP_UP_THR_9_SHIFT (0U)
/*! STEP_UP_THR_9 - STEP_UP_THR_9
 */
#define XCVR_RX_DIG_AGC_IDX9_THR_STEP_UP_THR_9(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX9_THR_STEP_UP_THR_9_SHIFT)) & XCVR_RX_DIG_AGC_IDX9_THR_STEP_UP_THR_9_MASK)

#define XCVR_RX_DIG_AGC_IDX9_THR_STEP_DOWN_THR_9_MASK (0x1FF0000U)
#define XCVR_RX_DIG_AGC_IDX9_THR_STEP_DOWN_THR_9_SHIFT (16U)
/*! STEP_DOWN_THR_9 - STEP_DOWN_THR_9
 */
#define XCVR_RX_DIG_AGC_IDX9_THR_STEP_DOWN_THR_9(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX9_THR_STEP_DOWN_THR_9_SHIFT)) & XCVR_RX_DIG_AGC_IDX9_THR_STEP_DOWN_THR_9_MASK)

#define XCVR_RX_DIG_AGC_IDX9_THR_STEP_DOWN_THR_9_DRS_OFS_MASK (0xFE000000U)
#define XCVR_RX_DIG_AGC_IDX9_THR_STEP_DOWN_THR_9_DRS_OFS_SHIFT (25U)
/*! STEP_DOWN_THR_9_DRS_OFS - STEP_DOWN_THR_9 DRS Offset
 */
#define XCVR_RX_DIG_AGC_IDX9_THR_STEP_DOWN_THR_9_DRS_OFS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX9_THR_STEP_DOWN_THR_9_DRS_OFS_SHIFT)) & XCVR_RX_DIG_AGC_IDX9_THR_STEP_DOWN_THR_9_DRS_OFS_MASK)
/*! @} */

/*! @name AGC_IDX8_THR - AGC IDX8 Slow Mode Threshold */
/*! @{ */

#define XCVR_RX_DIG_AGC_IDX8_THR_STEP_UP_THR_8_MASK (0x1FFU)
#define XCVR_RX_DIG_AGC_IDX8_THR_STEP_UP_THR_8_SHIFT (0U)
/*! STEP_UP_THR_8 - STEP_UP_THR_8
 */
#define XCVR_RX_DIG_AGC_IDX8_THR_STEP_UP_THR_8(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX8_THR_STEP_UP_THR_8_SHIFT)) & XCVR_RX_DIG_AGC_IDX8_THR_STEP_UP_THR_8_MASK)

#define XCVR_RX_DIG_AGC_IDX8_THR_STEP_DOWN_THR_8_MASK (0x1FF0000U)
#define XCVR_RX_DIG_AGC_IDX8_THR_STEP_DOWN_THR_8_SHIFT (16U)
/*! STEP_DOWN_THR_8 - STEP_DOWN_THR_8
 */
#define XCVR_RX_DIG_AGC_IDX8_THR_STEP_DOWN_THR_8(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX8_THR_STEP_DOWN_THR_8_SHIFT)) & XCVR_RX_DIG_AGC_IDX8_THR_STEP_DOWN_THR_8_MASK)

#define XCVR_RX_DIG_AGC_IDX8_THR_STEP_DOWN_THR_8_DRS_OFS_MASK (0xFE000000U)
#define XCVR_RX_DIG_AGC_IDX8_THR_STEP_DOWN_THR_8_DRS_OFS_SHIFT (25U)
/*! STEP_DOWN_THR_8_DRS_OFS - STEP_DOWN_THR_8 DRS Offset
 */
#define XCVR_RX_DIG_AGC_IDX8_THR_STEP_DOWN_THR_8_DRS_OFS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX8_THR_STEP_DOWN_THR_8_DRS_OFS_SHIFT)) & XCVR_RX_DIG_AGC_IDX8_THR_STEP_DOWN_THR_8_DRS_OFS_MASK)
/*! @} */

/*! @name AGC_IDX7_THR - AGC IDX7 Slow Mode Threshold */
/*! @{ */

#define XCVR_RX_DIG_AGC_IDX7_THR_STEP_UP_THR_7_MASK (0x1FFU)
#define XCVR_RX_DIG_AGC_IDX7_THR_STEP_UP_THR_7_SHIFT (0U)
/*! STEP_UP_THR_7 - STEP_UP_THR_7
 */
#define XCVR_RX_DIG_AGC_IDX7_THR_STEP_UP_THR_7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX7_THR_STEP_UP_THR_7_SHIFT)) & XCVR_RX_DIG_AGC_IDX7_THR_STEP_UP_THR_7_MASK)

#define XCVR_RX_DIG_AGC_IDX7_THR_STEP_DOWN_THR_7_MASK (0x1FF0000U)
#define XCVR_RX_DIG_AGC_IDX7_THR_STEP_DOWN_THR_7_SHIFT (16U)
/*! STEP_DOWN_THR_7 - STEP_DOWN_THR_7
 */
#define XCVR_RX_DIG_AGC_IDX7_THR_STEP_DOWN_THR_7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX7_THR_STEP_DOWN_THR_7_SHIFT)) & XCVR_RX_DIG_AGC_IDX7_THR_STEP_DOWN_THR_7_MASK)

#define XCVR_RX_DIG_AGC_IDX7_THR_STEP_DOWN_THR_7_DRS_OFS_MASK (0xFE000000U)
#define XCVR_RX_DIG_AGC_IDX7_THR_STEP_DOWN_THR_7_DRS_OFS_SHIFT (25U)
/*! STEP_DOWN_THR_7_DRS_OFS - STEP_DOWN_THR_7 DRS Offset
 */
#define XCVR_RX_DIG_AGC_IDX7_THR_STEP_DOWN_THR_7_DRS_OFS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX7_THR_STEP_DOWN_THR_7_DRS_OFS_SHIFT)) & XCVR_RX_DIG_AGC_IDX7_THR_STEP_DOWN_THR_7_DRS_OFS_MASK)
/*! @} */

/*! @name AGC_IDX6_THR - AGC IDX6 Slow Mode Threshold */
/*! @{ */

#define XCVR_RX_DIG_AGC_IDX6_THR_STEP_UP_THR_6_MASK (0x1FFU)
#define XCVR_RX_DIG_AGC_IDX6_THR_STEP_UP_THR_6_SHIFT (0U)
/*! STEP_UP_THR_6 - STEP_UP_THR_6
 */
#define XCVR_RX_DIG_AGC_IDX6_THR_STEP_UP_THR_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX6_THR_STEP_UP_THR_6_SHIFT)) & XCVR_RX_DIG_AGC_IDX6_THR_STEP_UP_THR_6_MASK)

#define XCVR_RX_DIG_AGC_IDX6_THR_STEP_DOWN_THR_6_MASK (0x1FF0000U)
#define XCVR_RX_DIG_AGC_IDX6_THR_STEP_DOWN_THR_6_SHIFT (16U)
/*! STEP_DOWN_THR_6 - STEP_DOWN_THR_6
 */
#define XCVR_RX_DIG_AGC_IDX6_THR_STEP_DOWN_THR_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX6_THR_STEP_DOWN_THR_6_SHIFT)) & XCVR_RX_DIG_AGC_IDX6_THR_STEP_DOWN_THR_6_MASK)

#define XCVR_RX_DIG_AGC_IDX6_THR_STEP_DOWN_THR_6_DRS_OFS_MASK (0xFE000000U)
#define XCVR_RX_DIG_AGC_IDX6_THR_STEP_DOWN_THR_6_DRS_OFS_SHIFT (25U)
/*! STEP_DOWN_THR_6_DRS_OFS - STEP_DOWN_THR_6 DRS Offset
 */
#define XCVR_RX_DIG_AGC_IDX6_THR_STEP_DOWN_THR_6_DRS_OFS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX6_THR_STEP_DOWN_THR_6_DRS_OFS_SHIFT)) & XCVR_RX_DIG_AGC_IDX6_THR_STEP_DOWN_THR_6_DRS_OFS_MASK)
/*! @} */

/*! @name AGC_IDX5_THR - AGC IDX5 Slow Mode Threshold */
/*! @{ */

#define XCVR_RX_DIG_AGC_IDX5_THR_STEP_UP_THR_5_MASK (0x1FFU)
#define XCVR_RX_DIG_AGC_IDX5_THR_STEP_UP_THR_5_SHIFT (0U)
/*! STEP_UP_THR_5 - STEP_UP_THR_5
 */
#define XCVR_RX_DIG_AGC_IDX5_THR_STEP_UP_THR_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX5_THR_STEP_UP_THR_5_SHIFT)) & XCVR_RX_DIG_AGC_IDX5_THR_STEP_UP_THR_5_MASK)

#define XCVR_RX_DIG_AGC_IDX5_THR_STEP_DOWN_THR_5_MASK (0x1FF0000U)
#define XCVR_RX_DIG_AGC_IDX5_THR_STEP_DOWN_THR_5_SHIFT (16U)
/*! STEP_DOWN_THR_5 - STEP_DOWN_THR_5
 */
#define XCVR_RX_DIG_AGC_IDX5_THR_STEP_DOWN_THR_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX5_THR_STEP_DOWN_THR_5_SHIFT)) & XCVR_RX_DIG_AGC_IDX5_THR_STEP_DOWN_THR_5_MASK)

#define XCVR_RX_DIG_AGC_IDX5_THR_STEP_DOWN_THR_5_DRS_OFS_MASK (0xFE000000U)
#define XCVR_RX_DIG_AGC_IDX5_THR_STEP_DOWN_THR_5_DRS_OFS_SHIFT (25U)
/*! STEP_DOWN_THR_5_DRS_OFS - STEP_DOWN_THR_5 DRS Offset
 */
#define XCVR_RX_DIG_AGC_IDX5_THR_STEP_DOWN_THR_5_DRS_OFS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX5_THR_STEP_DOWN_THR_5_DRS_OFS_SHIFT)) & XCVR_RX_DIG_AGC_IDX5_THR_STEP_DOWN_THR_5_DRS_OFS_MASK)
/*! @} */

/*! @name AGC_IDX4_THR - AGC IDX4 Slow Mode Threshold */
/*! @{ */

#define XCVR_RX_DIG_AGC_IDX4_THR_STEP_UP_THR_4_MASK (0x1FFU)
#define XCVR_RX_DIG_AGC_IDX4_THR_STEP_UP_THR_4_SHIFT (0U)
/*! STEP_UP_THR_4 - STEP_UP_THR_4
 */
#define XCVR_RX_DIG_AGC_IDX4_THR_STEP_UP_THR_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX4_THR_STEP_UP_THR_4_SHIFT)) & XCVR_RX_DIG_AGC_IDX4_THR_STEP_UP_THR_4_MASK)

#define XCVR_RX_DIG_AGC_IDX4_THR_STEP_DOWN_THR_4_MASK (0x1FF0000U)
#define XCVR_RX_DIG_AGC_IDX4_THR_STEP_DOWN_THR_4_SHIFT (16U)
/*! STEP_DOWN_THR_4 - STEP_DOWN_THR_4
 */
#define XCVR_RX_DIG_AGC_IDX4_THR_STEP_DOWN_THR_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX4_THR_STEP_DOWN_THR_4_SHIFT)) & XCVR_RX_DIG_AGC_IDX4_THR_STEP_DOWN_THR_4_MASK)

#define XCVR_RX_DIG_AGC_IDX4_THR_STEP_DOWN_THR_4_DRS_OFS_MASK (0xFE000000U)
#define XCVR_RX_DIG_AGC_IDX4_THR_STEP_DOWN_THR_4_DRS_OFS_SHIFT (25U)
/*! STEP_DOWN_THR_4_DRS_OFS - STEP_DOWN_THR_4 DRS Offset
 */
#define XCVR_RX_DIG_AGC_IDX4_THR_STEP_DOWN_THR_4_DRS_OFS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX4_THR_STEP_DOWN_THR_4_DRS_OFS_SHIFT)) & XCVR_RX_DIG_AGC_IDX4_THR_STEP_DOWN_THR_4_DRS_OFS_MASK)
/*! @} */

/*! @name AGC_IDX3_THR - AGC IDX3 Slow Mode Threshold */
/*! @{ */

#define XCVR_RX_DIG_AGC_IDX3_THR_STEP_UP_THR_3_MASK (0x1FFU)
#define XCVR_RX_DIG_AGC_IDX3_THR_STEP_UP_THR_3_SHIFT (0U)
/*! STEP_UP_THR_3 - STEP_UP_THR_3
 */
#define XCVR_RX_DIG_AGC_IDX3_THR_STEP_UP_THR_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX3_THR_STEP_UP_THR_3_SHIFT)) & XCVR_RX_DIG_AGC_IDX3_THR_STEP_UP_THR_3_MASK)

#define XCVR_RX_DIG_AGC_IDX3_THR_STEP_DOWN_THR_3_MASK (0x1FF0000U)
#define XCVR_RX_DIG_AGC_IDX3_THR_STEP_DOWN_THR_3_SHIFT (16U)
/*! STEP_DOWN_THR_3 - STEP_DOWN_THR_3
 */
#define XCVR_RX_DIG_AGC_IDX3_THR_STEP_DOWN_THR_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX3_THR_STEP_DOWN_THR_3_SHIFT)) & XCVR_RX_DIG_AGC_IDX3_THR_STEP_DOWN_THR_3_MASK)

#define XCVR_RX_DIG_AGC_IDX3_THR_STEP_DOWN_THR_3_DRS_OFS_MASK (0xFE000000U)
#define XCVR_RX_DIG_AGC_IDX3_THR_STEP_DOWN_THR_3_DRS_OFS_SHIFT (25U)
/*! STEP_DOWN_THR_3_DRS_OFS - STEP_DOWN_THR_3 DRS Offset
 */
#define XCVR_RX_DIG_AGC_IDX3_THR_STEP_DOWN_THR_3_DRS_OFS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX3_THR_STEP_DOWN_THR_3_DRS_OFS_SHIFT)) & XCVR_RX_DIG_AGC_IDX3_THR_STEP_DOWN_THR_3_DRS_OFS_MASK)
/*! @} */

/*! @name AGC_IDX2_THR - AGC IDX2 Slow Mode Threshold */
/*! @{ */

#define XCVR_RX_DIG_AGC_IDX2_THR_STEP_UP_THR_2_MASK (0x1FFU)
#define XCVR_RX_DIG_AGC_IDX2_THR_STEP_UP_THR_2_SHIFT (0U)
/*! STEP_UP_THR_2 - STEP_UP_THR_2
 */
#define XCVR_RX_DIG_AGC_IDX2_THR_STEP_UP_THR_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX2_THR_STEP_UP_THR_2_SHIFT)) & XCVR_RX_DIG_AGC_IDX2_THR_STEP_UP_THR_2_MASK)

#define XCVR_RX_DIG_AGC_IDX2_THR_STEP_DOWN_THR_2_MASK (0x1FF0000U)
#define XCVR_RX_DIG_AGC_IDX2_THR_STEP_DOWN_THR_2_SHIFT (16U)
/*! STEP_DOWN_THR_2 - STEP_DOWN_THR_2
 */
#define XCVR_RX_DIG_AGC_IDX2_THR_STEP_DOWN_THR_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX2_THR_STEP_DOWN_THR_2_SHIFT)) & XCVR_RX_DIG_AGC_IDX2_THR_STEP_DOWN_THR_2_MASK)

#define XCVR_RX_DIG_AGC_IDX2_THR_STEP_DOWN_THR_2_DRS_OFS_MASK (0xFE000000U)
#define XCVR_RX_DIG_AGC_IDX2_THR_STEP_DOWN_THR_2_DRS_OFS_SHIFT (25U)
/*! STEP_DOWN_THR_2_DRS_OFS - STEP_DOWN_THR_2 DRS Offset
 */
#define XCVR_RX_DIG_AGC_IDX2_THR_STEP_DOWN_THR_2_DRS_OFS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX2_THR_STEP_DOWN_THR_2_DRS_OFS_SHIFT)) & XCVR_RX_DIG_AGC_IDX2_THR_STEP_DOWN_THR_2_DRS_OFS_MASK)
/*! @} */

/*! @name AGC_IDX1_THR - AGC IDX1 Slow Mode Threshold */
/*! @{ */

#define XCVR_RX_DIG_AGC_IDX1_THR_STEP_UP_THR_1_MASK (0x1FFU)
#define XCVR_RX_DIG_AGC_IDX1_THR_STEP_UP_THR_1_SHIFT (0U)
/*! STEP_UP_THR_1 - STEP_UP_THR_1
 */
#define XCVR_RX_DIG_AGC_IDX1_THR_STEP_UP_THR_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX1_THR_STEP_UP_THR_1_SHIFT)) & XCVR_RX_DIG_AGC_IDX1_THR_STEP_UP_THR_1_MASK)

#define XCVR_RX_DIG_AGC_IDX1_THR_STEP_DOWN_THR_1_MASK (0x1FF0000U)
#define XCVR_RX_DIG_AGC_IDX1_THR_STEP_DOWN_THR_1_SHIFT (16U)
/*! STEP_DOWN_THR_1 - STEP_DOWN_THR_1
 */
#define XCVR_RX_DIG_AGC_IDX1_THR_STEP_DOWN_THR_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX1_THR_STEP_DOWN_THR_1_SHIFT)) & XCVR_RX_DIG_AGC_IDX1_THR_STEP_DOWN_THR_1_MASK)

#define XCVR_RX_DIG_AGC_IDX1_THR_STEP_DOWN_THR_1_DRS_OFS_MASK (0xFE000000U)
#define XCVR_RX_DIG_AGC_IDX1_THR_STEP_DOWN_THR_1_DRS_OFS_SHIFT (25U)
/*! STEP_DOWN_THR_1_DRS_OFS - STEP_DOWN_THR_1 DRS Offset
 */
#define XCVR_RX_DIG_AGC_IDX1_THR_STEP_DOWN_THR_1_DRS_OFS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX1_THR_STEP_DOWN_THR_1_DRS_OFS_SHIFT)) & XCVR_RX_DIG_AGC_IDX1_THR_STEP_DOWN_THR_1_DRS_OFS_MASK)
/*! @} */

/*! @name AGC_IDX0_THR - AGC IDX0 Slow Mode Threshold */
/*! @{ */

#define XCVR_RX_DIG_AGC_IDX0_THR_STEP_UP_THR_0_MASK (0x1FFU)
#define XCVR_RX_DIG_AGC_IDX0_THR_STEP_UP_THR_0_SHIFT (0U)
/*! STEP_UP_THR_0 - STEP_UP_THR_0
 */
#define XCVR_RX_DIG_AGC_IDX0_THR_STEP_UP_THR_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_IDX0_THR_STEP_UP_THR_0_SHIFT)) & XCVR_RX_DIG_AGC_IDX0_THR_STEP_UP_THR_0_MASK)
/*! @} */

/*! @name AGC_THR_MIS - AGC Miscellaneous Thresholds */
/*! @{ */

#define XCVR_RX_DIG_AGC_THR_MIS_DELTA_SLOW_THR_MASK (0x1FFU)
#define XCVR_RX_DIG_AGC_THR_MIS_DELTA_SLOW_THR_SHIFT (0U)
/*! DELTA_SLOW_THR - STEP_UP_THR_VLG2
 */
#define XCVR_RX_DIG_AGC_THR_MIS_DELTA_SLOW_THR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_THR_MIS_DELTA_SLOW_THR_SHIFT)) & XCVR_RX_DIG_AGC_THR_MIS_DELTA_SLOW_THR_MASK)

#define XCVR_RX_DIG_AGC_THR_MIS_HOLD_MARGIN_THR_MASK (0x1FF0000U)
#define XCVR_RX_DIG_AGC_THR_MIS_HOLD_MARGIN_THR_SHIFT (16U)
/*! HOLD_MARGIN_THR - STEP_UP_THR_VLG2large
 */
#define XCVR_RX_DIG_AGC_THR_MIS_HOLD_MARGIN_THR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_THR_MIS_HOLD_MARGIN_THR_SHIFT)) & XCVR_RX_DIG_AGC_THR_MIS_HOLD_MARGIN_THR_MASK)
/*! @} */

/*! @name AGC_OVRD - AGC Override Control */
/*! @{ */

#define XCVR_RX_DIG_AGC_OVRD_AGC_GAIN_OVRD_MASK  (0xFFFFU)
#define XCVR_RX_DIG_AGC_OVRD_AGC_GAIN_OVRD_SHIFT (0U)
#define XCVR_RX_DIG_AGC_OVRD_AGC_GAIN_OVRD(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_OVRD_AGC_GAIN_OVRD_SHIFT)) & XCVR_RX_DIG_AGC_OVRD_AGC_GAIN_OVRD_MASK)

#define XCVR_RX_DIG_AGC_OVRD_AGC_GAIN_OVRD_EN_MASK (0x10000U)
#define XCVR_RX_DIG_AGC_OVRD_AGC_GAIN_OVRD_EN_SHIFT (16U)
#define XCVR_RX_DIG_AGC_OVRD_AGC_GAIN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_OVRD_AGC_GAIN_OVRD_EN_SHIFT)) & XCVR_RX_DIG_AGC_OVRD_AGC_GAIN_OVRD_EN_MASK)

#define XCVR_RX_DIG_AGC_OVRD_AGC_GAIN_IDX_OVRD_MASK (0x1E0000U)
#define XCVR_RX_DIG_AGC_OVRD_AGC_GAIN_IDX_OVRD_SHIFT (17U)
#define XCVR_RX_DIG_AGC_OVRD_AGC_GAIN_IDX_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_OVRD_AGC_GAIN_IDX_OVRD_SHIFT)) & XCVR_RX_DIG_AGC_OVRD_AGC_GAIN_IDX_OVRD_MASK)

#define XCVR_RX_DIG_AGC_OVRD_AGC_GAIN_IDX_OVRD_EN_MASK (0x200000U)
#define XCVR_RX_DIG_AGC_OVRD_AGC_GAIN_IDX_OVRD_EN_SHIFT (21U)
#define XCVR_RX_DIG_AGC_OVRD_AGC_GAIN_IDX_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_OVRD_AGC_GAIN_IDX_OVRD_EN_SHIFT)) & XCVR_RX_DIG_AGC_OVRD_AGC_GAIN_IDX_OVRD_EN_MASK)

#define XCVR_RX_DIG_AGC_OVRD_AGC_PHY_HOLD_OVRD_MASK (0x400000U)
#define XCVR_RX_DIG_AGC_OVRD_AGC_PHY_HOLD_OVRD_SHIFT (22U)
#define XCVR_RX_DIG_AGC_OVRD_AGC_PHY_HOLD_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_OVRD_AGC_PHY_HOLD_OVRD_SHIFT)) & XCVR_RX_DIG_AGC_OVRD_AGC_PHY_HOLD_OVRD_MASK)

#define XCVR_RX_DIG_AGC_OVRD_AGC_PHY_HOLD_OVRD_EN_MASK (0x800000U)
#define XCVR_RX_DIG_AGC_OVRD_AGC_PHY_HOLD_OVRD_EN_SHIFT (23U)
#define XCVR_RX_DIG_AGC_OVRD_AGC_PHY_HOLD_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_OVRD_AGC_PHY_HOLD_OVRD_EN_SHIFT)) & XCVR_RX_DIG_AGC_OVRD_AGC_PHY_HOLD_OVRD_EN_MASK)

#define XCVR_RX_DIG_AGC_OVRD_AGC_PHY_FREEZE_OVRD_MASK (0x1000000U)
#define XCVR_RX_DIG_AGC_OVRD_AGC_PHY_FREEZE_OVRD_SHIFT (24U)
#define XCVR_RX_DIG_AGC_OVRD_AGC_PHY_FREEZE_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_OVRD_AGC_PHY_FREEZE_OVRD_SHIFT)) & XCVR_RX_DIG_AGC_OVRD_AGC_PHY_FREEZE_OVRD_MASK)

#define XCVR_RX_DIG_AGC_OVRD_AGC_PHY_FREEZE_OVRD_EN_MASK (0x2000000U)
#define XCVR_RX_DIG_AGC_OVRD_AGC_PHY_FREEZE_OVRD_EN_SHIFT (25U)
#define XCVR_RX_DIG_AGC_OVRD_AGC_PHY_FREEZE_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_OVRD_AGC_PHY_FREEZE_OVRD_EN_SHIFT)) & XCVR_RX_DIG_AGC_OVRD_AGC_PHY_FREEZE_OVRD_EN_MASK)
/*! @} */

/*! @name DC_RESID_CTRL - DC Residual Control */
/*! @{ */

#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN_MASK (0x7FU)
#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN_SHIFT (0U)
/*! DC_RESID_NWIN - DC Residual NWIN
 */
#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN_SHIFT)) & XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN_MASK)

#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ITER_FREEZE_MASK (0xF00U)
#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ITER_FREEZE_SHIFT (8U)
/*! DC_RESID_ITER_FREEZE - DC Residual Iteration Freeze
 */
#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ITER_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ITER_FREEZE_SHIFT)) & XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ITER_FREEZE_MASK)

#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ALPHA_MASK (0x7000U)
#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ALPHA_SHIFT (12U)
/*! DC_RESID_ALPHA - DC Residual Alpha
 *  0b000..Update factor is 1
 *  0b001..Update factor is 1/2
 *  0b010..Update factor is 1/4 + 1/8
 *  0b011..Update factor is 1/4
 *  0b100..Update factor is 1/8 + 16
 *  0b101..Update factor is 1/8
 *  0b110..Update factor is 1/16 + 1/32
 *  0b111..Update factor is 1/16
 */
#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ALPHA_SHIFT)) & XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ALPHA_MASK)

#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_GS_EN_MASK (0x8000U)
#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_GS_EN_SHIFT (15U)
/*! DC_RESID_GS_EN - DC Residual Gearshift Enable
 *  0b0..Gearshifting disabled
 *  0b1..Gearshifting enabled
 */
#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_GS_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_GS_EN_SHIFT)) & XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_GS_EN_MASK)

#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY_MASK (0x70000U)
#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY_SHIFT (16U)
/*! DC_RESID_DLY - DC Residual Delay
 */
#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY_SHIFT)) & XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY_MASK)

#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_SECOND_RUN_EN_MASK (0x80000U)
#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_SECOND_RUN_EN_SHIFT (19U)
/*! DC_RESID_SECOND_RUN_EN - DC Residual Second Run Enable
 *  0b0..Second Run disabled
 *  0b1..Second Run enabled
 */
#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_SECOND_RUN_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_SECOND_RUN_EN_SHIFT)) & XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_SECOND_RUN_EN_MASK)

#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_EXT_DC_EN_MASK (0x100000U)
#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_EXT_DC_EN_SHIFT (20U)
/*! DC_RESID_EXT_DC_EN - DC Residual External DC Enable
 *  0b0..External DC disable. The DC Residual activates at a delay specified by DC_RESID_DLY after an AGC gain
 *       change pulse. The DC Residual is initialized with a DC offset of 0.
 *  0b1..External DC enable. The DC residual activates after the DCOC's tracking hold timer expires. The DC
 *       Residual is initialized with the DC estimate from the DCOC tracking estimator.
 */
#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_EXT_DC_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_EXT_DC_EN_SHIFT)) & XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_EXT_DC_EN_MASK)

#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_MIN_AGC_IDX_MASK (0x1F000000U)
#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_MIN_AGC_IDX_SHIFT (24U)
/*! DC_RESID_MIN_AGC_IDX - DC Residual Minimum AGC Table Index
 */
#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_MIN_AGC_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_MIN_AGC_IDX_SHIFT)) & XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_MIN_AGC_IDX_MASK)

#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_GEARSHIFT_MASK (0xE0000000U)
#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_GEARSHIFT_SHIFT (29U)
/*! DC_RESID_GEARSHIFT - DC Residual Gearshift
 */
#define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_GEARSHIFT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_GEARSHIFT_SHIFT)) & XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_GEARSHIFT_MASK)
/*! @} */

/*! @name DC_RESID_CTRL2 - DC Residual Control2 */
/*! @{ */

#define XCVR_RX_DIG_DC_RESID_CTRL2_DC_RESID_NWIN2_MASK (0x1FFU)
#define XCVR_RX_DIG_DC_RESID_CTRL2_DC_RESID_NWIN2_SHIFT (0U)
/*! DC_RESID_NWIN2 - DC Residual NWIN, for Second Run
 */
#define XCVR_RX_DIG_DC_RESID_CTRL2_DC_RESID_NWIN2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_CTRL2_DC_RESID_NWIN2_SHIFT)) & XCVR_RX_DIG_DC_RESID_CTRL2_DC_RESID_NWIN2_MASK)

#define XCVR_RX_DIG_DC_RESID_CTRL2_DC_RESID_PHY_STOP_EN_MASK (0x200U)
#define XCVR_RX_DIG_DC_RESID_CTRL2_DC_RESID_PHY_STOP_EN_SHIFT (9U)
/*! DC_RESID_PHY_STOP_EN - DC Residual PHY Stop Enable
 */
#define XCVR_RX_DIG_DC_RESID_CTRL2_DC_RESID_PHY_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_CTRL2_DC_RESID_PHY_STOP_EN_SHIFT)) & XCVR_RX_DIG_DC_RESID_CTRL2_DC_RESID_PHY_STOP_EN_MASK)

#define XCVR_RX_DIG_DC_RESID_CTRL2_DC_RESID_CC_EN_MASK (0x400U)
#define XCVR_RX_DIG_DC_RESID_CTRL2_DC_RESID_CC_EN_SHIFT (10U)
/*! DC_RESID_CC_EN - DC Residual Continuous Correction Enable
 */
#define XCVR_RX_DIG_DC_RESID_CTRL2_DC_RESID_CC_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_CTRL2_DC_RESID_CC_EN_SHIFT)) & XCVR_RX_DIG_DC_RESID_CTRL2_DC_RESID_CC_EN_MASK)

#define XCVR_RX_DIG_DC_RESID_CTRL2_DC_RESID_SR2_EN_MASK (0x800U)
#define XCVR_RX_DIG_DC_RESID_CTRL2_DC_RESID_SR2_EN_SHIFT (11U)
/*! DC_RESID_SR2_EN - DC Residual Slewrate Enable, for Second Run
 */
#define XCVR_RX_DIG_DC_RESID_CTRL2_DC_RESID_SR2_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_CTRL2_DC_RESID_SR2_EN_SHIFT)) & XCVR_RX_DIG_DC_RESID_CTRL2_DC_RESID_SR2_EN_MASK)

#define XCVR_RX_DIG_DC_RESID_CTRL2_DC_RESID_ALPHA2_MASK (0x7000U)
#define XCVR_RX_DIG_DC_RESID_CTRL2_DC_RESID_ALPHA2_SHIFT (12U)
/*! DC_RESID_ALPHA2 - DC Residual Alpha, for Second Run
 *  0b000..Update factor is 1
 *  0b001..Update factor is 1/2
 *  0b010..Update factor is 1/4 + 1/8
 *  0b011..Update factor is 1/4
 *  0b100..Update factor is 1/8 + 16
 *  0b101..Update factor is 1/8
 *  0b110..Update factor is 1/16 + 1/32
 *  0b111..Update factor is 1/16
 */
#define XCVR_RX_DIG_DC_RESID_CTRL2_DC_RESID_ALPHA2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_CTRL2_DC_RESID_ALPHA2_SHIFT)) & XCVR_RX_DIG_DC_RESID_CTRL2_DC_RESID_ALPHA2_MASK)

#define XCVR_RX_DIG_DC_RESID_CTRL2_DC_RESID_GS2_EN_MASK (0x8000U)
#define XCVR_RX_DIG_DC_RESID_CTRL2_DC_RESID_GS2_EN_SHIFT (15U)
/*! DC_RESID_GS2_EN - DC Residual Gearshift Enable, for Second Run
 *  0b0..Gearshifting disabled for Second Run
 *  0b1..Gearshifting enabled for Second Run
 */
#define XCVR_RX_DIG_DC_RESID_CTRL2_DC_RESID_GS2_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_CTRL2_DC_RESID_GS2_EN_SHIFT)) & XCVR_RX_DIG_DC_RESID_CTRL2_DC_RESID_GS2_EN_MASK)

#define XCVR_RX_DIG_DC_RESID_CTRL2_DC_RESID_ITER_FREEZE2_MASK (0x1F0000U)
#define XCVR_RX_DIG_DC_RESID_CTRL2_DC_RESID_ITER_FREEZE2_SHIFT (16U)
/*! DC_RESID_ITER_FREEZE2 - DC Residual Iteration Freeze, for Second Run
 */
#define XCVR_RX_DIG_DC_RESID_CTRL2_DC_RESID_ITER_FREEZE2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_CTRL2_DC_RESID_ITER_FREEZE2_SHIFT)) & XCVR_RX_DIG_DC_RESID_CTRL2_DC_RESID_ITER_FREEZE2_MASK)

#define XCVR_RX_DIG_DC_RESID_CTRL2_DC_RESID_SLEWRATE2_MASK (0xE00000U)
#define XCVR_RX_DIG_DC_RESID_CTRL2_DC_RESID_SLEWRATE2_SHIFT (21U)
/*! DC_RESID_SLEWRATE2 - DC Residual Slewrate, for Second Run
 */
#define XCVR_RX_DIG_DC_RESID_CTRL2_DC_RESID_SLEWRATE2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_CTRL2_DC_RESID_SLEWRATE2_SHIFT)) & XCVR_RX_DIG_DC_RESID_CTRL2_DC_RESID_SLEWRATE2_MASK)

#define XCVR_RX_DIG_DC_RESID_CTRL2_DC_RESID_MIN_AGC_IDX2_MASK (0x1F000000U)
#define XCVR_RX_DIG_DC_RESID_CTRL2_DC_RESID_MIN_AGC_IDX2_SHIFT (24U)
/*! DC_RESID_MIN_AGC_IDX2 - DC Residual Minimum AGC Table Index, for Second Run
 */
#define XCVR_RX_DIG_DC_RESID_CTRL2_DC_RESID_MIN_AGC_IDX2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_CTRL2_DC_RESID_MIN_AGC_IDX2_SHIFT)) & XCVR_RX_DIG_DC_RESID_CTRL2_DC_RESID_MIN_AGC_IDX2_MASK)

#define XCVR_RX_DIG_DC_RESID_CTRL2_DC_RESID_GEARSHIFT2_MASK (0xE0000000U)
#define XCVR_RX_DIG_DC_RESID_CTRL2_DC_RESID_GEARSHIFT2_SHIFT (29U)
/*! DC_RESID_GEARSHIFT2 - DC Residual Gearshift, for Second Run
 */
#define XCVR_RX_DIG_DC_RESID_CTRL2_DC_RESID_GEARSHIFT2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_CTRL2_DC_RESID_GEARSHIFT2_SHIFT)) & XCVR_RX_DIG_DC_RESID_CTRL2_DC_RESID_GEARSHIFT2_MASK)
/*! @} */

/*! @name DC_RESID_CTRL_DRS - DC Residual Control DataRate1 */
/*! @{ */

#define XCVR_RX_DIG_DC_RESID_CTRL_DRS_DC_RESID_NWIN_MASK (0x7FU)
#define XCVR_RX_DIG_DC_RESID_CTRL_DRS_DC_RESID_NWIN_SHIFT (0U)
/*! DC_RESID_NWIN - DC Residual NWIN
 */
#define XCVR_RX_DIG_DC_RESID_CTRL_DRS_DC_RESID_NWIN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_CTRL_DRS_DC_RESID_NWIN_SHIFT)) & XCVR_RX_DIG_DC_RESID_CTRL_DRS_DC_RESID_NWIN_MASK)

#define XCVR_RX_DIG_DC_RESID_CTRL_DRS_DC_RESID_DLY_MASK (0x70000U)
#define XCVR_RX_DIG_DC_RESID_CTRL_DRS_DC_RESID_DLY_SHIFT (16U)
/*! DC_RESID_DLY - DC Residual Delay
 */
#define XCVR_RX_DIG_DC_RESID_CTRL_DRS_DC_RESID_DLY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_CTRL_DRS_DC_RESID_DLY_SHIFT)) & XCVR_RX_DIG_DC_RESID_CTRL_DRS_DC_RESID_DLY_MASK)

#define XCVR_RX_DIG_DC_RESID_CTRL_DRS_DC_RESID_NWIN2_MASK (0x1FF00000U)
#define XCVR_RX_DIG_DC_RESID_CTRL_DRS_DC_RESID_NWIN2_SHIFT (20U)
/*! DC_RESID_NWIN2 - DC Residual NWIN, for Second Run
 */
#define XCVR_RX_DIG_DC_RESID_CTRL_DRS_DC_RESID_NWIN2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_CTRL_DRS_DC_RESID_NWIN2_SHIFT)) & XCVR_RX_DIG_DC_RESID_CTRL_DRS_DC_RESID_NWIN2_MASK)
/*! @} */

/*! @name DC_RESID_EST - DC Residual Estimate */
/*! @{ */

#define XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_I_MASK (0x1FFFU)
#define XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_I_SHIFT (0U)
/*! DC_RESID_OFFSET_I - DC Residual Offset I
 */
#define XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_I_SHIFT)) & XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_I_MASK)

#define XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_Q_MASK (0x1FFF0000U)
#define XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_Q_SHIFT (16U)
/*! DC_RESID_OFFSET_Q - DC Residual Offset Q
 */
#define XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_Q_SHIFT)) & XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_Q_MASK)
/*! @} */

/*! @name DFT_TONE_ANALYZER0 - DfT tone analyzer */
/*! @{ */

#define XCVR_RX_DIG_DFT_TONE_ANALYZER0_ipr_dft_ana_start_offset_q_MASK (0x1FFU)
#define XCVR_RX_DIG_DFT_TONE_ANALYZER0_ipr_dft_ana_start_offset_q_SHIFT (0U)
/*! ipr_dft_ana_start_offset_q - Q Initial Phase
 */
#define XCVR_RX_DIG_DFT_TONE_ANALYZER0_ipr_dft_ana_start_offset_q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DFT_TONE_ANALYZER0_ipr_dft_ana_start_offset_q_SHIFT)) & XCVR_RX_DIG_DFT_TONE_ANALYZER0_ipr_dft_ana_start_offset_q_MASK)

#define XCVR_RX_DIG_DFT_TONE_ANALYZER0_ipr_dft_ana_start_offset_i_MASK (0x3FE00U)
#define XCVR_RX_DIG_DFT_TONE_ANALYZER0_ipr_dft_ana_start_offset_i_SHIFT (9U)
/*! ipr_dft_ana_start_offset_i - I Initial Phase
 */
#define XCVR_RX_DIG_DFT_TONE_ANALYZER0_ipr_dft_ana_start_offset_i(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DFT_TONE_ANALYZER0_ipr_dft_ana_start_offset_i_SHIFT)) & XCVR_RX_DIG_DFT_TONE_ANALYZER0_ipr_dft_ana_start_offset_i_MASK)

#define XCVR_RX_DIG_DFT_TONE_ANALYZER0_ipr_dft_ana_attenuation_q_MASK (0x1C0000U)
#define XCVR_RX_DIG_DFT_TONE_ANALYZER0_ipr_dft_ana_attenuation_q_SHIFT (18U)
/*! ipr_dft_ana_attenuation_q - Tone Attenuation For Q Path
 */
#define XCVR_RX_DIG_DFT_TONE_ANALYZER0_ipr_dft_ana_attenuation_q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DFT_TONE_ANALYZER0_ipr_dft_ana_attenuation_q_SHIFT)) & XCVR_RX_DIG_DFT_TONE_ANALYZER0_ipr_dft_ana_attenuation_q_MASK)

#define XCVR_RX_DIG_DFT_TONE_ANALYZER0_ipr_dft_ana_attenuation_i_MASK (0xE00000U)
#define XCVR_RX_DIG_DFT_TONE_ANALYZER0_ipr_dft_ana_attenuation_i_SHIFT (21U)
#define XCVR_RX_DIG_DFT_TONE_ANALYZER0_ipr_dft_ana_attenuation_i(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DFT_TONE_ANALYZER0_ipr_dft_ana_attenuation_i_SHIFT)) & XCVR_RX_DIG_DFT_TONE_ANALYZER0_ipr_dft_ana_attenuation_i_MASK)

#define XCVR_RX_DIG_DFT_TONE_ANALYZER0_ipr_dft_ana_en_MASK (0x1000000U)
#define XCVR_RX_DIG_DFT_TONE_ANALYZER0_ipr_dft_ana_en_SHIFT (24U)
/*! ipr_dft_ana_en - Enable for DfT tone analyzer
 */
#define XCVR_RX_DIG_DFT_TONE_ANALYZER0_ipr_dft_ana_en(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DFT_TONE_ANALYZER0_ipr_dft_ana_en_SHIFT)) & XCVR_RX_DIG_DFT_TONE_ANALYZER0_ipr_dft_ana_en_MASK)
/*! @} */

/*! @name DFT_TONE_ANALYZER1 - DfT tone analyzer */
/*! @{ */

#define XCVR_RX_DIG_DFT_TONE_ANALYZER1_rx_tone_ana_accu_ovf_MASK (0x1U)
#define XCVR_RX_DIG_DFT_TONE_ANALYZER1_rx_tone_ana_accu_ovf_SHIFT (0U)
#define XCVR_RX_DIG_DFT_TONE_ANALYZER1_rx_tone_ana_accu_ovf(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DFT_TONE_ANALYZER1_rx_tone_ana_accu_ovf_SHIFT)) & XCVR_RX_DIG_DFT_TONE_ANALYZER1_rx_tone_ana_accu_ovf_MASK)

#define XCVR_RX_DIG_DFT_TONE_ANALYZER1_rx_tone_ana_bitshift_ovf_MASK (0x2U)
#define XCVR_RX_DIG_DFT_TONE_ANALYZER1_rx_tone_ana_bitshift_ovf_SHIFT (1U)
#define XCVR_RX_DIG_DFT_TONE_ANALYZER1_rx_tone_ana_bitshift_ovf(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DFT_TONE_ANALYZER1_rx_tone_ana_bitshift_ovf_SHIFT)) & XCVR_RX_DIG_DFT_TONE_ANALYZER1_rx_tone_ana_bitshift_ovf_MASK)

#define XCVR_RX_DIG_DFT_TONE_ANALYZER1_ipr_dft_ana_bitshift_MASK (0x3CU)
#define XCVR_RX_DIG_DFT_TONE_ANALYZER1_ipr_dft_ana_bitshift_SHIFT (2U)
#define XCVR_RX_DIG_DFT_TONE_ANALYZER1_ipr_dft_ana_bitshift(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DFT_TONE_ANALYZER1_ipr_dft_ana_bitshift_SHIFT)) & XCVR_RX_DIG_DFT_TONE_ANALYZER1_ipr_dft_ana_bitshift_MASK)

#define XCVR_RX_DIG_DFT_TONE_ANALYZER1_rx_tone_ana_done_MASK (0x40U)
#define XCVR_RX_DIG_DFT_TONE_ANALYZER1_rx_tone_ana_done_SHIFT (6U)
#define XCVR_RX_DIG_DFT_TONE_ANALYZER1_rx_tone_ana_done(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DFT_TONE_ANALYZER1_rx_tone_ana_done_SHIFT)) & XCVR_RX_DIG_DFT_TONE_ANALYZER1_rx_tone_ana_done_MASK)

#define XCVR_RX_DIG_DFT_TONE_ANALYZER1_ipr_dft_ana_start_MASK (0x80U)
#define XCVR_RX_DIG_DFT_TONE_ANALYZER1_ipr_dft_ana_start_SHIFT (7U)
#define XCVR_RX_DIG_DFT_TONE_ANALYZER1_ipr_dft_ana_start(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DFT_TONE_ANALYZER1_ipr_dft_ana_start_SHIFT)) & XCVR_RX_DIG_DFT_TONE_ANALYZER1_ipr_dft_ana_start_MASK)

#define XCVR_RX_DIG_DFT_TONE_ANALYZER1_ipr_dft_ana_input_sel_2_MASK (0x300U)
#define XCVR_RX_DIG_DFT_TONE_ANALYZER1_ipr_dft_ana_input_sel_2_SHIFT (8U)
#define XCVR_RX_DIG_DFT_TONE_ANALYZER1_ipr_dft_ana_input_sel_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DFT_TONE_ANALYZER1_ipr_dft_ana_input_sel_2_SHIFT)) & XCVR_RX_DIG_DFT_TONE_ANALYZER1_ipr_dft_ana_input_sel_2_MASK)

#define XCVR_RX_DIG_DFT_TONE_ANALYZER1_ipr_dft_ana_input_sel_1_MASK (0xC00U)
#define XCVR_RX_DIG_DFT_TONE_ANALYZER1_ipr_dft_ana_input_sel_1_SHIFT (10U)
#define XCVR_RX_DIG_DFT_TONE_ANALYZER1_ipr_dft_ana_input_sel_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DFT_TONE_ANALYZER1_ipr_dft_ana_input_sel_1_SHIFT)) & XCVR_RX_DIG_DFT_TONE_ANALYZER1_ipr_dft_ana_input_sel_1_MASK)

#define XCVR_RX_DIG_DFT_TONE_ANALYZER1_ipr_dft_ana_increment_MASK (0x7F000U)
#define XCVR_RX_DIG_DFT_TONE_ANALYZER1_ipr_dft_ana_increment_SHIFT (12U)
#define XCVR_RX_DIG_DFT_TONE_ANALYZER1_ipr_dft_ana_increment(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DFT_TONE_ANALYZER1_ipr_dft_ana_increment_SHIFT)) & XCVR_RX_DIG_DFT_TONE_ANALYZER1_ipr_dft_ana_increment_MASK)

#define XCVR_RX_DIG_DFT_TONE_ANALYZER1_ipr_dft_ana_clk_div_MASK (0x380000U)
#define XCVR_RX_DIG_DFT_TONE_ANALYZER1_ipr_dft_ana_clk_div_SHIFT (19U)
/*! ipr_dft_ana_clk_div
 *  0b000..ref_clk
 *  0b001..ref_clk div 2
 *  0b010..ref_clk div 4
 *  0b011..ref_clk div 8
 *  0b100..ref_clk div 16
 */
#define XCVR_RX_DIG_DFT_TONE_ANALYZER1_ipr_dft_ana_clk_div(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DFT_TONE_ANALYZER1_ipr_dft_ana_clk_div_SHIFT)) & XCVR_RX_DIG_DFT_TONE_ANALYZER1_ipr_dft_ana_clk_div_MASK)
/*! @} */

/*! @name DFT_TONE_ANALYZER2 - DfT tone analyzer */
/*! @{ */

#define XCVR_RX_DIG_DFT_TONE_ANALYZER2_rx_tone_ana_out_q_MASK (0xFFFFU)
#define XCVR_RX_DIG_DFT_TONE_ANALYZER2_rx_tone_ana_out_q_SHIFT (0U)
#define XCVR_RX_DIG_DFT_TONE_ANALYZER2_rx_tone_ana_out_q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DFT_TONE_ANALYZER2_rx_tone_ana_out_q_SHIFT)) & XCVR_RX_DIG_DFT_TONE_ANALYZER2_rx_tone_ana_out_q_MASK)

#define XCVR_RX_DIG_DFT_TONE_ANALYZER2_rx_tone_ana_out_i_MASK (0xFFFF0000U)
#define XCVR_RX_DIG_DFT_TONE_ANALYZER2_rx_tone_ana_out_i_SHIFT (16U)
#define XCVR_RX_DIG_DFT_TONE_ANALYZER2_rx_tone_ana_out_i(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DFT_TONE_ANALYZER2_rx_tone_ana_out_i_SHIFT)) & XCVR_RX_DIG_DFT_TONE_ANALYZER2_rx_tone_ana_out_i_MASK)
/*! @} */

/*! @name DFT_TONE_ANALYZER3 - DfT tone analyzer */
/*! @{ */

#define XCVR_RX_DIG_DFT_TONE_ANALYZER3_ipr_dft_ana_accumulation_length_MASK (0x7FFFU)
#define XCVR_RX_DIG_DFT_TONE_ANALYZER3_ipr_dft_ana_accumulation_length_SHIFT (0U)
#define XCVR_RX_DIG_DFT_TONE_ANALYZER3_ipr_dft_ana_accumulation_length(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DFT_TONE_ANALYZER3_ipr_dft_ana_accumulation_length_SHIFT)) & XCVR_RX_DIG_DFT_TONE_ANALYZER3_ipr_dft_ana_accumulation_length_MASK)

#define XCVR_RX_DIG_DFT_TONE_ANALYZER3_rx_tone_ana_out_abs_MASK (0x7FFF8000U)
#define XCVR_RX_DIG_DFT_TONE_ANALYZER3_rx_tone_ana_out_abs_SHIFT (15U)
#define XCVR_RX_DIG_DFT_TONE_ANALYZER3_rx_tone_ana_out_abs(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DFT_TONE_ANALYZER3_rx_tone_ana_out_abs_SHIFT)) & XCVR_RX_DIG_DFT_TONE_ANALYZER3_rx_tone_ana_out_abs_MASK)
/*! @} */

/*! @name DCOC_DIG_CORR_RESULT - DCOC Digital Correction Result */
/*! @{ */

#define XCVR_RX_DIG_DCOC_DIG_CORR_RESULT_DCOC_DIG_CORR_Q_MASK (0xFFU)
#define XCVR_RX_DIG_DCOC_DIG_CORR_RESULT_DCOC_DIG_CORR_Q_SHIFT (0U)
/*! DCOC_DIG_CORR_Q - DCOC I-Channel Residual After Calibration
 */
#define XCVR_RX_DIG_DCOC_DIG_CORR_RESULT_DCOC_DIG_CORR_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_DIG_CORR_RESULT_DCOC_DIG_CORR_Q_SHIFT)) & XCVR_RX_DIG_DCOC_DIG_CORR_RESULT_DCOC_DIG_CORR_Q_MASK)

#define XCVR_RX_DIG_DCOC_DIG_CORR_RESULT_DCOC_DIG_CORR_I_MASK (0xFF00U)
#define XCVR_RX_DIG_DCOC_DIG_CORR_RESULT_DCOC_DIG_CORR_I_SHIFT (8U)
/*! DCOC_DIG_CORR_I - DCOC Q-Channel Residual After Calibration
 */
#define XCVR_RX_DIG_DCOC_DIG_CORR_RESULT_DCOC_DIG_CORR_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_DIG_CORR_RESULT_DCOC_DIG_CORR_I_SHIFT)) & XCVR_RX_DIG_DCOC_DIG_CORR_RESULT_DCOC_DIG_CORR_I_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group XCVR_RX_DIG_Register_Masks */


/* XCVR_RX_DIG - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral XCVR_RX_DIG base address */
  #define XCVR_RX_DIG_BASE                         (0x58A07000u)
  /** Peripheral XCVR_RX_DIG base address */
  #define XCVR_RX_DIG_BASE_NS                      (0x48A07000u)
  /** Peripheral XCVR_RX_DIG base pointer */
  #define XCVR_RX_DIG                              ((XCVR_RX_DIG_Type *)XCVR_RX_DIG_BASE)
  /** Peripheral XCVR_RX_DIG base pointer */
  #define XCVR_RX_DIG_NS                           ((XCVR_RX_DIG_Type *)XCVR_RX_DIG_BASE_NS)
  /** Array initializer of XCVR_RX_DIG peripheral base addresses */
  #define XCVR_RX_DIG_BASE_ADDRS                   { XCVR_RX_DIG_BASE }
  /** Array initializer of XCVR_RX_DIG peripheral base pointers */
  #define XCVR_RX_DIG_BASE_PTRS                    { XCVR_RX_DIG }
  /** Array initializer of XCVR_RX_DIG peripheral base addresses */
  #define XCVR_RX_DIG_BASE_ADDRS_NS                { XCVR_RX_DIG_BASE_NS }
  /** Array initializer of XCVR_RX_DIG peripheral base pointers */
  #define XCVR_RX_DIG_BASE_PTRS_NS                 { XCVR_RX_DIG_NS }
#else
  /** Peripheral XCVR_RX_DIG base address */
  #define XCVR_RX_DIG_BASE                         (0x48A07000u)
  /** Peripheral XCVR_RX_DIG base pointer */
  #define XCVR_RX_DIG                              ((XCVR_RX_DIG_Type *)XCVR_RX_DIG_BASE)
  /** Array initializer of XCVR_RX_DIG peripheral base addresses */
  #define XCVR_RX_DIG_BASE_ADDRS                   { XCVR_RX_DIG_BASE }
  /** Array initializer of XCVR_RX_DIG peripheral base pointers */
  #define XCVR_RX_DIG_BASE_PTRS                    { XCVR_RX_DIG }
#endif

/*!
 * @}
 */ /* end of group XCVR_RX_DIG_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- XCVR_TSM Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup XCVR_TSM_Peripheral_Access_Layer XCVR_TSM Peripheral Access Layer
 * @{
 */

/** XCVR_TSM - Register Layout Typedef */
typedef struct {
  __IO uint32_t CTRL;                              /**< TSM CONTROL, offset: 0x0 */
       uint8_t RESERVED_0[4];
  __IO uint32_t END_OF_SEQ;                        /**< TSM END OF SEQUENCE, offset: 0x8 */
  __IO uint32_t WU_LATENCY;                        /**< WARMUP LATENCY, offset: 0xC */
  __IO uint32_t RECYCLE_COUNT;                     /**< TSM RECYCLE COUNT, offset: 0x10 */
  __IO uint32_t FAST_CTRL1;                        /**< TSM FAST WARMUP CONTROL 1, offset: 0x14 */
  __IO uint32_t FAST_CTRL2;                        /**< TSM FAST WARMUP CONTROL 2, offset: 0x18 */
  __IO uint32_t FAST_CTRL3;                        /**< TSM FAST WARMUP CONTROL 3, offset: 0x1C */
  __IO uint32_t TIMING00;                          /**< TSM_TIMING00, offset: 0x20 */
  __IO uint32_t TIMING01;                          /**< TSM_TIMING01, offset: 0x24 */
  __IO uint32_t TIMING02;                          /**< TSM_TIMING02, offset: 0x28 */
  __IO uint32_t TIMING03;                          /**< TSM_TIMING03, offset: 0x2C */
  __IO uint32_t TIMING04;                          /**< TSM_TIMING04, offset: 0x30 */
  __IO uint32_t TIMING05;                          /**< TSM_TIMING05, offset: 0x34 */
  __IO uint32_t TIMING06;                          /**< TSM_TIMING06, offset: 0x38 */
  __IO uint32_t TIMING07;                          /**< TSM_TIMING07, offset: 0x3C */
  __IO uint32_t TIMING08;                          /**< TSM_TIMING08, offset: 0x40 */
  __IO uint32_t TIMING09;                          /**< TSM_TIMING09, offset: 0x44 */
  __IO uint32_t TIMING10;                          /**< TSM_TIMING10, offset: 0x48 */
  __IO uint32_t TIMING11;                          /**< TSM_TIMING11, offset: 0x4C */
  __IO uint32_t TIMING12;                          /**< TSM_TIMING12, offset: 0x50 */
  __IO uint32_t TIMING13;                          /**< TSM_TIMING13, offset: 0x54 */
  __IO uint32_t TIMING14;                          /**< TSM_TIMING14, offset: 0x58 */
  __IO uint32_t TIMING15;                          /**< TSM_TIMING15, offset: 0x5C */
  __IO uint32_t TIMING16;                          /**< TSM_TIMING16, offset: 0x60 */
  __IO uint32_t TIMING17;                          /**< TSM_TIMING17, offset: 0x64 */
  __IO uint32_t TIMING18;                          /**< TSM_TIMING18, offset: 0x68 */
  __IO uint32_t TIMING19;                          /**< TSM_TIMING19, offset: 0x6C */
  __IO uint32_t TIMING20;                          /**< TSM_TIMING20, offset: 0x70 */
  __IO uint32_t TIMING21;                          /**< TSM_TIMING21, offset: 0x74 */
  __IO uint32_t TIMING22;                          /**< TSM_TIMING22, offset: 0x78 */
  __IO uint32_t TIMING23;                          /**< TSM_TIMING23, offset: 0x7C */
  __IO uint32_t TIMING24;                          /**< TSM_TIMING24, offset: 0x80 */
  __IO uint32_t TIMING25;                          /**< TSM_TIMING25, offset: 0x84 */
  __IO uint32_t TIMING26;                          /**< TSM_TIMING26, offset: 0x88 */
  __IO uint32_t TIMING27;                          /**< TSM_TIMING27, offset: 0x8C */
  __IO uint32_t TIMING28;                          /**< TSM_TIMING28, offset: 0x90 */
  __IO uint32_t TIMING29;                          /**< TSM_TIMING29, offset: 0x94 */
  __IO uint32_t TIMING30;                          /**< TSM_TIMING30, offset: 0x98 */
  __IO uint32_t TIMING31;                          /**< TSM_TIMING31, offset: 0x9C */
  __IO uint32_t TIMING32;                          /**< TSM_TIMING32, offset: 0xA0 */
  __IO uint32_t TIMING33;                          /**< TSM_TIMING33, offset: 0xA4 */
  __IO uint32_t TIMING34;                          /**< TSM_TIMING34, offset: 0xA8 */
  __IO uint32_t TIMING35;                          /**< TSM_TIMING35, offset: 0xAC */
  __IO uint32_t TIMING36;                          /**< TSM_TIMING36, offset: 0xB0 */
  __IO uint32_t TIMING37;                          /**< TSM_TIMING37, offset: 0xB4 */
  __IO uint32_t TIMING38;                          /**< TSM_TIMING38, offset: 0xB8 */
  __IO uint32_t TIMING39;                          /**< TSM_TIMING39, offset: 0xBC */
  __IO uint32_t TIMING40;                          /**< TSM_TIMING40, offset: 0xC0 */
  __IO uint32_t TIMING41;                          /**< TSM_TIMING41, offset: 0xC4 */
  __IO uint32_t TIMING42;                          /**< TSM_TIMING42, offset: 0xC8 */
  __IO uint32_t TIMING43;                          /**< TSM_TIMING43, offset: 0xCC */
  __IO uint32_t TIMING44;                          /**< TSM_TIMING44, offset: 0xD0 */
  __IO uint32_t TIMING45;                          /**< TSM_TIMING45, offset: 0xD4 */
  __IO uint32_t TIMING46;                          /**< TSM_TIMING46, offset: 0xD8 */
  __IO uint32_t TIMING47;                          /**< TSM_TIMING47, offset: 0xDC */
  __IO uint32_t TIMING48;                          /**< TSM_TIMING48, offset: 0xE0 */
  __IO uint32_t TIMING49;                          /**< TSM_TIMING49, offset: 0xE4 */
  __IO uint32_t TIMING50;                          /**< TSM_TIMING50, offset: 0xE8 */
  __IO uint32_t TIMING51;                          /**< TSM_TIMING51, offset: 0xEC */
  __IO uint32_t TIMING52;                          /**< TSM_TIMING52, offset: 0xF0 */
  __IO uint32_t OVRD0;                             /**< TSM OVERRIDE REGISTER 0, offset: 0xF4 */
  __IO uint32_t OVRD1;                             /**< TSM OVERRIDE REGISTER 1, offset: 0xF8 */
  __IO uint32_t OVRD2;                             /**< TSM OVERRIDE REGISTER 2, offset: 0xFC */
  __IO uint32_t OVRD3;                             /**< TSM OVERRIDE REGISTER 3, offset: 0x100 */
} XCVR_TSM_Type;

/* ----------------------------------------------------------------------------
   -- XCVR_TSM Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup XCVR_TSM_Register_Masks XCVR_TSM Register Masks
 * @{
 */

/*! @name CTRL - TSM CONTROL */
/*! @{ */

#define XCVR_TSM_CTRL_TSM_SOFT_RESET_MASK        (0x2U)
#define XCVR_TSM_CTRL_TSM_SOFT_RESET_SHIFT       (1U)
/*! TSM_SOFT_RESET - TSM Soft Reset
 *  0b0..TSM Soft Reset removed. Normal operation.
 *  0b1..TSM Soft Reset engaged. TSM forced to IDLE, and holds there until the bit is cleared.
 */
#define XCVR_TSM_CTRL_TSM_SOFT_RESET(x)          (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_TSM_SOFT_RESET_SHIFT)) & XCVR_TSM_CTRL_TSM_SOFT_RESET_MASK)

#define XCVR_TSM_CTRL_FORCE_TX_EN_MASK           (0x4U)
#define XCVR_TSM_CTRL_FORCE_TX_EN_SHIFT          (2U)
/*! FORCE_TX_EN - Force Transmit Enable
 *  0b0..TSM Idle
 *  0b1..TSM executes a TX sequence
 */
#define XCVR_TSM_CTRL_FORCE_TX_EN(x)             (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_FORCE_TX_EN_SHIFT)) & XCVR_TSM_CTRL_FORCE_TX_EN_MASK)

#define XCVR_TSM_CTRL_FORCE_RX_EN_MASK           (0x8U)
#define XCVR_TSM_CTRL_FORCE_RX_EN_SHIFT          (3U)
/*! FORCE_RX_EN - Force Receive Enable
 *  0b0..TSM Idle
 *  0b1..TSM executes a RX sequence
 */
#define XCVR_TSM_CTRL_FORCE_RX_EN(x)             (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_FORCE_RX_EN_SHIFT)) & XCVR_TSM_CTRL_FORCE_RX_EN_MASK)

#define XCVR_TSM_CTRL_TX_ABORT_DIS_MASK          (0x10U)
#define XCVR_TSM_CTRL_TX_ABORT_DIS_SHIFT         (4U)
/*! TX_ABORT_DIS - Transmit Abort Disable
 */
#define XCVR_TSM_CTRL_TX_ABORT_DIS(x)            (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_TX_ABORT_DIS_SHIFT)) & XCVR_TSM_CTRL_TX_ABORT_DIS_MASK)

#define XCVR_TSM_CTRL_RX_ABORT_DIS_MASK          (0x20U)
#define XCVR_TSM_CTRL_RX_ABORT_DIS_SHIFT         (5U)
/*! RX_ABORT_DIS - Receive Abort Disable
 */
#define XCVR_TSM_CTRL_RX_ABORT_DIS(x)            (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_RX_ABORT_DIS_SHIFT)) & XCVR_TSM_CTRL_RX_ABORT_DIS_MASK)

#define XCVR_TSM_CTRL_ABORT_ON_CTUNE_MASK        (0x40U)
#define XCVR_TSM_CTRL_ABORT_ON_CTUNE_SHIFT       (6U)
/*! ABORT_ON_CTUNE - Abort On Coarse Tune Lock Detect Failure
 *  0b0..don't allow TSM abort on Coarse Tune Unlock Detect
 *  0b1..allow TSM abort on Coarse Tune Unlock Detect
 */
#define XCVR_TSM_CTRL_ABORT_ON_CTUNE(x)          (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_ABORT_ON_CTUNE_SHIFT)) & XCVR_TSM_CTRL_ABORT_ON_CTUNE_MASK)

#define XCVR_TSM_CTRL_ABORT_ON_FREQ_TARG_MASK    (0x80U)
#define XCVR_TSM_CTRL_ABORT_ON_FREQ_TARG_SHIFT   (7U)
/*! ABORT_ON_FREQ_TARG - Abort On Frequency Target Lock Detect Failure
 *  0b0..don't allow TSM abort on Frequency Target Unlock Detect
 *  0b1..allow TSM abort on Frequency Target Unlock Detect
 */
#define XCVR_TSM_CTRL_ABORT_ON_FREQ_TARG(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_ABORT_ON_FREQ_TARG_SHIFT)) & XCVR_TSM_CTRL_ABORT_ON_FREQ_TARG_MASK)

#define XCVR_TSM_CTRL_TSM_IRQ0_EN_MASK           (0x100U)
#define XCVR_TSM_CTRL_TSM_IRQ0_EN_SHIFT          (8U)
/*! TSM_IRQ0_EN - TSM_IRQ0 Enable/Disable bit
 *  0b0..TSM_IRQ0 is disabled
 *  0b1..TSM_IRQ0 is enabled
 */
#define XCVR_TSM_CTRL_TSM_IRQ0_EN(x)             (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_TSM_IRQ0_EN_SHIFT)) & XCVR_TSM_CTRL_TSM_IRQ0_EN_MASK)

#define XCVR_TSM_CTRL_TSM_IRQ1_EN_MASK           (0x200U)
#define XCVR_TSM_CTRL_TSM_IRQ1_EN_SHIFT          (9U)
/*! TSM_IRQ1_EN - TSM_IRQ1 Enable/Disable bit
 *  0b0..TSM_IRQ1 is disabled
 *  0b1..TSM_IRQ1 is enabled
 */
#define XCVR_TSM_CTRL_TSM_IRQ1_EN(x)             (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_TSM_IRQ1_EN_SHIFT)) & XCVR_TSM_CTRL_TSM_IRQ1_EN_MASK)

#define XCVR_TSM_CTRL_PLL_UNLOCK_IRQ_EN_MASK     (0x400U)
#define XCVR_TSM_CTRL_PLL_UNLOCK_IRQ_EN_SHIFT    (10U)
/*! PLL_UNLOCK_IRQ_EN - PLL Unlock Interrupt Enable
 *  0b0..allows PLL unlock event to generate an interrupt
 *  0b1..A PLL unlock event will set the PLL_UNLOCK_IRQ status bit, but an interrupt is not generated
 */
#define XCVR_TSM_CTRL_PLL_UNLOCK_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_PLL_UNLOCK_IRQ_EN_SHIFT)) & XCVR_TSM_CTRL_PLL_UNLOCK_IRQ_EN_MASK)

#define XCVR_TSM_CTRL_PLL_UNLOCK_IRQ_MASK        (0x800U)
#define XCVR_TSM_CTRL_PLL_UNLOCK_IRQ_SHIFT       (11U)
/*! PLL_UNLOCK_IRQ - PLL Unlock IRQ
 *  0b0..A PLL Unlock Interrupt has not occurred
 *  0b1..A PLL Unlock Interrupt has occurred
 */
#define XCVR_TSM_CTRL_PLL_UNLOCK_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_PLL_UNLOCK_IRQ_SHIFT)) & XCVR_TSM_CTRL_PLL_UNLOCK_IRQ_MASK)

#define XCVR_TSM_CTRL_TSM_LL_INHIBIT_MASK        (0xF000U)
#define XCVR_TSM_CTRL_TSM_LL_INHIBIT_SHIFT       (12U)
/*! TSM_LL_INHIBIT - TSM Per-Link-Layer Inhibit
 */
#define XCVR_TSM_CTRL_TSM_LL_INHIBIT(x)          (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_TSM_LL_INHIBIT_SHIFT)) & XCVR_TSM_CTRL_TSM_LL_INHIBIT_MASK)

#define XCVR_TSM_CTRL_TSM_SPARE1_EXTEND_MASK     (0xFF0000U)
#define XCVR_TSM_CTRL_TSM_SPARE1_EXTEND_SHIFT    (16U)
/*! TSM_SPARE1_EXTEND - TSM RF_ACTIVE Extension Duration
 */
#define XCVR_TSM_CTRL_TSM_SPARE1_EXTEND(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_TSM_SPARE1_EXTEND_SHIFT)) & XCVR_TSM_CTRL_TSM_SPARE1_EXTEND_MASK)

#define XCVR_TSM_CTRL_BKPT_MASK                  (0xFF000000U)
#define XCVR_TSM_CTRL_BKPT_SHIFT                 (24U)
/*! BKPT - TSM Breakpoint
 */
#define XCVR_TSM_CTRL_BKPT(x)                    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_BKPT_SHIFT)) & XCVR_TSM_CTRL_BKPT_MASK)
/*! @} */

/*! @name END_OF_SEQ - TSM END OF SEQUENCE */
/*! @{ */

#define XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_MASK    (0xFFU)
#define XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_SHIFT   (0U)
/*! END_OF_TX_WU - End of TX Warmup
 */
#define XCVR_TSM_END_OF_SEQ_END_OF_TX_WU(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_SHIFT)) & XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_MASK)

#define XCVR_TSM_END_OF_SEQ_END_OF_TX_WD_MASK    (0xFF00U)
#define XCVR_TSM_END_OF_SEQ_END_OF_TX_WD_SHIFT   (8U)
/*! END_OF_TX_WD - End of TX Warmdown
 */
#define XCVR_TSM_END_OF_SEQ_END_OF_TX_WD(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_END_OF_SEQ_END_OF_TX_WD_SHIFT)) & XCVR_TSM_END_OF_SEQ_END_OF_TX_WD_MASK)

#define XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK    (0xFF0000U)
#define XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT   (16U)
/*! END_OF_RX_WU - End of RX Warmup
 */
#define XCVR_TSM_END_OF_SEQ_END_OF_RX_WU(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT)) & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK)

#define XCVR_TSM_END_OF_SEQ_END_OF_RX_WD_MASK    (0xFF000000U)
#define XCVR_TSM_END_OF_SEQ_END_OF_RX_WD_SHIFT   (24U)
/*! END_OF_RX_WD - End of RX Warmdown
 */
#define XCVR_TSM_END_OF_SEQ_END_OF_RX_WD(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_END_OF_SEQ_END_OF_RX_WD_SHIFT)) & XCVR_TSM_END_OF_SEQ_END_OF_RX_WD_MASK)
/*! @} */

/*! @name WU_LATENCY - WARMUP LATENCY */
/*! @{ */

#define XCVR_TSM_WU_LATENCY_TX_DATAPATH_LATENCY_MASK (0xFFU)
#define XCVR_TSM_WU_LATENCY_TX_DATAPATH_LATENCY_SHIFT (0U)
/*! TX_DATAPATH_LATENCY - TX Datapath Latency
 */
#define XCVR_TSM_WU_LATENCY_TX_DATAPATH_LATENCY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_WU_LATENCY_TX_DATAPATH_LATENCY_SHIFT)) & XCVR_TSM_WU_LATENCY_TX_DATAPATH_LATENCY_MASK)

#define XCVR_TSM_WU_LATENCY_RX_SETTLING_LATENCY_MASK (0xFF0000U)
#define XCVR_TSM_WU_LATENCY_RX_SETTLING_LATENCY_SHIFT (16U)
/*! RX_SETTLING_LATENCY - RX Settling Latency
 */
#define XCVR_TSM_WU_LATENCY_RX_SETTLING_LATENCY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_WU_LATENCY_RX_SETTLING_LATENCY_SHIFT)) & XCVR_TSM_WU_LATENCY_RX_SETTLING_LATENCY_MASK)
/*! @} */

/*! @name RECYCLE_COUNT - TSM RECYCLE COUNT */
/*! @{ */

#define XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT0_MASK (0xFFU)
#define XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT0_SHIFT (0U)
/*! RECYCLE_COUNT0 - TSM RX Recycle Count 0
 */
#define XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT0_SHIFT)) & XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT0_MASK)

#define XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT1_MASK (0xFF00U)
#define XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT1_SHIFT (8U)
/*! RECYCLE_COUNT1 - TSM RX Recycle Count 1
 */
#define XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT1_SHIFT)) & XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT1_MASK)
/*! @} */

/*! @name FAST_CTRL1 - TSM FAST WARMUP CONTROL 1 */
/*! @{ */

#define XCVR_TSM_FAST_CTRL1_FAST_TX_WU_EN_MASK   (0x1U)
#define XCVR_TSM_FAST_CTRL1_FAST_TX_WU_EN_SHIFT  (0U)
/*! FAST_TX_WU_EN - Fast TSM TX Warmup Enable
 *  0b0..Fast TSM TX Warmups are disabled
 *  0b1..Fast TSM TX Warmups are enabled, if the RF channel has not changed since the last TX warmup, and for
 *       Bluetooth LE mode, the RF channel is not an advertising channel.
 */
#define XCVR_TSM_FAST_CTRL1_FAST_TX_WU_EN(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL1_FAST_TX_WU_EN_SHIFT)) & XCVR_TSM_FAST_CTRL1_FAST_TX_WU_EN_MASK)

#define XCVR_TSM_FAST_CTRL1_FAST_RX_WU_EN_MASK   (0x2U)
#define XCVR_TSM_FAST_CTRL1_FAST_RX_WU_EN_SHIFT  (1U)
/*! FAST_RX_WU_EN - Fast TSM RX Warmup Enable
 *  0b0..Fast TSM RX Warmups are disabled
 *  0b1..Fast TSM RX Warmups are enabled, if the RF channel has not changed since the last RX warmup, and for
 *       Bluetooth LE mode, the RF channel is not an advertising channel.
 */
#define XCVR_TSM_FAST_CTRL1_FAST_RX_WU_EN(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL1_FAST_RX_WU_EN_SHIFT)) & XCVR_TSM_FAST_CTRL1_FAST_RX_WU_EN_MASK)

#define XCVR_TSM_FAST_CTRL1_FAST_RX2TX_EN_MASK   (0x4U)
#define XCVR_TSM_FAST_CTRL1_FAST_RX2TX_EN_SHIFT  (2U)
/*! FAST_RX2TX_EN - Fast TSM RX-to-TX Transition Enable
 *  0b0..Disable Fast RX-to-TX transitions
 *  0b1..Enable Fast RX-to-TX transitions (if fast_rx2tx_wu is asserted by the Link Layer)
 */
#define XCVR_TSM_FAST_CTRL1_FAST_RX2TX_EN(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL1_FAST_RX2TX_EN_SHIFT)) & XCVR_TSM_FAST_CTRL1_FAST_RX2TX_EN_MASK)

#define XCVR_TSM_FAST_CTRL1_PWRSAVE_TX_WU_EN_MASK (0x10U)
#define XCVR_TSM_FAST_CTRL1_PWRSAVE_TX_WU_EN_SHIFT (4U)
/*! PWRSAVE_TX_WU_EN - Power Save TSM TX Warmup Enable
 *  0b0..PowerSave TSM TX Warmups are disabled
 *  0b1..PowerSave TSM TX Warmups are enabled, if the RF channel has not changed since the last TX warmup.
 */
#define XCVR_TSM_FAST_CTRL1_PWRSAVE_TX_WU_EN(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL1_PWRSAVE_TX_WU_EN_SHIFT)) & XCVR_TSM_FAST_CTRL1_PWRSAVE_TX_WU_EN_MASK)

#define XCVR_TSM_FAST_CTRL1_PWRSAVE_RX_WU_EN_MASK (0x20U)
#define XCVR_TSM_FAST_CTRL1_PWRSAVE_RX_WU_EN_SHIFT (5U)
/*! PWRSAVE_RX_WU_EN - Power Save TSM RX Warmup Enable
 *  0b0..PowerSave TSM RX Warmups are disabled
 *  0b1..PowerSave TSM RX Warmups are enabled, if the RF channel has not changed since the last RX warmup.
 */
#define XCVR_TSM_FAST_CTRL1_PWRSAVE_RX_WU_EN(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL1_PWRSAVE_RX_WU_EN_SHIFT)) & XCVR_TSM_FAST_CTRL1_PWRSAVE_RX_WU_EN_MASK)

#define XCVR_TSM_FAST_CTRL1_PWRSAVE_WU_CLEAR_MASK (0x40U)
#define XCVR_TSM_FAST_CTRL1_PWRSAVE_WU_CLEAR_SHIFT (6U)
/*! PWRSAVE_WU_CLEAR - PowerSave TSM Warmup Clear State
 */
#define XCVR_TSM_FAST_CTRL1_PWRSAVE_WU_CLEAR(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL1_PWRSAVE_WU_CLEAR_SHIFT)) & XCVR_TSM_FAST_CTRL1_PWRSAVE_WU_CLEAR_MASK)

#define XCVR_TSM_FAST_CTRL1_FAST_RX2TX_START_MASK (0xFF00U)
#define XCVR_TSM_FAST_CTRL1_FAST_RX2TX_START_SHIFT (8U)
/*! FAST_RX2TX_START - TSM "Jump-to" point for a Fast TSM RX-to-TX Transition.
 */
#define XCVR_TSM_FAST_CTRL1_FAST_RX2TX_START(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL1_FAST_RX2TX_START_SHIFT)) & XCVR_TSM_FAST_CTRL1_FAST_RX2TX_START_MASK)

#define XCVR_TSM_FAST_CTRL1_FAST_TX2RX_EN_MASK   (0x800000U)
#define XCVR_TSM_FAST_CTRL1_FAST_TX2RX_EN_SHIFT  (23U)
/*! FAST_TX2RX_EN - Fast TSM TX-to-RX Transition Enable
 *  0b0..Disable Fast TX-to-RX transitions
 *  0b1..Enable Fast TX-to-RX transitions (if fast_tx2rx_wu is asserted by Ranging sequence manager)
 */
#define XCVR_TSM_FAST_CTRL1_FAST_TX2RX_EN(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL1_FAST_TX2RX_EN_SHIFT)) & XCVR_TSM_FAST_CTRL1_FAST_TX2RX_EN_MASK)

#define XCVR_TSM_FAST_CTRL1_FAST_TX2RX_START_MASK (0xFF000000U)
#define XCVR_TSM_FAST_CTRL1_FAST_TX2RX_START_SHIFT (24U)
/*! FAST_TX2RX_START - TSM "Jump-to" point for a Fast TSM TX-to-RX Transition.
 */
#define XCVR_TSM_FAST_CTRL1_FAST_TX2RX_START(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL1_FAST_TX2RX_START_SHIFT)) & XCVR_TSM_FAST_CTRL1_FAST_TX2RX_START_MASK)
/*! @} */

/*! @name FAST_CTRL2 - TSM FAST WARMUP CONTROL 2 */
/*! @{ */

#define XCVR_TSM_FAST_CTRL2_FAST_START_TX_MASK   (0xFFU)
#define XCVR_TSM_FAST_CTRL2_FAST_START_TX_SHIFT  (0U)
/*! FAST_START_TX - Fast TSM TX "Jump-from" Point
 */
#define XCVR_TSM_FAST_CTRL2_FAST_START_TX(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL2_FAST_START_TX_SHIFT)) & XCVR_TSM_FAST_CTRL2_FAST_START_TX_MASK)

#define XCVR_TSM_FAST_CTRL2_FAST_DEST_TX_MASK    (0xFF00U)
#define XCVR_TSM_FAST_CTRL2_FAST_DEST_TX_SHIFT   (8U)
/*! FAST_DEST_TX - Fast TSM TX "Jump-to" Point
 */
#define XCVR_TSM_FAST_CTRL2_FAST_DEST_TX(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL2_FAST_DEST_TX_SHIFT)) & XCVR_TSM_FAST_CTRL2_FAST_DEST_TX_MASK)

#define XCVR_TSM_FAST_CTRL2_FAST_START_RX_MASK   (0xFF0000U)
#define XCVR_TSM_FAST_CTRL2_FAST_START_RX_SHIFT  (16U)
/*! FAST_START_RX - Fast TSM RX "Jump-from" Point
 */
#define XCVR_TSM_FAST_CTRL2_FAST_START_RX(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL2_FAST_START_RX_SHIFT)) & XCVR_TSM_FAST_CTRL2_FAST_START_RX_MASK)

#define XCVR_TSM_FAST_CTRL2_FAST_DEST_RX_MASK    (0xFF000000U)
#define XCVR_TSM_FAST_CTRL2_FAST_DEST_RX_SHIFT   (24U)
/*! FAST_DEST_RX - Fast TSM RX "Jump-to" Point
 */
#define XCVR_TSM_FAST_CTRL2_FAST_DEST_RX(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL2_FAST_DEST_RX_SHIFT)) & XCVR_TSM_FAST_CTRL2_FAST_DEST_RX_MASK)
/*! @} */

/*! @name FAST_CTRL3 - TSM FAST WARMUP CONTROL 3 */
/*! @{ */

#define XCVR_TSM_FAST_CTRL3_FAST_RX2TX_START_FC_MASK (0xFF00U)
#define XCVR_TSM_FAST_CTRL3_FAST_RX2TX_START_FC_SHIFT (8U)
/*! FAST_RX2TX_START_FC - TSM "Jump-to" point for RSM's FC RX-to-TX Transition
 */
#define XCVR_TSM_FAST_CTRL3_FAST_RX2TX_START_FC(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL3_FAST_RX2TX_START_FC_SHIFT)) & XCVR_TSM_FAST_CTRL3_FAST_RX2TX_START_FC_MASK)

#define XCVR_TSM_FAST_CTRL3_FAST_TX2RX_START_FC_MASK (0xFF000000U)
#define XCVR_TSM_FAST_CTRL3_FAST_TX2RX_START_FC_SHIFT (24U)
/*! FAST_TX2RX_START_FC - TSM "Jump-to" point for RSM's FC TX-to-RX Transition
 */
#define XCVR_TSM_FAST_CTRL3_FAST_TX2RX_START_FC(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL3_FAST_TX2RX_START_FC_SHIFT)) & XCVR_TSM_FAST_CTRL3_FAST_TX2RX_START_FC_MASK)
/*! @} */

/*! @name TIMING00 - TSM_TIMING00 */
/*! @{ */

#define XCVR_TSM_TIMING00_RF_ACTIVE_TX_HI_MASK   (0xFFU)
#define XCVR_TSM_TIMING00_RF_ACTIVE_TX_HI_SHIFT  (0U)
/*! RF_ACTIVE_TX_HI - Assertion time setting for RF_ACTIVE (TX)
 */
#define XCVR_TSM_TIMING00_RF_ACTIVE_TX_HI(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING00_RF_ACTIVE_TX_HI_SHIFT)) & XCVR_TSM_TIMING00_RF_ACTIVE_TX_HI_MASK)

#define XCVR_TSM_TIMING00_RF_ACTIVE_TX_LO_MASK   (0xFF00U)
#define XCVR_TSM_TIMING00_RF_ACTIVE_TX_LO_SHIFT  (8U)
/*! RF_ACTIVE_TX_LO - De-assertion time setting for RF_ACTIVE (TX)
 */
#define XCVR_TSM_TIMING00_RF_ACTIVE_TX_LO(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING00_RF_ACTIVE_TX_LO_SHIFT)) & XCVR_TSM_TIMING00_RF_ACTIVE_TX_LO_MASK)

#define XCVR_TSM_TIMING00_RF_ACTIVE_RX_HI_MASK   (0xFF0000U)
#define XCVR_TSM_TIMING00_RF_ACTIVE_RX_HI_SHIFT  (16U)
/*! RF_ACTIVE_RX_HI - Assertion time setting for RF_ACTIVE_EN (RX)
 */
#define XCVR_TSM_TIMING00_RF_ACTIVE_RX_HI(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING00_RF_ACTIVE_RX_HI_SHIFT)) & XCVR_TSM_TIMING00_RF_ACTIVE_RX_HI_MASK)

#define XCVR_TSM_TIMING00_RF_ACTIVE_RX_LO_MASK   (0xFF000000U)
#define XCVR_TSM_TIMING00_RF_ACTIVE_RX_LO_SHIFT  (24U)
/*! RF_ACTIVE_RX_LO - De-assertion time setting for RF_ACTIVE (RX)
 */
#define XCVR_TSM_TIMING00_RF_ACTIVE_RX_LO(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING00_RF_ACTIVE_RX_LO_SHIFT)) & XCVR_TSM_TIMING00_RF_ACTIVE_RX_LO_MASK)
/*! @} */

/*! @name TIMING01 - TSM_TIMING01 */
/*! @{ */

#define XCVR_TSM_TIMING01_RF_STATUS_TX_HI_MASK   (0xFFU)
#define XCVR_TSM_TIMING01_RF_STATUS_TX_HI_SHIFT  (0U)
/*! RF_STATUS_TX_HI - Assertion time setting for RF_STATUS (TX)
 */
#define XCVR_TSM_TIMING01_RF_STATUS_TX_HI(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING01_RF_STATUS_TX_HI_SHIFT)) & XCVR_TSM_TIMING01_RF_STATUS_TX_HI_MASK)

#define XCVR_TSM_TIMING01_RF_STATUS_TX_LO_MASK   (0xFF00U)
#define XCVR_TSM_TIMING01_RF_STATUS_TX_LO_SHIFT  (8U)
/*! RF_STATUS_TX_LO - De-assertion time setting for RF_STATUS (TX)
 */
#define XCVR_TSM_TIMING01_RF_STATUS_TX_LO(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING01_RF_STATUS_TX_LO_SHIFT)) & XCVR_TSM_TIMING01_RF_STATUS_TX_LO_MASK)

#define XCVR_TSM_TIMING01_RF_STATUS_RX_HI_MASK   (0xFF0000U)
#define XCVR_TSM_TIMING01_RF_STATUS_RX_HI_SHIFT  (16U)
/*! RF_STATUS_RX_HI - Assertion time setting for RF_STATUS (RX)
 */
#define XCVR_TSM_TIMING01_RF_STATUS_RX_HI(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING01_RF_STATUS_RX_HI_SHIFT)) & XCVR_TSM_TIMING01_RF_STATUS_RX_HI_MASK)

#define XCVR_TSM_TIMING01_RF_STATUS_RX_LO_MASK   (0xFF000000U)
#define XCVR_TSM_TIMING01_RF_STATUS_RX_LO_SHIFT  (24U)
/*! RF_STATUS_RX_LO - De-assertion time setting for RF_STATUS (RX)
 */
#define XCVR_TSM_TIMING01_RF_STATUS_RX_LO(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING01_RF_STATUS_RX_LO_SHIFT)) & XCVR_TSM_TIMING01_RF_STATUS_RX_LO_MASK)
/*! @} */

/*! @name TIMING02 - TSM_TIMING02 */
/*! @{ */

#define XCVR_TSM_TIMING02_RF_PRIORITY_TX_HI_MASK (0xFFU)
#define XCVR_TSM_TIMING02_RF_PRIORITY_TX_HI_SHIFT (0U)
/*! RF_PRIORITY_TX_HI - Assertion time setting for RF_PRIORITY (TX)
 */
#define XCVR_TSM_TIMING02_RF_PRIORITY_TX_HI(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING02_RF_PRIORITY_TX_HI_SHIFT)) & XCVR_TSM_TIMING02_RF_PRIORITY_TX_HI_MASK)

#define XCVR_TSM_TIMING02_RF_PRIORITY_TX_LO_MASK (0xFF00U)
#define XCVR_TSM_TIMING02_RF_PRIORITY_TX_LO_SHIFT (8U)
/*! RF_PRIORITY_TX_LO - De-assertion time setting for RF_PRIORITY (TX)
 */
#define XCVR_TSM_TIMING02_RF_PRIORITY_TX_LO(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING02_RF_PRIORITY_TX_LO_SHIFT)) & XCVR_TSM_TIMING02_RF_PRIORITY_TX_LO_MASK)

#define XCVR_TSM_TIMING02_RF_PRIORITY_RX_HI_MASK (0xFF0000U)
#define XCVR_TSM_TIMING02_RF_PRIORITY_RX_HI_SHIFT (16U)
/*! RF_PRIORITY_RX_HI - Assertion time setting for RF_PRIORITY (RX)
 */
#define XCVR_TSM_TIMING02_RF_PRIORITY_RX_HI(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING02_RF_PRIORITY_RX_HI_SHIFT)) & XCVR_TSM_TIMING02_RF_PRIORITY_RX_HI_MASK)

#define XCVR_TSM_TIMING02_RF_PRIORITY_RX_LO_MASK (0xFF000000U)
#define XCVR_TSM_TIMING02_RF_PRIORITY_RX_LO_SHIFT (24U)
/*! RF_PRIORITY_RX_LO - De-assertion time setting for RF_PRIORITY (RX)
 */
#define XCVR_TSM_TIMING02_RF_PRIORITY_RX_LO(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING02_RF_PRIORITY_RX_LO_SHIFT)) & XCVR_TSM_TIMING02_RF_PRIORITY_RX_LO_MASK)
/*! @} */

/*! @name TIMING03 - TSM_TIMING03 */
/*! @{ */

#define XCVR_TSM_TIMING03_IRQ0_START_TRIG_TX_HI_MASK (0xFFU)
#define XCVR_TSM_TIMING03_IRQ0_START_TRIG_TX_HI_SHIFT (0U)
/*! IRQ0_START_TRIG_TX_HI - Assertion time setting for IRQ0_START_TRIG (TX)
 */
#define XCVR_TSM_TIMING03_IRQ0_START_TRIG_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING03_IRQ0_START_TRIG_TX_HI_SHIFT)) & XCVR_TSM_TIMING03_IRQ0_START_TRIG_TX_HI_MASK)

#define XCVR_TSM_TIMING03_IRQ0_START_TRIG_TX_LO_MASK (0xFF00U)
#define XCVR_TSM_TIMING03_IRQ0_START_TRIG_TX_LO_SHIFT (8U)
/*! IRQ0_START_TRIG_TX_LO - De-assertion time setting for IRQ0_START_TRIG (TX)
 */
#define XCVR_TSM_TIMING03_IRQ0_START_TRIG_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING03_IRQ0_START_TRIG_TX_LO_SHIFT)) & XCVR_TSM_TIMING03_IRQ0_START_TRIG_TX_LO_MASK)

#define XCVR_TSM_TIMING03_IRQ0_START_TRIG_RX_HI_MASK (0xFF0000U)
#define XCVR_TSM_TIMING03_IRQ0_START_TRIG_RX_HI_SHIFT (16U)
/*! IRQ0_START_TRIG_RX_HI - Assertion time setting for IRQ0_START_TRIG (RX)
 */
#define XCVR_TSM_TIMING03_IRQ0_START_TRIG_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING03_IRQ0_START_TRIG_RX_HI_SHIFT)) & XCVR_TSM_TIMING03_IRQ0_START_TRIG_RX_HI_MASK)

#define XCVR_TSM_TIMING03_IRQ0_START_TRIG_RX_LO_MASK (0xFF000000U)
#define XCVR_TSM_TIMING03_IRQ0_START_TRIG_RX_LO_SHIFT (24U)
/*! IRQ0_START_TRIG_RX_LO - De-assertion time setting for IRQ0_START_TRIG (RX)
 */
#define XCVR_TSM_TIMING03_IRQ0_START_TRIG_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING03_IRQ0_START_TRIG_RX_LO_SHIFT)) & XCVR_TSM_TIMING03_IRQ0_START_TRIG_RX_LO_MASK)
/*! @} */

/*! @name TIMING04 - TSM_TIMING04 */
/*! @{ */

#define XCVR_TSM_TIMING04_IRQ1_STOP_TRIG_TX_HI_MASK (0xFFU)
#define XCVR_TSM_TIMING04_IRQ1_STOP_TRIG_TX_HI_SHIFT (0U)
/*! IRQ1_STOP_TRIG_TX_HI - Assertion time setting for IRQ1_STOP_TRIG (TX)
 */
#define XCVR_TSM_TIMING04_IRQ1_STOP_TRIG_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING04_IRQ1_STOP_TRIG_TX_HI_SHIFT)) & XCVR_TSM_TIMING04_IRQ1_STOP_TRIG_TX_HI_MASK)

#define XCVR_TSM_TIMING04_IRQ1_STOP_TRIG_TX_LO_MASK (0xFF00U)
#define XCVR_TSM_TIMING04_IRQ1_STOP_TRIG_TX_LO_SHIFT (8U)
/*! IRQ1_STOP_TRIG_TX_LO - De-assertion time setting for IRQ1_STOP_TRIG (TX)
 */
#define XCVR_TSM_TIMING04_IRQ1_STOP_TRIG_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING04_IRQ1_STOP_TRIG_TX_LO_SHIFT)) & XCVR_TSM_TIMING04_IRQ1_STOP_TRIG_TX_LO_MASK)

#define XCVR_TSM_TIMING04_IRQ1_STOP_TRIG_RX_HI_MASK (0xFF0000U)
#define XCVR_TSM_TIMING04_IRQ1_STOP_TRIG_RX_HI_SHIFT (16U)
/*! IRQ1_STOP_TRIG_RX_HI - Assertion time setting for IRQ1_STOP_TRIG (RX)
 */
#define XCVR_TSM_TIMING04_IRQ1_STOP_TRIG_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING04_IRQ1_STOP_TRIG_RX_HI_SHIFT)) & XCVR_TSM_TIMING04_IRQ1_STOP_TRIG_RX_HI_MASK)

#define XCVR_TSM_TIMING04_IRQ1_STOP_TRIG_RX_LO_MASK (0xFF000000U)
#define XCVR_TSM_TIMING04_IRQ1_STOP_TRIG_RX_LO_SHIFT (24U)
/*! IRQ1_STOP_TRIG_RX_LO - De-assertion time setting for IRQ1_STOP_TRIG (RX)
 */
#define XCVR_TSM_TIMING04_IRQ1_STOP_TRIG_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING04_IRQ1_STOP_TRIG_RX_LO_SHIFT)) & XCVR_TSM_TIMING04_IRQ1_STOP_TRIG_RX_LO_MASK)
/*! @} */

/*! @name TIMING05 - TSM_TIMING05 */
/*! @{ */

#define XCVR_TSM_TIMING05_GPIO0_TRIG_EN_TX_HI_MASK (0xFFU)
#define XCVR_TSM_TIMING05_GPIO0_TRIG_EN_TX_HI_SHIFT (0U)
/*! GPIO0_TRIG_EN_TX_HI - Assertion time setting for GPIO0_TRIG_EN (TX)
 */
#define XCVR_TSM_TIMING05_GPIO0_TRIG_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING05_GPIO0_TRIG_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING05_GPIO0_TRIG_EN_TX_HI_MASK)

#define XCVR_TSM_TIMING05_GPIO0_TRIG_EN_TX_LO_MASK (0xFF00U)
#define XCVR_TSM_TIMING05_GPIO0_TRIG_EN_TX_LO_SHIFT (8U)
/*! GPIO0_TRIG_EN_TX_LO - De-assertion time setting for GPIO0_TRIG_EN (TX)
 */
#define XCVR_TSM_TIMING05_GPIO0_TRIG_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING05_GPIO0_TRIG_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING05_GPIO0_TRIG_EN_TX_LO_MASK)

#define XCVR_TSM_TIMING05_GPIO0_TRIG_EN_RX_HI_MASK (0xFF0000U)
#define XCVR_TSM_TIMING05_GPIO0_TRIG_EN_RX_HI_SHIFT (16U)
/*! GPIO0_TRIG_EN_RX_HI - Assertion time setting for GPIO0_TRIG_EN (RX)
 */
#define XCVR_TSM_TIMING05_GPIO0_TRIG_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING05_GPIO0_TRIG_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING05_GPIO0_TRIG_EN_RX_HI_MASK)

#define XCVR_TSM_TIMING05_GPIO0_TRIG_EN_RX_LO_MASK (0xFF000000U)
#define XCVR_TSM_TIMING05_GPIO0_TRIG_EN_RX_LO_SHIFT (24U)
/*! GPIO0_TRIG_EN_RX_LO - De-assertion time setting for GPIO0_TRIG_EN (RX)
 */
#define XCVR_TSM_TIMING05_GPIO0_TRIG_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING05_GPIO0_TRIG_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING05_GPIO0_TRIG_EN_RX_LO_MASK)
/*! @} */

/*! @name TIMING06 - TSM_TIMING06 */
/*! @{ */

#define XCVR_TSM_TIMING06_GPIO1_TRIG_EN_TX_HI_MASK (0xFFU)
#define XCVR_TSM_TIMING06_GPIO1_TRIG_EN_TX_HI_SHIFT (0U)
/*! GPIO1_TRIG_EN_TX_HI - Assertion time setting for GPIO1_TRIG_EN (TX)
 */
#define XCVR_TSM_TIMING06_GPIO1_TRIG_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING06_GPIO1_TRIG_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING06_GPIO1_TRIG_EN_TX_HI_MASK)

#define XCVR_TSM_TIMING06_GPIO1_TRIG_EN_TX_LO_MASK (0xFF00U)
#define XCVR_TSM_TIMING06_GPIO1_TRIG_EN_TX_LO_SHIFT (8U)
/*! GPIO1_TRIG_EN_TX_LO - De-assertion time setting for GPIO1_TRIG_EN (TX)
 */
#define XCVR_TSM_TIMING06_GPIO1_TRIG_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING06_GPIO1_TRIG_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING06_GPIO1_TRIG_EN_TX_LO_MASK)

#define XCVR_TSM_TIMING06_GPIO1_TRIG_EN_RX_HI_MASK (0xFF0000U)
#define XCVR_TSM_TIMING06_GPIO1_TRIG_EN_RX_HI_SHIFT (16U)
/*! GPIO1_TRIG_EN_RX_HI - Assertion time setting for GPIO1_TRIG_EN (RX)
 */
#define XCVR_TSM_TIMING06_GPIO1_TRIG_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING06_GPIO1_TRIG_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING06_GPIO1_TRIG_EN_RX_HI_MASK)

#define XCVR_TSM_TIMING06_GPIO1_TRIG_EN_RX_LO_MASK (0xFF000000U)
#define XCVR_TSM_TIMING06_GPIO1_TRIG_EN_RX_LO_SHIFT (24U)
/*! GPIO1_TRIG_EN_RX_LO - De-assertion time setting for GPIO1_TRIG_EN (RX)
 */
#define XCVR_TSM_TIMING06_GPIO1_TRIG_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING06_GPIO1_TRIG_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING06_GPIO1_TRIG_EN_RX_LO_MASK)
/*! @} */

/*! @name TIMING07 - TSM_TIMING07 */
/*! @{ */

#define XCVR_TSM_TIMING07_GPIO2_TRIG_EN_TX_HI_MASK (0xFFU)
#define XCVR_TSM_TIMING07_GPIO2_TRIG_EN_TX_HI_SHIFT (0U)
/*! GPIO2_TRIG_EN_TX_HI - Assertion time setting for GPIO2_TRIG_EN (TX)
 */
#define XCVR_TSM_TIMING07_GPIO2_TRIG_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING07_GPIO2_TRIG_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING07_GPIO2_TRIG_EN_TX_HI_MASK)

#define XCVR_TSM_TIMING07_GPIO2_TRIG_EN_TX_LO_MASK (0xFF00U)
#define XCVR_TSM_TIMING07_GPIO2_TRIG_EN_TX_LO_SHIFT (8U)
/*! GPIO2_TRIG_EN_TX_LO - De-assertion time setting for GPIO2_TRIG_EN (TX)
 */
#define XCVR_TSM_TIMING07_GPIO2_TRIG_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING07_GPIO2_TRIG_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING07_GPIO2_TRIG_EN_TX_LO_MASK)

#define XCVR_TSM_TIMING07_GPIO2_TRIG_EN_RX_HI_MASK (0xFF0000U)
#define XCVR_TSM_TIMING07_GPIO2_TRIG_EN_RX_HI_SHIFT (16U)
/*! GPIO2_TRIG_EN_RX_HI - Assertion time setting for GPIO2_TRIG_EN (RX)
 */
#define XCVR_TSM_TIMING07_GPIO2_TRIG_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING07_GPIO2_TRIG_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING07_GPIO2_TRIG_EN_RX_HI_MASK)

#define XCVR_TSM_TIMING07_GPIO2_TRIG_EN_RX_LO_MASK (0xFF000000U)
#define XCVR_TSM_TIMING07_GPIO2_TRIG_EN_RX_LO_SHIFT (24U)
/*! GPIO2_TRIG_EN_RX_LO - De-assertion time setting for GPIO2_TRIG_EN (RX)
 */
#define XCVR_TSM_TIMING07_GPIO2_TRIG_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING07_GPIO2_TRIG_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING07_GPIO2_TRIG_EN_RX_LO_MASK)
/*! @} */

/*! @name TIMING08 - TSM_TIMING08 */
/*! @{ */

#define XCVR_TSM_TIMING08_GPIO3_TRIG_EN_TX_HI_MASK (0xFFU)
#define XCVR_TSM_TIMING08_GPIO3_TRIG_EN_TX_HI_SHIFT (0U)
/*! GPIO3_TRIG_EN_TX_HI - Assertion time setting for GPIO3_TRIG_EN (TX)
 */
#define XCVR_TSM_TIMING08_GPIO3_TRIG_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING08_GPIO3_TRIG_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING08_GPIO3_TRIG_EN_TX_HI_MASK)

#define XCVR_TSM_TIMING08_GPIO3_TRIG_EN_TX_LO_MASK (0xFF00U)
#define XCVR_TSM_TIMING08_GPIO3_TRIG_EN_TX_LO_SHIFT (8U)
/*! GPIO3_TRIG_EN_TX_LO - De-assertion time setting for GPIO3_TRIG_EN (TX)
 */
#define XCVR_TSM_TIMING08_GPIO3_TRIG_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING08_GPIO3_TRIG_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING08_GPIO3_TRIG_EN_TX_LO_MASK)

#define XCVR_TSM_TIMING08_GPIO3_TRIG_EN_RX_HI_MASK (0xFF0000U)
#define XCVR_TSM_TIMING08_GPIO3_TRIG_EN_RX_HI_SHIFT (16U)
/*! GPIO3_TRIG_EN_RX_HI - Assertion time setting for GPIO3_TRIG_EN (RX)
 */
#define XCVR_TSM_TIMING08_GPIO3_TRIG_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING08_GPIO3_TRIG_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING08_GPIO3_TRIG_EN_RX_HI_MASK)

#define XCVR_TSM_TIMING08_GPIO3_TRIG_EN_RX_LO_MASK (0xFF000000U)
#define XCVR_TSM_TIMING08_GPIO3_TRIG_EN_RX_LO_SHIFT (24U)
/*! GPIO3_TRIG_EN_RX_LO - De-assertion time setting for GPIO3_TRIG_EN (RX)
 */
#define XCVR_TSM_TIMING08_GPIO3_TRIG_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING08_GPIO3_TRIG_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING08_GPIO3_TRIG_EN_RX_LO_MASK)
/*! @} */

/*! @name TIMING09 - TSM_TIMING09 */
/*! @{ */

#define XCVR_TSM_TIMING09_DCOC_GAIN_CFG_EN_TX_HI_MASK (0xFFU)
#define XCVR_TSM_TIMING09_DCOC_GAIN_CFG_EN_TX_HI_SHIFT (0U)
/*! DCOC_GAIN_CFG_EN_TX_HI - Assertion time setting for DCOC_GAIN_CFG_EN (TX)
 */
#define XCVR_TSM_TIMING09_DCOC_GAIN_CFG_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING09_DCOC_GAIN_CFG_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING09_DCOC_GAIN_CFG_EN_TX_HI_MASK)

#define XCVR_TSM_TIMING09_DCOC_GAIN_CFG_EN_TX_LO_MASK (0xFF00U)
#define XCVR_TSM_TIMING09_DCOC_GAIN_CFG_EN_TX_LO_SHIFT (8U)
/*! DCOC_GAIN_CFG_EN_TX_LO - De-assertion time setting for DCOC_GAIN_CFG_EN (TX)
 */
#define XCVR_TSM_TIMING09_DCOC_GAIN_CFG_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING09_DCOC_GAIN_CFG_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING09_DCOC_GAIN_CFG_EN_TX_LO_MASK)

#define XCVR_TSM_TIMING09_DCOC_GAIN_CFG_EN_RX_HI_MASK (0xFF0000U)
#define XCVR_TSM_TIMING09_DCOC_GAIN_CFG_EN_RX_HI_SHIFT (16U)
/*! DCOC_GAIN_CFG_EN_RX_HI - Assertion time setting for DCOC_GAIN_CFG_EN (RX)
 */
#define XCVR_TSM_TIMING09_DCOC_GAIN_CFG_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING09_DCOC_GAIN_CFG_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING09_DCOC_GAIN_CFG_EN_RX_HI_MASK)

#define XCVR_TSM_TIMING09_DCOC_GAIN_CFG_EN_RX_LO_MASK (0xFF000000U)
#define XCVR_TSM_TIMING09_DCOC_GAIN_CFG_EN_RX_LO_SHIFT (24U)
/*! DCOC_GAIN_CFG_EN_RX_LO - De-assertion time setting for DCOC_GAIN_CFG_EN (RX)
 */
#define XCVR_TSM_TIMING09_DCOC_GAIN_CFG_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING09_DCOC_GAIN_CFG_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING09_DCOC_GAIN_CFG_EN_RX_LO_MASK)
/*! @} */

/*! @name TIMING10 - TSM_TIMING10 */
/*! @{ */

#define XCVR_TSM_TIMING10_LDO_CAL_EN_TX_HI_MASK  (0xFFU)
#define XCVR_TSM_TIMING10_LDO_CAL_EN_TX_HI_SHIFT (0U)
/*! LDO_CAL_EN_TX_HI - Assertion time setting for LDO_CAL_EN (TX)
 */
#define XCVR_TSM_TIMING10_LDO_CAL_EN_TX_HI(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING10_LDO_CAL_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING10_LDO_CAL_EN_TX_HI_MASK)

#define XCVR_TSM_TIMING10_LDO_CAL_EN_TX_LO_MASK  (0xFF00U)
#define XCVR_TSM_TIMING10_LDO_CAL_EN_TX_LO_SHIFT (8U)
/*! LDO_CAL_EN_TX_LO - De-assertion time setting for LDO_CAL_EN (TX)
 */
#define XCVR_TSM_TIMING10_LDO_CAL_EN_TX_LO(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING10_LDO_CAL_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING10_LDO_CAL_EN_TX_LO_MASK)

#define XCVR_TSM_TIMING10_LDO_CAL_EN_RX_HI_MASK  (0xFF0000U)
#define XCVR_TSM_TIMING10_LDO_CAL_EN_RX_HI_SHIFT (16U)
/*! LDO_CAL_EN_RX_HI - Assertion time setting for LDO_CAL_EN (RX)
 */
#define XCVR_TSM_TIMING10_LDO_CAL_EN_RX_HI(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING10_LDO_CAL_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING10_LDO_CAL_EN_RX_HI_MASK)

#define XCVR_TSM_TIMING10_LDO_CAL_EN_RX_LO_MASK  (0xFF000000U)
#define XCVR_TSM_TIMING10_LDO_CAL_EN_RX_LO_SHIFT (24U)
/*! LDO_CAL_EN_RX_LO - De-assertion time setting for LDO_CAL_EN (RX)
 */
#define XCVR_TSM_TIMING10_LDO_CAL_EN_RX_LO(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING10_LDO_CAL_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING10_LDO_CAL_EN_RX_LO_MASK)
/*! @} */

/*! @name TIMING11 - TSM_TIMING11 */
/*! @{ */

#define XCVR_TSM_TIMING11_PLL_DIG_EN_TX_HI_MASK  (0xFFU)
#define XCVR_TSM_TIMING11_PLL_DIG_EN_TX_HI_SHIFT (0U)
/*! PLL_DIG_EN_TX_HI - Assertion time setting for PLL_DIG_EN (TX)
 */
#define XCVR_TSM_TIMING11_PLL_DIG_EN_TX_HI(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING11_PLL_DIG_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING11_PLL_DIG_EN_TX_HI_MASK)

#define XCVR_TSM_TIMING11_PLL_DIG_EN_TX_LO_MASK  (0xFF00U)
#define XCVR_TSM_TIMING11_PLL_DIG_EN_TX_LO_SHIFT (8U)
/*! PLL_DIG_EN_TX_LO - De-assertion time setting for PLL_DIG_EN (TX)
 */
#define XCVR_TSM_TIMING11_PLL_DIG_EN_TX_LO(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING11_PLL_DIG_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING11_PLL_DIG_EN_TX_LO_MASK)

#define XCVR_TSM_TIMING11_PLL_DIG_EN_RX_HI_MASK  (0xFF0000U)
#define XCVR_TSM_TIMING11_PLL_DIG_EN_RX_HI_SHIFT (16U)
/*! PLL_DIG_EN_RX_HI - Assertion time setting for PLL_DIG_EN (RX)
 */
#define XCVR_TSM_TIMING11_PLL_DIG_EN_RX_HI(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING11_PLL_DIG_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING11_PLL_DIG_EN_RX_HI_MASK)

#define XCVR_TSM_TIMING11_PLL_DIG_EN_RX_LO_MASK  (0xFF000000U)
#define XCVR_TSM_TIMING11_PLL_DIG_EN_RX_LO_SHIFT (24U)
/*! PLL_DIG_EN_RX_LO - De-assertion time setting for PLL_DIG_EN (RX)
 */
#define XCVR_TSM_TIMING11_PLL_DIG_EN_RX_LO(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING11_PLL_DIG_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING11_PLL_DIG_EN_RX_LO_MASK)
/*! @} */

/*! @name TIMING12 - TSM_TIMING12 */
/*! @{ */

#define XCVR_TSM_TIMING12_SIGMA_DELTA_EN_TX_HI_MASK (0xFFU)
#define XCVR_TSM_TIMING12_SIGMA_DELTA_EN_TX_HI_SHIFT (0U)
/*! SIGMA_DELTA_EN_TX_HI - Assertion time setting for SIGMA_DELTA_EN (TX)
 */
#define XCVR_TSM_TIMING12_SIGMA_DELTA_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING12_SIGMA_DELTA_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING12_SIGMA_DELTA_EN_TX_HI_MASK)

#define XCVR_TSM_TIMING12_SIGMA_DELTA_EN_TX_LO_MASK (0xFF00U)
#define XCVR_TSM_TIMING12_SIGMA_DELTA_EN_TX_LO_SHIFT (8U)
/*! SIGMA_DELTA_EN_TX_LO - De-assertion time setting for SIGMA_DELTA_EN (TX)
 */
#define XCVR_TSM_TIMING12_SIGMA_DELTA_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING12_SIGMA_DELTA_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING12_SIGMA_DELTA_EN_TX_LO_MASK)

#define XCVR_TSM_TIMING12_SIGMA_DELTA_EN_RX_HI_MASK (0xFF0000U)
#define XCVR_TSM_TIMING12_SIGMA_DELTA_EN_RX_HI_SHIFT (16U)
/*! SIGMA_DELTA_EN_RX_HI - Assertion time setting for SIGMA_DELTA_EN (RX)
 */
#define XCVR_TSM_TIMING12_SIGMA_DELTA_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING12_SIGMA_DELTA_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING12_SIGMA_DELTA_EN_RX_HI_MASK)

#define XCVR_TSM_TIMING12_SIGMA_DELTA_EN_RX_LO_MASK (0xFF000000U)
#define XCVR_TSM_TIMING12_SIGMA_DELTA_EN_RX_LO_SHIFT (24U)
/*! SIGMA_DELTA_EN_RX_LO - De-assertion time setting for SIGMA_DELTA_EN (RX)
 */
#define XCVR_TSM_TIMING12_SIGMA_DELTA_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING12_SIGMA_DELTA_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING12_SIGMA_DELTA_EN_RX_LO_MASK)
/*! @} */

/*! @name TIMING13 - TSM_TIMING13 */
/*! @{ */

#define XCVR_TSM_TIMING13_DCOC_CAL_EN_TX_HI_MASK (0xFFU)
#define XCVR_TSM_TIMING13_DCOC_CAL_EN_TX_HI_SHIFT (0U)
/*! DCOC_CAL_EN_TX_HI - Assertion time setting for DCOC_CAL_EN (TX)
 */
#define XCVR_TSM_TIMING13_DCOC_CAL_EN_TX_HI(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING13_DCOC_CAL_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING13_DCOC_CAL_EN_TX_HI_MASK)

#define XCVR_TSM_TIMING13_DCOC_CAL_EN_TX_LO_MASK (0xFF00U)
#define XCVR_TSM_TIMING13_DCOC_CAL_EN_TX_LO_SHIFT (8U)
/*! DCOC_CAL_EN_TX_LO - De-assertion time setting for DCOC_CAL_EN (TX)
 */
#define XCVR_TSM_TIMING13_DCOC_CAL_EN_TX_LO(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING13_DCOC_CAL_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING13_DCOC_CAL_EN_TX_LO_MASK)

#define XCVR_TSM_TIMING13_DCOC_CAL_EN_RX_HI_MASK (0xFF0000U)
#define XCVR_TSM_TIMING13_DCOC_CAL_EN_RX_HI_SHIFT (16U)
/*! DCOC_CAL_EN_RX_HI - Assertion time setting for DCOC_CAL_EN (RX)
 */
#define XCVR_TSM_TIMING13_DCOC_CAL_EN_RX_HI(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING13_DCOC_CAL_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING13_DCOC_CAL_EN_RX_HI_MASK)

#define XCVR_TSM_TIMING13_DCOC_CAL_EN_RX_LO_MASK (0xFF000000U)
#define XCVR_TSM_TIMING13_DCOC_CAL_EN_RX_LO_SHIFT (24U)
/*! DCOC_CAL_EN_RX_LO - De-assertion time setting for DCOC_CAL_EN (RX)
 */
#define XCVR_TSM_TIMING13_DCOC_CAL_EN_RX_LO(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING13_DCOC_CAL_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING13_DCOC_CAL_EN_RX_LO_MASK)
/*! @} */

/*! @name TIMING14 - TSM_TIMING14 */
/*! @{ */

#define XCVR_TSM_TIMING14_TX_DIG_EN_TX_HI_MASK   (0xFFU)
#define XCVR_TSM_TIMING14_TX_DIG_EN_TX_HI_SHIFT  (0U)
/*! TX_DIG_EN_TX_HI - Assertion time setting for TX_DIG_EN (TX)
 */
#define XCVR_TSM_TIMING14_TX_DIG_EN_TX_HI(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING14_TX_DIG_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING14_TX_DIG_EN_TX_HI_MASK)

#define XCVR_TSM_TIMING14_TX_DIG_EN_TX_LO_MASK   (0xFF00U)
#define XCVR_TSM_TIMING14_TX_DIG_EN_TX_LO_SHIFT  (8U)
/*! TX_DIG_EN_TX_LO - De-assertion time setting for TX_DIG_EN (TX)
 */
#define XCVR_TSM_TIMING14_TX_DIG_EN_TX_LO(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING14_TX_DIG_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING14_TX_DIG_EN_TX_LO_MASK)
/*! @} */

/*! @name TIMING15 - TSM_TIMING15 */
/*! @{ */

#define XCVR_TSM_TIMING15_FREQ_TARG_LD_EN_TX_HI_MASK (0xFFU)
#define XCVR_TSM_TIMING15_FREQ_TARG_LD_EN_TX_HI_SHIFT (0U)
/*! FREQ_TARG_LD_EN_TX_HI - Assertion time setting for FREQ_TARG_LD_EN (TX)
 */
#define XCVR_TSM_TIMING15_FREQ_TARG_LD_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING15_FREQ_TARG_LD_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING15_FREQ_TARG_LD_EN_TX_HI_MASK)

#define XCVR_TSM_TIMING15_FREQ_TARG_LD_EN_TX_LO_MASK (0xFF00U)
#define XCVR_TSM_TIMING15_FREQ_TARG_LD_EN_TX_LO_SHIFT (8U)
/*! FREQ_TARG_LD_EN_TX_LO - De-assertion time setting for FREQ_TARG_LD_EN (TX)
 */
#define XCVR_TSM_TIMING15_FREQ_TARG_LD_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING15_FREQ_TARG_LD_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING15_FREQ_TARG_LD_EN_TX_LO_MASK)

#define XCVR_TSM_TIMING15_FREQ_TARG_LD_EN_RX_HI_MASK (0xFF0000U)
#define XCVR_TSM_TIMING15_FREQ_TARG_LD_EN_RX_HI_SHIFT (16U)
/*! FREQ_TARG_LD_EN_RX_HI - Assertion time setting for FREQ_TARG_LD_EN (RX)
 */
#define XCVR_TSM_TIMING15_FREQ_TARG_LD_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING15_FREQ_TARG_LD_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING15_FREQ_TARG_LD_EN_RX_HI_MASK)

#define XCVR_TSM_TIMING15_FREQ_TARG_LD_EN_RX_LO_MASK (0xFF000000U)
#define XCVR_TSM_TIMING15_FREQ_TARG_LD_EN_RX_LO_SHIFT (24U)
/*! FREQ_TARG_LD_EN_RX_LO - De-assertion time setting for FREQ_TARG_LD_EN (RX)
 */
#define XCVR_TSM_TIMING15_FREQ_TARG_LD_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING15_FREQ_TARG_LD_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING15_FREQ_TARG_LD_EN_RX_LO_MASK)
/*! @} */

/*! @name TIMING16 - TSM_TIMING16 */
/*! @{ */

#define XCVR_TSM_TIMING16_RX_INIT_RX_HI_MASK     (0xFF0000U)
#define XCVR_TSM_TIMING16_RX_INIT_RX_HI_SHIFT    (16U)
/*! RX_INIT_RX_HI - Assertion time setting for RX_INIT (RX)
 */
#define XCVR_TSM_TIMING16_RX_INIT_RX_HI(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING16_RX_INIT_RX_HI_SHIFT)) & XCVR_TSM_TIMING16_RX_INIT_RX_HI_MASK)

#define XCVR_TSM_TIMING16_RX_INIT_RX_LO_MASK     (0xFF000000U)
#define XCVR_TSM_TIMING16_RX_INIT_RX_LO_SHIFT    (24U)
/*! RX_INIT_RX_LO - De-assertion time setting for RX_INIT (RX)
 */
#define XCVR_TSM_TIMING16_RX_INIT_RX_LO(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING16_RX_INIT_RX_LO_SHIFT)) & XCVR_TSM_TIMING16_RX_INIT_RX_LO_MASK)
/*! @} */

/*! @name TIMING17 - TSM_TIMING17 */
/*! @{ */

#define XCVR_TSM_TIMING17_RX_DIG_EN_RX_HI_MASK   (0xFF0000U)
#define XCVR_TSM_TIMING17_RX_DIG_EN_RX_HI_SHIFT  (16U)
/*! RX_DIG_EN_RX_HI - Assertion time setting for RX_DIG_EN (RX)
 */
#define XCVR_TSM_TIMING17_RX_DIG_EN_RX_HI(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING17_RX_DIG_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING17_RX_DIG_EN_RX_HI_MASK)

#define XCVR_TSM_TIMING17_RX_DIG_EN_RX_LO_MASK   (0xFF000000U)
#define XCVR_TSM_TIMING17_RX_DIG_EN_RX_LO_SHIFT  (24U)
/*! RX_DIG_EN_RX_LO - De-assertion time setting for RX_DIG_EN (RX)
 */
#define XCVR_TSM_TIMING17_RX_DIG_EN_RX_LO(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING17_RX_DIG_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING17_RX_DIG_EN_RX_LO_MASK)
/*! @} */

/*! @name TIMING18 - TSM_TIMING18 */
/*! @{ */

#define XCVR_TSM_TIMING18_RX_PHY_EN_RX_HI_MASK   (0xFF0000U)
#define XCVR_TSM_TIMING18_RX_PHY_EN_RX_HI_SHIFT  (16U)
/*! RX_PHY_EN_RX_HI - Assertion time setting for RX_PHY_EN (RX)
 */
#define XCVR_TSM_TIMING18_RX_PHY_EN_RX_HI(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING18_RX_PHY_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING18_RX_PHY_EN_RX_HI_MASK)

#define XCVR_TSM_TIMING18_RX_PHY_EN_RX_LO_MASK   (0xFF000000U)
#define XCVR_TSM_TIMING18_RX_PHY_EN_RX_LO_SHIFT  (24U)
/*! RX_PHY_EN_RX_LO - De-assertion time setting for RX_PHY_EN (RX)
 */
#define XCVR_TSM_TIMING18_RX_PHY_EN_RX_LO(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING18_RX_PHY_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING18_RX_PHY_EN_RX_LO_MASK)
/*! @} */

/*! @name TIMING19 - TSM_TIMING19 */
/*! @{ */

#define XCVR_TSM_TIMING19_SEQ_BG_PUP_IBG_CAL_TX_HI_MASK (0xFFU)
#define XCVR_TSM_TIMING19_SEQ_BG_PUP_IBG_CAL_TX_HI_SHIFT (0U)
/*! SEQ_BG_PUP_IBG_CAL_TX_HI - Assertion time setting for SEQ_BG_PUP_IBG_CAL (TX)
 */
#define XCVR_TSM_TIMING19_SEQ_BG_PUP_IBG_CAL_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING19_SEQ_BG_PUP_IBG_CAL_TX_HI_SHIFT)) & XCVR_TSM_TIMING19_SEQ_BG_PUP_IBG_CAL_TX_HI_MASK)

#define XCVR_TSM_TIMING19_SEQ_BG_PUP_IBG_CAL_TX_LO_MASK (0xFF00U)
#define XCVR_TSM_TIMING19_SEQ_BG_PUP_IBG_CAL_TX_LO_SHIFT (8U)
/*! SEQ_BG_PUP_IBG_CAL_TX_LO - De-assertion time setting for SEQ_BG_PUP_IBG_CAL (TX)
 */
#define XCVR_TSM_TIMING19_SEQ_BG_PUP_IBG_CAL_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING19_SEQ_BG_PUP_IBG_CAL_TX_LO_SHIFT)) & XCVR_TSM_TIMING19_SEQ_BG_PUP_IBG_CAL_TX_LO_MASK)

#define XCVR_TSM_TIMING19_SEQ_BG_PUP_IBG_CAL_RX_HI_MASK (0xFF0000U)
#define XCVR_TSM_TIMING19_SEQ_BG_PUP_IBG_CAL_RX_HI_SHIFT (16U)
/*! SEQ_BG_PUP_IBG_CAL_RX_HI - Assertion time setting for SEQ_BG_PUP_IBG_CAL (RX)
 */
#define XCVR_TSM_TIMING19_SEQ_BG_PUP_IBG_CAL_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING19_SEQ_BG_PUP_IBG_CAL_RX_HI_SHIFT)) & XCVR_TSM_TIMING19_SEQ_BG_PUP_IBG_CAL_RX_HI_MASK)

#define XCVR_TSM_TIMING19_SEQ_BG_PUP_IBG_CAL_RX_LO_MASK (0xFF000000U)
#define XCVR_TSM_TIMING19_SEQ_BG_PUP_IBG_CAL_RX_LO_SHIFT (24U)
/*! SEQ_BG_PUP_IBG_CAL_RX_LO - De-assertion time setting for SEQ_BG_PUP_IBG_CAL (RX)
 */
#define XCVR_TSM_TIMING19_SEQ_BG_PUP_IBG_CAL_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING19_SEQ_BG_PUP_IBG_CAL_RX_LO_SHIFT)) & XCVR_TSM_TIMING19_SEQ_BG_PUP_IBG_CAL_RX_LO_MASK)
/*! @} */

/*! @name TIMING20 - TSM_TIMING20 */
/*! @{ */

#define XCVR_TSM_TIMING20_SEQ_LDOTRIM_PUP_TX_HI_MASK (0xFFU)
#define XCVR_TSM_TIMING20_SEQ_LDOTRIM_PUP_TX_HI_SHIFT (0U)
/*! SEQ_LDOTRIM_PUP_TX_HI - Assertion time setting for SEQ_LDOTRIM_PUP (TX)
 */
#define XCVR_TSM_TIMING20_SEQ_LDOTRIM_PUP_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING20_SEQ_LDOTRIM_PUP_TX_HI_SHIFT)) & XCVR_TSM_TIMING20_SEQ_LDOTRIM_PUP_TX_HI_MASK)

#define XCVR_TSM_TIMING20_SEQ_LDOTRIM_PUP_TX_LO_MASK (0xFF00U)
#define XCVR_TSM_TIMING20_SEQ_LDOTRIM_PUP_TX_LO_SHIFT (8U)
/*! SEQ_LDOTRIM_PUP_TX_LO - De-assertion time setting for SEQ_LDOTRIM_PUP (TX)
 */
#define XCVR_TSM_TIMING20_SEQ_LDOTRIM_PUP_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING20_SEQ_LDOTRIM_PUP_TX_LO_SHIFT)) & XCVR_TSM_TIMING20_SEQ_LDOTRIM_PUP_TX_LO_MASK)

#define XCVR_TSM_TIMING20_SEQ_LDOTRIM_PUP_RX_HI_MASK (0xFF0000U)
#define XCVR_TSM_TIMING20_SEQ_LDOTRIM_PUP_RX_HI_SHIFT (16U)
/*! SEQ_LDOTRIM_PUP_RX_HI - Assertion time setting for SEQ_LDOTRIM_PUP (RX)
 */
#define XCVR_TSM_TIMING20_SEQ_LDOTRIM_PUP_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING20_SEQ_LDOTRIM_PUP_RX_HI_SHIFT)) & XCVR_TSM_TIMING20_SEQ_LDOTRIM_PUP_RX_HI_MASK)

#define XCVR_TSM_TIMING20_SEQ_LDOTRIM_PUP_RX_LO_MASK (0xFF000000U)
#define XCVR_TSM_TIMING20_SEQ_LDOTRIM_PUP_RX_LO_SHIFT (24U)
/*! SEQ_LDOTRIM_PUP_RX_LO - De-assertion time setting for SEQ_LDOTRIM_PUP (RX)
 */
#define XCVR_TSM_TIMING20_SEQ_LDOTRIM_PUP_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING20_SEQ_LDOTRIM_PUP_RX_LO_SHIFT)) & XCVR_TSM_TIMING20_SEQ_LDOTRIM_PUP_RX_LO_MASK)
/*! @} */

/*! @name TIMING21 - TSM_TIMING21 */
/*! @{ */

#define XCVR_TSM_TIMING21_SEQ_LDO_CAL_PUP_TX_HI_MASK (0xFFU)
#define XCVR_TSM_TIMING21_SEQ_LDO_CAL_PUP_TX_HI_SHIFT (0U)
/*! SEQ_LDO_CAL_PUP_TX_HI - Assertion time setting for SEQ_LDO_CAL_PUP (TX)
 */
#define XCVR_TSM_TIMING21_SEQ_LDO_CAL_PUP_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING21_SEQ_LDO_CAL_PUP_TX_HI_SHIFT)) & XCVR_TSM_TIMING21_SEQ_LDO_CAL_PUP_TX_HI_MASK)

#define XCVR_TSM_TIMING21_SEQ_LDO_CAL_PUP_TX_LO_MASK (0xFF00U)
#define XCVR_TSM_TIMING21_SEQ_LDO_CAL_PUP_TX_LO_SHIFT (8U)
/*! SEQ_LDO_CAL_PUP_TX_LO - De-assertion time setting for SEQ_LDO_CAL_PUP (TX)
 */
#define XCVR_TSM_TIMING21_SEQ_LDO_CAL_PUP_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING21_SEQ_LDO_CAL_PUP_TX_LO_SHIFT)) & XCVR_TSM_TIMING21_SEQ_LDO_CAL_PUP_TX_LO_MASK)

#define XCVR_TSM_TIMING21_SEQ_LDO_CAL_PUP_RX_HI_MASK (0xFF0000U)
#define XCVR_TSM_TIMING21_SEQ_LDO_CAL_PUP_RX_HI_SHIFT (16U)
/*! SEQ_LDO_CAL_PUP_RX_HI - Assertion time setting for SEQ_LDO_CAL_PUP (RX)
 */
#define XCVR_TSM_TIMING21_SEQ_LDO_CAL_PUP_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING21_SEQ_LDO_CAL_PUP_RX_HI_SHIFT)) & XCVR_TSM_TIMING21_SEQ_LDO_CAL_PUP_RX_HI_MASK)

#define XCVR_TSM_TIMING21_SEQ_LDO_CAL_PUP_RX_LO_MASK (0xFF000000U)
#define XCVR_TSM_TIMING21_SEQ_LDO_CAL_PUP_RX_LO_SHIFT (24U)
/*! SEQ_LDO_CAL_PUP_RX_LO - De-assertion time setting for SEQ_LDO_CAL_PUP (RX)
 */
#define XCVR_TSM_TIMING21_SEQ_LDO_CAL_PUP_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING21_SEQ_LDO_CAL_PUP_RX_LO_SHIFT)) & XCVR_TSM_TIMING21_SEQ_LDO_CAL_PUP_RX_LO_MASK)
/*! @} */

/*! @name TIMING22 - TSM_TIMING22 */
/*! @{ */

#define XCVR_TSM_TIMING22_SEQ_BG_FC_TX_HI_MASK   (0xFFU)
#define XCVR_TSM_TIMING22_SEQ_BG_FC_TX_HI_SHIFT  (0U)
/*! SEQ_BG_FC_TX_HI - Assertion time setting for SEQ_BG_FC (TX)
 */
#define XCVR_TSM_TIMING22_SEQ_BG_FC_TX_HI(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING22_SEQ_BG_FC_TX_HI_SHIFT)) & XCVR_TSM_TIMING22_SEQ_BG_FC_TX_HI_MASK)

#define XCVR_TSM_TIMING22_SEQ_BG_FC_TX_LO_MASK   (0xFF00U)
#define XCVR_TSM_TIMING22_SEQ_BG_FC_TX_LO_SHIFT  (8U)
/*! SEQ_BG_FC_TX_LO - De-assertion time setting for SEQ_BG_FC (TX)
 */
#define XCVR_TSM_TIMING22_SEQ_BG_FC_TX_LO(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING22_SEQ_BG_FC_TX_LO_SHIFT)) & XCVR_TSM_TIMING22_SEQ_BG_FC_TX_LO_MASK)

#define XCVR_TSM_TIMING22_SEQ_BG_FC_RX_HI_MASK   (0xFF0000U)
#define XCVR_TSM_TIMING22_SEQ_BG_FC_RX_HI_SHIFT  (16U)
/*! SEQ_BG_FC_RX_HI - Assertion time setting for SEQ_BG_FC (RX)
 */
#define XCVR_TSM_TIMING22_SEQ_BG_FC_RX_HI(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING22_SEQ_BG_FC_RX_HI_SHIFT)) & XCVR_TSM_TIMING22_SEQ_BG_FC_RX_HI_MASK)

#define XCVR_TSM_TIMING22_SEQ_BG_FC_RX_LO_MASK   (0xFF000000U)
#define XCVR_TSM_TIMING22_SEQ_BG_FC_RX_LO_SHIFT  (24U)
/*! SEQ_BG_FC_RX_LO - De-assertion time setting for SEQ_BG_FC (RX)
 */
#define XCVR_TSM_TIMING22_SEQ_BG_FC_RX_LO(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING22_SEQ_BG_FC_RX_LO_SHIFT)) & XCVR_TSM_TIMING22_SEQ_BG_FC_RX_LO_MASK)
/*! @} */

/*! @name TIMING23 - TSM_TIMING23 */
/*! @{ */

#define XCVR_TSM_TIMING23_SEQ_LDO_GANG_FC_TX_HI_MASK (0xFFU)
#define XCVR_TSM_TIMING23_SEQ_LDO_GANG_FC_TX_HI_SHIFT (0U)
/*! SEQ_LDO_GANG_FC_TX_HI - Assertion time setting for SEQ_LDO_GANG_FC (TX)
 */
#define XCVR_TSM_TIMING23_SEQ_LDO_GANG_FC_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING23_SEQ_LDO_GANG_FC_TX_HI_SHIFT)) & XCVR_TSM_TIMING23_SEQ_LDO_GANG_FC_TX_HI_MASK)

#define XCVR_TSM_TIMING23_SEQ_LDO_GANG_FC_TX_LO_MASK (0xFF00U)
#define XCVR_TSM_TIMING23_SEQ_LDO_GANG_FC_TX_LO_SHIFT (8U)
/*! SEQ_LDO_GANG_FC_TX_LO - De-assertion time setting for SEQ_LDO_(PLL/RXTXHF/RXTXLF/VCO)_FC (TX)
 */
#define XCVR_TSM_TIMING23_SEQ_LDO_GANG_FC_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING23_SEQ_LDO_GANG_FC_TX_LO_SHIFT)) & XCVR_TSM_TIMING23_SEQ_LDO_GANG_FC_TX_LO_MASK)

#define XCVR_TSM_TIMING23_SEQ_LDO_GANG_FC_RX_HI_MASK (0xFF0000U)
#define XCVR_TSM_TIMING23_SEQ_LDO_GANG_FC_RX_HI_SHIFT (16U)
/*! SEQ_LDO_GANG_FC_RX_HI - Assertion time setting for SEQ_LDO_(PLL/RXTXHF/RXTXLF/VCO)_FC (RX)
 */
#define XCVR_TSM_TIMING23_SEQ_LDO_GANG_FC_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING23_SEQ_LDO_GANG_FC_RX_HI_SHIFT)) & XCVR_TSM_TIMING23_SEQ_LDO_GANG_FC_RX_HI_MASK)

#define XCVR_TSM_TIMING23_SEQ_LDO_GANG_FC_RX_LO_MASK (0xFF000000U)
#define XCVR_TSM_TIMING23_SEQ_LDO_GANG_FC_RX_LO_SHIFT (24U)
/*! SEQ_LDO_GANG_FC_RX_LO - De-assertion time setting for SEQ_LDO_(PLL/RXTXHF/RXTXLF/VCO)_FC (RX)
 */
#define XCVR_TSM_TIMING23_SEQ_LDO_GANG_FC_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING23_SEQ_LDO_GANG_FC_RX_LO_SHIFT)) & XCVR_TSM_TIMING23_SEQ_LDO_GANG_FC_RX_LO_MASK)
/*! @} */

/*! @name TIMING24 - TSM_TIMING24 */
/*! @{ */

#define XCVR_TSM_TIMING24_SEQ_LDO_GANG_PUP_TX_HI_MASK (0xFFU)
#define XCVR_TSM_TIMING24_SEQ_LDO_GANG_PUP_TX_HI_SHIFT (0U)
/*! SEQ_LDO_GANG_PUP_TX_HI - Assertion time setting for SEQ_LDO_(ANT/PLL/RXTXHF/RXTXLF/VCO/XO_DIST)_PUP (TX)
 */
#define XCVR_TSM_TIMING24_SEQ_LDO_GANG_PUP_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING24_SEQ_LDO_GANG_PUP_TX_HI_SHIFT)) & XCVR_TSM_TIMING24_SEQ_LDO_GANG_PUP_TX_HI_MASK)

#define XCVR_TSM_TIMING24_SEQ_LDO_GANG_PUP_TX_LO_MASK (0xFF00U)
#define XCVR_TSM_TIMING24_SEQ_LDO_GANG_PUP_TX_LO_SHIFT (8U)
/*! SEQ_LDO_GANG_PUP_TX_LO - De-assertion time setting for SEQ_LDO_(ANT/PLL/RXTXHF/RXTXLF/VCO/XO_DIST)_PUP (TX)
 */
#define XCVR_TSM_TIMING24_SEQ_LDO_GANG_PUP_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING24_SEQ_LDO_GANG_PUP_TX_LO_SHIFT)) & XCVR_TSM_TIMING24_SEQ_LDO_GANG_PUP_TX_LO_MASK)

#define XCVR_TSM_TIMING24_SEQ_LDO_GANG_PUP_RX_HI_MASK (0xFF0000U)
#define XCVR_TSM_TIMING24_SEQ_LDO_GANG_PUP_RX_HI_SHIFT (16U)
/*! SEQ_LDO_GANG_PUP_RX_HI - Assertion time setting for SEQ_LDO_(ANT/PLL/RXTXHF/RXTXLF/VCO/XO_DIST)_PUP (RX)
 */
#define XCVR_TSM_TIMING24_SEQ_LDO_GANG_PUP_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING24_SEQ_LDO_GANG_PUP_RX_HI_SHIFT)) & XCVR_TSM_TIMING24_SEQ_LDO_GANG_PUP_RX_HI_MASK)

#define XCVR_TSM_TIMING24_SEQ_LDO_GANG_PUP_RX_LO_MASK (0xFF000000U)
#define XCVR_TSM_TIMING24_SEQ_LDO_GANG_PUP_RX_LO_SHIFT (24U)
/*! SEQ_LDO_GANG_PUP_RX_LO - De-assertion time setting for SEQ_LDO_(ANT/PLL/RXTXHF/RXTXLF/VCO/XO_DIST)_PUP (RX)
 */
#define XCVR_TSM_TIMING24_SEQ_LDO_GANG_PUP_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING24_SEQ_LDO_GANG_PUP_RX_LO_SHIFT)) & XCVR_TSM_TIMING24_SEQ_LDO_GANG_PUP_RX_LO_MASK)
/*! @} */

/*! @name TIMING25 - TSM_TIMING25 */
/*! @{ */

#define XCVR_TSM_TIMING25_SEQ_LDO_LV_PUP_TX_HI_MASK (0xFFU)
#define XCVR_TSM_TIMING25_SEQ_LDO_LV_PUP_TX_HI_SHIFT (0U)
/*! SEQ_LDO_LV_PUP_TX_HI - Assertion time setting for SEQ_LDO_LV_PUP (TX)
 */
#define XCVR_TSM_TIMING25_SEQ_LDO_LV_PUP_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING25_SEQ_LDO_LV_PUP_TX_HI_SHIFT)) & XCVR_TSM_TIMING25_SEQ_LDO_LV_PUP_TX_HI_MASK)

#define XCVR_TSM_TIMING25_SEQ_LDO_LV_PUP_TX_LO_MASK (0xFF00U)
#define XCVR_TSM_TIMING25_SEQ_LDO_LV_PUP_TX_LO_SHIFT (8U)
/*! SEQ_LDO_LV_PUP_TX_LO - De-assertion time setting for SEQ_LDO_LV_PUP (TX)
 */
#define XCVR_TSM_TIMING25_SEQ_LDO_LV_PUP_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING25_SEQ_LDO_LV_PUP_TX_LO_SHIFT)) & XCVR_TSM_TIMING25_SEQ_LDO_LV_PUP_TX_LO_MASK)

#define XCVR_TSM_TIMING25_SEQ_LDO_LV_PUP_RX_HI_MASK (0xFF0000U)
#define XCVR_TSM_TIMING25_SEQ_LDO_LV_PUP_RX_HI_SHIFT (16U)
/*! SEQ_LDO_LV_PUP_RX_HI - Assertion time setting for SEQ_LDO_LV_PUP (RX)
 */
#define XCVR_TSM_TIMING25_SEQ_LDO_LV_PUP_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING25_SEQ_LDO_LV_PUP_RX_HI_SHIFT)) & XCVR_TSM_TIMING25_SEQ_LDO_LV_PUP_RX_HI_MASK)

#define XCVR_TSM_TIMING25_SEQ_LDO_LV_PUP_RX_LO_MASK (0xFF000000U)
#define XCVR_TSM_TIMING25_SEQ_LDO_LV_PUP_RX_LO_SHIFT (24U)
/*! SEQ_LDO_LV_PUP_RX_LO - De-assertion time setting for SEQ_LDO_LV_PUP (RX)
 */
#define XCVR_TSM_TIMING25_SEQ_LDO_LV_PUP_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING25_SEQ_LDO_LV_PUP_RX_LO_SHIFT)) & XCVR_TSM_TIMING25_SEQ_LDO_LV_PUP_RX_LO_MASK)
/*! @} */

/*! @name TIMING26 - TSM_TIMING26 */
/*! @{ */

#define XCVR_TSM_TIMING26_SEQ_BG_PUP_TX_HI_MASK  (0xFFU)
#define XCVR_TSM_TIMING26_SEQ_BG_PUP_TX_HI_SHIFT (0U)
/*! SEQ_BG_PUP_TX_HI - Assertion time setting for SEQ_BG_PUP (TX)
 */
#define XCVR_TSM_TIMING26_SEQ_BG_PUP_TX_HI(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING26_SEQ_BG_PUP_TX_HI_SHIFT)) & XCVR_TSM_TIMING26_SEQ_BG_PUP_TX_HI_MASK)

#define XCVR_TSM_TIMING26_SEQ_BG_PUP_TX_LO_MASK  (0xFF00U)
#define XCVR_TSM_TIMING26_SEQ_BG_PUP_TX_LO_SHIFT (8U)
/*! SEQ_BG_PUP_TX_LO - De-assertion time setting for SEQ_BG_PUP (TX)
 */
#define XCVR_TSM_TIMING26_SEQ_BG_PUP_TX_LO(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING26_SEQ_BG_PUP_TX_LO_SHIFT)) & XCVR_TSM_TIMING26_SEQ_BG_PUP_TX_LO_MASK)

#define XCVR_TSM_TIMING26_SEQ_BG_PUP_RX_HI_MASK  (0xFF0000U)
#define XCVR_TSM_TIMING26_SEQ_BG_PUP_RX_HI_SHIFT (16U)
/*! SEQ_BG_PUP_RX_HI - Assertion time setting for SEQ_BG_PUP (RX)
 */
#define XCVR_TSM_TIMING26_SEQ_BG_PUP_RX_HI(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING26_SEQ_BG_PUP_RX_HI_SHIFT)) & XCVR_TSM_TIMING26_SEQ_BG_PUP_RX_HI_MASK)

#define XCVR_TSM_TIMING26_SEQ_BG_PUP_RX_LO_MASK  (0xFF000000U)
#define XCVR_TSM_TIMING26_SEQ_BG_PUP_RX_LO_SHIFT (24U)
/*! SEQ_BG_PUP_RX_LO - De-assertion time setting for SEQ_BG_PUP (RX)
 */
#define XCVR_TSM_TIMING26_SEQ_BG_PUP_RX_LO(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING26_SEQ_BG_PUP_RX_LO_SHIFT)) & XCVR_TSM_TIMING26_SEQ_BG_PUP_RX_LO_MASK)
/*! @} */

/*! @name TIMING27 - TSM_TIMING27 */
/*! @{ */

#define XCVR_TSM_TIMING27_SEQ_BG_PUP_IBG_ANT_TX_HI_MASK (0xFFU)
#define XCVR_TSM_TIMING27_SEQ_BG_PUP_IBG_ANT_TX_HI_SHIFT (0U)
/*! SEQ_BG_PUP_IBG_ANT_TX_HI - Assertion time setting for SEQ_BG_PUP_IBG_ANT (TX)
 */
#define XCVR_TSM_TIMING27_SEQ_BG_PUP_IBG_ANT_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING27_SEQ_BG_PUP_IBG_ANT_TX_HI_SHIFT)) & XCVR_TSM_TIMING27_SEQ_BG_PUP_IBG_ANT_TX_HI_MASK)

#define XCVR_TSM_TIMING27_SEQ_BG_PUP_IBG_ANT_TX_LO_MASK (0xFF00U)
#define XCVR_TSM_TIMING27_SEQ_BG_PUP_IBG_ANT_TX_LO_SHIFT (8U)
/*! SEQ_BG_PUP_IBG_ANT_TX_LO - De-assertion time setting for SEQ_BG_PUP_IBG_ANT (TX)
 */
#define XCVR_TSM_TIMING27_SEQ_BG_PUP_IBG_ANT_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING27_SEQ_BG_PUP_IBG_ANT_TX_LO_SHIFT)) & XCVR_TSM_TIMING27_SEQ_BG_PUP_IBG_ANT_TX_LO_MASK)

#define XCVR_TSM_TIMING27_SEQ_BG_PUP_IBG_ANT_RX_HI_MASK (0xFF0000U)
#define XCVR_TSM_TIMING27_SEQ_BG_PUP_IBG_ANT_RX_HI_SHIFT (16U)
/*! SEQ_BG_PUP_IBG_ANT_RX_HI - Assertion time setting for SEQ_BG_PUP_IBG_ANT (RX)
 */
#define XCVR_TSM_TIMING27_SEQ_BG_PUP_IBG_ANT_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING27_SEQ_BG_PUP_IBG_ANT_RX_HI_SHIFT)) & XCVR_TSM_TIMING27_SEQ_BG_PUP_IBG_ANT_RX_HI_MASK)

#define XCVR_TSM_TIMING27_SEQ_BG_PUP_IBG_ANT_RX_LO_MASK (0xFF000000U)
#define XCVR_TSM_TIMING27_SEQ_BG_PUP_IBG_ANT_RX_LO_SHIFT (24U)
/*! SEQ_BG_PUP_IBG_ANT_RX_LO - De-assertion time setting for SEQ_BG_PUP_IBG_ANT (RX)
 */
#define XCVR_TSM_TIMING27_SEQ_BG_PUP_IBG_ANT_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING27_SEQ_BG_PUP_IBG_ANT_RX_LO_SHIFT)) & XCVR_TSM_TIMING27_SEQ_BG_PUP_IBG_ANT_RX_LO_MASK)
/*! @} */

/*! @name TIMING28 - TSM_TIMING28 */
/*! @{ */

#define XCVR_TSM_TIMING28_SEQ_BG_PUP_IBG_XO_DIST_TX_HI_MASK (0xFFU)
#define XCVR_TSM_TIMING28_SEQ_BG_PUP_IBG_XO_DIST_TX_HI_SHIFT (0U)
/*! SEQ_BG_PUP_IBG_XO_DIST_TX_HI - Assertion time setting for SEQ_BG_PUP_IBG_XO_DIST (TX)
 */
#define XCVR_TSM_TIMING28_SEQ_BG_PUP_IBG_XO_DIST_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING28_SEQ_BG_PUP_IBG_XO_DIST_TX_HI_SHIFT)) & XCVR_TSM_TIMING28_SEQ_BG_PUP_IBG_XO_DIST_TX_HI_MASK)

#define XCVR_TSM_TIMING28_SEQ_BG_PUP_IBG_XO_DIST_TX_LO_MASK (0xFF00U)
#define XCVR_TSM_TIMING28_SEQ_BG_PUP_IBG_XO_DIST_TX_LO_SHIFT (8U)
/*! SEQ_BG_PUP_IBG_XO_DIST_TX_LO - De-assertion time setting for SEQ_BG_PUP_IBG_XO_DIST (TX)
 */
#define XCVR_TSM_TIMING28_SEQ_BG_PUP_IBG_XO_DIST_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING28_SEQ_BG_PUP_IBG_XO_DIST_TX_LO_SHIFT)) & XCVR_TSM_TIMING28_SEQ_BG_PUP_IBG_XO_DIST_TX_LO_MASK)

#define XCVR_TSM_TIMING28_SEQ_BG_PUP_IBG_XO_DIST_RX_HI_MASK (0xFF0000U)
#define XCVR_TSM_TIMING28_SEQ_BG_PUP_IBG_XO_DIST_RX_HI_SHIFT (16U)
/*! SEQ_BG_PUP_IBG_XO_DIST_RX_HI - Assertion time setting for SEQ_BG_PUP_IBG_XO_DIST (RX)
 */
#define XCVR_TSM_TIMING28_SEQ_BG_PUP_IBG_XO_DIST_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING28_SEQ_BG_PUP_IBG_XO_DIST_RX_HI_SHIFT)) & XCVR_TSM_TIMING28_SEQ_BG_PUP_IBG_XO_DIST_RX_HI_MASK)

#define XCVR_TSM_TIMING28_SEQ_BG_PUP_IBG_XO_DIST_RX_LO_MASK (0xFF000000U)
#define XCVR_TSM_TIMING28_SEQ_BG_PUP_IBG_XO_DIST_RX_LO_SHIFT (24U)
/*! SEQ_BG_PUP_IBG_XO_DIST_RX_LO - De-assertion time setting for SEQ_BG_PUP_IBG_XO_DIST (RX)
 */
#define XCVR_TSM_TIMING28_SEQ_BG_PUP_IBG_XO_DIST_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING28_SEQ_BG_PUP_IBG_XO_DIST_RX_LO_SHIFT)) & XCVR_TSM_TIMING28_SEQ_BG_PUP_IBG_XO_DIST_RX_LO_MASK)
/*! @} */

/*! @name TIMING29 - TSM_TIMING29 */
/*! @{ */

#define XCVR_TSM_TIMING29_SEQ_BG_PUP_IBG_TX_TX_HI_MASK (0xFFU)
#define XCVR_TSM_TIMING29_SEQ_BG_PUP_IBG_TX_TX_HI_SHIFT (0U)
/*! SEQ_BG_PUP_IBG_TX_TX_HI - Assertion time setting for SEQ_BG_PUP_IBG_TX (TX)
 */
#define XCVR_TSM_TIMING29_SEQ_BG_PUP_IBG_TX_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING29_SEQ_BG_PUP_IBG_TX_TX_HI_SHIFT)) & XCVR_TSM_TIMING29_SEQ_BG_PUP_IBG_TX_TX_HI_MASK)

#define XCVR_TSM_TIMING29_SEQ_BG_PUP_IBG_TX_TX_LO_MASK (0xFF00U)
#define XCVR_TSM_TIMING29_SEQ_BG_PUP_IBG_TX_TX_LO_SHIFT (8U)
/*! SEQ_BG_PUP_IBG_TX_TX_LO - De-assertion time setting for SEQ_BG_PUP_IBG_TX (TX)
 */
#define XCVR_TSM_TIMING29_SEQ_BG_PUP_IBG_TX_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING29_SEQ_BG_PUP_IBG_TX_TX_LO_SHIFT)) & XCVR_TSM_TIMING29_SEQ_BG_PUP_IBG_TX_TX_LO_MASK)

#define XCVR_TSM_TIMING29_SEQ_BG_PUP_IBG_TX_RX_HI_MASK (0xFF0000U)
#define XCVR_TSM_TIMING29_SEQ_BG_PUP_IBG_TX_RX_HI_SHIFT (16U)
/*! SEQ_BG_PUP_IBG_TX_RX_HI - Assertion time setting for SEQ_BG_PUP_IBG_TX (RX)
 */
#define XCVR_TSM_TIMING29_SEQ_BG_PUP_IBG_TX_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING29_SEQ_BG_PUP_IBG_TX_RX_HI_SHIFT)) & XCVR_TSM_TIMING29_SEQ_BG_PUP_IBG_TX_RX_HI_MASK)

#define XCVR_TSM_TIMING29_SEQ_BG_PUP_IBG_TX_RX_LO_MASK (0xFF000000U)
#define XCVR_TSM_TIMING29_SEQ_BG_PUP_IBG_TX_RX_LO_SHIFT (24U)
/*! SEQ_BG_PUP_IBG_TX_RX_LO - De-assertion time setting for SEQ_BG_PUP_IBG_TX (RX)
 */
#define XCVR_TSM_TIMING29_SEQ_BG_PUP_IBG_TX_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING29_SEQ_BG_PUP_IBG_TX_RX_LO_SHIFT)) & XCVR_TSM_TIMING29_SEQ_BG_PUP_IBG_TX_RX_LO_MASK)
/*! @} */

/*! @name TIMING30 - TSM_TIMING30 */
/*! @{ */

#define XCVR_TSM_TIMING30_SEQ_BG_PUP_IBG_RX_TX_HI_MASK (0xFFU)
#define XCVR_TSM_TIMING30_SEQ_BG_PUP_IBG_RX_TX_HI_SHIFT (0U)
/*! SEQ_BG_PUP_IBG_RX_TX_HI - Assertion time setting for SEQ_BG_PUP_IBG_RX (TX)
 */
#define XCVR_TSM_TIMING30_SEQ_BG_PUP_IBG_RX_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING30_SEQ_BG_PUP_IBG_RX_TX_HI_SHIFT)) & XCVR_TSM_TIMING30_SEQ_BG_PUP_IBG_RX_TX_HI_MASK)

#define XCVR_TSM_TIMING30_SEQ_BG_PUP_IBG_RX_TX_LO_MASK (0xFF00U)
#define XCVR_TSM_TIMING30_SEQ_BG_PUP_IBG_RX_TX_LO_SHIFT (8U)
/*! SEQ_BG_PUP_IBG_RX_TX_LO - De-assertion time setting for SEQ_BG_PUP_IBG_RX (TX)
 */
#define XCVR_TSM_TIMING30_SEQ_BG_PUP_IBG_RX_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING30_SEQ_BG_PUP_IBG_RX_TX_LO_SHIFT)) & XCVR_TSM_TIMING30_SEQ_BG_PUP_IBG_RX_TX_LO_MASK)

#define XCVR_TSM_TIMING30_SEQ_BG_PUP_IBG_RX_RX_HI_MASK (0xFF0000U)
#define XCVR_TSM_TIMING30_SEQ_BG_PUP_IBG_RX_RX_HI_SHIFT (16U)
/*! SEQ_BG_PUP_IBG_RX_RX_HI - Assertion time setting for SEQ_BG_PUP_IBG_RX (RX)
 */
#define XCVR_TSM_TIMING30_SEQ_BG_PUP_IBG_RX_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING30_SEQ_BG_PUP_IBG_RX_RX_HI_SHIFT)) & XCVR_TSM_TIMING30_SEQ_BG_PUP_IBG_RX_RX_HI_MASK)

#define XCVR_TSM_TIMING30_SEQ_BG_PUP_IBG_RX_RX_LO_MASK (0xFF000000U)
#define XCVR_TSM_TIMING30_SEQ_BG_PUP_IBG_RX_RX_LO_SHIFT (24U)
/*! SEQ_BG_PUP_IBG_RX_RX_LO - De-assertion time setting for SEQ_BG_PUP_IBG_RX (RX)
 */
#define XCVR_TSM_TIMING30_SEQ_BG_PUP_IBG_RX_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING30_SEQ_BG_PUP_IBG_RX_RX_LO_SHIFT)) & XCVR_TSM_TIMING30_SEQ_BG_PUP_IBG_RX_RX_LO_MASK)
/*! @} */

/*! @name TIMING31 - TSM_TIMING31 */
/*! @{ */

#define XCVR_TSM_TIMING31_SEQ_TSM_ISO_B_2P4GHZ_TX_HI_MASK (0xFFU)
#define XCVR_TSM_TIMING31_SEQ_TSM_ISO_B_2P4GHZ_TX_HI_SHIFT (0U)
/*! SEQ_TSM_ISO_B_2P4GHZ_TX_HI - Assertion time setting for SEQ_TSM_ISO_B_2P4GHZ (TX)
 */
#define XCVR_TSM_TIMING31_SEQ_TSM_ISO_B_2P4GHZ_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING31_SEQ_TSM_ISO_B_2P4GHZ_TX_HI_SHIFT)) & XCVR_TSM_TIMING31_SEQ_TSM_ISO_B_2P4GHZ_TX_HI_MASK)

#define XCVR_TSM_TIMING31_SEQ_TSM_ISO_B_2P4GHZ_TX_LO_MASK (0xFF00U)
#define XCVR_TSM_TIMING31_SEQ_TSM_ISO_B_2P4GHZ_TX_LO_SHIFT (8U)
/*! SEQ_TSM_ISO_B_2P4GHZ_TX_LO - De-assertion time setting for SEQ_TSM_ISO_B_2P4GHZ (TX)
 */
#define XCVR_TSM_TIMING31_SEQ_TSM_ISO_B_2P4GHZ_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING31_SEQ_TSM_ISO_B_2P4GHZ_TX_LO_SHIFT)) & XCVR_TSM_TIMING31_SEQ_TSM_ISO_B_2P4GHZ_TX_LO_MASK)

#define XCVR_TSM_TIMING31_SEQ_TSM_ISO_B_2P4GHZ_RX_HI_MASK (0xFF0000U)
#define XCVR_TSM_TIMING31_SEQ_TSM_ISO_B_2P4GHZ_RX_HI_SHIFT (16U)
/*! SEQ_TSM_ISO_B_2P4GHZ_RX_HI - Assertion time setting for SEQ_TSM_ISO_B_2P4GHZ (RX)
 */
#define XCVR_TSM_TIMING31_SEQ_TSM_ISO_B_2P4GHZ_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING31_SEQ_TSM_ISO_B_2P4GHZ_RX_HI_SHIFT)) & XCVR_TSM_TIMING31_SEQ_TSM_ISO_B_2P4GHZ_RX_HI_MASK)

#define XCVR_TSM_TIMING31_SEQ_TSM_ISO_B_2P4GHZ_RX_LO_MASK (0xFF000000U)
#define XCVR_TSM_TIMING31_SEQ_TSM_ISO_B_2P4GHZ_RX_LO_SHIFT (24U)
/*! SEQ_TSM_ISO_B_2P4GHZ_RX_LO - De-assertion time setting for SEQ_TSM_ISO_B_2P4GHZ (RX)
 */
#define XCVR_TSM_TIMING31_SEQ_TSM_ISO_B_2P4GHZ_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING31_SEQ_TSM_ISO_B_2P4GHZ_RX_LO_SHIFT)) & XCVR_TSM_TIMING31_SEQ_TSM_ISO_B_2P4GHZ_RX_LO_MASK)
/*! @} */

/*! @name TIMING32 - TSM_TIMING32 */
/*! @{ */

#define XCVR_TSM_TIMING32_SEQ_RCCAL_PUP_TX_HI_MASK (0xFFU)
#define XCVR_TSM_TIMING32_SEQ_RCCAL_PUP_TX_HI_SHIFT (0U)
/*! SEQ_RCCAL_PUP_TX_HI - Assertion time setting for SEQ_RCCAL_PUP (TX)
 */
#define XCVR_TSM_TIMING32_SEQ_RCCAL_PUP_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING32_SEQ_RCCAL_PUP_TX_HI_SHIFT)) & XCVR_TSM_TIMING32_SEQ_RCCAL_PUP_TX_HI_MASK)

#define XCVR_TSM_TIMING32_SEQ_RCCAL_PUP_TX_LO_MASK (0xFF00U)
#define XCVR_TSM_TIMING32_SEQ_RCCAL_PUP_TX_LO_SHIFT (8U)
/*! SEQ_RCCAL_PUP_TX_LO - De-assertion time setting for SEQ_RCCAL_PUP (TX)
 */
#define XCVR_TSM_TIMING32_SEQ_RCCAL_PUP_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING32_SEQ_RCCAL_PUP_TX_LO_SHIFT)) & XCVR_TSM_TIMING32_SEQ_RCCAL_PUP_TX_LO_MASK)

#define XCVR_TSM_TIMING32_SEQ_RCCAL_PUP_RX_HI_MASK (0xFF0000U)
#define XCVR_TSM_TIMING32_SEQ_RCCAL_PUP_RX_HI_SHIFT (16U)
/*! SEQ_RCCAL_PUP_RX_HI - Assertion time setting for SEQ_RCCAL_PUP (RX)
 */
#define XCVR_TSM_TIMING32_SEQ_RCCAL_PUP_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING32_SEQ_RCCAL_PUP_RX_HI_SHIFT)) & XCVR_TSM_TIMING32_SEQ_RCCAL_PUP_RX_HI_MASK)

#define XCVR_TSM_TIMING32_SEQ_RCCAL_PUP_RX_LO_MASK (0xFF000000U)
#define XCVR_TSM_TIMING32_SEQ_RCCAL_PUP_RX_LO_SHIFT (24U)
/*! SEQ_RCCAL_PUP_RX_LO - De-assertion time setting for SEQ_RCCAL_PUP (RX)
 */
#define XCVR_TSM_TIMING32_SEQ_RCCAL_PUP_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING32_SEQ_RCCAL_PUP_RX_LO_SHIFT)) & XCVR_TSM_TIMING32_SEQ_RCCAL_PUP_RX_LO_MASK)
/*! @} */

/*! @name TIMING33 - TSM_TIMING33 */
/*! @{ */

#define XCVR_TSM_TIMING33_SEQ_PD_EN_FCAL_BIAS_TX_HI_MASK (0xFFU)
#define XCVR_TSM_TIMING33_SEQ_PD_EN_FCAL_BIAS_TX_HI_SHIFT (0U)
/*! SEQ_PD_EN_FCAL_BIAS_TX_HI - Assertion time setting for SEQ_PD_EN_FCAL_BIAS (TX)
 */
#define XCVR_TSM_TIMING33_SEQ_PD_EN_FCAL_BIAS_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING33_SEQ_PD_EN_FCAL_BIAS_TX_HI_SHIFT)) & XCVR_TSM_TIMING33_SEQ_PD_EN_FCAL_BIAS_TX_HI_MASK)

#define XCVR_TSM_TIMING33_SEQ_PD_EN_FCAL_BIAS_TX_LO_MASK (0xFF00U)
#define XCVR_TSM_TIMING33_SEQ_PD_EN_FCAL_BIAS_TX_LO_SHIFT (8U)
/*! SEQ_PD_EN_FCAL_BIAS_TX_LO - De-assertion time setting for SEQ_PD_EN_FCAL_BIAS (TX)
 */
#define XCVR_TSM_TIMING33_SEQ_PD_EN_FCAL_BIAS_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING33_SEQ_PD_EN_FCAL_BIAS_TX_LO_SHIFT)) & XCVR_TSM_TIMING33_SEQ_PD_EN_FCAL_BIAS_TX_LO_MASK)

#define XCVR_TSM_TIMING33_SEQ_PD_EN_FCAL_BIAS_RX_HI_MASK (0xFF0000U)
#define XCVR_TSM_TIMING33_SEQ_PD_EN_FCAL_BIAS_RX_HI_SHIFT (16U)
/*! SEQ_PD_EN_FCAL_BIAS_RX_HI - Assertion time setting for SEQ_PD_EN_FCAL_BIAS (RX)
 */
#define XCVR_TSM_TIMING33_SEQ_PD_EN_FCAL_BIAS_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING33_SEQ_PD_EN_FCAL_BIAS_RX_HI_SHIFT)) & XCVR_TSM_TIMING33_SEQ_PD_EN_FCAL_BIAS_RX_HI_MASK)

#define XCVR_TSM_TIMING33_SEQ_PD_EN_FCAL_BIAS_RX_LO_MASK (0xFF000000U)
#define XCVR_TSM_TIMING33_SEQ_PD_EN_FCAL_BIAS_RX_LO_SHIFT (24U)
/*! SEQ_PD_EN_FCAL_BIAS_RX_LO - De-assertion time setting for SEQ_PD_EN_FCAL_BIAS (RX)
 */
#define XCVR_TSM_TIMING33_SEQ_PD_EN_FCAL_BIAS_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING33_SEQ_PD_EN_FCAL_BIAS_RX_LO_SHIFT)) & XCVR_TSM_TIMING33_SEQ_PD_EN_FCAL_BIAS_RX_LO_MASK)
/*! @} */

/*! @name TIMING34 - TSM_TIMING34 */
/*! @{ */

#define XCVR_TSM_TIMING34_SEQ_PD_PUP_TX_HI_MASK  (0xFFU)
#define XCVR_TSM_TIMING34_SEQ_PD_PUP_TX_HI_SHIFT (0U)
/*! SEQ_PD_PUP_TX_HI - Assertion time setting for SEQ_PD_PUP (TX)
 */
#define XCVR_TSM_TIMING34_SEQ_PD_PUP_TX_HI(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING34_SEQ_PD_PUP_TX_HI_SHIFT)) & XCVR_TSM_TIMING34_SEQ_PD_PUP_TX_HI_MASK)

#define XCVR_TSM_TIMING34_SEQ_PD_PUP_TX_LO_MASK  (0xFF00U)
#define XCVR_TSM_TIMING34_SEQ_PD_PUP_TX_LO_SHIFT (8U)
/*! SEQ_PD_PUP_TX_LO - De-assertion time setting for SEQ_PD_PUP (TX)
 */
#define XCVR_TSM_TIMING34_SEQ_PD_PUP_TX_LO(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING34_SEQ_PD_PUP_TX_LO_SHIFT)) & XCVR_TSM_TIMING34_SEQ_PD_PUP_TX_LO_MASK)

#define XCVR_TSM_TIMING34_SEQ_PD_PUP_RX_HI_MASK  (0xFF0000U)
#define XCVR_TSM_TIMING34_SEQ_PD_PUP_RX_HI_SHIFT (16U)
/*! SEQ_PD_PUP_RX_HI - Assertion time setting for SEQ_PD_PUP (RX)
 */
#define XCVR_TSM_TIMING34_SEQ_PD_PUP_RX_HI(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING34_SEQ_PD_PUP_RX_HI_SHIFT)) & XCVR_TSM_TIMING34_SEQ_PD_PUP_RX_HI_MASK)

#define XCVR_TSM_TIMING34_SEQ_PD_PUP_RX_LO_MASK  (0xFF000000U)
#define XCVR_TSM_TIMING34_SEQ_PD_PUP_RX_LO_SHIFT (24U)
/*! SEQ_PD_PUP_RX_LO - De-assertion time setting for SEQ_PD_PUP (RX)
 */
#define XCVR_TSM_TIMING34_SEQ_PD_PUP_RX_LO(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING34_SEQ_PD_PUP_RX_LO_SHIFT)) & XCVR_TSM_TIMING34_SEQ_PD_PUP_RX_LO_MASK)
/*! @} */

/*! @name TIMING35 - TSM_TIMING35 */
/*! @{ */

#define XCVR_TSM_TIMING35_SEQ_VCO_PUP_TX_HI_MASK (0xFFU)
#define XCVR_TSM_TIMING35_SEQ_VCO_PUP_TX_HI_SHIFT (0U)
/*! SEQ_VCO_PUP_TX_HI - Assertion time setting for SEQ_VCO_PUP (TX)
 */
#define XCVR_TSM_TIMING35_SEQ_VCO_PUP_TX_HI(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING35_SEQ_VCO_PUP_TX_HI_SHIFT)) & XCVR_TSM_TIMING35_SEQ_VCO_PUP_TX_HI_MASK)

#define XCVR_TSM_TIMING35_SEQ_VCO_PUP_TX_LO_MASK (0xFF00U)
#define XCVR_TSM_TIMING35_SEQ_VCO_PUP_TX_LO_SHIFT (8U)
/*! SEQ_VCO_PUP_TX_LO - De-assertion time setting for SEQ_VCO_PUP (TX)
 */
#define XCVR_TSM_TIMING35_SEQ_VCO_PUP_TX_LO(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING35_SEQ_VCO_PUP_TX_LO_SHIFT)) & XCVR_TSM_TIMING35_SEQ_VCO_PUP_TX_LO_MASK)

#define XCVR_TSM_TIMING35_SEQ_VCO_PUP_RX_HI_MASK (0xFF0000U)
#define XCVR_TSM_TIMING35_SEQ_VCO_PUP_RX_HI_SHIFT (16U)
/*! SEQ_VCO_PUP_RX_HI - Assertion time setting for SEQ_VCO_PUP (RX)
 */
#define XCVR_TSM_TIMING35_SEQ_VCO_PUP_RX_HI(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING35_SEQ_VCO_PUP_RX_HI_SHIFT)) & XCVR_TSM_TIMING35_SEQ_VCO_PUP_RX_HI_MASK)

#define XCVR_TSM_TIMING35_SEQ_VCO_PUP_RX_LO_MASK (0xFF000000U)
#define XCVR_TSM_TIMING35_SEQ_VCO_PUP_RX_LO_SHIFT (24U)
/*! SEQ_VCO_PUP_RX_LO - De-assertion time setting for SEQ_VCO_PUP (RX)
 */
#define XCVR_TSM_TIMING35_SEQ_VCO_PUP_RX_LO(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING35_SEQ_VCO_PUP_RX_LO_SHIFT)) & XCVR_TSM_TIMING35_SEQ_VCO_PUP_RX_LO_MASK)
/*! @} */

/*! @name TIMING36 - TSM_TIMING36 */
/*! @{ */

#define XCVR_TSM_TIMING36_SEQ_XO_DIST_EN_TX_HI_MASK (0xFFU)
#define XCVR_TSM_TIMING36_SEQ_XO_DIST_EN_TX_HI_SHIFT (0U)
/*! SEQ_XO_DIST_EN_TX_HI - Assertion time setting for SEQ_XO_DIST_EN (TX)
 */
#define XCVR_TSM_TIMING36_SEQ_XO_DIST_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING36_SEQ_XO_DIST_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING36_SEQ_XO_DIST_EN_TX_HI_MASK)

#define XCVR_TSM_TIMING36_SEQ_XO_DIST_EN_TX_LO_MASK (0xFF00U)
#define XCVR_TSM_TIMING36_SEQ_XO_DIST_EN_TX_LO_SHIFT (8U)
/*! SEQ_XO_DIST_EN_TX_LO - De-assertion time setting for SEQ_XO_DIST_EN (TX)
 */
#define XCVR_TSM_TIMING36_SEQ_XO_DIST_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING36_SEQ_XO_DIST_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING36_SEQ_XO_DIST_EN_TX_LO_MASK)

#define XCVR_TSM_TIMING36_SEQ_XO_DIST_EN_RX_HI_MASK (0xFF0000U)
#define XCVR_TSM_TIMING36_SEQ_XO_DIST_EN_RX_HI_SHIFT (16U)
/*! SEQ_XO_DIST_EN_RX_HI - Assertion time setting for SEQ_XO_DIST_EN (RX)
 */
#define XCVR_TSM_TIMING36_SEQ_XO_DIST_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING36_SEQ_XO_DIST_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING36_SEQ_XO_DIST_EN_RX_HI_MASK)

#define XCVR_TSM_TIMING36_SEQ_XO_DIST_EN_RX_LO_MASK (0xFF000000U)
#define XCVR_TSM_TIMING36_SEQ_XO_DIST_EN_RX_LO_SHIFT (24U)
/*! SEQ_XO_DIST_EN_RX_LO - De-assertion time setting for SEQ_XO_DIST_EN (RX)
 */
#define XCVR_TSM_TIMING36_SEQ_XO_DIST_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING36_SEQ_XO_DIST_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING36_SEQ_XO_DIST_EN_RX_LO_MASK)
/*! @} */

/*! @name TIMING37 - TSM_TIMING37 */
/*! @{ */

#define XCVR_TSM_TIMING37_SEQ_XO_DIST_EN_CLK_REF_TX_HI_MASK (0xFFU)
#define XCVR_TSM_TIMING37_SEQ_XO_DIST_EN_CLK_REF_TX_HI_SHIFT (0U)
/*! SEQ_XO_DIST_EN_CLK_REF_TX_HI - Assertion time setting for SEQ_XO_DIST_EN_CLK_REF (TX)
 */
#define XCVR_TSM_TIMING37_SEQ_XO_DIST_EN_CLK_REF_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING37_SEQ_XO_DIST_EN_CLK_REF_TX_HI_SHIFT)) & XCVR_TSM_TIMING37_SEQ_XO_DIST_EN_CLK_REF_TX_HI_MASK)

#define XCVR_TSM_TIMING37_SEQ_XO_DIST_EN_CLK_REF_TX_LO_MASK (0xFF00U)
#define XCVR_TSM_TIMING37_SEQ_XO_DIST_EN_CLK_REF_TX_LO_SHIFT (8U)
/*! SEQ_XO_DIST_EN_CLK_REF_TX_LO - De-assertion time setting for SEQ_XO_DIST_EN_CLK_REF (TX)
 */
#define XCVR_TSM_TIMING37_SEQ_XO_DIST_EN_CLK_REF_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING37_SEQ_XO_DIST_EN_CLK_REF_TX_LO_SHIFT)) & XCVR_TSM_TIMING37_SEQ_XO_DIST_EN_CLK_REF_TX_LO_MASK)

#define XCVR_TSM_TIMING37_SEQ_XO_DIST_EN_CLK_REF_RX_HI_MASK (0xFF0000U)
#define XCVR_TSM_TIMING37_SEQ_XO_DIST_EN_CLK_REF_RX_HI_SHIFT (16U)
/*! SEQ_XO_DIST_EN_CLK_REF_RX_HI - Assertion time setting for SEQ_XO_DIST_EN_CLK_REF (RX)
 */
#define XCVR_TSM_TIMING37_SEQ_XO_DIST_EN_CLK_REF_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING37_SEQ_XO_DIST_EN_CLK_REF_RX_HI_SHIFT)) & XCVR_TSM_TIMING37_SEQ_XO_DIST_EN_CLK_REF_RX_HI_MASK)

#define XCVR_TSM_TIMING37_SEQ_XO_DIST_EN_CLK_REF_RX_LO_MASK (0xFF000000U)
#define XCVR_TSM_TIMING37_SEQ_XO_DIST_EN_CLK_REF_RX_LO_SHIFT (24U)
/*! SEQ_XO_DIST_EN_CLK_REF_RX_LO - De-assertion time setting for SEQ_XO_DIST_EN_CLK_REF (RX)
 */
#define XCVR_TSM_TIMING37_SEQ_XO_DIST_EN_CLK_REF_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING37_SEQ_XO_DIST_EN_CLK_REF_RX_LO_SHIFT)) & XCVR_TSM_TIMING37_SEQ_XO_DIST_EN_CLK_REF_RX_LO_MASK)
/*! @} */

/*! @name TIMING38 - TSM_TIMING38 */
/*! @{ */

#define XCVR_TSM_TIMING38_SEQ_XO_EN_CLK_2P4G_TX_HI_MASK (0xFFU)
#define XCVR_TSM_TIMING38_SEQ_XO_EN_CLK_2P4G_TX_HI_SHIFT (0U)
/*! SEQ_XO_EN_CLK_2P4G_TX_HI - Assertion time setting for SEQ_XO_EN_CLK_2P4G (TX)
 */
#define XCVR_TSM_TIMING38_SEQ_XO_EN_CLK_2P4G_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING38_SEQ_XO_EN_CLK_2P4G_TX_HI_SHIFT)) & XCVR_TSM_TIMING38_SEQ_XO_EN_CLK_2P4G_TX_HI_MASK)

#define XCVR_TSM_TIMING38_SEQ_XO_EN_CLK_2P4G_TX_LO_MASK (0xFF00U)
#define XCVR_TSM_TIMING38_SEQ_XO_EN_CLK_2P4G_TX_LO_SHIFT (8U)
/*! SEQ_XO_EN_CLK_2P4G_TX_LO - De-assertion time setting for SEQ_XO_EN_CLK_2P4G (TX)
 */
#define XCVR_TSM_TIMING38_SEQ_XO_EN_CLK_2P4G_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING38_SEQ_XO_EN_CLK_2P4G_TX_LO_SHIFT)) & XCVR_TSM_TIMING38_SEQ_XO_EN_CLK_2P4G_TX_LO_MASK)

#define XCVR_TSM_TIMING38_SEQ_XO_EN_CLK_2P4G_RX_HI_MASK (0xFF0000U)
#define XCVR_TSM_TIMING38_SEQ_XO_EN_CLK_2P4G_RX_HI_SHIFT (16U)
/*! SEQ_XO_EN_CLK_2P4G_RX_HI - Assertion time setting for SEQ_XO_EN_CLK_2P4G (RX)
 */
#define XCVR_TSM_TIMING38_SEQ_XO_EN_CLK_2P4G_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING38_SEQ_XO_EN_CLK_2P4G_RX_HI_SHIFT)) & XCVR_TSM_TIMING38_SEQ_XO_EN_CLK_2P4G_RX_HI_MASK)

#define XCVR_TSM_TIMING38_SEQ_XO_EN_CLK_2P4G_RX_LO_MASK (0xFF000000U)
#define XCVR_TSM_TIMING38_SEQ_XO_EN_CLK_2P4G_RX_LO_SHIFT (24U)
/*! SEQ_XO_EN_CLK_2P4G_RX_LO - De-assertion time setting for SEQ_XO_EN_CLK_2P4G (RX)
 */
#define XCVR_TSM_TIMING38_SEQ_XO_EN_CLK_2P4G_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING38_SEQ_XO_EN_CLK_2P4G_RX_LO_SHIFT)) & XCVR_TSM_TIMING38_SEQ_XO_EN_CLK_2P4G_RX_LO_MASK)
/*! @} */

/*! @name TIMING39 - TSM_TIMING39 */
/*! @{ */

#define XCVR_TSM_TIMING39_SEQ_XO_DIST_EN_CLK_ADCDAC_TX_HI_MASK (0xFFU)
#define XCVR_TSM_TIMING39_SEQ_XO_DIST_EN_CLK_ADCDAC_TX_HI_SHIFT (0U)
/*! SEQ_XO_DIST_EN_CLK_ADCDAC_TX_HI - Assertion time setting for SEQ_XO_DIST_EN_CLK_ADCDAC (TX)
 */
#define XCVR_TSM_TIMING39_SEQ_XO_DIST_EN_CLK_ADCDAC_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING39_SEQ_XO_DIST_EN_CLK_ADCDAC_TX_HI_SHIFT)) & XCVR_TSM_TIMING39_SEQ_XO_DIST_EN_CLK_ADCDAC_TX_HI_MASK)

#define XCVR_TSM_TIMING39_SEQ_XO_DIST_EN_CLK_ADCDAC_TX_LO_MASK (0xFF00U)
#define XCVR_TSM_TIMING39_SEQ_XO_DIST_EN_CLK_ADCDAC_TX_LO_SHIFT (8U)
/*! SEQ_XO_DIST_EN_CLK_ADCDAC_TX_LO - De-assertion time setting for SEQ_XO_DIST_EN_CLK_ADCDAC (TX)
 */
#define XCVR_TSM_TIMING39_SEQ_XO_DIST_EN_CLK_ADCDAC_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING39_SEQ_XO_DIST_EN_CLK_ADCDAC_TX_LO_SHIFT)) & XCVR_TSM_TIMING39_SEQ_XO_DIST_EN_CLK_ADCDAC_TX_LO_MASK)

#define XCVR_TSM_TIMING39_SEQ_XO_DIST_EN_CLK_ADCDAC_RX_HI_MASK (0xFF0000U)
#define XCVR_TSM_TIMING39_SEQ_XO_DIST_EN_CLK_ADCDAC_RX_HI_SHIFT (16U)
/*! SEQ_XO_DIST_EN_CLK_ADCDAC_RX_HI - Assertion time setting for SEQ_XO_DIST_EN_CLK_ADCDAC (RX)
 */
#define XCVR_TSM_TIMING39_SEQ_XO_DIST_EN_CLK_ADCDAC_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING39_SEQ_XO_DIST_EN_CLK_ADCDAC_RX_HI_SHIFT)) & XCVR_TSM_TIMING39_SEQ_XO_DIST_EN_CLK_ADCDAC_RX_HI_MASK)

#define XCVR_TSM_TIMING39_SEQ_XO_DIST_EN_CLK_ADCDAC_RX_LO_MASK (0xFF000000U)
#define XCVR_TSM_TIMING39_SEQ_XO_DIST_EN_CLK_ADCDAC_RX_LO_SHIFT (24U)
/*! SEQ_XO_DIST_EN_CLK_ADCDAC_RX_LO - De-assertion time setting for SEQ_XO_DIST_EN_CLK_ADCDAC (RX)
 */
#define XCVR_TSM_TIMING39_SEQ_XO_DIST_EN_CLK_ADCDAC_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING39_SEQ_XO_DIST_EN_CLK_ADCDAC_RX_LO_SHIFT)) & XCVR_TSM_TIMING39_SEQ_XO_DIST_EN_CLK_ADCDAC_RX_LO_MASK)
/*! @} */

/*! @name TIMING40 - TSM_TIMING40 */
/*! @{ */

#define XCVR_TSM_TIMING40_SEQ_DAC_PUP_TX_HI_MASK (0xFFU)
#define XCVR_TSM_TIMING40_SEQ_DAC_PUP_TX_HI_SHIFT (0U)
/*! SEQ_DAC_PUP_TX_HI - Assertion time setting for SEQ_DAC_PUP (TX)
 */
#define XCVR_TSM_TIMING40_SEQ_DAC_PUP_TX_HI(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING40_SEQ_DAC_PUP_TX_HI_SHIFT)) & XCVR_TSM_TIMING40_SEQ_DAC_PUP_TX_HI_MASK)

#define XCVR_TSM_TIMING40_SEQ_DAC_PUP_TX_LO_MASK (0xFF00U)
#define XCVR_TSM_TIMING40_SEQ_DAC_PUP_TX_LO_SHIFT (8U)
/*! SEQ_DAC_PUP_TX_LO - De-assertion time setting for SEQ_DAC_PUP (TX)
 */
#define XCVR_TSM_TIMING40_SEQ_DAC_PUP_TX_LO(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING40_SEQ_DAC_PUP_TX_LO_SHIFT)) & XCVR_TSM_TIMING40_SEQ_DAC_PUP_TX_LO_MASK)

#define XCVR_TSM_TIMING40_SEQ_DAC_PUP_RX_HI_MASK (0xFF0000U)
#define XCVR_TSM_TIMING40_SEQ_DAC_PUP_RX_HI_SHIFT (16U)
/*! SEQ_DAC_PUP_RX_HI - Assertion time setting for SEQ_DAC_PUP (RX)
 */
#define XCVR_TSM_TIMING40_SEQ_DAC_PUP_RX_HI(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING40_SEQ_DAC_PUP_RX_HI_SHIFT)) & XCVR_TSM_TIMING40_SEQ_DAC_PUP_RX_HI_MASK)

#define XCVR_TSM_TIMING40_SEQ_DAC_PUP_RX_LO_MASK (0xFF000000U)
#define XCVR_TSM_TIMING40_SEQ_DAC_PUP_RX_LO_SHIFT (24U)
/*! SEQ_DAC_PUP_RX_LO - De-assertion time setting for SEQ_DAC_PUP (RX)
 */
#define XCVR_TSM_TIMING40_SEQ_DAC_PUP_RX_LO(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING40_SEQ_DAC_PUP_RX_LO_SHIFT)) & XCVR_TSM_TIMING40_SEQ_DAC_PUP_RX_LO_MASK)
/*! @} */

/*! @name TIMING41 - TSM_TIMING41 */
/*! @{ */

#define XCVR_TSM_TIMING41_SEQ_VCO_EN_HPM_TX_HI_MASK (0xFFU)
#define XCVR_TSM_TIMING41_SEQ_VCO_EN_HPM_TX_HI_SHIFT (0U)
/*! SEQ_VCO_EN_HPM_TX_HI - Assertion time setting for SEQ_VCO_EN_HPM (TX)
 */
#define XCVR_TSM_TIMING41_SEQ_VCO_EN_HPM_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING41_SEQ_VCO_EN_HPM_TX_HI_SHIFT)) & XCVR_TSM_TIMING41_SEQ_VCO_EN_HPM_TX_HI_MASK)

#define XCVR_TSM_TIMING41_SEQ_VCO_EN_HPM_TX_LO_MASK (0xFF00U)
#define XCVR_TSM_TIMING41_SEQ_VCO_EN_HPM_TX_LO_SHIFT (8U)
/*! SEQ_VCO_EN_HPM_TX_LO - De-assertion time setting for SEQ_VCO_EN_HPM (TX)
 */
#define XCVR_TSM_TIMING41_SEQ_VCO_EN_HPM_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING41_SEQ_VCO_EN_HPM_TX_LO_SHIFT)) & XCVR_TSM_TIMING41_SEQ_VCO_EN_HPM_TX_LO_MASK)

#define XCVR_TSM_TIMING41_SEQ_VCO_EN_HPM_RX_HI_MASK (0xFF0000U)
#define XCVR_TSM_TIMING41_SEQ_VCO_EN_HPM_RX_HI_SHIFT (16U)
/*! SEQ_VCO_EN_HPM_RX_HI - Assertion time setting for SEQ_VCO_EN_HPM (RX)
 */
#define XCVR_TSM_TIMING41_SEQ_VCO_EN_HPM_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING41_SEQ_VCO_EN_HPM_RX_HI_SHIFT)) & XCVR_TSM_TIMING41_SEQ_VCO_EN_HPM_RX_HI_MASK)

#define XCVR_TSM_TIMING41_SEQ_VCO_EN_HPM_RX_LO_MASK (0xFF000000U)
#define XCVR_TSM_TIMING41_SEQ_VCO_EN_HPM_RX_LO_SHIFT (24U)
/*! SEQ_VCO_EN_HPM_RX_LO - De-assertion time setting for SEQ_VCO_EN_HPM (RX)
 */
#define XCVR_TSM_TIMING41_SEQ_VCO_EN_HPM_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING41_SEQ_VCO_EN_HPM_RX_LO_SHIFT)) & XCVR_TSM_TIMING41_SEQ_VCO_EN_HPM_RX_LO_MASK)
/*! @} */

/*! @name TIMING42 - TSM_TIMING42 */
/*! @{ */

#define XCVR_TSM_TIMING42_SEQ_LO_PUP_VLO_FBK_TX_HI_MASK (0xFFU)
#define XCVR_TSM_TIMING42_SEQ_LO_PUP_VLO_FBK_TX_HI_SHIFT (0U)
/*! SEQ_LO_PUP_VLO_FBK_TX_HI - Assertion time setting for SEQ_LO_PUP_VLO_FBK (TX)
 */
#define XCVR_TSM_TIMING42_SEQ_LO_PUP_VLO_FBK_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING42_SEQ_LO_PUP_VLO_FBK_TX_HI_SHIFT)) & XCVR_TSM_TIMING42_SEQ_LO_PUP_VLO_FBK_TX_HI_MASK)

#define XCVR_TSM_TIMING42_SEQ_LO_PUP_VLO_FBK_TX_LO_MASK (0xFF00U)
#define XCVR_TSM_TIMING42_SEQ_LO_PUP_VLO_FBK_TX_LO_SHIFT (8U)
/*! SEQ_LO_PUP_VLO_FBK_TX_LO - De-assertion time setting for SEQ_LO_PUP_VLO_FBK (TX)
 */
#define XCVR_TSM_TIMING42_SEQ_LO_PUP_VLO_FBK_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING42_SEQ_LO_PUP_VLO_FBK_TX_LO_SHIFT)) & XCVR_TSM_TIMING42_SEQ_LO_PUP_VLO_FBK_TX_LO_MASK)

#define XCVR_TSM_TIMING42_SEQ_LO_PUP_VLO_FBK_RX_HI_MASK (0xFF0000U)
#define XCVR_TSM_TIMING42_SEQ_LO_PUP_VLO_FBK_RX_HI_SHIFT (16U)
/*! SEQ_LO_PUP_VLO_FBK_RX_HI - Assertion time setting for SEQ_LO_PUP_VLO_FBK (RX)
 */
#define XCVR_TSM_TIMING42_SEQ_LO_PUP_VLO_FBK_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING42_SEQ_LO_PUP_VLO_FBK_RX_HI_SHIFT)) & XCVR_TSM_TIMING42_SEQ_LO_PUP_VLO_FBK_RX_HI_MASK)

#define XCVR_TSM_TIMING42_SEQ_LO_PUP_VLO_FBK_RX_LO_MASK (0xFF000000U)
#define XCVR_TSM_TIMING42_SEQ_LO_PUP_VLO_FBK_RX_LO_SHIFT (24U)
/*! SEQ_LO_PUP_VLO_FBK_RX_LO - De-assertion time setting for SEQ_LO_PUP_VLO_FBK (RX)
 */
#define XCVR_TSM_TIMING42_SEQ_LO_PUP_VLO_FBK_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING42_SEQ_LO_PUP_VLO_FBK_RX_LO_SHIFT)) & XCVR_TSM_TIMING42_SEQ_LO_PUP_VLO_FBK_RX_LO_MASK)
/*! @} */

/*! @name TIMING43 - TSM_TIMING43 */
/*! @{ */

#define XCVR_TSM_TIMING43_SEQ_LO_PUP_VLO_RX_TX_HI_MASK (0xFFU)
#define XCVR_TSM_TIMING43_SEQ_LO_PUP_VLO_RX_TX_HI_SHIFT (0U)
/*! SEQ_LO_PUP_VLO_RX_TX_HI - Assertion time setting for SEQ_LO_PUP_VLO_RX (TX)
 */
#define XCVR_TSM_TIMING43_SEQ_LO_PUP_VLO_RX_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING43_SEQ_LO_PUP_VLO_RX_TX_HI_SHIFT)) & XCVR_TSM_TIMING43_SEQ_LO_PUP_VLO_RX_TX_HI_MASK)

#define XCVR_TSM_TIMING43_SEQ_LO_PUP_VLO_RX_TX_LO_MASK (0xFF00U)
#define XCVR_TSM_TIMING43_SEQ_LO_PUP_VLO_RX_TX_LO_SHIFT (8U)
/*! SEQ_LO_PUP_VLO_RX_TX_LO - De-assertion time setting for SEQ_LO_PUP_VLO_RX (TX)
 */
#define XCVR_TSM_TIMING43_SEQ_LO_PUP_VLO_RX_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING43_SEQ_LO_PUP_VLO_RX_TX_LO_SHIFT)) & XCVR_TSM_TIMING43_SEQ_LO_PUP_VLO_RX_TX_LO_MASK)

#define XCVR_TSM_TIMING43_SEQ_LO_PUP_VLO_RX_RX_HI_MASK (0xFF0000U)
#define XCVR_TSM_TIMING43_SEQ_LO_PUP_VLO_RX_RX_HI_SHIFT (16U)
/*! SEQ_LO_PUP_VLO_RX_RX_HI - Assertion time setting for SEQ_LO_PUP_VLO_RX (RX)
 */
#define XCVR_TSM_TIMING43_SEQ_LO_PUP_VLO_RX_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING43_SEQ_LO_PUP_VLO_RX_RX_HI_SHIFT)) & XCVR_TSM_TIMING43_SEQ_LO_PUP_VLO_RX_RX_HI_MASK)

#define XCVR_TSM_TIMING43_SEQ_LO_PUP_VLO_RX_RX_LO_MASK (0xFF000000U)
#define XCVR_TSM_TIMING43_SEQ_LO_PUP_VLO_RX_RX_LO_SHIFT (24U)
/*! SEQ_LO_PUP_VLO_RX_RX_LO - De-assertion time setting for SEQ_LO_PUP_VLO_RX (RX)
 */
#define XCVR_TSM_TIMING43_SEQ_LO_PUP_VLO_RX_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING43_SEQ_LO_PUP_VLO_RX_RX_LO_SHIFT)) & XCVR_TSM_TIMING43_SEQ_LO_PUP_VLO_RX_RX_LO_MASK)
/*! @} */

/*! @name TIMING44 - TSM_TIMING44 */
/*! @{ */

#define XCVR_TSM_TIMING44_SEQ_LO_PUP_VLO_RXDRV_TX_HI_MASK (0xFFU)
#define XCVR_TSM_TIMING44_SEQ_LO_PUP_VLO_RXDRV_TX_HI_SHIFT (0U)
/*! SEQ_LO_PUP_VLO_RXDRV_TX_HI - Assertion time setting for SEQ_LO_PUP_VLO_RXDRV (TX)
 */
#define XCVR_TSM_TIMING44_SEQ_LO_PUP_VLO_RXDRV_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING44_SEQ_LO_PUP_VLO_RXDRV_TX_HI_SHIFT)) & XCVR_TSM_TIMING44_SEQ_LO_PUP_VLO_RXDRV_TX_HI_MASK)

#define XCVR_TSM_TIMING44_SEQ_LO_PUP_VLO_RXDRV_TX_LO_MASK (0xFF00U)
#define XCVR_TSM_TIMING44_SEQ_LO_PUP_VLO_RXDRV_TX_LO_SHIFT (8U)
/*! SEQ_LO_PUP_VLO_RXDRV_TX_LO - De-assertion time setting for SEQ_LO_PUP_VLO_RXDRV (TX)
 */
#define XCVR_TSM_TIMING44_SEQ_LO_PUP_VLO_RXDRV_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING44_SEQ_LO_PUP_VLO_RXDRV_TX_LO_SHIFT)) & XCVR_TSM_TIMING44_SEQ_LO_PUP_VLO_RXDRV_TX_LO_MASK)

#define XCVR_TSM_TIMING44_SEQ_LO_PUP_VLO_RXDRV_RX_HI_MASK (0xFF0000U)
#define XCVR_TSM_TIMING44_SEQ_LO_PUP_VLO_RXDRV_RX_HI_SHIFT (16U)
/*! SEQ_LO_PUP_VLO_RXDRV_RX_HI - Assertion time setting for SEQ_LO_PUP_VLO_RXDRV (RX)
 */
#define XCVR_TSM_TIMING44_SEQ_LO_PUP_VLO_RXDRV_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING44_SEQ_LO_PUP_VLO_RXDRV_RX_HI_SHIFT)) & XCVR_TSM_TIMING44_SEQ_LO_PUP_VLO_RXDRV_RX_HI_MASK)

#define XCVR_TSM_TIMING44_SEQ_LO_PUP_VLO_RXDRV_RX_LO_MASK (0xFF000000U)
#define XCVR_TSM_TIMING44_SEQ_LO_PUP_VLO_RXDRV_RX_LO_SHIFT (24U)
/*! SEQ_LO_PUP_VLO_RXDRV_RX_LO - De-assertion time setting for SEQ_LO_PUP_VLO_RXDRV (RX)
 */
#define XCVR_TSM_TIMING44_SEQ_LO_PUP_VLO_RXDRV_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING44_SEQ_LO_PUP_VLO_RXDRV_RX_LO_SHIFT)) & XCVR_TSM_TIMING44_SEQ_LO_PUP_VLO_RXDRV_RX_LO_MASK)
/*! @} */

/*! @name TIMING45 - TSM_TIMING45 */
/*! @{ */

#define XCVR_TSM_TIMING45_SEQ_LO_PUP_VLO_TX_TX_HI_MASK (0xFFU)
#define XCVR_TSM_TIMING45_SEQ_LO_PUP_VLO_TX_TX_HI_SHIFT (0U)
/*! SEQ_LO_PUP_VLO_TX_TX_HI - Assertion time setting for SEQ_LO_PUP_VLO_TX (TX)
 */
#define XCVR_TSM_TIMING45_SEQ_LO_PUP_VLO_TX_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING45_SEQ_LO_PUP_VLO_TX_TX_HI_SHIFT)) & XCVR_TSM_TIMING45_SEQ_LO_PUP_VLO_TX_TX_HI_MASK)

#define XCVR_TSM_TIMING45_SEQ_LO_PUP_VLO_TX_TX_LO_MASK (0xFF00U)
#define XCVR_TSM_TIMING45_SEQ_LO_PUP_VLO_TX_TX_LO_SHIFT (8U)
/*! SEQ_LO_PUP_VLO_TX_TX_LO - De-assertion time setting for SEQ_LO_PUP_VLO_TX (TX)
 */
#define XCVR_TSM_TIMING45_SEQ_LO_PUP_VLO_TX_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING45_SEQ_LO_PUP_VLO_TX_TX_LO_SHIFT)) & XCVR_TSM_TIMING45_SEQ_LO_PUP_VLO_TX_TX_LO_MASK)

#define XCVR_TSM_TIMING45_SEQ_LO_PUP_VLO_TX_RX_HI_MASK (0xFF0000U)
#define XCVR_TSM_TIMING45_SEQ_LO_PUP_VLO_TX_RX_HI_SHIFT (16U)
/*! SEQ_LO_PUP_VLO_TX_RX_HI - Assertion time setting for SEQ_LO_PUP_VLO_TX (RX)
 */
#define XCVR_TSM_TIMING45_SEQ_LO_PUP_VLO_TX_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING45_SEQ_LO_PUP_VLO_TX_RX_HI_SHIFT)) & XCVR_TSM_TIMING45_SEQ_LO_PUP_VLO_TX_RX_HI_MASK)

#define XCVR_TSM_TIMING45_SEQ_LO_PUP_VLO_TX_RX_LO_MASK (0xFF000000U)
#define XCVR_TSM_TIMING45_SEQ_LO_PUP_VLO_TX_RX_LO_SHIFT (24U)
/*! SEQ_LO_PUP_VLO_TX_RX_LO - De-assertion time setting for SEQ_LO_PUP_VLO_TX (RX)
 */
#define XCVR_TSM_TIMING45_SEQ_LO_PUP_VLO_TX_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING45_SEQ_LO_PUP_VLO_TX_RX_LO_SHIFT)) & XCVR_TSM_TIMING45_SEQ_LO_PUP_VLO_TX_RX_LO_MASK)
/*! @} */

/*! @name TIMING46 - TSM_TIMING46 */
/*! @{ */

#define XCVR_TSM_TIMING46_SEQ_LO_PUP_VLO_TXDRV_TX_HI_MASK (0xFFU)
#define XCVR_TSM_TIMING46_SEQ_LO_PUP_VLO_TXDRV_TX_HI_SHIFT (0U)
/*! SEQ_LO_PUP_VLO_TXDRV_TX_HI - Assertion time setting for SEQ_LO_PUP_VLO_TXDRV (TX)
 */
#define XCVR_TSM_TIMING46_SEQ_LO_PUP_VLO_TXDRV_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING46_SEQ_LO_PUP_VLO_TXDRV_TX_HI_SHIFT)) & XCVR_TSM_TIMING46_SEQ_LO_PUP_VLO_TXDRV_TX_HI_MASK)

#define XCVR_TSM_TIMING46_SEQ_LO_PUP_VLO_TXDRV_TX_LO_MASK (0xFF00U)
#define XCVR_TSM_TIMING46_SEQ_LO_PUP_VLO_TXDRV_TX_LO_SHIFT (8U)
/*! SEQ_LO_PUP_VLO_TXDRV_TX_LO - De-assertion time setting for SEQ_LO_PUP_VLO_TXDRV (TX)
 */
#define XCVR_TSM_TIMING46_SEQ_LO_PUP_VLO_TXDRV_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING46_SEQ_LO_PUP_VLO_TXDRV_TX_LO_SHIFT)) & XCVR_TSM_TIMING46_SEQ_LO_PUP_VLO_TXDRV_TX_LO_MASK)

#define XCVR_TSM_TIMING46_SEQ_LO_PUP_VLO_TXDRV_RX_HI_MASK (0xFF0000U)
#define XCVR_TSM_TIMING46_SEQ_LO_PUP_VLO_TXDRV_RX_HI_SHIFT (16U)
/*! SEQ_LO_PUP_VLO_TXDRV_RX_HI - Assertion time setting for SEQ_LO_PUP_VLO_TXDRV (RX)
 */
#define XCVR_TSM_TIMING46_SEQ_LO_PUP_VLO_TXDRV_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING46_SEQ_LO_PUP_VLO_TXDRV_RX_HI_SHIFT)) & XCVR_TSM_TIMING46_SEQ_LO_PUP_VLO_TXDRV_RX_HI_MASK)

#define XCVR_TSM_TIMING46_SEQ_LO_PUP_VLO_TXDRV_RX_LO_MASK (0xFF000000U)
#define XCVR_TSM_TIMING46_SEQ_LO_PUP_VLO_TXDRV_RX_LO_SHIFT (24U)
/*! SEQ_LO_PUP_VLO_TXDRV_RX_LO - De-assertion time setting for SEQ_LO_PUP_VLO_TXDRV (RX)
 */
#define XCVR_TSM_TIMING46_SEQ_LO_PUP_VLO_TXDRV_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING46_SEQ_LO_PUP_VLO_TXDRV_RX_LO_SHIFT)) & XCVR_TSM_TIMING46_SEQ_LO_PUP_VLO_TXDRV_RX_LO_MASK)
/*! @} */

/*! @name TIMING47 - TSM_TIMING47 */
/*! @{ */

#define XCVR_TSM_TIMING47_SEQ_DIVN_PUP_TX_HI_MASK (0xFFU)
#define XCVR_TSM_TIMING47_SEQ_DIVN_PUP_TX_HI_SHIFT (0U)
/*! SEQ_DIVN_PUP_TX_HI - Assertion time setting for SEQ_DIVN_PUP (TX)
 */
#define XCVR_TSM_TIMING47_SEQ_DIVN_PUP_TX_HI(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING47_SEQ_DIVN_PUP_TX_HI_SHIFT)) & XCVR_TSM_TIMING47_SEQ_DIVN_PUP_TX_HI_MASK)

#define XCVR_TSM_TIMING47_SEQ_DIVN_PUP_TX_LO_MASK (0xFF00U)
#define XCVR_TSM_TIMING47_SEQ_DIVN_PUP_TX_LO_SHIFT (8U)
/*! SEQ_DIVN_PUP_TX_LO - De-assertion time setting for SEQ_DIVN_PUP (TX)
 */
#define XCVR_TSM_TIMING47_SEQ_DIVN_PUP_TX_LO(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING47_SEQ_DIVN_PUP_TX_LO_SHIFT)) & XCVR_TSM_TIMING47_SEQ_DIVN_PUP_TX_LO_MASK)

#define XCVR_TSM_TIMING47_SEQ_DIVN_PUP_RX_HI_MASK (0xFF0000U)
#define XCVR_TSM_TIMING47_SEQ_DIVN_PUP_RX_HI_SHIFT (16U)
/*! SEQ_DIVN_PUP_RX_HI - Assertion time setting for SEQ_DIVN_PUP (RX)
 */
#define XCVR_TSM_TIMING47_SEQ_DIVN_PUP_RX_HI(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING47_SEQ_DIVN_PUP_RX_HI_SHIFT)) & XCVR_TSM_TIMING47_SEQ_DIVN_PUP_RX_HI_MASK)

#define XCVR_TSM_TIMING47_SEQ_DIVN_PUP_RX_LO_MASK (0xFF000000U)
#define XCVR_TSM_TIMING47_SEQ_DIVN_PUP_RX_LO_SHIFT (24U)
/*! SEQ_DIVN_PUP_RX_LO - De-assertion time setting for SEQ_DIVN_PUP (RX)
 */
#define XCVR_TSM_TIMING47_SEQ_DIVN_PUP_RX_LO(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING47_SEQ_DIVN_PUP_RX_LO_SHIFT)) & XCVR_TSM_TIMING47_SEQ_DIVN_PUP_RX_LO_MASK)
/*! @} */

/*! @name TIMING48 - TSM_TIMING48 */
/*! @{ */

#define XCVR_TSM_TIMING48_SEQ_DIVN_CLOSEDLOOP_TX_HI_MASK (0xFFU)
#define XCVR_TSM_TIMING48_SEQ_DIVN_CLOSEDLOOP_TX_HI_SHIFT (0U)
/*! SEQ_DIVN_CLOSEDLOOP_TX_HI - Assertion time setting for SEQ_DIVN_CLOSEDLOOP (TX)
 */
#define XCVR_TSM_TIMING48_SEQ_DIVN_CLOSEDLOOP_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING48_SEQ_DIVN_CLOSEDLOOP_TX_HI_SHIFT)) & XCVR_TSM_TIMING48_SEQ_DIVN_CLOSEDLOOP_TX_HI_MASK)

#define XCVR_TSM_TIMING48_SEQ_DIVN_CLOSEDLOOP_TX_LO_MASK (0xFF00U)
#define XCVR_TSM_TIMING48_SEQ_DIVN_CLOSEDLOOP_TX_LO_SHIFT (8U)
/*! SEQ_DIVN_CLOSEDLOOP_TX_LO - De-assertion time setting for SEQ_DIVN_CLOSEDLOOP (TX)
 */
#define XCVR_TSM_TIMING48_SEQ_DIVN_CLOSEDLOOP_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING48_SEQ_DIVN_CLOSEDLOOP_TX_LO_SHIFT)) & XCVR_TSM_TIMING48_SEQ_DIVN_CLOSEDLOOP_TX_LO_MASK)

#define XCVR_TSM_TIMING48_SEQ_DIVN_CLOSEDLOOP_RX_HI_MASK (0xFF0000U)
#define XCVR_TSM_TIMING48_SEQ_DIVN_CLOSEDLOOP_RX_HI_SHIFT (16U)
/*! SEQ_DIVN_CLOSEDLOOP_RX_HI - Assertion time setting for SEQ_DIVN_CLOSEDLOOP (RX)
 */
#define XCVR_TSM_TIMING48_SEQ_DIVN_CLOSEDLOOP_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING48_SEQ_DIVN_CLOSEDLOOP_RX_HI_SHIFT)) & XCVR_TSM_TIMING48_SEQ_DIVN_CLOSEDLOOP_RX_HI_MASK)

#define XCVR_TSM_TIMING48_SEQ_DIVN_CLOSEDLOOP_RX_LO_MASK (0xFF000000U)
#define XCVR_TSM_TIMING48_SEQ_DIVN_CLOSEDLOOP_RX_LO_SHIFT (24U)
/*! SEQ_DIVN_CLOSEDLOOP_RX_LO - De-assertion time setting for SEQ_DIVN_CLOSEDLOOP (RX)
 */
#define XCVR_TSM_TIMING48_SEQ_DIVN_CLOSEDLOOP_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING48_SEQ_DIVN_CLOSEDLOOP_RX_LO_SHIFT)) & XCVR_TSM_TIMING48_SEQ_DIVN_CLOSEDLOOP_RX_LO_MASK)
/*! @} */

/*! @name TIMING49 - TSM_TIMING49 */
/*! @{ */

#define XCVR_TSM_TIMING49_SEQ_PD_EN_PD_DRV_TX_HI_MASK (0xFFU)
#define XCVR_TSM_TIMING49_SEQ_PD_EN_PD_DRV_TX_HI_SHIFT (0U)
/*! SEQ_PD_EN_PD_DRV_TX_HI - Assertion time setting for SEQ_PD_EN_PD_DRV (TX)
 */
#define XCVR_TSM_TIMING49_SEQ_PD_EN_PD_DRV_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING49_SEQ_PD_EN_PD_DRV_TX_HI_SHIFT)) & XCVR_TSM_TIMING49_SEQ_PD_EN_PD_DRV_TX_HI_MASK)

#define XCVR_TSM_TIMING49_SEQ_PD_EN_PD_DRV_TX_LO_MASK (0xFF00U)
#define XCVR_TSM_TIMING49_SEQ_PD_EN_PD_DRV_TX_LO_SHIFT (8U)
/*! SEQ_PD_EN_PD_DRV_TX_LO - De-assertion time setting for SEQ_PD_EN_PD_DRV (TX)
 */
#define XCVR_TSM_TIMING49_SEQ_PD_EN_PD_DRV_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING49_SEQ_PD_EN_PD_DRV_TX_LO_SHIFT)) & XCVR_TSM_TIMING49_SEQ_PD_EN_PD_DRV_TX_LO_MASK)

#define XCVR_TSM_TIMING49_SEQ_PD_EN_PD_DRV_RX_HI_MASK (0xFF0000U)
#define XCVR_TSM_TIMING49_SEQ_PD_EN_PD_DRV_RX_HI_SHIFT (16U)
/*! SEQ_PD_EN_PD_DRV_RX_HI - Assertion time setting for SEQ_PD_EN_PD_DRV (RX)
 */
#define XCVR_TSM_TIMING49_SEQ_PD_EN_PD_DRV_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING49_SEQ_PD_EN_PD_DRV_RX_HI_SHIFT)) & XCVR_TSM_TIMING49_SEQ_PD_EN_PD_DRV_RX_HI_MASK)

#define XCVR_TSM_TIMING49_SEQ_PD_EN_PD_DRV_RX_LO_MASK (0xFF000000U)
#define XCVR_TSM_TIMING49_SEQ_PD_EN_PD_DRV_RX_LO_SHIFT (24U)
/*! SEQ_PD_EN_PD_DRV_RX_LO - De-assertion time setting for SEQ_PD_EN_PD_DRV (RX)
 */
#define XCVR_TSM_TIMING49_SEQ_PD_EN_PD_DRV_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING49_SEQ_PD_EN_PD_DRV_RX_LO_SHIFT)) & XCVR_TSM_TIMING49_SEQ_PD_EN_PD_DRV_RX_LO_MASK)
/*! @} */

/*! @name TIMING50 - TSM_TIMING50 */
/*! @{ */

#define XCVR_TSM_TIMING50_SEQ_CBPF_EN_DCOC_TX_HI_MASK (0xFFU)
#define XCVR_TSM_TIMING50_SEQ_CBPF_EN_DCOC_TX_HI_SHIFT (0U)
/*! SEQ_CBPF_EN_DCOC_TX_HI - Assertion time setting for SEQ_CBPF_EN_DCOC (TX)
 */
#define XCVR_TSM_TIMING50_SEQ_CBPF_EN_DCOC_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING50_SEQ_CBPF_EN_DCOC_TX_HI_SHIFT)) & XCVR_TSM_TIMING50_SEQ_CBPF_EN_DCOC_TX_HI_MASK)

#define XCVR_TSM_TIMING50_SEQ_CBPF_EN_DCOC_TX_LO_MASK (0xFF00U)
#define XCVR_TSM_TIMING50_SEQ_CBPF_EN_DCOC_TX_LO_SHIFT (8U)
/*! SEQ_CBPF_EN_DCOC_TX_LO - De-assertion time setting for SEQ_CBPF_EN_DCOC (TX)
 */
#define XCVR_TSM_TIMING50_SEQ_CBPF_EN_DCOC_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING50_SEQ_CBPF_EN_DCOC_TX_LO_SHIFT)) & XCVR_TSM_TIMING50_SEQ_CBPF_EN_DCOC_TX_LO_MASK)

#define XCVR_TSM_TIMING50_SEQ_CBPF_EN_DCOC_RX_HI_MASK (0xFF0000U)
#define XCVR_TSM_TIMING50_SEQ_CBPF_EN_DCOC_RX_HI_SHIFT (16U)
/*! SEQ_CBPF_EN_DCOC_RX_HI - Assertion time setting for SEQ_CBPF_EN_DCOC (RX)
 */
#define XCVR_TSM_TIMING50_SEQ_CBPF_EN_DCOC_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING50_SEQ_CBPF_EN_DCOC_RX_HI_SHIFT)) & XCVR_TSM_TIMING50_SEQ_CBPF_EN_DCOC_RX_HI_MASK)

#define XCVR_TSM_TIMING50_SEQ_CBPF_EN_DCOC_RX_LO_MASK (0xFF000000U)
#define XCVR_TSM_TIMING50_SEQ_CBPF_EN_DCOC_RX_LO_SHIFT (24U)
/*! SEQ_CBPF_EN_DCOC_RX_LO - De-assertion time setting for SEQ_CBPF_EN_DCOC (RX)
 */
#define XCVR_TSM_TIMING50_SEQ_CBPF_EN_DCOC_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING50_SEQ_CBPF_EN_DCOC_RX_LO_SHIFT)) & XCVR_TSM_TIMING50_SEQ_CBPF_EN_DCOC_RX_LO_MASK)
/*! @} */

/*! @name TIMING51 - TSM_TIMING51 */
/*! @{ */

#define XCVR_TSM_TIMING51_SEQ_RX_GANG_PUP_TX_HI_MASK (0xFFU)
#define XCVR_TSM_TIMING51_SEQ_RX_GANG_PUP_TX_HI_SHIFT (0U)
/*! SEQ_RX_GANG_PUP_TX_HI - Assertion time setting for SEQ_(RX_LAN/RX_MIX/CBPF/ADC_PUP) and SEQ_SPARE1 (TX)
 */
#define XCVR_TSM_TIMING51_SEQ_RX_GANG_PUP_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING51_SEQ_RX_GANG_PUP_TX_HI_SHIFT)) & XCVR_TSM_TIMING51_SEQ_RX_GANG_PUP_TX_HI_MASK)

#define XCVR_TSM_TIMING51_SEQ_RX_GANG_PUP_TX_LO_MASK (0xFF00U)
#define XCVR_TSM_TIMING51_SEQ_RX_GANG_PUP_TX_LO_SHIFT (8U)
/*! SEQ_RX_GANG_PUP_TX_LO - De-assertion time setting for SEQ_(RX_LAN/RX_MIX/CBPF/ADC_PUP) and SEQ_SPARE1 (TX)
 */
#define XCVR_TSM_TIMING51_SEQ_RX_GANG_PUP_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING51_SEQ_RX_GANG_PUP_TX_LO_SHIFT)) & XCVR_TSM_TIMING51_SEQ_RX_GANG_PUP_TX_LO_MASK)

#define XCVR_TSM_TIMING51_SEQ_RX_GANG_PUP_RX_HI_MASK (0xFF0000U)
#define XCVR_TSM_TIMING51_SEQ_RX_GANG_PUP_RX_HI_SHIFT (16U)
/*! SEQ_RX_GANG_PUP_RX_HI - Assertion time setting for SEQ_(RX_LAN/RX_MIX/CBPF/ADC_PUP) and SEQ_SPARE1 (RX)
 */
#define XCVR_TSM_TIMING51_SEQ_RX_GANG_PUP_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING51_SEQ_RX_GANG_PUP_RX_HI_SHIFT)) & XCVR_TSM_TIMING51_SEQ_RX_GANG_PUP_RX_HI_MASK)

#define XCVR_TSM_TIMING51_SEQ_RX_GANG_PUP_RX_LO_MASK (0xFF000000U)
#define XCVR_TSM_TIMING51_SEQ_RX_GANG_PUP_RX_LO_SHIFT (24U)
/*! SEQ_RX_GANG_PUP_RX_LO - De-assertion time setting for SEQ_(RX_LAN/RX_MIX/CBPF/ADC_PUP) and SEQ_SPARE1 (RX)
 */
#define XCVR_TSM_TIMING51_SEQ_RX_GANG_PUP_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING51_SEQ_RX_GANG_PUP_RX_LO_SHIFT)) & XCVR_TSM_TIMING51_SEQ_RX_GANG_PUP_RX_LO_MASK)
/*! @} */

/*! @name TIMING52 - TSM_TIMING52 */
/*! @{ */

#define XCVR_TSM_TIMING52_SEQ_SPARE3_TX_HI_MASK  (0xFFU)
#define XCVR_TSM_TIMING52_SEQ_SPARE3_TX_HI_SHIFT (0U)
/*! SEQ_SPARE3_TX_HI - Assertion time setting for SEQ_SPARE3 (TX)
 */
#define XCVR_TSM_TIMING52_SEQ_SPARE3_TX_HI(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING52_SEQ_SPARE3_TX_HI_SHIFT)) & XCVR_TSM_TIMING52_SEQ_SPARE3_TX_HI_MASK)

#define XCVR_TSM_TIMING52_SEQ_SPARE3_TX_LO_MASK  (0xFF00U)
#define XCVR_TSM_TIMING52_SEQ_SPARE3_TX_LO_SHIFT (8U)
/*! SEQ_SPARE3_TX_LO - De-assertion time setting for SEQ_SPARE3 (TX)
 */
#define XCVR_TSM_TIMING52_SEQ_SPARE3_TX_LO(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING52_SEQ_SPARE3_TX_LO_SHIFT)) & XCVR_TSM_TIMING52_SEQ_SPARE3_TX_LO_MASK)

#define XCVR_TSM_TIMING52_SEQ_SPARE3_RX_HI_MASK  (0xFF0000U)
#define XCVR_TSM_TIMING52_SEQ_SPARE3_RX_HI_SHIFT (16U)
/*! SEQ_SPARE3_RX_HI - Assertion time setting for SEQ_SPARE3 (RX)
 */
#define XCVR_TSM_TIMING52_SEQ_SPARE3_RX_HI(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING52_SEQ_SPARE3_RX_HI_SHIFT)) & XCVR_TSM_TIMING52_SEQ_SPARE3_RX_HI_MASK)

#define XCVR_TSM_TIMING52_SEQ_SPARE3_RX_LO_MASK  (0xFF000000U)
#define XCVR_TSM_TIMING52_SEQ_SPARE3_RX_LO_SHIFT (24U)
/*! SEQ_SPARE3_RX_LO - De-assertion time setting for SEQ_SPARE3 (RX)
 */
#define XCVR_TSM_TIMING52_SEQ_SPARE3_RX_LO(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING52_SEQ_SPARE3_RX_LO_SHIFT)) & XCVR_TSM_TIMING52_SEQ_SPARE3_RX_LO_MASK)
/*! @} */

/*! @name OVRD0 - TSM OVERRIDE REGISTER 0 */
/*! @{ */

#define XCVR_TSM_OVRD0_TSM_RF_ACTIVE_OVRD_EN_MASK (0x1U)
#define XCVR_TSM_OVRD0_TSM_RF_ACTIVE_OVRD_EN_SHIFT (0U)
/*! TSM_RF_ACTIVE_OVRD_EN - Override control for TSM_RF_ACTIVE
 *  0b0..Normal operation.
 *  0b1..Use the state of TSM_RF_ACTIVE_OVRD to override the signal "tsm_rf_active".
 */
#define XCVR_TSM_OVRD0_TSM_RF_ACTIVE_OVRD_EN(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_TSM_RF_ACTIVE_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_TSM_RF_ACTIVE_OVRD_EN_MASK)

#define XCVR_TSM_OVRD0_TSM_RF_ACTIVE_OVRD_MASK   (0x2U)
#define XCVR_TSM_OVRD0_TSM_RF_ACTIVE_OVRD_SHIFT  (1U)
/*! TSM_RF_ACTIVE_OVRD - Override value for tsm_rf_active
 */
#define XCVR_TSM_OVRD0_TSM_RF_ACTIVE_OVRD(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_TSM_RF_ACTIVE_OVRD_SHIFT)) & XCVR_TSM_OVRD0_TSM_RF_ACTIVE_OVRD_MASK)

#define XCVR_TSM_OVRD0_TSM_RF_STATUS_OVRD_EN_MASK (0x4U)
#define XCVR_TSM_OVRD0_TSM_RF_STATUS_OVRD_EN_SHIFT (2U)
/*! TSM_RF_STATUS_OVRD_EN - Override control for TSM_RF_STATUS_EN
 *  0b0..Normal operation.
 *  0b1..Use the state of TSM_RF_STATUS_OVRD to override the signal "tsm_rf_status".
 */
#define XCVR_TSM_OVRD0_TSM_RF_STATUS_OVRD_EN(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_TSM_RF_STATUS_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_TSM_RF_STATUS_OVRD_EN_MASK)

#define XCVR_TSM_OVRD0_TSM_RF_STATUS_OVRD_MASK   (0x8U)
#define XCVR_TSM_OVRD0_TSM_RF_STATUS_OVRD_SHIFT  (3U)
/*! TSM_RF_STATUS_OVRD - Override value for TSM_RF_STATUS
 */
#define XCVR_TSM_OVRD0_TSM_RF_STATUS_OVRD(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_TSM_RF_STATUS_OVRD_SHIFT)) & XCVR_TSM_OVRD0_TSM_RF_STATUS_OVRD_MASK)

#define XCVR_TSM_OVRD0_TSM_RF_PRIORITY_OVRD_EN_MASK (0x10U)
#define XCVR_TSM_OVRD0_TSM_RF_PRIORITY_OVRD_EN_SHIFT (4U)
/*! TSM_RF_PRIORITY_OVRD_EN - Override control for TSM_RF_PRIORITY_EN
 *  0b0..Normal operation.
 *  0b1..Use the state of TSM_RF_PRIORITY_OVRD to override the signal "tsm_rf_priority".
 */
#define XCVR_TSM_OVRD0_TSM_RF_PRIORITY_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_TSM_RF_PRIORITY_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_TSM_RF_PRIORITY_OVRD_EN_MASK)

#define XCVR_TSM_OVRD0_TSM_RF_PRIORITY_OVRD_MASK (0x20U)
#define XCVR_TSM_OVRD0_TSM_RF_PRIORITY_OVRD_SHIFT (5U)
/*! TSM_RF_PRIORITY_OVRD - Override value for tsm_rf_priority
 */
#define XCVR_TSM_OVRD0_TSM_RF_PRIORITY_OVRD(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_TSM_RF_PRIORITY_OVRD_SHIFT)) & XCVR_TSM_OVRD0_TSM_RF_PRIORITY_OVRD_MASK)

#define XCVR_TSM_OVRD0_TSM_IRQ0_START_TRIG_OVRD_EN_MASK (0x40U)
#define XCVR_TSM_OVRD0_TSM_IRQ0_START_TRIG_OVRD_EN_SHIFT (6U)
/*! TSM_IRQ0_START_TRIG_OVRD_EN - Override control for TSM_IRQ0_START_TRIG_EN
 *  0b0..Normal operation.
 *  0b1..Use the state of TSM_IRQ0_START_TRIG_OVRD to override the signal "tsm_irq0_start_trig".
 */
#define XCVR_TSM_OVRD0_TSM_IRQ0_START_TRIG_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_TSM_IRQ0_START_TRIG_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_TSM_IRQ0_START_TRIG_OVRD_EN_MASK)

#define XCVR_TSM_OVRD0_TSM_IRQ0_START_TRIG_OVRD_MASK (0x80U)
#define XCVR_TSM_OVRD0_TSM_IRQ0_START_TRIG_OVRD_SHIFT (7U)
/*! TSM_IRQ0_START_TRIG_OVRD - Override value for TSM_IRQ0_START_TRIG
 */
#define XCVR_TSM_OVRD0_TSM_IRQ0_START_TRIG_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_TSM_IRQ0_START_TRIG_OVRD_SHIFT)) & XCVR_TSM_OVRD0_TSM_IRQ0_START_TRIG_OVRD_MASK)

#define XCVR_TSM_OVRD0_TSM_IRQ1_STOP_TRIG_OVRD_EN_MASK (0x100U)
#define XCVR_TSM_OVRD0_TSM_IRQ1_STOP_TRIG_OVRD_EN_SHIFT (8U)
/*! TSM_IRQ1_STOP_TRIG_OVRD_EN - Override control for TSM_IRQ1_STOP_TRIG
 *  0b0..Normal operation.
 *  0b1..Use the state of TSM_IRQ1_STOP_TRIG_OVRD to override the signal "tsm_irq1_stop_trig".
 */
#define XCVR_TSM_OVRD0_TSM_IRQ1_STOP_TRIG_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_TSM_IRQ1_STOP_TRIG_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_TSM_IRQ1_STOP_TRIG_OVRD_EN_MASK)

#define XCVR_TSM_OVRD0_TSM_IRQ1_STOP_TRIG_OVRD_MASK (0x200U)
#define XCVR_TSM_OVRD0_TSM_IRQ1_STOP_TRIG_OVRD_SHIFT (9U)
/*! TSM_IRQ1_STOP_TRIG_OVRD - Override value for TSM_IRQ1_STOP_TRIG
 */
#define XCVR_TSM_OVRD0_TSM_IRQ1_STOP_TRIG_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_TSM_IRQ1_STOP_TRIG_OVRD_SHIFT)) & XCVR_TSM_OVRD0_TSM_IRQ1_STOP_TRIG_OVRD_MASK)

#define XCVR_TSM_OVRD0_DCOC_GAIN_CFG_EN_OVRD_EN_MASK (0x400U)
#define XCVR_TSM_OVRD0_DCOC_GAIN_CFG_EN_OVRD_EN_SHIFT (10U)
/*! DCOC_GAIN_CFG_EN_OVRD_EN - Override control for DCOC_GAIN_CFG_EN
 *  0b0..Normal operation.
 *  0b1..Use the state of DCOC_GAIN_CFG_EN_OVRD to override the signal "dcoc_gain_cfg_en".
 */
#define XCVR_TSM_OVRD0_DCOC_GAIN_CFG_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_DCOC_GAIN_CFG_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_DCOC_GAIN_CFG_EN_OVRD_EN_MASK)

#define XCVR_TSM_OVRD0_DCOC_GAIN_CFG_EN_OVRD_MASK (0x800U)
#define XCVR_TSM_OVRD0_DCOC_GAIN_CFG_EN_OVRD_SHIFT (11U)
/*! DCOC_GAIN_CFG_EN_OVRD - Override value for DCOC_GAIN_CFG_EN
 */
#define XCVR_TSM_OVRD0_DCOC_GAIN_CFG_EN_OVRD(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_DCOC_GAIN_CFG_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_DCOC_GAIN_CFG_EN_OVRD_MASK)

#define XCVR_TSM_OVRD0_LDO_CAL_EN_OVRD_EN_MASK   (0x1000U)
#define XCVR_TSM_OVRD0_LDO_CAL_EN_OVRD_EN_SHIFT  (12U)
/*! LDO_CAL_EN_OVRD_EN - Override control for LDO_CAL_EN_
 *  0b0..Normal operation.
 *  0b1..Use the state of LDO_CAL_EN_OVRD to override the signal "ldo_cal_en".
 */
#define XCVR_TSM_OVRD0_LDO_CAL_EN_OVRD_EN(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_LDO_CAL_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_LDO_CAL_EN_OVRD_EN_MASK)

#define XCVR_TSM_OVRD0_LDO_CAL_EN_OVRD_MASK      (0x2000U)
#define XCVR_TSM_OVRD0_LDO_CAL_EN_OVRD_SHIFT     (13U)
/*! LDO_CAL_EN_OVRD - Override value for LDO_CAL_EN
 */
#define XCVR_TSM_OVRD0_LDO_CAL_EN_OVRD(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_LDO_CAL_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_LDO_CAL_EN_OVRD_MASK)

#define XCVR_TSM_OVRD0_PLL_DIG_EN_OVRD_EN_MASK   (0x4000U)
#define XCVR_TSM_OVRD0_PLL_DIG_EN_OVRD_EN_SHIFT  (14U)
/*! PLL_DIG_EN_OVRD_EN - Override control for PLL_DIG_EN
 *  0b0..Normal operation.
 *  0b1..Use the state of PLL_DIG_EN_OVRD to override the signal "pll_dig_en".
 */
#define XCVR_TSM_OVRD0_PLL_DIG_EN_OVRD_EN(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_PLL_DIG_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_PLL_DIG_EN_OVRD_EN_MASK)

#define XCVR_TSM_OVRD0_PLL_DIG_EN_OVRD_MASK      (0x8000U)
#define XCVR_TSM_OVRD0_PLL_DIG_EN_OVRD_SHIFT     (15U)
/*! PLL_DIG_EN_OVRD - Override value for PLL_DIG_EN
 */
#define XCVR_TSM_OVRD0_PLL_DIG_EN_OVRD(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_PLL_DIG_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_PLL_DIG_EN_OVRD_MASK)

#define XCVR_TSM_OVRD0_SIGMA_DELTA_EN_OVRD_EN_MASK (0x10000U)
#define XCVR_TSM_OVRD0_SIGMA_DELTA_EN_OVRD_EN_SHIFT (16U)
/*! SIGMA_DELTA_EN_OVRD_EN - Override control for SIGMA_DELTA_EN
 *  0b0..Normal operation.
 *  0b1..Use the state of SIGMA_DELTA_EN_OVRD to override the signal "sigma_delta_en".
 */
#define XCVR_TSM_OVRD0_SIGMA_DELTA_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_SIGMA_DELTA_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_SIGMA_DELTA_EN_OVRD_EN_MASK)

#define XCVR_TSM_OVRD0_SIGMA_DELTA_EN_OVRD_MASK  (0x20000U)
#define XCVR_TSM_OVRD0_SIGMA_DELTA_EN_OVRD_SHIFT (17U)
/*! SIGMA_DELTA_EN_OVRD - Override value for SIGMA_DELTA_EN
 */
#define XCVR_TSM_OVRD0_SIGMA_DELTA_EN_OVRD(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_SIGMA_DELTA_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_SIGMA_DELTA_EN_OVRD_MASK)

#define XCVR_TSM_OVRD0_DCOC_CAL_EN_OVRD_EN_MASK  (0x40000U)
#define XCVR_TSM_OVRD0_DCOC_CAL_EN_OVRD_EN_SHIFT (18U)
/*! DCOC_CAL_EN_OVRD_EN - Override control for DCOC_CAL_EN
 *  0b0..Normal operation.
 *  0b1..Use the state of DCOC_CAL_EN_OVRD to override the signal "dcoc_cal_en".
 */
#define XCVR_TSM_OVRD0_DCOC_CAL_EN_OVRD_EN(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_DCOC_CAL_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_DCOC_CAL_EN_OVRD_EN_MASK)

#define XCVR_TSM_OVRD0_DCOC_CAL_EN_OVRD_MASK     (0x80000U)
#define XCVR_TSM_OVRD0_DCOC_CAL_EN_OVRD_SHIFT    (19U)
/*! DCOC_CAL_EN_OVRD - Override value for DCOC_CAL_EN
 */
#define XCVR_TSM_OVRD0_DCOC_CAL_EN_OVRD(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_DCOC_CAL_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_DCOC_CAL_EN_OVRD_MASK)

#define XCVR_TSM_OVRD0_TX_DIG_EN_OVRD_EN_MASK    (0x100000U)
#define XCVR_TSM_OVRD0_TX_DIG_EN_OVRD_EN_SHIFT   (20U)
/*! TX_DIG_EN_OVRD_EN - Override control for TX_DIG_EN
 *  0b0..Normal operation.
 *  0b1..Use the state of TX_DIG_EN_OVRD to override the signal "tx_dig_en".
 */
#define XCVR_TSM_OVRD0_TX_DIG_EN_OVRD_EN(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_TX_DIG_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_TX_DIG_EN_OVRD_EN_MASK)

#define XCVR_TSM_OVRD0_TX_DIG_EN_OVRD_MASK       (0x200000U)
#define XCVR_TSM_OVRD0_TX_DIG_EN_OVRD_SHIFT      (21U)
/*! TX_DIG_EN_OVRD - Override value for TX_DIG_EN
 */
#define XCVR_TSM_OVRD0_TX_DIG_EN_OVRD(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_TX_DIG_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_TX_DIG_EN_OVRD_MASK)

#define XCVR_TSM_OVRD0_FREQ_TARG_LD_EN_OVRD_EN_MASK (0x400000U)
#define XCVR_TSM_OVRD0_FREQ_TARG_LD_EN_OVRD_EN_SHIFT (22U)
/*! FREQ_TARG_LD_EN_OVRD_EN - Override control for FREQ_TARG_LD_EN
 *  0b0..Normal operation.
 *  0b1..Use the state of FREQ_TARG_LD_EN_OVRD to override the signal "freq_targ_ld_en".
 */
#define XCVR_TSM_OVRD0_FREQ_TARG_LD_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_FREQ_TARG_LD_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_FREQ_TARG_LD_EN_OVRD_EN_MASK)

#define XCVR_TSM_OVRD0_FREQ_TARG_LD_EN_OVRD_MASK (0x800000U)
#define XCVR_TSM_OVRD0_FREQ_TARG_LD_EN_OVRD_SHIFT (23U)
/*! FREQ_TARG_LD_EN_OVRD - Override value for FREQ_TARG_LD_EN
 */
#define XCVR_TSM_OVRD0_FREQ_TARG_LD_EN_OVRD(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_FREQ_TARG_LD_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_FREQ_TARG_LD_EN_OVRD_MASK)

#define XCVR_TSM_OVRD0_RX_INIT_EN_OVRD_EN_MASK   (0x1000000U)
#define XCVR_TSM_OVRD0_RX_INIT_EN_OVRD_EN_SHIFT  (24U)
/*! RX_INIT_EN_OVRD_EN - Override control for RX_INIT_EN
 *  0b0..Normal operation.
 *  0b1..Use the state of RX_INIT_EN_OVRD to override the signal "rx_init_en".
 */
#define XCVR_TSM_OVRD0_RX_INIT_EN_OVRD_EN(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_RX_INIT_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_RX_INIT_EN_OVRD_EN_MASK)

#define XCVR_TSM_OVRD0_RX_INIT_EN_OVRD_MASK      (0x2000000U)
#define XCVR_TSM_OVRD0_RX_INIT_EN_OVRD_SHIFT     (25U)
/*! RX_INIT_EN_OVRD - Override value for RX_INIT_EN
 */
#define XCVR_TSM_OVRD0_RX_INIT_EN_OVRD(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_RX_INIT_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_RX_INIT_EN_OVRD_MASK)

#define XCVR_TSM_OVRD0_RX_DIG_EN_OVRD_EN_MASK    (0x4000000U)
#define XCVR_TSM_OVRD0_RX_DIG_EN_OVRD_EN_SHIFT   (26U)
/*! RX_DIG_EN_OVRD_EN - Override control for RX_DIG_EN
 *  0b0..Normal operation.
 *  0b1..Use the state of RX_DIG_EN_OVRD to override the signal "rx_dig_en".
 */
#define XCVR_TSM_OVRD0_RX_DIG_EN_OVRD_EN(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_RX_DIG_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_RX_DIG_EN_OVRD_EN_MASK)

#define XCVR_TSM_OVRD0_RX_DIG_EN_OVRD_MASK       (0x8000000U)
#define XCVR_TSM_OVRD0_RX_DIG_EN_OVRD_SHIFT      (27U)
/*! RX_DIG_EN_OVRD - Override value for RX_DIG_EN
 */
#define XCVR_TSM_OVRD0_RX_DIG_EN_OVRD(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_RX_DIG_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_RX_DIG_EN_OVRD_MASK)

#define XCVR_TSM_OVRD0_RX_PHY_EN_OVRD_EN_MASK    (0x10000000U)
#define XCVR_TSM_OVRD0_RX_PHY_EN_OVRD_EN_SHIFT   (28U)
/*! RX_PHY_EN_OVRD_EN - Override control for RX_PHY_EN
 *  0b0..Normal operation.
 *  0b1..Use the state of RX_PHY_EN_OVRD to override the signal "rx_phy_en".
 */
#define XCVR_TSM_OVRD0_RX_PHY_EN_OVRD_EN(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_RX_PHY_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_RX_PHY_EN_OVRD_EN_MASK)

#define XCVR_TSM_OVRD0_RX_PHY_EN_OVRD_MASK       (0x20000000U)
#define XCVR_TSM_OVRD0_RX_PHY_EN_OVRD_SHIFT      (29U)
/*! RX_PHY_EN_OVRD - Override value for RX_PHY_EN
 */
#define XCVR_TSM_OVRD0_RX_PHY_EN_OVRD(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_RX_PHY_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_RX_PHY_EN_OVRD_MASK)

#define XCVR_TSM_OVRD0_SEQ_BG_PUP_IBG_CAL_OVRD_EN_MASK (0x40000000U)
#define XCVR_TSM_OVRD0_SEQ_BG_PUP_IBG_CAL_OVRD_EN_SHIFT (30U)
/*! SEQ_BG_PUP_IBG_CAL_OVRD_EN - Override control for SEQ_BG_PUP_IBG_CAL
 *  0b0..Normal operation.
 *  0b1..Use the state of SEQ_BG_PUP_IBG_CAL_OVRD to override the signal "seq_bg_pup_ibg_cal".
 */
#define XCVR_TSM_OVRD0_SEQ_BG_PUP_IBG_CAL_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_SEQ_BG_PUP_IBG_CAL_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_SEQ_BG_PUP_IBG_CAL_OVRD_EN_MASK)

#define XCVR_TSM_OVRD0_SEQ_BG_PUP_IBG_CAL_OVRD_MASK (0x80000000U)
#define XCVR_TSM_OVRD0_SEQ_BG_PUP_IBG_CAL_OVRD_SHIFT (31U)
/*! SEQ_BG_PUP_IBG_CAL_OVRD - Override value for SEQ_BG_PUP_IBG_CAL
 */
#define XCVR_TSM_OVRD0_SEQ_BG_PUP_IBG_CAL_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_SEQ_BG_PUP_IBG_CAL_OVRD_SHIFT)) & XCVR_TSM_OVRD0_SEQ_BG_PUP_IBG_CAL_OVRD_MASK)
/*! @} */

/*! @name OVRD1 - TSM OVERRIDE REGISTER 1 */
/*! @{ */

#define XCVR_TSM_OVRD1_SEQ_LDOTRIM_PUP_OVRD_EN_MASK (0x1U)
#define XCVR_TSM_OVRD1_SEQ_LDOTRIM_PUP_OVRD_EN_SHIFT (0U)
/*! SEQ_LDOTRIM_PUP_OVRD_EN - Override control for SEQ_LDOTRIM_PUP
 *  0b0..Normal operation.
 *  0b1..Use the state of SEQ_LDOTRIM_PUP_OVRD to override the signal "seq_ldotrim_pup".
 */
#define XCVR_TSM_OVRD1_SEQ_LDOTRIM_PUP_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SEQ_LDOTRIM_PUP_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SEQ_LDOTRIM_PUP_OVRD_EN_MASK)

#define XCVR_TSM_OVRD1_SEQ_LDOTRIM_PUP_OVRD_MASK (0x2U)
#define XCVR_TSM_OVRD1_SEQ_LDOTRIM_PUP_OVRD_SHIFT (1U)
/*! SEQ_LDOTRIM_PUP_OVRD - Override value for SEQ_LDOTRIM_PUP
 */
#define XCVR_TSM_OVRD1_SEQ_LDOTRIM_PUP_OVRD(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SEQ_LDOTRIM_PUP_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SEQ_LDOTRIM_PUP_OVRD_MASK)

#define XCVR_TSM_OVRD1_SEQ_LDO_CAL_PUP_OVRD_EN_MASK (0x4U)
#define XCVR_TSM_OVRD1_SEQ_LDO_CAL_PUP_OVRD_EN_SHIFT (2U)
/*! SEQ_LDO_CAL_PUP_OVRD_EN - Override control for SEQ_LDO_CAL_PUP
 *  0b0..Normal operation.
 *  0b1..Use the state of SEQ_LDO_CAL_PUP_OVRD to override the signal "seq_ldo_cal_pup".
 */
#define XCVR_TSM_OVRD1_SEQ_LDO_CAL_PUP_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SEQ_LDO_CAL_PUP_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SEQ_LDO_CAL_PUP_OVRD_EN_MASK)

#define XCVR_TSM_OVRD1_SEQ_LDO_CAL_PUP_OVRD_MASK (0x8U)
#define XCVR_TSM_OVRD1_SEQ_LDO_CAL_PUP_OVRD_SHIFT (3U)
/*! SEQ_LDO_CAL_PUP_OVRD - Override value for SEQ_LDO_CAL_PUP
 */
#define XCVR_TSM_OVRD1_SEQ_LDO_CAL_PUP_OVRD(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SEQ_LDO_CAL_PUP_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SEQ_LDO_CAL_PUP_OVRD_MASK)

#define XCVR_TSM_OVRD1_SEQ_BG_FC_OVRD_EN_MASK    (0x10U)
#define XCVR_TSM_OVRD1_SEQ_BG_FC_OVRD_EN_SHIFT   (4U)
/*! SEQ_BG_FC_OVRD_EN - Override control for SEQ_BG_FC
 *  0b0..Normal operation.
 *  0b1..Use the state of SEQ_BG_FC_OVRD to override the signal "seq_bg_fc".
 */
#define XCVR_TSM_OVRD1_SEQ_BG_FC_OVRD_EN(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SEQ_BG_FC_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SEQ_BG_FC_OVRD_EN_MASK)

#define XCVR_TSM_OVRD1_SEQ_BG_FC_OVRD_MASK       (0x20U)
#define XCVR_TSM_OVRD1_SEQ_BG_FC_OVRD_SHIFT      (5U)
/*! SEQ_BG_FC_OVRD - Override value for SEQ_BG_FC
 */
#define XCVR_TSM_OVRD1_SEQ_BG_FC_OVRD(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SEQ_BG_FC_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SEQ_BG_FC_OVRD_MASK)

#define XCVR_TSM_OVRD1_SEQ_LDO_PLL_FC_OVRD_EN_MASK (0x40U)
#define XCVR_TSM_OVRD1_SEQ_LDO_PLL_FC_OVRD_EN_SHIFT (6U)
/*! SEQ_LDO_PLL_FC_OVRD_EN - Override control for SEQ_LDO_PLL_FC
 *  0b0..Normal operation.
 *  0b1..Use the state of SEQ_LDO_PLL_FC_OVRD to override the signal "seq_ldo_pll_fc".
 */
#define XCVR_TSM_OVRD1_SEQ_LDO_PLL_FC_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SEQ_LDO_PLL_FC_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SEQ_LDO_PLL_FC_OVRD_EN_MASK)

#define XCVR_TSM_OVRD1_SEQ_LDO_PLL_FC_OVRD_MASK  (0x80U)
#define XCVR_TSM_OVRD1_SEQ_LDO_PLL_FC_OVRD_SHIFT (7U)
/*! SEQ_LDO_PLL_FC_OVRD - Override value for SEQ_LDO_PLL_FC
 */
#define XCVR_TSM_OVRD1_SEQ_LDO_PLL_FC_OVRD(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SEQ_LDO_PLL_FC_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SEQ_LDO_PLL_FC_OVRD_MASK)

#define XCVR_TSM_OVRD1_SEQ_LDO_VCO_FC_OVRD_EN_MASK (0x100U)
#define XCVR_TSM_OVRD1_SEQ_LDO_VCO_FC_OVRD_EN_SHIFT (8U)
/*! SEQ_LDO_VCO_FC_OVRD_EN - Override control for SEQ_LDO_VCO_FC
 *  0b0..Normal operation.
 *  0b1..Use the state of SEQ_LDO_VCO_FC_OVRD to override the signal "seq_ldo_vco_fc".
 */
#define XCVR_TSM_OVRD1_SEQ_LDO_VCO_FC_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SEQ_LDO_VCO_FC_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SEQ_LDO_VCO_FC_OVRD_EN_MASK)

#define XCVR_TSM_OVRD1_SEQ_LDO_VCO_FC_OVRD_MASK  (0x200U)
#define XCVR_TSM_OVRD1_SEQ_LDO_VCO_FC_OVRD_SHIFT (9U)
/*! SEQ_LDO_VCO_FC_OVRD - Override value for SEQ_LDO_VCO_FC
 */
#define XCVR_TSM_OVRD1_SEQ_LDO_VCO_FC_OVRD(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SEQ_LDO_VCO_FC_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SEQ_LDO_VCO_FC_OVRD_MASK)

#define XCVR_TSM_OVRD1_SEQ_LDO_RXTXHF_FC_OVRD_EN_MASK (0x400U)
#define XCVR_TSM_OVRD1_SEQ_LDO_RXTXHF_FC_OVRD_EN_SHIFT (10U)
/*! SEQ_LDO_RXTXHF_FC_OVRD_EN - Override control for SEQ_LDO_RXTXHF_FC
 *  0b0..Normal operation.
 *  0b1..Use the state of SEQ_LDO_RXTXHF_FC_OVRD to override the signal "seq_ldo_rxtxhf_fc".
 */
#define XCVR_TSM_OVRD1_SEQ_LDO_RXTXHF_FC_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SEQ_LDO_RXTXHF_FC_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SEQ_LDO_RXTXHF_FC_OVRD_EN_MASK)

#define XCVR_TSM_OVRD1_SEQ_LDO_RXTXHF_FC_OVRD_MASK (0x800U)
#define XCVR_TSM_OVRD1_SEQ_LDO_RXTXHF_FC_OVRD_SHIFT (11U)
/*! SEQ_LDO_RXTXHF_FC_OVRD - Override value for SEQ_LDO_RXTXHF_FC
 */
#define XCVR_TSM_OVRD1_SEQ_LDO_RXTXHF_FC_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SEQ_LDO_RXTXHF_FC_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SEQ_LDO_RXTXHF_FC_OVRD_MASK)

#define XCVR_TSM_OVRD1_SEQ_LDO_RXTXLF_FC_OVRD_EN_MASK (0x1000U)
#define XCVR_TSM_OVRD1_SEQ_LDO_RXTXLF_FC_OVRD_EN_SHIFT (12U)
/*! SEQ_LDO_RXTXLF_FC_OVRD_EN - Override control for SEQ_LDO_RXTXLF_FC
 *  0b0..Normal operation.
 *  0b1..Use the state of SEQ_LDO_RXTXLF_FC_OVRD to override the signal "seq_ldo_rxtxlf_fc".
 */
#define XCVR_TSM_OVRD1_SEQ_LDO_RXTXLF_FC_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SEQ_LDO_RXTXLF_FC_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SEQ_LDO_RXTXLF_FC_OVRD_EN_MASK)

#define XCVR_TSM_OVRD1_SEQ_LDO_RXTXLF_FC_OVRD_MASK (0x2000U)
#define XCVR_TSM_OVRD1_SEQ_LDO_RXTXLF_FC_OVRD_SHIFT (13U)
/*! SEQ_LDO_RXTXLF_FC_OVRD - Override value for SEQ_LDO_RXTXLF_FC
 */
#define XCVR_TSM_OVRD1_SEQ_LDO_RXTXLF_FC_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SEQ_LDO_RXTXLF_FC_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SEQ_LDO_RXTXLF_FC_OVRD_MASK)

#define XCVR_TSM_OVRD1_SEQ_LDO_ANT_PUP_OVRD_EN_MASK (0x4000U)
#define XCVR_TSM_OVRD1_SEQ_LDO_ANT_PUP_OVRD_EN_SHIFT (14U)
/*! SEQ_LDO_ANT_PUP_OVRD_EN - Override control for SEQ_LDO_ANT_PUP
 *  0b0..Normal operation.
 *  0b1..Use the state of SEQ_LDO_ANT_PUP_OVRD to override the signal "seq_ldo_ant_pup".
 */
#define XCVR_TSM_OVRD1_SEQ_LDO_ANT_PUP_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SEQ_LDO_ANT_PUP_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SEQ_LDO_ANT_PUP_OVRD_EN_MASK)

#define XCVR_TSM_OVRD1_SEQ_LDO_ANT_PUP_OVRD_MASK (0x8000U)
#define XCVR_TSM_OVRD1_SEQ_LDO_ANT_PUP_OVRD_SHIFT (15U)
/*! SEQ_LDO_ANT_PUP_OVRD - Override value for SEQ_LDO_ANT_PUP
 */
#define XCVR_TSM_OVRD1_SEQ_LDO_ANT_PUP_OVRD(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SEQ_LDO_ANT_PUP_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SEQ_LDO_ANT_PUP_OVRD_MASK)

#define XCVR_TSM_OVRD1_SEQ_LDO_PLL_PUP_OVRD_EN_MASK (0x10000U)
#define XCVR_TSM_OVRD1_SEQ_LDO_PLL_PUP_OVRD_EN_SHIFT (16U)
/*! SEQ_LDO_PLL_PUP_OVRD_EN - Override control for SEQ_LDO_PLL_PUP
 *  0b0..Normal operation.
 *  0b1..Use the state of SEQ_LDO_PLL_PUP_OVRD to override the signal "seq_ldo_pll_pup".
 */
#define XCVR_TSM_OVRD1_SEQ_LDO_PLL_PUP_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SEQ_LDO_PLL_PUP_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SEQ_LDO_PLL_PUP_OVRD_EN_MASK)

#define XCVR_TSM_OVRD1_SEQ_LDO_PLL_PUP_OVRD_MASK (0x20000U)
#define XCVR_TSM_OVRD1_SEQ_LDO_PLL_PUP_OVRD_SHIFT (17U)
/*! SEQ_LDO_PLL_PUP_OVRD - Override value for SEQ_LDO_PLL_PUP
 */
#define XCVR_TSM_OVRD1_SEQ_LDO_PLL_PUP_OVRD(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SEQ_LDO_PLL_PUP_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SEQ_LDO_PLL_PUP_OVRD_MASK)

#define XCVR_TSM_OVRD1_SEQ_LDO_VCO_PUP_OVRD_EN_MASK (0x40000U)
#define XCVR_TSM_OVRD1_SEQ_LDO_VCO_PUP_OVRD_EN_SHIFT (18U)
/*! SEQ_LDO_VCO_PUP_OVRD_EN - Override control for SEQ_LDO_VCO_PUP
 *  0b0..Normal operation.
 *  0b1..Use the state of SEQ_LDO_VCO_PUP_OVRD to override the signal "seq_ldo_vco_pup".
 */
#define XCVR_TSM_OVRD1_SEQ_LDO_VCO_PUP_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SEQ_LDO_VCO_PUP_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SEQ_LDO_VCO_PUP_OVRD_EN_MASK)

#define XCVR_TSM_OVRD1_SEQ_LDO_VCO_PUP_OVRD_MASK (0x80000U)
#define XCVR_TSM_OVRD1_SEQ_LDO_VCO_PUP_OVRD_SHIFT (19U)
/*! SEQ_LDO_VCO_PUP_OVRD - Override value for SEQ_LDO_VCO_PUP
 */
#define XCVR_TSM_OVRD1_SEQ_LDO_VCO_PUP_OVRD(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SEQ_LDO_VCO_PUP_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SEQ_LDO_VCO_PUP_OVRD_MASK)

#define XCVR_TSM_OVRD1_SEQ_LDO_XO_DIST_PUP_OVRD_EN_MASK (0x100000U)
#define XCVR_TSM_OVRD1_SEQ_LDO_XO_DIST_PUP_OVRD_EN_SHIFT (20U)
/*! SEQ_LDO_XO_DIST_PUP_OVRD_EN - Override control for SEQ_LDO_XO_DIST_PUP
 *  0b0..Normal operation.
 *  0b1..Use the state of SEQ_LDO_XO_DIST_PUP_OVRD to override the signal "seq_ldo_xo_dist_pup".
 */
#define XCVR_TSM_OVRD1_SEQ_LDO_XO_DIST_PUP_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SEQ_LDO_XO_DIST_PUP_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SEQ_LDO_XO_DIST_PUP_OVRD_EN_MASK)

#define XCVR_TSM_OVRD1_SEQ_LDO_XO_DIST_PUP_OVRD_MASK (0x200000U)
#define XCVR_TSM_OVRD1_SEQ_LDO_XO_DIST_PUP_OVRD_SHIFT (21U)
/*! SEQ_LDO_XO_DIST_PUP_OVRD - Override value for SEQ_LDO_XO_DIST_PUP
 */
#define XCVR_TSM_OVRD1_SEQ_LDO_XO_DIST_PUP_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SEQ_LDO_XO_DIST_PUP_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SEQ_LDO_XO_DIST_PUP_OVRD_MASK)

#define XCVR_TSM_OVRD1_SEQ_LDO_RXTXHF_PUP_OVRD_EN_MASK (0x400000U)
#define XCVR_TSM_OVRD1_SEQ_LDO_RXTXHF_PUP_OVRD_EN_SHIFT (22U)
/*! SEQ_LDO_RXTXHF_PUP_OVRD_EN - Override control for SEQ_LDO_RXTXHF_PUP
 *  0b0..Normal operation.
 *  0b1..Use the state of SEQ_LDO_RXTXHF_PUP_OVRD to override the signal "seq_ldo_rxtxhf_pup".
 */
#define XCVR_TSM_OVRD1_SEQ_LDO_RXTXHF_PUP_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SEQ_LDO_RXTXHF_PUP_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SEQ_LDO_RXTXHF_PUP_OVRD_EN_MASK)

#define XCVR_TSM_OVRD1_SEQ_LDO_RXTXHF_PUP_OVRD_MASK (0x800000U)
#define XCVR_TSM_OVRD1_SEQ_LDO_RXTXHF_PUP_OVRD_SHIFT (23U)
/*! SEQ_LDO_RXTXHF_PUP_OVRD - Override value for SEQ_LDO_RXTXHF_PUP
 */
#define XCVR_TSM_OVRD1_SEQ_LDO_RXTXHF_PUP_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SEQ_LDO_RXTXHF_PUP_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SEQ_LDO_RXTXHF_PUP_OVRD_MASK)

#define XCVR_TSM_OVRD1_SEQ_LDO_RXTXLF_PUP_OVRD_EN_MASK (0x1000000U)
#define XCVR_TSM_OVRD1_SEQ_LDO_RXTXLF_PUP_OVRD_EN_SHIFT (24U)
/*! SEQ_LDO_RXTXLF_PUP_OVRD_EN - Override control for SEQ_LDO_RXTXLF_PUP
 *  0b0..Normal operation.
 *  0b1..Use the state of SEQ_LDO_RXTXLF_PUP_OVRD to override the signal "seq_ldo_rxtxlf_pup".
 */
#define XCVR_TSM_OVRD1_SEQ_LDO_RXTXLF_PUP_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SEQ_LDO_RXTXLF_PUP_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SEQ_LDO_RXTXLF_PUP_OVRD_EN_MASK)

#define XCVR_TSM_OVRD1_SEQ_LDO_RXTXLF_PUP_OVRD_MASK (0x2000000U)
#define XCVR_TSM_OVRD1_SEQ_LDO_RXTXLF_PUP_OVRD_SHIFT (25U)
/*! SEQ_LDO_RXTXLF_PUP_OVRD - Override value for SEQ_LDO_RXTXLF_PUP
 */
#define XCVR_TSM_OVRD1_SEQ_LDO_RXTXLF_PUP_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SEQ_LDO_RXTXLF_PUP_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SEQ_LDO_RXTXLF_PUP_OVRD_MASK)

#define XCVR_TSM_OVRD1_SEQ_LDO_LV_PUP_OVRD_EN_MASK (0x4000000U)
#define XCVR_TSM_OVRD1_SEQ_LDO_LV_PUP_OVRD_EN_SHIFT (26U)
/*! SEQ_LDO_LV_PUP_OVRD_EN - Override control for SEQ_LDO_LV_PUP
 *  0b0..Normal operation.
 *  0b1..Use the state of SEQ_LDO_LV_PUP_OVRD to override the signal "seq_ldo_lv_pup".
 */
#define XCVR_TSM_OVRD1_SEQ_LDO_LV_PUP_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SEQ_LDO_LV_PUP_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SEQ_LDO_LV_PUP_OVRD_EN_MASK)

#define XCVR_TSM_OVRD1_SEQ_LDO_LV_PUP_OVRD_MASK  (0x8000000U)
#define XCVR_TSM_OVRD1_SEQ_LDO_LV_PUP_OVRD_SHIFT (27U)
/*! SEQ_LDO_LV_PUP_OVRD - Override value for SEQ_LDO_LV_PUP
 */
#define XCVR_TSM_OVRD1_SEQ_LDO_LV_PUP_OVRD(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SEQ_LDO_LV_PUP_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SEQ_LDO_LV_PUP_OVRD_MASK)

#define XCVR_TSM_OVRD1_SEQ_BG_PUP_OVRD_EN_MASK   (0x10000000U)
#define XCVR_TSM_OVRD1_SEQ_BG_PUP_OVRD_EN_SHIFT  (28U)
/*! SEQ_BG_PUP_OVRD_EN - Override control for SEQ_BG_PUP_OVRD_EN
 *  0b0..Normal operation.
 *  0b1..Use the state of SEQ_BG_PUP_OVRD to override the signal "seq_bg_pup".
 */
#define XCVR_TSM_OVRD1_SEQ_BG_PUP_OVRD_EN(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SEQ_BG_PUP_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SEQ_BG_PUP_OVRD_EN_MASK)

#define XCVR_TSM_OVRD1_SEQ_BG_PUP_OVRD_MASK      (0x20000000U)
#define XCVR_TSM_OVRD1_SEQ_BG_PUP_OVRD_SHIFT     (29U)
/*! SEQ_BG_PUP_OVRD - Override value for SEQ_BG_PUP
 */
#define XCVR_TSM_OVRD1_SEQ_BG_PUP_OVRD(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SEQ_BG_PUP_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SEQ_BG_PUP_OVRD_MASK)

#define XCVR_TSM_OVRD1_SEQ_BG_PUP_IBG_ANT_OVRD_EN_MASK (0x40000000U)
#define XCVR_TSM_OVRD1_SEQ_BG_PUP_IBG_ANT_OVRD_EN_SHIFT (30U)
/*! SEQ_BG_PUP_IBG_ANT_OVRD_EN - Override control for SEQ_BG_PUP_IBG_ANT
 *  0b0..Normal operation.
 *  0b1..Use the state of SEQ_BG_PUP_IBG_ANT_OVRD to override the signal "seq_bg_pup_ibg_ant".
 */
#define XCVR_TSM_OVRD1_SEQ_BG_PUP_IBG_ANT_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SEQ_BG_PUP_IBG_ANT_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SEQ_BG_PUP_IBG_ANT_OVRD_EN_MASK)

#define XCVR_TSM_OVRD1_SEQ_BG_PUP_IBG_ANT_OVRD_MASK (0x80000000U)
#define XCVR_TSM_OVRD1_SEQ_BG_PUP_IBG_ANT_OVRD_SHIFT (31U)
/*! SEQ_BG_PUP_IBG_ANT_OVRD - Override value for SEQ_BG_PUP_IBG_ANT
 */
#define XCVR_TSM_OVRD1_SEQ_BG_PUP_IBG_ANT_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SEQ_BG_PUP_IBG_ANT_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SEQ_BG_PUP_IBG_ANT_OVRD_MASK)
/*! @} */

/*! @name OVRD2 - TSM OVERRIDE REGISTER 2 */
/*! @{ */

#define XCVR_TSM_OVRD2_SEQ_BG_PUP_IBG_XO_DIST_OVRD_EN_MASK (0x1U)
#define XCVR_TSM_OVRD2_SEQ_BG_PUP_IBG_XO_DIST_OVRD_EN_SHIFT (0U)
/*! SEQ_BG_PUP_IBG_XO_DIST_OVRD_EN - Override control for SEQ_BG_PUP_IBG_XO_DIST
 *  0b0..Normal operation.
 *  0b1..Use the state of SEQ_BG_PUP_IBG_XO_DIST_OVRD to override the signal "seq_bg_pup_ibg_xo_dist".
 */
#define XCVR_TSM_OVRD2_SEQ_BG_PUP_IBG_XO_DIST_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_SEQ_BG_PUP_IBG_XO_DIST_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_SEQ_BG_PUP_IBG_XO_DIST_OVRD_EN_MASK)

#define XCVR_TSM_OVRD2_SEQ_BG_PUP_IBG_XO_DIST_OVRD_MASK (0x2U)
#define XCVR_TSM_OVRD2_SEQ_BG_PUP_IBG_XO_DIST_OVRD_SHIFT (1U)
/*! SEQ_BG_PUP_IBG_XO_DIST_OVRD - Override value for SEQ_BG_PUP_IBG_XO_DIST
 */
#define XCVR_TSM_OVRD2_SEQ_BG_PUP_IBG_XO_DIST_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_SEQ_BG_PUP_IBG_XO_DIST_OVRD_SHIFT)) & XCVR_TSM_OVRD2_SEQ_BG_PUP_IBG_XO_DIST_OVRD_MASK)

#define XCVR_TSM_OVRD2_SEQ_BG_PUP_IBG_TX_OVRD_EN_MASK (0x4U)
#define XCVR_TSM_OVRD2_SEQ_BG_PUP_IBG_TX_OVRD_EN_SHIFT (2U)
/*! SEQ_BG_PUP_IBG_TX_OVRD_EN - Override control for SEQ_BG_PUP_IBG_TX
 *  0b0..Normal operation.
 *  0b1..Use the state of SEQ_BG_PUP_IBG_TX_OVRD to override the signal "seq_bg_pup_ibg_tx".
 */
#define XCVR_TSM_OVRD2_SEQ_BG_PUP_IBG_TX_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_SEQ_BG_PUP_IBG_TX_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_SEQ_BG_PUP_IBG_TX_OVRD_EN_MASK)

#define XCVR_TSM_OVRD2_SEQ_BG_PUP_IBG_TX_OVRD_MASK (0x8U)
#define XCVR_TSM_OVRD2_SEQ_BG_PUP_IBG_TX_OVRD_SHIFT (3U)
/*! SEQ_BG_PUP_IBG_TX_OVRD - Override value for SEQ_BG_PUP_IBG_TX
 */
#define XCVR_TSM_OVRD2_SEQ_BG_PUP_IBG_TX_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_SEQ_BG_PUP_IBG_TX_OVRD_SHIFT)) & XCVR_TSM_OVRD2_SEQ_BG_PUP_IBG_TX_OVRD_MASK)

#define XCVR_TSM_OVRD2_SEQ_BG_PUP_IBG_RX_OVRD_EN_MASK (0x10U)
#define XCVR_TSM_OVRD2_SEQ_BG_PUP_IBG_RX_OVRD_EN_SHIFT (4U)
/*! SEQ_BG_PUP_IBG_RX_OVRD_EN - Override control for SEQ_BG_PUP_IBG_RX
 *  0b0..Normal operation.
 *  0b1..Use the state of SEQ_BG_PUP_IBG_RX_OVRD to override the signal "seq_bg_pup_ibg_rx".
 */
#define XCVR_TSM_OVRD2_SEQ_BG_PUP_IBG_RX_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_SEQ_BG_PUP_IBG_RX_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_SEQ_BG_PUP_IBG_RX_OVRD_EN_MASK)

#define XCVR_TSM_OVRD2_SEQ_BG_PUP_IBG_RX_OVRD_MASK (0x20U)
#define XCVR_TSM_OVRD2_SEQ_BG_PUP_IBG_RX_OVRD_SHIFT (5U)
/*! SEQ_BG_PUP_IBG_RX_OVRD - Override value for SEQ_BG_PUP_IBG_RX
 */
#define XCVR_TSM_OVRD2_SEQ_BG_PUP_IBG_RX_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_SEQ_BG_PUP_IBG_RX_OVRD_SHIFT)) & XCVR_TSM_OVRD2_SEQ_BG_PUP_IBG_RX_OVRD_MASK)

#define XCVR_TSM_OVRD2_SEQ_TSM_ISO_B_2P4GHZ_OVRD_EN_MASK (0x40U)
#define XCVR_TSM_OVRD2_SEQ_TSM_ISO_B_2P4GHZ_OVRD_EN_SHIFT (6U)
/*! SEQ_TSM_ISO_B_2P4GHZ_OVRD_EN - Override control for SEQ_TSM_ISO_B_2P4GHZ
 *  0b0..Normal operation.
 *  0b1..Use the state of SEQ_TSM_ISO_B_2P4GHZ_OVRD to override the signal "seq_tsm_iso_b_2p4ghz".
 */
#define XCVR_TSM_OVRD2_SEQ_TSM_ISO_B_2P4GHZ_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_SEQ_TSM_ISO_B_2P4GHZ_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_SEQ_TSM_ISO_B_2P4GHZ_OVRD_EN_MASK)

#define XCVR_TSM_OVRD2_SEQ_TSM_ISO_B_2P4GHZ_OVRD_MASK (0x80U)
#define XCVR_TSM_OVRD2_SEQ_TSM_ISO_B_2P4GHZ_OVRD_SHIFT (7U)
/*! SEQ_TSM_ISO_B_2P4GHZ_OVRD - Override value for SEQ_TSM_ISO_B_2P4GHZ
 */
#define XCVR_TSM_OVRD2_SEQ_TSM_ISO_B_2P4GHZ_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_SEQ_TSM_ISO_B_2P4GHZ_OVRD_SHIFT)) & XCVR_TSM_OVRD2_SEQ_TSM_ISO_B_2P4GHZ_OVRD_MASK)

#define XCVR_TSM_OVRD2_SEQ_RCCAL_PUP_OVRD_EN_MASK (0x100U)
#define XCVR_TSM_OVRD2_SEQ_RCCAL_PUP_OVRD_EN_SHIFT (8U)
/*! SEQ_RCCAL_PUP_OVRD_EN - Override control for SEQ_RCCAL_PUP
 *  0b0..Normal operation.
 *  0b1..Use the state of SEQ_RCCAL_PUP_OVRD to override the signal "rx_rccal_pup".
 */
#define XCVR_TSM_OVRD2_SEQ_RCCAL_PUP_OVRD_EN(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_SEQ_RCCAL_PUP_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_SEQ_RCCAL_PUP_OVRD_EN_MASK)

#define XCVR_TSM_OVRD2_SEQ_RCCAL_PUP_OVRD_MASK   (0x200U)
#define XCVR_TSM_OVRD2_SEQ_RCCAL_PUP_OVRD_SHIFT  (9U)
/*! SEQ_RCCAL_PUP_OVRD - Override value for SEQ_RCCAL_PUP
 */
#define XCVR_TSM_OVRD2_SEQ_RCCAL_PUP_OVRD(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_SEQ_RCCAL_PUP_OVRD_SHIFT)) & XCVR_TSM_OVRD2_SEQ_RCCAL_PUP_OVRD_MASK)

#define XCVR_TSM_OVRD2_SEQ_PD_EN_FCAL_BIAS_OVRD_EN_MASK (0x400U)
#define XCVR_TSM_OVRD2_SEQ_PD_EN_FCAL_BIAS_OVRD_EN_SHIFT (10U)
/*! SEQ_PD_EN_FCAL_BIAS_OVRD_EN - Override control for SEQ_PD_EN_FCAL_BIAS
 *  0b0..Normal operation.
 *  0b1..Use the state of SEQ_PD_EN_FCAL_BIAS_OVRD to override the signal "seq_pd_en_fcal_bias".
 */
#define XCVR_TSM_OVRD2_SEQ_PD_EN_FCAL_BIAS_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_SEQ_PD_EN_FCAL_BIAS_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_SEQ_PD_EN_FCAL_BIAS_OVRD_EN_MASK)

#define XCVR_TSM_OVRD2_SEQ_PD_EN_FCAL_BIAS_OVRD_MASK (0x800U)
#define XCVR_TSM_OVRD2_SEQ_PD_EN_FCAL_BIAS_OVRD_SHIFT (11U)
/*! SEQ_PD_EN_FCAL_BIAS_OVRD - Override value for SEQ_PD_EN_FCAL_BIAS
 */
#define XCVR_TSM_OVRD2_SEQ_PD_EN_FCAL_BIAS_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_SEQ_PD_EN_FCAL_BIAS_OVRD_SHIFT)) & XCVR_TSM_OVRD2_SEQ_PD_EN_FCAL_BIAS_OVRD_MASK)

#define XCVR_TSM_OVRD2_SEQ_PD_PUP_OVRD_EN_MASK   (0x1000U)
#define XCVR_TSM_OVRD2_SEQ_PD_PUP_OVRD_EN_SHIFT  (12U)
/*! SEQ_PD_PUP_OVRD_EN - Override control for SEQ_PD_PUP
 *  0b0..Normal operation.
 *  0b1..Use the state of SEQ_PD_PUP_OVRD to override the signal "seq_pd_pup".
 */
#define XCVR_TSM_OVRD2_SEQ_PD_PUP_OVRD_EN(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_SEQ_PD_PUP_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_SEQ_PD_PUP_OVRD_EN_MASK)

#define XCVR_TSM_OVRD2_SEQ_PD_PUP_OVRD_MASK      (0x2000U)
#define XCVR_TSM_OVRD2_SEQ_PD_PUP_OVRD_SHIFT     (13U)
/*! SEQ_PD_PUP_OVRD - Override value for SEQ_PD_PUP
 */
#define XCVR_TSM_OVRD2_SEQ_PD_PUP_OVRD(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_SEQ_PD_PUP_OVRD_SHIFT)) & XCVR_TSM_OVRD2_SEQ_PD_PUP_OVRD_MASK)

#define XCVR_TSM_OVRD2_SEQ_VCO_PUP_OVRD_EN_MASK  (0x4000U)
#define XCVR_TSM_OVRD2_SEQ_VCO_PUP_OVRD_EN_SHIFT (14U)
/*! SEQ_VCO_PUP_OVRD_EN - Override control for SEQ_VCO_PUP
 *  0b0..Normal operation.
 *  0b1..Use the state of SEQ_VCO_PUP_OVRD to override the signal "seq_vco_pup".
 */
#define XCVR_TSM_OVRD2_SEQ_VCO_PUP_OVRD_EN(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_SEQ_VCO_PUP_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_SEQ_VCO_PUP_OVRD_EN_MASK)

#define XCVR_TSM_OVRD2_SEQ_VCO_PUP_OVRD_MASK     (0x8000U)
#define XCVR_TSM_OVRD2_SEQ_VCO_PUP_OVRD_SHIFT    (15U)
/*! SEQ_VCO_PUP_OVRD - Override value for SEQ_VCO_PUP
 */
#define XCVR_TSM_OVRD2_SEQ_VCO_PUP_OVRD(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_SEQ_VCO_PUP_OVRD_SHIFT)) & XCVR_TSM_OVRD2_SEQ_VCO_PUP_OVRD_MASK)

#define XCVR_TSM_OVRD2_SEQ_XO_DIST_EN_OVRD_EN_MASK (0x10000U)
#define XCVR_TSM_OVRD2_SEQ_XO_DIST_EN_OVRD_EN_SHIFT (16U)
/*! SEQ_XO_DIST_EN_OVRD_EN - Override control for SEQ_XO_DIST_EN
 *  0b0..Normal operation.
 *  0b1..Use the state of SEQ_XO_DIST_EN_OVRD to override the signal "seq_xo_dist_en".
 */
#define XCVR_TSM_OVRD2_SEQ_XO_DIST_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_SEQ_XO_DIST_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_SEQ_XO_DIST_EN_OVRD_EN_MASK)

#define XCVR_TSM_OVRD2_SEQ_XO_DIST_EN_OVRD_MASK  (0x20000U)
#define XCVR_TSM_OVRD2_SEQ_XO_DIST_EN_OVRD_SHIFT (17U)
/*! SEQ_XO_DIST_EN_OVRD - Override value for SEQ_XO_DIST_EN
 */
#define XCVR_TSM_OVRD2_SEQ_XO_DIST_EN_OVRD(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_SEQ_XO_DIST_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_SEQ_XO_DIST_EN_OVRD_MASK)

#define XCVR_TSM_OVRD2_SEQ_XO_DIST_EN_CLK_REF_OVRD_EN_MASK (0x40000U)
#define XCVR_TSM_OVRD2_SEQ_XO_DIST_EN_CLK_REF_OVRD_EN_SHIFT (18U)
/*! SEQ_XO_DIST_EN_CLK_REF_OVRD_EN - Override control for SEQ_XO_DIST_EN_CLK_REF
 *  0b0..Normal operation.
 *  0b1..Use the state of SEQ_XO_DIST_EN_CLK_REF_OVRD to override the signal "seq_xo_dist_en_clk_ref".
 */
#define XCVR_TSM_OVRD2_SEQ_XO_DIST_EN_CLK_REF_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_SEQ_XO_DIST_EN_CLK_REF_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_SEQ_XO_DIST_EN_CLK_REF_OVRD_EN_MASK)

#define XCVR_TSM_OVRD2_SEQ_XO_DIST_EN_CLK_REF_OVRD_MASK (0x80000U)
#define XCVR_TSM_OVRD2_SEQ_XO_DIST_EN_CLK_REF_OVRD_SHIFT (19U)
/*! SEQ_XO_DIST_EN_CLK_REF_OVRD - Override value for SEQ_XO_DIST_EN_CLK_REF
 */
#define XCVR_TSM_OVRD2_SEQ_XO_DIST_EN_CLK_REF_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_SEQ_XO_DIST_EN_CLK_REF_OVRD_SHIFT)) & XCVR_TSM_OVRD2_SEQ_XO_DIST_EN_CLK_REF_OVRD_MASK)

#define XCVR_TSM_OVRD2_SEQ_XO_EN_CLK_2P4G_OVRD_EN_MASK (0x100000U)
#define XCVR_TSM_OVRD2_SEQ_XO_EN_CLK_2P4G_OVRD_EN_SHIFT (20U)
/*! SEQ_XO_EN_CLK_2P4G_OVRD_EN - Override control for SEQ_XO_EN_CLK_2P4G
 *  0b0..Normal operation.
 *  0b1..Use the state of SEQ_XO_EN_CLK_2P4G_OVRD to override the signal "seq_xo_en_clk_2p4g".
 */
#define XCVR_TSM_OVRD2_SEQ_XO_EN_CLK_2P4G_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_SEQ_XO_EN_CLK_2P4G_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_SEQ_XO_EN_CLK_2P4G_OVRD_EN_MASK)

#define XCVR_TSM_OVRD2_SEQ_XO_EN_CLK_2P4G_OVRD_MASK (0x200000U)
#define XCVR_TSM_OVRD2_SEQ_XO_EN_CLK_2P4G_OVRD_SHIFT (21U)
/*! SEQ_XO_EN_CLK_2P4G_OVRD - Override value for SEQ_XO_EN_CLK_2P4G_OVRD_EN
 */
#define XCVR_TSM_OVRD2_SEQ_XO_EN_CLK_2P4G_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_SEQ_XO_EN_CLK_2P4G_OVRD_SHIFT)) & XCVR_TSM_OVRD2_SEQ_XO_EN_CLK_2P4G_OVRD_MASK)

#define XCVR_TSM_OVRD2_SEQ_XO_DIST_EN_CLK_ADCDAC_OVRD_EN_MASK (0x400000U)
#define XCVR_TSM_OVRD2_SEQ_XO_DIST_EN_CLK_ADCDAC_OVRD_EN_SHIFT (22U)
/*! SEQ_XO_DIST_EN_CLK_ADCDAC_OVRD_EN - Override control for SEQ_XO_DIST_EN_CLK_ADCDAC
 *  0b0..Normal operation.
 *  0b1..Use the state of SEQ_XO_DIST_EN_CLK_ADCDAC_OVRD_EN to override the signal "seq_xo_dist_en_clk_adcdac".
 */
#define XCVR_TSM_OVRD2_SEQ_XO_DIST_EN_CLK_ADCDAC_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_SEQ_XO_DIST_EN_CLK_ADCDAC_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_SEQ_XO_DIST_EN_CLK_ADCDAC_OVRD_EN_MASK)

#define XCVR_TSM_OVRD2_SEQ_XO_DIST_EN_CLK_ADCDAC_OVRD_MASK (0x800000U)
#define XCVR_TSM_OVRD2_SEQ_XO_DIST_EN_CLK_ADCDAC_OVRD_SHIFT (23U)
/*! SEQ_XO_DIST_EN_CLK_ADCDAC_OVRD - Override value for SEQ_XO_DIST_EN_CLK_ADCDAC
 */
#define XCVR_TSM_OVRD2_SEQ_XO_DIST_EN_CLK_ADCDAC_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_SEQ_XO_DIST_EN_CLK_ADCDAC_OVRD_SHIFT)) & XCVR_TSM_OVRD2_SEQ_XO_DIST_EN_CLK_ADCDAC_OVRD_MASK)

#define XCVR_TSM_OVRD2_SEQ_DAC_PUP_OVRD_EN_MASK  (0x1000000U)
#define XCVR_TSM_OVRD2_SEQ_DAC_PUP_OVRD_EN_SHIFT (24U)
/*! SEQ_DAC_PUP_OVRD_EN - Override control for SEQ_DAC_PUP
 *  0b0..Normal operation.
 *  0b1..Use the state of SEQ_DAC_PUP_OVRD to override the signal "seq_dac_pup".
 */
#define XCVR_TSM_OVRD2_SEQ_DAC_PUP_OVRD_EN(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_SEQ_DAC_PUP_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_SEQ_DAC_PUP_OVRD_EN_MASK)

#define XCVR_TSM_OVRD2_SEQ_DAC_PUP_OVRD_MASK     (0x2000000U)
#define XCVR_TSM_OVRD2_SEQ_DAC_PUP_OVRD_SHIFT    (25U)
/*! SEQ_DAC_PUP_OVRD - Override value for SEQ_DAC_PUP
 */
#define XCVR_TSM_OVRD2_SEQ_DAC_PUP_OVRD(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_SEQ_DAC_PUP_OVRD_SHIFT)) & XCVR_TSM_OVRD2_SEQ_DAC_PUP_OVRD_MASK)

#define XCVR_TSM_OVRD2_SEQ_VCO_EN_HPM_OVRD_EN_MASK (0x4000000U)
#define XCVR_TSM_OVRD2_SEQ_VCO_EN_HPM_OVRD_EN_SHIFT (26U)
/*! SEQ_VCO_EN_HPM_OVRD_EN - Override control for SEQ_VCO_EN_HPM
 *  0b0..Normal operation.
 *  0b1..Use the state of SEQ_VCO_EN_HPM_OVRD to override the signal "seq_vco_en_hpm".
 */
#define XCVR_TSM_OVRD2_SEQ_VCO_EN_HPM_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_SEQ_VCO_EN_HPM_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_SEQ_VCO_EN_HPM_OVRD_EN_MASK)

#define XCVR_TSM_OVRD2_SEQ_VCO_EN_HPM_OVRD_MASK  (0x8000000U)
#define XCVR_TSM_OVRD2_SEQ_VCO_EN_HPM_OVRD_SHIFT (27U)
/*! SEQ_VCO_EN_HPM_OVRD - Override value for SEQ_VCO_EN_HPM
 */
#define XCVR_TSM_OVRD2_SEQ_VCO_EN_HPM_OVRD(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_SEQ_VCO_EN_HPM_OVRD_SHIFT)) & XCVR_TSM_OVRD2_SEQ_VCO_EN_HPM_OVRD_MASK)

#define XCVR_TSM_OVRD2_SEQ_LO_PUP_VLO_FBK_OVRD_EN_MASK (0x10000000U)
#define XCVR_TSM_OVRD2_SEQ_LO_PUP_VLO_FBK_OVRD_EN_SHIFT (28U)
/*! SEQ_LO_PUP_VLO_FBK_OVRD_EN - Override control for SEQ_LO_PUP_VLO_FBK
 *  0b0..Normal operation.
 *  0b1..Use the state of SEQ_LO_PUP_VLO_FBK_OVRD to override the signal "seq_lo_pup_vlo_fbk".
 */
#define XCVR_TSM_OVRD2_SEQ_LO_PUP_VLO_FBK_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_SEQ_LO_PUP_VLO_FBK_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_SEQ_LO_PUP_VLO_FBK_OVRD_EN_MASK)

#define XCVR_TSM_OVRD2_SEQ_LO_PUP_VLO_FBK_OVRD_MASK (0x20000000U)
#define XCVR_TSM_OVRD2_SEQ_LO_PUP_VLO_FBK_OVRD_SHIFT (29U)
/*! SEQ_LO_PUP_VLO_FBK_OVRD - Override value for SEQ_LO_PUP_VLO_FBK
 */
#define XCVR_TSM_OVRD2_SEQ_LO_PUP_VLO_FBK_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_SEQ_LO_PUP_VLO_FBK_OVRD_SHIFT)) & XCVR_TSM_OVRD2_SEQ_LO_PUP_VLO_FBK_OVRD_MASK)

#define XCVR_TSM_OVRD2_SEQ_LO_PUP_VLO_RXDRV_OVRD_EN_MASK (0x40000000U)
#define XCVR_TSM_OVRD2_SEQ_LO_PUP_VLO_RXDRV_OVRD_EN_SHIFT (30U)
/*! SEQ_LO_PUP_VLO_RXDRV_OVRD_EN - Override control for SEQ_LO_PUP_VLO_RXDRV
 *  0b0..Normal operation.
 *  0b1..Use the state of SEQ_LO_PUP_VLO_RXDRV_OVRD to override the signal "seq_lo_pup_vlo_rxdrv".
 */
#define XCVR_TSM_OVRD2_SEQ_LO_PUP_VLO_RXDRV_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_SEQ_LO_PUP_VLO_RXDRV_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_SEQ_LO_PUP_VLO_RXDRV_OVRD_EN_MASK)

#define XCVR_TSM_OVRD2_SEQ_LO_PUP_VLO_RXDRV_OVRD_MASK (0x80000000U)
#define XCVR_TSM_OVRD2_SEQ_LO_PUP_VLO_RXDRV_OVRD_SHIFT (31U)
/*! SEQ_LO_PUP_VLO_RXDRV_OVRD - Override value for SEQ_LO_PUP_VLO_RXDRV
 */
#define XCVR_TSM_OVRD2_SEQ_LO_PUP_VLO_RXDRV_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_SEQ_LO_PUP_VLO_RXDRV_OVRD_SHIFT)) & XCVR_TSM_OVRD2_SEQ_LO_PUP_VLO_RXDRV_OVRD_MASK)
/*! @} */

/*! @name OVRD3 - TSM OVERRIDE REGISTER 3 */
/*! @{ */

#define XCVR_TSM_OVRD3_SEQ_LO_PUP_VLO_RX_OVRD_EN_MASK (0x1U)
#define XCVR_TSM_OVRD3_SEQ_LO_PUP_VLO_RX_OVRD_EN_SHIFT (0U)
/*! SEQ_LO_PUP_VLO_RX_OVRD_EN - Override control for SEQ_LO_PUP_VLO_RX
 *  0b0..Normal operation.
 *  0b1..Use the state of SEQ_LO_PUP_VLO_RX_OVRD to override the signal "seq_lo_pup_vlo_rx".
 */
#define XCVR_TSM_OVRD3_SEQ_LO_PUP_VLO_RX_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_SEQ_LO_PUP_VLO_RX_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_SEQ_LO_PUP_VLO_RX_OVRD_EN_MASK)

#define XCVR_TSM_OVRD3_SEQ_LO_PUP_VLO_RX_OVRD_MASK (0x2U)
#define XCVR_TSM_OVRD3_SEQ_LO_PUP_VLO_RX_OVRD_SHIFT (1U)
/*! SEQ_LO_PUP_VLO_RX_OVRD - Override value for SEQ_LO_PUP_VLO_RX
 */
#define XCVR_TSM_OVRD3_SEQ_LO_PUP_VLO_RX_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_SEQ_LO_PUP_VLO_RX_OVRD_SHIFT)) & XCVR_TSM_OVRD3_SEQ_LO_PUP_VLO_RX_OVRD_MASK)

#define XCVR_TSM_OVRD3_SEQ_LO_PUP_VLO_TX_OVRD_EN_MASK (0x4U)
#define XCVR_TSM_OVRD3_SEQ_LO_PUP_VLO_TX_OVRD_EN_SHIFT (2U)
/*! SEQ_LO_PUP_VLO_TX_OVRD_EN - Override control for SEQ_LO_PUP_VLO_TX
 *  0b0..Normal operation.
 *  0b1..Use the state of SEQ_LO_PUP_VLO_TX_OVRD to override the signal "seq_lo_pup_vlo_tx".
 */
#define XCVR_TSM_OVRD3_SEQ_LO_PUP_VLO_TX_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_SEQ_LO_PUP_VLO_TX_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_SEQ_LO_PUP_VLO_TX_OVRD_EN_MASK)

#define XCVR_TSM_OVRD3_SEQ_LO_PUP_VLO_TX_OVRD_MASK (0x8U)
#define XCVR_TSM_OVRD3_SEQ_LO_PUP_VLO_TX_OVRD_SHIFT (3U)
/*! SEQ_LO_PUP_VLO_TX_OVRD - Override value for SEQ_LO_PUP_VLO_TX
 */
#define XCVR_TSM_OVRD3_SEQ_LO_PUP_VLO_TX_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_SEQ_LO_PUP_VLO_TX_OVRD_SHIFT)) & XCVR_TSM_OVRD3_SEQ_LO_PUP_VLO_TX_OVRD_MASK)

#define XCVR_TSM_OVRD3_SEQ_LO_PUP_VLO_TXDRV_OVRD_EN_MASK (0x10U)
#define XCVR_TSM_OVRD3_SEQ_LO_PUP_VLO_TXDRV_OVRD_EN_SHIFT (4U)
/*! SEQ_LO_PUP_VLO_TXDRV_OVRD_EN - Override control for SEQ_LO_PUP_VLO_TXDRV
 *  0b0..Normal operation.
 *  0b1..Use the state of SEQ_LO_PUP_VLO_TXDRV_OVRD to override the signal "seq_lo_pup_vlo_txdrv".
 */
#define XCVR_TSM_OVRD3_SEQ_LO_PUP_VLO_TXDRV_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_SEQ_LO_PUP_VLO_TXDRV_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_SEQ_LO_PUP_VLO_TXDRV_OVRD_EN_MASK)

#define XCVR_TSM_OVRD3_SEQ_LO_PUP_VLO_TXDRV_OVRD_MASK (0x20U)
#define XCVR_TSM_OVRD3_SEQ_LO_PUP_VLO_TXDRV_OVRD_SHIFT (5U)
/*! SEQ_LO_PUP_VLO_TXDRV_OVRD - Override value for SEQ_LO_PUP_VLO_TXDRV
 */
#define XCVR_TSM_OVRD3_SEQ_LO_PUP_VLO_TXDRV_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_SEQ_LO_PUP_VLO_TXDRV_OVRD_SHIFT)) & XCVR_TSM_OVRD3_SEQ_LO_PUP_VLO_TXDRV_OVRD_MASK)

#define XCVR_TSM_OVRD3_SEQ_DIVN_PUP_OVRD_EN_MASK (0x40U)
#define XCVR_TSM_OVRD3_SEQ_DIVN_PUP_OVRD_EN_SHIFT (6U)
/*! SEQ_DIVN_PUP_OVRD_EN - Override control for SEQ_DIVN_PUP
 *  0b0..Normal operation.
 *  0b1..Use the state of SEQ_DIVN_PUP_OVRD to override the signal "seq_divn_pup".
 */
#define XCVR_TSM_OVRD3_SEQ_DIVN_PUP_OVRD_EN(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_SEQ_DIVN_PUP_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_SEQ_DIVN_PUP_OVRD_EN_MASK)

#define XCVR_TSM_OVRD3_SEQ_DIVN_PUP_OVRD_MASK    (0x80U)
#define XCVR_TSM_OVRD3_SEQ_DIVN_PUP_OVRD_SHIFT   (7U)
/*! SEQ_DIVN_PUP_OVRD - Override value for SEQ_DIVN_PUP
 */
#define XCVR_TSM_OVRD3_SEQ_DIVN_PUP_OVRD(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_SEQ_DIVN_PUP_OVRD_SHIFT)) & XCVR_TSM_OVRD3_SEQ_DIVN_PUP_OVRD_MASK)

#define XCVR_TSM_OVRD3_SEQ_DIVN_OPENLOOP_OVRD_EN_MASK (0x100U)
#define XCVR_TSM_OVRD3_SEQ_DIVN_OPENLOOP_OVRD_EN_SHIFT (8U)
/*! SEQ_DIVN_OPENLOOP_OVRD_EN - Override control for SEQ_DIVN_OPENLOOP
 *  0b0..Normal operation.
 *  0b1..Use the state of SEQ_DIVN_OPENLOOP_OVRD to override the signal "seq_divn_openloop".
 */
#define XCVR_TSM_OVRD3_SEQ_DIVN_OPENLOOP_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_SEQ_DIVN_OPENLOOP_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_SEQ_DIVN_OPENLOOP_OVRD_EN_MASK)

#define XCVR_TSM_OVRD3_SEQ_DIVN_OPENLOOP_OVRD_MASK (0x200U)
#define XCVR_TSM_OVRD3_SEQ_DIVN_OPENLOOP_OVRD_SHIFT (9U)
/*! SEQ_DIVN_OPENLOOP_OVRD - Override value for SEQ_DIVN_OPENLOOP
 */
#define XCVR_TSM_OVRD3_SEQ_DIVN_OPENLOOP_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_SEQ_DIVN_OPENLOOP_OVRD_SHIFT)) & XCVR_TSM_OVRD3_SEQ_DIVN_OPENLOOP_OVRD_MASK)

#define XCVR_TSM_OVRD3_SEQ_PD_EN_PD_DRV_OVRD_EN_MASK (0x400U)
#define XCVR_TSM_OVRD3_SEQ_PD_EN_PD_DRV_OVRD_EN_SHIFT (10U)
/*! SEQ_PD_EN_PD_DRV_OVRD_EN - Override control for SEQ_PD_EN_PD_DRV
 *  0b0..Normal operation.
 *  0b1..Use the state of SEQ_PD_EN_PD_DRV_OVRD to override the signal "seq_pd_en_pd_drv".
 */
#define XCVR_TSM_OVRD3_SEQ_PD_EN_PD_DRV_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_SEQ_PD_EN_PD_DRV_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_SEQ_PD_EN_PD_DRV_OVRD_EN_MASK)

#define XCVR_TSM_OVRD3_SEQ_PD_EN_PD_DRV_OVRD_MASK (0x800U)
#define XCVR_TSM_OVRD3_SEQ_PD_EN_PD_DRV_OVRD_SHIFT (11U)
/*! SEQ_PD_EN_PD_DRV_OVRD - Override value for SEQ_PD_EN_PD_DRV
 */
#define XCVR_TSM_OVRD3_SEQ_PD_EN_PD_DRV_OVRD(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_SEQ_PD_EN_PD_DRV_OVRD_SHIFT)) & XCVR_TSM_OVRD3_SEQ_PD_EN_PD_DRV_OVRD_MASK)

#define XCVR_TSM_OVRD3_SEQ_CBPF_EN_DCOC_OVRD_EN_MASK (0x1000U)
#define XCVR_TSM_OVRD3_SEQ_CBPF_EN_DCOC_OVRD_EN_SHIFT (12U)
/*! SEQ_CBPF_EN_DCOC_OVRD_EN - Override control for SEQ_CBPF_EN_DCOC
 *  0b0..Normal operation.
 *  0b1..Use the state of SEQ_CBPF_EN_DCOC_OVRD to override the signal "seq_cbpf_en_dcoc".
 */
#define XCVR_TSM_OVRD3_SEQ_CBPF_EN_DCOC_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_SEQ_CBPF_EN_DCOC_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_SEQ_CBPF_EN_DCOC_OVRD_EN_MASK)

#define XCVR_TSM_OVRD3_SEQ_CBPF_EN_DCOC_OVRD_MASK (0x2000U)
#define XCVR_TSM_OVRD3_SEQ_CBPF_EN_DCOC_OVRD_SHIFT (13U)
/*! SEQ_CBPF_EN_DCOC_OVRD - Override value for SEQ_CBPF_EN_DCOC
 */
#define XCVR_TSM_OVRD3_SEQ_CBPF_EN_DCOC_OVRD(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_SEQ_CBPF_EN_DCOC_OVRD_SHIFT)) & XCVR_TSM_OVRD3_SEQ_CBPF_EN_DCOC_OVRD_MASK)

#define XCVR_TSM_OVRD3_SEQ_RX_LNA_PUP_OVRD_EN_MASK (0x4000U)
#define XCVR_TSM_OVRD3_SEQ_RX_LNA_PUP_OVRD_EN_SHIFT (14U)
/*! SEQ_RX_LNA_PUP_OVRD_EN - Override control for SEQ_RX_LNA_PUP
 *  0b0..Normal operation.
 *  0b1..Use the state of SEQ_RX_LNA_PUP_OVRD to override the signal "seq_rx_lna_pup".
 */
#define XCVR_TSM_OVRD3_SEQ_RX_LNA_PUP_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_SEQ_RX_LNA_PUP_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_SEQ_RX_LNA_PUP_OVRD_EN_MASK)

#define XCVR_TSM_OVRD3_SEQ_RX_LNA_PUP_OVRD_MASK  (0x8000U)
#define XCVR_TSM_OVRD3_SEQ_RX_LNA_PUP_OVRD_SHIFT (15U)
/*! SEQ_RX_LNA_PUP_OVRD - Override value for SEQ_RX_LNA_PUP
 */
#define XCVR_TSM_OVRD3_SEQ_RX_LNA_PUP_OVRD(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_SEQ_RX_LNA_PUP_OVRD_SHIFT)) & XCVR_TSM_OVRD3_SEQ_RX_LNA_PUP_OVRD_MASK)

#define XCVR_TSM_OVRD3_SEQ_ADC_PUP_OVRD_EN_MASK  (0x10000U)
#define XCVR_TSM_OVRD3_SEQ_ADC_PUP_OVRD_EN_SHIFT (16U)
/*! SEQ_ADC_PUP_OVRD_EN - Override control for SEQ_ADC_PUP
 *  0b0..Normal operation.
 *  0b1..Use the state of SEQ_ADC_PUP_OVRD to override the signal "seq_adc_pup".
 */
#define XCVR_TSM_OVRD3_SEQ_ADC_PUP_OVRD_EN(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_SEQ_ADC_PUP_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_SEQ_ADC_PUP_OVRD_EN_MASK)

#define XCVR_TSM_OVRD3_SEQ_ADC_PUP_OVRD_MASK     (0x20000U)
#define XCVR_TSM_OVRD3_SEQ_ADC_PUP_OVRD_SHIFT    (17U)
/*! SEQ_ADC_PUP_OVRD - Override value for RX_DIG_EN
 */
#define XCVR_TSM_OVRD3_SEQ_ADC_PUP_OVRD(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_SEQ_ADC_PUP_OVRD_SHIFT)) & XCVR_TSM_OVRD3_SEQ_ADC_PUP_OVRD_MASK)

#define XCVR_TSM_OVRD3_SEQ_CBPF_PUP_OVRD_EN_MASK (0x40000U)
#define XCVR_TSM_OVRD3_SEQ_CBPF_PUP_OVRD_EN_SHIFT (18U)
/*! SEQ_CBPF_PUP_OVRD_EN - Override control for SEQ_CBPF_PUP
 *  0b0..Normal operation.
 *  0b1..Use the state of SEQ_CBPF_PUP_OVRD to override the signal "seq_cbpf_pup".
 */
#define XCVR_TSM_OVRD3_SEQ_CBPF_PUP_OVRD_EN(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_SEQ_CBPF_PUP_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_SEQ_CBPF_PUP_OVRD_EN_MASK)

#define XCVR_TSM_OVRD3_SEQ_CBPF_PUP_OVRD_MASK    (0x80000U)
#define XCVR_TSM_OVRD3_SEQ_CBPF_PUP_OVRD_SHIFT   (19U)
/*! SEQ_CBPF_PUP_OVRD - Override value for SEQ_CBPF_PUP
 */
#define XCVR_TSM_OVRD3_SEQ_CBPF_PUP_OVRD(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_SEQ_CBPF_PUP_OVRD_SHIFT)) & XCVR_TSM_OVRD3_SEQ_CBPF_PUP_OVRD_MASK)

#define XCVR_TSM_OVRD3_SEQ_RX_MIX_PUP_OVRD_EN_MASK (0x100000U)
#define XCVR_TSM_OVRD3_SEQ_RX_MIX_PUP_OVRD_EN_SHIFT (20U)
/*! SEQ_RX_MIX_PUP_OVRD_EN - Override control for SEQ_RX_MIX_PUP
 *  0b0..Normal operation.
 *  0b1..Use the state of SEQ_RX_MIX_PUP_OVRD to override the signal "seq_rx_mix_pup".
 */
#define XCVR_TSM_OVRD3_SEQ_RX_MIX_PUP_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_SEQ_RX_MIX_PUP_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_SEQ_RX_MIX_PUP_OVRD_EN_MASK)

#define XCVR_TSM_OVRD3_SEQ_RX_MIX_PUP_OVRD_MASK  (0x200000U)
#define XCVR_TSM_OVRD3_SEQ_RX_MIX_PUP_OVRD_SHIFT (21U)
/*! SEQ_RX_MIX_PUP_OVRD - Override control for SEQ_RX_MIX_PUP
 *  0b0..Normal operation.
 *  0b1..Use the state of SEQ_RX_MIX_PUP_OVRD to override the signal "seq_rx_mix_pup".
 */
#define XCVR_TSM_OVRD3_SEQ_RX_MIX_PUP_OVRD(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_SEQ_RX_MIX_PUP_OVRD_SHIFT)) & XCVR_TSM_OVRD3_SEQ_RX_MIX_PUP_OVRD_MASK)

#define XCVR_TSM_OVRD3_SEQ_SPARE1_OVRD_EN_MASK   (0x400000U)
#define XCVR_TSM_OVRD3_SEQ_SPARE1_OVRD_EN_SHIFT  (22U)
/*! SEQ_SPARE1_OVRD_EN - Override control for SEQ_SPARE1
 *  0b0..Normal operation.
 *  0b1..Use the state of SEQ_SPARE1_OVRD to override the signal "seq_spare1".
 */
#define XCVR_TSM_OVRD3_SEQ_SPARE1_OVRD_EN(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_SEQ_SPARE1_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_SEQ_SPARE1_OVRD_EN_MASK)

#define XCVR_TSM_OVRD3_SEQ_SPARE1_OVRD_MASK      (0x800000U)
#define XCVR_TSM_OVRD3_SEQ_SPARE1_OVRD_SHIFT     (23U)
/*! SEQ_SPARE1_OVRD - Override value for SEQ_SPARE1
 */
#define XCVR_TSM_OVRD3_SEQ_SPARE1_OVRD(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_SEQ_SPARE1_OVRD_SHIFT)) & XCVR_TSM_OVRD3_SEQ_SPARE1_OVRD_MASK)

#define XCVR_TSM_OVRD3_SEQ_SPARE3_OVRD_EN_MASK   (0x1000000U)
#define XCVR_TSM_OVRD3_SEQ_SPARE3_OVRD_EN_SHIFT  (24U)
/*! SEQ_SPARE3_OVRD_EN - Override control for SEQ_SPARE3
 *  0b0..Normal operation.
 *  0b1..Use the state of SEQ_SPARE3_OVRD to override the signal "seq_spare3".
 */
#define XCVR_TSM_OVRD3_SEQ_SPARE3_OVRD_EN(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_SEQ_SPARE3_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_SEQ_SPARE3_OVRD_EN_MASK)

#define XCVR_TSM_OVRD3_SEQ_SPARE3_OVRD_MASK      (0x2000000U)
#define XCVR_TSM_OVRD3_SEQ_SPARE3_OVRD_SHIFT     (25U)
/*! SEQ_SPARE3_OVRD - Override value for SEQ_SPARE3
 */
#define XCVR_TSM_OVRD3_SEQ_SPARE3_OVRD(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_SEQ_SPARE3_OVRD_SHIFT)) & XCVR_TSM_OVRD3_SEQ_SPARE3_OVRD_MASK)

#define XCVR_TSM_OVRD3_TX_MODE_OVRD_EN_MASK      (0x4000000U)
#define XCVR_TSM_OVRD3_TX_MODE_OVRD_EN_SHIFT     (26U)
/*! TX_MODE_OVRD_EN - Override control for TX_MODE_OVRD
 *  0b0..Normal operation.
 *  0b1..Use the state of TX_MODE_OVRD to override the signal "tx_mode".
 */
#define XCVR_TSM_OVRD3_TX_MODE_OVRD_EN(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TX_MODE_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_TX_MODE_OVRD_EN_MASK)

#define XCVR_TSM_OVRD3_TX_MODE_OVRD_MASK         (0x8000000U)
#define XCVR_TSM_OVRD3_TX_MODE_OVRD_SHIFT        (27U)
/*! TX_MODE_OVRD - Override value for TX_MODE
 */
#define XCVR_TSM_OVRD3_TX_MODE_OVRD(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TX_MODE_OVRD_SHIFT)) & XCVR_TSM_OVRD3_TX_MODE_OVRD_MASK)

#define XCVR_TSM_OVRD3_RX_MODE_OVRD_EN_MASK      (0x10000000U)
#define XCVR_TSM_OVRD3_RX_MODE_OVRD_EN_SHIFT     (28U)
/*! RX_MODE_OVRD_EN - Override control for RX_MODE
 *  0b0..Normal operation.
 *  0b1..Use the state of RX_MODE_OVRD to override the signal "rx_mode".
 */
#define XCVR_TSM_OVRD3_RX_MODE_OVRD_EN(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RX_MODE_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_RX_MODE_OVRD_EN_MASK)

#define XCVR_TSM_OVRD3_RX_MODE_OVRD_MASK         (0x20000000U)
#define XCVR_TSM_OVRD3_RX_MODE_OVRD_SHIFT        (29U)
/*! RX_MODE_OVRD - Override value for RX_MODE
 */
#define XCVR_TSM_OVRD3_RX_MODE_OVRD(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RX_MODE_OVRD_SHIFT)) & XCVR_TSM_OVRD3_RX_MODE_OVRD_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group XCVR_TSM_Register_Masks */


/* XCVR_TSM - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral XCVR_TSM base address */
  #define XCVR_TSM_BASE                            (0x58A07800u)
  /** Peripheral XCVR_TSM base address */
  #define XCVR_TSM_BASE_NS                         (0x48A07800u)
  /** Peripheral XCVR_TSM base pointer */
  #define XCVR_TSM                                 ((XCVR_TSM_Type *)XCVR_TSM_BASE)
  /** Peripheral XCVR_TSM base pointer */
  #define XCVR_TSM_NS                              ((XCVR_TSM_Type *)XCVR_TSM_BASE_NS)
  /** Array initializer of XCVR_TSM peripheral base addresses */
  #define XCVR_TSM_BASE_ADDRS                      { XCVR_TSM_BASE }
  /** Array initializer of XCVR_TSM peripheral base pointers */
  #define XCVR_TSM_BASE_PTRS                       { XCVR_TSM }
  /** Array initializer of XCVR_TSM peripheral base addresses */
  #define XCVR_TSM_BASE_ADDRS_NS                   { XCVR_TSM_BASE_NS }
  /** Array initializer of XCVR_TSM peripheral base pointers */
  #define XCVR_TSM_BASE_PTRS_NS                    { XCVR_TSM_NS }
#else
  /** Peripheral XCVR_TSM base address */
  #define XCVR_TSM_BASE                            (0x48A07800u)
  /** Peripheral XCVR_TSM base pointer */
  #define XCVR_TSM                                 ((XCVR_TSM_Type *)XCVR_TSM_BASE)
  /** Array initializer of XCVR_TSM peripheral base addresses */
  #define XCVR_TSM_BASE_ADDRS                      { XCVR_TSM_BASE }
  /** Array initializer of XCVR_TSM peripheral base pointers */
  #define XCVR_TSM_BASE_PTRS                       { XCVR_TSM }
#endif

/*!
 * @}
 */ /* end of group XCVR_TSM_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- XCVR_TX_DIG Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup XCVR_TX_DIG_Peripheral_Access_Layer XCVR_TX_DIG Peripheral Access Layer
 * @{
 */

/** XCVR_TX_DIG - Register Layout Typedef */
typedef struct {
  __IO uint32_t TXDIG_CTRL;                        /**< TXDIG_CTRL, offset: 0x0 */
  __IO uint32_t DATA_PADDING_CTRL;                 /**< DATA_PADDING_CTRL, offset: 0x4 */
  __IO uint32_t DATA_PADDING_CTRL_1;               /**< DATA_PADDING_CTRL_1, offset: 0x8 */
  __IO uint32_t DATA_PADDING_CTRL_2;               /**< DATA_PADDING_CTRL_2, offset: 0xC */
  __IO uint32_t FSK_CTRL;                          /**< FSK_CTRL, offset: 0x10 */
  __IO uint32_t GFSK_CTRL;                         /**< GFSK_CTRL, offset: 0x14 */
  __IO uint32_t GFSK_COEFF_0_1;                    /**< GFSK_COEFF_0_1, offset: 0x18 */
  __IO uint32_t GFSK_COEFF_2_3;                    /**< GFSK_COEFF_2_3, offset: 0x1C */
  __IO uint32_t GFSK_COEFF_4_5;                    /**< GFSK_COEFF_4_5, offset: 0x20 */
  __IO uint32_t GFSK_COEFF_6_7;                    /**< GFSK_COEFF_6_7, offset: 0x24 */
  __IO uint32_t IMAGE_FILTER_CTRL;                 /**< IMAGE_FILTER_CTRL, offset: 0x28 */
  __IO uint32_t PA_CTRL;                           /**< PA_CTRL, offset: 0x2C */
  __IO uint32_t PA_RAMP_TBL0;                      /**< PA_RAMP_TBL0, offset: 0x30 */
  __IO uint32_t PA_RAMP_TBL1;                      /**< PA_RAMP_TBL1, offset: 0x34 */
  __IO uint32_t PA_RAMP_TBL2;                      /**< PA_RAMP_TBL2, offset: 0x38 */
  __IO uint32_t PA_RAMP_TBL3;                      /**< PA_RAMP_TBL3, offset: 0x3C */
  __IO uint32_t SWITCH_TX_CTRL;                    /**< SWITCH_TX_CTRL, offset: 0x40 */
  __IO uint32_t RF_DFT_TX_CTRL0;                   /**< RF_DFT_TX_CTRL0, offset: 0x44 */
  __IO uint32_t RF_DFT_TX_CTRL1;                   /**< RF_DFT_TX_CTRL1, offset: 0x48 */
  __IO uint32_t RF_DFT_TX_CTRL2;                   /**< RF_DFT_TX_CTRL2, offset: 0x4C */
  __IO uint32_t RF_DFT_PATTERN;                    /**< RF_DFT_PATTERN, offset: 0x50 */
  __IO uint32_t DATARATE_CONFIG_FSK_CTRL;          /**< DATARATE_CONFIG_FSK_CTRL, offset: 0x54 */
  __IO uint32_t DATARATE_CONFIG_GFSK_CTRL;         /**< DATARATE_CONFIG_GFSK_CTRL, offset: 0x58 */
  __IO uint32_t DATARATE_CONFIG_FILTER_CTRL;       /**< DATARATE_CONFIG_FILTER_CTRL, offset: 0x5C */
} XCVR_TX_DIG_Type;

/* ----------------------------------------------------------------------------
   -- XCVR_TX_DIG Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup XCVR_TX_DIG_Register_Masks XCVR_TX_DIG Register Masks
 * @{
 */

/*! @name TXDIG_CTRL - TXDIG_CTRL */
/*! @{ */

#define XCVR_TX_DIG_TXDIG_CTRL_MODULATOR_SEL_MASK (0x1U)
#define XCVR_TX_DIG_TXDIG_CTRL_MODULATOR_SEL_SHIFT (0U)
/*! MODULATOR_SEL - MODULATOR_SEL
 */
#define XCVR_TX_DIG_TXDIG_CTRL_MODULATOR_SEL(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_TXDIG_CTRL_MODULATOR_SEL_SHIFT)) & XCVR_TX_DIG_TXDIG_CTRL_MODULATOR_SEL_MASK)

#define XCVR_TX_DIG_TXDIG_CTRL_PFC_EN_MASK       (0x2U)
#define XCVR_TX_DIG_TXDIG_CTRL_PFC_EN_SHIFT      (1U)
/*! PFC_EN - PFC_EN
 */
#define XCVR_TX_DIG_TXDIG_CTRL_PFC_EN(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_TXDIG_CTRL_PFC_EN_SHIFT)) & XCVR_TX_DIG_TXDIG_CTRL_PFC_EN_MASK)

#define XCVR_TX_DIG_TXDIG_CTRL_DATA_STREAM_SEL_MASK (0x4U)
#define XCVR_TX_DIG_TXDIG_CTRL_DATA_STREAM_SEL_SHIFT (2U)
/*! DATA_STREAM_SEL - DATA_STREAM_SEL
 */
#define XCVR_TX_DIG_TXDIG_CTRL_DATA_STREAM_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_TXDIG_CTRL_DATA_STREAM_SEL_SHIFT)) & XCVR_TX_DIG_TXDIG_CTRL_DATA_STREAM_SEL_MASK)

#define XCVR_TX_DIG_TXDIG_CTRL_INV_DATA_OUT_MASK (0x10U)
#define XCVR_TX_DIG_TXDIG_CTRL_INV_DATA_OUT_SHIFT (4U)
/*! INV_DATA_OUT - INV_DATA_OUT
 */
#define XCVR_TX_DIG_TXDIG_CTRL_INV_DATA_OUT(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_TXDIG_CTRL_INV_DATA_OUT_SHIFT)) & XCVR_TX_DIG_TXDIG_CTRL_INV_DATA_OUT_MASK)
/*! @} */

/*! @name DATA_PADDING_CTRL - DATA_PADDING_CTRL */
/*! @{ */

#define XCVR_TX_DIG_DATA_PADDING_CTRL_DATA_PADDING_SEL_MASK (0x3U)
#define XCVR_TX_DIG_DATA_PADDING_CTRL_DATA_PADDING_SEL_SHIFT (0U)
/*! DATA_PADDING_SEL - DATA_PADDING_SEL
 */
#define XCVR_TX_DIG_DATA_PADDING_CTRL_DATA_PADDING_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATA_PADDING_CTRL_DATA_PADDING_SEL_SHIFT)) & XCVR_TX_DIG_DATA_PADDING_CTRL_DATA_PADDING_SEL_MASK)

#define XCVR_TX_DIG_DATA_PADDING_CTRL_TX_CAPTURE_POL_MASK (0x4U)
#define XCVR_TX_DIG_DATA_PADDING_CTRL_TX_CAPTURE_POL_SHIFT (2U)
/*! TX_CAPTURE_POL - TX_CAPTURE_POL
 */
#define XCVR_TX_DIG_DATA_PADDING_CTRL_TX_CAPTURE_POL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATA_PADDING_CTRL_TX_CAPTURE_POL_SHIFT)) & XCVR_TX_DIG_DATA_PADDING_CTRL_TX_CAPTURE_POL_MASK)

#define XCVR_TX_DIG_DATA_PADDING_CTRL_CTE_DATA_MASK (0x10U)
#define XCVR_TX_DIG_DATA_PADDING_CTRL_CTE_DATA_SHIFT (4U)
/*! CTE_DATA - CTE_DATA
 */
#define XCVR_TX_DIG_DATA_PADDING_CTRL_CTE_DATA(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATA_PADDING_CTRL_CTE_DATA_SHIFT)) & XCVR_TX_DIG_DATA_PADDING_CTRL_CTE_DATA_MASK)

#define XCVR_TX_DIG_DATA_PADDING_CTRL_PAD_DLY_MASK (0xF00U)
#define XCVR_TX_DIG_DATA_PADDING_CTRL_PAD_DLY_SHIFT (8U)
/*! PAD_DLY - PAD_DLY
 */
#define XCVR_TX_DIG_DATA_PADDING_CTRL_PAD_DLY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATA_PADDING_CTRL_PAD_DLY_SHIFT)) & XCVR_TX_DIG_DATA_PADDING_CTRL_PAD_DLY_MASK)

#define XCVR_TX_DIG_DATA_PADDING_CTRL_PAD_DLY_EN_MASK (0x1000U)
#define XCVR_TX_DIG_DATA_PADDING_CTRL_PAD_DLY_EN_SHIFT (12U)
/*! PAD_DLY_EN - PAD_DLY_EN
 */
#define XCVR_TX_DIG_DATA_PADDING_CTRL_PAD_DLY_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATA_PADDING_CTRL_PAD_DLY_EN_SHIFT)) & XCVR_TX_DIG_DATA_PADDING_CTRL_PAD_DLY_EN_MASK)

#define XCVR_TX_DIG_DATA_PADDING_CTRL_RAMP_DN_PAD_EN_MASK (0x10000U)
#define XCVR_TX_DIG_DATA_PADDING_CTRL_RAMP_DN_PAD_EN_SHIFT (16U)
/*! RAMP_DN_PAD_EN - RAMP_DN_PAD_EN
 */
#define XCVR_TX_DIG_DATA_PADDING_CTRL_RAMP_DN_PAD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATA_PADDING_CTRL_RAMP_DN_PAD_EN_SHIFT)) & XCVR_TX_DIG_DATA_PADDING_CTRL_RAMP_DN_PAD_EN_MASK)
/*! @} */

/*! @name DATA_PADDING_CTRL_1 - DATA_PADDING_CTRL_1 */
/*! @{ */

#define XCVR_TX_DIG_DATA_PADDING_CTRL_1_RAMP_UP_DLY_MASK (0x1FU)
#define XCVR_TX_DIG_DATA_PADDING_CTRL_1_RAMP_UP_DLY_SHIFT (0U)
/*! RAMP_UP_DLY - RAMP_UP_DLY
 */
#define XCVR_TX_DIG_DATA_PADDING_CTRL_1_RAMP_UP_DLY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATA_PADDING_CTRL_1_RAMP_UP_DLY_SHIFT)) & XCVR_TX_DIG_DATA_PADDING_CTRL_1_RAMP_UP_DLY_MASK)

#define XCVR_TX_DIG_DATA_PADDING_CTRL_1_TX_DATA_FLUSH_DLY_MASK (0x700U)
#define XCVR_TX_DIG_DATA_PADDING_CTRL_1_TX_DATA_FLUSH_DLY_SHIFT (8U)
/*! TX_DATA_FLUSH_DLY - TX_DATA_FLUSH_DLY
 */
#define XCVR_TX_DIG_DATA_PADDING_CTRL_1_TX_DATA_FLUSH_DLY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATA_PADDING_CTRL_1_TX_DATA_FLUSH_DLY_SHIFT)) & XCVR_TX_DIG_DATA_PADDING_CTRL_1_TX_DATA_FLUSH_DLY_MASK)

#define XCVR_TX_DIG_DATA_PADDING_CTRL_1_PA_PUP_ADJ_MASK (0xF000U)
#define XCVR_TX_DIG_DATA_PADDING_CTRL_1_PA_PUP_ADJ_SHIFT (12U)
/*! PA_PUP_ADJ - PA_PUP_ADJ
 */
#define XCVR_TX_DIG_DATA_PADDING_CTRL_1_PA_PUP_ADJ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATA_PADDING_CTRL_1_PA_PUP_ADJ_SHIFT)) & XCVR_TX_DIG_DATA_PADDING_CTRL_1_PA_PUP_ADJ_MASK)
/*! @} */

/*! @name DATA_PADDING_CTRL_2 - DATA_PADDING_CTRL_2 */
/*! @{ */

#define XCVR_TX_DIG_DATA_PADDING_CTRL_2_DATA_PAD_MFDEV_MASK (0x1FFFU)
#define XCVR_TX_DIG_DATA_PADDING_CTRL_2_DATA_PAD_MFDEV_SHIFT (0U)
/*! DATA_PAD_MFDEV - DATA_PAD_MFDEV
 */
#define XCVR_TX_DIG_DATA_PADDING_CTRL_2_DATA_PAD_MFDEV(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATA_PADDING_CTRL_2_DATA_PAD_MFDEV_SHIFT)) & XCVR_TX_DIG_DATA_PADDING_CTRL_2_DATA_PAD_MFDEV_MASK)

#define XCVR_TX_DIG_DATA_PADDING_CTRL_2_DATA_PAD_PFDEV_MASK (0x1FFF0000U)
#define XCVR_TX_DIG_DATA_PADDING_CTRL_2_DATA_PAD_PFDEV_SHIFT (16U)
/*! DATA_PAD_PFDEV - DATA_PAD_PFDEV
 */
#define XCVR_TX_DIG_DATA_PADDING_CTRL_2_DATA_PAD_PFDEV(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATA_PADDING_CTRL_2_DATA_PAD_PFDEV_SHIFT)) & XCVR_TX_DIG_DATA_PADDING_CTRL_2_DATA_PAD_PFDEV_MASK)
/*! @} */

/*! @name FSK_CTRL - FSK_CTRL */
/*! @{ */

#define XCVR_TX_DIG_FSK_CTRL_FSK_FDEV_0_MASK     (0x1FFFU)
#define XCVR_TX_DIG_FSK_CTRL_FSK_FDEV_0_SHIFT    (0U)
/*! FSK_FDEV_0 - FSK_FDEV_0
 */
#define XCVR_TX_DIG_FSK_CTRL_FSK_FDEV_0(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_FSK_CTRL_FSK_FDEV_0_SHIFT)) & XCVR_TX_DIG_FSK_CTRL_FSK_FDEV_0_MASK)

#define XCVR_TX_DIG_FSK_CTRL_FSK_FDEV_1_MASK     (0x1FFF0000U)
#define XCVR_TX_DIG_FSK_CTRL_FSK_FDEV_1_SHIFT    (16U)
/*! FSK_FDEV_1 - FSK_FDEV_1
 */
#define XCVR_TX_DIG_FSK_CTRL_FSK_FDEV_1(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_FSK_CTRL_FSK_FDEV_1_SHIFT)) & XCVR_TX_DIG_FSK_CTRL_FSK_FDEV_1_MASK)
/*! @} */

/*! @name GFSK_CTRL - GFSK_CTRL */
/*! @{ */

#define XCVR_TX_DIG_GFSK_CTRL_GFSK_FDEV_MASK     (0xFFFU)
#define XCVR_TX_DIG_GFSK_CTRL_GFSK_FDEV_SHIFT    (0U)
/*! GFSK_FDEV - GFSK_FDEV
 */
#define XCVR_TX_DIG_GFSK_CTRL_GFSK_FDEV(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_CTRL_GFSK_FDEV_SHIFT)) & XCVR_TX_DIG_GFSK_CTRL_GFSK_FDEV_MASK)

#define XCVR_TX_DIG_GFSK_CTRL_GFSK_COEFF_MAN_MASK (0x1000U)
#define XCVR_TX_DIG_GFSK_CTRL_GFSK_COEFF_MAN_SHIFT (12U)
/*! GFSK_COEFF_MAN - GFSK_COEFF_MAN
 */
#define XCVR_TX_DIG_GFSK_CTRL_GFSK_COEFF_MAN(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_CTRL_GFSK_COEFF_MAN_SHIFT)) & XCVR_TX_DIG_GFSK_CTRL_GFSK_COEFF_MAN_MASK)

#define XCVR_TX_DIG_GFSK_CTRL_BT_EQ_OR_GTR_ONE_MASK (0x10000U)
#define XCVR_TX_DIG_GFSK_CTRL_BT_EQ_OR_GTR_ONE_SHIFT (16U)
/*! BT_EQ_OR_GTR_ONE - BT_EQ_OR_GTR_ONE
 */
#define XCVR_TX_DIG_GFSK_CTRL_BT_EQ_OR_GTR_ONE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_CTRL_BT_EQ_OR_GTR_ONE_SHIFT)) & XCVR_TX_DIG_GFSK_CTRL_BT_EQ_OR_GTR_ONE_MASK)
/*! @} */

/*! @name GFSK_COEFF_0_1 - GFSK_COEFF_0_1 */
/*! @{ */

#define XCVR_TX_DIG_GFSK_COEFF_0_1_GFSK_COEFF_0_MASK (0x1FFU)
#define XCVR_TX_DIG_GFSK_COEFF_0_1_GFSK_COEFF_0_SHIFT (0U)
/*! GFSK_COEFF_0 - GFSK_COEFF_0
 */
#define XCVR_TX_DIG_GFSK_COEFF_0_1_GFSK_COEFF_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_COEFF_0_1_GFSK_COEFF_0_SHIFT)) & XCVR_TX_DIG_GFSK_COEFF_0_1_GFSK_COEFF_0_MASK)

#define XCVR_TX_DIG_GFSK_COEFF_0_1_GFSK_COEFF_1_MASK (0x1FF0000U)
#define XCVR_TX_DIG_GFSK_COEFF_0_1_GFSK_COEFF_1_SHIFT (16U)
/*! GFSK_COEFF_1 - GFSK_COEFF_1
 */
#define XCVR_TX_DIG_GFSK_COEFF_0_1_GFSK_COEFF_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_COEFF_0_1_GFSK_COEFF_1_SHIFT)) & XCVR_TX_DIG_GFSK_COEFF_0_1_GFSK_COEFF_1_MASK)
/*! @} */

/*! @name GFSK_COEFF_2_3 - GFSK_COEFF_2_3 */
/*! @{ */

#define XCVR_TX_DIG_GFSK_COEFF_2_3_GFSK_COEFF_2_MASK (0x1FFU)
#define XCVR_TX_DIG_GFSK_COEFF_2_3_GFSK_COEFF_2_SHIFT (0U)
/*! GFSK_COEFF_2 - GFSK_COEFF_2
 */
#define XCVR_TX_DIG_GFSK_COEFF_2_3_GFSK_COEFF_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_COEFF_2_3_GFSK_COEFF_2_SHIFT)) & XCVR_TX_DIG_GFSK_COEFF_2_3_GFSK_COEFF_2_MASK)

#define XCVR_TX_DIG_GFSK_COEFF_2_3_GFSK_COEFF_3_MASK (0x1FF0000U)
#define XCVR_TX_DIG_GFSK_COEFF_2_3_GFSK_COEFF_3_SHIFT (16U)
/*! GFSK_COEFF_3 - GFSK_COEFF_3
 */
#define XCVR_TX_DIG_GFSK_COEFF_2_3_GFSK_COEFF_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_COEFF_2_3_GFSK_COEFF_3_SHIFT)) & XCVR_TX_DIG_GFSK_COEFF_2_3_GFSK_COEFF_3_MASK)
/*! @} */

/*! @name GFSK_COEFF_4_5 - GFSK_COEFF_4_5 */
/*! @{ */

#define XCVR_TX_DIG_GFSK_COEFF_4_5_GFSK_COEFF_4_MASK (0x1FFU)
#define XCVR_TX_DIG_GFSK_COEFF_4_5_GFSK_COEFF_4_SHIFT (0U)
/*! GFSK_COEFF_4 - GFSK_COEFF_4
 */
#define XCVR_TX_DIG_GFSK_COEFF_4_5_GFSK_COEFF_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_COEFF_4_5_GFSK_COEFF_4_SHIFT)) & XCVR_TX_DIG_GFSK_COEFF_4_5_GFSK_COEFF_4_MASK)

#define XCVR_TX_DIG_GFSK_COEFF_4_5_GFSK_COEFF_5_MASK (0x1FF0000U)
#define XCVR_TX_DIG_GFSK_COEFF_4_5_GFSK_COEFF_5_SHIFT (16U)
/*! GFSK_COEFF_5 - GFSK_COEFF_5
 */
#define XCVR_TX_DIG_GFSK_COEFF_4_5_GFSK_COEFF_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_COEFF_4_5_GFSK_COEFF_5_SHIFT)) & XCVR_TX_DIG_GFSK_COEFF_4_5_GFSK_COEFF_5_MASK)
/*! @} */

/*! @name GFSK_COEFF_6_7 - GFSK_COEFF_6_7 */
/*! @{ */

#define XCVR_TX_DIG_GFSK_COEFF_6_7_GFSK_COEFF_6_MASK (0x1FFU)
#define XCVR_TX_DIG_GFSK_COEFF_6_7_GFSK_COEFF_6_SHIFT (0U)
/*! GFSK_COEFF_6 - GFSK_COEFF_6
 */
#define XCVR_TX_DIG_GFSK_COEFF_6_7_GFSK_COEFF_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_COEFF_6_7_GFSK_COEFF_6_SHIFT)) & XCVR_TX_DIG_GFSK_COEFF_6_7_GFSK_COEFF_6_MASK)

#define XCVR_TX_DIG_GFSK_COEFF_6_7_GFSK_COEFF_7_MASK (0x1FF0000U)
#define XCVR_TX_DIG_GFSK_COEFF_6_7_GFSK_COEFF_7_SHIFT (16U)
/*! GFSK_COEFF_7 - GFSK_COEFF_7
 */
#define XCVR_TX_DIG_GFSK_COEFF_6_7_GFSK_COEFF_7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_COEFF_6_7_GFSK_COEFF_7_SHIFT)) & XCVR_TX_DIG_GFSK_COEFF_6_7_GFSK_COEFF_7_MASK)
/*! @} */

/*! @name IMAGE_FILTER_CTRL - IMAGE_FILTER_CTRL */
/*! @{ */

#define XCVR_TX_DIG_IMAGE_FILTER_CTRL_IMAGE_FIR_FILTER_SEL_MASK (0x3U)
#define XCVR_TX_DIG_IMAGE_FILTER_CTRL_IMAGE_FIR_FILTER_SEL_SHIFT (0U)
/*! IMAGE_FIR_FILTER_SEL - IMAGE_FIR_FILTER_SEL
 */
#define XCVR_TX_DIG_IMAGE_FILTER_CTRL_IMAGE_FIR_FILTER_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_IMAGE_FILTER_CTRL_IMAGE_FIR_FILTER_SEL_SHIFT)) & XCVR_TX_DIG_IMAGE_FILTER_CTRL_IMAGE_FIR_FILTER_SEL_MASK)

#define XCVR_TX_DIG_IMAGE_FILTER_CTRL_IMAGE_FILTER_OVRD_EN_MASK (0x4U)
#define XCVR_TX_DIG_IMAGE_FILTER_CTRL_IMAGE_FILTER_OVRD_EN_SHIFT (2U)
/*! IMAGE_FILTER_OVRD_EN - IMAGE_FILTER_OVRD_EN
 */
#define XCVR_TX_DIG_IMAGE_FILTER_CTRL_IMAGE_FILTER_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_IMAGE_FILTER_CTRL_IMAGE_FILTER_OVRD_EN_SHIFT)) & XCVR_TX_DIG_IMAGE_FILTER_CTRL_IMAGE_FILTER_OVRD_EN_MASK)

#define XCVR_TX_DIG_IMAGE_FILTER_CTRL_IMAGE_FIR_FILTER_OVRD_MASK (0x8U)
#define XCVR_TX_DIG_IMAGE_FILTER_CTRL_IMAGE_FIR_FILTER_OVRD_SHIFT (3U)
/*! IMAGE_FIR_FILTER_OVRD - IMAGE_FIR_FILTER_OVRD
 */
#define XCVR_TX_DIG_IMAGE_FILTER_CTRL_IMAGE_FIR_FILTER_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_IMAGE_FILTER_CTRL_IMAGE_FIR_FILTER_OVRD_SHIFT)) & XCVR_TX_DIG_IMAGE_FILTER_CTRL_IMAGE_FIR_FILTER_OVRD_MASK)

#define XCVR_TX_DIG_IMAGE_FILTER_CTRL_IMAGE_SYNC1_FILTER_OVRD_MASK (0x10U)
#define XCVR_TX_DIG_IMAGE_FILTER_CTRL_IMAGE_SYNC1_FILTER_OVRD_SHIFT (4U)
/*! IMAGE_SYNC1_FILTER_OVRD - IMAGE_SYNC1_FILTER_OVRD
 */
#define XCVR_TX_DIG_IMAGE_FILTER_CTRL_IMAGE_SYNC1_FILTER_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_IMAGE_FILTER_CTRL_IMAGE_SYNC1_FILTER_OVRD_SHIFT)) & XCVR_TX_DIG_IMAGE_FILTER_CTRL_IMAGE_SYNC1_FILTER_OVRD_MASK)

#define XCVR_TX_DIG_IMAGE_FILTER_CTRL_IMAGE_SYNC0_FILTER_OVRD_MASK (0x20U)
#define XCVR_TX_DIG_IMAGE_FILTER_CTRL_IMAGE_SYNC0_FILTER_OVRD_SHIFT (5U)
/*! IMAGE_SYNC0_FILTER_OVRD - IMAGE_SYNC0_FILTER_OVRD
 */
#define XCVR_TX_DIG_IMAGE_FILTER_CTRL_IMAGE_SYNC0_FILTER_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_IMAGE_FILTER_CTRL_IMAGE_SYNC0_FILTER_OVRD_SHIFT)) & XCVR_TX_DIG_IMAGE_FILTER_CTRL_IMAGE_SYNC0_FILTER_OVRD_MASK)

#define XCVR_TX_DIG_IMAGE_FILTER_CTRL_FREQ_WORD_ADJ_MASK (0x3FF0000U)
#define XCVR_TX_DIG_IMAGE_FILTER_CTRL_FREQ_WORD_ADJ_SHIFT (16U)
/*! FREQ_WORD_ADJ - FREQ_WORD_ADJ
 */
#define XCVR_TX_DIG_IMAGE_FILTER_CTRL_FREQ_WORD_ADJ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_IMAGE_FILTER_CTRL_FREQ_WORD_ADJ_SHIFT)) & XCVR_TX_DIG_IMAGE_FILTER_CTRL_FREQ_WORD_ADJ_MASK)
/*! @} */

/*! @name PA_CTRL - PA_CTRL */
/*! @{ */

#define XCVR_TX_DIG_PA_CTRL_PA_TGT_POWER_MASK    (0x3FU)
#define XCVR_TX_DIG_PA_CTRL_PA_TGT_POWER_SHIFT   (0U)
/*! PA_TGT_POWER - PA_TGT_POWER
 */
#define XCVR_TX_DIG_PA_CTRL_PA_TGT_POWER(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_PA_CTRL_PA_TGT_POWER_SHIFT)) & XCVR_TX_DIG_PA_CTRL_PA_TGT_POWER_MASK)

#define XCVR_TX_DIG_PA_CTRL_TGT_PWR_SRC_MASK     (0x100U)
#define XCVR_TX_DIG_PA_CTRL_TGT_PWR_SRC_SHIFT    (8U)
/*! TGT_PWR_SRC - TGT_PWR_SRC
 */
#define XCVR_TX_DIG_PA_CTRL_TGT_PWR_SRC(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_PA_CTRL_TGT_PWR_SRC_SHIFT)) & XCVR_TX_DIG_PA_CTRL_TGT_PWR_SRC_MASK)

#define XCVR_TX_DIG_PA_CTRL_EARLY_WU_COMPLETE_MASK (0x1000U)
#define XCVR_TX_DIG_PA_CTRL_EARLY_WU_COMPLETE_SHIFT (12U)
/*! EARLY_WU_COMPLETE - EARLY_WU_COMPLETE
 */
#define XCVR_TX_DIG_PA_CTRL_EARLY_WU_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_PA_CTRL_EARLY_WU_COMPLETE_SHIFT)) & XCVR_TX_DIG_PA_CTRL_EARLY_WU_COMPLETE_MASK)

#define XCVR_TX_DIG_PA_CTRL_RAMP_CS_MASK         (0xE000U)
#define XCVR_TX_DIG_PA_CTRL_RAMP_CS_SHIFT        (13U)
/*! RAMP_CS - RAMP_CS
 */
#define XCVR_TX_DIG_PA_CTRL_RAMP_CS(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_PA_CTRL_RAMP_CS_SHIFT)) & XCVR_TX_DIG_PA_CTRL_RAMP_CS_MASK)

#define XCVR_TX_DIG_PA_CTRL_PA_RAMP_SEL_MASK     (0x30000U)
#define XCVR_TX_DIG_PA_CTRL_PA_RAMP_SEL_SHIFT    (16U)
/*! PA_RAMP_SEL - PA_RAMP_SEL
 */
#define XCVR_TX_DIG_PA_CTRL_PA_RAMP_SEL(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_PA_CTRL_PA_RAMP_SEL_SHIFT)) & XCVR_TX_DIG_PA_CTRL_PA_RAMP_SEL_MASK)

#define XCVR_TX_DIG_PA_CTRL_TX_PA_PUP_OVRD_MASK  (0x40000000U)
#define XCVR_TX_DIG_PA_CTRL_TX_PA_PUP_OVRD_SHIFT (30U)
/*! TX_PA_PUP_OVRD - TX_PA_PUP_OVRD
 */
#define XCVR_TX_DIG_PA_CTRL_TX_PA_PUP_OVRD(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_PA_CTRL_TX_PA_PUP_OVRD_SHIFT)) & XCVR_TX_DIG_PA_CTRL_TX_PA_PUP_OVRD_MASK)

#define XCVR_TX_DIG_PA_CTRL_TX_PA_PUP_OVRD_EN_MASK (0x80000000U)
#define XCVR_TX_DIG_PA_CTRL_TX_PA_PUP_OVRD_EN_SHIFT (31U)
/*! TX_PA_PUP_OVRD_EN - TX_PA_PUP_OVRD_EN
 */
#define XCVR_TX_DIG_PA_CTRL_TX_PA_PUP_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_PA_CTRL_TX_PA_PUP_OVRD_EN_SHIFT)) & XCVR_TX_DIG_PA_CTRL_TX_PA_PUP_OVRD_EN_MASK)
/*! @} */

/*! @name PA_RAMP_TBL0 - PA_RAMP_TBL0 */
/*! @{ */

#define XCVR_TX_DIG_PA_RAMP_TBL0_PA_RAMP0_MASK   (0x3FU)
#define XCVR_TX_DIG_PA_RAMP_TBL0_PA_RAMP0_SHIFT  (0U)
/*! PA_RAMP0 - PA_RAMP0
 */
#define XCVR_TX_DIG_PA_RAMP_TBL0_PA_RAMP0(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_PA_RAMP_TBL0_PA_RAMP0_SHIFT)) & XCVR_TX_DIG_PA_RAMP_TBL0_PA_RAMP0_MASK)

#define XCVR_TX_DIG_PA_RAMP_TBL0_PA_RAMP1_MASK   (0x3F00U)
#define XCVR_TX_DIG_PA_RAMP_TBL0_PA_RAMP1_SHIFT  (8U)
/*! PA_RAMP1 - PA_RAMP1
 */
#define XCVR_TX_DIG_PA_RAMP_TBL0_PA_RAMP1(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_PA_RAMP_TBL0_PA_RAMP1_SHIFT)) & XCVR_TX_DIG_PA_RAMP_TBL0_PA_RAMP1_MASK)

#define XCVR_TX_DIG_PA_RAMP_TBL0_PA_RAMP2_MASK   (0x3F0000U)
#define XCVR_TX_DIG_PA_RAMP_TBL0_PA_RAMP2_SHIFT  (16U)
/*! PA_RAMP2 - PA_RAMP2
 */
#define XCVR_TX_DIG_PA_RAMP_TBL0_PA_RAMP2(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_PA_RAMP_TBL0_PA_RAMP2_SHIFT)) & XCVR_TX_DIG_PA_RAMP_TBL0_PA_RAMP2_MASK)

#define XCVR_TX_DIG_PA_RAMP_TBL0_PA_RAMP3_MASK   (0x3F000000U)
#define XCVR_TX_DIG_PA_RAMP_TBL0_PA_RAMP3_SHIFT  (24U)
/*! PA_RAMP3 - PA_RAMP3
 */
#define XCVR_TX_DIG_PA_RAMP_TBL0_PA_RAMP3(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_PA_RAMP_TBL0_PA_RAMP3_SHIFT)) & XCVR_TX_DIG_PA_RAMP_TBL0_PA_RAMP3_MASK)
/*! @} */

/*! @name PA_RAMP_TBL1 - PA_RAMP_TBL1 */
/*! @{ */

#define XCVR_TX_DIG_PA_RAMP_TBL1_PA_RAMP4_MASK   (0x3FU)
#define XCVR_TX_DIG_PA_RAMP_TBL1_PA_RAMP4_SHIFT  (0U)
/*! PA_RAMP4 - PA_RAMP4
 */
#define XCVR_TX_DIG_PA_RAMP_TBL1_PA_RAMP4(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_PA_RAMP_TBL1_PA_RAMP4_SHIFT)) & XCVR_TX_DIG_PA_RAMP_TBL1_PA_RAMP4_MASK)

#define XCVR_TX_DIG_PA_RAMP_TBL1_PA_RAMP5_MASK   (0x3F00U)
#define XCVR_TX_DIG_PA_RAMP_TBL1_PA_RAMP5_SHIFT  (8U)
/*! PA_RAMP5 - PA_RAMP5
 */
#define XCVR_TX_DIG_PA_RAMP_TBL1_PA_RAMP5(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_PA_RAMP_TBL1_PA_RAMP5_SHIFT)) & XCVR_TX_DIG_PA_RAMP_TBL1_PA_RAMP5_MASK)

#define XCVR_TX_DIG_PA_RAMP_TBL1_PA_RAMP6_MASK   (0x3F0000U)
#define XCVR_TX_DIG_PA_RAMP_TBL1_PA_RAMP6_SHIFT  (16U)
/*! PA_RAMP6 - PA_RAMP6
 */
#define XCVR_TX_DIG_PA_RAMP_TBL1_PA_RAMP6(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_PA_RAMP_TBL1_PA_RAMP6_SHIFT)) & XCVR_TX_DIG_PA_RAMP_TBL1_PA_RAMP6_MASK)

#define XCVR_TX_DIG_PA_RAMP_TBL1_PA_RAMP7_MASK   (0x3F000000U)
#define XCVR_TX_DIG_PA_RAMP_TBL1_PA_RAMP7_SHIFT  (24U)
/*! PA_RAMP7 - PA_RAMP7
 */
#define XCVR_TX_DIG_PA_RAMP_TBL1_PA_RAMP7(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_PA_RAMP_TBL1_PA_RAMP7_SHIFT)) & XCVR_TX_DIG_PA_RAMP_TBL1_PA_RAMP7_MASK)
/*! @} */

/*! @name PA_RAMP_TBL2 - PA_RAMP_TBL2 */
/*! @{ */

#define XCVR_TX_DIG_PA_RAMP_TBL2_PA_RAMP8_MASK   (0x3FU)
#define XCVR_TX_DIG_PA_RAMP_TBL2_PA_RAMP8_SHIFT  (0U)
/*! PA_RAMP8 - PA_RAMP8
 */
#define XCVR_TX_DIG_PA_RAMP_TBL2_PA_RAMP8(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_PA_RAMP_TBL2_PA_RAMP8_SHIFT)) & XCVR_TX_DIG_PA_RAMP_TBL2_PA_RAMP8_MASK)

#define XCVR_TX_DIG_PA_RAMP_TBL2_PA_RAMP9_MASK   (0x3F00U)
#define XCVR_TX_DIG_PA_RAMP_TBL2_PA_RAMP9_SHIFT  (8U)
/*! PA_RAMP9 - PA_RAMP9
 */
#define XCVR_TX_DIG_PA_RAMP_TBL2_PA_RAMP9(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_PA_RAMP_TBL2_PA_RAMP9_SHIFT)) & XCVR_TX_DIG_PA_RAMP_TBL2_PA_RAMP9_MASK)

#define XCVR_TX_DIG_PA_RAMP_TBL2_PA_RAMP10_MASK  (0x3F0000U)
#define XCVR_TX_DIG_PA_RAMP_TBL2_PA_RAMP10_SHIFT (16U)
/*! PA_RAMP10 - PA_RAMP10
 */
#define XCVR_TX_DIG_PA_RAMP_TBL2_PA_RAMP10(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_PA_RAMP_TBL2_PA_RAMP10_SHIFT)) & XCVR_TX_DIG_PA_RAMP_TBL2_PA_RAMP10_MASK)

#define XCVR_TX_DIG_PA_RAMP_TBL2_PA_RAMP11_MASK  (0x3F000000U)
#define XCVR_TX_DIG_PA_RAMP_TBL2_PA_RAMP11_SHIFT (24U)
/*! PA_RAMP11 - PA_RAMP11
 */
#define XCVR_TX_DIG_PA_RAMP_TBL2_PA_RAMP11(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_PA_RAMP_TBL2_PA_RAMP11_SHIFT)) & XCVR_TX_DIG_PA_RAMP_TBL2_PA_RAMP11_MASK)
/*! @} */

/*! @name PA_RAMP_TBL3 - PA_RAMP_TBL3 */
/*! @{ */

#define XCVR_TX_DIG_PA_RAMP_TBL3_PA_RAMP12_MASK  (0x3FU)
#define XCVR_TX_DIG_PA_RAMP_TBL3_PA_RAMP12_SHIFT (0U)
/*! PA_RAMP12 - PA_RAMP12
 */
#define XCVR_TX_DIG_PA_RAMP_TBL3_PA_RAMP12(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_PA_RAMP_TBL3_PA_RAMP12_SHIFT)) & XCVR_TX_DIG_PA_RAMP_TBL3_PA_RAMP12_MASK)

#define XCVR_TX_DIG_PA_RAMP_TBL3_PA_RAMP13_MASK  (0x3F00U)
#define XCVR_TX_DIG_PA_RAMP_TBL3_PA_RAMP13_SHIFT (8U)
/*! PA_RAMP13 - PA_RAMP13
 */
#define XCVR_TX_DIG_PA_RAMP_TBL3_PA_RAMP13(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_PA_RAMP_TBL3_PA_RAMP13_SHIFT)) & XCVR_TX_DIG_PA_RAMP_TBL3_PA_RAMP13_MASK)

#define XCVR_TX_DIG_PA_RAMP_TBL3_PA_RAMP14_MASK  (0x3F0000U)
#define XCVR_TX_DIG_PA_RAMP_TBL3_PA_RAMP14_SHIFT (16U)
/*! PA_RAMP14 - PA_RAMP14
 */
#define XCVR_TX_DIG_PA_RAMP_TBL3_PA_RAMP14(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_PA_RAMP_TBL3_PA_RAMP14_SHIFT)) & XCVR_TX_DIG_PA_RAMP_TBL3_PA_RAMP14_MASK)

#define XCVR_TX_DIG_PA_RAMP_TBL3_PA_RAMP15_MASK  (0x3F000000U)
#define XCVR_TX_DIG_PA_RAMP_TBL3_PA_RAMP15_SHIFT (24U)
/*! PA_RAMP15 - PA_RAMP15
 */
#define XCVR_TX_DIG_PA_RAMP_TBL3_PA_RAMP15(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_PA_RAMP_TBL3_PA_RAMP15_SHIFT)) & XCVR_TX_DIG_PA_RAMP_TBL3_PA_RAMP15_MASK)
/*! @} */

/*! @name SWITCH_TX_CTRL - SWITCH_TX_CTRL */
/*! @{ */

#define XCVR_TX_DIG_SWITCH_TX_CTRL_SWITCH_MOD_MASK (0x1U)
#define XCVR_TX_DIG_SWITCH_TX_CTRL_SWITCH_MOD_SHIFT (0U)
/*! SWITCH_MOD - SWITCH_MOD
 */
#define XCVR_TX_DIG_SWITCH_TX_CTRL_SWITCH_MOD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_SWITCH_TX_CTRL_SWITCH_MOD_SHIFT)) & XCVR_TX_DIG_SWITCH_TX_CTRL_SWITCH_MOD_MASK)

#define XCVR_TX_DIG_SWITCH_TX_CTRL_SWITCH_FIR_SEL_MASK (0x6U)
#define XCVR_TX_DIG_SWITCH_TX_CTRL_SWITCH_FIR_SEL_SHIFT (1U)
/*! SWITCH_FIR_SEL - SWITCH_FIR_SEL
 */
#define XCVR_TX_DIG_SWITCH_TX_CTRL_SWITCH_FIR_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_SWITCH_TX_CTRL_SWITCH_FIR_SEL_SHIFT)) & XCVR_TX_DIG_SWITCH_TX_CTRL_SWITCH_FIR_SEL_MASK)

#define XCVR_TX_DIG_SWITCH_TX_CTRL_SWITCH_GFSK_COEFF_MASK (0x8U)
#define XCVR_TX_DIG_SWITCH_TX_CTRL_SWITCH_GFSK_COEFF_SHIFT (3U)
/*! SWITCH_GFSK_COEFF - SWITCH_GFSK_COEFF
 */
#define XCVR_TX_DIG_SWITCH_TX_CTRL_SWITCH_GFSK_COEFF(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_SWITCH_TX_CTRL_SWITCH_GFSK_COEFF_SHIFT)) & XCVR_TX_DIG_SWITCH_TX_CTRL_SWITCH_GFSK_COEFF_MASK)

#define XCVR_TX_DIG_SWITCH_TX_CTRL_SWITCH_TGT_PWR_MASK (0x3F00U)
#define XCVR_TX_DIG_SWITCH_TX_CTRL_SWITCH_TGT_PWR_SHIFT (8U)
/*! SWITCH_TGT_PWR - SWITCH_TGT_PWR
 */
#define XCVR_TX_DIG_SWITCH_TX_CTRL_SWITCH_TGT_PWR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_SWITCH_TX_CTRL_SWITCH_TGT_PWR_SHIFT)) & XCVR_TX_DIG_SWITCH_TX_CTRL_SWITCH_TGT_PWR_MASK)
/*! @} */

/*! @name RF_DFT_TX_CTRL0 - RF_DFT_TX_CTRL0 */
/*! @{ */

#define XCVR_TX_DIG_RF_DFT_TX_CTRL0_DFT_MAX_RAM_SIZE_MASK (0x7FFFU)
#define XCVR_TX_DIG_RF_DFT_TX_CTRL0_DFT_MAX_RAM_SIZE_SHIFT (0U)
/*! DFT_MAX_RAM_SIZE - DFT_MAX_RAM_SIZE
 */
#define XCVR_TX_DIG_RF_DFT_TX_CTRL0_DFT_MAX_RAM_SIZE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_TX_CTRL0_DFT_MAX_RAM_SIZE_SHIFT)) & XCVR_TX_DIG_RF_DFT_TX_CTRL0_DFT_MAX_RAM_SIZE_MASK)

#define XCVR_TX_DIG_RF_DFT_TX_CTRL0_DFT_RAM_BASE_ADDR_MASK (0x7FFF0000U)
#define XCVR_TX_DIG_RF_DFT_TX_CTRL0_DFT_RAM_BASE_ADDR_SHIFT (16U)
/*! DFT_RAM_BASE_ADDR - DFT_RAM_BASE_ADDR
 */
#define XCVR_TX_DIG_RF_DFT_TX_CTRL0_DFT_RAM_BASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_TX_CTRL0_DFT_RAM_BASE_ADDR_SHIFT)) & XCVR_TX_DIG_RF_DFT_TX_CTRL0_DFT_RAM_BASE_ADDR_MASK)

#define XCVR_TX_DIG_RF_DFT_TX_CTRL0_DFT_RAM_EN_MASK (0x80000000U)
#define XCVR_TX_DIG_RF_DFT_TX_CTRL0_DFT_RAM_EN_SHIFT (31U)
/*! DFT_RAM_EN - DFT_RAM_EN
 */
#define XCVR_TX_DIG_RF_DFT_TX_CTRL0_DFT_RAM_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_TX_CTRL0_DFT_RAM_EN_SHIFT)) & XCVR_TX_DIG_RF_DFT_TX_CTRL0_DFT_RAM_EN_MASK)
/*! @} */

/*! @name RF_DFT_TX_CTRL1 - RF_DFT_TX_CTRL1 */
/*! @{ */

#define XCVR_TX_DIG_RF_DFT_TX_CTRL1_LFSR_OUT_MASK (0x1FFFFU)
#define XCVR_TX_DIG_RF_DFT_TX_CTRL1_LFSR_OUT_SHIFT (0U)
/*! LFSR_OUT - LFSR_OUT
 */
#define XCVR_TX_DIG_RF_DFT_TX_CTRL1_LFSR_OUT(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_TX_CTRL1_LFSR_OUT_SHIFT)) & XCVR_TX_DIG_RF_DFT_TX_CTRL1_LFSR_OUT_MASK)

#define XCVR_TX_DIG_RF_DFT_TX_CTRL1_LFSR_CLK_SEL_MASK (0x7000000U)
#define XCVR_TX_DIG_RF_DFT_TX_CTRL1_LFSR_CLK_SEL_SHIFT (24U)
/*! LFSR_CLK_SEL - LFSR_CLK_SEL
 */
#define XCVR_TX_DIG_RF_DFT_TX_CTRL1_LFSR_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_TX_CTRL1_LFSR_CLK_SEL_SHIFT)) & XCVR_TX_DIG_RF_DFT_TX_CTRL1_LFSR_CLK_SEL_MASK)

#define XCVR_TX_DIG_RF_DFT_TX_CTRL1_LFSR_LENGTH_MASK (0x38000000U)
#define XCVR_TX_DIG_RF_DFT_TX_CTRL1_LFSR_LENGTH_SHIFT (27U)
/*! LFSR_LENGTH - LFSR_LENGTH
 */
#define XCVR_TX_DIG_RF_DFT_TX_CTRL1_LFSR_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_TX_CTRL1_LFSR_LENGTH_SHIFT)) & XCVR_TX_DIG_RF_DFT_TX_CTRL1_LFSR_LENGTH_MASK)

#define XCVR_TX_DIG_RF_DFT_TX_CTRL1_LRM_MASK     (0x40000000U)
#define XCVR_TX_DIG_RF_DFT_TX_CTRL1_LRM_SHIFT    (30U)
/*! LRM - LRM
 */
#define XCVR_TX_DIG_RF_DFT_TX_CTRL1_LRM(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_TX_CTRL1_LRM_SHIFT)) & XCVR_TX_DIG_RF_DFT_TX_CTRL1_LRM_MASK)

#define XCVR_TX_DIG_RF_DFT_TX_CTRL1_LFSR_EN_MASK (0x80000000U)
#define XCVR_TX_DIG_RF_DFT_TX_CTRL1_LFSR_EN_SHIFT (31U)
/*! LFSR_EN - LFSR_EN
 */
#define XCVR_TX_DIG_RF_DFT_TX_CTRL1_LFSR_EN(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_TX_CTRL1_LFSR_EN_SHIFT)) & XCVR_TX_DIG_RF_DFT_TX_CTRL1_LFSR_EN_MASK)
/*! @} */

/*! @name RF_DFT_TX_CTRL2 - RF_DFT_TX_CTRL2 */
/*! @{ */

#define XCVR_TX_DIG_RF_DFT_TX_CTRL2_DFT_PA_AM_MOD_FREQ_MASK (0xFU)
#define XCVR_TX_DIG_RF_DFT_TX_CTRL2_DFT_PA_AM_MOD_FREQ_SHIFT (0U)
/*! DFT_PA_AM_MOD_FREQ - DFT_PA_AM_MOD_FREQ
 */
#define XCVR_TX_DIG_RF_DFT_TX_CTRL2_DFT_PA_AM_MOD_FREQ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_TX_CTRL2_DFT_PA_AM_MOD_FREQ_SHIFT)) & XCVR_TX_DIG_RF_DFT_TX_CTRL2_DFT_PA_AM_MOD_FREQ_MASK)

#define XCVR_TX_DIG_RF_DFT_TX_CTRL2_DFT_PA_AM_MOD_ENTRIES_MASK (0xF0U)
#define XCVR_TX_DIG_RF_DFT_TX_CTRL2_DFT_PA_AM_MOD_ENTRIES_SHIFT (4U)
/*! DFT_PA_AM_MOD_ENTRIES - DFT_PA_AM_MOD_ENTRIES
 */
#define XCVR_TX_DIG_RF_DFT_TX_CTRL2_DFT_PA_AM_MOD_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_TX_CTRL2_DFT_PA_AM_MOD_ENTRIES_SHIFT)) & XCVR_TX_DIG_RF_DFT_TX_CTRL2_DFT_PA_AM_MOD_ENTRIES_MASK)

#define XCVR_TX_DIG_RF_DFT_TX_CTRL2_DFT_PA_AM_MOD_EN_MASK (0x100U)
#define XCVR_TX_DIG_RF_DFT_TX_CTRL2_DFT_PA_AM_MOD_EN_SHIFT (8U)
/*! DFT_PA_AM_MOD_EN - DFT_PA_AM_MOD_EN
 */
#define XCVR_TX_DIG_RF_DFT_TX_CTRL2_DFT_PA_AM_MOD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_TX_CTRL2_DFT_PA_AM_MOD_EN_SHIFT)) & XCVR_TX_DIG_RF_DFT_TX_CTRL2_DFT_PA_AM_MOD_EN_MASK)

#define XCVR_TX_DIG_RF_DFT_TX_CTRL2_DFT_PATTERN_EN_MASK (0x80000000U)
#define XCVR_TX_DIG_RF_DFT_TX_CTRL2_DFT_PATTERN_EN_SHIFT (31U)
/*! DFT_PATTERN_EN - DFT_PATTERN_EN
 */
#define XCVR_TX_DIG_RF_DFT_TX_CTRL2_DFT_PATTERN_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_TX_CTRL2_DFT_PATTERN_EN_SHIFT)) & XCVR_TX_DIG_RF_DFT_TX_CTRL2_DFT_PATTERN_EN_MASK)
/*! @} */

/*! @name RF_DFT_PATTERN - RF_DFT_PATTERN */
/*! @{ */

#define XCVR_TX_DIG_RF_DFT_PATTERN_DFT_MOD_PATTERN_MASK (0xFFFFFFFFU)
#define XCVR_TX_DIG_RF_DFT_PATTERN_DFT_MOD_PATTERN_SHIFT (0U)
/*! DFT_MOD_PATTERN - DFT_MOD_PATTERN
 */
#define XCVR_TX_DIG_RF_DFT_PATTERN_DFT_MOD_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_PATTERN_DFT_MOD_PATTERN_SHIFT)) & XCVR_TX_DIG_RF_DFT_PATTERN_DFT_MOD_PATTERN_MASK)
/*! @} */

/*! @name DATARATE_CONFIG_FSK_CTRL - DATARATE_CONFIG_FSK_CTRL */
/*! @{ */

#define XCVR_TX_DIG_DATARATE_CONFIG_FSK_CTRL_DATARATE_CONFIG_FSK_FDEV0_MASK (0x1FFFU)
#define XCVR_TX_DIG_DATARATE_CONFIG_FSK_CTRL_DATARATE_CONFIG_FSK_FDEV0_SHIFT (0U)
/*! DATARATE_CONFIG_FSK_FDEV0 - DATARATE_CONFIG_DATA_PAD_MFDEV
 */
#define XCVR_TX_DIG_DATARATE_CONFIG_FSK_CTRL_DATARATE_CONFIG_FSK_FDEV0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATARATE_CONFIG_FSK_CTRL_DATARATE_CONFIG_FSK_FDEV0_SHIFT)) & XCVR_TX_DIG_DATARATE_CONFIG_FSK_CTRL_DATARATE_CONFIG_FSK_FDEV0_MASK)

#define XCVR_TX_DIG_DATARATE_CONFIG_FSK_CTRL_DATARATE_CONFIG_FSK_FDEV1_MASK (0x1FFF0000U)
#define XCVR_TX_DIG_DATARATE_CONFIG_FSK_CTRL_DATARATE_CONFIG_FSK_FDEV1_SHIFT (16U)
/*! DATARATE_CONFIG_FSK_FDEV1 - DATARATE_CONFIG_DATA_PAD_PFDEV
 */
#define XCVR_TX_DIG_DATARATE_CONFIG_FSK_CTRL_DATARATE_CONFIG_FSK_FDEV1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATARATE_CONFIG_FSK_CTRL_DATARATE_CONFIG_FSK_FDEV1_SHIFT)) & XCVR_TX_DIG_DATARATE_CONFIG_FSK_CTRL_DATARATE_CONFIG_FSK_FDEV1_MASK)
/*! @} */

/*! @name DATARATE_CONFIG_GFSK_CTRL - DATARATE_CONFIG_GFSK_CTRL */
/*! @{ */

#define XCVR_TX_DIG_DATARATE_CONFIG_GFSK_CTRL_DATARATE_CONFIG_GFSK_FDEV_MASK (0xFFFU)
#define XCVR_TX_DIG_DATARATE_CONFIG_GFSK_CTRL_DATARATE_CONFIG_GFSK_FDEV_SHIFT (0U)
/*! DATARATE_CONFIG_GFSK_FDEV - DATARATE_CONFIG_GFSK_FDEV
 */
#define XCVR_TX_DIG_DATARATE_CONFIG_GFSK_CTRL_DATARATE_CONFIG_GFSK_FDEV(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATARATE_CONFIG_GFSK_CTRL_DATARATE_CONFIG_GFSK_FDEV_SHIFT)) & XCVR_TX_DIG_DATARATE_CONFIG_GFSK_CTRL_DATARATE_CONFIG_GFSK_FDEV_MASK)
/*! @} */

/*! @name DATARATE_CONFIG_FILTER_CTRL - DATARATE_CONFIG_FILTER_CTRL */
/*! @{ */

#define XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_IMAGE_FILTER_OVRD_EN_MASK (0x1U)
#define XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_IMAGE_FILTER_OVRD_EN_SHIFT (0U)
/*! DATARATE_CONFIG_IMAGE_FILTER_OVRD_EN - DATARATE_CONFIG_IMAGE_FILTER_OVRD_EN
 */
#define XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_IMAGE_FILTER_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_IMAGE_FILTER_OVRD_EN_SHIFT)) & XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_IMAGE_FILTER_OVRD_EN_MASK)

#define XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_FIR_FILTER_OVRD_MASK (0x2U)
#define XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_FIR_FILTER_OVRD_SHIFT (1U)
/*! DATARATE_CONFIG_FIR_FILTER_OVRD - DATARATE_CONFIG_FIR_FILTER_OVRD
 */
#define XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_FIR_FILTER_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_FIR_FILTER_OVRD_SHIFT)) & XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_FIR_FILTER_OVRD_MASK)

#define XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_SYNC0_FILTER_OVRD_MASK (0x4U)
#define XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_SYNC0_FILTER_OVRD_SHIFT (2U)
/*! DATARATE_CONFIG_SYNC0_FILTER_OVRD - DATARATE_CONFIG_SYNC0_FILTER_OVRD
 */
#define XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_SYNC0_FILTER_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_SYNC0_FILTER_OVRD_SHIFT)) & XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_SYNC0_FILTER_OVRD_MASK)

#define XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_SYNC1_FILTER_OVRD_MASK (0x8U)
#define XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_SYNC1_FILTER_OVRD_SHIFT (3U)
/*! DATARATE_CONFIG_SYNC1_FILTER_OVRD - DATARATE_CONFIG_SYNC1_FILTER_OVRD
 */
#define XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_SYNC1_FILTER_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_SYNC1_FILTER_OVRD_SHIFT)) & XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_SYNC1_FILTER_OVRD_MASK)

#define XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_GFSK_FILT_CLK_SEL_MASK (0x70000U)
#define XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_GFSK_FILT_CLK_SEL_SHIFT (16U)
/*! DATARATE_CONFIG_GFSK_FILT_CLK_SEL - DATARATE_CONFIG_GFSK_FILT_CLK_SEL
 */
#define XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_GFSK_FILT_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_GFSK_FILT_CLK_SEL_SHIFT)) & XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_GFSK_FILT_CLK_SEL_MASK)

#define XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_SYNC0_CLK_SEL_MASK (0x700000U)
#define XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_SYNC0_CLK_SEL_SHIFT (20U)
/*! DATARATE_CONFIG_SYNC0_CLK_SEL - DATARATE_CONFIG_IMAGE_SYNC0_CLK_SEL
 */
#define XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_SYNC0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_SYNC0_CLK_SEL_SHIFT)) & XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_SYNC0_CLK_SEL_MASK)

#define XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_SYNC1_CLK_SEL_MASK (0x7000000U)
#define XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_SYNC1_CLK_SEL_SHIFT (24U)
/*! DATARATE_CONFIG_SYNC1_CLK_SEL - DATARATE_CONFIG_IMAGE_SYNC1_CLK_SEL
 */
#define XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_SYNC1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_SYNC1_CLK_SEL_SHIFT)) & XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_SYNC1_CLK_SEL_MASK)

#define XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_IMAGE_FIR_CLK_SEL_MASK (0x10000000U)
#define XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_IMAGE_FIR_CLK_SEL_SHIFT (28U)
/*! DATARATE_CONFIG_IMAGE_FIR_CLK_SEL - DATARATE_CONFIG_IMAGE_FIR_CLK_SEL
 */
#define XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_IMAGE_FIR_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_IMAGE_FIR_CLK_SEL_SHIFT)) & XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_IMAGE_FIR_CLK_SEL_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group XCVR_TX_DIG_Register_Masks */


/* XCVR_TX_DIG - Peripheral instance base addresses */
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
  /** Peripheral XCVR_TX_DIG base address */
  #define XCVR_TX_DIG_BASE                         (0x58A07200u)
  /** Peripheral XCVR_TX_DIG base address */
  #define XCVR_TX_DIG_BASE_NS                      (0x48A07200u)
  /** Peripheral XCVR_TX_DIG base pointer */
  #define XCVR_TX_DIG                              ((XCVR_TX_DIG_Type *)XCVR_TX_DIG_BASE)
  /** Peripheral XCVR_TX_DIG base pointer */
  #define XCVR_TX_DIG_NS                           ((XCVR_TX_DIG_Type *)XCVR_TX_DIG_BASE_NS)
  /** Array initializer of XCVR_TX_DIG peripheral base addresses */
  #define XCVR_TX_DIG_BASE_ADDRS                   { XCVR_TX_DIG_BASE }
  /** Array initializer of XCVR_TX_DIG peripheral base pointers */
  #define XCVR_TX_DIG_BASE_PTRS                    { XCVR_TX_DIG }
  /** Array initializer of XCVR_TX_DIG peripheral base addresses */
  #define XCVR_TX_DIG_BASE_ADDRS_NS                { XCVR_TX_DIG_BASE_NS }
  /** Array initializer of XCVR_TX_DIG peripheral base pointers */
  #define XCVR_TX_DIG_BASE_PTRS_NS                 { XCVR_TX_DIG_NS }
#else
  /** Peripheral XCVR_TX_DIG base address */
  #define XCVR_TX_DIG_BASE                         (0x48A07200u)
  /** Peripheral XCVR_TX_DIG base pointer */
  #define XCVR_TX_DIG                              ((XCVR_TX_DIG_Type *)XCVR_TX_DIG_BASE)
  /** Array initializer of XCVR_TX_DIG peripheral base addresses */
  #define XCVR_TX_DIG_BASE_ADDRS                   { XCVR_TX_DIG_BASE }
  /** Array initializer of XCVR_TX_DIG peripheral base pointers */
  #define XCVR_TX_DIG_BASE_PTRS                    { XCVR_TX_DIG }
#endif

/*!
 * @}
 */ /* end of group XCVR_TX_DIG_Peripheral_Access_Layer */


/*
** End of section using anonymous unions
*/

#if defined(__ARMCC_VERSION)
  #if (__ARMCC_VERSION >= 6010050)
    #pragma clang diagnostic pop
  #else
    #pragma pop
  #endif
#elif defined(__GNUC__)
  /* leave anonymous unions enabled */
#elif defined(__IAR_SYSTEMS_ICC__)
  #pragma language=default
#else
  #error Not supported compiler type
#endif

/*!
 * @}
 */ /* end of group Peripheral_access_layer */


/* ----------------------------------------------------------------------------
   -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
 * @{
 */

#if defined(__ARMCC_VERSION)
  #if (__ARMCC_VERSION >= 6010050)
    #pragma clang system_header
  #endif
#elif defined(__IAR_SYSTEMS_ICC__)
  #pragma system_include
#endif

/**
 * @brief Mask and left-shift a bit field value for use in a register bit range.
 * @param field Name of the register bit field.
 * @param value Value of the bit field.
 * @return Masked and shifted value.
 */
#define NXP_VAL2FLD(field, value)    (((value) << (field ## _SHIFT)) & (field ## _MASK))
/**
 * @brief Mask and right-shift a register value to extract a bit field value.
 * @param field Name of the register bit field.
 * @param value Value of the register.
 * @return Masked and shifted bit field value.
 */
#define NXP_FLD2VAL(field, value)    (((value) & (field ## _MASK)) >> (field ## _SHIFT))

/*!
 * @}
 */ /* end of group Bit_Field_Generic_Macros */


/* ----------------------------------------------------------------------------
   -- SDK Compatibility
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
 * @{
 */

#define RADIO_IS_GEN_4P5 (1)
#define NXP_RADIO_GEN (450)

/*! @brief define LTC0 from LTC. */
#define LTC0 LTC

/*! @brief IMU message link between current CPU and remote peer CPU. */
typedef enum
{
    kIMU_LinkCpu1Cpu2 = 0, /*! Message link between CPU1 and CPU2. */
    kIMU_LinkMax           /*! Message link count used for boundary check. */
} imu_link_t;

/*! @brief IMU base register for current CPU. */
#define IMU_CUR_CPU_BASE(link) (&(CIU2->CIU2_IMU_CPU1_WR_MSG_TO_CPU2))
/*! @brief IMU base register for peer CPU. */
#define IMU_PEER_CPU_BASE(link) (&(CIU2->CIU2_IMU_CPU2_WR_MSG_TO_CPU1))

/*! @brief IMU CPU index for current CPU. */
#define IMU_CPU_INDEX (1U)

/*
 * Macros below define the chip revision.
 */
#define DEVICE_REVISION_A0     (0x10U)
#define DEVICE_REVISION_A1     (0x11U)
#define DEVICE_REVISION_OTHERS (0xFFU)

#define IS_CHIP_REVISION_A0() (DEVICE_REVISION_A0 == Chip_GetVersion())
#define IS_CHIP_REVISION_A1() (DEVICE_REVISION_A1 == Chip_GetVersion())

/*!
* @brief Get the chip value.
*
* @return chip version, 0x10: A0 version chip, 0x11: A1 version chip, 0xFF: invalid version.
*/
static inline uint8_t Chip_GetVersion(void)
{
    uint8_t deviceRevision;

    deviceRevision = (uint8_t)(*((uint8_t *)0x1480C000)) & 0xFFu;

    if (DEVICE_REVISION_A0 == deviceRevision) /* A0 device revision is 0x10 */
    {
        return DEVICE_REVISION_A0;
    }
    else if (DEVICE_REVISION_A1 == deviceRevision) /* A1 device revision is 0x11 */
    {
        return DEVICE_REVISION_A1;
    }
    else
    {
        return DEVICE_REVISION_OTHERS;
    }
}

/*!
 * @}
 */ /* end of group SDK_Compatibility_Symbols */


#endif  /* _KW45B41Z83_H_ */

