/***********************************************************************************************************************
 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
 **********************************************************************************************************************/

/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: TEE v3.0
processor: MIMXRT595S
package_id: MIMXRT595SFFOC
mcu_data: ksdk2_0
processor_version: 9.0.0
board: MIMXRT595-EVK
 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */

/***********************************************************************************************************************
 * Included files
 **********************************************************************************************************************/
#include "fsl_common.h"
#include "resource_config.h"

/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
tee:
- ahb:
  - regions: [{memory: BootROM, security: ns_user, start: '0x00000000', size: '0x00020000'}, {memory: FlexSPI0, security: ns_user, start: '0x00000000', size: '0x08000000'},
    {memory: SRAM_ROM, security: ns_user, start: '0x00000000', size: '0x00020000'}, {memory: SRAM_SHARED, security: ns_user, start: '0x00000000', size: '0x00060000'},
    {memory: SRAM, security: ns_user, start: '0x00000000', size: '0x00280000'}, {memory: SRAM_DSP, security: ns_user, start: '0x00000000', size: '0x00200000'}, {
      memory: SmartDMA, security: ns_user, start: '0x00000000', size: '0x00008000'}, {memory: FlexSPI1, security: ns_user, start: '0x00000000', size: '0x08000000'},
    {memory: USB_RAM, security: ns_user, start: '0x00000000', size: '0x00004000'}]
  - masters: {ns_user: {id: [DMA0, DMA1, DSP, GPU, POWERQUAD, SDIO0, SDIO1, SDMA_D, SDMA_I]}}
  - peripherals: {ns_user: {id: [ACMP0, ADC0, AHB_SECURE_CTRL, CACHE64_CTRL0, CACHE64_CTRL1, CASPER, CLKCTL0, CLKCTL1, CRC_ENGINE, CTIMER0, CTIMER1, CTIMER2, CTIMER3,
        CTIMER4, DEBUGGER_MAILBOX, DMA0, DMA1, DMIC0, FLEXCOMM0, FLEXCOMM1, FLEXCOMM10, FLEXCOMM11, FLEXCOMM12, FLEXCOMM13, FLEXCOMM14, FLEXCOMM15, FLEXCOMM16, FLEXCOMM2,
        FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, FLEXCOMM9, FLEXIO0, FLEXSPI0, FLEXSPI1, FREQME, GPIO, GPU, HASHCRYPT, I3C0, I3C1, INPUTMUX,
        IOPCTL, LCDIF, MIPI_DSI_HOST, MRT0, MUA, MUB, OCOTP0, OSTIMER0, OSTIMER1, PINT, PMC, POWERQUAD, PUF, RSTCTL0, RSTCTL1, RTC, SCT0, SECGPIO, SEMA42, SMARTDMA,
        SYSCTL0, SYSCTL1, TRNG, USBHSD, USBHSH, USBPHY, USDHC0, USDHC1, UTICK0, WWDT0, WWDT1]}}
  - interrupts:
    - masking: {Non-masked: {id: [DSP_INTR0_SEC, DSP_INTR10_SEC, DSP_INTR11_SEC, DSP_INTR12_SEC, DSP_INTR13_SEC, DSP_INTR14_SEC, DSP_INTR15_SEC, DSP_INTR16_SEC,
          DSP_INTR17_SEC, DSP_INTR18_SEC, DSP_INTR19_SEC, DSP_INTR1_SEC, DSP_INTR20_SEC, DSP_INTR21_SEC, DSP_INTR22_SEC, DSP_INTR23_SEC, DSP_INTR24_SEC, DSP_INTR25_SEC,
          DSP_INTR26_SEC, DSP_INTR2_SEC, DSP_INTR3_SEC, DSP_INTR4_SEC, DSP_INTR5_SEC, DSP_INTR6_SEC, DSP_INTR7_SEC, DSP_INTR8_SEC, DSP_INTR9_SEC]}}
    - security: {Secure: {id: [ACMP_IRQn, ADC0_IRQn, CASPER_IRQn, CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn, DMA0_IRQn, DMA1_IRQn, DMIC0_IRQn,
          DSP_TIE_EXPSTATE1_IRQn, FLEXCOMM0_IRQn, FLEXCOMM10_IRQn, FLEXCOMM11_IRQn, FLEXCOMM12_IRQn, FLEXCOMM13_IRQn, FLEXCOMM14_IRQn, FLEXCOMM15_IRQn, FLEXCOMM16_IRQn,
          FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn, FLEXIO_IRQn,
          FLEXSPI0_FLEXSPI1_IRQn, GPIO_INTA_IRQn, GPIO_INTB_IRQn, GPU_IRQn, HASHCRYPT_IRQn, HWVAD0_IRQn, HYPERVISOR_IRQn, I3C0_IRQn, I3C1_IRQn, LCDIF_IRQn, MIPI_IRQn,
          MRT0_IRQn, MU_A_IRQn, OS_EVENT_IRQn, PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn, PIN_INT4_IRQn, PIN_INT5_IRQn, PIN_INT6_IRQn, PIN_INT7_IRQn,
          PMU_PMIC_IRQn, POWERQUAD_IRQn, PUF_IRQn, RNG_IRQn, RTC_IRQn, SCT0_IRQn, SDMA_IRQn, SECURE_VIOLATION_IRQn, SGPIO_INTA_IRQn, SGPIO_INTB_IRQn, USB0_IRQn, USB0_NEEDCLK_IRQn,
          USB_PHYDCD_IRQn, USDHC0_IRQn, USDHC1_IRQn, UTICK0_IRQn, WDT0_IRQn, WDT1_IRQn]}}
  - pins_masks:
    - pio0: {Non-masked: {id: ['0', '1', '10', '11', '12', '13', '14', '15', '16', '17', '18', '19', '2', '21', '22', '23', '24', '25', '28', '29', '3', '30', '31',
          '4', '5', '6', '7', '8', '9']}}
    - pio1: {Non-masked: {id: ['0', '10', '11', '12', '13', '14', '15', '18', '19', '20', '21', '22', '23', '24', '25', '26', '27', '28', '29', '3', '30', '31',
          '4', '5', '6', '7']}}
    - pio2: {Non-masked: {id: ['0', '1', '10', '11', '14', '15', '2', '24', '25', '26', '27', '28', '29', '3', '30', '31', '4', '5', '6', '7', '8', '9']}}
- sau:
  - enabled: 'false'
  - all_non_secure: 'false'
  - generate_code_for_disabled_regions: 'false'
  - regions: [{index: '0', enabled: 'false', security: ns, start: '0x00000000', size: '0x00000020'}, {index: '1', enabled: 'false', security: ns, start: '0x00000000',
      size: '0x00000020'}, {index: '2', enabled: 'false', security: ns, start: '0x00000000', size: '0x00000020'}, {index: '3', enabled: 'false', security: ns, start: '0x00000000',
      size: '0x00000020'}, {index: '4', enabled: 'false', security: ns, start: '0x00000000', size: '0x00000020'}, {index: '5', enabled: 'false', security: ns, start: '0x00000000',
      size: '0x00000020'}, {index: '6', enabled: 'false', security: ns, start: '0x00000000', size: '0x00000020'}, {index: '7', enabled: 'false', security: ns, start: '0x00000000',
      size: '0x00000020'}]
- global_options:
  - no:
    - id: [AIRCR_PRIS, AIRCR_BFHFNMINS, AIRCR_SYSRESETREQS, SCR_SLEEPDEEPS, SHCSR_SECUREFAULTENA, NSACR_CP0, NSACR_CP1, NSACR_CP2, NSACR_CP3, NSACR_CP4, NSACR_CP5,
      NSACR_CP6, NSACR_CP7, NSACR_CP10, NSACR_CP11, CPPWR_SU0, CPPWR_SUS0, CPPWR_SU1, CPPWR_SUS1, CPPWR_SU2, CPPWR_SUS2, CPPWR_SU3, CPPWR_SUS3, CPPWR_SU4, CPPWR_SUS4,
      CPPWR_SU5, CPPWR_SUS5, CPPWR_SU6, CPPWR_SUS6, CPPWR_SU7, CPPWR_SUS7, CPPWR_SU10, CPPWR_SUS10, CPPWR_SU11, CPPWR_SUS11, SEC_GPIO_MASK0_LOCK, SEC_GPIO_MASK1_LOCK,
      SEC_GPIO_MASK2_LOCK, SEC_DSP_INT_MASK_LOCK, MASTER_SEC_LEVEL_LOCK, CPU0_LOCK_NS_VTOR, CPU0_LOCK_NS_MPU, CPU0_LOCK_S_VTOR, CPU0_LOCK_S_MPU, CPU0_LOCK_SAU, CPU0_LOCK_REG_LOCK,
      AHB_MISC_CTRL_REG_ENABLE_SECURE_CHECKING, AHB_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK, AHB_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK, AHB_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT,
      AHB_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE, AHB_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE, AHB_MISC_CTRL_REG_IDAU_ALL_NS, AHB_MISC_CTRL_REG_WRITE_LOCK,
      _legacy_source_names_]
  - c_code:
    - id: [_output_type_]
- user_memory_regions: []
- mpus:
  - mpu:
    - enabled: 'false'
    - id: 's'
    - priv_default_map: 'false'
    - handler_enabled: 'false'
    - generate_code_for_disabled_regions: 'false'
    - attributes: [{index: '0', id: '0', memory_type: device, device: nGnRE}, {index: '1', id: '1', memory_type: device, device: nGnRE}, {index: '2', id: '2', memory_type: device,
        device: nGnRE}, {index: '3', id: '3', memory_type: device, device: nGnRE}, {index: '4', id: '4', memory_type: device, device: nGnRE}, {index: '5', id: '5',
        memory_type: device, device: nGnRE}, {index: '6', id: '6', memory_type: device, device: nGnRE}, {index: '7', id: '7', memory_type: device, device: nGnRE}]
    - regions: [{executable: 'false', read_only: 'false', attributes_index: '0', index: '0', enabled: 'false', security: priv, start: '0x00000000', size: '0x00000020'},
      {executable: 'false', read_only: 'false', attributes_index: '0', index: '1', enabled: 'false', security: priv, start: '0x00000000', size: '0x00000020'}, {executable: 'false',
        read_only: 'false', attributes_index: '0', index: '2', enabled: 'false', security: priv, start: '0x00000000', size: '0x00000020'}, {executable: 'false', read_only: 'false',
        attributes_index: '0', index: '3', enabled: 'false', security: priv, start: '0x00000000', size: '0x00000020'}, {executable: 'false', read_only: 'false', attributes_index: '0',
        index: '4', enabled: 'false', security: priv, start: '0x00000000', size: '0x00000020'}, {executable: 'false', read_only: 'false', attributes_index: '0', index: '5',
        enabled: 'false', security: priv, start: '0x00000000', size: '0x00000020'}, {executable: 'false', read_only: 'false', attributes_index: '0', index: '6', enabled: 'false',
        security: priv, start: '0x00000000', size: '0x00000020'}, {executable: 'false', read_only: 'false', attributes_index: '0', index: '7', enabled: 'false', security: priv,
        start: '0x00000000', size: '0x00000020'}]
  - mpu:
    - enabled: 'false'
    - id: 'ns'
    - priv_default_map: 'false'
    - handler_enabled: 'false'
    - generate_code_for_disabled_regions: 'false'
    - attributes: [{index: '0', id: '0', memory_type: device, device: nGnRE}, {index: '1', id: '1', memory_type: device, device: nGnRE}, {index: '2', id: '2', memory_type: device,
        device: nGnRE}, {index: '3', id: '3', memory_type: device, device: nGnRE}, {index: '4', id: '4', memory_type: device, device: nGnRE}, {index: '5', id: '5',
        memory_type: device, device: nGnRE}, {index: '6', id: '6', memory_type: device, device: nGnRE}, {index: '7', id: '7', memory_type: device, device: nGnRE}]
    - regions: [{executable: 'false', read_only: 'false', attributes_index: '0', index: '0', enabled: 'false', security: priv, start: '0x00000000', size: '0x00000020'},
      {executable: 'false', read_only: 'false', attributes_index: '0', index: '1', enabled: 'false', security: priv, start: '0x00000000', size: '0x00000020'}, {executable: 'false',
        read_only: 'false', attributes_index: '0', index: '2', enabled: 'false', security: priv, start: '0x00000000', size: '0x00000020'}, {executable: 'false', read_only: 'false',
        attributes_index: '0', index: '3', enabled: 'false', security: priv, start: '0x00000000', size: '0x00000020'}, {executable: 'false', read_only: 'false', attributes_index: '0',
        index: '4', enabled: 'false', security: priv, start: '0x00000000', size: '0x00000020'}, {executable: 'false', read_only: 'false', attributes_index: '0', index: '5',
        enabled: 'false', security: priv, start: '0x00000000', size: '0x00000020'}, {executable: 'false', read_only: 'false', attributes_index: '0', index: '6', enabled: 'false',
        security: priv, start: '0x00000000', size: '0x00000020'}, {executable: 'false', read_only: 'false', attributes_index: '0', index: '7', enabled: 'false', security: priv,
        start: '0x00000000', size: '0x00000020'}]
 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */

/***********************************************************************************************************************
 * BOARD_InitTrustZone function
 **********************************************************************************************************************/
void BOARD_InitTrustZone()
{
    /* SAU configuration */
    
    /* Set SAU Control register: Disable SAU and All Secure */
    SAU->CTRL = 0;
    
    /* Force memory writes before continuing */
    __DSB();
    /* Flush and refill pipeline with updated permissions */
    __ISB();
    
    /* Set SAU Control register: Disable SAU and All Secure */
    SAU->CTRL = ((0U << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk)
        | ((0U << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk);
    
}

/***********************************************************************************************************************
 * BOARD_InitAHBSE function
 **********************************************************************************************************************/
void BOARD_InitAHBSE()
{
    /* AHB configuration */

    /*--------------------------------------------------------------------
     - AHB Security Level Configurations
     -------------------------------------------------------------------*/
    /* Configuration of AHB Secure Controller
       Possible values for every memory sector or peripheral rule:
        0    Non-secure, User access allowed.
        1    Non-secure, Privileged access allowed.
        2    Secure, User access allowed.
        3    Secure, Privileged access allowed.
    */

    /* Security level configuration of all checkers */
    AHB_SECURE_CTRL->ROM_MEM_RULE[0] = 0;
    AHB_SECURE_CTRL->ROM_MEM_RULE[1] = 0;
    AHB_SECURE_CTRL->ROM_MEM_RULE[2] = 0;
    AHB_SECURE_CTRL->ROM_MEM_RULE[3] = 0;
    AHB_SECURE_CTRL->FLEXSPI0_REGION0_RULE[0] = 0;
    AHB_SECURE_CTRL->FLEXSPI0_REGION0_RULE[1] = 0;
    AHB_SECURE_CTRL->FLEXSPI0_REGION0_RULE[2] = 0;
    AHB_SECURE_CTRL->FLEXSPI0_REGION0_RULE[3] = 0;
    AHB_SECURE_CTRL->FLEXSPI0_REGION1_4_RULE[0].FLEXSPI0_REGION_RULE0 = 0;
    AHB_SECURE_CTRL->FLEXSPI0_REGION1_4_RULE[1].FLEXSPI0_REGION_RULE0 = 0;
    AHB_SECURE_CTRL->FLEXSPI0_REGION1_4_RULE[2].FLEXSPI0_REGION_RULE0 = 0;
    AHB_SECURE_CTRL->FLEXSPI0_REGION1_4_RULE[3].FLEXSPI0_REGION_RULE0 = 0;
    AHB_SECURE_CTRL->RAM00_RULE[0] = 0;
    AHB_SECURE_CTRL->RAM00_RULE[1] = 0;
    AHB_SECURE_CTRL->RAM00_RULE[2] = 0;
    AHB_SECURE_CTRL->RAM00_RULE[3] = 0;
    AHB_SECURE_CTRL->RAM01_RULE[0] = 0;
    AHB_SECURE_CTRL->RAM01_RULE[1] = 0;
    AHB_SECURE_CTRL->RAM01_RULE[2] = 0;
    AHB_SECURE_CTRL->RAM01_RULE[3] = 0;
    AHB_SECURE_CTRL->RAM02_RULE[0] = 0;
    AHB_SECURE_CTRL->RAM02_RULE[1] = 0;
    AHB_SECURE_CTRL->RAM02_RULE[2] = 0;
    AHB_SECURE_CTRL->RAM02_RULE[3] = 0;
    AHB_SECURE_CTRL->RAM03_RULE[0] = 0;
    AHB_SECURE_CTRL->RAM03_RULE[1] = 0;
    AHB_SECURE_CTRL->RAM03_RULE[2] = 0;
    AHB_SECURE_CTRL->RAM03_RULE[3] = 0;
    AHB_SECURE_CTRL->RAM04_RULE[0] = 0;
    AHB_SECURE_CTRL->RAM04_RULE[1] = 0;
    AHB_SECURE_CTRL->RAM04_RULE[2] = 0;
    AHB_SECURE_CTRL->RAM04_RULE[3] = 0;
    AHB_SECURE_CTRL->RAM05_RULE[0] = 0;
    AHB_SECURE_CTRL->RAM05_RULE[1] = 0;
    AHB_SECURE_CTRL->RAM05_RULE[2] = 0;
    AHB_SECURE_CTRL->RAM05_RULE[3] = 0;
    AHB_SECURE_CTRL->RAM06_RULE[0] = 0;
    AHB_SECURE_CTRL->RAM06_RULE[1] = 0;
    AHB_SECURE_CTRL->RAM06_RULE[2] = 0;
    AHB_SECURE_CTRL->RAM06_RULE[3] = 0;
    AHB_SECURE_CTRL->RAM07_RULE[0] = 0;
    AHB_SECURE_CTRL->RAM07_RULE[1] = 0;
    AHB_SECURE_CTRL->RAM07_RULE[2] = 0;
    AHB_SECURE_CTRL->RAM07_RULE[3] = 0;
    AHB_SECURE_CTRL->RAM08_RULE[0] = 0;
    AHB_SECURE_CTRL->RAM08_RULE[1] = 0;
    AHB_SECURE_CTRL->RAM08_RULE[2] = 0;
    AHB_SECURE_CTRL->RAM08_RULE[3] = 0;
    AHB_SECURE_CTRL->RAM09_RULE[0] = 0;
    AHB_SECURE_CTRL->RAM09_RULE[1] = 0;
    AHB_SECURE_CTRL->RAM09_RULE[2] = 0;
    AHB_SECURE_CTRL->RAM09_RULE[3] = 0;
    AHB_SECURE_CTRL->RAM10_RULE[0] = 0;
    AHB_SECURE_CTRL->RAM10_RULE[1] = 0;
    AHB_SECURE_CTRL->RAM10_RULE[2] = 0;
    AHB_SECURE_CTRL->RAM10_RULE[3] = 0;
    AHB_SECURE_CTRL->RAM11_RULE[0] = 0;
    AHB_SECURE_CTRL->RAM11_RULE[1] = 0;
    AHB_SECURE_CTRL->RAM11_RULE[2] = 0;
    AHB_SECURE_CTRL->RAM11_RULE[3] = 0;
    AHB_SECURE_CTRL->RAM12_RULE[0] = 0;
    AHB_SECURE_CTRL->RAM12_RULE[1] = 0;
    AHB_SECURE_CTRL->RAM12_RULE[2] = 0;
    AHB_SECURE_CTRL->RAM12_RULE[3] = 0;
    AHB_SECURE_CTRL->RAM13_RULE[0] = 0;
    AHB_SECURE_CTRL->RAM13_RULE[1] = 0;
    AHB_SECURE_CTRL->RAM13_RULE[2] = 0;
    AHB_SECURE_CTRL->RAM13_RULE[3] = 0;
    AHB_SECURE_CTRL->RAM14_RULE[0] = 0;
    AHB_SECURE_CTRL->RAM14_RULE[1] = 0;
    AHB_SECURE_CTRL->RAM14_RULE[2] = 0;
    AHB_SECURE_CTRL->RAM14_RULE[3] = 0;
    AHB_SECURE_CTRL->RAM15_RULE[0] = 0;
    AHB_SECURE_CTRL->RAM15_RULE[1] = 0;
    AHB_SECURE_CTRL->RAM15_RULE[2] = 0;
    AHB_SECURE_CTRL->RAM15_RULE[3] = 0;
    AHB_SECURE_CTRL->RAM16_RULE[0] = 0;
    AHB_SECURE_CTRL->RAM16_RULE[1] = 0;
    AHB_SECURE_CTRL->RAM16_RULE[2] = 0;
    AHB_SECURE_CTRL->RAM16_RULE[3] = 0;
    AHB_SECURE_CTRL->RAM17_RULE[0] = 0;
    AHB_SECURE_CTRL->RAM17_RULE[1] = 0;
    AHB_SECURE_CTRL->RAM17_RULE[2] = 0;
    AHB_SECURE_CTRL->RAM17_RULE[3] = 0;
    AHB_SECURE_CTRL->RAM18_RULE[0] = 0;
    AHB_SECURE_CTRL->RAM18_RULE[1] = 0;
    AHB_SECURE_CTRL->RAM18_RULE[2] = 0;
    AHB_SECURE_CTRL->RAM18_RULE[3] = 0;
    AHB_SECURE_CTRL->RAM19_RULE[0] = 0;
    AHB_SECURE_CTRL->RAM19_RULE[1] = 0;
    AHB_SECURE_CTRL->RAM19_RULE[2] = 0;
    AHB_SECURE_CTRL->RAM19_RULE[3] = 0;
    AHB_SECURE_CTRL->RAM20_RULE[0] = 0;
    AHB_SECURE_CTRL->RAM20_RULE[1] = 0;
    AHB_SECURE_CTRL->RAM20_RULE[2] = 0;
    AHB_SECURE_CTRL->RAM20_RULE[3] = 0;
    AHB_SECURE_CTRL->RAM21_RULE[0] = 0;
    AHB_SECURE_CTRL->RAM21_RULE[1] = 0;
    AHB_SECURE_CTRL->RAM21_RULE[2] = 0;
    AHB_SECURE_CTRL->RAM21_RULE[3] = 0;
    AHB_SECURE_CTRL->RAM22_RULE[0] = 0;
    AHB_SECURE_CTRL->RAM22_RULE[1] = 0;
    AHB_SECURE_CTRL->RAM22_RULE[2] = 0;
    AHB_SECURE_CTRL->RAM22_RULE[3] = 0;
    AHB_SECURE_CTRL->RAM23_RULE[0] = 0;
    AHB_SECURE_CTRL->RAM23_RULE[1] = 0;
    AHB_SECURE_CTRL->RAM23_RULE[2] = 0;
    AHB_SECURE_CTRL->RAM23_RULE[3] = 0;
    AHB_SECURE_CTRL->RAM24_RULE[0] = 0;
    AHB_SECURE_CTRL->RAM24_RULE[1] = 0;
    AHB_SECURE_CTRL->RAM24_RULE[2] = 0;
    AHB_SECURE_CTRL->RAM24_RULE[3] = 0;
    AHB_SECURE_CTRL->RAM25_RULE[0] = 0;
    AHB_SECURE_CTRL->RAM25_RULE[1] = 0;
    AHB_SECURE_CTRL->RAM25_RULE[2] = 0;
    AHB_SECURE_CTRL->RAM25_RULE[3] = 0;
    AHB_SECURE_CTRL->RAM26_RULE[0] = 0;
    AHB_SECURE_CTRL->RAM26_RULE[1] = 0;
    AHB_SECURE_CTRL->RAM26_RULE[2] = 0;
    AHB_SECURE_CTRL->RAM26_RULE[3] = 0;
    AHB_SECURE_CTRL->RAM27_RULE[0] = 0;
    AHB_SECURE_CTRL->RAM27_RULE[1] = 0;
    AHB_SECURE_CTRL->RAM27_RULE[2] = 0;
    AHB_SECURE_CTRL->RAM27_RULE[3] = 0;
    AHB_SECURE_CTRL->RAM28_RULE[0] = 0;
    AHB_SECURE_CTRL->RAM28_RULE[1] = 0;
    AHB_SECURE_CTRL->RAM28_RULE[2] = 0;
    AHB_SECURE_CTRL->RAM28_RULE[3] = 0;
    AHB_SECURE_CTRL->RAM29_RULE[0] = 0;
    AHB_SECURE_CTRL->RAM29_RULE[1] = 0;
    AHB_SECURE_CTRL->RAM29_RULE[2] = 0;
    AHB_SECURE_CTRL->RAM29_RULE[3] = 0;
    AHB_SECURE_CTRL->RAM30_RULE[0] = 0;
    AHB_SECURE_CTRL->RAM30_RULE[1] = 0;
    AHB_SECURE_CTRL->RAM30_RULE[2] = 0;
    AHB_SECURE_CTRL->RAM30_RULE[3] = 0;
    AHB_SECURE_CTRL->RAM31_RULE[0] = 0;
    AHB_SECURE_CTRL->RAM31_RULE[1] = 0;
    AHB_SECURE_CTRL->RAM31_RULE[2] = 0;
    AHB_SECURE_CTRL->RAM31_RULE[3] = 0;
    AHB_SECURE_CTRL->SDMA_RAM_RULE[0] = 0;
    AHB_SECURE_CTRL->SDMA_RAM_RULE[1] = 0;
    AHB_SECURE_CTRL->SDMA_RAM_RULE[2] = 0;
    AHB_SECURE_CTRL->SDMA_RAM_RULE[3] = 0;
    AHB_SECURE_CTRL->FLEXSPI1_REGION0_RULE[0] = 0;
    AHB_SECURE_CTRL->FLEXSPI1_REGION0_RULE[1] = 0;
    AHB_SECURE_CTRL->FLEXSPI1_REGION0_RULE[2] = 0;
    AHB_SECURE_CTRL->FLEXSPI1_REGION0_RULE[3] = 0;
    AHB_SECURE_CTRL->FLEXSPI1_REGIONN_RULE0[0].FLEXSPI1_REGION_RULE0 = 0;
    AHB_SECURE_CTRL->FLEXSPI1_REGIONN_RULE0[1].FLEXSPI1_REGION_RULE0 = 0;
    AHB_SECURE_CTRL->FLEXSPI1_REGIONN_RULE0[2].FLEXSPI1_REGION_RULE0 = 0;
    AHB_SECURE_CTRL->FLEXSPI1_REGIONN_RULE0[3].FLEXSPI1_REGION_RULE0 = 0;
    AHB_SECURE_CTRL->AHB_PERIPH2_SLAVE_RULE0 = 0;
    AHB_SECURE_CTRL->APB_BRIDGE_PER0_RULE0 = 0;
    AHB_SECURE_CTRL->APB_BRIDGE_PER0_RULE1 = 0;
    AHB_SECURE_CTRL->APB_BRIDGE_PER1_RULE0 = 0;
    AHB_SECURE_CTRL->APB_BRIDGE_PER1_RULE1 = 0;
    AHB_SECURE_CTRL->APB_BRIDGE_PER1_RULE2 = 0;
    AHB_SECURE_CTRL->AHB_PERIPH0_SLAVE_RULE0 = 0;
    AHB_SECURE_CTRL->AIPS_BRIDGE0_PER_RULE0 = 0;
    AHB_SECURE_CTRL->AHB_PERIPH1_SLAVE_RULE0 = 0;
    AHB_SECURE_CTRL->AHB_PERIPH1_SLAVE_RULE1 = 0;
    AHB_SECURE_CTRL->AIPS_BRIDGE1_PER_RULE0 = 0;
    AHB_SECURE_CTRL->AIPS_BRIDGE1_PER_RULE1 = 0;
    AHB_SECURE_CTRL->AHB_SECURE_CTRL_PERIPH_RULE0 = 0;
    AHB_SECURE_CTRL->AHB_PERIPH3_SLAVE_RULE0 = 0;
    AHB_SECURE_CTRL->AHB_PERIPH3_SLAVE_RULE1 = 0;

    /* Security level configuration of masters */
    AHB_SECURE_CTRL->MASTER_SEC_LEVEL = 0x80000000U;
    AHB_SECURE_CTRL->MASTER_SEC_ANTI_POL_REG = 0xBFFFFFFFU;

    /*--------------------------------------------------------------------
     - Pins: Reading GPIO state
     -------------------------------------------------------------------*/
    /* Possible values for every pin:
     *  0b0    Deny
     *  0b1    Allow */
    AHB_SECURE_CTRL->SEC_GPIO_MASK0 = 0xFFFFFFFFU;
    AHB_SECURE_CTRL->SEC_GPIO_MASK1 = 0xFFFFFFFFU;
    AHB_SECURE_CTRL->SEC_GPIO_MASK2 = 0xFFFFFFFFU;

    /*--------------------------------------------------------------------
     - Interrupts: Interrupt handling by Core1
     -------------------------------------------------------------------*/
    /* Possible values for every interrupt:
     *  0b0    Deny
     *  0b1    Allow */
    AHB_SECURE_CTRL->DSP_INT_MASK0 = 0xFFFFFFFFU;

    /*--------------------------------------------------------------------
     - Interrupts: Interrupt security configuration
     -------------------------------------------------------------------*/
    /* Possible values for every interrupt:
     *  0b0    Secure
     *  0b1    Non-secure */
    NVIC->ITNS[0] = 0;
    NVIC->ITNS[1] = 0;
    NVIC->ITNS[2] = 0;

    /* Global Options */
    SCB->AIRCR = (SCB->AIRCR & 0x000009FF7U) | 0x005FA0000U;
    SCB->SCR &= 0x0FFFFFFF7U;
    SCB->SHCSR &= 0x0FFF7FFFFU;
    SCB->NSACR = 0;
    SCnSCB->CPPWR = 0;
    AHB_SECURE_CTRL->SEC_MASK_LOCK = (AHB_SECURE_CTRL->SEC_MASK_LOCK & 0x0FFFCFFC0U) | 0x00002002AU;
    AHB_SECURE_CTRL->MASTER_SEC_LEVEL = (AHB_SECURE_CTRL->MASTER_SEC_LEVEL & 0x03FFFFFFFU) | 0x080000000U;
    AHB_SECURE_CTRL->MASTER_SEC_ANTI_POL_REG = (AHB_SECURE_CTRL->MASTER_SEC_ANTI_POL_REG & 0x03FFFFFFFU) | 0x080000000U;
    AHB_SECURE_CTRL->CM33_LOCK_REG = 0x800002AAU;
    AHB_SECURE_CTRL->MISC_CTRL_REG = 0x0000AAAAU;
    AHB_SECURE_CTRL->MISC_CTRL_DP_REG = 0x0000AAAAU;
}

/***********************************************************************************************************************
 * BOARD_InitTEE function
 **********************************************************************************************************************/
void BOARD_InitTEE()
{
    BOARD_InitTrustZone();
    BOARD_InitAHBSE();
}

